]>
git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshr_u32.c
1 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
3 #include "test_sve_acle.h"
7 ** urshr z0\.s, p0/m, z0\.s, #1
10 TEST_UNIFORM_Z (rshr_1_u32_m_tied1
, svuint32_t
,
11 z0
= svrshr_n_u32_m (p0
, z0
, 1),
12 z0
= svrshr_m (p0
, z0
, 1))
15 ** rshr_1_u32_m_untied:
17 ** urshr z0\.s, p0/m, z0\.s, #1
20 TEST_UNIFORM_Z (rshr_1_u32_m_untied
, svuint32_t
,
21 z0
= svrshr_n_u32_m (p0
, z1
, 1),
22 z0
= svrshr_m (p0
, z1
, 1))
25 ** rshr_2_u32_m_tied1:
26 ** urshr z0\.s, p0/m, z0\.s, #2
29 TEST_UNIFORM_Z (rshr_2_u32_m_tied1
, svuint32_t
,
30 z0
= svrshr_n_u32_m (p0
, z0
, 2),
31 z0
= svrshr_m (p0
, z0
, 2))
34 ** rshr_2_u32_m_untied:
36 ** urshr z0\.s, p0/m, z0\.s, #2
39 TEST_UNIFORM_Z (rshr_2_u32_m_untied
, svuint32_t
,
40 z0
= svrshr_n_u32_m (p0
, z1
, 2),
41 z0
= svrshr_m (p0
, z1
, 2))
44 ** rshr_32_u32_m_tied1:
45 ** urshr z0\.s, p0/m, z0\.s, #32
48 TEST_UNIFORM_Z (rshr_32_u32_m_tied1
, svuint32_t
,
49 z0
= svrshr_n_u32_m (p0
, z0
, 32),
50 z0
= svrshr_m (p0
, z0
, 32))
53 ** rshr_32_u32_m_untied:
55 ** urshr z0\.s, p0/m, z0\.s, #32
58 TEST_UNIFORM_Z (rshr_32_u32_m_untied
, svuint32_t
,
59 z0
= svrshr_n_u32_m (p0
, z1
, 32),
60 z0
= svrshr_m (p0
, z1
, 32))
63 ** rshr_1_u32_z_tied1:
64 ** movprfx z0\.s, p0/z, z0\.s
65 ** urshr z0\.s, p0/m, z0\.s, #1
68 TEST_UNIFORM_Z (rshr_1_u32_z_tied1
, svuint32_t
,
69 z0
= svrshr_n_u32_z (p0
, z0
, 1),
70 z0
= svrshr_z (p0
, z0
, 1))
73 ** rshr_1_u32_z_untied:
74 ** movprfx z0\.s, p0/z, z1\.s
75 ** urshr z0\.s, p0/m, z0\.s, #1
78 TEST_UNIFORM_Z (rshr_1_u32_z_untied
, svuint32_t
,
79 z0
= svrshr_n_u32_z (p0
, z1
, 1),
80 z0
= svrshr_z (p0
, z1
, 1))
83 ** rshr_2_u32_z_tied1:
84 ** movprfx z0\.s, p0/z, z0\.s
85 ** urshr z0\.s, p0/m, z0\.s, #2
88 TEST_UNIFORM_Z (rshr_2_u32_z_tied1
, svuint32_t
,
89 z0
= svrshr_n_u32_z (p0
, z0
, 2),
90 z0
= svrshr_z (p0
, z0
, 2))
93 ** rshr_2_u32_z_untied:
94 ** movprfx z0\.s, p0/z, z1\.s
95 ** urshr z0\.s, p0/m, z0\.s, #2
98 TEST_UNIFORM_Z (rshr_2_u32_z_untied
, svuint32_t
,
99 z0
= svrshr_n_u32_z (p0
, z1
, 2),
100 z0
= svrshr_z (p0
, z1
, 2))
103 ** rshr_32_u32_z_tied1:
104 ** movprfx z0\.s, p0/z, z0\.s
105 ** urshr z0\.s, p0/m, z0\.s, #32
108 TEST_UNIFORM_Z (rshr_32_u32_z_tied1
, svuint32_t
,
109 z0
= svrshr_n_u32_z (p0
, z0
, 32),
110 z0
= svrshr_z (p0
, z0
, 32))
113 ** rshr_32_u32_z_untied:
114 ** movprfx z0\.s, p0/z, z1\.s
115 ** urshr z0\.s, p0/m, z0\.s, #32
118 TEST_UNIFORM_Z (rshr_32_u32_z_untied
, svuint32_t
,
119 z0
= svrshr_n_u32_z (p0
, z1
, 32),
120 z0
= svrshr_z (p0
, z1
, 32))
123 ** rshr_1_u32_x_tied1:
124 ** urshr z0\.s, p0/m, z0\.s, #1
127 TEST_UNIFORM_Z (rshr_1_u32_x_tied1
, svuint32_t
,
128 z0
= svrshr_n_u32_x (p0
, z0
, 1),
129 z0
= svrshr_x (p0
, z0
, 1))
132 ** rshr_1_u32_x_untied:
134 ** urshr z0\.s, p0/m, z0\.s, #1
137 TEST_UNIFORM_Z (rshr_1_u32_x_untied
, svuint32_t
,
138 z0
= svrshr_n_u32_x (p0
, z1
, 1),
139 z0
= svrshr_x (p0
, z1
, 1))
142 ** rshr_2_u32_x_tied1:
143 ** urshr z0\.s, p0/m, z0\.s, #2
146 TEST_UNIFORM_Z (rshr_2_u32_x_tied1
, svuint32_t
,
147 z0
= svrshr_n_u32_x (p0
, z0
, 2),
148 z0
= svrshr_x (p0
, z0
, 2))
151 ** rshr_2_u32_x_untied:
153 ** urshr z0\.s, p0/m, z0\.s, #2
156 TEST_UNIFORM_Z (rshr_2_u32_x_untied
, svuint32_t
,
157 z0
= svrshr_n_u32_x (p0
, z1
, 2),
158 z0
= svrshr_x (p0
, z1
, 2))
161 ** rshr_32_u32_x_tied1:
162 ** urshr z0\.s, p0/m, z0\.s, #32
165 TEST_UNIFORM_Z (rshr_32_u32_x_tied1
, svuint32_t
,
166 z0
= svrshr_n_u32_x (p0
, z0
, 32),
167 z0
= svrshr_x (p0
, z0
, 32))
170 ** rshr_32_u32_x_untied:
172 ** urshr z0\.s, p0/m, z0\.s, #32
175 TEST_UNIFORM_Z (rshr_32_u32_x_untied
, svuint32_t
,
176 z0
= svrshr_n_u32_x (p0
, z1
, 32),
177 z0
= svrshr_x (p0
, z1
, 32))