gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-mmicromips" } */
   3
   4 /* This test ensures that we do not generate microMIPS SWP or LWP
   5    instructions when any component of the accessed memory is volatile;
   6    they are unsafe for such since they might cause replay of partial
   7    accesses if interrupted by an exception.  */
   8
   9 static void set_csr (volatile void *p, int v)
  10 {
  11   *(volatile int *) (p) = v;
  12 }
  13
  14 static int get_csr (volatile void *p)
  15 {
  16   return *(volatile int *) (p);
  17 }
  18
  19 int main ()
  20 {
  21   int i, q = 0, p = 0, r = 0;
  22
  23   for (i = 0; i < 20; i++)
  24     {
  25       set_csr ((volatile void *) 0xbf0100a8, 0xffff0002);
  26       set_csr ((volatile void *) 0xbf0100a4, 0x80000008);
  27     }
  28
  29   for (i = 0; i < 20; i++)
  30     {
  31       register int k, j;
  32       k = get_csr ((volatile void *) 0xbf0100b8);
  33       p += k;
  34       j = get_csr ((volatile void *) 0xbf0100b4);
  35       r += j;
  36       q = j + k;
  37     }
  38   return q + r + p;
  39 }
  40
  41 /* { dg-final { scan-assembler-not "\tswp" } } */
  42 /* { dg-final { scan-assembler-not "\tlwp" } } */