gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c

   1 /* Verify that overloaded built-ins for vec_insert() with short
   2    inputs produce the right codegen.  Power9 variant.  */
   3
   4 /* { dg-do compile { target { powerpc*-*-linux* } } } */
   5 /* { dg-require-effective-target powerpc_p9vector_ok } */
   6 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
   7 /* { dg-options "-O2 -mcpu=power9" } */
   8
   9 #include <altivec.h>
  10
  11 vector bool short
  12 testbs_var(unsigned short x, vector bool short v, signed int i)
  13 {
  14    return vec_insert(x, v, i);
  15 }
  16 vector signed short
  17 testss_var(signed short x, vector signed short v, signed int i)
  18 {
  19    return vec_insert(x, v, i);
  20 }
  21 vector unsigned short
  22 testus1_var(signed short x, vector unsigned short v, signed int i)
  23 {
  24    return vec_insert(x, v, i);
  25 }
  26 vector unsigned short
  27 testus2_var(unsigned short x, vector unsigned short v, signed int i)
  28 {
  29    return vec_insert(x, v, i);
  30 }
  31 vector bool short
  32 testbs_cst(signed short x, vector bool short v)
  33 {
  34    return vec_insert(x, v, 12);
  35 }
  36 vector signed short
  37 testss_cst(signed short x, vector signed short v)
  38 {
  39    return vec_insert(x, v, 12);
  40 }
  41 vector unsigned short
  42 testus1_cst(signed short x, vector unsigned short v)
  43 {
  44    return vec_insert(x, v, 12);
  45 }
  46 vector unsigned short
  47 testus2_cst(unsigned short x, vector unsigned short v)
  48 {
  49    return vec_insert(x, v, 12);
  50 }
  51
  52 /* { dg-final { scan-assembler-times {\mmtvsrwz\M} 4 { target lp64 } } } */
  53 /* { dg-final { scan-assembler-times {\mvinserth\M} 4 { target lp64 } } } */
  54
  55 /* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 } } */
  56 /* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 4 { target lp64 }} } */
  57
  58 /* -m32 uses sth/lvehx as part of the sequence. */
  59 /* { dg-final { scan-assembler-times {\msth\M} 8 { target ilp32 }} } */
  60 /* { dg-final { scan-assembler-times {\mlvehx\M} 4 { target ilp32 }} } */
  61 /* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 8 { target ilp32 }} } */
  62