]>
git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/testsuite/gcc.target/powerpc/pr65849-2.c
1 /* { dg-do compile { target { powerpc*-*-* } } } */
2 /* { dg-require-effective-target powerpc_p8vector_ok } */
3 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
4 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
5 /* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
7 /* Test whether we can enable the -mupper-regs-sf with target pragmas. Make
8 sure float values are allocated to the Altivec registers as well as the
9 traditional FPR registers. */
16 #define MASK_TYPE unsigned long long
19 #define MASK_ONE ((MASK_TYPE)1)
20 #define ZERO ((TYPE) 0.0)
22 #pragma GCC target ("upper-regs-sf")
24 test_add (const MASK_TYPE
*add_mask
, const TYPE
*add_values
,
25 const MASK_TYPE
*sub_mask
, const TYPE
*sub_values
,
26 const MASK_TYPE
*mul_mask
, const TYPE
*mul_values
,
27 const MASK_TYPE
*div_mask
, const TYPE
*div_values
,
28 const MASK_TYPE
*eq0_mask
, int *eq0_ptr
)
74 while ((mask
= *add_mask
++) != 0)
76 value
= *add_values
++;
78 __asm__ (" #reg %0" : "+d" (value
));
80 if ((mask
& (MASK_ONE
<< 0)) != 0)
83 if ((mask
& (MASK_ONE
<< 1)) != 0)
86 if ((mask
& (MASK_ONE
<< 2)) != 0)
89 if ((mask
& (MASK_ONE
<< 3)) != 0)
92 if ((mask
& (MASK_ONE
<< 4)) != 0)
95 if ((mask
& (MASK_ONE
<< 5)) != 0)
98 if ((mask
& (MASK_ONE
<< 6)) != 0)
101 if ((mask
& (MASK_ONE
<< 7)) != 0)
104 if ((mask
& (MASK_ONE
<< 8)) != 0)
107 if ((mask
& (MASK_ONE
<< 9)) != 0)
110 if ((mask
& (MASK_ONE
<< 10)) != 0)
113 if ((mask
& (MASK_ONE
<< 11)) != 0)
116 if ((mask
& (MASK_ONE
<< 12)) != 0)
119 if ((mask
& (MASK_ONE
<< 13)) != 0)
122 if ((mask
& (MASK_ONE
<< 14)) != 0)
125 if ((mask
& (MASK_ONE
<< 15)) != 0)
128 if ((mask
& (MASK_ONE
<< 16)) != 0)
131 if ((mask
& (MASK_ONE
<< 17)) != 0)
134 if ((mask
& (MASK_ONE
<< 18)) != 0)
137 if ((mask
& (MASK_ONE
<< 19)) != 0)
140 if ((mask
& (MASK_ONE
<< 20)) != 0)
143 if ((mask
& (MASK_ONE
<< 21)) != 0)
146 if ((mask
& (MASK_ONE
<< 22)) != 0)
149 if ((mask
& (MASK_ONE
<< 23)) != 0)
152 if ((mask
& (MASK_ONE
<< 24)) != 0)
155 if ((mask
& (MASK_ONE
<< 25)) != 0)
158 if ((mask
& (MASK_ONE
<< 26)) != 0)
161 if ((mask
& (MASK_ONE
<< 27)) != 0)
164 if ((mask
& (MASK_ONE
<< 28)) != 0)
167 if ((mask
& (MASK_ONE
<< 29)) != 0)
170 if ((mask
& (MASK_ONE
<< 30)) != 0)
173 if ((mask
& (MASK_ONE
<< 31)) != 0)
176 if ((mask
& (MASK_ONE
<< 32)) != 0)
179 if ((mask
& (MASK_ONE
<< 33)) != 0)
182 if ((mask
& (MASK_ONE
<< 34)) != 0)
185 if ((mask
& (MASK_ONE
<< 35)) != 0)
188 if ((mask
& (MASK_ONE
<< 36)) != 0)
191 if ((mask
& (MASK_ONE
<< 37)) != 0)
194 if ((mask
& (MASK_ONE
<< 38)) != 0)
197 if ((mask
& (MASK_ONE
<< 39)) != 0)
201 while ((mask
= *sub_mask
++) != 0)
203 value
= *sub_values
++;
205 __asm__ (" #reg %0" : "+d" (value
));
207 if ((mask
& (MASK_ONE
<< 0)) != 0)
210 if ((mask
& (MASK_ONE
<< 1)) != 0)
213 if ((mask
& (MASK_ONE
<< 2)) != 0)
216 if ((mask
& (MASK_ONE
<< 3)) != 0)
219 if ((mask
& (MASK_ONE
<< 4)) != 0)
222 if ((mask
& (MASK_ONE
<< 5)) != 0)
225 if ((mask
& (MASK_ONE
<< 6)) != 0)
228 if ((mask
& (MASK_ONE
<< 7)) != 0)
231 if ((mask
& (MASK_ONE
<< 8)) != 0)
234 if ((mask
& (MASK_ONE
<< 9)) != 0)
237 if ((mask
& (MASK_ONE
<< 10)) != 0)
240 if ((mask
& (MASK_ONE
<< 11)) != 0)
243 if ((mask
& (MASK_ONE
<< 12)) != 0)
246 if ((mask
& (MASK_ONE
<< 13)) != 0)
249 if ((mask
& (MASK_ONE
<< 14)) != 0)
252 if ((mask
& (MASK_ONE
<< 15)) != 0)
255 if ((mask
& (MASK_ONE
<< 16)) != 0)
258 if ((mask
& (MASK_ONE
<< 17)) != 0)
261 if ((mask
& (MASK_ONE
<< 18)) != 0)
264 if ((mask
& (MASK_ONE
<< 19)) != 0)
267 if ((mask
& (MASK_ONE
<< 20)) != 0)
270 if ((mask
& (MASK_ONE
<< 21)) != 0)
273 if ((mask
& (MASK_ONE
<< 22)) != 0)
276 if ((mask
& (MASK_ONE
<< 23)) != 0)
279 if ((mask
& (MASK_ONE
<< 24)) != 0)
282 if ((mask
& (MASK_ONE
<< 25)) != 0)
285 if ((mask
& (MASK_ONE
<< 26)) != 0)
288 if ((mask
& (MASK_ONE
<< 27)) != 0)
291 if ((mask
& (MASK_ONE
<< 28)) != 0)
294 if ((mask
& (MASK_ONE
<< 29)) != 0)
297 if ((mask
& (MASK_ONE
<< 30)) != 0)
300 if ((mask
& (MASK_ONE
<< 31)) != 0)
303 if ((mask
& (MASK_ONE
<< 32)) != 0)
306 if ((mask
& (MASK_ONE
<< 33)) != 0)
309 if ((mask
& (MASK_ONE
<< 34)) != 0)
312 if ((mask
& (MASK_ONE
<< 35)) != 0)
315 if ((mask
& (MASK_ONE
<< 36)) != 0)
318 if ((mask
& (MASK_ONE
<< 37)) != 0)
321 if ((mask
& (MASK_ONE
<< 38)) != 0)
324 if ((mask
& (MASK_ONE
<< 39)) != 0)
328 while ((mask
= *mul_mask
++) != 0)
330 value
= *mul_values
++;
332 __asm__ (" #reg %0" : "+d" (value
));
334 if ((mask
& (MASK_ONE
<< 0)) != 0)
337 if ((mask
& (MASK_ONE
<< 1)) != 0)
340 if ((mask
& (MASK_ONE
<< 2)) != 0)
343 if ((mask
& (MASK_ONE
<< 3)) != 0)
346 if ((mask
& (MASK_ONE
<< 4)) != 0)
349 if ((mask
& (MASK_ONE
<< 5)) != 0)
352 if ((mask
& (MASK_ONE
<< 6)) != 0)
355 if ((mask
& (MASK_ONE
<< 7)) != 0)
358 if ((mask
& (MASK_ONE
<< 8)) != 0)
361 if ((mask
& (MASK_ONE
<< 9)) != 0)
364 if ((mask
& (MASK_ONE
<< 10)) != 0)
367 if ((mask
& (MASK_ONE
<< 11)) != 0)
370 if ((mask
& (MASK_ONE
<< 12)) != 0)
373 if ((mask
& (MASK_ONE
<< 13)) != 0)
376 if ((mask
& (MASK_ONE
<< 14)) != 0)
379 if ((mask
& (MASK_ONE
<< 15)) != 0)
382 if ((mask
& (MASK_ONE
<< 16)) != 0)
385 if ((mask
& (MASK_ONE
<< 17)) != 0)
388 if ((mask
& (MASK_ONE
<< 18)) != 0)
391 if ((mask
& (MASK_ONE
<< 19)) != 0)
394 if ((mask
& (MASK_ONE
<< 20)) != 0)
397 if ((mask
& (MASK_ONE
<< 21)) != 0)
400 if ((mask
& (MASK_ONE
<< 22)) != 0)
403 if ((mask
& (MASK_ONE
<< 23)) != 0)
406 if ((mask
& (MASK_ONE
<< 24)) != 0)
409 if ((mask
& (MASK_ONE
<< 25)) != 0)
412 if ((mask
& (MASK_ONE
<< 26)) != 0)
415 if ((mask
& (MASK_ONE
<< 27)) != 0)
418 if ((mask
& (MASK_ONE
<< 28)) != 0)
421 if ((mask
& (MASK_ONE
<< 29)) != 0)
424 if ((mask
& (MASK_ONE
<< 30)) != 0)
427 if ((mask
& (MASK_ONE
<< 31)) != 0)
430 if ((mask
& (MASK_ONE
<< 32)) != 0)
433 if ((mask
& (MASK_ONE
<< 33)) != 0)
436 if ((mask
& (MASK_ONE
<< 34)) != 0)
439 if ((mask
& (MASK_ONE
<< 35)) != 0)
442 if ((mask
& (MASK_ONE
<< 36)) != 0)
445 if ((mask
& (MASK_ONE
<< 37)) != 0)
448 if ((mask
& (MASK_ONE
<< 38)) != 0)
451 if ((mask
& (MASK_ONE
<< 39)) != 0)
455 while ((mask
= *div_mask
++) != 0)
457 value
= *div_values
++;
459 __asm__ (" #reg %0" : "+d" (value
));
461 if ((mask
& (MASK_ONE
<< 0)) != 0)
464 if ((mask
& (MASK_ONE
<< 1)) != 0)
467 if ((mask
& (MASK_ONE
<< 2)) != 0)
470 if ((mask
& (MASK_ONE
<< 3)) != 0)
473 if ((mask
& (MASK_ONE
<< 4)) != 0)
476 if ((mask
& (MASK_ONE
<< 5)) != 0)
479 if ((mask
& (MASK_ONE
<< 6)) != 0)
482 if ((mask
& (MASK_ONE
<< 7)) != 0)
485 if ((mask
& (MASK_ONE
<< 8)) != 0)
488 if ((mask
& (MASK_ONE
<< 9)) != 0)
491 if ((mask
& (MASK_ONE
<< 10)) != 0)
494 if ((mask
& (MASK_ONE
<< 11)) != 0)
497 if ((mask
& (MASK_ONE
<< 12)) != 0)
500 if ((mask
& (MASK_ONE
<< 13)) != 0)
503 if ((mask
& (MASK_ONE
<< 14)) != 0)
506 if ((mask
& (MASK_ONE
<< 15)) != 0)
509 if ((mask
& (MASK_ONE
<< 16)) != 0)
512 if ((mask
& (MASK_ONE
<< 17)) != 0)
515 if ((mask
& (MASK_ONE
<< 18)) != 0)
518 if ((mask
& (MASK_ONE
<< 19)) != 0)
521 if ((mask
& (MASK_ONE
<< 20)) != 0)
524 if ((mask
& (MASK_ONE
<< 21)) != 0)
527 if ((mask
& (MASK_ONE
<< 22)) != 0)
530 if ((mask
& (MASK_ONE
<< 23)) != 0)
533 if ((mask
& (MASK_ONE
<< 24)) != 0)
536 if ((mask
& (MASK_ONE
<< 25)) != 0)
539 if ((mask
& (MASK_ONE
<< 26)) != 0)
542 if ((mask
& (MASK_ONE
<< 27)) != 0)
545 if ((mask
& (MASK_ONE
<< 28)) != 0)
548 if ((mask
& (MASK_ONE
<< 29)) != 0)
551 if ((mask
& (MASK_ONE
<< 30)) != 0)
554 if ((mask
& (MASK_ONE
<< 31)) != 0)
557 if ((mask
& (MASK_ONE
<< 32)) != 0)
560 if ((mask
& (MASK_ONE
<< 33)) != 0)
563 if ((mask
& (MASK_ONE
<< 34)) != 0)
566 if ((mask
& (MASK_ONE
<< 35)) != 0)
569 if ((mask
& (MASK_ONE
<< 36)) != 0)
572 if ((mask
& (MASK_ONE
<< 37)) != 0)
575 if ((mask
& (MASK_ONE
<< 38)) != 0)
578 if ((mask
& (MASK_ONE
<< 39)) != 0)
582 while ((mask
= *eq0_mask
++) != 0)
586 if ((mask
& (MASK_ONE
<< 0)) != 0)
587 eq0
|= (value00
== ZERO
);
589 if ((mask
& (MASK_ONE
<< 1)) != 0)
590 eq0
|= (value01
== ZERO
);
592 if ((mask
& (MASK_ONE
<< 2)) != 0)
593 eq0
|= (value02
== ZERO
);
595 if ((mask
& (MASK_ONE
<< 3)) != 0)
596 eq0
|= (value03
== ZERO
);
598 if ((mask
& (MASK_ONE
<< 4)) != 0)
599 eq0
|= (value04
== ZERO
);
601 if ((mask
& (MASK_ONE
<< 5)) != 0)
602 eq0
|= (value05
== ZERO
);
604 if ((mask
& (MASK_ONE
<< 6)) != 0)
605 eq0
|= (value06
== ZERO
);
607 if ((mask
& (MASK_ONE
<< 7)) != 0)
608 eq0
|= (value07
== ZERO
);
610 if ((mask
& (MASK_ONE
<< 8)) != 0)
611 eq0
|= (value08
== ZERO
);
613 if ((mask
& (MASK_ONE
<< 9)) != 0)
614 eq0
|= (value09
== ZERO
);
616 if ((mask
& (MASK_ONE
<< 10)) != 0)
617 eq0
|= (value10
== ZERO
);
619 if ((mask
& (MASK_ONE
<< 11)) != 0)
620 eq0
|= (value11
== ZERO
);
622 if ((mask
& (MASK_ONE
<< 12)) != 0)
623 eq0
|= (value12
== ZERO
);
625 if ((mask
& (MASK_ONE
<< 13)) != 0)
626 eq0
|= (value13
== ZERO
);
628 if ((mask
& (MASK_ONE
<< 14)) != 0)
629 eq0
|= (value14
== ZERO
);
631 if ((mask
& (MASK_ONE
<< 15)) != 0)
632 eq0
|= (value15
== ZERO
);
634 if ((mask
& (MASK_ONE
<< 16)) != 0)
635 eq0
|= (value16
== ZERO
);
637 if ((mask
& (MASK_ONE
<< 17)) != 0)
638 eq0
|= (value17
== ZERO
);
640 if ((mask
& (MASK_ONE
<< 18)) != 0)
641 eq0
|= (value18
== ZERO
);
643 if ((mask
& (MASK_ONE
<< 19)) != 0)
644 eq0
|= (value19
== ZERO
);
646 if ((mask
& (MASK_ONE
<< 20)) != 0)
647 eq0
|= (value20
== ZERO
);
649 if ((mask
& (MASK_ONE
<< 21)) != 0)
650 eq0
|= (value21
== ZERO
);
652 if ((mask
& (MASK_ONE
<< 22)) != 0)
653 eq0
|= (value22
== ZERO
);
655 if ((mask
& (MASK_ONE
<< 23)) != 0)
656 eq0
|= (value23
== ZERO
);
658 if ((mask
& (MASK_ONE
<< 24)) != 0)
659 eq0
|= (value24
== ZERO
);
661 if ((mask
& (MASK_ONE
<< 25)) != 0)
662 eq0
|= (value25
== ZERO
);
664 if ((mask
& (MASK_ONE
<< 26)) != 0)
665 eq0
|= (value26
== ZERO
);
667 if ((mask
& (MASK_ONE
<< 27)) != 0)
668 eq0
|= (value27
== ZERO
);
670 if ((mask
& (MASK_ONE
<< 28)) != 0)
671 eq0
|= (value28
== ZERO
);
673 if ((mask
& (MASK_ONE
<< 29)) != 0)
674 eq0
|= (value29
== ZERO
);
676 if ((mask
& (MASK_ONE
<< 30)) != 0)
677 eq0
|= (value30
== ZERO
);
679 if ((mask
& (MASK_ONE
<< 31)) != 0)
680 eq0
|= (value31
== ZERO
);
682 if ((mask
& (MASK_ONE
<< 32)) != 0)
683 eq0
|= (value32
== ZERO
);
685 if ((mask
& (MASK_ONE
<< 33)) != 0)
686 eq0
|= (value33
== ZERO
);
688 if ((mask
& (MASK_ONE
<< 34)) != 0)
689 eq0
|= (value34
== ZERO
);
691 if ((mask
& (MASK_ONE
<< 35)) != 0)
692 eq0
|= (value35
== ZERO
);
694 if ((mask
& (MASK_ONE
<< 36)) != 0)
695 eq0
|= (value36
== ZERO
);
697 if ((mask
& (MASK_ONE
<< 37)) != 0)
698 eq0
|= (value37
== ZERO
);
700 if ((mask
& (MASK_ONE
<< 38)) != 0)
701 eq0
|= (value38
== ZERO
);
703 if ((mask
& (MASK_ONE
<< 39)) != 0)
704 eq0
|= (value39
== ZERO
);
709 return ( value00
+ value01
+ value02
+ value03
+ value04
710 + value05
+ value06
+ value07
+ value08
+ value09
711 + value10
+ value11
+ value12
+ value13
+ value14
712 + value15
+ value16
+ value17
+ value18
+ value19
713 + value20
+ value21
+ value22
+ value23
+ value24
714 + value25
+ value26
+ value27
+ value28
+ value29
715 + value30
+ value31
+ value32
+ value33
+ value34
716 + value35
+ value36
+ value37
+ value38
+ value39
);
719 /* { dg-final { scan-assembler "fadds" } } */
720 /* { dg-final { scan-assembler "fsubs" } } */
721 /* { dg-final { scan-assembler "fmuls" } } */
722 /* { dg-final { scan-assembler "fdivs" } } */
723 /* { dg-final { scan-assembler "fcmpu" } } */
724 /* { dg-final { scan-assembler "xsaddsp" } } */
725 /* { dg-final { scan-assembler "xssubsp" } } */
726 /* { dg-final { scan-assembler "xsmulsp" } } */
727 /* { dg-final { scan-assembler "xsdivsp" } } */
728 /* { dg-final { scan-assembler "xscmpudp" } } */