gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c

   1 /* { dg-do compile } */
   2 /* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
   3
   4 #include <stdint-gcc.h>
   5
   6 typedef int64_t vnx2di __attribute__((vector_size (16)));
   7 typedef int32_t vnx4si __attribute__((vector_size (16)));
   8 typedef int16_t vnx8hi __attribute__((vector_size (16)));
   9 typedef int8_t vnx16qi __attribute__((vector_size (16)));
  10 typedef _Float16 vnx8hf __attribute__((vector_size (16)));
  11 typedef float vnx4sf __attribute__((vector_size (16)));
  12 typedef double vnx2df __attribute__((vector_size (16)));
  13
  14 #define VEC_EXTRACT(S,V,IDX)                    \
  15   S                                             \
  16   __attribute__((noipa))                        \
  17   vec_extract_##V##_##IDX (V v)                 \
  18   {                                             \
  19     return v[IDX];                              \
  20   }
  21
  22 #define VEC_EXTRACT_VAR1(S,V)                   \
  23   S                                             \
  24   __attribute__((noipa))                        \
  25   vec_extract_var_##V (V v, int8_t idx)         \
  26   {                                             \
  27     return v[idx];                              \
  28   }
  29
  30 #define TEST_ALL1(T)                            \
  31   T (_Float16, vnx8hf, 0)                       \
  32   T (_Float16, vnx8hf, 3)                       \
  33   T (_Float16, vnx8hf, 7)                       \
  34   T (float, vnx4sf, 0)                          \
  35   T (float, vnx4sf, 1)                          \
  36   T (float, vnx4sf, 3)                          \
  37   T (double, vnx2df, 0)                         \
  38   T (double, vnx2df, 1)                         \
  39   T (int64_t, vnx2di, 0)                        \
  40   T (int64_t, vnx2di, 1)                        \
  41   T (int32_t, vnx4si, 0)                        \
  42   T (int32_t, vnx4si, 1)                        \
  43   T (int32_t, vnx4si, 3)                        \
  44   T (int16_t, vnx8hi, 0)                        \
  45   T (int16_t, vnx8hi, 2)                        \
  46   T (int16_t, vnx8hi, 6)                        \
  47   T (int8_t, vnx16qi, 0)                        \
  48   T (int8_t, vnx16qi, 1)                        \
  49   T (int8_t, vnx16qi, 7)                        \
  50   T (int8_t, vnx16qi, 11)                       \
  51   T (int8_t, vnx16qi, 15)                       \
  52
  53 #define TEST_ALL_VAR1(T)                        \
  54   T (_Float16, vnx8hf)                          \
  55   T (float, vnx4sf)                             \
  56   T (double, vnx2df)                            \
  57   T (int64_t, vnx2di)                           \
  58   T (int32_t, vnx4si)                           \
  59   T (int16_t, vnx8hi)                           \
  60   T (int8_t, vnx16qi)                           \
  61
  62 TEST_ALL1 (VEC_EXTRACT)
  63 TEST_ALL_VAR1 (VEC_EXTRACT_VAR1)
  64
  65 /* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*ta,\s*ma} 6 } } */
  66 /* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*ta,\s*ma} 8 } } */
  67 /* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*ta,\s*ma} 8 } } */
  68 /* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*ta,\s*ma} 6 } } */
  69
  70 /* { dg-final { scan-assembler-times {\tvslidedown.vi} 14 } } */
  71 /* { dg-final { scan-assembler-times {\tvslidedown.vx} 7 } } */
  72
  73 /* { dg-final { scan-assembler-times {\tvfmv.f.s} 11 } } */
  74 /* { dg-final { scan-assembler-times {\tvmv.x.s} 17 } } */
  75
  76 /* { dg-final { scan-assembler-not {\tsext} } } */