gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c

   1 /* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
   2
   3 /* These loads cannot be compressed because only one compressed reg is
   4    available (since args are passed in a0-a4, that leaves a5-a7 available, of
   5    which only a5 is a compressed reg). Therefore the shorten_memrefs pass should
   6    not attempt to rewrite these loads into a compressible format. It may not
   7    be possible to avoid this because shorten_memrefs happens before reg alloc.
   8 */
   9
  10 extern int sub1 (int, int, int, int, int, int, int);
  11
  12 int
  13 load1a (int a0, int a1, int a2, int a3, int a4, int *array)
  14 {
  15   int a = 0;
  16   a += array[200];
  17   a += array[201];
  18   a += array[202];
  19   a += array[203];
  20   return sub1 (a0, a1, a2, a3, a4, 0, a);
  21 }
  22
  23 extern long long sub2 (long long, long long, long long, long long, long long,
  24            long long, long long);
  25
  26 long long
  27 load2a (long long a0, long long a1, long long a2, long long a3, long long a4,
  28   long long *array)
  29 {
  30   int a = 0;
  31   a += array[200];
  32   a += array[201];
  33   a += array[202];
  34   a += array[203];
  35   return sub2 (a0, a1, a2, a3, a4, 0, a);
  36 }
  37
  38 /* { dg-final { scan-assembler-not "load1a:\n\taddi" { xfail riscv*-*-* } } } */
  39 /* { dg-final { scan-assembler-not "load2a:\n.*addi\[ \t\]*\[at\]\[0-9\],\[at\]\[0-9\],\[0-9\]*" { xfail riscv*-*-*  } } } */