include/configs/stxssa.h

   1 /*
   2  * (C) Copyright 2005 Embedded Alley Solutions, Inc.
   3  * Dan Malek <dan@embeddedalley.com>
   4  * Copied from STx GP3.
   5  * Updates for Silicon Tx GP3 SSA board.
   6  *
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 /* mpc8560ads board configuration file */
  14 /* please refer to doc/README.mpc85xx for more info */
  15 /* make sure you change the MAC address and other network params first,
  16  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  17  */
  18
  19 #ifndef __CONFIG_H
  20 #define __CONFIG_H
  21
  22 /* High Level Configuration Options */
  23 #define CONFIG_BOOKE            1       /* BOOKE                */
  24 #define CONFIG_E500             1       /* BOOKE e500 family    */
  25 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560      */
  26 #define CONFIG_CPM2             1       /* has CPM2 */
  27 #define CONFIG_STXSSA           1       /* Silicon Tx GPPP SSA board specific*/
  28 #define CONFIG_MPC8560          1
  29
  30 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  31
  32 #define CONFIG_PCI                      /* PCI ethernet support */
  33 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  34 #define CONFIG_TSEC_ENET                /* tsec ethernet support*/
  35 #undef CONFIG_ETHER_ON_FCC              /* cpm FCC ethernet support */
  36 #define CONFIG_ENV_OVERWRITE
  37
  38 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  39
  40 /* sysclk for MPC85xx
  41  */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33000000 /* most pci cards are 33Mhz */
  44
  45 /* Blinkin' LEDs for Robert :-)
  46 */
  47 #define CONFIG_SHOW_ACTIVITY 1
  48
  49 /*
  50  * These can be toggled for performance analysis, otherwise use default.
  51  */
  52 #define CONFIG_L2_CACHE                         /* toggle L2 cache             */
  53 #define  CONFIG_BTB                             /* toggle branch predition */
  54
  55 #define CONFIG_BOARD_EARLY_INIT_F   1           /* Call board_pre_init   */
  56
  57 #undef  CONFIG_SYS_DRAM_TEST                            /* memory test, takes time      */
  58 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  59 #define CONFIG_SYS_MEMTEST_END          0x00400000
  60
  61
  62 /* Localbus connector.  There are many options that can be
  63  * connected here, including sdram or lots of flash.
  64  * This address, however, is used to configure a 256M local bus
  65  * window that includes the Config latch below.
  66  */
  67 #define CONFIG_SYS_LBC_OPTION_BASE      0xF0000000      /* Localbus Extension */
  68 #define CONFIG_SYS_LBC_OPTION_SIZE      256             /* 256MB */
  69
  70 /* There are various flash options used, we configure for the largest,
  71  * which is 64Mbytes.  The CFI works fine and will discover the proper
  72  * sizes.
  73  */
  74 #ifdef CONFIG_STXSSA_4M
  75 #define CONFIG_SYS_FLASH_BASE           0xFFC00000      /* start of  4 MiB flash */
  76 #else
  77 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of 64 MiB flash */
  78 #endif
  79 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit      */
  80 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_FLASH_BASE | 0x0FF7)
  81
  82 #define CONFIG_SYS_FLASH_CFI            1
  83 #define CONFIG_FLASH_CFI_DRIVER 1
  84 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* use buffered writes (20x faster) */
  85 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
  86 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks   */
  87
  88 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  89
  90 #define CONFIG_SYS_FLASH_PROTECTION
  91
  92 /* The configuration latch is Chip Select 1.
  93  * It's an 8-bit latch in the lower 8 bits of the word.
  94  */
  95 #define CONFIG_SYS_LBC_CFGLATCH_BASE    0xFB000000      /* Base of config latch */
  96 #define CONFIG_SYS_BR1_PRELIM           0xFB001801      /* 32-bit port */
  97 #define CONFIG_SYS_OR1_PRELIM           0xFFFF0FF7      /* 64K is enough */
  98
  99 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
 100
 101 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 102 #define CONFIG_SYS_RAMBOOT
 103 #else
 104 #undef  CONFIG_SYS_RAMBOOT
 105 #endif
 106
 107 #ifdef CONFIG_SYS_RAMBOOT
 108 #define CONFIG_SYS_CCSRBAR_DEFAULT      0x40000000      /* CCSRBAR by BDI cfg   */
 109 #endif
 110
 111 #define CONFIG_SYS_CCSRBAR              0xe0000000
 112 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 113
 114 /* DDR Setup */
 115 #define CONFIG_SYS_FSL_DDR1
 116 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 117 #define CONFIG_DDR_SPD
 118 #undef CONFIG_FSL_DDR_INTERACTIVE
 119
 120 #undef  CONFIG_DDR_ECC                  /* only for ECC DDR module */
 121 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
 122
 123 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 124
 125 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 126 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 127
 128 #define CONFIG_NUM_DDR_CONTROLLERS      1
 129 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 130 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 131
 132 /* I2C addresses of SPD EEPROMs */
 133 #define SPD_EEPROM_ADDRESS      0x54    /* CTLR 0 DIMM 0 */
 134
 135 #undef CONFIG_CLOCKS_IN_MHZ
 136
 137 /* local bus definitions */
 138 #define CONFIG_SYS_BR2_PRELIM           0xf8001861      /* 64MB localbus SDRAM  */
 139 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 140 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* local bus freq       */
 141 #define CONFIG_SYS_LBC_LBCR             0x00000000
 142 #define CONFIG_SYS_LBC_LSRT             0x20000000
 143 #define CONFIG_SYS_LBC_MRTPR            0x20000000
 144 #define CONFIG_SYS_LBC_LSDMR_1          0x2861b723
 145 #define CONFIG_SYS_LBC_LSDMR_2          0x0861b723
 146 #define CONFIG_SYS_LBC_LSDMR_3          0x0861b723
 147 #define CONFIG_SYS_LBC_LSDMR_4          0x1861b723
 148 #define CONFIG_SYS_LBC_LSDMR_5          0x4061b723
 149
 150 #define CONFIG_SYS_INIT_RAM_LOCK        1
 151 #define CONFIG_SYS_INIT_RAM_ADDR        0x60000000      /* Initial RAM address  */
 152 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 153
 154 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 155 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 156
 157 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 158 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)    /* Reserved for malloc */
 159
 160 /* Serial Port */
 161 #define CONFIG_CONS_INDEX     2
 162 #define CONFIG_SYS_NS16550
 163 #define CONFIG_SYS_NS16550_SERIAL
 164 #define CONFIG_SYS_NS16550_REG_SIZE     1
 165 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 166
 167 #define CONFIG_SYS_BAUDRATE_TABLE  \
 168         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 169
 170 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 171 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 172
 173 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 174 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 175 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 176
 177 /* pass open firmware flat tree */
 178 #define CONFIG_OF_LIBFDT                1
 179 #define CONFIG_OF_BOARD_SETUP           1
 180 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 181
 182 /*
 183  * I2C
 184  */
 185 #define CONFIG_SYS_I2C
 186 #define CONFIG_SYS_I2C_FSL
 187 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 188 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 189 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 190 #undef CONFIG_SYS_I2C_NOPROBES
 191
 192 /* I2C RTC */
 193 #define CONFIG_RTC_DS1337               /* This is really a DS1339 RTC  */
 194 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 195
 196 /* I2C EEPROM.  AT24C32, we keep our environment in here.
 197 */
 198 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x51    /* 1010001x             */
 199 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write  */
 201 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 202
 203 /*
 204  * Standard 8555 PCI mapping.
 205  * Addresses are mapped 1-1.
 206  */
 207 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 208 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 209 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 210 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 211 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 212 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M */
 213
 214 #define CONFIG_SYS_PCI2_MEM_BASE        0xa0000000
 215 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 216 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 217 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 218 #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
 219 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000      /* 16M */
 220
 221 #if defined(CONFIG_PCI)                 /* PCI Ethernet card */
 222 #define CONFIG_MPC85XX_PCI2     1
 223 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 224
 225 #define CONFIG_EEPRO100
 226 #define CONFIG_TULIP
 227
 228 #if !defined(CONFIG_PCI_PNP)
 229   #define PCI_ENET0_IOADDR      0xe0000000
 230   #define PCI_ENET0_MEMADDR     0xe0000000
 231   #define PCI_IDSEL_NUMBER      0x0c    /* slot0->3(IDSEL)=12->15 */
 232 #endif
 233
 234 #define CONFIG_PCI_SCAN_SHOW
 235 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 236
 237 #endif /* CONFIG_PCI */
 238
 239 #if defined(CONFIG_TSEC_ENET)
 240
 241 #define CONFIG_MII              1       /* MII PHY management           */
 242
 243 #define CONFIG_TSEC1    1
 244 #define CONFIG_TSEC1_NAME       "TSEC0"
 245 #define CONFIG_TSEC2    1
 246 #define CONFIG_TSEC2_NAME       "TSEC1"
 247
 248 #define TSEC1_PHY_ADDR          2
 249 #define TSEC2_PHY_ADDR          4
 250 #define TSEC1_PHYIDX            0
 251 #define TSEC2_PHYIDX            0
 252 #define TSEC1_FLAGS             TSEC_GIGABIT
 253 #define TSEC2_FLAGS             TSEC_GIGABIT
 254 #define CONFIG_ETHPRIME         "TSEC0"
 255
 256 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 257
 258 #define CONFIG_ETHER_ON_FCC2            /* define if ether on FCC   */
 259 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 260 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
 261
 262 #if (CONFIG_ETHER_INDEX == 2)
 263   /*
 264    * - Rx-CLK is CLK13
 265    * - Tx-CLK is CLK14
 266    * - Select bus for bd/buffers
 267    * - Full duplex
 268    */
 269   #define CONFIG_SYS_CMXFCR_MASK2       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 270   #define CONFIG_SYS_CMXFCR_VALUE2      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 271   #define CONFIG_SYS_CPMFCR_RAMTYPE     0
 272 #if 0
 273   #define CONFIG_SYS_FCC_PSMR           (FCC_PSMR_FDE)
 274 #else
 275   #define CONFIG_SYS_FCC_PSMR           0
 276 #endif
 277   #define FETH2_RST             0x01
 278 #elif (CONFIG_ETHER_INDEX == 3)
 279   /* need more definitions here for FE3 */
 280   #define FETH3_RST             0x80
 281 #endif                                  /* CONFIG_ETHER_INDEX */
 282
 283 /* MDIO is done through the TSEC0 control.
 284 */
 285 #define CONFIG_MII                      /* MII PHY management */
 286 #undef CONFIG_BITBANGMII                /* bit-bang MII PHY management  */
 287
 288 #endif
 289
 290 /* Environment - default config is in flash, see below */
 291 #if 0   /* in EEPROM */
 292 # define CONFIG_ENV_IS_IN_EEPROM        1
 293 # define CONFIG_ENV_OFFSET              0
 294 # define CONFIG_ENV_SIZE                2048
 295 #else   /* in flash */
 296 # define CONFIG_ENV_IS_IN_FLASH 1
 297 # ifdef CONFIG_STXSSA_4M
 298 #  define CONFIG_ENV_SECT_SIZE  0x20000
 299 # else  /* default configuration - 64 MiB flash */
 300 #  define CONFIG_ENV_SECT_SIZE  0x40000
 301 # endif
 302 # define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 303 # define CONFIG_ENV_SIZE                0x4000
 304 # define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 305 # define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
 306 #endif
 307
 308 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 309 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 310
 311 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
 312
 313
 314 /*
 315  * BOOTP options
 316  */
 317 #define CONFIG_BOOTP_BOOTFILESIZE
 318 #define CONFIG_BOOTP_BOOTPATH
 319 #define CONFIG_BOOTP_GATEWAY
 320 #define CONFIG_BOOTP_HOSTNAME
 321
 322
 323 /*
 324  * Command line configuration.
 325  */
 326 #include <config_cmd_default.h>
 327
 328 #define CONFIG_CMD_DATE
 329 #define CONFIG_CMD_DHCP
 330 #define CONFIG_CMD_EEPROM
 331 #define CONFIG_CMD_I2C
 332 #define CONFIG_CMD_NFS
 333 #define CONFIG_CMD_PING
 334 #define CONFIG_CMD_SNTP
 335 #define CONFIG_CMD_REGINFO
 336
 337 #if defined(CONFIG_PCI)
 338     #define CONFIG_CMD_PCI
 339 #endif
 340
 341 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 342     #define CONFIG_CMD_MII
 343 #endif
 344
 345 #if defined(CONFIG_SYS_RAMBOOT)
 346     #undef CONFIG_CMD_SAVEENV
 347     #undef CONFIG_CMD_LOADS
 348 #else
 349     #define CONFIG_CMD_ELF
 350 #endif
 351
 352
 353 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 354
 355 /*
 356  * Miscellaneous configurable options
 357  */
 358 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 359 #define CONFIG_SYS_PROMPT       "SSA=> "        /* Monitor Command Prompt       */
 360 #if defined(CONFIG_CMD_KGDB)
 361 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 362 #else
 363 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 364 #endif
 365 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 366 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 367 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 368 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 369
 370 /*
 371  * For booting Linux, the board info and command line data
 372  * have to be in the first 8 MB of memory, since this is
 373  * the maximum mapped by the Linux kernel during initialization.
 374  */
 375 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 376
 377 #if defined(CONFIG_CMD_KGDB)
 378 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 379 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 380 #endif
 381
 382 /*Note: change below for your network setting!!! */
 383 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 384 #define CONFIG_HAS_ETH0
 385 #define CONFIG_ETHADDR   00:e0:0c:07:9b:8a
 386 #define CONFIG_HAS_ETH1
 387 #define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
 388 #define CONFIG_HAS_ETH2
 389 #define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
 390 #endif
 391
 392 /*
 393  * Environment in EEPROM is compatible with different flash sector sizes,
 394  * but only little space is available, so we use a very simple setup.
 395  * With environment in flash, we use a more powerful default configuration.
 396  */
 397 #ifdef CONFIG_ENV_IS_IN_EEPROM          /* use restricted "standard" environment */
 398
 399 #define CONFIG_BAUDRATE         38400
 400
 401 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 402 #define CONFIG_BOOTCOMMAND      "bootm 0xffc00000 0xffd00000"
 403 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
 404 #define CONFIG_SERVERIP         192.168.85.1
 405 #define CONFIG_IPADDR           192.168.85.60
 406 #define CONFIG_GATEWAYIP        192.168.85.1
 407 #define CONFIG_NETMASK          255.255.255.0
 408 #define CONFIG_HOSTNAME         STX_SSA
 409 #define CONFIG_ROOTPATH         "/gppproot"
 410 #define CONFIG_BOOTFILE         "uImage"
 411 #define CONFIG_LOADADDR         0x1000000
 412
 413 #else /* ENV IS IN FLASH                -- use a full-blown envionment */
 414
 415 #define CONFIG_BAUDRATE         115200
 416
 417 #define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 418
 419 #define CONFIG_PREBOOT  "echo;" \
 420         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 421         "echo"
 422
 423 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 424
 425 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 426         "hostname=gp3ssa\0"                                             \
 427         "bootfile=/tftpboot/gp3ssa/uImage\0"                            \
 428         "loadaddr=400000\0"                                             \
 429         "netdev=eth0\0"                                                 \
 430         "consdev=ttyS1\0"                                               \
 431         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 432                 "nfsroot=$serverip:$rootpath\0"                         \
 433         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 434         "addip=setenv bootargs $bootargs "                              \
 435                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 436                 ":$hostname:$netdev:off panic=1\0"                      \
 437         "addcons=setenv bootargs $bootargs "                            \
 438                 "console=$consdev,$baudrate\0"                          \
 439         "flash_nfs=run nfsargs addip addcons;"                          \
 440                 "bootm $kernel_addr\0"                                  \
 441         "flash_self=run ramargs addip addcons;"                         \
 442                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 443         "net_nfs=tftp $loadaddr $bootfile;"                             \
 444                 "run nfsargs addip addcons;bootm\0"                     \
 445         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 446         "kernel_addr=FC000000\0"                                        \
 447         "ramdisk_addr=FC200000\0"                                       \
 448         ""
 449 #define CONFIG_BOOTCOMMAND      "run flash_self"
 450
 451 #endif  /* CONFIG_ENV_IS_IN_EEPROM */
 452
 453 #endif  /* __CONFIG_H */