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git.ipfire.org Git - thirdparty/gcc.git/blob - libatomic/config/x86/host-config.h
1 /* Copyright (C) 2012-2021 Free Software Foundation, Inc.
2 Contributed by Richard Henderson <rth@redhat.com>.
4 This file is part of the GNU Atomic Library (libatomic).
6 Libatomic is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 Libatomic is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
13 FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 Under Section 7 of GPL version 3, you are granted additional
17 permissions described in the GCC Runtime Library Exception, version
18 3.1, as published by the Free Software Foundation.
20 You should have received a copy of the GNU General Public License and
21 a copy of the GCC Runtime Library Exception along with this program;
22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23 <http://www.gnu.org/licenses/>. */
29 # define FEAT1_REGISTER ecx
31 # define FEAT1_REGISTER edx
34 /* Value of the CPUID feature register FEAT1_REGISTER for the cmpxchg
35 bit for IFUNC_COND1 below. */
36 extern unsigned int __libat_feat1 HIDDEN
;
38 /* Initialize libat_feat1 and return its value. */
39 unsigned int __libat_feat1_init (void) HIDDEN
;
41 /* Return the value of the relevant feature register for the relevant
42 cmpxchg bit, or 0 if there is no CPUID support. */
43 static inline unsigned int
44 __attribute__ ((const))
47 /* See the store in __libat_feat1_init. */
48 unsigned int feat1
= __atomic_load_n (&__libat_feat1
, __ATOMIC_RELAXED
);
50 /* Assume that initialization has not happened yet. This may get
51 called repeatedly if the CPU does not have any feature bits at
53 feat1
= __libat_feat1_init ();
58 # define IFUNC_COND_1 (load_feat1 () & bit_CMPXCHG16B)
60 # define IFUNC_COND_1 (load_feat1 () & bit_CMPXCHG8B)
64 # define IFUNC_NCOND(N) (N == 16)
66 # define IFUNC_NCOND(N) (N == 8)
70 # undef MAYBE_HAVE_ATOMIC_CAS_16
71 # define MAYBE_HAVE_ATOMIC_CAS_16 IFUNC_COND_1
72 # undef MAYBE_HAVE_ATOMIC_EXCHANGE_16
73 # define MAYBE_HAVE_ATOMIC_EXCHANGE_16 IFUNC_COND_1
74 # undef MAYBE_HAVE_ATOMIC_LDST_16
75 # define MAYBE_HAVE_ATOMIC_LDST_16 IFUNC_COND_1
76 /* Since load and store are implemented with CAS, they are not fast. */
77 # undef FAST_ATOMIC_LDST_16
78 # define FAST_ATOMIC_LDST_16 0
80 # undef HAVE_ATOMIC_CAS_16
81 # define HAVE_ATOMIC_CAS_16 1
84 # undef MAYBE_HAVE_ATOMIC_CAS_8
85 # define MAYBE_HAVE_ATOMIC_CAS_8 IFUNC_COND_1
86 # undef MAYBE_HAVE_ATOMIC_EXCHANGE_8
87 # define MAYBE_HAVE_ATOMIC_EXCHANGE_8 IFUNC_COND_1
88 # undef MAYBE_HAVE_ATOMIC_LDST_8
89 # define MAYBE_HAVE_ATOMIC_LDST_8 IFUNC_COND_1
91 # undef HAVE_ATOMIC_CAS_8
92 # define HAVE_ATOMIC_CAS_8 1
96 #if defined(__x86_64__) && N == 16 && IFUNC_ALT == 1
98 atomic_compare_exchange_n (UTYPE
*mptr
, UTYPE
*eptr
, UTYPE newval
,
99 bool weak_p UNUSED
, int sm UNUSED
, int fm UNUSED
)
101 UTYPE cmpval
= *eptr
;
102 UTYPE oldval
= __sync_val_compare_and_swap_16 (mptr
, cmpval
, newval
);
103 if (oldval
== cmpval
)
108 # define atomic_compare_exchange_n atomic_compare_exchange_n
109 #endif /* Have CAS 16 */
111 #endif /* HAVE_IFUNC */
113 #include_next <host-config.h>