libgcc/config/aarch64/sync-cache.c

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 void
  22 __aarch64_sync_cache_range (const void *base, const void *end)
  23 {
  24   unsigned icache_lsize;
  25   unsigned dcache_lsize;
  26   static unsigned int cache_info = 0;
  27   const char *address;
  28
  29   if (! cache_info)
  30     /* CTR_EL0 [3:0] contains log2 of icache line size in words.
  31        CTR_EL0 [19:16] contains log2 of dcache line size in words.  */
  32     asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info));
  33
  34   icache_lsize = 4 << (cache_info & 0xF);
  35   dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
  36
  37   /* Loop over the address range, clearing one cache line at once.
  38      Data cache must be flushed to unification first to make sure the
  39      instruction cache fetches the updated data.  'end' is exclusive,
  40      as per the GNU definition of __clear_cache.  */
  41
  42   /* Make the start address of the loop cache aligned.  */
  43   address = (const char*) ((__UINTPTR_TYPE__) base
  44                            & ~ (__UINTPTR_TYPE__) (dcache_lsize - 1));
  45
  46   for (address; address < (const char *) end; address += dcache_lsize)
  47     asm volatile ("dc\tcvau, %0"
  48                   :
  49                   : "r" (address)
  50                   : "memory");
  51
  52   asm volatile ("dsb\tish" : : : "memory");
  53
  54   /* Make the start address of the loop cache aligned.  */
  55   address = (const char*) ((__UINTPTR_TYPE__) base
  56                            & ~ (__UINTPTR_TYPE__) (icache_lsize - 1));
  57
  58   for (address; address < (const char *) end; address += icache_lsize)
  59     asm volatile ("ic\tivau, %0"
  60                   :
  61                   : "r" (address)
  62                   : "memory");
  63
  64   asm volatile ("dsb\tish; isb" : : : "memory");
  65 }