libgcc/config/arc/gmon/dcache_linesz.S

   1 /* This file contains code to do profiling.
   2
   3    Copyright (C) 2007-2016 Free Software Foundation, Inc.
   4    Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
   5                 on behalf of Synopsys Inc.
   6
   7 This file is part of GCC.
   8
   9 GCC is free software; you can redistribute it and/or modify it under
  10 the terms of the GNU General Public License as published by the Free
  11 Software Foundation; either version 3, or (at your option) any later
  12 version.
  13
  14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 for more details.
  18
  19 Under Section 7 of GPL version 3, you are granted additional
  20 permissions described in the GCC Runtime Library Exception, version
  21 3.1, as published by the Free Software Foundation.
  22
  23 You should have received a copy of the GNU General Public License and
  24 a copy of the GCC Runtime Library Exception along with this program;
  25 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  26 <http://www.gnu.org/licenses/>.  */
  27
  28 #include "../asm.h"
  29 #include "auxreg.h"
  30 /*  This file contains code to do profiling.  */
  31         .weak   __profile_timer_cycles
  32         .global __profile_timer_cycles
  33         .set    __profile_timer_cycles, 200
  34         .text
  35         ; For Arctangent-A5, if no data cache is present, a read of the
  36         ; cache build register returns the ID register.  For ARC600 and
  37         ; later, the version field will be zero.
  38         .global __dcache_linesz
  39         .balign 4
  40 __dcache_linesz:
  41 #if !defined (__EM__) && !defined (__HS__)
  42         lr      r12,[D_CACHE_BUILD]
  43         extb_s  r0,r12
  44         breq_s  r0,0,.Lsz_nocache
  45         brge    r0,0x20,.Lsz_havecache
  46         lr      r0,[IDENTITY]
  47         breq    r12,r0,.Lsz_nocache
  48 .Lsz_havecache:
  49         lsr_s   r12,r12,16
  50         mov_s   r0,16
  51         bmsk_s  r12,r12,3
  52         asl_s   r0,r0,r12
  53         j_s     [blink]
  54 .Lsz_nocache:
  55 #endif /* !__EM__  && !__HS__ */
  56         mov_s   r0,1
  57         j_s     [blink]