libgcc/config/nds32/isr-library/save_partial.inc

   1 /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2015 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    Under Section 7 of GPL version 3, you are granted additional
  18    permissions described in the GCC Runtime Library Exception, version
  19    3.1, as published by the Free Software Foundation.
  20
  21    You should have received a copy of the GNU General Public License and
  22    a copy of the GCC Runtime Library Exception along with this program;
  23    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  24    <http://www.gnu.org/licenses/>.  */
  25
  26 .macro SAVE_PARTIAL_4B
  27 #ifdef __NDS32_REDUCED_REGS__
  28         smw.adm $r15, [$sp], $r15, #0x2
  29 #else /* not __NDS32_REDUCED_REGS__ */
  30         smw.adm $r15, [$sp], $r27, #0x2
  31 #endif /* not __NDS32_REDUCED_REGS__ */
  32         smw.adm $r0, [$sp], $r5, #0x0
  33 #ifdef NDS32_EXT_IFC
  34         mfusr   $r1, $IFC_LP
  35         smw.adm $r1, [$sp], $r2, #0x0   /* Save extra $r2 to keep
  36                                            stack 8-byte alignment.  */
  37 #endif
  38         SAVE_MAC_REGS
  39         SAVE_FPU_REGS
  40 #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
  41        mfsr    $r1, $IPC       /* Get IPC.  */
  42        mfsr    $r2, $IPSW      /* Get IPSW.  */
  43        smw.adm $r1, [$sp], $r2, #0x0   /* Push IPC, IPSW.  */
  44 #endif
  45         mfsr    $r0, $ITYPE     /* Get VID to $r0.  */
  46         srli    $r0, $r0, #5
  47 #ifdef __NDS32_ISA_V2__
  48         andi    $r0, $r0, #127
  49 #else
  50         fexti33 $r0, #6
  51 #endif
  52 .endm
  53
  54 .macro SAVE_PARTIAL
  55 /* SAVE_CALLER_REGS code has been moved to
  56    vector table generated by compiler.  */
  57 #ifdef NDS32_EXT_IFC
  58         mfusr   $r1, $IFC_LP
  59         smw.adm $r1, [$sp], $r2, #0x0   /* Save extra $r2 to keep
  60                                            stack 8-byte alignment.  */
  61 #endif
  62         SAVE_MAC_REGS
  63         SAVE_FPU_REGS
  64 #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
  65        mfsr    $r1, $IPC       /* Get IPC.  */
  66        mfsr    $r2, $IPSW      /* Get IPSW.  */
  67        smw.adm $r1, [$sp], $r2, #0x0   /* Push IPC, IPSW.  */
  68 #endif
  69 .endm