libstdc++-v3/config/cpu/ia64/atomic_word.h

   1 // Low-level type for atomic operations -*- C++ -*-
   2
   3 // Copyright (C) 2004, 2005, 2006, 2007, 2009, 2011
   4 // Free Software Foundation, Inc.
   5 //
   6 // This file is part of the GNU ISO C++ Library.  This library is free
   7 // software; you can redistribute it and/or modify it under the
   8 // terms of the GNU General Public License as published by the
   9 // Free Software Foundation; either version 3, or (at your option)
  10 // any later version.
  11
  12 // This library is distributed in the hope that it will be useful,
  13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 // GNU General Public License for more details.
  16
  17 // Under Section 7 of GPL version 3, you are granted additional
  18 // permissions described in the GCC Runtime Library Exception, version
  19 // 3.1, as published by the Free Software Foundation.
  20
  21 // You should have received a copy of the GNU General Public License and
  22 // a copy of the GCC Runtime Library Exception along with this program;
  23 // see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  24 // <http://www.gnu.org/licenses/>.
  25
  26 #ifndef _GLIBCXX_ATOMIC_WORD_H
  27 #define _GLIBCXX_ATOMIC_WORD_H  1
  28
  29 #include <bits/cxxabi_tweaks.h>
  30
  31 typedef int _Atomic_word;
  32
  33 namespace __gnu_cxx _GLIBCXX_VISIBILITY(default)
  34 {
  35   // Test the first byte of __g and ensure that no loads are hoisted across
  36   // the test.
  37   inline bool
  38   __test_and_acquire (__cxxabiv1::__guard *__g)
  39   {
  40     unsigned char __c;
  41     unsigned char *__p = reinterpret_cast<unsigned char *>(__g);
  42     // ldN.acq is a load with an implied hoist barrier.
  43     // would ld8+mask be faster than just doing an ld1?
  44     __asm __volatile ("ld1.acq %0 = %1" : "=r"(__c) : "m"(*__p) : "memory");
  45     return __c != 0;
  46   }
  47
  48   // Set the first byte of __g to 1 and ensure that no stores are sunk
  49   // across the store.
  50   inline void
  51   __set_and_release (__cxxabiv1::__guard *__g)
  52   {
  53     unsigned char *__p = reinterpret_cast<unsigned char *>(__g);
  54     // stN.rel is a store with an implied sink barrier.
  55     // could load word, set flag, and CAS it back
  56     __asm __volatile ("st1.rel %0 = %1" : "=m"(*__p) : "r"(1) : "memory");
  57   }
  58
  59   // We don't define the _BARRIER macros on ia64 because the barriers are
  60   // included in the test and set, above.
  61 #define _GLIBCXX_GUARD_TEST_AND_ACQUIRE(G) __gnu_cxx::__test_and_acquire (G)
  62 #define _GLIBCXX_GUARD_SET_AND_RELEASE(G) __gnu_cxx::__set_and_release (G)
  63 }
  64
  65 #endif