2 * The PCI Utilities -- Show Capabilities
4 * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 cap_pm(struct device
*d
, int where
, int cap
)
18 static int pm_aux_current
[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
20 printf("Power Management version %d\n", cap
& PCI_PM_CAP_VER_MASK
);
23 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
24 FLAG(cap
, PCI_PM_CAP_PME_CLOCK
),
25 FLAG(cap
, PCI_PM_CAP_DSI
),
26 FLAG(cap
, PCI_PM_CAP_D1
),
27 FLAG(cap
, PCI_PM_CAP_D2
),
28 pm_aux_current
[(cap
>> 6) & 7],
29 FLAG(cap
, PCI_PM_CAP_PME_D0
),
30 FLAG(cap
, PCI_PM_CAP_PME_D1
),
31 FLAG(cap
, PCI_PM_CAP_PME_D2
),
32 FLAG(cap
, PCI_PM_CAP_PME_D3_HOT
),
33 FLAG(cap
, PCI_PM_CAP_PME_D3_COLD
));
34 if (!config_fetch(d
, where
+ PCI_PM_CTRL
, PCI_PM_SIZEOF
- PCI_PM_CTRL
))
36 t
= get_conf_word(d
, where
+ PCI_PM_CTRL
);
37 printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
38 t
& PCI_PM_CTRL_STATE_MASK
,
39 FLAG(t
, PCI_PM_CTRL_NO_SOFT_RST
),
40 FLAG(t
, PCI_PM_CTRL_PME_ENABLE
),
41 (t
& PCI_PM_CTRL_DATA_SEL_MASK
) >> 9,
42 (t
& PCI_PM_CTRL_DATA_SCALE_MASK
) >> 13,
43 FLAG(t
, PCI_PM_CTRL_PME_STATUS
));
44 b
= get_conf_byte(d
, where
+ PCI_PM_PPB_EXTENSIONS
);
46 printf("\t\tBridge: PM%c B3%c\n",
47 FLAG(t
, PCI_PM_BPCC_ENABLE
),
48 FLAG(~t
, PCI_PM_PPB_B2_B3
));
52 format_agp_rate(int rate
, char *buf
, int agp3
)
62 c
+= sprintf(c
, "x%d", 1 << (i
+ 2*agp3
));
67 strcpy(buf
, "<none>");
71 cap_agp(struct device
*d
, int where
, int cap
)
78 ver
= (cap
>> 4) & 0x0f;
80 printf("AGP version %x.%x\n", ver
, rev
);
83 if (!config_fetch(d
, where
+ PCI_AGP_STATUS
, PCI_AGP_SIZEOF
- PCI_AGP_STATUS
))
85 t
= get_conf_long(d
, where
+ PCI_AGP_STATUS
);
86 if (ver
>= 3 && (t
& PCI_AGP_STATUS_AGP3
))
88 format_agp_rate(t
& 7, rate
, agp3
);
89 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
90 ((t
& PCI_AGP_STATUS_RQ_MASK
) >> 24U) + 1,
91 FLAG(t
, PCI_AGP_STATUS_ISOCH
),
92 ((t
& PCI_AGP_STATUS_ARQSZ_MASK
) >> 13),
93 ((t
& PCI_AGP_STATUS_CAL_MASK
) >> 10),
94 FLAG(t
, PCI_AGP_STATUS_SBA
),
95 FLAG(t
, PCI_AGP_STATUS_ITA_COH
),
96 FLAG(t
, PCI_AGP_STATUS_GART64
),
97 FLAG(t
, PCI_AGP_STATUS_HTRANS
),
98 FLAG(t
, PCI_AGP_STATUS_64BIT
),
99 FLAG(t
, PCI_AGP_STATUS_FW
),
100 FLAG(t
, PCI_AGP_STATUS_AGP3
),
102 t
= get_conf_long(d
, where
+ PCI_AGP_COMMAND
);
103 format_agp_rate(t
& 7, rate
, agp3
);
104 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
105 ((t
& PCI_AGP_COMMAND_RQ_MASK
) >> 24U) + 1,
106 ((t
& PCI_AGP_COMMAND_ARQSZ_MASK
) >> 13),
107 ((t
& PCI_AGP_COMMAND_CAL_MASK
) >> 10),
108 FLAG(t
, PCI_AGP_COMMAND_SBA
),
109 FLAG(t
, PCI_AGP_COMMAND_AGP
),
110 FLAG(t
, PCI_AGP_COMMAND_GART64
),
111 FLAG(t
, PCI_AGP_COMMAND_64BIT
),
112 FLAG(t
, PCI_AGP_COMMAND_FW
),
117 cap_pcix_nobridge(struct device
*d
, int where
)
121 static const byte max_outstanding
[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
123 printf("PCI-X non-bridge device\n");
128 if (!config_fetch(d
, where
+ PCI_PCIX_STATUS
, 4))
131 command
= get_conf_word(d
, where
+ PCI_PCIX_COMMAND
);
132 status
= get_conf_long(d
, where
+ PCI_PCIX_STATUS
);
133 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
134 FLAG(command
, PCI_PCIX_COMMAND_DPERE
),
135 FLAG(command
, PCI_PCIX_COMMAND_ERO
),
136 1 << (9 + ((command
& PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT
) >> 2U)),
137 max_outstanding
[(command
& PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS
) >> 4U]);
138 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
139 ((status
>> 8) & 0xff),
140 ((status
>> 3) & 0x1f),
141 (status
& PCI_PCIX_STATUS_FUNCTION
),
142 FLAG(status
, PCI_PCIX_STATUS_64BIT
),
143 FLAG(status
, PCI_PCIX_STATUS_133MHZ
),
144 FLAG(status
, PCI_PCIX_STATUS_SC_DISCARDED
),
145 FLAG(status
, PCI_PCIX_STATUS_UNEXPECTED_SC
),
146 ((status
& PCI_PCIX_STATUS_DEVICE_COMPLEXITY
) ? "bridge" : "simple"),
147 1 << (9 + ((status
>> 21) & 3U)),
148 max_outstanding
[(status
>> 23) & 7U],
149 1 << (3 + ((status
>> 26) & 7U)),
150 FLAG(status
, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS
),
151 FLAG(status
, PCI_PCIX_STATUS_266MHZ
),
152 FLAG(status
, PCI_PCIX_STATUS_533MHZ
));
156 cap_pcix_bridge(struct device
*d
, int where
)
158 static const char * const sec_clock_freq
[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
160 u32 status
, upstcr
, downstcr
;
162 printf("PCI-X bridge device\n");
167 if (!config_fetch(d
, where
+ PCI_PCIX_BRIDGE_STATUS
, 12))
170 secstatus
= get_conf_word(d
, where
+ PCI_PCIX_BRIDGE_SEC_STATUS
);
171 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
172 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT
),
173 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ
),
174 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED
),
175 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC
),
176 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN
),
177 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED
),
178 sec_clock_freq
[(secstatus
>> 6) & 7]);
179 status
= get_conf_long(d
, where
+ PCI_PCIX_BRIDGE_STATUS
);
180 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
181 ((status
>> 8) & 0xff),
182 ((status
>> 3) & 0x1f),
183 (status
& PCI_PCIX_BRIDGE_STATUS_FUNCTION
),
184 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_64BIT
),
185 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_133MHZ
),
186 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED
),
187 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC
),
188 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN
),
189 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED
));
190 upstcr
= get_conf_long(d
, where
+ PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL
);
191 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
192 (upstcr
& PCI_PCIX_BRIDGE_STR_CAPACITY
),
193 (upstcr
>> 16) & 0xffff);
194 downstcr
= get_conf_long(d
, where
+ PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL
);
195 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
196 (downstcr
& PCI_PCIX_BRIDGE_STR_CAPACITY
),
197 (downstcr
>> 16) & 0xffff);
201 cap_pcix(struct device
*d
, int where
)
203 switch (get_conf_byte(d
, PCI_HEADER_TYPE
) & 0x7f)
205 case PCI_HEADER_TYPE_NORMAL
:
206 cap_pcix_nobridge(d
, where
);
208 case PCI_HEADER_TYPE_BRIDGE
:
209 cap_pcix_bridge(d
, where
);
215 ht_link_width(unsigned width
)
217 static char * const widths
[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
218 return widths
[width
];
222 ht_link_freq(unsigned freq
)
224 static char * const freqs
[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
225 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
230 cap_ht_pri(struct device
*d
, int where
, int cmd
)
232 u16 lctr0
, lcnf0
, lctr1
, lcnf1
, eh
;
233 u8 rid
, lfrer0
, lfcap0
, ftr
, lfrer1
, lfcap1
, mbu
, mlu
, bn
;
236 printf("HyperTransport: Slave or Primary Interface\n");
240 if (!config_fetch(d
, where
+ PCI_HT_PRI_LCTR0
, PCI_HT_PRI_SIZEOF
- PCI_HT_PRI_LCTR0
))
242 rid
= get_conf_byte(d
, where
+ PCI_HT_PRI_RID
);
243 if (rid
< 0x22 && rid
> 0x11)
244 printf("\t\t!!! Possibly incomplete decoding\n");
247 fmt
= "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
249 fmt
= "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
251 (cmd
& PCI_HT_PRI_CMD_BUID
),
252 (cmd
& PCI_HT_PRI_CMD_UC
) >> 5,
253 FLAG(cmd
, PCI_HT_PRI_CMD_MH
),
254 FLAG(cmd
, PCI_HT_PRI_CMD_DD
),
255 FLAG(cmd
, PCI_HT_PRI_CMD_DUL
));
256 lctr0
= get_conf_word(d
, where
+ PCI_HT_PRI_LCTR0
);
258 fmt
= "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
260 fmt
= "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
262 FLAG(lctr0
, PCI_HT_LCTR_CFLE
),
263 FLAG(lctr0
, PCI_HT_LCTR_CST
),
264 FLAG(lctr0
, PCI_HT_LCTR_CFE
),
265 FLAG(lctr0
, PCI_HT_LCTR_LKFAIL
),
266 FLAG(lctr0
, PCI_HT_LCTR_INIT
),
267 FLAG(lctr0
, PCI_HT_LCTR_EOC
),
268 FLAG(lctr0
, PCI_HT_LCTR_TXO
),
269 (lctr0
& PCI_HT_LCTR_CRCERR
) >> 8,
270 FLAG(lctr0
, PCI_HT_LCTR_ISOCEN
),
271 FLAG(lctr0
, PCI_HT_LCTR_LSEN
),
272 FLAG(lctr0
, PCI_HT_LCTR_EXTCTL
),
273 FLAG(lctr0
, PCI_HT_LCTR_64B
));
274 lcnf0
= get_conf_word(d
, where
+ PCI_HT_PRI_LCNF0
);
276 fmt
= "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
278 fmt
= "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
280 ht_link_width(lcnf0
& PCI_HT_LCNF_MLWI
),
281 ht_link_width((lcnf0
& PCI_HT_LCNF_MLWO
) >> 4),
282 ht_link_width((lcnf0
& PCI_HT_LCNF_LWI
) >> 8),
283 ht_link_width((lcnf0
& PCI_HT_LCNF_LWO
) >> 12),
284 FLAG(lcnf0
, PCI_HT_LCNF_DFI
),
285 FLAG(lcnf0
, PCI_HT_LCNF_DFO
),
286 FLAG(lcnf0
, PCI_HT_LCNF_DFIE
),
287 FLAG(lcnf0
, PCI_HT_LCNF_DFOE
));
288 lctr1
= get_conf_word(d
, where
+ PCI_HT_PRI_LCTR1
);
290 fmt
= "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
292 fmt
= "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
294 FLAG(lctr1
, PCI_HT_LCTR_CFLE
),
295 FLAG(lctr1
, PCI_HT_LCTR_CST
),
296 FLAG(lctr1
, PCI_HT_LCTR_CFE
),
297 FLAG(lctr1
, PCI_HT_LCTR_LKFAIL
),
298 FLAG(lctr1
, PCI_HT_LCTR_INIT
),
299 FLAG(lctr1
, PCI_HT_LCTR_EOC
),
300 FLAG(lctr1
, PCI_HT_LCTR_TXO
),
301 (lctr1
& PCI_HT_LCTR_CRCERR
) >> 8,
302 FLAG(lctr1
, PCI_HT_LCTR_ISOCEN
),
303 FLAG(lctr1
, PCI_HT_LCTR_LSEN
),
304 FLAG(lctr1
, PCI_HT_LCTR_EXTCTL
),
305 FLAG(lctr1
, PCI_HT_LCTR_64B
));
306 lcnf1
= get_conf_word(d
, where
+ PCI_HT_PRI_LCNF1
);
308 fmt
= "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
310 fmt
= "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
312 ht_link_width(lcnf1
& PCI_HT_LCNF_MLWI
),
313 ht_link_width((lcnf1
& PCI_HT_LCNF_MLWO
) >> 4),
314 ht_link_width((lcnf1
& PCI_HT_LCNF_LWI
) >> 8),
315 ht_link_width((lcnf1
& PCI_HT_LCNF_LWO
) >> 12),
316 FLAG(lcnf1
, PCI_HT_LCNF_DFI
),
317 FLAG(lcnf1
, PCI_HT_LCNF_DFO
),
318 FLAG(lcnf1
, PCI_HT_LCNF_DFIE
),
319 FLAG(lcnf1
, PCI_HT_LCNF_DFOE
));
320 printf("\t\tRevision ID: %u.%02u\n",
321 (rid
& PCI_HT_RID_MAJ
) >> 5, (rid
& PCI_HT_RID_MIN
));
324 lfrer0
= get_conf_byte(d
, where
+ PCI_HT_PRI_LFRER0
);
325 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0
& PCI_HT_LFRER_FREQ
));
326 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
327 FLAG(lfrer0
, PCI_HT_LFRER_PROT
),
328 FLAG(lfrer0
, PCI_HT_LFRER_OV
),
329 FLAG(lfrer0
, PCI_HT_LFRER_EOC
),
330 FLAG(lfrer0
, PCI_HT_LFRER_CTLT
));
331 lfcap0
= get_conf_byte(d
, where
+ PCI_HT_PRI_LFCAP0
);
332 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
333 FLAG(lfcap0
, PCI_HT_LFCAP_200
),
334 FLAG(lfcap0
, PCI_HT_LFCAP_300
),
335 FLAG(lfcap0
, PCI_HT_LFCAP_400
),
336 FLAG(lfcap0
, PCI_HT_LFCAP_500
),
337 FLAG(lfcap0
, PCI_HT_LFCAP_600
),
338 FLAG(lfcap0
, PCI_HT_LFCAP_800
),
339 FLAG(lfcap0
, PCI_HT_LFCAP_1000
),
340 FLAG(lfcap0
, PCI_HT_LFCAP_1200
),
341 FLAG(lfcap0
, PCI_HT_LFCAP_1400
),
342 FLAG(lfcap0
, PCI_HT_LFCAP_1600
),
343 FLAG(lfcap0
, PCI_HT_LFCAP_VEND
));
344 ftr
= get_conf_byte(d
, where
+ PCI_HT_PRI_FTR
);
345 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
346 FLAG(ftr
, PCI_HT_FTR_ISOCFC
),
347 FLAG(ftr
, PCI_HT_FTR_LDTSTOP
),
348 FLAG(ftr
, PCI_HT_FTR_CRCTM
),
349 FLAG(ftr
, PCI_HT_FTR_ECTLT
),
350 FLAG(ftr
, PCI_HT_FTR_64BA
),
351 FLAG(ftr
, PCI_HT_FTR_UIDRD
));
352 lfrer1
= get_conf_byte(d
, where
+ PCI_HT_PRI_LFRER1
);
353 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1
& PCI_HT_LFRER_FREQ
));
354 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
355 FLAG(lfrer1
, PCI_HT_LFRER_PROT
),
356 FLAG(lfrer1
, PCI_HT_LFRER_OV
),
357 FLAG(lfrer1
, PCI_HT_LFRER_EOC
),
358 FLAG(lfrer1
, PCI_HT_LFRER_CTLT
));
359 lfcap1
= get_conf_byte(d
, where
+ PCI_HT_PRI_LFCAP1
);
360 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
361 FLAG(lfcap1
, PCI_HT_LFCAP_200
),
362 FLAG(lfcap1
, PCI_HT_LFCAP_300
),
363 FLAG(lfcap1
, PCI_HT_LFCAP_400
),
364 FLAG(lfcap1
, PCI_HT_LFCAP_500
),
365 FLAG(lfcap1
, PCI_HT_LFCAP_600
),
366 FLAG(lfcap1
, PCI_HT_LFCAP_800
),
367 FLAG(lfcap1
, PCI_HT_LFCAP_1000
),
368 FLAG(lfcap1
, PCI_HT_LFCAP_1200
),
369 FLAG(lfcap1
, PCI_HT_LFCAP_1400
),
370 FLAG(lfcap1
, PCI_HT_LFCAP_1600
),
371 FLAG(lfcap1
, PCI_HT_LFCAP_VEND
));
372 eh
= get_conf_word(d
, where
+ PCI_HT_PRI_EH
);
373 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
374 FLAG(eh
, PCI_HT_EH_PFLE
),
375 FLAG(eh
, PCI_HT_EH_OFLE
),
376 FLAG(eh
, PCI_HT_EH_PFE
),
377 FLAG(eh
, PCI_HT_EH_OFE
),
378 FLAG(eh
, PCI_HT_EH_EOCFE
),
379 FLAG(eh
, PCI_HT_EH_RFE
),
380 FLAG(eh
, PCI_HT_EH_CRCFE
),
381 FLAG(eh
, PCI_HT_EH_SERRFE
),
382 FLAG(eh
, PCI_HT_EH_CF
),
383 FLAG(eh
, PCI_HT_EH_RE
),
384 FLAG(eh
, PCI_HT_EH_PNFE
),
385 FLAG(eh
, PCI_HT_EH_ONFE
),
386 FLAG(eh
, PCI_HT_EH_EOCNFE
),
387 FLAG(eh
, PCI_HT_EH_RNFE
),
388 FLAG(eh
, PCI_HT_EH_CRCNFE
),
389 FLAG(eh
, PCI_HT_EH_SERRNFE
));
390 mbu
= get_conf_byte(d
, where
+ PCI_HT_PRI_MBU
);
391 mlu
= get_conf_byte(d
, where
+ PCI_HT_PRI_MLU
);
392 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu
, mlu
);
393 bn
= get_conf_byte(d
, where
+ PCI_HT_PRI_BN
);
394 printf("\t\tBus Number: %02x\n", bn
);
398 cap_ht_sec(struct device
*d
, int where
, int cmd
)
400 u16 lctr
, lcnf
, ftr
, eh
;
401 u8 rid
, lfrer
, lfcap
, mbu
, mlu
;
404 printf("HyperTransport: Host or Secondary Interface\n");
408 if (!config_fetch(d
, where
+ PCI_HT_SEC_LCTR
, PCI_HT_SEC_SIZEOF
- PCI_HT_SEC_LCTR
))
410 rid
= get_conf_byte(d
, where
+ PCI_HT_SEC_RID
);
411 if (rid
< 0x22 && rid
> 0x11)
412 printf("\t\t!!! Possibly incomplete decoding\n");
415 fmt
= "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
417 fmt
= "\t\tCommand: WarmRst%c DblEnd%c\n";
419 FLAG(cmd
, PCI_HT_SEC_CMD_WR
),
420 FLAG(cmd
, PCI_HT_SEC_CMD_DE
),
421 (cmd
& PCI_HT_SEC_CMD_DN
) >> 2,
422 FLAG(cmd
, PCI_HT_SEC_CMD_CS
),
423 FLAG(cmd
, PCI_HT_SEC_CMD_HH
),
424 FLAG(cmd
, PCI_HT_SEC_CMD_AS
),
425 FLAG(cmd
, PCI_HT_SEC_CMD_HIECE
),
426 FLAG(cmd
, PCI_HT_SEC_CMD_DUL
));
427 lctr
= get_conf_word(d
, where
+ PCI_HT_SEC_LCTR
);
429 fmt
= "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
431 fmt
= "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
433 FLAG(lctr
, PCI_HT_LCTR_CFLE
),
434 FLAG(lctr
, PCI_HT_LCTR_CST
),
435 FLAG(lctr
, PCI_HT_LCTR_CFE
),
436 FLAG(lctr
, PCI_HT_LCTR_LKFAIL
),
437 FLAG(lctr
, PCI_HT_LCTR_INIT
),
438 FLAG(lctr
, PCI_HT_LCTR_EOC
),
439 FLAG(lctr
, PCI_HT_LCTR_TXO
),
440 (lctr
& PCI_HT_LCTR_CRCERR
) >> 8,
441 FLAG(lctr
, PCI_HT_LCTR_ISOCEN
),
442 FLAG(lctr
, PCI_HT_LCTR_LSEN
),
443 FLAG(lctr
, PCI_HT_LCTR_EXTCTL
),
444 FLAG(lctr
, PCI_HT_LCTR_64B
));
445 lcnf
= get_conf_word(d
, where
+ PCI_HT_SEC_LCNF
);
447 fmt
= "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
449 fmt
= "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
451 ht_link_width(lcnf
& PCI_HT_LCNF_MLWI
),
452 ht_link_width((lcnf
& PCI_HT_LCNF_MLWO
) >> 4),
453 ht_link_width((lcnf
& PCI_HT_LCNF_LWI
) >> 8),
454 ht_link_width((lcnf
& PCI_HT_LCNF_LWO
) >> 12),
455 FLAG(lcnf
, PCI_HT_LCNF_DFI
),
456 FLAG(lcnf
, PCI_HT_LCNF_DFO
),
457 FLAG(lcnf
, PCI_HT_LCNF_DFIE
),
458 FLAG(lcnf
, PCI_HT_LCNF_DFOE
));
459 printf("\t\tRevision ID: %u.%02u\n",
460 (rid
& PCI_HT_RID_MAJ
) >> 5, (rid
& PCI_HT_RID_MIN
));
463 lfrer
= get_conf_byte(d
, where
+ PCI_HT_SEC_LFRER
);
464 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer
& PCI_HT_LFRER_FREQ
));
465 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
466 FLAG(lfrer
, PCI_HT_LFRER_PROT
),
467 FLAG(lfrer
, PCI_HT_LFRER_OV
),
468 FLAG(lfrer
, PCI_HT_LFRER_EOC
),
469 FLAG(lfrer
, PCI_HT_LFRER_CTLT
));
470 lfcap
= get_conf_byte(d
, where
+ PCI_HT_SEC_LFCAP
);
471 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
472 FLAG(lfcap
, PCI_HT_LFCAP_200
),
473 FLAG(lfcap
, PCI_HT_LFCAP_300
),
474 FLAG(lfcap
, PCI_HT_LFCAP_400
),
475 FLAG(lfcap
, PCI_HT_LFCAP_500
),
476 FLAG(lfcap
, PCI_HT_LFCAP_600
),
477 FLAG(lfcap
, PCI_HT_LFCAP_800
),
478 FLAG(lfcap
, PCI_HT_LFCAP_1000
),
479 FLAG(lfcap
, PCI_HT_LFCAP_1200
),
480 FLAG(lfcap
, PCI_HT_LFCAP_1400
),
481 FLAG(lfcap
, PCI_HT_LFCAP_1600
),
482 FLAG(lfcap
, PCI_HT_LFCAP_VEND
));
483 ftr
= get_conf_word(d
, where
+ PCI_HT_SEC_FTR
);
484 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
485 FLAG(ftr
, PCI_HT_FTR_ISOCFC
),
486 FLAG(ftr
, PCI_HT_FTR_LDTSTOP
),
487 FLAG(ftr
, PCI_HT_FTR_CRCTM
),
488 FLAG(ftr
, PCI_HT_FTR_ECTLT
),
489 FLAG(ftr
, PCI_HT_FTR_64BA
),
490 FLAG(ftr
, PCI_HT_FTR_UIDRD
),
491 FLAG(ftr
, PCI_HT_SEC_FTR_EXTRS
),
492 FLAG(ftr
, PCI_HT_SEC_FTR_UCNFE
));
493 if (ftr
& PCI_HT_SEC_FTR_EXTRS
)
495 eh
= get_conf_word(d
, where
+ PCI_HT_SEC_EH
);
496 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
497 FLAG(eh
, PCI_HT_EH_PFLE
),
498 FLAG(eh
, PCI_HT_EH_OFLE
),
499 FLAG(eh
, PCI_HT_EH_PFE
),
500 FLAG(eh
, PCI_HT_EH_OFE
),
501 FLAG(eh
, PCI_HT_EH_EOCFE
),
502 FLAG(eh
, PCI_HT_EH_RFE
),
503 FLAG(eh
, PCI_HT_EH_CRCFE
),
504 FLAG(eh
, PCI_HT_EH_SERRFE
),
505 FLAG(eh
, PCI_HT_EH_CF
),
506 FLAG(eh
, PCI_HT_EH_RE
),
507 FLAG(eh
, PCI_HT_EH_PNFE
),
508 FLAG(eh
, PCI_HT_EH_ONFE
),
509 FLAG(eh
, PCI_HT_EH_EOCNFE
),
510 FLAG(eh
, PCI_HT_EH_RNFE
),
511 FLAG(eh
, PCI_HT_EH_CRCNFE
),
512 FLAG(eh
, PCI_HT_EH_SERRNFE
));
513 mbu
= get_conf_byte(d
, where
+ PCI_HT_SEC_MBU
);
514 mlu
= get_conf_byte(d
, where
+ PCI_HT_SEC_MLU
);
515 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu
, mlu
);
520 cap_ht(struct device
*d
, int where
, int cmd
)
524 switch (cmd
& PCI_HT_CMD_TYP_HI
)
526 case PCI_HT_CMD_TYP_HI_PRI
:
527 cap_ht_pri(d
, where
, cmd
);
529 case PCI_HT_CMD_TYP_HI_SEC
:
530 cap_ht_sec(d
, where
, cmd
);
534 type
= cmd
& PCI_HT_CMD_TYP
;
537 case PCI_HT_CMD_TYP_SW
:
538 printf("HyperTransport: Switch\n");
540 case PCI_HT_CMD_TYP_IDC
:
541 printf("HyperTransport: Interrupt Discovery and Configuration\n");
543 case PCI_HT_CMD_TYP_RID
:
544 printf("HyperTransport: Revision ID: %u.%02u\n",
545 (cmd
& PCI_HT_RID_MAJ
) >> 5, (cmd
& PCI_HT_RID_MIN
));
547 case PCI_HT_CMD_TYP_UIDC
:
548 printf("HyperTransport: UnitID Clumping\n");
550 case PCI_HT_CMD_TYP_ECSA
:
551 printf("HyperTransport: Extended Configuration Space Access\n");
553 case PCI_HT_CMD_TYP_AM
:
554 printf("HyperTransport: Address Mapping\n");
556 case PCI_HT_CMD_TYP_MSIM
:
557 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
558 FLAG(cmd
, PCI_HT_MSIM_CMD_EN
),
559 FLAG(cmd
, PCI_HT_MSIM_CMD_FIXD
));
560 if (verbose
>= 2 && !(cmd
& PCI_HT_MSIM_CMD_FIXD
))
563 if (!config_fetch(d
, where
+ PCI_HT_MSIM_ADDR_LO
, 8))
565 offl
= get_conf_long(d
, where
+ PCI_HT_MSIM_ADDR_LO
);
566 offh
= get_conf_long(d
, where
+ PCI_HT_MSIM_ADDR_HI
);
567 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh
<< 32) | (offl
& ~0xfffff));
570 case PCI_HT_CMD_TYP_DR
:
571 printf("HyperTransport: DirectRoute\n");
573 case PCI_HT_CMD_TYP_VCS
:
574 printf("HyperTransport: VCSet\n");
576 case PCI_HT_CMD_TYP_RM
:
577 printf("HyperTransport: Retry Mode\n");
579 case PCI_HT_CMD_TYP_X86
:
580 printf("HyperTransport: X86 (reserved)\n");
583 printf("HyperTransport: #%02x\n", type
>> 11);
588 cap_msi(struct device
*d
, int where
, int cap
)
594 printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
595 FLAG(cap
, PCI_MSI_FLAGS_ENABLE
),
596 1 << ((cap
& PCI_MSI_FLAGS_QSIZE
) >> 4),
597 1 << ((cap
& PCI_MSI_FLAGS_QMASK
) >> 1),
598 FLAG(cap
, PCI_MSI_FLAGS_MASK_BIT
),
599 FLAG(cap
, PCI_MSI_FLAGS_64BIT
));
602 is64
= cap
& PCI_MSI_FLAGS_64BIT
;
603 if (!config_fetch(d
, where
+ PCI_MSI_ADDRESS_LO
, (is64
? PCI_MSI_DATA_64
: PCI_MSI_DATA_32
) + 2 - PCI_MSI_ADDRESS_LO
))
605 printf("\t\tAddress: ");
608 t
= get_conf_long(d
, where
+ PCI_MSI_ADDRESS_HI
);
609 w
= get_conf_word(d
, where
+ PCI_MSI_DATA_64
);
613 w
= get_conf_word(d
, where
+ PCI_MSI_DATA_32
);
614 t
= get_conf_long(d
, where
+ PCI_MSI_ADDRESS_LO
);
615 printf("%08x Data: %04x\n", t
, w
);
616 if (cap
& PCI_MSI_FLAGS_MASK_BIT
)
622 if (!config_fetch(d
, where
+ PCI_MSI_MASK_BIT_64
, 8))
624 mask
= get_conf_long(d
, where
+ PCI_MSI_MASK_BIT_64
);
625 pending
= get_conf_long(d
, where
+ PCI_MSI_PENDING_64
);
629 if (!config_fetch(d
, where
+ PCI_MSI_MASK_BIT_32
, 8))
631 mask
= get_conf_long(d
, where
+ PCI_MSI_MASK_BIT_32
);
632 pending
= get_conf_long(d
, where
+ PCI_MSI_PENDING_32
);
634 printf("\t\tMasking: %08x Pending: %08x\n", mask
, pending
);
638 static float power_limit(int value
, int scale
)
640 static const float scales
[4] = { 1.0, 0.1, 0.01, 0.001 };
641 return value
* scales
[scale
];
644 static const char *latency_l0s(int value
)
646 static const char *latencies
[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
647 return latencies
[value
];
650 static const char *latency_l1(int value
)
652 static const char *latencies
[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
653 return latencies
[value
];
656 static void cap_express_dev(struct device
*d
, int where
, int type
)
661 t
= get_conf_long(d
, where
+ PCI_EXP_DEVCAP
);
662 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
663 128 << (t
& PCI_EXP_DEVCAP_PAYLOAD
),
664 (1 << ((t
& PCI_EXP_DEVCAP_PHANTOM
) >> 3)) - 1);
665 if ((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_LEG_END
))
666 printf(", Latency L0s %s, L1 %s",
667 latency_l0s((t
& PCI_EXP_DEVCAP_L0S
) >> 6),
668 latency_l1((t
& PCI_EXP_DEVCAP_L1
) >> 9));
670 printf("\t\t\tExtTag%c", FLAG(t
, PCI_EXP_DEVCAP_EXT_TAG
));
671 if ((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_LEG_END
) ||
672 (type
== PCI_EXP_TYPE_UPSTREAM
) || (type
== PCI_EXP_TYPE_PCI_BRIDGE
))
673 printf(" AttnBtn%c AttnInd%c PwrInd%c",
674 FLAG(t
, PCI_EXP_DEVCAP_ATN_BUT
),
675 FLAG(t
, PCI_EXP_DEVCAP_ATN_IND
), FLAG(t
, PCI_EXP_DEVCAP_PWR_IND
));
677 FLAG(t
, PCI_EXP_DEVCAP_RBE
));
678 if ((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_LEG_END
))
680 FLAG(t
, PCI_EXP_DEVCAP_FLRESET
));
681 if ((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_UPSTREAM
) ||
682 (type
== PCI_EXP_TYPE_PCI_BRIDGE
))
683 printf(" SlotPowerLimit %.3fW",
684 power_limit((t
& PCI_EXP_DEVCAP_PWR_VAL
) >> 18,
685 (t
& PCI_EXP_DEVCAP_PWR_SCL
) >> 26));
688 w
= get_conf_word(d
, where
+ PCI_EXP_DEVCTL
);
689 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
690 FLAG(w
, PCI_EXP_DEVCTL_CERE
),
691 FLAG(w
, PCI_EXP_DEVCTL_NFERE
),
692 FLAG(w
, PCI_EXP_DEVCTL_FERE
),
693 FLAG(w
, PCI_EXP_DEVCTL_URRE
));
694 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
695 FLAG(w
, PCI_EXP_DEVCTL_RELAXED
),
696 FLAG(w
, PCI_EXP_DEVCTL_EXT_TAG
),
697 FLAG(w
, PCI_EXP_DEVCTL_PHANTOM
),
698 FLAG(w
, PCI_EXP_DEVCTL_AUX_PME
),
699 FLAG(w
, PCI_EXP_DEVCTL_NOSNOOP
));
700 if (type
== PCI_EXP_TYPE_PCI_BRIDGE
)
701 printf(" BrConfRtry%c", FLAG(w
, PCI_EXP_DEVCTL_BCRE
));
702 if (((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_LEG_END
)) &&
703 (t
& PCI_EXP_DEVCAP_FLRESET
))
704 printf(" FLReset%c", FLAG(w
, PCI_EXP_DEVCTL_FLRESET
));
705 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
706 128 << ((w
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5),
707 128 << ((w
& PCI_EXP_DEVCTL_READRQ
) >> 12));
709 w
= get_conf_word(d
, where
+ PCI_EXP_DEVSTA
);
710 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
711 FLAG(w
, PCI_EXP_DEVSTA_CED
),
712 FLAG(w
, PCI_EXP_DEVSTA_NFED
),
713 FLAG(w
, PCI_EXP_DEVSTA_FED
),
714 FLAG(w
, PCI_EXP_DEVSTA_URD
),
715 FLAG(w
, PCI_EXP_DEVSTA_AUXPD
),
716 FLAG(w
, PCI_EXP_DEVSTA_TRPND
));
719 static char *link_speed(int speed
)
734 static char *aspm_support(int code
)
739 return "not supported";
751 static const char *aspm_enabled(int code
)
753 static const char *desc
[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
757 static void cap_express_link(struct device
*d
, int where
, int type
)
762 t
= get_conf_long(d
, where
+ PCI_EXP_LNKCAP
);
763 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Exit Latency L0s %s, L1 %s\n",
765 link_speed(t
& PCI_EXP_LNKCAP_SPEED
), (t
& PCI_EXP_LNKCAP_WIDTH
) >> 4,
766 aspm_support((t
& PCI_EXP_LNKCAP_ASPM
) >> 10),
767 latency_l0s((t
& PCI_EXP_LNKCAP_L0S
) >> 12),
768 latency_l1((t
& PCI_EXP_LNKCAP_L1
) >> 15));
769 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
770 FLAG(t
, PCI_EXP_LNKCAP_CLOCKPM
),
771 FLAG(t
, PCI_EXP_LNKCAP_SURPRISE
),
772 FLAG(t
, PCI_EXP_LNKCAP_DLLA
),
773 FLAG(t
, PCI_EXP_LNKCAP_LBNC
),
774 FLAG(t
, PCI_EXP_LNKCAP_AOC
));
776 w
= get_conf_word(d
, where
+ PCI_EXP_LNKCTL
);
777 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w
& PCI_EXP_LNKCTL_ASPM
));
778 if ((type
== PCI_EXP_TYPE_ROOT_PORT
) || (type
== PCI_EXP_TYPE_ENDPOINT
) ||
779 (type
== PCI_EXP_TYPE_LEG_END
) || (type
== PCI_EXP_TYPE_PCI_BRIDGE
))
780 printf(" RCB %d bytes", w
& PCI_EXP_LNKCTL_RCB
? 128 : 64);
781 printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
782 FLAG(w
, PCI_EXP_LNKCTL_DISABLE
),
783 FLAG(w
, PCI_EXP_LNKCTL_CLOCK
),
784 FLAG(w
, PCI_EXP_LNKCTL_XSYNCH
),
785 FLAG(w
, PCI_EXP_LNKCTL_CLOCKPM
),
786 FLAG(w
, PCI_EXP_LNKCTL_HWAUTWD
),
787 FLAG(w
, PCI_EXP_LNKCTL_BWMIE
),
788 FLAG(w
, PCI_EXP_LNKCTL_AUTBWIE
));
790 w
= get_conf_word(d
, where
+ PCI_EXP_LNKSTA
);
791 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
792 link_speed(w
& PCI_EXP_LNKSTA_SPEED
),
793 (w
& PCI_EXP_LNKSTA_WIDTH
) >> 4,
794 FLAG(w
, PCI_EXP_LNKSTA_TR_ERR
),
795 FLAG(w
, PCI_EXP_LNKSTA_TRAIN
),
796 FLAG(w
, PCI_EXP_LNKSTA_SL_CLK
),
797 FLAG(w
, PCI_EXP_LNKSTA_DL_ACT
),
798 FLAG(w
, PCI_EXP_LNKSTA_BWMGMT
),
799 FLAG(w
, PCI_EXP_LNKSTA_AUTBW
));
802 static const char *indicator(int code
)
804 static const char *names
[] = { "Unknown", "On", "Blink", "Off" };
808 static void cap_express_slot(struct device
*d
, int where
)
813 t
= get_conf_long(d
, where
+ PCI_EXP_SLTCAP
);
814 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
815 FLAG(t
, PCI_EXP_SLTCAP_ATNB
),
816 FLAG(t
, PCI_EXP_SLTCAP_PWRC
),
817 FLAG(t
, PCI_EXP_SLTCAP_MRL
),
818 FLAG(t
, PCI_EXP_SLTCAP_ATNI
),
819 FLAG(t
, PCI_EXP_SLTCAP_PWRI
),
820 FLAG(t
, PCI_EXP_SLTCAP_HPC
),
821 FLAG(t
, PCI_EXP_SLTCAP_HPS
));
822 printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
824 power_limit((t
& PCI_EXP_SLTCAP_PWR_VAL
) >> 7, (t
& PCI_EXP_SLTCAP_PWR_SCL
) >> 15),
825 FLAG(t
, PCI_EXP_SLTCAP_INTERLOCK
),
826 FLAG(t
, PCI_EXP_SLTCAP_NOCMDCOMP
));
828 w
= get_conf_word(d
, where
+ PCI_EXP_SLTCTL
);
829 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
830 FLAG(w
, PCI_EXP_SLTCTL_ATNB
),
831 FLAG(w
, PCI_EXP_SLTCTL_PWRF
),
832 FLAG(w
, PCI_EXP_SLTCTL_MRLS
),
833 FLAG(w
, PCI_EXP_SLTCTL_PRSD
),
834 FLAG(w
, PCI_EXP_SLTCTL_CMDC
),
835 FLAG(w
, PCI_EXP_SLTCTL_HPIE
),
836 FLAG(w
, PCI_EXP_SLTCTL_LLCHG
));
837 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
838 indicator((w
& PCI_EXP_SLTCTL_ATNI
) >> 6),
839 indicator((w
& PCI_EXP_SLTCTL_PWRI
) >> 8),
840 FLAG(w
, PCI_EXP_SLTCTL_PWRC
),
841 FLAG(w
, PCI_EXP_SLTCTL_INTERLOCK
));
843 w
= get_conf_word(d
, where
+ PCI_EXP_SLTSTA
);
844 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
845 FLAG(w
, PCI_EXP_SLTSTA_ATNB
),
846 FLAG(w
, PCI_EXP_SLTSTA_PWRF
),
847 FLAG(w
, PCI_EXP_SLTSTA_MRL_ST
),
848 FLAG(w
, PCI_EXP_SLTSTA_CMDC
),
849 FLAG(w
, PCI_EXP_SLTSTA_PRES
),
850 FLAG(w
, PCI_EXP_SLTSTA_INTERLOCK
));
851 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
852 FLAG(w
, PCI_EXP_SLTSTA_MRLS
),
853 FLAG(w
, PCI_EXP_SLTSTA_PRSD
),
854 FLAG(w
, PCI_EXP_SLTSTA_LLCHG
));
857 static void cap_express_root(struct device
*d
, int where
)
859 u32 w
= get_conf_word(d
, where
+ PCI_EXP_RTCTL
);
860 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
861 FLAG(w
, PCI_EXP_RTCTL_SECEE
),
862 FLAG(w
, PCI_EXP_RTCTL_SENFEE
),
863 FLAG(w
, PCI_EXP_RTCTL_SEFEE
),
864 FLAG(w
, PCI_EXP_RTCTL_PMEIE
),
865 FLAG(w
, PCI_EXP_RTCTL_CRSVIS
));
867 w
= get_conf_word(d
, where
+ PCI_EXP_RTCAP
);
868 printf("\t\tRootCap: CRSVisible%c\n",
869 FLAG(w
, PCI_EXP_RTCAP_CRSVIS
));
871 w
= get_conf_word(d
, where
+ PCI_EXP_RTSTA
);
872 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
873 w
& PCI_EXP_RTSTA_PME_REQID
,
874 FLAG(w
, PCI_EXP_RTSTA_PME_STATUS
),
875 FLAG(w
, PCI_EXP_RTSTA_PME_PENDING
));
878 static const char *cap_express_dev2_timeout_range(int type
)
880 /* Decode Completion Timeout Ranges. */
884 return "Not Supported";
904 static const char *cap_express_dev2_timeout_value(int type
)
906 /* Decode Completion Timeout Value. */
910 return "50us to 50ms";
912 return "50us to 100us";
914 return "1ms to 10ms";
916 return "16ms to 55ms";
918 return "65ms to 210ms";
920 return "260ms to 900ms";
932 static const char *cap_express_devcap2_obff(int obff
)
937 return "Via message";
941 return "Via message/WAKE#";
943 return "Not Supported";
947 static const char *cap_express_devctl2_obff(int obff
)
954 return "Via message A";
956 return "Via message B";
964 static void cap_express_dev2(struct device
*d
, int where
, int type
)
969 l
= get_conf_long(d
, where
+ PCI_EXP_DEVCAP2
);
970 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
971 cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l
)),
972 FLAG(l
, PCI_EXP_DEV2_TIMEOUT_DIS
),
973 FLAG(l
, PCI_EXP_DEVCAP2_LTR
),
974 cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l
)));
975 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_DOWNSTREAM
)
976 printf(" ARIFwd%c\n", FLAG(l
, PCI_EXP_DEV2_ARI
));
980 w
= get_conf_word(d
, where
+ PCI_EXP_DEVCTL2
);
981 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
982 cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w
)),
983 FLAG(w
, PCI_EXP_DEV2_TIMEOUT_DIS
),
984 FLAG(w
, PCI_EXP_DEV2_LTR
),
985 cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w
)));
986 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_DOWNSTREAM
)
987 printf(" ARIFwd%c\n", FLAG(w
, PCI_EXP_DEV2_ARI
));
992 static const char *cap_express_link2_speed(int type
)
996 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1008 static const char *cap_express_link2_deemphasis(int type
)
1021 static const char *cap_express_link2_transmargin(int type
)
1026 return "Normal Operating Range";
1028 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1033 return "200-400mV(full-swing)/100-200mV(half-swing)";
1039 static void cap_express_link2(struct device
*d
, int where
, int type
)
1043 if (!((type
== PCI_EXP_TYPE_ENDPOINT
|| type
== PCI_EXP_TYPE_LEG_END
) &&
1044 (d
->dev
->dev
!= 0 || d
->dev
->func
!= 0))) {
1045 w
= get_conf_word(d
, where
+ PCI_EXP_LNKCTL2
);
1046 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1047 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w
)),
1048 FLAG(w
, PCI_EXP_LNKCTL2_CMPLNC
),
1049 FLAG(w
, PCI_EXP_LNKCTL2_SPEED_DIS
));
1050 if (type
== PCI_EXP_TYPE_DOWNSTREAM
)
1051 printf(", Selectable De-emphasis: %s",
1052 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w
)));
1054 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1055 "\t\t\t Compliance De-emphasis: %s\n",
1056 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w
)),
1057 FLAG(w
, PCI_EXP_LNKCTL2_MOD_CMPLNC
),
1058 FLAG(w
, PCI_EXP_LNKCTL2_CMPLNC_SOS
),
1059 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w
)));
1062 w
= get_conf_word(d
, where
+ PCI_EXP_LNKSTA2
);
1063 printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"
1064 "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n",
1065 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w
)),
1066 FLAG(w
, PCI_EXP_LINKSTA2_EQU_COMP
),
1067 FLAG(w
, PCI_EXP_LINKSTA2_EQU_PHASE1
),
1068 FLAG(w
, PCI_EXP_LINKSTA2_EQU_PHASE2
),
1069 FLAG(w
, PCI_EXP_LINKSTA2_EQU_PHASE3
),
1070 FLAG(w
, PCI_EXP_LINKSTA2_EQU_REQ
));
1073 static void cap_express_slot2(struct device
*d UNUSED
, int where UNUSED
)
1075 /* No capabilities that require this field in PCIe rev2.0 spec. */
1079 cap_express(struct device
*d
, int where
, int cap
)
1081 int type
= (cap
& PCI_EXP_FLAGS_TYPE
) >> 4;
1088 printf("(v%d) ", cap
& PCI_EXP_FLAGS_VERS
);
1091 case PCI_EXP_TYPE_ENDPOINT
:
1094 case PCI_EXP_TYPE_LEG_END
:
1095 printf("Legacy Endpoint");
1097 case PCI_EXP_TYPE_ROOT_PORT
:
1098 slot
= cap
& PCI_EXP_FLAGS_SLOT
;
1099 printf("Root Port (Slot%c)", FLAG(cap
, PCI_EXP_FLAGS_SLOT
));
1101 case PCI_EXP_TYPE_UPSTREAM
:
1102 printf("Upstream Port");
1104 case PCI_EXP_TYPE_DOWNSTREAM
:
1105 slot
= cap
& PCI_EXP_FLAGS_SLOT
;
1106 printf("Downstream Port (Slot%c)", FLAG(cap
, PCI_EXP_FLAGS_SLOT
));
1108 case PCI_EXP_TYPE_PCI_BRIDGE
:
1109 printf("PCI-Express to PCI/PCI-X Bridge");
1111 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1112 printf("PCI/PCI-X to PCI-Express Bridge");
1114 case PCI_EXP_TYPE_ROOT_INT_EP
:
1116 printf("Root Complex Integrated Endpoint");
1118 case PCI_EXP_TYPE_ROOT_EC
:
1120 printf("Root Complex Event Collector");
1123 printf("Unknown type %d", type
);
1125 printf(", MSI %02x\n", (cap
& PCI_EXP_FLAGS_IRQ
) >> 9);
1132 if (type
== PCI_EXP_TYPE_ROOT_PORT
)
1134 if (!config_fetch(d
, where
+ PCI_EXP_DEVCAP
, size
))
1137 cap_express_dev(d
, where
, type
);
1139 cap_express_link(d
, where
, type
);
1141 cap_express_slot(d
, where
);
1142 if (type
== PCI_EXP_TYPE_ROOT_PORT
)
1143 cap_express_root(d
, where
);
1145 if ((cap
& PCI_EXP_FLAGS_VERS
) < 2)
1151 if (!config_fetch(d
, where
+ PCI_EXP_DEVCAP2
, size
))
1154 cap_express_dev2(d
, where
, type
);
1156 cap_express_link2(d
, where
, type
);
1158 cap_express_slot2(d
, where
);
1162 cap_msix(struct device
*d
, int where
, int cap
)
1166 printf("MSI-X: Enable%c Count=%d Masked%c\n",
1167 FLAG(cap
, PCI_MSIX_ENABLE
),
1168 (cap
& PCI_MSIX_TABSIZE
) + 1,
1169 FLAG(cap
, PCI_MSIX_MASK
));
1170 if (verbose
< 2 || !config_fetch(d
, where
+ PCI_MSIX_TABLE
, 8))
1173 off
= get_conf_long(d
, where
+ PCI_MSIX_TABLE
);
1174 printf("\t\tVector table: BAR=%d offset=%08x\n",
1175 off
& PCI_MSIX_BIR
, off
& ~PCI_MSIX_BIR
);
1176 off
= get_conf_long(d
, where
+ PCI_MSIX_PBA
);
1177 printf("\t\tPBA: BAR=%d offset=%08x\n",
1178 off
& PCI_MSIX_BIR
, off
& ~PCI_MSIX_BIR
);
1184 int esr
= cap
& 0xff;
1187 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1188 esr
& PCI_SID_ESR_NSLOTS
,
1189 FLAG(esr
, PCI_SID_ESR_FIC
),
1194 cap_ssvid(struct device
*d
, int where
)
1196 u16 subsys_v
, subsys_d
;
1197 char ssnamebuf
[256];
1199 if (!config_fetch(d
, where
, 8))
1201 subsys_v
= get_conf_word(d
, where
+ PCI_SSVID_VENDOR
);
1202 subsys_d
= get_conf_word(d
, where
+ PCI_SSVID_DEVICE
);
1203 printf("Subsystem: %s\n",
1204 pci_lookup_name(pacc
, ssnamebuf
, sizeof(ssnamebuf
),
1205 PCI_LOOKUP_SUBSYSTEM
| PCI_LOOKUP_VENDOR
| PCI_LOOKUP_DEVICE
,
1206 d
->dev
->vendor_id
, d
->dev
->device_id
, subsys_v
, subsys_d
));
1210 cap_debug_port(int cap
)
1212 int bar
= cap
>> 13;
1213 int pos
= cap
& 0x1fff;
1214 printf("Debug port: BAR=%d offset=%04x\n", bar
, pos
);
1218 cap_af(struct device
*d
, int where
)
1222 printf("PCI Advanced Features\n");
1223 if (verbose
< 2 || !config_fetch(d
, where
+ PCI_AF_CAP
, 3))
1226 reg
= get_conf_byte(d
, where
+ PCI_AF_CAP
);
1227 printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg
, PCI_AF_CAP_TP
),
1228 FLAG(reg
, PCI_AF_CAP_FLR
));
1229 reg
= get_conf_byte(d
, where
+ PCI_AF_CTRL
);
1230 printf("\t\tAFCtrl: FLR%c\n", FLAG(reg
, PCI_AF_CTRL_FLR
));
1231 reg
= get_conf_byte(d
, where
+ PCI_AF_STATUS
);
1232 printf("\t\tAFStatus: TP%c\n", FLAG(reg
, PCI_AF_STATUS_TP
));
1236 cap_sata_hba(struct device
*d
, int where
, int cap
)
1241 printf("SATA HBA v%d.%d", BITS(cap
, 4, 4), BITS(cap
, 0, 4));
1242 if (verbose
< 2 || !config_fetch(d
, where
+ PCI_SATA_HBA_BARS
, 4))
1248 bars
= get_conf_long(d
, where
+ PCI_SATA_HBA_BARS
);
1249 bar
= BITS(bars
, 0, 4);
1250 if (bar
>= 4 && bar
<= 9)
1251 printf(" BAR%d Offset=%08x\n", bar
- 4, BITS(bars
, 4, 20));
1253 printf(" InCfgSpace\n");
1255 printf(" BAR??%d\n", bar
);
1258 static const char *cap_ea_property(int p
, int is_secondary
)
1262 return "memory space, non-prefetchable";
1264 return "memory space, prefetchable";
1268 return "VF memory space, prefetchable";
1270 return "VF memory space, non-prefetchable";
1272 return "allocation behind bridge, non-prefetchable memory";
1274 return "allocation behind bridge, prefetchable memory";
1276 return "allocation behind bridge, I/O space";
1278 return "memory space resource unavailable for use";
1280 return "I/O space resource unavailable for use";
1283 return "entry unavailable for use, PrimaryProperties should be used";
1285 return "entry unavailable for use";
1291 static void cap_ea(struct device
*d
, int where
, int cap
)
1294 int entry_base
= where
+ 4;
1295 int num_entries
= BITS(cap
, 0, 6);
1296 u8 htype
= get_conf_byte(d
, PCI_HEADER_TYPE
) & 0x7f;
1298 printf("Enhanced Allocation (EA): NumEntries=%u", num_entries
);
1299 if (htype
== PCI_HEADER_TYPE_BRIDGE
) {
1300 byte fixed_sub
, fixed_sec
;
1303 if (!config_fetch(d
, where
+ 4, 2)) {
1307 fixed_sec
= get_conf_byte(d
, where
+ PCI_EA_CAP_TYPE1_SECONDARY
);
1308 fixed_sub
= get_conf_byte(d
, where
+ PCI_EA_CAP_TYPE1_SUBORDINATE
);
1309 printf(", secondary=%d, subordinate=%d", fixed_sec
, fixed_sub
);
1315 for (entry
= 0; entry
< num_entries
; entry
++) {
1316 int max_offset_high_pos
, has_base_high
, has_max_offset_high
;
1318 u32 base
, max_offset
;
1319 int es
, bei
, pp
, sp
;
1320 const char *prop_text
;
1322 if (!config_fetch(d
, entry_base
, 4))
1324 entry_header
= get_conf_long(d
, entry_base
);
1325 es
= BITS(entry_header
, 0, 3);
1326 bei
= BITS(entry_header
, 4, 4);
1327 pp
= BITS(entry_header
, 8, 8);
1328 sp
= BITS(entry_header
, 16, 8);
1329 if (!config_fetch(d
, entry_base
+ 4, es
* 4))
1331 printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry
,
1332 FLAG(entry_header
, PCI_EA_CAP_ENT_ENABLE
),
1333 FLAG(entry_header
, PCI_EA_CAP_ENT_WRITABLE
), es
);
1334 printf("\t\t\t BAR Equivalent Indicator: ");
1342 printf("BAR %u", bei
);
1345 printf("resource behind function");
1348 printf("not indicated");
1351 printf("expansion ROM");
1359 printf("VF-BAR %u", bei
- 9);
1367 prop_text
= cap_ea_property(pp
, 0);
1368 printf("\t\t\t PrimaryProperties: ");
1370 printf("%s\n", prop_text
);
1372 printf("[%02x]\n", pp
);
1374 prop_text
= cap_ea_property(sp
, 1);
1375 printf("\t\t\t SecondaryProperties: ");
1377 printf("%s\n", prop_text
);
1379 printf("[%02x]\n", sp
);
1381 base
= get_conf_long(d
, entry_base
+ 4);
1382 has_base_high
= ((base
& 2) != 0);
1385 max_offset
= get_conf_long(d
, entry_base
+ 8);
1386 has_max_offset_high
= ((max_offset
& 2) != 0);
1388 max_offset_high_pos
= entry_base
+ 12;
1390 printf("\t\t\t Base: ");
1391 if (has_base_high
) {
1392 u32 base_high
= get_conf_long(d
, entry_base
+ 12);
1394 printf("%x", base_high
);
1395 max_offset_high_pos
+= 4;
1397 printf("%08x\n", base
);
1399 printf("\t\t\t MaxOffset: ");
1400 if (has_max_offset_high
) {
1401 u32 max_offset_high
= get_conf_long(d
, max_offset_high_pos
);
1403 printf("%x", max_offset_high
);
1405 printf("%08x\n", max_offset
);
1407 entry_base
+= 4 + 4 * es
;
1412 show_caps(struct device
*d
, int where
)
1414 int can_have_ext_caps
= 0;
1416 if (get_conf_word(d
, PCI_STATUS
) & PCI_STATUS_CAP_LIST
)
1418 byte been_there
[256];
1419 where
= get_conf_byte(d
, where
) & ~3;
1420 memset(been_there
, 0, 256);
1424 printf("\tCapabilities: ");
1425 if (!config_fetch(d
, where
, 4))
1427 puts("<access denied>");
1430 id
= get_conf_byte(d
, where
+ PCI_CAP_LIST_ID
);
1431 next
= get_conf_byte(d
, where
+ PCI_CAP_LIST_NEXT
) & ~3;
1432 cap
= get_conf_word(d
, where
+ PCI_CAP_FLAGS
);
1433 printf("[%02x] ", where
);
1434 if (been_there
[where
]++)
1436 printf("<chain looped>\n");
1441 printf("<chain broken>\n");
1447 cap_pm(d
, where
, cap
);
1449 case PCI_CAP_ID_AGP
:
1450 cap_agp(d
, where
, cap
);
1452 case PCI_CAP_ID_VPD
:
1455 case PCI_CAP_ID_SLOTID
:
1458 case PCI_CAP_ID_MSI
:
1459 cap_msi(d
, where
, cap
);
1461 case PCI_CAP_ID_CHSWP
:
1462 printf("CompactPCI hot-swap <?>\n");
1464 case PCI_CAP_ID_PCIX
:
1466 can_have_ext_caps
= 1;
1469 cap_ht(d
, where
, cap
);
1471 case PCI_CAP_ID_VNDR
:
1472 show_vendor_caps(d
, where
, cap
);
1474 case PCI_CAP_ID_DBG
:
1475 cap_debug_port(cap
);
1477 case PCI_CAP_ID_CCRC
:
1478 printf("CompactPCI central resource control <?>\n");
1480 case PCI_CAP_ID_HOTPLUG
:
1481 printf("Hot-plug capable\n");
1483 case PCI_CAP_ID_SSVID
:
1484 cap_ssvid(d
, where
);
1486 case PCI_CAP_ID_AGP3
:
1487 printf("AGP3 <?>\n");
1489 case PCI_CAP_ID_SECURE
:
1490 printf("Secure device <?>\n");
1492 case PCI_CAP_ID_EXP
:
1493 cap_express(d
, where
, cap
);
1494 can_have_ext_caps
= 1;
1496 case PCI_CAP_ID_MSIX
:
1497 cap_msix(d
, where
, cap
);
1499 case PCI_CAP_ID_SATA
:
1500 cap_sata_hba(d
, where
, cap
);
1506 cap_ea(d
, where
, cap
);
1509 printf("#%02x [%04x]\n", id
, cap
);
1514 if (can_have_ext_caps
)