2 * The PCI Utilities -- Show Extended Capabilities
4 * Copyright (c) 1997--2020 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 cap_tph(struct device
*d
, int where
)
18 printf("Transaction Processing Hints\n");
22 if (!config_fetch(d
, where
+ PCI_TPH_CAPABILITIES
, 4))
25 tph_cap
= get_conf_long(d
, where
+ PCI_TPH_CAPABILITIES
);
27 if (tph_cap
& PCI_TPH_INTVEC_SUP
)
28 printf("\t\tInterrupt vector mode supported\n");
29 if (tph_cap
& PCI_TPH_DEV_SUP
)
30 printf("\t\tDevice specific mode supported\n");
31 if (tph_cap
& PCI_TPH_EXT_REQ_SUP
)
32 printf("\t\tExtended requester support\n");
34 switch (tph_cap
& PCI_TPH_ST_LOC_MASK
) {
36 printf("\t\tNo steering table available\n");
39 printf("\t\tSteering table in TPH capability structure\n");
42 printf("\t\tSteering table in MSI-X table\n");
45 printf("\t\tReserved steering table location\n");
51 cap_ltr_scale(u8 scale
)
53 return 1 << (scale
* 5);
57 cap_ltr(struct device
*d
, int where
)
61 printf("Latency Tolerance Reporting\n");
65 if (!config_fetch(d
, where
+ PCI_LTR_MAX_SNOOP
, 4))
68 snoop
= get_conf_word(d
, where
+ PCI_LTR_MAX_SNOOP
);
69 scale
= cap_ltr_scale((snoop
>> PCI_LTR_SCALE_SHIFT
) & PCI_LTR_SCALE_MASK
);
70 printf("\t\tMax snoop latency: %lldns\n",
71 ((unsigned long long)snoop
& PCI_LTR_VALUE_MASK
) * scale
);
73 nosnoop
= get_conf_word(d
, where
+ PCI_LTR_MAX_NOSNOOP
);
74 scale
= cap_ltr_scale((nosnoop
>> PCI_LTR_SCALE_SHIFT
) & PCI_LTR_SCALE_MASK
);
75 printf("\t\tMax no snoop latency: %lldns\n",
76 ((unsigned long long)nosnoop
& PCI_LTR_VALUE_MASK
) * scale
);
80 cap_sec(struct device
*d
, int where
)
82 u32 ctrl3
, lane_err_stat
;
84 printf("Secondary PCI Express\n");
88 if (!config_fetch(d
, where
+ PCI_SEC_LNKCTL3
, 12))
91 ctrl3
= get_conf_word(d
, where
+ PCI_SEC_LNKCTL3
);
92 printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
93 FLAG(ctrl3
, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN
),
94 FLAG(ctrl3
, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU
));
96 lane_err_stat
= get_conf_word(d
, where
+ PCI_SEC_LANE_ERR
);
97 printf("\t\tLaneErrStat: ");
100 printf("LaneErr at lane:");
101 for (lane
= 0; lane_err_stat
; lane_err_stat
>>= 1, lane
+= 1)
102 if (BITS(lane_err_stat
, 0, 1))
111 cap_dsn(struct device
*d
, int where
)
114 if (!config_fetch(d
, where
+ 4, 8))
116 t1
= get_conf_long(d
, where
+ 4);
117 t2
= get_conf_long(d
, where
+ 8);
118 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
119 t2
>> 24, (t2
>> 16) & 0xff, (t2
>> 8) & 0xff, t2
& 0xff,
120 t1
>> 24, (t1
>> 16) & 0xff, (t1
>> 8) & 0xff, t1
& 0xff);
124 cap_aer(struct device
*d
, int where
, int type
)
126 u32 l
, l0
, l1
, l2
, l3
;
129 printf("Advanced Error Reporting\n");
133 if (!config_fetch(d
, where
+ PCI_ERR_UNCOR_STATUS
, 40))
136 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_STATUS
);
137 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
138 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
139 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
140 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
141 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
142 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
143 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_MASK
);
144 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
145 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
146 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
147 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
148 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
149 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
150 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_SEVER
);
151 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
152 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
153 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
154 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
155 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
156 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
157 l
= get_conf_long(d
, where
+ PCI_ERR_COR_STATUS
);
158 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
159 FLAG(l
, PCI_ERR_COR_RCVR
), FLAG(l
, PCI_ERR_COR_BAD_TLP
), FLAG(l
, PCI_ERR_COR_BAD_DLLP
),
160 FLAG(l
, PCI_ERR_COR_REP_ROLL
), FLAG(l
, PCI_ERR_COR_REP_TIMER
), FLAG(l
, PCI_ERR_COR_REP_ANFE
));
161 l
= get_conf_long(d
, where
+ PCI_ERR_COR_MASK
);
162 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
163 FLAG(l
, PCI_ERR_COR_RCVR
), FLAG(l
, PCI_ERR_COR_BAD_TLP
), FLAG(l
, PCI_ERR_COR_BAD_DLLP
),
164 FLAG(l
, PCI_ERR_COR_REP_ROLL
), FLAG(l
, PCI_ERR_COR_REP_TIMER
), FLAG(l
, PCI_ERR_COR_REP_ANFE
));
165 l
= get_conf_long(d
, where
+ PCI_ERR_CAP
);
166 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
167 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
168 PCI_ERR_CAP_FEP(l
), FLAG(l
, PCI_ERR_CAP_ECRC_GENC
), FLAG(l
, PCI_ERR_CAP_ECRC_GENE
),
169 FLAG(l
, PCI_ERR_CAP_ECRC_CHKC
), FLAG(l
, PCI_ERR_CAP_ECRC_CHKE
),
170 FLAG(l
, PCI_ERR_CAP_MULT_HDRC
), FLAG(l
, PCI_ERR_CAP_MULT_HDRE
),
171 FLAG(l
, PCI_ERR_CAP_TLP_PFX
), FLAG(l
, PCI_ERR_CAP_HDR_LOG
));
173 l0
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
);
174 l1
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 4);
175 l2
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 8);
176 l3
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 12);
177 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0
, l1
, l2
, l3
);
179 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_ROOT_EC
)
181 if (!config_fetch(d
, where
+ PCI_ERR_ROOT_COMMAND
, 12))
184 l
= get_conf_long(d
, where
+ PCI_ERR_ROOT_COMMAND
);
185 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
186 FLAG(l
, PCI_ERR_ROOT_CMD_COR_EN
),
187 FLAG(l
, PCI_ERR_ROOT_CMD_NONFATAL_EN
),
188 FLAG(l
, PCI_ERR_ROOT_CMD_FATAL_EN
));
190 l
= get_conf_long(d
, where
+ PCI_ERR_ROOT_STATUS
);
191 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
192 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
193 FLAG(l
, PCI_ERR_ROOT_COR_RCV
),
194 FLAG(l
, PCI_ERR_ROOT_MULTI_COR_RCV
),
195 FLAG(l
, PCI_ERR_ROOT_UNCOR_RCV
),
196 FLAG(l
, PCI_ERR_ROOT_MULTI_UNCOR_RCV
),
197 FLAG(l
, PCI_ERR_ROOT_FIRST_FATAL
),
198 FLAG(l
, PCI_ERR_ROOT_NONFATAL_RCV
),
199 FLAG(l
, PCI_ERR_ROOT_FATAL_RCV
),
202 w
= get_conf_word(d
, where
+ PCI_ERR_ROOT_COR_SRC
);
203 printf("\t\tErrorSrc: ERR_COR: %04x ", w
);
205 w
= get_conf_word(d
, where
+ PCI_ERR_ROOT_SRC
);
206 printf("ERR_FATAL/NONFATAL: %04x\n", w
);
210 static void cap_dpc(struct device
*d
, int where
)
214 printf("Downstream Port Containment\n");
218 if (!config_fetch(d
, where
+ PCI_DPC_CAP
, 8))
221 l
= get_conf_word(d
, where
+ PCI_DPC_CAP
);
222 printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
223 PCI_DPC_CAP_INT_MSG(l
), FLAG(l
, PCI_DPC_CAP_RP_EXT
), FLAG(l
, PCI_DPC_CAP_TLP_BLOCK
),
224 FLAG(l
, PCI_DPC_CAP_SW_TRIGGER
), PCI_DPC_CAP_RP_LOG(l
), FLAG(l
, PCI_DPC_CAP_DL_ACT_ERR
));
226 l
= get_conf_word(d
, where
+ PCI_DPC_CTL
);
227 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
228 PCI_DPC_CTL_TRIGGER(l
), FLAG(l
, PCI_DPC_CTL_CMPL
), FLAG(l
, PCI_DPC_CTL_INT
),
229 FLAG(l
, PCI_DPC_CTL_ERR_COR
), FLAG(l
, PCI_DPC_CTL_TLP
), FLAG(l
, PCI_DPC_CTL_SW_TRIGGER
),
230 FLAG(l
, PCI_DPC_CTL_DL_ACTIVE
));
232 l
= get_conf_word(d
, where
+ PCI_DPC_STATUS
);
233 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
234 FLAG(l
, PCI_DPC_STS_TRIGGER
), PCI_DPC_STS_REASON(l
), FLAG(l
, PCI_DPC_STS_INT
),
235 FLAG(l
, PCI_DPC_STS_RP_BUSY
), PCI_DPC_STS_TRIGGER_EXT(l
), PCI_DPC_STS_PIO_FEP(l
));
237 l
= get_conf_word(d
, where
+ PCI_DPC_SOURCE
);
238 printf("\t\tSource:\t%04x\n", l
);
242 cap_acs(struct device
*d
, int where
)
246 printf("Access Control Services\n");
250 if (!config_fetch(d
, where
+ PCI_ACS_CAP
, 4))
253 w
= get_conf_word(d
, where
+ PCI_ACS_CAP
);
254 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
256 FLAG(w
, PCI_ACS_CAP_VALID
), FLAG(w
, PCI_ACS_CAP_BLOCK
), FLAG(w
, PCI_ACS_CAP_REQ_RED
),
257 FLAG(w
, PCI_ACS_CAP_CMPLT_RED
), FLAG(w
, PCI_ACS_CAP_FORWARD
), FLAG(w
, PCI_ACS_CAP_EGRESS
),
258 FLAG(w
, PCI_ACS_CAP_TRANS
));
259 w
= get_conf_word(d
, where
+ PCI_ACS_CTRL
);
260 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
262 FLAG(w
, PCI_ACS_CTRL_VALID
), FLAG(w
, PCI_ACS_CTRL_BLOCK
), FLAG(w
, PCI_ACS_CTRL_REQ_RED
),
263 FLAG(w
, PCI_ACS_CTRL_CMPLT_RED
), FLAG(w
, PCI_ACS_CTRL_FORWARD
), FLAG(w
, PCI_ACS_CTRL_EGRESS
),
264 FLAG(w
, PCI_ACS_CTRL_TRANS
));
268 cap_ari(struct device
*d
, int where
)
272 printf("Alternative Routing-ID Interpretation (ARI)\n");
276 if (!config_fetch(d
, where
+ PCI_ARI_CAP
, 4))
279 w
= get_conf_word(d
, where
+ PCI_ARI_CAP
);
280 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
281 FLAG(w
, PCI_ARI_CAP_MFVC
), FLAG(w
, PCI_ARI_CAP_ACS
),
283 w
= get_conf_word(d
, where
+ PCI_ARI_CTRL
);
284 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
285 FLAG(w
, PCI_ARI_CTRL_MFVC
), FLAG(w
, PCI_ARI_CTRL_ACS
),
290 cap_ats(struct device
*d
, int where
)
294 printf("Address Translation Service (ATS)\n");
298 if (!config_fetch(d
, where
+ PCI_ATS_CAP
, 4))
301 w
= get_conf_word(d
, where
+ PCI_ATS_CAP
);
302 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w
));
303 w
= get_conf_word(d
, where
+ PCI_ATS_CTRL
);
304 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
305 FLAG(w
, PCI_ATS_CTRL_ENABLE
), PCI_ATS_CTRL_STU(w
));
309 cap_pri(struct device
*d
, int where
)
314 printf("Page Request Interface (PRI)\n");
318 if (!config_fetch(d
, where
+ PCI_PRI_CTRL
, 0xc))
321 w
= get_conf_word(d
, where
+ PCI_PRI_CTRL
);
322 printf("\t\tPRICtl: Enable%c Reset%c\n",
323 FLAG(w
, PCI_PRI_CTRL_ENABLE
), FLAG(w
, PCI_PRI_CTRL_RESET
));
324 w
= get_conf_word(d
, where
+ PCI_PRI_STATUS
);
325 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
326 FLAG(w
, PCI_PRI_STATUS_RF
), FLAG(w
, PCI_PRI_STATUS_UPRGI
),
327 FLAG(w
, PCI_PRI_STATUS_STOPPED
));
328 l
= get_conf_long(d
, where
+ PCI_PRI_MAX_REQ
);
329 printf("\t\tPage Request Capacity: %08x, ", l
);
330 l
= get_conf_long(d
, where
+ PCI_PRI_ALLOC_REQ
);
331 printf("Page Request Allocation: %08x\n", l
);
335 cap_pasid(struct device
*d
, int where
)
339 printf("Process Address Space ID (PASID)\n");
343 if (!config_fetch(d
, where
+ PCI_PASID_CAP
, 4))
346 w
= get_conf_word(d
, where
+ PCI_PASID_CAP
);
347 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
348 FLAG(w
, PCI_PASID_CAP_EXEC
), FLAG(w
, PCI_PASID_CAP_PRIV
),
349 PCI_PASID_CAP_WIDTH(w
));
350 w
= get_conf_word(d
, where
+ PCI_PASID_CTRL
);
351 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
352 FLAG(w
, PCI_PASID_CTRL_ENABLE
), FLAG(w
, PCI_PASID_CTRL_EXEC
),
353 FLAG(w
, PCI_PASID_CTRL_PRIV
));
357 cap_sriov(struct device
*d
, int where
)
364 printf("Single Root I/O Virtualization (SR-IOV)\n");
368 if (!config_fetch(d
, where
+ PCI_IOV_CAP
, 0x3c))
371 l
= get_conf_long(d
, where
+ PCI_IOV_CAP
);
372 printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
373 FLAG(l
, PCI_IOV_CAP_VFM
), PCI_IOV_CAP_IMN(l
));
374 w
= get_conf_word(d
, where
+ PCI_IOV_CTRL
);
375 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
376 FLAG(w
, PCI_IOV_CTRL_VFE
), FLAG(w
, PCI_IOV_CTRL_VFME
),
377 FLAG(w
, PCI_IOV_CTRL_VFMIE
), FLAG(w
, PCI_IOV_CTRL_MSE
),
378 FLAG(w
, PCI_IOV_CTRL_ARI
));
379 w
= get_conf_word(d
, where
+ PCI_IOV_STATUS
);
380 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w
, PCI_IOV_STATUS_MS
));
381 w
= get_conf_word(d
, where
+ PCI_IOV_INITIALVF
);
382 printf("\t\tInitial VFs: %d, ", w
);
383 w
= get_conf_word(d
, where
+ PCI_IOV_TOTALVF
);
384 printf("Total VFs: %d, ", w
);
385 w
= get_conf_word(d
, where
+ PCI_IOV_NUMVF
);
386 printf("Number of VFs: %d, ", w
);
387 b
= get_conf_byte(d
, where
+ PCI_IOV_FDL
);
388 printf("Function Dependency Link: %02x\n", b
);
389 w
= get_conf_word(d
, where
+ PCI_IOV_OFFSET
);
390 printf("\t\tVF offset: %d, ", w
);
391 w
= get_conf_word(d
, where
+ PCI_IOV_STRIDE
);
392 printf("stride: %d, ", w
);
393 w
= get_conf_word(d
, where
+ PCI_IOV_DID
);
394 printf("Device ID: %04x\n", w
);
395 l
= get_conf_long(d
, where
+ PCI_IOV_SUPPS
);
396 printf("\t\tSupported Page Size: %08x, ", l
);
397 l
= get_conf_long(d
, where
+ PCI_IOV_SYSPS
);
398 printf("System Page Size: %08x\n", l
);
400 for (i
=0; i
< PCI_IOV_NUM_BAR
; i
++)
405 l
= get_conf_long(d
, where
+ PCI_IOV_BAR_BASE
+ 4*i
);
410 printf("\t\tRegion %d: Memory at ", i
);
411 addr
= l
& PCI_ADDR_MEM_MASK
;
412 type
= l
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
413 if (type
== PCI_BASE_ADDRESS_MEM_TYPE_64
)
416 h
= get_conf_long(d
, where
+ PCI_IOV_BAR_BASE
+ (i
*4));
419 printf("%08x (%s-bit, %sprefetchable)\n",
421 (type
== PCI_BASE_ADDRESS_MEM_TYPE_32
) ? "32" : "64",
422 (l
& PCI_BASE_ADDRESS_MEM_PREFETCH
) ? "" : "non-");
425 l
= get_conf_long(d
, where
+ PCI_IOV_MSAO
);
426 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l
),
431 cap_multicast(struct device
*d
, int where
, int type
)
437 printf("Multicast\n");
441 if (!config_fetch(d
, where
+ PCI_MCAST_CAP
, 0x30))
444 w
= get_conf_word(d
, where
+ PCI_MCAST_CAP
);
445 printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w
) + 1);
446 if (type
== PCI_EXP_TYPE_ENDPOINT
|| type
== PCI_EXP_TYPE_ROOT_INT_EP
)
447 printf(", WindowSz %d (%d bytes)",
448 PCI_MCAST_CAP_WIN_SIZE(w
), 1 << PCI_MCAST_CAP_WIN_SIZE(w
));
449 if (type
== PCI_EXP_TYPE_ROOT_PORT
||
450 type
== PCI_EXP_TYPE_UPSTREAM
|| type
== PCI_EXP_TYPE_DOWNSTREAM
)
451 printf(", ECRCRegen%c\n", FLAG(w
, PCI_MCAST_CAP_ECRC
));
452 w
= get_conf_word(d
, where
+ PCI_MCAST_CTRL
);
453 printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
454 PCI_MCAST_CTRL_NUM_GROUP(w
) + 1, FLAG(w
, PCI_MCAST_CTRL_ENABLE
));
455 bar
= get_conf_long(d
, where
+ PCI_MCAST_BAR
);
456 l
= get_conf_long(d
, where
+ PCI_MCAST_BAR
+ 4);
457 bar
|= (u64
) l
<< 32;
458 printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X
"\n",
459 PCI_MCAST_BAR_INDEX_POS(bar
), bar
& PCI_MCAST_BAR_MASK
);
460 rcv
= get_conf_long(d
, where
+ PCI_MCAST_RCV
);
461 l
= get_conf_long(d
, where
+ PCI_MCAST_RCV
+ 4);
462 rcv
|= (u64
) l
<< 32;
463 printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X
"\n", rcv
);
464 block
= get_conf_long(d
, where
+ PCI_MCAST_BLOCK
);
465 l
= get_conf_long(d
, where
+ PCI_MCAST_BLOCK
+ 4);
466 block
|= (u64
) l
<< 32;
467 printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X
"\n", block
);
468 block
= get_conf_long(d
, where
+ PCI_MCAST_BLOCK_UNTRANS
);
469 l
= get_conf_long(d
, where
+ PCI_MCAST_BLOCK_UNTRANS
+ 4);
470 block
|= (u64
) l
<< 32;
471 printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X
"\n", block
);
473 if (type
== PCI_EXP_TYPE_ENDPOINT
|| type
== PCI_EXP_TYPE_ROOT_INT_EP
)
475 bar
= get_conf_long(d
, where
+ PCI_MCAST_OVL_BAR
);
476 l
= get_conf_long(d
, where
+ PCI_MCAST_OVL_BAR
+ 4);
477 bar
|= (u64
) l
<< 32;
478 printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar
));
479 if (PCI_MCAST_OVL_SIZE(bar
) >= 6)
480 printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar
));
482 printf("(disabled)");
483 printf(", BaseAddr %016" PCI_U64_FMT_X
"\n", bar
& PCI_MCAST_OVL_MASK
);
487 cap_vc(struct device
*d
, int where
)
494 static const char ref_clocks
[][6] = { "100ns" };
495 static const char arb_selects
[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
496 static const char vc_arb_selects
[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
499 printf("Virtual Channel\n");
503 if (!config_fetch(d
, where
+ 4, 0x1c - 4))
506 cr1
= get_conf_long(d
, where
+ PCI_VC_PORT_REG1
);
507 cr2
= get_conf_long(d
, where
+ PCI_VC_PORT_REG2
);
508 ctrl
= get_conf_word(d
, where
+ PCI_VC_PORT_CTRL
);
509 status
= get_conf_word(d
, where
+ PCI_VC_PORT_STATUS
);
511 evc_cnt
= BITS(cr1
, 0, 3);
512 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
514 TABLE(ref_clocks
, BITS(cr1
, 8, 2), buf
),
515 1 << BITS(cr1
, 10, 2));
519 if (arb_selects
[i
][0] != '?' || cr2
& (1 << i
))
520 printf("%c%s%c", (i
? ' ' : '\t'), arb_selects
[i
], FLAG(cr2
, 1 << i
));
521 arb_table_pos
= BITS(cr2
, 24, 8);
523 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects
, BITS(ctrl
, 1, 3), buf
));
524 printf("\t\tStatus:\tInProgress%c\n", FLAG(status
, 1));
528 arb_table_pos
= where
+ 16*arb_table_pos
;
529 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos
);
532 for (i
=0; i
<=evc_cnt
; i
++)
534 int pos
= where
+ PCI_VC_RES_CAP
+ 12*i
;
539 printf("\t\tVC%d:\t", i
);
540 if (!config_fetch(d
, pos
, 12))
542 printf("<unreadable>\n");
545 rcap
= get_conf_long(d
, pos
);
546 rctrl
= get_conf_long(d
, pos
+4);
547 rstatus
= get_conf_word(d
, pos
+10);
549 pat_pos
= BITS(rcap
, 24, 8);
550 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
552 BITS(rcap
, 16, 6) + 1,
553 FLAG(rcap
, 1 << 15));
555 printf("\t\t\tArb:");
557 if (vc_arb_selects
[j
][0] != '?' || rcap
& (1 << j
))
558 printf("%c%s%c", (j
? ' ' : '\t'), vc_arb_selects
[j
], FLAG(rcap
, 1 << j
));
560 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
561 FLAG(rctrl
, 1 << 31),
563 TABLE(vc_arb_selects
, BITS(rctrl
, 17, 3), buf
),
566 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
571 printf("\t\t\tPort Arbitration Table <?>\n");
576 cap_rclink(struct device
*d
, int where
)
581 static const char elt_types
[][9] = { "Config", "Egress", "Internal" };
584 printf("Root Complex Link\n");
588 if (!config_fetch(d
, where
+ 4, PCI_RCLINK_LINK1
- 4))
591 esd
= get_conf_long(d
, where
+ PCI_RCLINK_ESD
);
592 num_links
= BITS(esd
, 8, 8);
593 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
596 TABLE(elt_types
, BITS(esd
, 0, 8), buf
));
598 for (i
=0; i
<num_links
; i
++)
600 int pos
= where
+ PCI_RCLINK_LINK1
+ i
*PCI_RCLINK_LINK_SIZE
;
602 u32 addr_lo
, addr_hi
;
604 printf("\t\tLink%d:\t", i
);
605 if (!config_fetch(d
, pos
, PCI_RCLINK_LINK_SIZE
))
607 printf("<unreadable>\n");
610 desc
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_DESC
);
611 addr_lo
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_ADDR
);
612 addr_hi
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_ADDR
+ 4);
614 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
618 ((desc
& 2) ? "Config" : "MemMapped"),
626 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
627 BITS(addr_lo
, 20, n
),
628 BITS(addr_lo
, 15, 5),
629 BITS(addr_lo
, 12, 3),
633 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi
, addr_lo
);
638 cap_rcec(struct device
*d
, int where
)
640 printf("Root Complex Event Collector Endpoint Association\n");
644 if (!config_fetch(d
, where
, 12))
647 u32 hdr
= get_conf_long(d
, where
);
648 byte cap_ver
= PCI_RCEC_EP_CAP_VER(hdr
);
649 u32 bmap
= get_conf_long(d
, where
+ PCI_RCEC_RCIEP_BMAP
);
650 printf("\t\tRCiEPBitmap: ");
656 printf("RCiEP at Device(s):");
657 for (int dev
=0; dev
< 32; dev
++)
659 if (BITS(bmap
, dev
, 1))
662 printf("%s %u", (prevmatched
) ? "," : "", dev
);
670 printf("-%u", prevdev
);
676 printf("%s", (verbose
> 2) ? "00000000 [none]" : "[none]");
679 if (cap_ver
< PCI_RCEC_BUSN_REG_VER
)
682 u32 busn
= get_conf_long(d
, where
+ PCI_RCEC_BUSN_REG
);
683 u8 lastbusn
= BITS(busn
, 16, 8);
684 u8 nextbusn
= BITS(busn
, 8, 8);
686 if ((lastbusn
== 0x00) && (nextbusn
== 0xff))
687 printf("\t\tAssociatedBusNumbers: %s\n", (verbose
> 2) ? "ff-00 [none]" : "[none]");
689 printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn
, lastbusn
);
693 cap_dvsec_cxl(struct device
*d
, int where
)
701 if (!config_fetch(d
, where
+ PCI_CXL_CAP
, 12))
704 l
= get_conf_word(d
, where
+ PCI_CXL_CAP
);
705 printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
706 FLAG(l
, PCI_CXL_CAP_CACHE
), FLAG(l
, PCI_CXL_CAP_IO
), FLAG(l
, PCI_CXL_CAP_MEM
),
707 FLAG(l
, PCI_CXL_CAP_MEM_HWINIT
), PCI_CXL_CAP_HDM_CNT(l
), FLAG(l
, PCI_CXL_CAP_VIRAL
));
709 l
= get_conf_word(d
, where
+ PCI_CXL_CTRL
);
710 printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
711 FLAG(l
, PCI_CXL_CTRL_CACHE
), FLAG(l
, PCI_CXL_CTRL_IO
), FLAG(l
, PCI_CXL_CTRL_MEM
),
712 PCI_CXL_CTRL_CACHE_SF_COV(l
), PCI_CXL_CTRL_CACHE_SF_GRAN(l
), FLAG(l
, PCI_CXL_CTRL_CACHE_CLN
),
713 FLAG(l
, PCI_CXL_CTRL_VIRAL
));
715 l
= get_conf_word(d
, where
+ PCI_CXL_STATUS
);
716 printf("\t\tCXLSta:\tViral%c\n", FLAG(l
, PCI_CXL_STATUS_VIRAL
));
720 cap_dvsec(struct device
*d
, int where
)
722 printf("Designated Vendor-Specific: ");
723 if (!config_fetch(d
, where
+ PCI_DVSEC_HEADER1
, 8))
725 printf("<unreadable>\n");
729 u32 hdr
= get_conf_long(d
, where
+ PCI_DVSEC_HEADER1
);
730 u16 vendor
= BITS(hdr
, 0, 16);
731 byte rev
= BITS(hdr
, 16, 4);
732 u16 len
= BITS(hdr
, 20, 12);
734 u16 id
= get_conf_long(d
, where
+ PCI_DVSEC_HEADER2
);
736 printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor
, id
, rev
, len
);
737 if (vendor
== PCI_DVSEC_VENDOR_ID_CXL
&& id
== PCI_DVSEC_ID_CXL
&& len
>= 16)
738 cap_dvsec_cxl(d
, where
);
744 cap_evendor(struct device
*d
, int where
)
748 printf("Vendor Specific Information: ");
749 if (!config_fetch(d
, where
+ PCI_EVNDR_HEADER
, 4))
751 printf("<unreadable>\n");
755 hdr
= get_conf_long(d
, where
+ PCI_EVNDR_HEADER
);
756 printf("ID=%04x Rev=%d Len=%03x <?>\n",
762 static int l1pm_calc_pwron(int scale
, int value
)
777 cap_l1pm(struct device
*d
, int where
)
779 u32 l1_cap
, val
, scale
;
782 printf("L1 PM Substates\n");
787 if (!config_fetch(d
, where
+ PCI_L1PM_SUBSTAT_CAP
, 12))
789 printf("\t\t<unreadable>\n");
793 l1_cap
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CAP
);
794 printf("\t\tL1SubCap: ");
795 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
796 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_PM_L12
),
797 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_PM_L11
),
798 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_ASPM_L12
),
799 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_ASPM_L11
),
800 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP
));
802 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
804 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap
, 8, 8));
805 time
= l1pm_calc_pwron(BITS(l1_cap
, 16, 2), BITS(l1_cap
, 19, 5));
807 printf("PortTPowerOnTime=%dus\n", time
);
809 printf("PortTPowerOnTime=<error>\n");
812 val
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CTL1
);
813 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
814 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_PM_L12
),
815 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_PM_L11
),
816 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12
),
817 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11
));
819 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
821 printf("\t\t\t T_CommonMode=%dus", BITS(val
, 8, 8));
823 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
825 scale
= BITS(val
, 29, 3);
827 printf(" LTR1.2_Threshold=<error>");
829 printf(" LTR1.2_Threshold=%lldns", BITS(val
, 16, 10) * (unsigned long long) cap_ltr_scale(scale
));
834 val
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CTL2
);
835 printf("\t\tL1SubCtl2:");
836 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
838 time
= l1pm_calc_pwron(BITS(val
, 0, 2), BITS(val
, 3, 5));
840 printf(" T_PwrOn=%dus", time
);
842 printf(" T_PwrOn=<error>");
848 cap_ptm(struct device
*d
, int where
)
853 printf("Precision Time Measurement\n");
858 if (!config_fetch(d
, where
+ 4, 8))
860 printf("\t\t<unreadable>\n");
864 buff
= get_conf_long(d
, where
+ 4);
865 printf("\t\tPTMCap: ");
866 printf("Requester:%c Responder:%c Root:%c\n",
871 clock
= BITS(buff
, 8, 8);
872 printf("\t\tPTMClockGranularity: ");
876 printf("Unimplemented\n");
879 printf("Greater than 254ns\n");
882 printf("%huns\n", clock
);
885 buff
= get_conf_long(d
, where
+ 8);
886 printf("\t\tPTMControl: ");
887 printf("Enabled:%c RootSelected:%c\n",
891 clock
= BITS(buff
, 8, 8);
892 printf("\t\tPTMEffectiveGranularity: ");
899 printf("Greater than 254ns\n");
902 printf("%huns\n", clock
);
907 print_rebar_range_size(int ld2_size
)
909 // This function prints the input as a power-of-2 size value
910 // It is biased with 1MB = 0, ...
911 // Maximum resizable BAR value supported is 2^63 bytes = 43
912 // for the extended resizable BAR capability definition
913 // (otherwise it would stop at 2^28)
915 if (ld2_size
>= 0 && ld2_size
< 10)
916 printf(" %dMB", (1 << ld2_size
));
917 else if (ld2_size
>= 10 && ld2_size
< 20)
918 printf(" %dGB", (1 << (ld2_size
-10)));
919 else if (ld2_size
>= 20 && ld2_size
< 30)
920 printf(" %dTB", (1 << (ld2_size
-20)));
921 else if (ld2_size
>= 30 && ld2_size
< 40)
922 printf(" %dPB", (1 << (ld2_size
-30)));
923 else if (ld2_size
>= 40 && ld2_size
< 44)
924 printf(" %dEB", (1 << (ld2_size
-40)));
926 printf(" <unknown>");
930 cap_rebar(struct device
*d
, int where
, int virtual)
932 u32 sizes_buffer
, control_buffer
, ext_sizes
, current_size
;
933 u16 bar_index
, barcount
, i
;
934 // If the structure exists, at least one bar is defined
937 printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical");
942 // Go through all defined BAR definitions of the caps, at minimum 1
943 // (loop also terminates if num_bars read from caps is > 6)
944 for (barcount
= 0; barcount
< num_bars
; barcount
++)
948 // Get the next BAR configuration
949 if (!config_fetch(d
, where
, 8))
951 printf("\t\t<unreadable>\n");
955 sizes_buffer
= get_conf_long(d
, where
) >> 4;
957 control_buffer
= get_conf_long(d
, where
);
959 bar_index
= BITS(control_buffer
, 0, 3);
960 current_size
= BITS(control_buffer
, 8, 6);
961 ext_sizes
= BITS(control_buffer
, 16, 16);
965 // Only index 0 controlreg has the num_bar count definition
966 num_bars
= BITS(control_buffer
, 5, 3);
967 if (num_bars
< 1 || num_bars
> 6)
969 printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars
);
974 // Resizable BAR list entry have an arbitrary index and current size
975 printf("\t\tBAR %d: current size:", bar_index
);
976 print_rebar_range_size(current_size
);
978 if (sizes_buffer
|| ext_sizes
)
980 printf(", supported:");
983 if (sizes_buffer
& (1U << i
))
984 print_rebar_range_size(i
);
987 if (ext_sizes
& (1U << i
))
988 print_rebar_range_size(i
+ 28);
996 show_ext_caps(struct device
*d
, int type
)
999 char been_there
[0x1000];
1000 memset(been_there
, 0, 0x1000);
1006 if (!config_fetch(d
, where
, 4))
1008 header
= get_conf_long(d
, where
);
1011 id
= header
& 0xffff;
1012 version
= (header
>> 16) & 0xf;
1013 printf("\tCapabilities: [%03x", where
);
1015 printf(" v%d", version
);
1017 if (been_there
[where
]++)
1019 printf("<chain looped>\n");
1024 case PCI_EXT_CAP_ID_NULL
:
1027 case PCI_EXT_CAP_ID_AER
:
1028 cap_aer(d
, where
, type
);
1030 case PCI_EXT_CAP_ID_DPC
:
1033 case PCI_EXT_CAP_ID_VC
:
1034 case PCI_EXT_CAP_ID_VC2
:
1037 case PCI_EXT_CAP_ID_DSN
:
1040 case PCI_EXT_CAP_ID_PB
:
1041 printf("Power Budgeting <?>\n");
1043 case PCI_EXT_CAP_ID_RCLINK
:
1044 cap_rclink(d
, where
);
1046 case PCI_EXT_CAP_ID_RCILINK
:
1047 printf("Root Complex Internal Link <?>\n");
1049 case PCI_EXT_CAP_ID_RCEC
:
1052 case PCI_EXT_CAP_ID_MFVC
:
1053 printf("Multi-Function Virtual Channel <?>\n");
1055 case PCI_EXT_CAP_ID_RCRB
:
1056 printf("Root Complex Register Block <?>\n");
1058 case PCI_EXT_CAP_ID_VNDR
:
1059 cap_evendor(d
, where
);
1061 case PCI_EXT_CAP_ID_ACS
:
1064 case PCI_EXT_CAP_ID_ARI
:
1067 case PCI_EXT_CAP_ID_ATS
:
1070 case PCI_EXT_CAP_ID_SRIOV
:
1071 cap_sriov(d
, where
);
1073 case PCI_EXT_CAP_ID_MRIOV
:
1074 printf("Multi-Root I/O Virtualization <?>\n");
1076 case PCI_EXT_CAP_ID_MCAST
:
1077 cap_multicast(d
, where
, type
);
1079 case PCI_EXT_CAP_ID_PRI
:
1082 case PCI_EXT_CAP_ID_REBAR
:
1083 cap_rebar(d
, where
, 0);
1085 case PCI_EXT_CAP_ID_DPA
:
1086 printf("Dynamic Power Allocation <?>\n");
1088 case PCI_EXT_CAP_ID_TPH
:
1091 case PCI_EXT_CAP_ID_LTR
:
1094 case PCI_EXT_CAP_ID_SECPCI
:
1097 case PCI_EXT_CAP_ID_PMUX
:
1098 printf("Protocol Multiplexing <?>\n");
1100 case PCI_EXT_CAP_ID_PASID
:
1101 cap_pasid(d
, where
);
1103 case PCI_EXT_CAP_ID_LNR
:
1104 printf("LN Requester <?>\n");
1106 case PCI_EXT_CAP_ID_L1PM
:
1109 case PCI_EXT_CAP_ID_PTM
:
1112 case PCI_EXT_CAP_ID_M_PCIE
:
1113 printf("PCI Express over M_PHY <?>\n");
1115 case PCI_EXT_CAP_ID_FRS
:
1116 printf("FRS Queueing <?>\n");
1118 case PCI_EXT_CAP_ID_RTR
:
1119 printf("Readiness Time Reporting <?>\n");
1121 case PCI_EXT_CAP_ID_DVSEC
:
1122 cap_dvsec(d
, where
);
1124 case PCI_EXT_CAP_ID_VF_REBAR
:
1125 cap_rebar(d
, where
, 1);
1127 case PCI_EXT_CAP_ID_DLNK
:
1128 printf("Data Link Feature <?>\n");
1130 case PCI_EXT_CAP_ID_16GT
:
1131 printf("Physical Layer 16.0 GT/s <?>\n");
1133 case PCI_EXT_CAP_ID_LMR
:
1134 printf("Lane Margining at the Receiver <?>\n");
1136 case PCI_EXT_CAP_ID_HIER_ID
:
1137 printf("Hierarchy ID <?>\n");
1139 case PCI_EXT_CAP_ID_NPEM
:
1140 printf("Native PCIe Enclosure Management <?>\n");
1143 printf("Extended Capability ID %#02x\n", id
);
1146 where
= (header
>> 20) & ~3;