2 * The PCI Utilities -- Show Extended Capabilities
4 * Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
8 * SPDX-License-Identifier: GPL-2.0-or-later
17 cap_tph(struct device
*d
, int where
)
20 printf("Transaction Processing Hints\n");
24 if (!config_fetch(d
, where
+ PCI_TPH_CAPABILITIES
, 4))
27 tph_cap
= get_conf_long(d
, where
+ PCI_TPH_CAPABILITIES
);
29 if (tph_cap
& PCI_TPH_INTVEC_SUP
)
30 printf("\t\tInterrupt vector mode supported\n");
31 if (tph_cap
& PCI_TPH_DEV_SUP
)
32 printf("\t\tDevice specific mode supported\n");
33 if (tph_cap
& PCI_TPH_EXT_REQ_SUP
)
34 printf("\t\tExtended requester support\n");
36 switch (tph_cap
& PCI_TPH_ST_LOC_MASK
) {
38 printf("\t\tNo steering table available\n");
41 printf("\t\tSteering table in TPH capability structure\n");
44 printf("\t\tSteering table in MSI-X table\n");
47 printf("\t\tReserved steering table location\n");
53 cap_ltr_scale(u8 scale
)
55 return 1 << (scale
* 5);
59 cap_ltr(struct device
*d
, int where
)
63 printf("Latency Tolerance Reporting\n");
67 if (!config_fetch(d
, where
+ PCI_LTR_MAX_SNOOP
, 4))
70 snoop
= get_conf_word(d
, where
+ PCI_LTR_MAX_SNOOP
);
71 scale
= cap_ltr_scale((snoop
>> PCI_LTR_SCALE_SHIFT
) & PCI_LTR_SCALE_MASK
);
72 printf("\t\tMax snoop latency: %" PCI_U64_FMT_U
"ns\n",
73 ((u64
)snoop
& PCI_LTR_VALUE_MASK
) * scale
);
75 nosnoop
= get_conf_word(d
, where
+ PCI_LTR_MAX_NOSNOOP
);
76 scale
= cap_ltr_scale((nosnoop
>> PCI_LTR_SCALE_SHIFT
) & PCI_LTR_SCALE_MASK
);
77 printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U
"ns\n",
78 ((u64
)nosnoop
& PCI_LTR_VALUE_MASK
) * scale
);
82 cap_sec(struct device
*d
, int where
)
84 u32 ctrl3
, lane_err_stat
;
86 printf("Secondary PCI Express\n");
90 if (!config_fetch(d
, where
+ PCI_SEC_LNKCTL3
, 12))
93 ctrl3
= get_conf_word(d
, where
+ PCI_SEC_LNKCTL3
);
94 printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
95 FLAG(ctrl3
, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN
),
96 FLAG(ctrl3
, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU
));
98 lane_err_stat
= get_conf_word(d
, where
+ PCI_SEC_LANE_ERR
);
99 printf("\t\tLaneErrStat: ");
102 printf("LaneErr at lane:");
103 for (lane
= 0; lane_err_stat
; lane_err_stat
>>= 1, lane
+= 1)
104 if (BITS(lane_err_stat
, 0, 1))
113 cap_dsn(struct device
*d
, int where
)
116 if (!config_fetch(d
, where
+ 4, 8))
118 t1
= get_conf_long(d
, where
+ 4);
119 t2
= get_conf_long(d
, where
+ 8);
120 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
121 t2
>> 24, (t2
>> 16) & 0xff, (t2
>> 8) & 0xff, t2
& 0xff,
122 t1
>> 24, (t1
>> 16) & 0xff, (t1
>> 8) & 0xff, t1
& 0xff);
126 cap_aer(struct device
*d
, int where
, int type
)
128 u32 l
, l0
, l1
, l2
, l3
;
131 printf("Advanced Error Reporting\n");
135 if (!config_fetch(d
, where
+ PCI_ERR_UNCOR_STATUS
, 40))
138 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_STATUS
);
139 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
140 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
141 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
142 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
143 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
144 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
145 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_MASK
);
146 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
147 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
148 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
149 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
150 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
151 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
152 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_SEVER
);
153 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
154 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
155 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
156 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
157 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
158 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
159 l
= get_conf_long(d
, where
+ PCI_ERR_COR_STATUS
);
160 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
161 FLAG(l
, PCI_ERR_COR_RCVR
), FLAG(l
, PCI_ERR_COR_BAD_TLP
), FLAG(l
, PCI_ERR_COR_BAD_DLLP
),
162 FLAG(l
, PCI_ERR_COR_REP_ROLL
), FLAG(l
, PCI_ERR_COR_REP_TIMER
), FLAG(l
, PCI_ERR_COR_REP_ANFE
));
163 l
= get_conf_long(d
, where
+ PCI_ERR_COR_MASK
);
164 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
165 FLAG(l
, PCI_ERR_COR_RCVR
), FLAG(l
, PCI_ERR_COR_BAD_TLP
), FLAG(l
, PCI_ERR_COR_BAD_DLLP
),
166 FLAG(l
, PCI_ERR_COR_REP_ROLL
), FLAG(l
, PCI_ERR_COR_REP_TIMER
), FLAG(l
, PCI_ERR_COR_REP_ANFE
));
167 l
= get_conf_long(d
, where
+ PCI_ERR_CAP
);
168 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
169 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
170 PCI_ERR_CAP_FEP(l
), FLAG(l
, PCI_ERR_CAP_ECRC_GENC
), FLAG(l
, PCI_ERR_CAP_ECRC_GENE
),
171 FLAG(l
, PCI_ERR_CAP_ECRC_CHKC
), FLAG(l
, PCI_ERR_CAP_ECRC_CHKE
),
172 FLAG(l
, PCI_ERR_CAP_MULT_HDRC
), FLAG(l
, PCI_ERR_CAP_MULT_HDRE
),
173 FLAG(l
, PCI_ERR_CAP_TLP_PFX
), FLAG(l
, PCI_ERR_CAP_HDR_LOG
));
175 l0
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
);
176 l1
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 4);
177 l2
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 8);
178 l3
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 12);
179 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0
, l1
, l2
, l3
);
181 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_ROOT_EC
)
183 if (!config_fetch(d
, where
+ PCI_ERR_ROOT_COMMAND
, 12))
186 l
= get_conf_long(d
, where
+ PCI_ERR_ROOT_COMMAND
);
187 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
188 FLAG(l
, PCI_ERR_ROOT_CMD_COR_EN
),
189 FLAG(l
, PCI_ERR_ROOT_CMD_NONFATAL_EN
),
190 FLAG(l
, PCI_ERR_ROOT_CMD_FATAL_EN
));
192 l
= get_conf_long(d
, where
+ PCI_ERR_ROOT_STATUS
);
193 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
194 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d\n",
195 FLAG(l
, PCI_ERR_ROOT_COR_RCV
),
196 FLAG(l
, PCI_ERR_ROOT_MULTI_COR_RCV
),
197 FLAG(l
, PCI_ERR_ROOT_UNCOR_RCV
),
198 FLAG(l
, PCI_ERR_ROOT_MULTI_UNCOR_RCV
),
199 FLAG(l
, PCI_ERR_ROOT_FIRST_FATAL
),
200 FLAG(l
, PCI_ERR_ROOT_NONFATAL_RCV
),
201 FLAG(l
, PCI_ERR_ROOT_FATAL_RCV
),
204 w
= get_conf_word(d
, where
+ PCI_ERR_ROOT_COR_SRC
);
205 printf("\t\tErrorSrc: ERR_COR: %04x ", w
);
207 w
= get_conf_word(d
, where
+ PCI_ERR_ROOT_SRC
);
208 printf("ERR_FATAL/NONFATAL: %04x\n", w
);
212 static void cap_dpc(struct device
*d
, int where
)
216 printf("Downstream Port Containment\n");
220 if (!config_fetch(d
, where
+ PCI_DPC_CAP
, 8))
223 l
= get_conf_word(d
, where
+ PCI_DPC_CAP
);
224 printf("\t\tDpcCap:\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
225 PCI_DPC_CAP_INT_MSG(l
), FLAG(l
, PCI_DPC_CAP_RP_EXT
), FLAG(l
, PCI_DPC_CAP_TLP_BLOCK
),
226 FLAG(l
, PCI_DPC_CAP_SW_TRIGGER
), PCI_DPC_CAP_RP_LOG(l
), FLAG(l
, PCI_DPC_CAP_DL_ACT_ERR
));
228 l
= get_conf_word(d
, where
+ PCI_DPC_CTL
);
229 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
230 PCI_DPC_CTL_TRIGGER(l
), FLAG(l
, PCI_DPC_CTL_CMPL
), FLAG(l
, PCI_DPC_CTL_INT
),
231 FLAG(l
, PCI_DPC_CTL_ERR_COR
), FLAG(l
, PCI_DPC_CTL_TLP
), FLAG(l
, PCI_DPC_CTL_SW_TRIGGER
),
232 FLAG(l
, PCI_DPC_CTL_DL_ACTIVE
));
234 l
= get_conf_word(d
, where
+ PCI_DPC_STATUS
);
235 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
236 FLAG(l
, PCI_DPC_STS_TRIGGER
), PCI_DPC_STS_REASON(l
), FLAG(l
, PCI_DPC_STS_INT
),
237 FLAG(l
, PCI_DPC_STS_RP_BUSY
), PCI_DPC_STS_TRIGGER_EXT(l
), PCI_DPC_STS_PIO_FEP(l
));
239 l
= get_conf_word(d
, where
+ PCI_DPC_SOURCE
);
240 printf("\t\tSource:\t%04x\n", l
);
244 cap_acs(struct device
*d
, int where
)
248 printf("Access Control Services\n");
252 if (!config_fetch(d
, where
+ PCI_ACS_CAP
, 4))
255 w
= get_conf_word(d
, where
+ PCI_ACS_CAP
);
256 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
258 FLAG(w
, PCI_ACS_CAP_VALID
), FLAG(w
, PCI_ACS_CAP_BLOCK
), FLAG(w
, PCI_ACS_CAP_REQ_RED
),
259 FLAG(w
, PCI_ACS_CAP_CMPLT_RED
), FLAG(w
, PCI_ACS_CAP_FORWARD
), FLAG(w
, PCI_ACS_CAP_EGRESS
),
260 FLAG(w
, PCI_ACS_CAP_TRANS
));
261 w
= get_conf_word(d
, where
+ PCI_ACS_CTRL
);
262 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
264 FLAG(w
, PCI_ACS_CTRL_VALID
), FLAG(w
, PCI_ACS_CTRL_BLOCK
), FLAG(w
, PCI_ACS_CTRL_REQ_RED
),
265 FLAG(w
, PCI_ACS_CTRL_CMPLT_RED
), FLAG(w
, PCI_ACS_CTRL_FORWARD
), FLAG(w
, PCI_ACS_CTRL_EGRESS
),
266 FLAG(w
, PCI_ACS_CTRL_TRANS
));
270 cap_ari(struct device
*d
, int where
)
274 printf("Alternative Routing-ID Interpretation (ARI)\n");
278 if (!config_fetch(d
, where
+ PCI_ARI_CAP
, 4))
281 w
= get_conf_word(d
, where
+ PCI_ARI_CAP
);
282 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
283 FLAG(w
, PCI_ARI_CAP_MFVC
), FLAG(w
, PCI_ARI_CAP_ACS
),
285 w
= get_conf_word(d
, where
+ PCI_ARI_CTRL
);
286 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
287 FLAG(w
, PCI_ARI_CTRL_MFVC
), FLAG(w
, PCI_ARI_CTRL_ACS
),
292 cap_ats(struct device
*d
, int where
)
296 printf("Address Translation Service (ATS)\n");
300 if (!config_fetch(d
, where
+ PCI_ATS_CAP
, 4))
303 w
= get_conf_word(d
, where
+ PCI_ATS_CAP
);
304 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w
));
305 w
= get_conf_word(d
, where
+ PCI_ATS_CTRL
);
306 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
307 FLAG(w
, PCI_ATS_CTRL_ENABLE
), PCI_ATS_CTRL_STU(w
));
311 cap_pri(struct device
*d
, int where
)
316 printf("Page Request Interface (PRI)\n");
320 if (!config_fetch(d
, where
+ PCI_PRI_CTRL
, 0xc))
323 w
= get_conf_word(d
, where
+ PCI_PRI_CTRL
);
324 printf("\t\tPRICtl: Enable%c Reset%c\n",
325 FLAG(w
, PCI_PRI_CTRL_ENABLE
), FLAG(w
, PCI_PRI_CTRL_RESET
));
326 w
= get_conf_word(d
, where
+ PCI_PRI_STATUS
);
327 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c PASID%c\n",
328 FLAG(w
, PCI_PRI_STATUS_RF
), FLAG(w
, PCI_PRI_STATUS_UPRGI
),
329 FLAG(w
, PCI_PRI_STATUS_STOPPED
), FLAG(w
, PCI_PRI_STATUS_PASID
));
330 l
= get_conf_long(d
, where
+ PCI_PRI_MAX_REQ
);
331 printf("\t\tPage Request Capacity: %08x, ", l
);
332 l
= get_conf_long(d
, where
+ PCI_PRI_ALLOC_REQ
);
333 printf("Page Request Allocation: %08x\n", l
);
337 cap_pasid(struct device
*d
, int where
)
341 printf("Process Address Space ID (PASID)\n");
345 if (!config_fetch(d
, where
+ PCI_PASID_CAP
, 4))
348 w
= get_conf_word(d
, where
+ PCI_PASID_CAP
);
349 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
350 FLAG(w
, PCI_PASID_CAP_EXEC
), FLAG(w
, PCI_PASID_CAP_PRIV
),
351 PCI_PASID_CAP_WIDTH(w
));
352 w
= get_conf_word(d
, where
+ PCI_PASID_CTRL
);
353 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
354 FLAG(w
, PCI_PASID_CTRL_ENABLE
), FLAG(w
, PCI_PASID_CTRL_EXEC
),
355 FLAG(w
, PCI_PASID_CTRL_PRIV
));
359 cap_sriov(struct device
*d
, int where
)
366 printf("Single Root I/O Virtualization (SR-IOV)\n");
370 if (!config_fetch(d
, where
+ PCI_IOV_CAP
, 0x3c))
373 l
= get_conf_long(d
, where
+ PCI_IOV_CAP
);
374 printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c IntMsgNum %d\n",
375 FLAG(l
, PCI_IOV_CAP_VFM
), FLAG(l
, PCI_IOV_CAP_VF_10BIT_TAG_REQ
), PCI_IOV_CAP_IMN(l
));
376 w
= get_conf_word(d
, where
+ PCI_IOV_CTRL
);
377 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
378 FLAG(w
, PCI_IOV_CTRL_VFE
), FLAG(w
, PCI_IOV_CTRL_VFME
),
379 FLAG(w
, PCI_IOV_CTRL_VFMIE
), FLAG(w
, PCI_IOV_CTRL_MSE
),
380 FLAG(w
, PCI_IOV_CTRL_ARI
), FLAG(w
, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN
));
381 w
= get_conf_word(d
, where
+ PCI_IOV_STATUS
);
382 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w
, PCI_IOV_STATUS_MS
));
383 w
= get_conf_word(d
, where
+ PCI_IOV_INITIALVF
);
384 printf("\t\tInitial VFs: %d, ", w
);
385 w
= get_conf_word(d
, where
+ PCI_IOV_TOTALVF
);
386 printf("Total VFs: %d, ", w
);
387 w
= get_conf_word(d
, where
+ PCI_IOV_NUMVF
);
388 printf("Number of VFs: %d, ", w
);
389 b
= get_conf_byte(d
, where
+ PCI_IOV_FDL
);
390 printf("Function Dependency Link: %02x\n", b
);
391 w
= get_conf_word(d
, where
+ PCI_IOV_OFFSET
);
392 printf("\t\tVF offset: %d, ", w
);
393 w
= get_conf_word(d
, where
+ PCI_IOV_STRIDE
);
394 printf("stride: %d, ", w
);
395 w
= get_conf_word(d
, where
+ PCI_IOV_DID
);
396 printf("Device ID: %04x\n", w
);
397 l
= get_conf_long(d
, where
+ PCI_IOV_SUPPS
);
398 printf("\t\tSupported Page Size: %08x, ", l
);
399 l
= get_conf_long(d
, where
+ PCI_IOV_SYSPS
);
400 printf("System Page Size: %08x\n", l
);
402 for (i
=0; i
< PCI_IOV_NUM_BAR
; i
++)
407 l
= get_conf_long(d
, where
+ PCI_IOV_BAR_BASE
+ 4*i
);
412 printf("\t\tRegion %d: Memory at ", i
);
413 addr
= l
& PCI_ADDR_MEM_MASK
;
414 type
= l
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
415 if (type
== PCI_BASE_ADDRESS_MEM_TYPE_64
)
418 h
= get_conf_long(d
, where
+ PCI_IOV_BAR_BASE
+ (i
*4));
421 printf("%08x (%s-bit, %sprefetchable)\n",
423 (type
== PCI_BASE_ADDRESS_MEM_TYPE_32
) ? "32" : "64",
424 (l
& PCI_BASE_ADDRESS_MEM_PREFETCH
) ? "" : "non-");
427 l
= get_conf_long(d
, where
+ PCI_IOV_MSAO
);
428 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l
),
433 cap_multicast(struct device
*d
, int where
, int type
)
439 printf("Multicast\n");
443 if (!config_fetch(d
, where
+ PCI_MCAST_CAP
, 0x30))
446 w
= get_conf_word(d
, where
+ PCI_MCAST_CAP
);
447 printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w
) + 1);
448 if (type
== PCI_EXP_TYPE_ENDPOINT
|| type
== PCI_EXP_TYPE_ROOT_INT_EP
)
449 printf(", WindowSz %d (%d bytes)",
450 PCI_MCAST_CAP_WIN_SIZE(w
), 1 << PCI_MCAST_CAP_WIN_SIZE(w
));
451 if (type
== PCI_EXP_TYPE_ROOT_PORT
||
452 type
== PCI_EXP_TYPE_UPSTREAM
|| type
== PCI_EXP_TYPE_DOWNSTREAM
)
453 printf(", ECRCRegen%c\n", FLAG(w
, PCI_MCAST_CAP_ECRC
));
454 w
= get_conf_word(d
, where
+ PCI_MCAST_CTRL
);
455 printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
456 PCI_MCAST_CTRL_NUM_GROUP(w
) + 1, FLAG(w
, PCI_MCAST_CTRL_ENABLE
));
457 bar
= get_conf_long(d
, where
+ PCI_MCAST_BAR
);
458 l
= get_conf_long(d
, where
+ PCI_MCAST_BAR
+ 4);
459 bar
|= (u64
) l
<< 32;
460 printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X
"\n",
461 PCI_MCAST_BAR_INDEX_POS(bar
), bar
& PCI_MCAST_BAR_MASK
);
462 rcv
= get_conf_long(d
, where
+ PCI_MCAST_RCV
);
463 l
= get_conf_long(d
, where
+ PCI_MCAST_RCV
+ 4);
464 rcv
|= (u64
) l
<< 32;
465 printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X
"\n", rcv
);
466 block
= get_conf_long(d
, where
+ PCI_MCAST_BLOCK
);
467 l
= get_conf_long(d
, where
+ PCI_MCAST_BLOCK
+ 4);
468 block
|= (u64
) l
<< 32;
469 printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X
"\n", block
);
470 block
= get_conf_long(d
, where
+ PCI_MCAST_BLOCK_UNTRANS
);
471 l
= get_conf_long(d
, where
+ PCI_MCAST_BLOCK_UNTRANS
+ 4);
472 block
|= (u64
) l
<< 32;
473 printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X
"\n", block
);
475 if (type
== PCI_EXP_TYPE_ENDPOINT
|| type
== PCI_EXP_TYPE_ROOT_INT_EP
)
477 bar
= get_conf_long(d
, where
+ PCI_MCAST_OVL_BAR
);
478 l
= get_conf_long(d
, where
+ PCI_MCAST_OVL_BAR
+ 4);
479 bar
|= (u64
) l
<< 32;
480 printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar
));
481 if (PCI_MCAST_OVL_SIZE(bar
) >= 6)
482 printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar
));
484 printf("(disabled)");
485 printf(", BaseAddr %016" PCI_U64_FMT_X
"\n", bar
& PCI_MCAST_OVL_MASK
);
489 cap_vc(struct device
*d
, int where
)
496 static const char ref_clocks
[][6] = { "100ns" };
497 static const char arb_selects
[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
498 static const char vc_arb_selects
[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
501 printf("Virtual Channel\n");
505 if (!config_fetch(d
, where
+ 4, 0x1c - 4))
508 cr1
= get_conf_long(d
, where
+ PCI_VC_PORT_REG1
);
509 cr2
= get_conf_long(d
, where
+ PCI_VC_PORT_REG2
);
510 ctrl
= get_conf_word(d
, where
+ PCI_VC_PORT_CTRL
);
511 status
= get_conf_word(d
, where
+ PCI_VC_PORT_STATUS
);
513 evc_cnt
= BITS(cr1
, 0, 3);
514 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
516 TABLE(ref_clocks
, BITS(cr1
, 8, 2), buf
),
517 1 << BITS(cr1
, 10, 2));
521 if (arb_selects
[i
][0] != '?' || cr2
& (1 << i
))
522 printf("%c%s%c", (i
? ' ' : '\t'), arb_selects
[i
], FLAG(cr2
, 1 << i
));
523 arb_table_pos
= BITS(cr2
, 24, 8);
525 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects
, BITS(ctrl
, 1, 3), buf
));
526 printf("\t\tStatus:\tInProgress%c\n", FLAG(status
, 1));
530 arb_table_pos
= where
+ 16*arb_table_pos
;
531 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos
);
534 for (i
=0; i
<=evc_cnt
; i
++)
536 int pos
= where
+ PCI_VC_RES_CAP
+ 12*i
;
541 printf("\t\tVC%d:\t", i
);
542 if (!config_fetch(d
, pos
, 12))
544 printf("<unreadable>\n");
547 rcap
= get_conf_long(d
, pos
);
548 rctrl
= get_conf_long(d
, pos
+4);
549 rstatus
= get_conf_word(d
, pos
+10);
551 pat_pos
= BITS(rcap
, 24, 8);
552 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
554 BITS(rcap
, 16, 7) + 1,
555 FLAG(rcap
, 1 << 15));
557 printf("\t\t\tArb:");
559 if (vc_arb_selects
[j
][0] != '?' || rcap
& (1 << j
))
560 printf("%c%s%c", (j
? ' ' : '\t'), vc_arb_selects
[j
], FLAG(rcap
, 1 << j
));
562 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
563 FLAG(rctrl
, 1 << 31),
565 TABLE(vc_arb_selects
, BITS(rctrl
, 17, 3), buf
),
568 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
573 printf("\t\t\tPort Arbitration Table <?>\n");
578 cap_rclink(struct device
*d
, int where
)
583 static const char elt_types
[][9] = { "Config", "Egress", "Internal" };
586 printf("Root Complex Link\n");
590 if (!config_fetch(d
, where
+ 4, PCI_RCLINK_LINK1
- 4))
593 esd
= get_conf_long(d
, where
+ PCI_RCLINK_ESD
);
594 num_links
= BITS(esd
, 8, 8);
595 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
598 TABLE(elt_types
, BITS(esd
, 0, 8), buf
));
600 for (i
=0; i
<num_links
; i
++)
602 int pos
= where
+ PCI_RCLINK_LINK1
+ i
*PCI_RCLINK_LINK_SIZE
;
604 u32 addr_lo
, addr_hi
;
606 printf("\t\tLink%d:\t", i
);
607 if (!config_fetch(d
, pos
, PCI_RCLINK_LINK_SIZE
))
609 printf("<unreadable>\n");
612 desc
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_DESC
);
613 addr_lo
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_ADDR
);
614 addr_hi
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_ADDR
+ 4);
616 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
620 ((desc
& 2) ? "Config" : "MemMapped"),
628 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
629 BITS(addr_lo
, 20, n
),
630 BITS(addr_lo
, 15, 5),
631 BITS(addr_lo
, 12, 3),
635 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi
, addr_lo
);
640 cap_rcec(struct device
*d
, int where
)
642 printf("Root Complex Event Collector Endpoint Association\n");
646 if (!config_fetch(d
, where
, 12))
649 u32 hdr
= get_conf_long(d
, where
);
650 byte cap_ver
= PCI_RCEC_EP_CAP_VER(hdr
);
651 u32 bmap
= get_conf_long(d
, where
+ PCI_RCEC_RCIEP_BMAP
);
652 printf("\t\tRCiEPBitmap: ");
658 printf("RCiEP at Device(s):");
659 for (int dev
=0; dev
< 32; dev
++)
661 if (BITS(bmap
, dev
, 1))
664 printf("%s %u", (prevmatched
) ? "," : "", dev
);
672 printf("-%u", prevdev
);
678 printf("%s", (verbose
> 2) ? "00000000 [none]" : "[none]");
681 if (cap_ver
< PCI_RCEC_BUSN_REG_VER
)
684 u32 busn
= get_conf_long(d
, where
+ PCI_RCEC_BUSN_REG
);
685 u8 lastbusn
= BITS(busn
, 16, 8);
686 u8 nextbusn
= BITS(busn
, 8, 8);
688 if ((lastbusn
== 0x00) && (nextbusn
== 0xff))
689 printf("\t\tAssociatedBusNumbers: %s\n", (verbose
> 2) ? "ff-00 [none]" : "[none]");
691 printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn
, lastbusn
);
695 cap_lmr(struct device
*d
, int where
)
697 printf("Lane Margining at the Receiver\n");
702 if (!config_fetch(d
, where
, 8))
705 u16 port_caps
= get_conf_word(d
, where
+ PCI_LMR_CAPS
);
706 u16 port_status
= get_conf_word(d
, where
+ PCI_LMR_PORT_STS
);
708 printf("\t\tPortCap: Uses Driver%c\n", FLAG(port_caps
, PCI_LMR_CAPS_DRVR
));
709 printf("\t\tPortSta: MargReady%c MargSoftReady%c\n",
710 FLAG(port_status
, PCI_LMR_PORT_STS_READY
),
711 FLAG(port_status
, PCI_LMR_PORT_STS_SOFT_READY
));
715 cxl_range(u64 base
, u64 size
, int n
)
717 u32 interleave
[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 };
718 const char *type
[] = { "Volatile", "Non-volatile", "CDAT" };
719 const char *class[] = { "DRAM", "Storage", "CDAT" };
724 size
&= ~0x0fffffffULL
;
726 printf("\t\tRange%d: %016"PCI_U64_FMT_X
"-%016"PCI_U64_FMT_X
" [size=0x%"PCI_U64_FMT_X
"]\n", n
, base
, base
+ size
- 1, size
);
727 printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n",
728 FLAG(w
, PCI_CXL_RANGE_VALID
), FLAG(w
, PCI_CXL_RANGE_ACTIVE
),
729 type
[PCI_CXL_RANGE_TYPE(w
)], class[PCI_CXL_RANGE_CLASS(w
)],
730 interleave
[PCI_CXL_RANGE_INTERLEAVE(w
)],
731 1 << (PCI_CXL_RANGE_TIMEOUT(w
) * 2));
735 dvsec_cxl_device(struct device
*d
, int rev
, int where
, int len
)
737 u32 cache_size
, cache_unit_size
;
738 u64 range_base
, range_size
;
741 /* Legacy 1.1 revs aren't handled */
745 if (rev
>= 1 && len
>= PCI_CXL_DEV_LEN
)
747 w
= get_conf_word(d
, where
+ PCI_CXL_DEV_CAP
);
748 printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n",
749 FLAG(w
, PCI_CXL_DEV_CAP_CACHE
), FLAG(w
, PCI_CXL_DEV_CAP_IO
), FLAG(w
, PCI_CXL_DEV_CAP_MEM
),
750 FLAG(w
, PCI_CXL_DEV_CAP_MEM_HWINIT
), PCI_CXL_DEV_CAP_HDM_CNT(w
), FLAG(w
, PCI_CXL_DEV_CAP_VIRAL
));
752 w
= get_conf_word(d
, where
+ PCI_CXL_DEV_CTRL
);
753 printf("\t\tCXLCtl:\tCache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c\n",
754 FLAG(w
, PCI_CXL_DEV_CTRL_CACHE
), FLAG(w
, PCI_CXL_DEV_CTRL_IO
), FLAG(w
, PCI_CXL_DEV_CTRL_MEM
),
755 PCI_CXL_DEV_CTRL_CACHE_SF_COV(w
), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w
), FLAG(w
, PCI_CXL_DEV_CTRL_CACHE_CLN
),
756 FLAG(w
, PCI_CXL_DEV_CTRL_VIRAL
));
758 w
= get_conf_word(d
, where
+ PCI_CXL_DEV_STATUS
);
759 printf("\t\tCXLSta:\tViral%c\n", FLAG(w
, PCI_CXL_DEV_STATUS_VIRAL
));
761 w
= get_conf_word(d
, where
+ PCI_CXL_DEV_CTRL2
);
762 printf("\t\tCXLCtl2:\tDisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c",
763 FLAG(w
, PCI_CXL_DEV_CTRL2_DISABLE_CACHING
),
764 FLAG(w
, PCI_CXL_DEV_CTRL2_INIT_WB_INVAL
),
765 FLAG(w
, PCI_CXL_DEV_CTRL2_INIT_CXL_RST
),
766 FLAG(w
, PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN
));
768 printf(" DesiredVolatileHDMStateAfterHotReset%c", FLAG(w
, PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST
));
771 w
= get_conf_word(d
, where
+ PCI_CXL_DEV_STATUS2
);
772 printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
773 FLAG(w
, PCI_CXL_DEV_STATUS_RC
), FLAG(w
,PCI_CXL_DEV_STATUS_RE
), FLAG(w
, PCI_CXL_DEV_STATUS_PMC
));
775 w
= get_conf_word(d
, where
+ PCI_CXL_DEV_CAP2
);
776 printf("\t\tCXLCap2:\t");
777 cache_unit_size
= BITS(w
, 0, 4);
778 cache_size
= BITS(w
, 8, 8);
779 switch (cache_unit_size
)
781 case PCI_CXL_DEV_CAP2_CACHE_1M
:
782 printf("Cache Size: %08x\n", cache_size
* (1<<20));
784 case PCI_CXL_DEV_CAP2_CACHE_64K
:
785 printf("Cache Size: %08x\n", cache_size
* (64<<10));
787 case PCI_CXL_DEV_CAP2_CACHE_UNK
:
788 printf("Cache Size Not Reported\n");
791 printf("Cache Size: %d of unknown unit size (%d)\n", cache_size
, cache_unit_size
);
795 range_size
= (u64
) get_conf_long(d
, where
+ PCI_CXL_DEV_RANGE1_SIZE_HI
) << 32;
796 range_size
|= get_conf_long(d
, where
+ PCI_CXL_DEV_RANGE1_SIZE_LO
);
797 range_base
= (u64
) get_conf_long(d
, where
+ PCI_CXL_DEV_RANGE1_BASE_HI
) << 32;
798 range_base
|= get_conf_long(d
, where
+ PCI_CXL_DEV_RANGE1_BASE_LO
);
799 cxl_range(range_base
, range_size
, 1);
801 range_size
= (u64
) get_conf_long(d
, where
+ PCI_CXL_DEV_RANGE2_SIZE_HI
) << 32;
802 range_size
|= get_conf_long(d
, where
+ PCI_CXL_DEV_RANGE2_SIZE_LO
);
803 range_base
= (u64
) get_conf_long(d
, where
+ PCI_CXL_DEV_RANGE2_BASE_HI
) << 32;
804 range_base
|= get_conf_long(d
, where
+ PCI_CXL_DEV_RANGE2_BASE_LO
);
805 cxl_range(range_base
, range_size
, 2);
808 if (rev
>= 2 && len
>= PCI_CXL_DEV_LEN_REV2
)
810 w
= get_conf_word(d
, where
+ PCI_CXL_DEV_CAP3
);
811 printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n",
812 FLAG(w
, PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD
),
813 FLAG(w
, PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM
),
814 FLAG(w
, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT
),
815 FLAG(w
, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG
));
819 if (len
> PCI_CXL_DEV_LEN_REV2
)
824 dvsec_cxl_port(struct device
*d
, int where
, int len
)
829 if (len
< PCI_CXL_PORT_EXT_LEN
)
832 w
= get_conf_word(d
, where
+ PCI_CXL_PORT_EXT_STATUS
);
833 printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w
, PCI_CXL_PORT_EXT_STATUS
));
835 w
= get_conf_word(d
, where
+ PCI_CXL_PORT_CTRL
);
836 printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
837 FLAG(w
, PCI_CXL_PORT_UNMASK_SBR
), FLAG(w
, PCI_CXL_PORT_UNMASK_LINK
),
838 FLAG(w
, PCI_CXL_PORT_ALT_MEMORY
), FLAG(w
, PCI_CXL_PORT_ALT_BME
),
839 FLAG(w
, PCI_CXL_PORT_VIRAL_EN
));
841 b1
= get_conf_byte(d
, where
+ PCI_CXL_PORT_ALT_BUS_BASE
);
842 b2
= get_conf_byte(d
, where
+ PCI_CXL_PORT_ALT_BUS_LIMIT
);
843 printf("\t\tAlternateBus:\t%02x-%02x\n", b1
, b2
);
844 m1
= get_conf_word(d
, where
+ PCI_CXL_PORT_ALT_MEM_BASE
);
845 m2
= get_conf_word(d
, where
+ PCI_CXL_PORT_ALT_MEM_LIMIT
);
846 printf("\t\tAlternateBus:\t%04x-%04x\n", m1
, m2
);
850 dvsec_cxl_register_locator(struct device
*d
, int where
, int len
)
852 static const char * const id_names
[] = {
854 "component registers",
855 "BAR virtualization",
856 "CXL device registers",
862 int pos
= where
+ PCI_CXL_RL_BLOCK1_LO
+ 8*i
;
863 if (pos
+ 7 >= where
+ len
)
866 u32 lo
= get_conf_long(d
, pos
);
867 u32 hi
= get_conf_long(d
, pos
+ 4);
869 unsigned int bir
= BITS(lo
, 0, 3);
870 unsigned int block_id
= BITS(lo
, 8, 8);
871 u64 base
= (BITS(lo
, 16, 16) << 16) | ((u64
) hi
<< 32);
877 if (block_id
< sizeof(id_names
) / sizeof(*id_names
))
878 id_name
= id_names
[block_id
];
879 else if (block_id
== 0xff)
880 id_name
= "vendor-specific";
884 printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X
"\n", i
+ 1, bir
, id_name
, base
);
889 dvsec_cxl_gpf_device(struct device
*d
, int where
)
893 u8 time_base
, time_scale
;
895 w
= get_conf_word(d
, where
+ PCI_CXL_GPF_DEV_PHASE2_DUR
);
896 time_base
= BITS(w
, 0, 4);
897 time_scale
= BITS(w
, 8, 4);
901 case PCI_CXL_GPF_DEV_100US
:
902 case PCI_CXL_GPF_DEV_100MS
:
903 duration
= time_base
* 100;
905 case PCI_CXL_GPF_DEV_10US
:
906 case PCI_CXL_GPF_DEV_10MS
:
907 case PCI_CXL_GPF_DEV_10S
:
908 duration
= time_base
* 10;
910 case PCI_CXL_GPF_DEV_1US
:
911 case PCI_CXL_GPF_DEV_1MS
:
912 case PCI_CXL_GPF_DEV_1S
:
913 duration
= time_base
;
917 printf("\t\tReserved time scale encoding %x\n", time_scale
);
918 duration
= time_base
;
921 printf("\t\tGPF Phase 2 Duration: %u%s\n", duration
,
922 (time_scale
< PCI_CXL_GPF_DEV_1MS
) ? "us":
923 (time_scale
< PCI_CXL_GPF_DEV_1S
) ? "ms" :
924 (time_scale
== PCI_CXL_GPF_DEV_1S
) ? "s" : "<?>");
926 l
= get_conf_long(d
, where
+ PCI_CXL_GPF_DEV_PHASE2_POW
);
927 printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l
);
931 dvsec_cxl_gpf_port(struct device
*d
, int where
)
934 u8 time_base
, time_scale
;
936 w
= get_conf_word(d
, where
+ PCI_CXL_GPF_PORT_PHASE1_CTRL
);
937 time_base
= BITS(w
, 0, 4);
938 time_scale
= BITS(w
, 8, 4);
942 case PCI_CXL_GPF_PORT_100US
:
943 case PCI_CXL_GPF_PORT_100MS
:
944 timeout
= time_base
* 100;
946 case PCI_CXL_GPF_PORT_10US
:
947 case PCI_CXL_GPF_PORT_10MS
:
948 case PCI_CXL_GPF_PORT_10S
:
949 timeout
= time_base
* 10;
951 case PCI_CXL_GPF_PORT_1US
:
952 case PCI_CXL_GPF_PORT_1MS
:
953 case PCI_CXL_GPF_PORT_1S
:
958 printf("\t\tReserved time scale encoding %x\n", time_scale
);
962 printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout
,
963 (time_scale
< PCI_CXL_GPF_PORT_1MS
) ? "us":
964 (time_scale
< PCI_CXL_GPF_PORT_1S
) ? "ms" :
965 (time_scale
== PCI_CXL_GPF_PORT_1S
) ? "s" : "<?>");
967 w
= get_conf_word(d
, where
+ PCI_CXL_GPF_PORT_PHASE2_CTRL
);
968 time_base
= BITS(w
, 0, 4);
969 time_scale
= BITS(w
, 8, 4);
973 case PCI_CXL_GPF_PORT_100US
:
974 case PCI_CXL_GPF_PORT_100MS
:
975 timeout
= time_base
* 100;
977 case PCI_CXL_GPF_PORT_10US
:
978 case PCI_CXL_GPF_PORT_10MS
:
979 case PCI_CXL_GPF_PORT_10S
:
980 timeout
= time_base
* 10;
982 case PCI_CXL_GPF_PORT_1US
:
983 case PCI_CXL_GPF_PORT_1MS
:
984 case PCI_CXL_GPF_PORT_1S
:
989 printf("\t\tReserved time scale encoding %x\n", time_scale
);
993 printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout
,
994 (time_scale
< PCI_CXL_GPF_PORT_1MS
) ? "us":
995 (time_scale
< PCI_CXL_GPF_PORT_1S
) ? "ms" :
996 (time_scale
== PCI_CXL_GPF_PORT_1S
) ? "s" : "<?>");
1000 dvsec_cxl_flex_bus(struct device
*d
, int where
, int rev
, int len
)
1005 // Sanity check: Does the length correspond to its revision?
1008 if (len
!= PCI_CXL_FB_MOD_TS_DATA
)
1009 printf("\t\t<Wrong length for Revision %d>\n", rev
);
1012 if (len
!= PCI_CXL_FB_PORT_CAP2
)
1013 printf("\t\t<Wrong length for Revision %d>\n", rev
);
1016 if (len
!= PCI_CXL_FB_NEXT_UNSUPPORTED
)
1017 printf("\t\t<Wrong length for Revision %d>\n", rev
);
1024 w
= get_conf_word(d
, where
+ PCI_CXL_FB_PORT_CAP
);
1025 printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
1026 FLAG(w
, PCI_CXL_FB_CAP_CACHE
), FLAG(w
, PCI_CXL_FB_CAP_IO
),
1027 FLAG(w
, PCI_CXL_FB_CAP_MEM
), FLAG(w
, PCI_CXL_FB_CAP_68B_FLIT
),
1028 FLAG(w
, PCI_CXL_FB_CAP_MULT_LOG_DEV
));
1031 printf(" 256BFlit%c PBRFlit%c",
1032 FLAG(w
, PCI_CXL_FB_CAP_256B_FLIT
), FLAG(w
, PCI_CXL_FB_CAP_PBR_FLIT
));
1034 w
= get_conf_word(d
, where
+ PCI_CXL_FB_PORT_CTRL
);
1035 printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
1036 FLAG(w
, PCI_CXL_FB_CTRL_CACHE
), FLAG(w
, PCI_CXL_FB_CTRL_IO
),
1037 FLAG(w
, PCI_CXL_FB_CTRL_MEM
), FLAG(w
, PCI_CXL_FB_CTRL_SYNC_HDR_BYP
),
1038 FLAG(w
, PCI_CXL_FB_CTRL_DRFT_BUF
), FLAG(w
, PCI_CXL_FB_CTRL_68B_FLIT
),
1039 FLAG(w
, PCI_CXL_FB_CTRL_MULT_LOG_DEV
), FLAG(w
, PCI_CXL_FB_CTRL_RCD
),
1040 FLAG(w
, PCI_CXL_FB_CTRL_RETIMER1
), FLAG(w
, PCI_CXL_FB_CTRL_RETIMER2
));
1043 printf(" 256BFlit%c PBRFlit%c",
1044 FLAG(w
, PCI_CXL_FB_CTRL_256B_FLIT
), FLAG(w
, PCI_CXL_FB_CTRL_PBR_FLIT
));
1046 w
= get_conf_word(d
, where
+ PCI_CXL_FB_PORT_STATUS
);
1047 printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
1048 FLAG(w
, PCI_CXL_FB_STAT_CACHE
), FLAG(w
, PCI_CXL_FB_STAT_IO
),
1049 FLAG(w
, PCI_CXL_FB_STAT_MEM
), FLAG(w
, PCI_CXL_FB_STAT_SYNC_HDR_BYP
),
1050 FLAG(w
, PCI_CXL_FB_STAT_DRFT_BUF
), FLAG(w
, PCI_CXL_FB_STAT_68B_FLIT
),
1051 FLAG(w
, PCI_CXL_FB_STAT_MULT_LOG_DEV
));
1054 printf(" 256BFlit%c PBRFlit%c",
1055 FLAG(w
, PCI_CXL_FB_STAT_256B_FLIT
), FLAG(w
, PCI_CXL_FB_STAT_PBR_FLIT
));
1061 l
= get_conf_long(d
, where
+ PCI_CXL_FB_MOD_TS_DATA
);
1062 data
= BITS(l
, 0, 24);
1063 printf("\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data
);
1071 l
= get_conf_long(d
, where
+ PCI_CXL_FB_PORT_CAP2
);
1072 printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l
, PCI_CXL_FB_CAP2_NOP_HINT
));
1074 l
= get_conf_long(d
, where
+ PCI_CXL_FB_PORT_CTRL2
);
1075 printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l
, PCI_CXL_FB_CTRL2_NOP_HINT
));
1077 l
= get_conf_long(d
, where
+ PCI_CXL_FB_PORT_STATUS2
);
1078 nop
= BITS(l
, 0, 2);
1079 printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop
);
1083 if (len
> PCI_CXL_FB_LEN
)
1084 printf("\t\t<?>\n");
1088 dvsec_cxl_mld(struct device
*d
, int where
)
1092 w
= get_conf_word(d
, where
+ PCI_CXL_MLD_NUM_LD
);
1094 /* Encodings greater than 16 are reserved */
1095 if (w
&& w
<= PCI_CXL_MLD_MAX_LD
)
1096 printf("\t\tNumLogDevs: %d\n", w
);
1100 dvsec_cxl_function_map(struct device
*d
, int where
)
1103 printf("\t\tFuncMap 0: %08x\n",
1104 (unsigned int)(get_conf_word(d
, where
+ PCI_CXL_FUN_MAP_REG_0
)));
1106 printf("\t\tFuncMap 1: %08x\n",
1107 (unsigned int)(get_conf_word(d
, where
+ PCI_CXL_FUN_MAP_REG_1
)));
1109 printf("\t\tFuncMap 2: %08x\n",
1110 (unsigned int)(get_conf_word(d
, where
+ PCI_CXL_FUN_MAP_REG_2
)));
1112 printf("\t\tFuncMap 3: %08x\n",
1113 (unsigned int)(get_conf_word(d
, where
+ PCI_CXL_FUN_MAP_REG_3
)));
1115 printf("\t\tFuncMap 4: %08x\n",
1116 (unsigned int)(get_conf_word(d
, where
+ PCI_CXL_FUN_MAP_REG_4
)));
1118 printf("\t\tFuncMap 5: %08x\n",
1119 (unsigned int)(get_conf_word(d
, where
+ PCI_CXL_FUN_MAP_REG_5
)));
1121 printf("\t\tFuncMap 6: %08x\n",
1122 (unsigned int)(get_conf_word(d
, where
+ PCI_CXL_FUN_MAP_REG_6
)));
1124 printf("\t\tFuncMap 7: %08x\n",
1125 (unsigned int)(get_conf_word(d
, where
+ PCI_CXL_FUN_MAP_REG_7
)));
1129 cap_dvsec_cxl(struct device
*d
, int id
, int rev
, int where
, int len
)
1135 if (!config_fetch(d
, where
, len
))
1141 printf("\t\tPCIe DVSEC for CXL Devices\n");
1142 dvsec_cxl_device(d
, rev
, where
, len
);
1145 printf("\t\tNon-CXL Function Map DVSEC\n");
1146 dvsec_cxl_function_map(d
, where
);
1149 printf("\t\tCXL Extensions DVSEC for Ports\n");
1150 dvsec_cxl_port(d
, where
, len
);
1153 printf("\t\tGPF DVSEC for CXL Ports\n");
1154 dvsec_cxl_gpf_port(d
, where
);
1157 printf("\t\tGPF DVSEC for CXL Devices\n");
1158 dvsec_cxl_gpf_device(d
, where
);
1161 printf("\t\tPCIe DVSEC for Flex Bus Port\n");
1162 dvsec_cxl_flex_bus(d
, where
, rev
, len
);
1165 printf("\t\tRegister Locator DVSEC\n");
1166 dvsec_cxl_register_locator(d
, where
, len
);
1169 printf("\t\tMLD DVSEC\n");
1170 dvsec_cxl_mld(d
, where
);
1173 printf("\t\tPCIe DVSEC for Test Capability <?>\n");
1176 printf("\t\tUnknown ID %04x\n", id
);
1181 cap_dvsec(struct device
*d
, int where
)
1183 printf("Designated Vendor-Specific: ");
1184 if (!config_fetch(d
, where
+ PCI_DVSEC_HEADER1
, 8))
1186 printf("<unreadable>\n");
1190 u32 hdr
= get_conf_long(d
, where
+ PCI_DVSEC_HEADER1
);
1191 u16 vendor
= BITS(hdr
, 0, 16);
1192 byte rev
= BITS(hdr
, 16, 4);
1193 u16 len
= BITS(hdr
, 20, 12);
1195 u16 id
= get_conf_long(d
, where
+ PCI_DVSEC_HEADER2
);
1197 printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor
, id
, rev
, len
);
1198 if (vendor
== PCI_DVSEC_VENDOR_ID_CXL
&& len
>= 16)
1199 cap_dvsec_cxl(d
, id
, rev
, where
, len
);
1205 cap_evendor(struct device
*d
, int where
)
1209 printf("Vendor Specific Information: ");
1210 if (!config_fetch(d
, where
+ PCI_EVNDR_HEADER
, 4))
1212 printf("<unreadable>\n");
1216 hdr
= get_conf_long(d
, where
+ PCI_EVNDR_HEADER
);
1217 printf("ID=%04x Rev=%d Len=%03x <?>\n",
1223 static int l1pm_calc_pwron(int scale
, int value
)
1238 cap_l1pm(struct device
*d
, int where
)
1240 u32 l1_cap
, val
, scale
;
1243 printf("L1 PM Substates\n");
1248 if (!config_fetch(d
, where
+ PCI_L1PM_SUBSTAT_CAP
, 12))
1250 printf("\t\t<unreadable>\n");
1254 l1_cap
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CAP
);
1255 printf("\t\tL1SubCap: ");
1256 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
1257 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_PM_L12
),
1258 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_PM_L11
),
1259 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_ASPM_L12
),
1260 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_ASPM_L11
),
1261 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP
));
1263 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
1265 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap
, 8, 8));
1266 time
= l1pm_calc_pwron(BITS(l1_cap
, 16, 2), BITS(l1_cap
, 19, 5));
1268 printf("PortTPowerOnTime=%dus\n", time
);
1270 printf("PortTPowerOnTime=<error>\n");
1273 val
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CTL1
);
1274 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
1275 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_PM_L12
),
1276 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_PM_L11
),
1277 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12
),
1278 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11
));
1280 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
1282 printf("\t\t\t T_CommonMode=%dus", BITS(val
, 8, 8));
1284 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
1286 scale
= BITS(val
, 29, 3);
1288 printf(" LTR1.2_Threshold=<error>");
1290 printf(" LTR1.2_Threshold=%" PCI_U64_FMT_U
"ns", BITS(val
, 16, 10) * (u64
) cap_ltr_scale(scale
));
1295 val
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CTL2
);
1296 printf("\t\tL1SubCtl2:");
1297 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
1299 time
= l1pm_calc_pwron(BITS(val
, 0, 2), BITS(val
, 3, 5));
1301 printf(" T_PwrOn=%dus", time
);
1303 printf(" T_PwrOn=<error>");
1309 cap_ptm(struct device
*d
, int where
)
1314 printf("Precision Time Measurement\n");
1319 if (!config_fetch(d
, where
+ 4, 8))
1321 printf("\t\t<unreadable>\n");
1325 buff
= get_conf_long(d
, where
+ 4);
1326 printf("\t\tPTMCap: ");
1327 printf("Requester%c Responder%c Root%c\n",
1332 clock
= BITS(buff
, 8, 8);
1333 printf("\t\tPTMClockGranularity: ");
1337 printf("Unimplemented\n");
1340 printf("Greater than 254ns\n");
1343 printf("%huns\n", clock
);
1346 buff
= get_conf_long(d
, where
+ 8);
1347 printf("\t\tPTMControl: ");
1348 printf("Enabled%c RootSelected%c\n",
1352 clock
= BITS(buff
, 8, 8);
1353 printf("\t\tPTMEffectiveGranularity: ");
1357 printf("Unknown\n");
1360 printf("Greater than 254ns\n");
1363 printf("%huns\n", clock
);
1368 print_rebar_range_size(int ld2_size
)
1370 // This function prints the input as a power-of-2 size value
1371 // It is biased with 1MB = 0, ...
1372 // Maximum resizable BAR value supported is 2^63 bytes = 43
1373 // for the extended resizable BAR capability definition
1374 // (otherwise it would stop at 2^28)
1376 if (ld2_size
>= 0 && ld2_size
< 10)
1377 printf(" %dMB", (1 << ld2_size
));
1378 else if (ld2_size
>= 10 && ld2_size
< 20)
1379 printf(" %dGB", (1 << (ld2_size
-10)));
1380 else if (ld2_size
>= 20 && ld2_size
< 30)
1381 printf(" %dTB", (1 << (ld2_size
-20)));
1382 else if (ld2_size
>= 30 && ld2_size
< 40)
1383 printf(" %dPB", (1 << (ld2_size
-30)));
1384 else if (ld2_size
>= 40 && ld2_size
< 44)
1385 printf(" %dEB", (1 << (ld2_size
-40)));
1387 printf(" <unknown>");
1391 cap_rebar(struct device
*d
, int where
, int virtual)
1393 u32 sizes_buffer
, control_buffer
, ext_sizes
, current_size
;
1394 u16 bar_index
, barcount
, i
;
1395 // If the structure exists, at least one bar is defined
1398 printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical");
1403 // Go through all defined BAR definitions of the caps, at minimum 1
1404 // (loop also terminates if num_bars read from caps is > 6)
1405 for (barcount
= 0; barcount
< num_bars
; barcount
++)
1409 // Get the next BAR configuration
1410 if (!config_fetch(d
, where
, 8))
1412 printf("\t\t<unreadable>\n");
1416 sizes_buffer
= get_conf_long(d
, where
) >> 4;
1418 control_buffer
= get_conf_long(d
, where
);
1420 bar_index
= BITS(control_buffer
, 0, 3);
1421 current_size
= BITS(control_buffer
, 8, 6);
1422 ext_sizes
= BITS(control_buffer
, 16, 16);
1426 // Only index 0 controlreg has the num_bar count definition
1427 num_bars
= BITS(control_buffer
, 5, 3);
1428 if (num_bars
< 1 || num_bars
> 6)
1430 printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars
);
1435 // Resizable BAR list entry have an arbitrary index and current size
1436 printf("\t\tBAR %d: current size:", bar_index
);
1437 print_rebar_range_size(current_size
);
1439 if (sizes_buffer
|| ext_sizes
)
1441 printf(", supported:");
1443 for (i
=0; i
<28; i
++)
1444 if (sizes_buffer
& (1U << i
))
1445 print_rebar_range_size(i
);
1447 for (i
=0; i
<16; i
++)
1448 if (ext_sizes
& (1U << i
))
1449 print_rebar_range_size(i
+ 28);
1457 cap_doe(struct device
*d
, int where
)
1461 printf("Data Object Exchange\n");
1466 if (!config_fetch(d
, where
+ PCI_DOE_CAP
, 0x14))
1468 printf("\t\t<unreadable>\n");
1472 l
= get_conf_long(d
, where
+ PCI_DOE_CAP
);
1473 printf("\t\tDOECap: IntSup%c\n",
1474 FLAG(l
, PCI_DOE_CAP_INT_SUPP
));
1475 if (l
& PCI_DOE_CAP_INT_SUPP
)
1476 printf("\t\t\tIntMsgNum %d\n",
1477 PCI_DOE_CAP_INT_MSG(l
));
1479 l
= get_conf_long(d
, where
+ PCI_DOE_CTL
);
1480 printf("\t\tDOECtl: IntEn%c\n",
1481 FLAG(l
, PCI_DOE_CTL_INT
));
1483 l
= get_conf_long(d
, where
+ PCI_DOE_STS
);
1484 printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n",
1485 FLAG(l
, PCI_DOE_STS_BUSY
),
1486 FLAG(l
, PCI_DOE_STS_INT
),
1487 FLAG(l
, PCI_DOE_STS_ERROR
),
1488 FLAG(l
, PCI_DOE_STS_OBJECT_READY
));
1492 show_ext_caps(struct device
*d
, int type
)
1495 char been_there
[0x1000];
1496 memset(been_there
, 0, 0x1000);
1502 if (!config_fetch(d
, where
, 4))
1504 header
= get_conf_long(d
, where
);
1505 if (!header
|| header
== 0xffffffff)
1507 id
= header
& 0xffff;
1508 version
= (header
>> 16) & 0xf;
1509 printf("\tCapabilities: [%03x", where
);
1511 printf(" v%d", version
);
1513 if (been_there
[where
]++)
1515 printf("<chain looped>\n");
1520 case PCI_EXT_CAP_ID_NULL
:
1523 case PCI_EXT_CAP_ID_AER
:
1524 cap_aer(d
, where
, type
);
1526 case PCI_EXT_CAP_ID_DPC
:
1529 case PCI_EXT_CAP_ID_VC
:
1530 case PCI_EXT_CAP_ID_VC2
:
1533 case PCI_EXT_CAP_ID_DSN
:
1536 case PCI_EXT_CAP_ID_PB
:
1537 printf("Power Budgeting <?>\n");
1539 case PCI_EXT_CAP_ID_RCLINK
:
1540 cap_rclink(d
, where
);
1542 case PCI_EXT_CAP_ID_RCILINK
:
1543 printf("Root Complex Internal Link <?>\n");
1545 case PCI_EXT_CAP_ID_RCEC
:
1548 case PCI_EXT_CAP_ID_MFVC
:
1549 printf("Multi-Function Virtual Channel <?>\n");
1551 case PCI_EXT_CAP_ID_RCRB
:
1552 printf("Root Complex Register Block <?>\n");
1554 case PCI_EXT_CAP_ID_VNDR
:
1555 cap_evendor(d
, where
);
1557 case PCI_EXT_CAP_ID_ACS
:
1560 case PCI_EXT_CAP_ID_ARI
:
1563 case PCI_EXT_CAP_ID_ATS
:
1566 case PCI_EXT_CAP_ID_SRIOV
:
1567 cap_sriov(d
, where
);
1569 case PCI_EXT_CAP_ID_MRIOV
:
1570 printf("Multi-Root I/O Virtualization <?>\n");
1572 case PCI_EXT_CAP_ID_MCAST
:
1573 cap_multicast(d
, where
, type
);
1575 case PCI_EXT_CAP_ID_PRI
:
1578 case PCI_EXT_CAP_ID_REBAR
:
1579 cap_rebar(d
, where
, 0);
1581 case PCI_EXT_CAP_ID_DPA
:
1582 printf("Dynamic Power Allocation <?>\n");
1584 case PCI_EXT_CAP_ID_TPH
:
1587 case PCI_EXT_CAP_ID_LTR
:
1590 case PCI_EXT_CAP_ID_SECPCI
:
1593 case PCI_EXT_CAP_ID_PMUX
:
1594 printf("Protocol Multiplexing <?>\n");
1596 case PCI_EXT_CAP_ID_PASID
:
1597 cap_pasid(d
, where
);
1599 case PCI_EXT_CAP_ID_LNR
:
1600 printf("LN Requester <?>\n");
1602 case PCI_EXT_CAP_ID_L1PM
:
1605 case PCI_EXT_CAP_ID_PTM
:
1608 case PCI_EXT_CAP_ID_M_PCIE
:
1609 printf("PCI Express over M_PHY <?>\n");
1611 case PCI_EXT_CAP_ID_FRS
:
1612 printf("FRS Queueing <?>\n");
1614 case PCI_EXT_CAP_ID_RTR
:
1615 printf("Readiness Time Reporting <?>\n");
1617 case PCI_EXT_CAP_ID_DVSEC
:
1618 cap_dvsec(d
, where
);
1620 case PCI_EXT_CAP_ID_VF_REBAR
:
1621 cap_rebar(d
, where
, 1);
1623 case PCI_EXT_CAP_ID_DLNK
:
1624 printf("Data Link Feature <?>\n");
1626 case PCI_EXT_CAP_ID_16GT
:
1627 printf("Physical Layer 16.0 GT/s <?>\n");
1629 case PCI_EXT_CAP_ID_LMR
:
1632 case PCI_EXT_CAP_ID_HIER_ID
:
1633 printf("Hierarchy ID <?>\n");
1635 case PCI_EXT_CAP_ID_NPEM
:
1636 printf("Native PCIe Enclosure Management <?>\n");
1638 case PCI_EXT_CAP_ID_32GT
:
1639 printf("Physical Layer 32.0 GT/s <?>\n");
1641 case PCI_EXT_CAP_ID_DOE
:
1645 printf("Extended Capability ID %#02x\n", id
);
1648 where
= (header
>> 20) & ~3;