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Register caching rewrite
[thirdparty/pciutils.git] / lspci.c
1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #include "pciutils.h"
16
17 /* Options */
18
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
26
27 static char options[] = "nvbxs:d:ti:mgM" GENERIC_OPTIONS ;
28
29 static char help_msg[] = "\
30 Usage: lspci [<switches>]\n\
31 \n\
32 -v\t\tBe verbose\n\
33 -n\t\tShow numeric ID's\n\
34 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
35 -x\t\tShow hex-dump of the standard portion of config space\n\
36 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
37 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
38 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
39 -d [<vendor>]:[<device>]\tShow only selected devices\n\
40 -t\t\tShow bus tree\n\
41 -m\t\tProduce machine-readable output\n\
42 -i <file>\tUse specified ID database instead of %s\n\
43 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
44 GENERIC_HELP
45 ;
46
47 /* Communication with libpci */
48
49 static struct pci_access *pacc;
50
51 /*
52 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
53 * This increases our memory footprint, but only slightly since we don't
54 * use alloca() much.
55 */
56
57 #ifndef __GNUC__
58 #undef alloca
59 #define alloca xmalloc
60 #endif
61
62 /* Our view of the PCI bus */
63
64 struct device {
65 struct device *next;
66 struct pci_dev *dev;
67 unsigned int config_cached, config_bufsize;
68 byte *config; /* Cached configuration space data */
69 byte *present; /* Maps which configuration bytes are present */
70 };
71
72 static struct device *first_dev;
73
74 static int
75 config_fetch(struct device *d, unsigned int pos, unsigned int len)
76 {
77 unsigned int end = pos+len;
78 int result;
79
80 while (pos < d->config_bufsize && len && d->present[pos])
81 pos++, len--;
82 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
83 len--;
84 if (!len)
85 return 1;
86
87 if (end > d->config_bufsize)
88 {
89 int orig_size = d->config_bufsize;
90 while (end > d->config_bufsize)
91 d->config_bufsize *= 2;
92 d->config = xrealloc(d->config, d->config_bufsize);
93 d->present = xrealloc(d->present, d->config_bufsize);
94 bzero(d->present + orig_size, d->config_bufsize - orig_size);
95 }
96 result = pci_read_block(d->dev, pos, d->config + pos, len);
97 if (result)
98 memset(d->present + pos, 1, len);
99 return result;
100 }
101
102 static struct device *
103 scan_device(struct pci_dev *p)
104 {
105 struct device *d;
106
107 if (!pci_filter_match(&filter, p))
108 return NULL;
109 d = xmalloc(sizeof(struct device));
110 bzero(d, sizeof(*d));
111 d->dev = p;
112 d->config_cached = d->config_bufsize = 64;
113 d->config = xmalloc(64);
114 d->present = xmalloc(64);
115 memset(d->present, 1, 64);
116 if (!pci_read_block(p, 0, d->config, 64))
117 die("Unable to read the standard configuration space header");
118 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
119 {
120 /* For cardbus bridges, we need to fetch 64 bytes more to get the
121 * full standard header... */
122 if (config_fetch(d, 64, 64))
123 d->config_cached += 64;
124 }
125 pci_setup_cache(p, d->config, d->config_cached);
126 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
127 return d;
128 }
129
130 static void
131 scan_devices(void)
132 {
133 struct device *d;
134 struct pci_dev *p;
135
136 pci_scan_bus(pacc);
137 for(p=pacc->devices; p; p=p->next)
138 if (d = scan_device(p))
139 {
140 d->next = first_dev;
141 first_dev = d;
142 }
143 }
144
145 /* Config space accesses */
146
147 static void
148 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
149 {
150 while (len)
151 if (!d->present[pos])
152 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
153 else
154 pos++, len--;
155 }
156
157 static inline byte
158 get_conf_byte(struct device *d, unsigned int pos)
159 {
160 check_conf_range(d, pos, 1);
161 return d->config[pos];
162 }
163
164 static word
165 get_conf_word(struct device *d, unsigned int pos)
166 {
167 check_conf_range(d, pos, 2);
168 return d->config[pos] | (d->config[pos+1] << 8);
169 }
170
171 static u32
172 get_conf_long(struct device *d, unsigned int pos)
173 {
174 check_conf_range(d, pos, 4);
175 return d->config[pos] |
176 (d->config[pos+1] << 8) |
177 (d->config[pos+2] << 16) |
178 (d->config[pos+3] << 24);
179 }
180
181 /* Sorting */
182
183 static int
184 compare_them(const void *A, const void *B)
185 {
186 const struct pci_dev *a = (*(const struct device **)A)->dev;
187 const struct pci_dev *b = (*(const struct device **)B)->dev;
188
189 if (a->domain < b->domain)
190 return -1;
191 if (a->domain > b->domain)
192 return 1;
193 if (a->bus < b->bus)
194 return -1;
195 if (a->bus > b->bus)
196 return 1;
197 if (a->dev < b->dev)
198 return -1;
199 if (a->dev > b->dev)
200 return 1;
201 if (a->func < b->func)
202 return -1;
203 if (a->func > b->func)
204 return 1;
205 return 0;
206 }
207
208 static void
209 sort_them(void)
210 {
211 struct device **index, **h, **last_dev;
212 int cnt;
213 struct device *d;
214
215 cnt = 0;
216 for(d=first_dev; d; d=d->next)
217 cnt++;
218 h = index = alloca(sizeof(struct device *) * cnt);
219 for(d=first_dev; d; d=d->next)
220 *h++ = d;
221 qsort(index, cnt, sizeof(struct device *), compare_them);
222 last_dev = &first_dev;
223 h = index;
224 while (cnt--)
225 {
226 *last_dev = *h;
227 last_dev = &(*h)->next;
228 h++;
229 }
230 *last_dev = NULL;
231 }
232
233 /* Normal output */
234
235 #define FLAG(x,y) ((x & y) ? '+' : '-')
236
237 static void
238 show_slot_name(struct device *d)
239 {
240 struct pci_dev *p = d->dev;
241
242 if (p->domain)
243 printf("%04x:", p->domain);
244 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
245 }
246
247 static void
248 show_terse(struct device *d)
249 {
250 int c;
251 struct pci_dev *p = d->dev;
252 byte classbuf[128], devbuf[128];
253
254 show_slot_name(d);
255 printf(" %s: %s",
256 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
257 PCI_LOOKUP_CLASS,
258 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
259 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
260 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
261 p->vendor_id, p->device_id, 0, 0));
262 if (c = get_conf_byte(d, PCI_REVISION_ID))
263 printf(" (rev %02x)", c);
264 if (verbose)
265 {
266 char *x;
267 c = get_conf_byte(d, PCI_CLASS_PROG);
268 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
269 PCI_LOOKUP_PROGIF,
270 get_conf_word(d, PCI_CLASS_DEVICE), c, 0, 0);
271 if (c || x)
272 {
273 printf(" (prog-if %02x", c);
274 if (x)
275 printf(" [%s]", x);
276 putchar(')');
277 }
278 }
279 putchar('\n');
280 }
281
282 static void
283 show_size(pciaddr_t x)
284 {
285 if (!x)
286 return;
287 printf(" [size=");
288 if (x < 1024)
289 printf("%d", (int) x);
290 else if (x < 1048576)
291 printf("%dK", (int)(x / 1024));
292 else if (x < 0x80000000)
293 printf("%dM", (int)(x / 1048576));
294 else
295 printf(PCIADDR_T_FMT, x);
296 putchar(']');
297 }
298
299 static void
300 show_bases(struct device *d, int cnt)
301 {
302 struct pci_dev *p = d->dev;
303 word cmd = get_conf_word(d, PCI_COMMAND);
304 int i;
305
306 for(i=0; i<cnt; i++)
307 {
308 pciaddr_t pos = p->base_addr[i];
309 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
310 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
311 if (flg == 0xffffffff)
312 flg = 0;
313 if (!pos && !flg && !len)
314 continue;
315 if (verbose > 1)
316 printf("\tRegion %d: ", i);
317 else
318 putchar('\t');
319 if (pos && !flg) /* Reported by the OS, but not by the device */
320 {
321 printf("[virtual] ");
322 flg = pos;
323 }
324 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
325 {
326 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
327 printf("I/O ports at ");
328 if (a)
329 printf(PCIADDR_PORT_FMT, a);
330 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
331 printf("<ignored>");
332 else
333 printf("<unassigned>");
334 if (!(cmd & PCI_COMMAND_IO))
335 printf(" [disabled]");
336 }
337 else
338 {
339 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
340 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
341 int done = 0;
342 u32 z = 0;
343
344 printf("Memory at ");
345 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
346 {
347 if (i >= cnt - 1)
348 {
349 printf("<invalid-64bit-slot>");
350 done = 1;
351 }
352 else
353 {
354 i++;
355 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
356 if (buscentric_view)
357 {
358 if (a || z)
359 printf("%08x" PCIADDR_T_FMT, z, a);
360 else
361 printf("<unassigned>");
362 done = 1;
363 }
364 }
365 }
366 if (!done)
367 {
368 if (a)
369 printf(PCIADDR_T_FMT, a);
370 else
371 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
372 }
373 printf(" (%s, %sprefetchable)",
374 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
375 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
376 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
377 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
378 if (!(cmd & PCI_COMMAND_MEMORY))
379 printf(" [disabled]");
380 }
381 show_size(len);
382 putchar('\n');
383 }
384 }
385
386 static void
387 show_pm(struct device *d, int where, int cap)
388 {
389 int t, b;
390 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
391
392 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
393 if (verbose < 2)
394 return;
395 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
396 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
397 FLAG(cap, PCI_PM_CAP_DSI),
398 FLAG(cap, PCI_PM_CAP_D1),
399 FLAG(cap, PCI_PM_CAP_D2),
400 pm_aux_current[(cap >> 6) & 7],
401 FLAG(cap, PCI_PM_CAP_PME_D0),
402 FLAG(cap, PCI_PM_CAP_PME_D1),
403 FLAG(cap, PCI_PM_CAP_PME_D2),
404 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
405 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
406 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
407 return;
408 t = get_conf_word(d, where + PCI_PM_CTRL);
409 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
410 t & PCI_PM_CTRL_STATE_MASK,
411 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
412 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
413 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
414 FLAG(t, PCI_PM_CTRL_PME_STATUS));
415 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
416 if (b)
417 printf("\t\tBridge: PM%c B3%c\n",
418 FLAG(t, PCI_PM_BPCC_ENABLE),
419 FLAG(~t, PCI_PM_PPB_B2_B3));
420 }
421
422 static void
423 format_agp_rate(int rate, char *buf, int agp3)
424 {
425 char *c = buf;
426 int i;
427
428 for(i=0; i<=2; i++)
429 if (rate & (1 << i))
430 {
431 if (c != buf)
432 *c++ = ',';
433 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
434 }
435 if (c != buf)
436 *c = 0;
437 else
438 strcpy(buf, "<none>");
439 }
440
441 static void
442 show_agp(struct device *d, int where, int cap)
443 {
444 u32 t;
445 char rate[16];
446 int ver, rev;
447 int agp3 = 0;
448
449 ver = (cap >> 4) & 0x0f;
450 rev = cap & 0x0f;
451 printf("AGP version %x.%x\n", ver, rev);
452 if (verbose < 2)
453 return;
454 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
455 return;
456 t = get_conf_long(d, where + PCI_AGP_STATUS);
457 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
458 agp3 = 1;
459 format_agp_rate(t & 7, rate, agp3);
460 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
461 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
462 FLAG(t, PCI_AGP_STATUS_ISOCH),
463 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
464 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
465 FLAG(t, PCI_AGP_STATUS_SBA),
466 FLAG(t, PCI_AGP_STATUS_ITA_COH),
467 FLAG(t, PCI_AGP_STATUS_GART64),
468 FLAG(t, PCI_AGP_STATUS_HTRANS),
469 FLAG(t, PCI_AGP_STATUS_64BIT),
470 FLAG(t, PCI_AGP_STATUS_FW),
471 FLAG(t, PCI_AGP_STATUS_AGP3),
472 rate);
473 t = get_conf_long(d, where + PCI_AGP_COMMAND);
474 format_agp_rate(t & 7, rate, agp3);
475 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
476 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
477 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
478 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
479 FLAG(t, PCI_AGP_COMMAND_SBA),
480 FLAG(t, PCI_AGP_COMMAND_AGP),
481 FLAG(t, PCI_AGP_COMMAND_GART64),
482 FLAG(t, PCI_AGP_COMMAND_64BIT),
483 FLAG(t, PCI_AGP_COMMAND_FW),
484 rate);
485 }
486
487 static void
488 show_pcix_nobridge(struct device *d, int where)
489 {
490 u16 command;
491 u32 status;
492 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
493
494 printf("PCI-X non-bridge device\n");
495
496 if (verbose < 2)
497 return;
498
499 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
500 return;
501
502 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
503 status = get_conf_long(d, where + PCI_PCIX_STATUS);
504 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
505 FLAG(command, PCI_PCIX_COMMAND_DPERE),
506 FLAG(command, PCI_PCIX_COMMAND_ERO),
507 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
508 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
509 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
510 ((status >> 8) & 0xff),
511 ((status >> 3) & 0x1f),
512 (status & PCI_PCIX_STATUS_FUNCTION),
513 FLAG(status, PCI_PCIX_STATUS_64BIT),
514 FLAG(status, PCI_PCIX_STATUS_133MHZ),
515 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
516 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
517 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
518 1 << (9 + ((status >> 21) & 3U)),
519 max_outstanding[(status >> 23) & 7U],
520 1 << (3 + ((status >> 26) & 7U)),
521 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
522 FLAG(status, PCI_PCIX_STATUS_266MHZ),
523 FLAG(status, PCI_PCIX_STATUS_533MHZ));
524 }
525
526 static void
527 show_pcix_bridge(struct device *d, int where)
528 {
529 static const byte * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
530 u16 secstatus;
531 u32 status, upstcr, downstcr;
532
533 printf("PCI-X bridge device\n");
534
535 if (verbose < 2)
536 return;
537
538 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
539 return;
540
541 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
542 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
543 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
544 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
545 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
546 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
547 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
548 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
549 sec_clock_freq[(secstatus >> 6) & 7]);
550 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
551 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
552 ((status >> 8) & 0xff),
553 ((status >> 3) & 0x1f),
554 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
555 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
556 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
557 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
558 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
559 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
560 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
561 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
562 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
563 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
564 (upstcr >> 16) & 0xffff);
565 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
566 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
567 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
568 (downstcr >> 16) & 0xffff);
569 }
570
571 static void
572 show_pcix(struct device *d, int where)
573 {
574 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
575 {
576 case PCI_HEADER_TYPE_NORMAL:
577 show_pcix_nobridge(d, where);
578 break;
579 case PCI_HEADER_TYPE_BRIDGE:
580 show_pcix_bridge(d, where);
581 break;
582 }
583 }
584
585 static inline char *
586 ht_link_width(unsigned width)
587 {
588 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
589 return widths[width];
590 }
591
592 static inline char *
593 ht_link_freq(unsigned freq)
594 {
595 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
596 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
597 return freqs[freq];
598 }
599
600 static void
601 show_ht_pri(struct device *d, int where, int cmd)
602 {
603 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
604 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
605 char *fmt;
606
607 printf("HyperTransport: Slave or Primary Interface\n");
608 if (verbose < 2)
609 return;
610
611 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
612 return;
613 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
614 if (rid < 0x23 && rid > 0x11)
615 printf("\t\t!!! Possibly incomplete decoding\n");
616
617 if (rid >= 0x23)
618 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
619 else
620 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
621 printf(fmt,
622 (cmd & PCI_HT_PRI_CMD_BUID),
623 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
624 FLAG(cmd, PCI_HT_PRI_CMD_MH),
625 FLAG(cmd, PCI_HT_PRI_CMD_DD),
626 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
627 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
628 if (rid >= 0x23)
629 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
630 else
631 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
632 printf(fmt,
633 FLAG(lctr0, PCI_HT_LCTR_CFLE),
634 FLAG(lctr0, PCI_HT_LCTR_CST),
635 FLAG(lctr0, PCI_HT_LCTR_CFE),
636 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
637 FLAG(lctr0, PCI_HT_LCTR_INIT),
638 FLAG(lctr0, PCI_HT_LCTR_EOC),
639 FLAG(lctr0, PCI_HT_LCTR_TXO),
640 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
641 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
642 FLAG(lctr0, PCI_HT_LCTR_LSEN),
643 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
644 FLAG(lctr0, PCI_HT_LCTR_64B));
645 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
646 if (rid >= 0x23)
647 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
648 else
649 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
650 printf(fmt,
651 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
652 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
653 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
654 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
655 FLAG(lcnf0, PCI_HT_LCNF_DFI),
656 FLAG(lcnf0, PCI_HT_LCNF_DFO),
657 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
658 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
659 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
660 if (rid >= 0x23)
661 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
662 else
663 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
664 printf(fmt,
665 FLAG(lctr1, PCI_HT_LCTR_CFLE),
666 FLAG(lctr1, PCI_HT_LCTR_CST),
667 FLAG(lctr1, PCI_HT_LCTR_CFE),
668 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
669 FLAG(lctr1, PCI_HT_LCTR_INIT),
670 FLAG(lctr1, PCI_HT_LCTR_EOC),
671 FLAG(lctr1, PCI_HT_LCTR_TXO),
672 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
673 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
674 FLAG(lctr1, PCI_HT_LCTR_LSEN),
675 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
676 FLAG(lctr1, PCI_HT_LCTR_64B));
677 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
678 if (rid >= 0x23)
679 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
680 else
681 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
682 printf(fmt,
683 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
684 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
685 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
686 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
687 FLAG(lcnf1, PCI_HT_LCNF_DFI),
688 FLAG(lcnf1, PCI_HT_LCNF_DFO),
689 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
690 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
691 printf("\t\tRevision ID: %u.%02u\n",
692 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
693 if (rid < 0x23)
694 return;
695 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
696 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
697 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
698 FLAG(lfrer0, PCI_HT_LFRER_PROT),
699 FLAG(lfrer0, PCI_HT_LFRER_OV),
700 FLAG(lfrer0, PCI_HT_LFRER_EOC),
701 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
702 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
703 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
704 FLAG(lfcap0, PCI_HT_LFCAP_200),
705 FLAG(lfcap0, PCI_HT_LFCAP_300),
706 FLAG(lfcap0, PCI_HT_LFCAP_400),
707 FLAG(lfcap0, PCI_HT_LFCAP_500),
708 FLAG(lfcap0, PCI_HT_LFCAP_600),
709 FLAG(lfcap0, PCI_HT_LFCAP_800),
710 FLAG(lfcap0, PCI_HT_LFCAP_1000),
711 FLAG(lfcap0, PCI_HT_LFCAP_1200),
712 FLAG(lfcap0, PCI_HT_LFCAP_1400),
713 FLAG(lfcap0, PCI_HT_LFCAP_1600),
714 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
715 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
716 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
717 FLAG(ftr, PCI_HT_FTR_ISOCFC),
718 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
719 FLAG(ftr, PCI_HT_FTR_CRCTM),
720 FLAG(ftr, PCI_HT_FTR_ECTLT),
721 FLAG(ftr, PCI_HT_FTR_64BA),
722 FLAG(ftr, PCI_HT_FTR_UIDRD));
723 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
724 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
725 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
726 FLAG(lfrer1, PCI_HT_LFRER_PROT),
727 FLAG(lfrer1, PCI_HT_LFRER_OV),
728 FLAG(lfrer1, PCI_HT_LFRER_EOC),
729 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
730 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
731 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
732 FLAG(lfcap1, PCI_HT_LFCAP_200),
733 FLAG(lfcap1, PCI_HT_LFCAP_300),
734 FLAG(lfcap1, PCI_HT_LFCAP_400),
735 FLAG(lfcap1, PCI_HT_LFCAP_500),
736 FLAG(lfcap1, PCI_HT_LFCAP_600),
737 FLAG(lfcap1, PCI_HT_LFCAP_800),
738 FLAG(lfcap1, PCI_HT_LFCAP_1000),
739 FLAG(lfcap1, PCI_HT_LFCAP_1200),
740 FLAG(lfcap1, PCI_HT_LFCAP_1400),
741 FLAG(lfcap1, PCI_HT_LFCAP_1600),
742 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
743 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
744 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
745 FLAG(eh, PCI_HT_EH_PFLE),
746 FLAG(eh, PCI_HT_EH_OFLE),
747 FLAG(eh, PCI_HT_EH_PFE),
748 FLAG(eh, PCI_HT_EH_OFE),
749 FLAG(eh, PCI_HT_EH_EOCFE),
750 FLAG(eh, PCI_HT_EH_RFE),
751 FLAG(eh, PCI_HT_EH_CRCFE),
752 FLAG(eh, PCI_HT_EH_SERRFE),
753 FLAG(eh, PCI_HT_EH_CF),
754 FLAG(eh, PCI_HT_EH_RE),
755 FLAG(eh, PCI_HT_EH_PNFE),
756 FLAG(eh, PCI_HT_EH_ONFE),
757 FLAG(eh, PCI_HT_EH_EOCNFE),
758 FLAG(eh, PCI_HT_EH_RNFE),
759 FLAG(eh, PCI_HT_EH_CRCNFE),
760 FLAG(eh, PCI_HT_EH_SERRNFE));
761 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
762 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
763 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
764 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
765 printf("\t\tBus Number: %02x\n", bn);
766 }
767
768 static void
769 show_ht_sec(struct device *d, int where, int cmd)
770 {
771 u16 lctr, lcnf, ftr, eh;
772 u8 rid, lfrer, lfcap, mbu, mlu;
773 char *fmt;
774
775 printf("HyperTransport: Host or Secondary Interface\n");
776 if (verbose < 2)
777 return;
778
779 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
780 return;
781 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
782 if (rid < 0x23 && rid > 0x11)
783 printf("\t\t!!! Possibly incomplete decoding\n");
784
785 if (rid >= 0x23)
786 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
787 else
788 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
789 printf(fmt,
790 FLAG(cmd, PCI_HT_SEC_CMD_WR),
791 FLAG(cmd, PCI_HT_SEC_CMD_DE),
792 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
793 FLAG(cmd, PCI_HT_SEC_CMD_CS),
794 FLAG(cmd, PCI_HT_SEC_CMD_HH),
795 FLAG(cmd, PCI_HT_SEC_CMD_AS),
796 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
797 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
798 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
799 if (rid >= 0x23)
800 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
801 else
802 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
803 printf(fmt,
804 FLAG(lctr, PCI_HT_LCTR_CFLE),
805 FLAG(lctr, PCI_HT_LCTR_CST),
806 FLAG(lctr, PCI_HT_LCTR_CFE),
807 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
808 FLAG(lctr, PCI_HT_LCTR_INIT),
809 FLAG(lctr, PCI_HT_LCTR_EOC),
810 FLAG(lctr, PCI_HT_LCTR_TXO),
811 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
812 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
813 FLAG(lctr, PCI_HT_LCTR_LSEN),
814 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
815 FLAG(lctr, PCI_HT_LCTR_64B));
816 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
817 if (rid >= 0x23)
818 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
819 else
820 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
821 printf(fmt,
822 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
823 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
824 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
825 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
826 FLAG(lcnf, PCI_HT_LCNF_DFI),
827 FLAG(lcnf, PCI_HT_LCNF_DFO),
828 FLAG(lcnf, PCI_HT_LCNF_DFIE),
829 FLAG(lcnf, PCI_HT_LCNF_DFOE));
830 printf("\t\tRevision ID: %u.%02u\n",
831 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
832 if (rid < 0x23)
833 return;
834 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
835 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
836 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
837 FLAG(lfrer, PCI_HT_LFRER_PROT),
838 FLAG(lfrer, PCI_HT_LFRER_OV),
839 FLAG(lfrer, PCI_HT_LFRER_EOC),
840 FLAG(lfrer, PCI_HT_LFRER_CTLT));
841 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
842 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
843 FLAG(lfcap, PCI_HT_LFCAP_200),
844 FLAG(lfcap, PCI_HT_LFCAP_300),
845 FLAG(lfcap, PCI_HT_LFCAP_400),
846 FLAG(lfcap, PCI_HT_LFCAP_500),
847 FLAG(lfcap, PCI_HT_LFCAP_600),
848 FLAG(lfcap, PCI_HT_LFCAP_800),
849 FLAG(lfcap, PCI_HT_LFCAP_1000),
850 FLAG(lfcap, PCI_HT_LFCAP_1200),
851 FLAG(lfcap, PCI_HT_LFCAP_1400),
852 FLAG(lfcap, PCI_HT_LFCAP_1600),
853 FLAG(lfcap, PCI_HT_LFCAP_VEND));
854 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
855 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
856 FLAG(ftr, PCI_HT_FTR_ISOCFC),
857 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
858 FLAG(ftr, PCI_HT_FTR_CRCTM),
859 FLAG(ftr, PCI_HT_FTR_ECTLT),
860 FLAG(ftr, PCI_HT_FTR_64BA),
861 FLAG(ftr, PCI_HT_FTR_UIDRD),
862 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
863 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
864 if (ftr & PCI_HT_SEC_FTR_EXTRS)
865 {
866 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
867 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
868 FLAG(eh, PCI_HT_EH_PFLE),
869 FLAG(eh, PCI_HT_EH_OFLE),
870 FLAG(eh, PCI_HT_EH_PFE),
871 FLAG(eh, PCI_HT_EH_OFE),
872 FLAG(eh, PCI_HT_EH_EOCFE),
873 FLAG(eh, PCI_HT_EH_RFE),
874 FLAG(eh, PCI_HT_EH_CRCFE),
875 FLAG(eh, PCI_HT_EH_SERRFE),
876 FLAG(eh, PCI_HT_EH_CF),
877 FLAG(eh, PCI_HT_EH_RE),
878 FLAG(eh, PCI_HT_EH_PNFE),
879 FLAG(eh, PCI_HT_EH_ONFE),
880 FLAG(eh, PCI_HT_EH_EOCNFE),
881 FLAG(eh, PCI_HT_EH_RNFE),
882 FLAG(eh, PCI_HT_EH_CRCNFE),
883 FLAG(eh, PCI_HT_EH_SERRNFE));
884 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
885 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
886 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
887 }
888 }
889
890 static void
891 show_ht(struct device *d, int where, int cmd)
892 {
893 int type;
894
895 switch (cmd & PCI_HT_CMD_TYP_HI)
896 {
897 case PCI_HT_CMD_TYP_HI_PRI:
898 show_ht_pri(d, where, cmd);
899 return;
900 case PCI_HT_CMD_TYP_HI_SEC:
901 show_ht_sec(d, where, cmd);
902 return;
903 }
904
905 type = cmd & PCI_HT_CMD_TYP;
906 switch (type)
907 {
908 case PCI_HT_CMD_TYP_SW:
909 printf("HyperTransport: Switch\n");
910 break;
911 case PCI_HT_CMD_TYP_IDC:
912 printf("HyperTransport: Interrupt Discovery and Configuration\n");
913 break;
914 case PCI_HT_CMD_TYP_RID:
915 printf("HyperTransport: Revision ID: %u.%02u\n",
916 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
917 break;
918 case PCI_HT_CMD_TYP_UIDC:
919 printf("HyperTransport: UnitID Clumping\n");
920 break;
921 case PCI_HT_CMD_TYP_ECSA:
922 printf("HyperTransport: Extended Configuration Space Access\n");
923 break;
924 case PCI_HT_CMD_TYP_AM:
925 printf("HyperTransport: Address Mapping\n");
926 break;
927 case PCI_HT_CMD_TYP_MSIM:
928 printf("HyperTransport: MSI Mapping\n");
929 break;
930 case PCI_HT_CMD_TYP_DR:
931 printf("HyperTransport: DirectRoute\n");
932 break;
933 case PCI_HT_CMD_TYP_VCS:
934 printf("HyperTransport: VCSet\n");
935 break;
936 case PCI_HT_CMD_TYP_RM:
937 printf("HyperTransport: Retry Mode\n");
938 break;
939 case PCI_HT_CMD_TYP_X86:
940 printf("HyperTransport: X86 (reserved)\n");
941 break;
942 default:
943 printf("HyperTransport: #%02x\n", type >> 11);
944 }
945 }
946
947 static void
948 show_rom(struct device *d, int reg)
949 {
950 struct pci_dev *p = d->dev;
951 pciaddr_t rom = p->rom_base_addr;
952 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
953 u32 flg = get_conf_long(d, reg);
954 word cmd = get_conf_word(d, PCI_COMMAND);
955
956 if (!rom && !flg && !len)
957 return;
958 putchar('\t');
959 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
960 {
961 printf("[virtual] ");
962 flg = rom;
963 }
964 printf("Expansion ROM at ");
965 if (rom & PCI_ROM_ADDRESS_MASK)
966 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
967 else if (flg & PCI_ROM_ADDRESS_MASK)
968 printf("<ignored>");
969 else
970 printf("<unassigned>");
971 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
972 printf(" [disabled]");
973 else if (!(cmd & PCI_COMMAND_MEMORY))
974 printf(" [disabled by cmd]");
975 show_size(len);
976 putchar('\n');
977 }
978
979 static void
980 show_msi(struct device *d, int where, int cap)
981 {
982 int is64;
983 u32 t;
984 u16 w;
985
986 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
987 FLAG(cap, PCI_MSI_FLAGS_64BIT),
988 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
989 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
990 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
991 if (verbose < 2)
992 return;
993 is64 = cap & PCI_MSI_FLAGS_64BIT;
994 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
995 return;
996 printf("\t\tAddress: ");
997 if (is64)
998 {
999 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
1000 w = get_conf_word(d, where + PCI_MSI_DATA_64);
1001 printf("%08x", t);
1002 }
1003 else
1004 w = get_conf_word(d, where + PCI_MSI_DATA_32);
1005 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
1006 printf("%08x Data: %04x\n", t, w);
1007 }
1008
1009 static void show_vendor(void)
1010 {
1011 printf("Vendor Specific Information\n");
1012 }
1013
1014 static void show_debug(void)
1015 {
1016 printf("Debug port\n");
1017 }
1018
1019 static float power_limit(int value, int scale)
1020 {
1021 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
1022 return value * scales[scale];
1023 }
1024
1025 static const char *latency_l0s(int value)
1026 {
1027 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1028 return latencies[value];
1029 }
1030
1031 static const char *latency_l1(int value)
1032 {
1033 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1034 return latencies[value];
1035 }
1036
1037 static void show_express_dev(struct device *d, int where, int type)
1038 {
1039 u32 t;
1040 u16 w;
1041
1042 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1043 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
1044 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1045 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1046 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1047 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
1048 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1049 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1050 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1051 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1052 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
1053 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1054 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1055 if (type == PCI_EXP_TYPE_UPSTREAM)
1056 printf("\t\tDevice: SlotPowerLimit %f\n",
1057 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1058 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1059
1060 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1061 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1062 FLAG(w, PCI_EXP_DEVCTL_CERE),
1063 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1064 FLAG(w, PCI_EXP_DEVCTL_FERE),
1065 FLAG(w, PCI_EXP_DEVCTL_URRE));
1066 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
1067 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1068 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1069 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1070 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1071 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1072 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
1073 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1074 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1075 }
1076
1077 static char *link_speed(int speed)
1078 {
1079 switch (speed)
1080 {
1081 case 1:
1082 return "2.5Gb/s";
1083 default:
1084 return "unknown";
1085 }
1086 }
1087
1088 static char *aspm_support(int code)
1089 {
1090 switch (code)
1091 {
1092 case 1:
1093 return "L0s";
1094 case 3:
1095 return "L0s L1";
1096 default:
1097 return "unknown";
1098 }
1099 }
1100
1101 static const char *aspm_enabled(int code)
1102 {
1103 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1104 return desc[code];
1105 }
1106
1107 static void show_express_link(struct device *d, int where, int type)
1108 {
1109 u32 t;
1110 u16 w;
1111
1112 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1113 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1114 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1115 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1116 t >> 24);
1117 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1118 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1119 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1120 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1121 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1122 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1123 (type == PCI_EXP_TYPE_LEG_END))
1124 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1125 if (w & PCI_EXP_LNKCTL_DISABLE)
1126 printf(" Disabled");
1127 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1128 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1129 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1130 printf("\t\tLink: Speed %s, Width x%d\n",
1131 link_speed(t & PCI_EXP_LNKSTA_SPEED), (t & PCI_EXP_LNKSTA_WIDTH) >> 4);
1132 }
1133
1134 static const char *indicator(int code)
1135 {
1136 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1137 return names[code];
1138 }
1139
1140 static void show_express_slot(struct device *d, int where)
1141 {
1142 u32 t;
1143 u16 w;
1144
1145 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1146 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1147 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1148 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1149 FLAG(t, PCI_EXP_SLTCAP_MRL),
1150 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1151 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1152 FLAG(t, PCI_EXP_SLTCAP_HPC),
1153 FLAG(t, PCI_EXP_SLTCAP_HPS));
1154 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1155 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1156 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1157 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1158 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1159 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1160 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1161 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1162 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1163 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1164 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1165 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1166 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1167 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1168 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1169 }
1170
1171 static void show_express_root(struct device *d, int where)
1172 {
1173 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1174 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1175 FLAG(w, PCI_EXP_RTCTL_SECEE),
1176 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1177 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1178 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1179 }
1180
1181 static void
1182 show_express(struct device *d, int where, int cap)
1183 {
1184 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1185 int size;
1186 int slot = 0;
1187
1188 printf("Express ");
1189 switch (type)
1190 {
1191 case PCI_EXP_TYPE_ENDPOINT:
1192 printf("Endpoint");
1193 break;
1194 case PCI_EXP_TYPE_LEG_END:
1195 printf("Legacy Endpoint");
1196 break;
1197 case PCI_EXP_TYPE_ROOT_PORT:
1198 slot = cap & PCI_EXP_FLAGS_SLOT;
1199 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1200 break;
1201 case PCI_EXP_TYPE_UPSTREAM:
1202 printf("Upstream Port");
1203 break;
1204 case PCI_EXP_TYPE_DOWNSTREAM:
1205 slot = cap & PCI_EXP_FLAGS_SLOT;
1206 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1207 break;
1208 case PCI_EXP_TYPE_PCI_BRIDGE:
1209 printf("PCI/PCI-X Bridge");
1210 break;
1211 default:
1212 printf("Unknown type");
1213 }
1214 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1215 if (verbose < 2)
1216 return;
1217
1218 size = 16;
1219 if (slot)
1220 size = 24;
1221 if (type == PCI_EXP_TYPE_ROOT_PORT)
1222 size = 32;
1223 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1224 return;
1225
1226 show_express_dev(d, where, type);
1227 show_express_link(d, where, type);
1228 if (slot)
1229 show_express_slot(d, where);
1230 if (type == PCI_EXP_TYPE_ROOT_PORT)
1231 show_express_root(d, where);
1232 }
1233
1234 static void
1235 show_msix(struct device *d, int where, int cap)
1236 {
1237 u32 off;
1238
1239 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1240 FLAG(cap, PCI_MSIX_ENABLE),
1241 FLAG(cap, PCI_MSIX_MASK),
1242 (cap & PCI_MSIX_TABSIZE) + 1);
1243 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1244 return;
1245
1246 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1247 printf("\t\tVector table: BAR=%d offset=%08x\n",
1248 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1249 off = get_conf_long(d, where + PCI_MSIX_PBA);
1250 printf("\t\tPBA: BAR=%d offset=%08x\n",
1251 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1252 }
1253
1254 static void
1255 show_slotid(int cap)
1256 {
1257 int esr = cap & 0xff;
1258 int chs = cap >> 8;
1259
1260 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1261 esr & PCI_SID_ESR_NSLOTS,
1262 FLAG(esr, PCI_SID_ESR_FIC),
1263 chs);
1264 }
1265
1266 static void
1267 show_aer(struct device *d UNUSED, int where UNUSED)
1268 {
1269 printf("Advanced Error Reporting\n");
1270 }
1271
1272 static void
1273 show_vc(struct device *d UNUSED, int where UNUSED)
1274 {
1275 printf("Virtual Channel\n");
1276 }
1277
1278 static void
1279 show_dsn(struct device *d, int where)
1280 {
1281 u32 t1, t2;
1282 if (!config_fetch(d, where + 4, 8))
1283 return;
1284 t1 = get_conf_long(d, where + 4);
1285 t2 = get_conf_long(d, where + 8);
1286 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1287 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1288 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1289 }
1290
1291 static void
1292 show_pb(struct device *d UNUSED, int where UNUSED)
1293 {
1294 printf("Power Budgeting\n");
1295 }
1296
1297 static void
1298 show_ext_caps(struct device *d)
1299 {
1300 int where = 0x100;
1301 do
1302 {
1303 u32 header;
1304 int id;
1305
1306 if (!config_fetch(d, where, 4))
1307 break;
1308 header = get_conf_long(d, where);
1309 if (!header)
1310 break;
1311 id = header & 0xffff;
1312 printf("\tCapabilities: [%03x] ", where);
1313 switch (id)
1314 {
1315 case PCI_EXT_CAP_ID_AER:
1316 show_aer(d, where);
1317 break;
1318 case PCI_EXT_CAP_ID_VC:
1319 show_vc(d, where);
1320 break;
1321 case PCI_EXT_CAP_ID_DSN:
1322 show_dsn(d, where);
1323 break;
1324 case PCI_EXT_CAP_ID_PB:
1325 show_pb(d, where);
1326 break;
1327 default:
1328 printf("Unknown (%d)\n", id);
1329 break;
1330 }
1331 where = header >> 20;
1332 } while (where);
1333 }
1334
1335 static void
1336 show_caps(struct device *d)
1337 {
1338 int can_have_ext_caps = 0;
1339
1340 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1341 {
1342 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1343 while (where)
1344 {
1345 int id, next, cap;
1346 printf("\tCapabilities: ");
1347 if (!config_fetch(d, where, 4))
1348 {
1349 puts("<access denied>");
1350 break;
1351 }
1352 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1353 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1354 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1355 printf("[%02x] ", where);
1356 if (id == 0xff)
1357 {
1358 printf("<chain broken>\n");
1359 break;
1360 }
1361 switch (id)
1362 {
1363 case PCI_CAP_ID_PM:
1364 show_pm(d, where, cap);
1365 break;
1366 case PCI_CAP_ID_AGP:
1367 show_agp(d, where, cap);
1368 break;
1369 case PCI_CAP_ID_VPD:
1370 printf("Vital Product Data\n");
1371 break;
1372 case PCI_CAP_ID_SLOTID:
1373 show_slotid(cap);
1374 break;
1375 case PCI_CAP_ID_MSI:
1376 show_msi(d, where, cap);
1377 break;
1378 case PCI_CAP_ID_PCIX:
1379 show_pcix(d, where);
1380 can_have_ext_caps = 1;
1381 break;
1382 case PCI_CAP_ID_HT:
1383 show_ht(d, where, cap);
1384 break;
1385 case PCI_CAP_ID_VNDR:
1386 show_vendor();
1387 break;
1388 case PCI_CAP_ID_DBG:
1389 show_debug();
1390 break;
1391 case PCI_CAP_ID_EXP:
1392 show_express(d, where, cap);
1393 can_have_ext_caps = 1;
1394 break;
1395 case PCI_CAP_ID_MSIX:
1396 show_msix(d, where, cap);
1397 break;
1398 default:
1399 printf("#%02x [%04x]\n", id, cap);
1400 }
1401 where = next;
1402 }
1403 }
1404 if (can_have_ext_caps)
1405 show_ext_caps(d);
1406 }
1407
1408 static void
1409 show_htype0(struct device *d)
1410 {
1411 show_bases(d, 6);
1412 show_rom(d, PCI_ROM_ADDRESS);
1413 show_caps(d);
1414 }
1415
1416 static void
1417 show_htype1(struct device *d)
1418 {
1419 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1420 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1421 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1422 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1423 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1424 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1425 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1426 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1427 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1428 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1429 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1430 int verb = verbose > 2;
1431
1432 show_bases(d, 2);
1433 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1434 get_conf_byte(d, PCI_PRIMARY_BUS),
1435 get_conf_byte(d, PCI_SECONDARY_BUS),
1436 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1437 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1438
1439 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1440 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1441 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1442 else
1443 {
1444 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1445 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1446 if (io_type == PCI_IO_RANGE_TYPE_32)
1447 {
1448 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1449 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1450 }
1451 if (io_base <= io_limit || verb)
1452 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1453 }
1454
1455 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1456 mem_type)
1457 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1458 else
1459 {
1460 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1461 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1462 if (mem_base <= mem_limit || verb)
1463 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1464 }
1465
1466 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1467 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1468 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1469 else
1470 {
1471 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1472 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1473 if (pref_base <= pref_limit || verb)
1474 {
1475 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1476 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1477 else
1478 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1479 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1480 pref_base,
1481 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1482 pref_limit);
1483 }
1484 }
1485
1486 if (verbose > 1)
1487 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1488 FLAG(sec_stat, PCI_STATUS_66MHZ),
1489 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1490 FLAG(sec_stat, PCI_STATUS_PARITY),
1491 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1492 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1493 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1494 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1495 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1496 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1497 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1498 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1499
1500 show_rom(d, PCI_ROM_ADDRESS1);
1501
1502 if (verbose > 1)
1503 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1504 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1505 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1506 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1507 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1508 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1509 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1510 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1511
1512 show_caps(d);
1513 }
1514
1515 static void
1516 show_htype2(struct device *d)
1517 {
1518 int i;
1519 word cmd = get_conf_word(d, PCI_COMMAND);
1520 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1521 word exca;
1522 int verb = verbose > 2;
1523
1524 show_bases(d, 1);
1525 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1526 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1527 get_conf_byte(d, PCI_CB_CARD_BUS),
1528 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1529 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1530 for(i=0; i<2; i++)
1531 {
1532 int p = 8*i;
1533 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1534 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1535 if (limit > base || verb)
1536 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1537 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1538 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1539 }
1540 for(i=0; i<2; i++)
1541 {
1542 int p = 8*i;
1543 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1544 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1545 if (!(base & PCI_IO_RANGE_TYPE_32))
1546 {
1547 base &= 0xffff;
1548 limit &= 0xffff;
1549 }
1550 base &= PCI_CB_IO_RANGE_MASK;
1551 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1552 if (base <= limit || verb)
1553 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1554 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1555 }
1556
1557 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1558 printf("\tSecondary status: SERR\n");
1559 if (verbose > 1)
1560 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1561 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1562 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1563 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1564 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1565 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1566 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1567 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1568 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1569
1570 if (d->config_cached < 128)
1571 {
1572 printf("\t<access denied to the rest>\n");
1573 return;
1574 }
1575
1576 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1577 if (exca)
1578 printf("\t16-bit legacy interface ports at %04x\n", exca);
1579 }
1580
1581 static void
1582 show_verbose(struct device *d)
1583 {
1584 struct pci_dev *p = d->dev;
1585 word status = get_conf_word(d, PCI_STATUS);
1586 word cmd = get_conf_word(d, PCI_COMMAND);
1587 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1588 byte bist = get_conf_byte(d, PCI_BIST);
1589 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1590 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1591 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1592 byte max_lat, min_gnt;
1593 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1594 unsigned int irq = p->irq;
1595 word subsys_v = 0, subsys_d = 0;
1596 char ssnamebuf[256];
1597
1598 show_terse(d);
1599
1600 switch (htype)
1601 {
1602 case PCI_HEADER_TYPE_NORMAL:
1603 if (class == PCI_CLASS_BRIDGE_PCI)
1604 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1605 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1606 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1607 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1608 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1609 break;
1610 case PCI_HEADER_TYPE_BRIDGE:
1611 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1612 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1613 irq = int_pin = min_gnt = max_lat = 0;
1614 break;
1615 case PCI_HEADER_TYPE_CARDBUS:
1616 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1617 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1618 min_gnt = max_lat = 0;
1619 if (d->config_cached >= 128)
1620 {
1621 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1622 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1623 }
1624 break;
1625 default:
1626 printf("\t!!! Unknown header type %02x\n", htype);
1627 return;
1628 }
1629
1630 if (subsys_v && subsys_v != 0xffff)
1631 printf("\tSubsystem: %s\n",
1632 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1633 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1634 p->vendor_id, p->device_id, subsys_v, subsys_d));
1635
1636 if (verbose > 1)
1637 {
1638 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1639 FLAG(cmd, PCI_COMMAND_IO),
1640 FLAG(cmd, PCI_COMMAND_MEMORY),
1641 FLAG(cmd, PCI_COMMAND_MASTER),
1642 FLAG(cmd, PCI_COMMAND_SPECIAL),
1643 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1644 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1645 FLAG(cmd, PCI_COMMAND_PARITY),
1646 FLAG(cmd, PCI_COMMAND_WAIT),
1647 FLAG(cmd, PCI_COMMAND_SERR),
1648 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1649 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1650 FLAG(status, PCI_STATUS_CAP_LIST),
1651 FLAG(status, PCI_STATUS_66MHZ),
1652 FLAG(status, PCI_STATUS_UDF),
1653 FLAG(status, PCI_STATUS_FAST_BACK),
1654 FLAG(status, PCI_STATUS_PARITY),
1655 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1656 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1657 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1658 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1659 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1660 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1661 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1662 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1663 if (cmd & PCI_COMMAND_MASTER)
1664 {
1665 printf("\tLatency: %d", latency);
1666 if (min_gnt || max_lat)
1667 {
1668 printf(" (");
1669 if (min_gnt)
1670 printf("%dns min", min_gnt*250);
1671 if (min_gnt && max_lat)
1672 printf(", ");
1673 if (max_lat)
1674 printf("%dns max", max_lat*250);
1675 putchar(')');
1676 }
1677 if (cache_line)
1678 printf(", Cache Line Size %02x", cache_line);
1679 putchar('\n');
1680 }
1681 if (int_pin || irq)
1682 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1683 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1684 }
1685 else
1686 {
1687 printf("\tFlags: ");
1688 if (cmd & PCI_COMMAND_MASTER)
1689 printf("bus master, ");
1690 if (cmd & PCI_COMMAND_VGA_PALETTE)
1691 printf("VGA palette snoop, ");
1692 if (cmd & PCI_COMMAND_WAIT)
1693 printf("stepping, ");
1694 if (cmd & PCI_COMMAND_FAST_BACK)
1695 printf("fast Back2Back, ");
1696 if (status & PCI_STATUS_66MHZ)
1697 printf("66MHz, ");
1698 if (status & PCI_STATUS_UDF)
1699 printf("user-definable features, ");
1700 printf("%s devsel",
1701 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1702 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1703 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1704 if (cmd & PCI_COMMAND_MASTER)
1705 printf(", latency %d", latency);
1706 if (irq)
1707 printf(", IRQ " PCIIRQ_FMT, irq);
1708 putchar('\n');
1709 }
1710
1711 if (bist & PCI_BIST_CAPABLE)
1712 {
1713 if (bist & PCI_BIST_START)
1714 printf("\tBIST is running\n");
1715 else
1716 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1717 }
1718
1719 switch (htype)
1720 {
1721 case PCI_HEADER_TYPE_NORMAL:
1722 show_htype0(d);
1723 break;
1724 case PCI_HEADER_TYPE_BRIDGE:
1725 show_htype1(d);
1726 break;
1727 case PCI_HEADER_TYPE_CARDBUS:
1728 show_htype2(d);
1729 break;
1730 }
1731 }
1732
1733 static void
1734 show_hex_dump(struct device *d)
1735 {
1736 unsigned int i, cnt;
1737
1738 cnt = d->config_cached;
1739 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1740 {
1741 cnt = 256;
1742 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1743 cnt = 4096;
1744 }
1745
1746 for(i=0; i<cnt; i++)
1747 {
1748 if (! (i & 15))
1749 printf("%02x:", i);
1750 printf(" %02x", get_conf_byte(d, i));
1751 if ((i & 15) == 15)
1752 putchar('\n');
1753 }
1754 }
1755
1756 static void
1757 show_machine(struct device *d)
1758 {
1759 struct pci_dev *p = d->dev;
1760 int c;
1761 word sv_id=0, sd_id=0;
1762 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1763
1764 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1765 {
1766 case PCI_HEADER_TYPE_NORMAL:
1767 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1768 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1769 break;
1770 case PCI_HEADER_TYPE_CARDBUS:
1771 if (d->config_cached >= 128)
1772 {
1773 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1774 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1775 }
1776 break;
1777 }
1778
1779 if (verbose)
1780 {
1781 printf("Device:\t");
1782 show_slot_name(d);
1783 putchar('\n');
1784 printf("Class:\t%s\n",
1785 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0));
1786 printf("Vendor:\t%s\n",
1787 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, 0, 0));
1788 printf("Device:\t%s\n",
1789 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, 0, 0));
1790 if (sv_id && sv_id != 0xffff)
1791 {
1792 printf("SVendor:\t%s\n",
1793 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id));
1794 printf("SDevice:\t%s\n",
1795 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1796 }
1797 if (c = get_conf_byte(d, PCI_REVISION_ID))
1798 printf("Rev:\t%02x\n", c);
1799 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1800 printf("ProgIf:\t%02x\n", c);
1801 }
1802 else
1803 {
1804 show_slot_name(d);
1805 printf(" \"%s\" \"%s\" \"%s\"",
1806 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1807 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
1808 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1809 p->vendor_id, p->device_id, 0, 0),
1810 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1811 p->vendor_id, p->device_id, 0, 0));
1812 if (c = get_conf_byte(d, PCI_REVISION_ID))
1813 printf(" -r%02x", c);
1814 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1815 printf(" -p%02x", c);
1816 if (sv_id && sv_id != 0xffff)
1817 printf(" \"%s\" \"%s\"",
1818 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id),
1819 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1820 else
1821 printf(" \"\" \"\"");
1822 putchar('\n');
1823 }
1824 }
1825
1826 static void
1827 show_device(struct device *d)
1828 {
1829 if (machine_readable)
1830 show_machine(d);
1831 else if (verbose)
1832 show_verbose(d);
1833 else
1834 show_terse(d);
1835 if (show_hex)
1836 show_hex_dump(d);
1837 if (verbose || show_hex)
1838 putchar('\n');
1839 }
1840
1841 static void
1842 show(void)
1843 {
1844 struct device *d;
1845
1846 for(d=first_dev; d; d=d->next)
1847 show_device(d);
1848 }
1849
1850 /* Tree output */
1851
1852 struct bridge {
1853 struct bridge *chain; /* Single-linked list of bridges */
1854 struct bridge *next, *child; /* Tree of bridges */
1855 struct bus *first_bus; /* List of buses connected to this bridge */
1856 unsigned int domain;
1857 unsigned int primary, secondary, subordinate; /* Bus numbers */
1858 struct device *br_dev;
1859 };
1860
1861 struct bus {
1862 unsigned int domain;
1863 unsigned int number;
1864 struct bus *sibling;
1865 struct device *first_dev, **last_dev;
1866 };
1867
1868 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1869
1870 static struct bus *
1871 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1872 {
1873 struct bus *bus;
1874
1875 for(bus=b->first_bus; bus; bus=bus->sibling)
1876 if (bus->domain == domain && bus->number == n)
1877 break;
1878 return bus;
1879 }
1880
1881 static struct bus *
1882 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1883 {
1884 struct bus *bus = xmalloc(sizeof(struct bus));
1885
1886 bus = xmalloc(sizeof(struct bus));
1887 bus->domain = domain;
1888 bus->number = n;
1889 bus->sibling = b->first_bus;
1890 bus->first_dev = NULL;
1891 bus->last_dev = &bus->first_dev;
1892 b->first_bus = bus;
1893 return bus;
1894 }
1895
1896 static void
1897 insert_dev(struct device *d, struct bridge *b)
1898 {
1899 struct pci_dev *p = d->dev;
1900 struct bus *bus;
1901
1902 if (! (bus = find_bus(b, p->domain, p->bus)))
1903 {
1904 struct bridge *c;
1905 for(c=b->child; c; c=c->next)
1906 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1907 {
1908 insert_dev(d, c);
1909 return;
1910 }
1911 bus = new_bus(b, p->domain, p->bus);
1912 }
1913 /* Simple insertion at the end _does_ guarantee the correct order as the
1914 * original device list was sorted by (domain, bus, devfn) lexicographically
1915 * and all devices on the new list have the same bus number.
1916 */
1917 *bus->last_dev = d;
1918 bus->last_dev = &d->next;
1919 d->next = NULL;
1920 }
1921
1922 static void
1923 grow_tree(void)
1924 {
1925 struct device *d, *d2;
1926 struct bridge **last_br, *b;
1927
1928 /* Build list of bridges */
1929
1930 last_br = &host_bridge.chain;
1931 for(d=first_dev; d; d=d->next)
1932 {
1933 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1934 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1935 if (class == PCI_CLASS_BRIDGE_PCI &&
1936 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1937 {
1938 b = xmalloc(sizeof(struct bridge));
1939 b->domain = d->dev->domain;
1940 if (ht == PCI_HEADER_TYPE_BRIDGE)
1941 {
1942 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1943 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1944 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1945 }
1946 else
1947 {
1948 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1949 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1950 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1951 }
1952 *last_br = b;
1953 last_br = &b->chain;
1954 b->next = b->child = NULL;
1955 b->first_bus = NULL;
1956 b->br_dev = d;
1957 }
1958 }
1959 *last_br = NULL;
1960
1961 /* Create a bridge tree */
1962
1963 for(b=&host_bridge; b; b=b->chain)
1964 {
1965 struct bridge *c, *best;
1966 best = NULL;
1967 for(c=&host_bridge; c; c=c->chain)
1968 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1969 b->primary >= c->secondary && b->primary <= c->subordinate &&
1970 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1971 best = c;
1972 if (best)
1973 {
1974 b->next = best->child;
1975 best->child = b;
1976 }
1977 }
1978
1979 /* Insert secondary bus for each bridge */
1980
1981 for(b=&host_bridge; b; b=b->chain)
1982 if (!find_bus(b, b->domain, b->secondary))
1983 new_bus(b, b->domain, b->secondary);
1984
1985 /* Create bus structs and link devices */
1986
1987 for(d=first_dev; d;)
1988 {
1989 d2 = d->next;
1990 insert_dev(d, &host_bridge);
1991 d = d2;
1992 }
1993 }
1994
1995 static void
1996 print_it(byte *line, byte *p)
1997 {
1998 *p++ = '\n';
1999 *p = 0;
2000 fputs(line, stdout);
2001 for(p=line; *p; p++)
2002 if (*p == '+' || *p == '|')
2003 *p = '|';
2004 else
2005 *p = ' ';
2006 }
2007
2008 static void show_tree_bridge(struct bridge *, byte *, byte *);
2009
2010 static void
2011 show_tree_dev(struct device *d, byte *line, byte *p)
2012 {
2013 struct pci_dev *q = d->dev;
2014 struct bridge *b;
2015 char namebuf[256];
2016
2017 p += sprintf(p, "%02x.%x", q->dev, q->func);
2018 for(b=&host_bridge; b; b=b->chain)
2019 if (b->br_dev == d)
2020 {
2021 if (b->secondary == b->subordinate)
2022 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2023 else
2024 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2025 show_tree_bridge(b, line, p);
2026 return;
2027 }
2028 if (verbose)
2029 p += sprintf(p, " %s",
2030 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2031 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2032 q->vendor_id, q->device_id, 0, 0));
2033 print_it(line, p);
2034 }
2035
2036 static void
2037 show_tree_bus(struct bus *b, byte *line, byte *p)
2038 {
2039 if (!b->first_dev)
2040 print_it(line, p);
2041 else if (!b->first_dev->next)
2042 {
2043 *p++ = '-';
2044 *p++ = '-';
2045 show_tree_dev(b->first_dev, line, p);
2046 }
2047 else
2048 {
2049 struct device *d = b->first_dev;
2050 while (d->next)
2051 {
2052 p[0] = '+';
2053 p[1] = '-';
2054 show_tree_dev(d, line, p+2);
2055 d = d->next;
2056 }
2057 p[0] = '\\';
2058 p[1] = '-';
2059 show_tree_dev(d, line, p+2);
2060 }
2061 }
2062
2063 static void
2064 show_tree_bridge(struct bridge *b, byte *line, byte *p)
2065 {
2066 *p++ = '-';
2067 if (!b->first_bus->sibling)
2068 {
2069 if (b == &host_bridge)
2070 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2071 show_tree_bus(b->first_bus, line, p);
2072 }
2073 else
2074 {
2075 struct bus *u = b->first_bus;
2076 byte *k;
2077
2078 while (u->sibling)
2079 {
2080 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2081 show_tree_bus(u, line, k);
2082 u = u->sibling;
2083 }
2084 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2085 show_tree_bus(u, line, k);
2086 }
2087 }
2088
2089 static void
2090 show_forest(void)
2091 {
2092 char line[256];
2093
2094 grow_tree();
2095 show_tree_bridge(&host_bridge, line, line);
2096 }
2097
2098 /* Bus mapping mode */
2099
2100 struct bus_bridge {
2101 struct bus_bridge *next;
2102 byte this, dev, func, first, last, bug;
2103 };
2104
2105 struct bus_info {
2106 byte exists;
2107 byte guestbook;
2108 struct bus_bridge *bridges, *via;
2109 };
2110
2111 static struct bus_info *bus_info;
2112
2113 static void
2114 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2115 {
2116 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2117 struct pci_dev *p = d->dev;
2118
2119 b->next = bi->bridges;
2120 bi->bridges = b;
2121 b->this = get_conf_byte(d, np);
2122 b->dev = p->dev;
2123 b->func = p->func;
2124 b->first = get_conf_byte(d, ns);
2125 b->last = get_conf_byte(d, nl);
2126 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2127 p->bus, p->dev, p->func, b->this, b->first, b->last);
2128 if (b->this != p->bus)
2129 printf("!!! Bridge points to invalid primary bus.\n");
2130 if (b->first > b->last)
2131 {
2132 printf("!!! Bridge points to invalid bus range.\n");
2133 b->last = b->first;
2134 }
2135 }
2136
2137 static void
2138 do_map_bus(int bus)
2139 {
2140 int dev, func;
2141 int verbose = pacc->debugging;
2142 struct bus_info *bi = bus_info + bus;
2143 struct device *d;
2144
2145 if (verbose)
2146 printf("Mapping bus %02x\n", bus);
2147 for(dev = 0; dev < 32; dev++)
2148 if (filter.slot < 0 || filter.slot == dev)
2149 {
2150 int func_limit = 1;
2151 for(func = 0; func < func_limit; func++)
2152 if (filter.func < 0 || filter.func == func)
2153 {
2154 /* XXX: Bus mapping supports only domain 0 */
2155 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2156 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2157 if (vendor && vendor != 0xffff)
2158 {
2159 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2160 func_limit = 8;
2161 if (verbose)
2162 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2163 bi->exists = 1;
2164 if (d = scan_device(p))
2165 {
2166 show_device(d);
2167 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2168 {
2169 case PCI_HEADER_TYPE_BRIDGE:
2170 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2171 break;
2172 case PCI_HEADER_TYPE_CARDBUS:
2173 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2174 break;
2175 }
2176 free(d);
2177 }
2178 else if (verbose)
2179 printf("But it was filtered out.\n");
2180 }
2181 pci_free_dev(p);
2182 }
2183 }
2184 }
2185
2186 static void
2187 do_map_bridges(int bus, int min, int max)
2188 {
2189 struct bus_info *bi = bus_info + bus;
2190 struct bus_bridge *b;
2191
2192 bi->guestbook = 1;
2193 for(b=bi->bridges; b; b=b->next)
2194 {
2195 if (bus_info[b->first].guestbook)
2196 b->bug = 1;
2197 else if (b->first < min || b->last > max)
2198 b->bug = 2;
2199 else
2200 {
2201 bus_info[b->first].via = b;
2202 do_map_bridges(b->first, b->first, b->last);
2203 }
2204 }
2205 }
2206
2207 static void
2208 map_bridges(void)
2209 {
2210 int i;
2211
2212 printf("\nSummary of buses:\n\n");
2213 for(i=0; i<256; i++)
2214 if (bus_info[i].exists && !bus_info[i].guestbook)
2215 do_map_bridges(i, 0, 255);
2216 for(i=0; i<256; i++)
2217 {
2218 struct bus_info *bi = bus_info + i;
2219 struct bus_bridge *b = bi->via;
2220
2221 if (bi->exists)
2222 {
2223 printf("%02x: ", i);
2224 if (b)
2225 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2226 else if (!i)
2227 printf("Primary host bus\n");
2228 else
2229 printf("Secondary host bus (?)\n");
2230 }
2231 for(b=bi->bridges; b; b=b->next)
2232 {
2233 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2234 switch (b->bug)
2235 {
2236 case 1:
2237 printf(" <overlap bug>");
2238 break;
2239 case 2:
2240 printf(" <crossing bug>");
2241 break;
2242 }
2243 putchar('\n');
2244 }
2245 }
2246 }
2247
2248 static void
2249 map_the_bus(void)
2250 {
2251 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2252 pacc->method == PCI_ACCESS_DUMP)
2253 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2254 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2255 bzero(bus_info, sizeof(struct bus_info) * 256);
2256 if (filter.bus >= 0)
2257 do_map_bus(filter.bus);
2258 else
2259 {
2260 int bus;
2261 for(bus=0; bus<256; bus++)
2262 do_map_bus(bus);
2263 }
2264 map_bridges();
2265 }
2266
2267 /* Main */
2268
2269 int
2270 main(int argc, char **argv)
2271 {
2272 int i;
2273 char *msg;
2274
2275 if (argc == 2 && !strcmp(argv[1], "--version"))
2276 {
2277 puts("lspci version " PCIUTILS_VERSION);
2278 return 0;
2279 }
2280
2281 pacc = pci_alloc();
2282 pacc->error = die;
2283 pci_filter_init(pacc, &filter);
2284
2285 while ((i = getopt(argc, argv, options)) != -1)
2286 switch (i)
2287 {
2288 case 'n':
2289 pacc->numeric_ids = 1;
2290 break;
2291 case 'v':
2292 verbose++;
2293 break;
2294 case 'b':
2295 pacc->buscentric = 1;
2296 buscentric_view = 1;
2297 break;
2298 case 's':
2299 if (msg = pci_filter_parse_slot(&filter, optarg))
2300 die("-s: %s", msg);
2301 break;
2302 case 'd':
2303 if (msg = pci_filter_parse_id(&filter, optarg))
2304 die("-d: %s", msg);
2305 break;
2306 case 'x':
2307 show_hex++;
2308 break;
2309 case 't':
2310 show_tree++;
2311 break;
2312 case 'i':
2313 pacc->id_file_name = optarg;
2314 break;
2315 case 'm':
2316 machine_readable++;
2317 break;
2318 case 'M':
2319 map_mode++;
2320 break;
2321 default:
2322 if (parse_generic_option(i, pacc, optarg))
2323 break;
2324 bad:
2325 fprintf(stderr, help_msg, pacc->id_file_name);
2326 return 1;
2327 }
2328 if (optind < argc)
2329 goto bad;
2330
2331 pci_init(pacc);
2332 if (map_mode)
2333 map_the_bus();
2334 else
2335 {
2336 scan_devices();
2337 sort_them();
2338 if (show_tree)
2339 show_forest();
2340 else
2341 show();
2342 }
2343 pci_cleanup(pacc);
2344
2345 return 0;
2346 }
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