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Alternative Routing-ID Interpretation capability support
[thirdparty/pciutils.git] / lspci.c
1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #define PCIUTILS_LSPCI
16 #include "pciutils.h"
17
18 /* Options */
19
20 static int verbose; /* Show detailed information */
21 static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
22 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
23 static struct pci_filter filter; /* Device filter */
24 static int opt_tree; /* Show bus tree */
25 static int opt_machine; /* Generate machine-readable output */
26 static int opt_map_mode; /* Bus mapping mode enabled */
27 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
28 static int opt_kernel; /* Show kernel drivers */
29 static int opt_query_dns; /* Query the DNS (0=disabled, 1=enabled, 2=refresh cache) */
30 static int opt_query_all; /* Query the DNS for all entries */
31 static char *opt_pcimap; /* Override path to Linux modules.pcimap */
32
33 const char program_name[] = "lspci";
34
35 static char options[] = "nvbxs:d:ti:mgp:qkMDQ" GENERIC_OPTIONS ;
36
37 static char help_msg[] =
38 "Usage: lspci [<switches>]\n"
39 "\n"
40 "Basic display modes:\n"
41 "-mm\t\tProduce machine-readable output (single -m for an obsolete format)\n"
42 "-t\t\tShow bus tree\n"
43 "\n"
44 "Display options:\n"
45 "-v\t\tBe verbose (-vv for very verbose)\n"
46 #ifdef PCI_OS_LINUX
47 "-k\t\tShow kernel drivers handling each device\n"
48 #endif
49 "-x\t\tShow hex-dump of the standard part of the config space\n"
50 "-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
51 "-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
52 "-b\t\tBus-centric view (addresses and IRQ's as seen by the bus)\n"
53 "-D\t\tAlways show domain numbers\n"
54 "\n"
55 "Resolving of device ID's to names:\n"
56 "-n\t\tShow numeric ID's\n"
57 "-nn\t\tShow both textual and numeric ID's (names & numbers)\n"
58 #ifdef PCI_USE_DNS
59 "-q\t\tQuery the PCI ID database for unknown ID's via DNS\n"
60 "-qq\t\tAs above, but re-query locally cached entries\n"
61 "-Q\t\tQuery the PCI ID database for all ID's via DNS\n"
62 #endif
63 "\n"
64 "Selection of devices:\n"
65 "-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n"
66 "-d [<vendor>]:[<device>]\t\t\tShow only devices with specified ID's\n"
67 "\n"
68 "Other options:\n"
69 "-i <file>\tUse specified ID database instead of %s\n"
70 #ifdef PCI_OS_LINUX
71 "-p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
72 #endif
73 "-M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
74 "\n"
75 "PCI access options:\n"
76 GENERIC_HELP
77 ;
78
79 /*** Communication with libpci ***/
80
81 static struct pci_access *pacc;
82
83 /*
84 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
85 * This increases our memory footprint, but only slightly since we don't
86 * use alloca() much.
87 */
88 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
89 /* alloca() is defined in stdlib.h */
90 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
91 #include <alloca.h>
92 #else
93 #undef alloca
94 #define alloca xmalloc
95 #endif
96
97 /*** Our view of the PCI bus ***/
98
99 struct device {
100 struct device *next;
101 struct pci_dev *dev;
102 unsigned int config_cached, config_bufsize;
103 byte *config; /* Cached configuration space data */
104 byte *present; /* Maps which configuration bytes are present */
105 };
106
107 static struct device *first_dev;
108 static int seen_errors;
109
110 static int
111 config_fetch(struct device *d, unsigned int pos, unsigned int len)
112 {
113 unsigned int end = pos+len;
114 int result;
115
116 while (pos < d->config_bufsize && len && d->present[pos])
117 pos++, len--;
118 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
119 len--;
120 if (!len)
121 return 1;
122
123 if (end > d->config_bufsize)
124 {
125 int orig_size = d->config_bufsize;
126 while (end > d->config_bufsize)
127 d->config_bufsize *= 2;
128 d->config = xrealloc(d->config, d->config_bufsize);
129 d->present = xrealloc(d->present, d->config_bufsize);
130 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
131 }
132 result = pci_read_block(d->dev, pos, d->config + pos, len);
133 if (result)
134 memset(d->present + pos, 1, len);
135 return result;
136 }
137
138 static struct device *
139 scan_device(struct pci_dev *p)
140 {
141 struct device *d;
142
143 if (p->domain && !opt_domains)
144 opt_domains = 1;
145 if (!pci_filter_match(&filter, p))
146 return NULL;
147 d = xmalloc(sizeof(struct device));
148 memset(d, 0, sizeof(*d));
149 d->dev = p;
150 d->config_cached = d->config_bufsize = 64;
151 d->config = xmalloc(64);
152 d->present = xmalloc(64);
153 memset(d->present, 1, 64);
154 if (!pci_read_block(p, 0, d->config, 64))
155 {
156 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
157 p->domain, p->bus, p->dev, p->func);
158 seen_errors++;
159 return NULL;
160 }
161 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
162 {
163 /* For cardbus bridges, we need to fetch 64 bytes more to get the
164 * full standard header... */
165 if (config_fetch(d, 64, 64))
166 d->config_cached += 64;
167 }
168 pci_setup_cache(p, d->config, d->config_cached);
169 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
170 return d;
171 }
172
173 static void
174 scan_devices(void)
175 {
176 struct device *d;
177 struct pci_dev *p;
178
179 pci_scan_bus(pacc);
180 for(p=pacc->devices; p; p=p->next)
181 if (d = scan_device(p))
182 {
183 d->next = first_dev;
184 first_dev = d;
185 }
186 }
187
188 /*** Config space accesses ***/
189
190 static void
191 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
192 {
193 while (len)
194 if (!d->present[pos])
195 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
196 else
197 pos++, len--;
198 }
199
200 static inline byte
201 get_conf_byte(struct device *d, unsigned int pos)
202 {
203 check_conf_range(d, pos, 1);
204 return d->config[pos];
205 }
206
207 static word
208 get_conf_word(struct device *d, unsigned int pos)
209 {
210 check_conf_range(d, pos, 2);
211 return d->config[pos] | (d->config[pos+1] << 8);
212 }
213
214 static u32
215 get_conf_long(struct device *d, unsigned int pos)
216 {
217 check_conf_range(d, pos, 4);
218 return d->config[pos] |
219 (d->config[pos+1] << 8) |
220 (d->config[pos+2] << 16) |
221 (d->config[pos+3] << 24);
222 }
223
224 /*** Sorting ***/
225
226 static int
227 compare_them(const void *A, const void *B)
228 {
229 const struct pci_dev *a = (*(const struct device **)A)->dev;
230 const struct pci_dev *b = (*(const struct device **)B)->dev;
231
232 if (a->domain < b->domain)
233 return -1;
234 if (a->domain > b->domain)
235 return 1;
236 if (a->bus < b->bus)
237 return -1;
238 if (a->bus > b->bus)
239 return 1;
240 if (a->dev < b->dev)
241 return -1;
242 if (a->dev > b->dev)
243 return 1;
244 if (a->func < b->func)
245 return -1;
246 if (a->func > b->func)
247 return 1;
248 return 0;
249 }
250
251 static void
252 sort_them(void)
253 {
254 struct device **index, **h, **last_dev;
255 int cnt;
256 struct device *d;
257
258 cnt = 0;
259 for(d=first_dev; d; d=d->next)
260 cnt++;
261 h = index = alloca(sizeof(struct device *) * cnt);
262 for(d=first_dev; d; d=d->next)
263 *h++ = d;
264 qsort(index, cnt, sizeof(struct device *), compare_them);
265 last_dev = &first_dev;
266 h = index;
267 while (cnt--)
268 {
269 *last_dev = *h;
270 last_dev = &(*h)->next;
271 h++;
272 }
273 *last_dev = NULL;
274 }
275
276 /*** Normal output ***/
277
278 #define FLAG(x,y) ((x & y) ? '+' : '-')
279
280 static void
281 show_slot_name(struct device *d)
282 {
283 struct pci_dev *p = d->dev;
284
285 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
286 printf("%04x:", p->domain);
287 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
288 }
289
290 static void
291 show_terse(struct device *d)
292 {
293 int c;
294 struct pci_dev *p = d->dev;
295 char classbuf[128], devbuf[128];
296
297 show_slot_name(d);
298 printf(" %s: %s",
299 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
300 PCI_LOOKUP_CLASS,
301 p->device_class),
302 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
303 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
304 p->vendor_id, p->device_id));
305 if (c = get_conf_byte(d, PCI_REVISION_ID))
306 printf(" (rev %02x)", c);
307 if (verbose)
308 {
309 char *x;
310 c = get_conf_byte(d, PCI_CLASS_PROG);
311 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
312 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
313 p->device_class, c);
314 if (c || x)
315 {
316 printf(" (prog-if %02x", c);
317 if (x)
318 printf(" [%s]", x);
319 putchar(')');
320 }
321 }
322 putchar('\n');
323 }
324
325 static void
326 get_subid(struct device *d, word *subvp, word *subdp)
327 {
328 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
329
330 if (htype == PCI_HEADER_TYPE_NORMAL)
331 {
332 *subvp = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
333 *subdp = get_conf_word(d, PCI_SUBSYSTEM_ID);
334 }
335 else if (htype == PCI_HEADER_TYPE_CARDBUS && d->config_cached >= 128)
336 {
337 *subvp = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
338 *subdp = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
339 }
340 else
341 *subvp = *subdp = 0xffff;
342 }
343
344 /*** Capabilities ***/
345
346 static void
347 cap_pm(struct device *d, int where, int cap)
348 {
349 int t, b;
350 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
351
352 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
353 if (verbose < 2)
354 return;
355 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
356 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
357 FLAG(cap, PCI_PM_CAP_DSI),
358 FLAG(cap, PCI_PM_CAP_D1),
359 FLAG(cap, PCI_PM_CAP_D2),
360 pm_aux_current[(cap >> 6) & 7],
361 FLAG(cap, PCI_PM_CAP_PME_D0),
362 FLAG(cap, PCI_PM_CAP_PME_D1),
363 FLAG(cap, PCI_PM_CAP_PME_D2),
364 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
365 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
366 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
367 return;
368 t = get_conf_word(d, where + PCI_PM_CTRL);
369 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
370 t & PCI_PM_CTRL_STATE_MASK,
371 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
372 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
373 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
374 FLAG(t, PCI_PM_CTRL_PME_STATUS));
375 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
376 if (b)
377 printf("\t\tBridge: PM%c B3%c\n",
378 FLAG(t, PCI_PM_BPCC_ENABLE),
379 FLAG(~t, PCI_PM_PPB_B2_B3));
380 }
381
382 static void
383 format_agp_rate(int rate, char *buf, int agp3)
384 {
385 char *c = buf;
386 int i;
387
388 for(i=0; i<=2; i++)
389 if (rate & (1 << i))
390 {
391 if (c != buf)
392 *c++ = ',';
393 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
394 }
395 if (c != buf)
396 *c = 0;
397 else
398 strcpy(buf, "<none>");
399 }
400
401 static void
402 cap_agp(struct device *d, int where, int cap)
403 {
404 u32 t;
405 char rate[16];
406 int ver, rev;
407 int agp3 = 0;
408
409 ver = (cap >> 4) & 0x0f;
410 rev = cap & 0x0f;
411 printf("AGP version %x.%x\n", ver, rev);
412 if (verbose < 2)
413 return;
414 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
415 return;
416 t = get_conf_long(d, where + PCI_AGP_STATUS);
417 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
418 agp3 = 1;
419 format_agp_rate(t & 7, rate, agp3);
420 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
421 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
422 FLAG(t, PCI_AGP_STATUS_ISOCH),
423 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
424 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
425 FLAG(t, PCI_AGP_STATUS_SBA),
426 FLAG(t, PCI_AGP_STATUS_ITA_COH),
427 FLAG(t, PCI_AGP_STATUS_GART64),
428 FLAG(t, PCI_AGP_STATUS_HTRANS),
429 FLAG(t, PCI_AGP_STATUS_64BIT),
430 FLAG(t, PCI_AGP_STATUS_FW),
431 FLAG(t, PCI_AGP_STATUS_AGP3),
432 rate);
433 t = get_conf_long(d, where + PCI_AGP_COMMAND);
434 format_agp_rate(t & 7, rate, agp3);
435 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
436 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
437 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
438 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
439 FLAG(t, PCI_AGP_COMMAND_SBA),
440 FLAG(t, PCI_AGP_COMMAND_AGP),
441 FLAG(t, PCI_AGP_COMMAND_GART64),
442 FLAG(t, PCI_AGP_COMMAND_64BIT),
443 FLAG(t, PCI_AGP_COMMAND_FW),
444 rate);
445 }
446
447 static void
448 cap_pcix_nobridge(struct device *d, int where)
449 {
450 u16 command;
451 u32 status;
452 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
453
454 printf("PCI-X non-bridge device\n");
455
456 if (verbose < 2)
457 return;
458
459 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
460 return;
461
462 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
463 status = get_conf_long(d, where + PCI_PCIX_STATUS);
464 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
465 FLAG(command, PCI_PCIX_COMMAND_DPERE),
466 FLAG(command, PCI_PCIX_COMMAND_ERO),
467 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
468 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
469 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
470 ((status >> 8) & 0xff),
471 ((status >> 3) & 0x1f),
472 (status & PCI_PCIX_STATUS_FUNCTION),
473 FLAG(status, PCI_PCIX_STATUS_64BIT),
474 FLAG(status, PCI_PCIX_STATUS_133MHZ),
475 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
476 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
477 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
478 1 << (9 + ((status >> 21) & 3U)),
479 max_outstanding[(status >> 23) & 7U],
480 1 << (3 + ((status >> 26) & 7U)),
481 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
482 FLAG(status, PCI_PCIX_STATUS_266MHZ),
483 FLAG(status, PCI_PCIX_STATUS_533MHZ));
484 }
485
486 static void
487 cap_pcix_bridge(struct device *d, int where)
488 {
489 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
490 u16 secstatus;
491 u32 status, upstcr, downstcr;
492
493 printf("PCI-X bridge device\n");
494
495 if (verbose < 2)
496 return;
497
498 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
499 return;
500
501 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
502 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
503 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
504 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
505 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
506 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
507 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
508 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
509 sec_clock_freq[(secstatus >> 6) & 7]);
510 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
511 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
512 ((status >> 8) & 0xff),
513 ((status >> 3) & 0x1f),
514 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
515 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
516 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
517 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
518 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
519 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
520 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
521 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
522 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
523 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
524 (upstcr >> 16) & 0xffff);
525 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
526 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
527 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
528 (downstcr >> 16) & 0xffff);
529 }
530
531 static void
532 cap_pcix(struct device *d, int where)
533 {
534 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
535 {
536 case PCI_HEADER_TYPE_NORMAL:
537 cap_pcix_nobridge(d, where);
538 break;
539 case PCI_HEADER_TYPE_BRIDGE:
540 cap_pcix_bridge(d, where);
541 break;
542 }
543 }
544
545 static inline char *
546 ht_link_width(unsigned width)
547 {
548 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
549 return widths[width];
550 }
551
552 static inline char *
553 ht_link_freq(unsigned freq)
554 {
555 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
556 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
557 return freqs[freq];
558 }
559
560 static void
561 cap_ht_pri(struct device *d, int where, int cmd)
562 {
563 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
564 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
565 char *fmt;
566
567 printf("HyperTransport: Slave or Primary Interface\n");
568 if (verbose < 2)
569 return;
570
571 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
572 return;
573 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
574 if (rid < 0x23 && rid > 0x11)
575 printf("\t\t!!! Possibly incomplete decoding\n");
576
577 if (rid >= 0x23)
578 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
579 else
580 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
581 printf(fmt,
582 (cmd & PCI_HT_PRI_CMD_BUID),
583 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
584 FLAG(cmd, PCI_HT_PRI_CMD_MH),
585 FLAG(cmd, PCI_HT_PRI_CMD_DD),
586 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
587 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
588 if (rid >= 0x23)
589 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
590 else
591 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
592 printf(fmt,
593 FLAG(lctr0, PCI_HT_LCTR_CFLE),
594 FLAG(lctr0, PCI_HT_LCTR_CST),
595 FLAG(lctr0, PCI_HT_LCTR_CFE),
596 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
597 FLAG(lctr0, PCI_HT_LCTR_INIT),
598 FLAG(lctr0, PCI_HT_LCTR_EOC),
599 FLAG(lctr0, PCI_HT_LCTR_TXO),
600 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
601 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
602 FLAG(lctr0, PCI_HT_LCTR_LSEN),
603 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
604 FLAG(lctr0, PCI_HT_LCTR_64B));
605 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
606 if (rid >= 0x23)
607 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
608 else
609 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
610 printf(fmt,
611 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
612 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
613 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
614 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
615 FLAG(lcnf0, PCI_HT_LCNF_DFI),
616 FLAG(lcnf0, PCI_HT_LCNF_DFO),
617 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
618 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
619 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
620 if (rid >= 0x23)
621 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
622 else
623 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
624 printf(fmt,
625 FLAG(lctr1, PCI_HT_LCTR_CFLE),
626 FLAG(lctr1, PCI_HT_LCTR_CST),
627 FLAG(lctr1, PCI_HT_LCTR_CFE),
628 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
629 FLAG(lctr1, PCI_HT_LCTR_INIT),
630 FLAG(lctr1, PCI_HT_LCTR_EOC),
631 FLAG(lctr1, PCI_HT_LCTR_TXO),
632 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
633 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
634 FLAG(lctr1, PCI_HT_LCTR_LSEN),
635 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
636 FLAG(lctr1, PCI_HT_LCTR_64B));
637 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
638 if (rid >= 0x23)
639 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
640 else
641 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
642 printf(fmt,
643 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
644 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
645 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
646 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
647 FLAG(lcnf1, PCI_HT_LCNF_DFI),
648 FLAG(lcnf1, PCI_HT_LCNF_DFO),
649 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
650 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
651 printf("\t\tRevision ID: %u.%02u\n",
652 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
653 if (rid < 0x23)
654 return;
655 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
656 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
657 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
658 FLAG(lfrer0, PCI_HT_LFRER_PROT),
659 FLAG(lfrer0, PCI_HT_LFRER_OV),
660 FLAG(lfrer0, PCI_HT_LFRER_EOC),
661 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
662 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
663 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
664 FLAG(lfcap0, PCI_HT_LFCAP_200),
665 FLAG(lfcap0, PCI_HT_LFCAP_300),
666 FLAG(lfcap0, PCI_HT_LFCAP_400),
667 FLAG(lfcap0, PCI_HT_LFCAP_500),
668 FLAG(lfcap0, PCI_HT_LFCAP_600),
669 FLAG(lfcap0, PCI_HT_LFCAP_800),
670 FLAG(lfcap0, PCI_HT_LFCAP_1000),
671 FLAG(lfcap0, PCI_HT_LFCAP_1200),
672 FLAG(lfcap0, PCI_HT_LFCAP_1400),
673 FLAG(lfcap0, PCI_HT_LFCAP_1600),
674 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
675 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
676 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
677 FLAG(ftr, PCI_HT_FTR_ISOCFC),
678 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
679 FLAG(ftr, PCI_HT_FTR_CRCTM),
680 FLAG(ftr, PCI_HT_FTR_ECTLT),
681 FLAG(ftr, PCI_HT_FTR_64BA),
682 FLAG(ftr, PCI_HT_FTR_UIDRD));
683 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
684 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
685 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
686 FLAG(lfrer1, PCI_HT_LFRER_PROT),
687 FLAG(lfrer1, PCI_HT_LFRER_OV),
688 FLAG(lfrer1, PCI_HT_LFRER_EOC),
689 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
690 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
691 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
692 FLAG(lfcap1, PCI_HT_LFCAP_200),
693 FLAG(lfcap1, PCI_HT_LFCAP_300),
694 FLAG(lfcap1, PCI_HT_LFCAP_400),
695 FLAG(lfcap1, PCI_HT_LFCAP_500),
696 FLAG(lfcap1, PCI_HT_LFCAP_600),
697 FLAG(lfcap1, PCI_HT_LFCAP_800),
698 FLAG(lfcap1, PCI_HT_LFCAP_1000),
699 FLAG(lfcap1, PCI_HT_LFCAP_1200),
700 FLAG(lfcap1, PCI_HT_LFCAP_1400),
701 FLAG(lfcap1, PCI_HT_LFCAP_1600),
702 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
703 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
704 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
705 FLAG(eh, PCI_HT_EH_PFLE),
706 FLAG(eh, PCI_HT_EH_OFLE),
707 FLAG(eh, PCI_HT_EH_PFE),
708 FLAG(eh, PCI_HT_EH_OFE),
709 FLAG(eh, PCI_HT_EH_EOCFE),
710 FLAG(eh, PCI_HT_EH_RFE),
711 FLAG(eh, PCI_HT_EH_CRCFE),
712 FLAG(eh, PCI_HT_EH_SERRFE),
713 FLAG(eh, PCI_HT_EH_CF),
714 FLAG(eh, PCI_HT_EH_RE),
715 FLAG(eh, PCI_HT_EH_PNFE),
716 FLAG(eh, PCI_HT_EH_ONFE),
717 FLAG(eh, PCI_HT_EH_EOCNFE),
718 FLAG(eh, PCI_HT_EH_RNFE),
719 FLAG(eh, PCI_HT_EH_CRCNFE),
720 FLAG(eh, PCI_HT_EH_SERRNFE));
721 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
722 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
723 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
724 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
725 printf("\t\tBus Number: %02x\n", bn);
726 }
727
728 static void
729 cap_ht_sec(struct device *d, int where, int cmd)
730 {
731 u16 lctr, lcnf, ftr, eh;
732 u8 rid, lfrer, lfcap, mbu, mlu;
733 char *fmt;
734
735 printf("HyperTransport: Host or Secondary Interface\n");
736 if (verbose < 2)
737 return;
738
739 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
740 return;
741 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
742 if (rid < 0x23 && rid > 0x11)
743 printf("\t\t!!! Possibly incomplete decoding\n");
744
745 if (rid >= 0x23)
746 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
747 else
748 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
749 printf(fmt,
750 FLAG(cmd, PCI_HT_SEC_CMD_WR),
751 FLAG(cmd, PCI_HT_SEC_CMD_DE),
752 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
753 FLAG(cmd, PCI_HT_SEC_CMD_CS),
754 FLAG(cmd, PCI_HT_SEC_CMD_HH),
755 FLAG(cmd, PCI_HT_SEC_CMD_AS),
756 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
757 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
758 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
759 if (rid >= 0x23)
760 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
761 else
762 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
763 printf(fmt,
764 FLAG(lctr, PCI_HT_LCTR_CFLE),
765 FLAG(lctr, PCI_HT_LCTR_CST),
766 FLAG(lctr, PCI_HT_LCTR_CFE),
767 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
768 FLAG(lctr, PCI_HT_LCTR_INIT),
769 FLAG(lctr, PCI_HT_LCTR_EOC),
770 FLAG(lctr, PCI_HT_LCTR_TXO),
771 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
772 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
773 FLAG(lctr, PCI_HT_LCTR_LSEN),
774 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
775 FLAG(lctr, PCI_HT_LCTR_64B));
776 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
777 if (rid >= 0x23)
778 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
779 else
780 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
781 printf(fmt,
782 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
783 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
784 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
785 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
786 FLAG(lcnf, PCI_HT_LCNF_DFI),
787 FLAG(lcnf, PCI_HT_LCNF_DFO),
788 FLAG(lcnf, PCI_HT_LCNF_DFIE),
789 FLAG(lcnf, PCI_HT_LCNF_DFOE));
790 printf("\t\tRevision ID: %u.%02u\n",
791 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
792 if (rid < 0x23)
793 return;
794 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
795 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
796 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
797 FLAG(lfrer, PCI_HT_LFRER_PROT),
798 FLAG(lfrer, PCI_HT_LFRER_OV),
799 FLAG(lfrer, PCI_HT_LFRER_EOC),
800 FLAG(lfrer, PCI_HT_LFRER_CTLT));
801 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
802 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
803 FLAG(lfcap, PCI_HT_LFCAP_200),
804 FLAG(lfcap, PCI_HT_LFCAP_300),
805 FLAG(lfcap, PCI_HT_LFCAP_400),
806 FLAG(lfcap, PCI_HT_LFCAP_500),
807 FLAG(lfcap, PCI_HT_LFCAP_600),
808 FLAG(lfcap, PCI_HT_LFCAP_800),
809 FLAG(lfcap, PCI_HT_LFCAP_1000),
810 FLAG(lfcap, PCI_HT_LFCAP_1200),
811 FLAG(lfcap, PCI_HT_LFCAP_1400),
812 FLAG(lfcap, PCI_HT_LFCAP_1600),
813 FLAG(lfcap, PCI_HT_LFCAP_VEND));
814 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
815 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
816 FLAG(ftr, PCI_HT_FTR_ISOCFC),
817 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
818 FLAG(ftr, PCI_HT_FTR_CRCTM),
819 FLAG(ftr, PCI_HT_FTR_ECTLT),
820 FLAG(ftr, PCI_HT_FTR_64BA),
821 FLAG(ftr, PCI_HT_FTR_UIDRD),
822 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
823 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
824 if (ftr & PCI_HT_SEC_FTR_EXTRS)
825 {
826 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
827 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
828 FLAG(eh, PCI_HT_EH_PFLE),
829 FLAG(eh, PCI_HT_EH_OFLE),
830 FLAG(eh, PCI_HT_EH_PFE),
831 FLAG(eh, PCI_HT_EH_OFE),
832 FLAG(eh, PCI_HT_EH_EOCFE),
833 FLAG(eh, PCI_HT_EH_RFE),
834 FLAG(eh, PCI_HT_EH_CRCFE),
835 FLAG(eh, PCI_HT_EH_SERRFE),
836 FLAG(eh, PCI_HT_EH_CF),
837 FLAG(eh, PCI_HT_EH_RE),
838 FLAG(eh, PCI_HT_EH_PNFE),
839 FLAG(eh, PCI_HT_EH_ONFE),
840 FLAG(eh, PCI_HT_EH_EOCNFE),
841 FLAG(eh, PCI_HT_EH_RNFE),
842 FLAG(eh, PCI_HT_EH_CRCNFE),
843 FLAG(eh, PCI_HT_EH_SERRNFE));
844 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
845 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
846 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
847 }
848 }
849
850 static void
851 cap_ht(struct device *d, int where, int cmd)
852 {
853 int type;
854
855 switch (cmd & PCI_HT_CMD_TYP_HI)
856 {
857 case PCI_HT_CMD_TYP_HI_PRI:
858 cap_ht_pri(d, where, cmd);
859 return;
860 case PCI_HT_CMD_TYP_HI_SEC:
861 cap_ht_sec(d, where, cmd);
862 return;
863 }
864
865 type = cmd & PCI_HT_CMD_TYP;
866 switch (type)
867 {
868 case PCI_HT_CMD_TYP_SW:
869 printf("HyperTransport: Switch\n");
870 break;
871 case PCI_HT_CMD_TYP_IDC:
872 printf("HyperTransport: Interrupt Discovery and Configuration\n");
873 break;
874 case PCI_HT_CMD_TYP_RID:
875 printf("HyperTransport: Revision ID: %u.%02u\n",
876 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
877 break;
878 case PCI_HT_CMD_TYP_UIDC:
879 printf("HyperTransport: UnitID Clumping\n");
880 break;
881 case PCI_HT_CMD_TYP_ECSA:
882 printf("HyperTransport: Extended Configuration Space Access\n");
883 break;
884 case PCI_HT_CMD_TYP_AM:
885 printf("HyperTransport: Address Mapping\n");
886 break;
887 case PCI_HT_CMD_TYP_MSIM:
888 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
889 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
890 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
891 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
892 {
893 u32 offl, offh;
894 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
895 break;
896 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
897 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
898 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
899 }
900 break;
901 case PCI_HT_CMD_TYP_DR:
902 printf("HyperTransport: DirectRoute\n");
903 break;
904 case PCI_HT_CMD_TYP_VCS:
905 printf("HyperTransport: VCSet\n");
906 break;
907 case PCI_HT_CMD_TYP_RM:
908 printf("HyperTransport: Retry Mode\n");
909 break;
910 case PCI_HT_CMD_TYP_X86:
911 printf("HyperTransport: X86 (reserved)\n");
912 break;
913 default:
914 printf("HyperTransport: #%02x\n", type >> 11);
915 }
916 }
917
918 static void
919 cap_msi(struct device *d, int where, int cap)
920 {
921 int is64;
922 u32 t;
923 u16 w;
924
925 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
926 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
927 FLAG(cap, PCI_MSI_FLAGS_64BIT),
928 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
929 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
930 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
931 if (verbose < 2)
932 return;
933 is64 = cap & PCI_MSI_FLAGS_64BIT;
934 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
935 return;
936 printf("\t\tAddress: ");
937 if (is64)
938 {
939 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
940 w = get_conf_word(d, where + PCI_MSI_DATA_64);
941 printf("%08x", t);
942 }
943 else
944 w = get_conf_word(d, where + PCI_MSI_DATA_32);
945 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
946 printf("%08x Data: %04x\n", t, w);
947 if (cap & PCI_MSI_FLAGS_MASK_BIT)
948 {
949 u32 mask, pending;
950
951 if (is64)
952 {
953 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
954 return;
955 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
956 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
957 }
958 else
959 {
960 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
961 return;
962 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
963 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
964 }
965 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
966 }
967 }
968
969 static float power_limit(int value, int scale)
970 {
971 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
972 return value * scales[scale];
973 }
974
975 static const char *latency_l0s(int value)
976 {
977 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
978 return latencies[value];
979 }
980
981 static const char *latency_l1(int value)
982 {
983 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
984 return latencies[value];
985 }
986
987 static void cap_express_dev(struct device *d, int where, int type)
988 {
989 u32 t;
990 u16 w;
991
992 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
993 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
994 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
995 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
996 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
997 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
998 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
999 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1000 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1001 printf(" AttnBtn%c AttnInd%c PwrInd%c",
1002 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1003 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1004 printf(" RBE%c FLReset%c",
1005 FLAG(t, PCI_EXP_DEVCAP_RBE),
1006 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
1007 if (type == PCI_EXP_TYPE_UPSTREAM)
1008 printf("SlotPowerLimit %fW",
1009 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1010 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1011 printf("\n");
1012
1013 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1014 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1015 FLAG(w, PCI_EXP_DEVCTL_CERE),
1016 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1017 FLAG(w, PCI_EXP_DEVCTL_FERE),
1018 FLAG(w, PCI_EXP_DEVCTL_URRE));
1019 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
1020 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1021 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1022 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1023 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1024 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1025 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
1026 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
1027 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
1028 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
1029 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
1030 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1031 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1032
1033 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
1034 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
1035 FLAG(w, PCI_EXP_DEVSTA_CED),
1036 FLAG(w, PCI_EXP_DEVSTA_NFED),
1037 FLAG(w, PCI_EXP_DEVSTA_FED),
1038 FLAG(w, PCI_EXP_DEVSTA_URD),
1039 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
1040 FLAG(w, PCI_EXP_DEVSTA_TRPND));
1041 }
1042
1043 static char *link_speed(int speed)
1044 {
1045 switch (speed)
1046 {
1047 case 1:
1048 return "2.5GT/s";
1049 case 2:
1050 return "5GT/s";
1051 default:
1052 return "unknown";
1053 }
1054 }
1055
1056 static char *aspm_support(int code)
1057 {
1058 switch (code)
1059 {
1060 case 1:
1061 return "L0s";
1062 case 3:
1063 return "L0s L1";
1064 default:
1065 return "unknown";
1066 }
1067 }
1068
1069 static const char *aspm_enabled(int code)
1070 {
1071 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1072 return desc[code];
1073 }
1074
1075 static void cap_express_link(struct device *d, int where, int type)
1076 {
1077 u32 t;
1078 u16 w;
1079
1080 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1081 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1082 t >> 24,
1083 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1084 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1085 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1086 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1087 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1088 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1089 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1090 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1091 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1092
1093 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1094 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1095 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1096 (type == PCI_EXP_TYPE_LEG_END))
1097 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1098 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1099 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1100 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1101 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1102 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1103 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1104 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1105 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1106 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1107
1108 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1109 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1110 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1111 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1112 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1113 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1114 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1115 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1116 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1117 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1118 }
1119
1120 static const char *indicator(int code)
1121 {
1122 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1123 return names[code];
1124 }
1125
1126 static void cap_express_slot(struct device *d, int where)
1127 {
1128 u32 t;
1129 u16 w;
1130
1131 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1132 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1133 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1134 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1135 FLAG(t, PCI_EXP_SLTCAP_MRL),
1136 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1137 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1138 FLAG(t, PCI_EXP_SLTCAP_HPC),
1139 FLAG(t, PCI_EXP_SLTCAP_HPS));
1140 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1141 t >> 19,
1142 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1143 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1144 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1145
1146 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1147 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1148 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1149 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1150 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1151 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1152 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1153 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1154 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1155 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1156 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1157 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1158 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1159 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1160
1161 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1162 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1163 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1164 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1165 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1166 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1167 FLAG(w, PCI_EXP_SLTSTA_PRES),
1168 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1169 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1170 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1171 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1172 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1173 }
1174
1175 static void cap_express_root(struct device *d, int where)
1176 {
1177 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1178 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1179 FLAG(w, PCI_EXP_RTCTL_SECEE),
1180 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1181 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1182 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1183 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1184
1185 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1186 printf("\t\tRootCap: CRSVisible%c\n",
1187 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1188
1189 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1190 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1191 w & PCI_EXP_RTSTA_PME_REQID,
1192 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1193 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1194 }
1195
1196 static const char *cap_express_dev2_timeout_range(int type)
1197 {
1198 /* Decode Completion Timeout Ranges. */
1199 switch (type)
1200 {
1201 case 0:
1202 return "Not Supported";
1203 case 1:
1204 return "Range A";
1205 case 2:
1206 return "Range B";
1207 case 3:
1208 return "Range AB";
1209 case 6:
1210 return "Range BC";
1211 case 7:
1212 return "Range ABC";
1213 case 14:
1214 return "Range BCD";
1215 case 15:
1216 return "Range ABCD";
1217 default:
1218 return "Unknown";
1219 }
1220 }
1221
1222 static const char *cap_express_dev2_timeout_value(int type)
1223 {
1224 /* Decode Completion Timeout Value. */
1225 switch (type)
1226 {
1227 case 0:
1228 return "50us to 50ms";
1229 case 1:
1230 return "50us to 100us";
1231 case 2:
1232 return "1ms to 10ms";
1233 case 5:
1234 return "16ms to 55ms";
1235 case 6:
1236 return "65ms to 210ms";
1237 case 9:
1238 return "260ms to 900ms";
1239 case 10:
1240 return "1s to 3.5s";
1241 case 13:
1242 return "4s to 13s";
1243 case 14:
1244 return "17s to 64s";
1245 default:
1246 return "Unknown";
1247 }
1248 }
1249
1250 static void cap_express_dev2(struct device *d, int where, int type)
1251 {
1252 u32 l;
1253 u16 w;
1254
1255 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1256 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c",
1257 cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
1258 FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS));
1259 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1260 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
1261 else
1262 printf("\n");
1263
1264 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1265 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
1266 cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
1267 FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS));
1268 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1269 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
1270 else
1271 printf("\n");
1272 }
1273
1274 static const char *cap_express_link2_speed(int type)
1275 {
1276 switch (type)
1277 {
1278 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1279 case 1:
1280 return "2.5GT/s";
1281 case 2:
1282 return "5GT/s";
1283 default:
1284 return "Unknown";
1285 }
1286 }
1287
1288 static const char *cap_express_link2_deemphasis(int type)
1289 {
1290 switch (type)
1291 {
1292 case 0:
1293 return "-6dB";
1294 case 1:
1295 return "-3.5dB";
1296 default:
1297 return "Unknown";
1298 }
1299 }
1300
1301 static const char *cap_express_link2_transmargin(int type)
1302 {
1303 switch (type)
1304 {
1305 case 0:
1306 return "Normal Operating Range";
1307 case 1:
1308 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1309 case 2:
1310 case 3:
1311 case 4:
1312 case 5:
1313 return "200-400mV(full-swing)/100-200mV(half-swing)";
1314 default:
1315 return "Unknown";
1316 }
1317 }
1318
1319 static void cap_express_link2(struct device *d, int where, int type UNUSED)
1320 {
1321 u16 w;
1322
1323 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1324 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
1325 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1326 "\t\t\t Compliance De-emphasis: %s\n",
1327 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1328 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1329 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
1330 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
1331 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1332 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1333 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1334 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1335
1336 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1337 printf("\t\tLnkSta2: Current De-emphasis Level: %s\n",
1338 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)));
1339 }
1340
1341 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1342 {
1343 /* No capabilities that require this field in PCIe rev2.0 spec. */
1344 }
1345
1346 static void
1347 cap_express(struct device *d, int where, int cap)
1348 {
1349 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1350 int size;
1351 int slot = 0;
1352
1353 printf("Express ");
1354 if (verbose >= 2)
1355 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1356 switch (type)
1357 {
1358 case PCI_EXP_TYPE_ENDPOINT:
1359 printf("Endpoint");
1360 break;
1361 case PCI_EXP_TYPE_LEG_END:
1362 printf("Legacy Endpoint");
1363 break;
1364 case PCI_EXP_TYPE_ROOT_PORT:
1365 slot = cap & PCI_EXP_FLAGS_SLOT;
1366 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1367 break;
1368 case PCI_EXP_TYPE_UPSTREAM:
1369 printf("Upstream Port");
1370 break;
1371 case PCI_EXP_TYPE_DOWNSTREAM:
1372 slot = cap & PCI_EXP_FLAGS_SLOT;
1373 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1374 break;
1375 case PCI_EXP_TYPE_PCI_BRIDGE:
1376 printf("PCI/PCI-X Bridge");
1377 break;
1378 case PCI_EXP_TYPE_PCIE_BRIDGE:
1379 printf("PCI/PCI-X to PCI-Express Bridge");
1380 break;
1381 case PCI_EXP_TYPE_ROOT_INT_EP:
1382 printf("Root Complex Integrated Endpoint");
1383 break;
1384 case PCI_EXP_TYPE_ROOT_EC:
1385 printf("Root Complex Event Collector");
1386 break;
1387 default:
1388 printf("Unknown type %d", type);
1389 }
1390 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1391 if (verbose < 2)
1392 return;
1393
1394 size = 16;
1395 if (slot)
1396 size = 24;
1397 if (type == PCI_EXP_TYPE_ROOT_PORT)
1398 size = 32;
1399 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1400 return;
1401
1402 cap_express_dev(d, where, type);
1403 cap_express_link(d, where, type);
1404 if (slot)
1405 cap_express_slot(d, where);
1406 if (type == PCI_EXP_TYPE_ROOT_PORT)
1407 cap_express_root(d, where);
1408
1409 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1410 return;
1411
1412 size = 16;
1413 if (slot)
1414 size = 24;
1415 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1416 return;
1417
1418 cap_express_dev2(d, where, type);
1419 cap_express_link2(d, where, type);
1420 if (slot)
1421 cap_express_slot2(d, where);
1422 }
1423
1424 static void
1425 cap_msix(struct device *d, int where, int cap)
1426 {
1427 u32 off;
1428
1429 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1430 FLAG(cap, PCI_MSIX_ENABLE),
1431 FLAG(cap, PCI_MSIX_MASK),
1432 (cap & PCI_MSIX_TABSIZE) + 1);
1433 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1434 return;
1435
1436 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1437 printf("\t\tVector table: BAR=%d offset=%08x\n",
1438 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1439 off = get_conf_long(d, where + PCI_MSIX_PBA);
1440 printf("\t\tPBA: BAR=%d offset=%08x\n",
1441 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1442 }
1443
1444 static void
1445 cap_slotid(int cap)
1446 {
1447 int esr = cap & 0xff;
1448 int chs = cap >> 8;
1449
1450 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1451 esr & PCI_SID_ESR_NSLOTS,
1452 FLAG(esr, PCI_SID_ESR_FIC),
1453 chs);
1454 }
1455
1456 static void
1457 cap_ssvid(struct device *d, int where)
1458 {
1459 u16 subsys_v, subsys_d;
1460 char ssnamebuf[256];
1461
1462 if (!config_fetch(d, where, 8))
1463 return;
1464 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1465 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1466 printf("Subsystem: %s\n",
1467 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1468 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1469 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1470 }
1471
1472 static void
1473 cap_dsn(struct device *d, int where)
1474 {
1475 u32 t1, t2;
1476 if (!config_fetch(d, where + 4, 8))
1477 return;
1478 t1 = get_conf_long(d, where + 4);
1479 t2 = get_conf_long(d, where + 8);
1480 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1481 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1482 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1483 }
1484
1485 static void
1486 cap_debug_port(int cap)
1487 {
1488 int bar = cap >> 13;
1489 int pos = cap & 0x1fff;
1490 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1491 }
1492
1493 static void
1494 cap_aer(struct device *d, int where)
1495 {
1496 u32 l;
1497
1498 printf("Advanced Error Reporting\n");
1499 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
1500 return;
1501
1502 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
1503 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1504 "MalfTLP%c ECRC%c UnsupReq%c ACSVoil%c\n",
1505 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1506 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1507 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1508 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1509 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
1510 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1511 "MalfTLP%c ECRC%c UnsupReq%c ACSVoil%c\n",
1512 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1513 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1514 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1515 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1516 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
1517 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1518 "MalfTLP%c ECRC%c UnsupReq%c ACSVoil%c\n",
1519 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1520 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1521 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1522 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1523 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
1524 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
1525 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
1526 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
1527 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
1528 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
1529 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
1530 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
1531 l = get_conf_long(d, where + PCI_ERR_CAP);
1532 printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
1533 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
1534 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
1535
1536 }
1537
1538 static void
1539 cap_acs(struct device *d, int where)
1540 {
1541 u16 w;
1542
1543 printf("Access Control Services\n");
1544 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
1545 return;
1546
1547 w = get_conf_word(d, where + PCI_ACS_CAP);
1548 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
1549 "DirectTrans%c\n",
1550 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
1551 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
1552 FLAG(w, PCI_ACS_CAP_TRANS));
1553 w = get_conf_word(d, where + PCI_ACS_CTRL);
1554 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
1555 "DirectTrans%c\n",
1556 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
1557 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
1558 FLAG(w, PCI_ACS_CTRL_TRANS));
1559 }
1560
1561 static void
1562 cap_ari(struct device *d, int where)
1563 {
1564 u16 w;
1565
1566 printf("Alternative Routing-ID Interpretation (ARI)\n");
1567 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
1568 return;
1569
1570 w = get_conf_word(d, where + PCI_ARI_CAP);
1571 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
1572 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
1573 PCI_ARI_CAP_NFN(w));
1574 w = get_conf_word(d, where + PCI_ARI_CTRL);
1575 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
1576 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
1577 PCI_ARI_CTRL_FG(w));
1578 }
1579
1580 static void
1581 show_ext_caps(struct device *d)
1582 {
1583 int where = 0x100;
1584 char been_there[0x1000];
1585 memset(been_there, 0, 0x1000);
1586 do
1587 {
1588 u32 header;
1589 int id;
1590
1591 if (!config_fetch(d, where, 4))
1592 break;
1593 header = get_conf_long(d, where);
1594 if (!header)
1595 break;
1596 id = header & 0xffff;
1597 printf("\tCapabilities: [%03x] ", where);
1598 if (been_there[where]++)
1599 {
1600 printf("<chain looped>\n");
1601 break;
1602 }
1603 switch (id)
1604 {
1605 case PCI_EXT_CAP_ID_AER:
1606 cap_aer(d, where);
1607 break;
1608 case PCI_EXT_CAP_ID_VC:
1609 printf("Virtual Channel <?>\n");
1610 break;
1611 case PCI_EXT_CAP_ID_DSN:
1612 cap_dsn(d, where);
1613 break;
1614 case PCI_EXT_CAP_ID_PB:
1615 printf("Power Budgeting <?>\n");
1616 break;
1617 case PCI_EXT_CAP_ID_RCLINK:
1618 printf("Root Complex Link <?>\n");
1619 break;
1620 case PCI_EXT_CAP_ID_RCILINK:
1621 printf("Root Complex Internal Link <?>\n");
1622 break;
1623 case PCI_EXT_CAP_ID_RCECOLL:
1624 printf("Root Complex Event Collector <?>\n");
1625 break;
1626 case PCI_EXT_CAP_ID_MFVC:
1627 printf("Multi-Function Virtual Channel <?>\n");
1628 break;
1629 case PCI_EXT_CAP_ID_RBCB:
1630 printf("Root Bridge Control Block <?>\n");
1631 break;
1632 case PCI_EXT_CAP_ID_VNDR:
1633 printf("Vendor Specific Information <?>\n");
1634 break;
1635 case PCI_EXT_CAP_ID_ACS:
1636 cap_acs(d, where);
1637 break;
1638 case PCI_EXT_CAP_ID_ARI:
1639 cap_ari(d, where);
1640 break;
1641 default:
1642 printf("#%02x\n", id);
1643 break;
1644 }
1645 where = header >> 20;
1646 } while (where);
1647 }
1648
1649 static void
1650 show_caps(struct device *d)
1651 {
1652 int can_have_ext_caps = 0;
1653
1654 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1655 {
1656 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1657 byte been_there[256];
1658 memset(been_there, 0, 256);
1659 while (where)
1660 {
1661 int id, next, cap;
1662 printf("\tCapabilities: ");
1663 if (!config_fetch(d, where, 4))
1664 {
1665 puts("<access denied>");
1666 break;
1667 }
1668 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1669 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1670 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1671 printf("[%02x] ", where);
1672 if (been_there[where]++)
1673 {
1674 printf("<chain looped>\n");
1675 break;
1676 }
1677 if (id == 0xff)
1678 {
1679 printf("<chain broken>\n");
1680 break;
1681 }
1682 switch (id)
1683 {
1684 case PCI_CAP_ID_PM:
1685 cap_pm(d, where, cap);
1686 break;
1687 case PCI_CAP_ID_AGP:
1688 cap_agp(d, where, cap);
1689 break;
1690 case PCI_CAP_ID_VPD:
1691 printf("Vital Product Data <?>\n");
1692 break;
1693 case PCI_CAP_ID_SLOTID:
1694 cap_slotid(cap);
1695 break;
1696 case PCI_CAP_ID_MSI:
1697 cap_msi(d, where, cap);
1698 break;
1699 case PCI_CAP_ID_CHSWP:
1700 printf("CompactPCI hot-swap <?>\n");
1701 break;
1702 case PCI_CAP_ID_PCIX:
1703 cap_pcix(d, where);
1704 can_have_ext_caps = 1;
1705 break;
1706 case PCI_CAP_ID_HT:
1707 cap_ht(d, where, cap);
1708 break;
1709 case PCI_CAP_ID_VNDR:
1710 printf("Vendor Specific Information <?>\n");
1711 break;
1712 case PCI_CAP_ID_DBG:
1713 cap_debug_port(cap);
1714 break;
1715 case PCI_CAP_ID_CCRC:
1716 printf("CompactPCI central resource control <?>\n");
1717 break;
1718 case PCI_CAP_ID_HOTPLUG:
1719 printf("Hot-plug capable\n");
1720 break;
1721 case PCI_CAP_ID_SSVID:
1722 cap_ssvid(d, where);
1723 break;
1724 case PCI_CAP_ID_AGP3:
1725 printf("AGP3 <?>\n");
1726 break;
1727 case PCI_CAP_ID_SECURE:
1728 printf("Secure device <?>\n");
1729 break;
1730 case PCI_CAP_ID_EXP:
1731 cap_express(d, where, cap);
1732 can_have_ext_caps = 1;
1733 break;
1734 case PCI_CAP_ID_MSIX:
1735 cap_msix(d, where, cap);
1736 break;
1737 case PCI_CAP_ID_SATA:
1738 printf("SATA HBA <?>\n");
1739 break;
1740 case PCI_CAP_ID_AF:
1741 printf("PCIe advanced features <?>\n");
1742 break;
1743 default:
1744 printf("#%02x [%04x]\n", id, cap);
1745 }
1746 where = next;
1747 }
1748 }
1749 if (can_have_ext_caps)
1750 show_ext_caps(d);
1751 }
1752
1753 /*** Kernel drivers ***/
1754
1755 #ifdef PCI_OS_LINUX
1756
1757 #include <sys/utsname.h>
1758
1759 struct pcimap_entry {
1760 struct pcimap_entry *next;
1761 unsigned int vendor, device;
1762 unsigned int subvendor, subdevice;
1763 unsigned int class, class_mask;
1764 char module[1];
1765 };
1766
1767 static struct pcimap_entry *pcimap_head;
1768
1769 static void
1770 load_pcimap(void)
1771 {
1772 static int tried_pcimap;
1773 struct utsname uts;
1774 char *name, line[1024];
1775 FILE *f;
1776
1777 if (tried_pcimap)
1778 return;
1779 tried_pcimap = 1;
1780
1781 if (name = opt_pcimap)
1782 {
1783 f = fopen(name, "r");
1784 if (!f)
1785 die("Cannot open pcimap file %s: %m", name);
1786 }
1787 else
1788 {
1789 if (uname(&uts) < 0)
1790 die("uname() failed: %m");
1791 name = alloca(64 + strlen(uts.release));
1792 sprintf(name, "/lib/modules/%s/modules.pcimap", uts.release);
1793 f = fopen(name, "r");
1794 if (!f)
1795 return;
1796 }
1797
1798 while (fgets(line, sizeof(line), f))
1799 {
1800 char *c = strchr(line, '\n');
1801 struct pcimap_entry *e;
1802
1803 if (!c)
1804 die("Unterminated or too long line in %s", name);
1805 *c = 0;
1806 if (!line[0] || line[0] == '#')
1807 continue;
1808
1809 c = line;
1810 while (*c && *c != ' ' && *c != '\t')
1811 c++;
1812 if (!*c)
1813 continue; /* FIXME: Emit warnings! */
1814 *c++ = 0;
1815
1816 e = xmalloc(sizeof(*e) + strlen(line));
1817 if (sscanf(c, "%i%i%i%i%i%i",
1818 &e->vendor, &e->device,
1819 &e->subvendor, &e->subdevice,
1820 &e->class, &e->class_mask) != 6)
1821 continue;
1822 e->next = pcimap_head;
1823 pcimap_head = e;
1824 strcpy(e->module, line);
1825 }
1826 fclose(f);
1827 }
1828
1829 static int
1830 match_pcimap(struct device *d, struct pcimap_entry *e)
1831 {
1832 struct pci_dev *dev = d->dev;
1833 unsigned int class = get_conf_long(d, PCI_REVISION_ID) >> 8;
1834 word subv, subd;
1835
1836 #define MATCH(x, y) ((y) > 0xffff || (x) == (y))
1837 get_subid(d, &subv, &subd);
1838 return
1839 MATCH(dev->vendor_id, e->vendor) &&
1840 MATCH(dev->device_id, e->device) &&
1841 MATCH(subv, e->subvendor) &&
1842 MATCH(subd, e->subdevice) &&
1843 (class & e->class_mask) == e->class;
1844 #undef MATCH
1845 }
1846
1847 #define DRIVER_BUF_SIZE 1024
1848
1849 static char *
1850 find_driver(struct device *d, char *buf)
1851 {
1852 struct pci_dev *dev = d->dev;
1853 char name[1024], *drv, *base;
1854 int n;
1855
1856 if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
1857 return NULL;
1858
1859 base = pci_get_param(dev->access, "sysfs.path");
1860 if (!base || !base[0])
1861 return NULL;
1862
1863 n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
1864 base, dev->domain, dev->bus, dev->dev, dev->func);
1865 if (n < 0 || n >= (int)sizeof(name))
1866 die("show_driver: sysfs device name too long, why?");
1867
1868 n = readlink(name, buf, DRIVER_BUF_SIZE);
1869 if (n < 0)
1870 return NULL;
1871 if (n >= DRIVER_BUF_SIZE)
1872 return "<name-too-long>";
1873 buf[n] = 0;
1874
1875 if (drv = strrchr(buf, '/'))
1876 return drv+1;
1877 else
1878 return buf;
1879 }
1880
1881 static void
1882 show_kernel(struct device *d)
1883 {
1884 char buf[DRIVER_BUF_SIZE];
1885 char *driver;
1886 struct pcimap_entry *e, *last = NULL;
1887
1888 if (driver = find_driver(d, buf))
1889 printf("\tKernel driver in use: %s\n", driver);
1890
1891 load_pcimap();
1892 for (e=pcimap_head; e; e=e->next)
1893 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1894 {
1895 printf("%s %s", (last ? "," : "\tKernel modules:"), e->module);
1896 last = e;
1897 }
1898 if (last)
1899 putchar('\n');
1900 }
1901
1902 static void
1903 show_kernel_machine(struct device *d)
1904 {
1905 char buf[DRIVER_BUF_SIZE];
1906 char *driver;
1907 struct pcimap_entry *e, *last = NULL;
1908
1909 if (driver = find_driver(d, buf))
1910 printf("Driver:\t%s\n", driver);
1911
1912 load_pcimap();
1913 for (e=pcimap_head; e; e=e->next)
1914 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1915 {
1916 printf("Module:\t%s\n", e->module);
1917 last = e;
1918 }
1919 }
1920
1921 #else
1922
1923 static void
1924 show_kernel(struct device *d UNUSED)
1925 {
1926 }
1927
1928 static void
1929 show_kernel_machine(struct device *d UNUSED)
1930 {
1931 }
1932
1933 #endif
1934
1935 /*** Verbose output ***/
1936
1937 static void
1938 show_size(pciaddr_t x)
1939 {
1940 if (!x)
1941 return;
1942 printf(" [size=");
1943 if (x < 1024)
1944 printf("%d", (int) x);
1945 else if (x < 1048576)
1946 printf("%dK", (int)(x / 1024));
1947 else if (x < 0x80000000)
1948 printf("%dM", (int)(x / 1048576));
1949 else
1950 printf(PCIADDR_T_FMT, x);
1951 putchar(']');
1952 }
1953
1954 static void
1955 show_bases(struct device *d, int cnt)
1956 {
1957 struct pci_dev *p = d->dev;
1958 word cmd = get_conf_word(d, PCI_COMMAND);
1959 int i;
1960
1961 for(i=0; i<cnt; i++)
1962 {
1963 pciaddr_t pos = p->base_addr[i];
1964 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
1965 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1966 if (flg == 0xffffffff)
1967 flg = 0;
1968 if (!pos && !flg && !len)
1969 continue;
1970 if (verbose > 1)
1971 printf("\tRegion %d: ", i);
1972 else
1973 putchar('\t');
1974 if (pos && !flg) /* Reported by the OS, but not by the device */
1975 {
1976 printf("[virtual] ");
1977 flg = pos;
1978 }
1979 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
1980 {
1981 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
1982 printf("I/O ports at ");
1983 if (a)
1984 printf(PCIADDR_PORT_FMT, a);
1985 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
1986 printf("<ignored>");
1987 else
1988 printf("<unassigned>");
1989 if (!(cmd & PCI_COMMAND_IO))
1990 printf(" [disabled]");
1991 }
1992 else
1993 {
1994 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1995 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
1996 int done = 0;
1997 u32 z = 0;
1998
1999 printf("Memory at ");
2000 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
2001 {
2002 if (i >= cnt - 1)
2003 {
2004 printf("<invalid-64bit-slot>");
2005 done = 1;
2006 }
2007 else
2008 {
2009 i++;
2010 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
2011 if (opt_buscentric)
2012 {
2013 u32 y = a & 0xffffffff;
2014 if (a || z)
2015 printf("%08x%08x", z, y);
2016 else
2017 printf("<unassigned>");
2018 done = 1;
2019 }
2020 }
2021 }
2022 if (!done)
2023 {
2024 if (a)
2025 printf(PCIADDR_T_FMT, a);
2026 else
2027 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
2028 }
2029 printf(" (%s, %sprefetchable)",
2030 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
2031 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
2032 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
2033 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
2034 if (!(cmd & PCI_COMMAND_MEMORY))
2035 printf(" [disabled]");
2036 }
2037 show_size(len);
2038 putchar('\n');
2039 }
2040 }
2041
2042 static void
2043 show_rom(struct device *d, int reg)
2044 {
2045 struct pci_dev *p = d->dev;
2046 pciaddr_t rom = p->rom_base_addr;
2047 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
2048 u32 flg = get_conf_long(d, reg);
2049 word cmd = get_conf_word(d, PCI_COMMAND);
2050
2051 if (!rom && !flg && !len)
2052 return;
2053 putchar('\t');
2054 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
2055 {
2056 printf("[virtual] ");
2057 flg = rom;
2058 }
2059 printf("Expansion ROM at ");
2060 if (rom & PCI_ROM_ADDRESS_MASK)
2061 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
2062 else if (flg & PCI_ROM_ADDRESS_MASK)
2063 printf("<ignored>");
2064 else
2065 printf("<unassigned>");
2066 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
2067 printf(" [disabled]");
2068 else if (!(cmd & PCI_COMMAND_MEMORY))
2069 printf(" [disabled by cmd]");
2070 show_size(len);
2071 putchar('\n');
2072 }
2073
2074 static void
2075 show_htype0(struct device *d)
2076 {
2077 show_bases(d, 6);
2078 show_rom(d, PCI_ROM_ADDRESS);
2079 show_caps(d);
2080 }
2081
2082 static void
2083 show_htype1(struct device *d)
2084 {
2085 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
2086 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
2087 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
2088 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
2089 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
2090 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
2091 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
2092 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
2093 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
2094 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
2095 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
2096 int verb = verbose > 2;
2097
2098 show_bases(d, 2);
2099 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
2100 get_conf_byte(d, PCI_PRIMARY_BUS),
2101 get_conf_byte(d, PCI_SECONDARY_BUS),
2102 get_conf_byte(d, PCI_SUBORDINATE_BUS),
2103 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
2104
2105 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
2106 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
2107 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
2108 else
2109 {
2110 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
2111 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
2112 if (io_type == PCI_IO_RANGE_TYPE_32)
2113 {
2114 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
2115 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
2116 }
2117 if (io_base <= io_limit || verb)
2118 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
2119 }
2120
2121 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
2122 mem_type)
2123 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
2124 else
2125 {
2126 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
2127 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
2128 if (mem_base <= mem_limit || verb)
2129 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
2130 }
2131
2132 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
2133 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
2134 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
2135 else
2136 {
2137 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
2138 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
2139 if (pref_base <= pref_limit || verb)
2140 {
2141 if (pref_type == PCI_PREF_RANGE_TYPE_32)
2142 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
2143 else
2144 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
2145 get_conf_long(d, PCI_PREF_BASE_UPPER32),
2146 pref_base,
2147 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
2148 pref_limit + 0xfffff);
2149 }
2150 }
2151
2152 if (verbose > 1)
2153 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
2154 FLAG(sec_stat, PCI_STATUS_66MHZ),
2155 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
2156 FLAG(sec_stat, PCI_STATUS_PARITY),
2157 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2158 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2159 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2160 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
2161 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
2162 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
2163 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
2164 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
2165
2166 show_rom(d, PCI_ROM_ADDRESS1);
2167
2168 if (verbose > 1)
2169 {
2170 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
2171 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
2172 FLAG(brc, PCI_BRIDGE_CTL_SERR),
2173 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
2174 FLAG(brc, PCI_BRIDGE_CTL_VGA),
2175 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
2176 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
2177 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
2178 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
2179 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
2180 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
2181 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
2182 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
2183 }
2184
2185 show_caps(d);
2186 }
2187
2188 static void
2189 show_htype2(struct device *d)
2190 {
2191 int i;
2192 word cmd = get_conf_word(d, PCI_COMMAND);
2193 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
2194 word exca;
2195 int verb = verbose > 2;
2196
2197 show_bases(d, 1);
2198 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
2199 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
2200 get_conf_byte(d, PCI_CB_CARD_BUS),
2201 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
2202 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
2203 for(i=0; i<2; i++)
2204 {
2205 int p = 8*i;
2206 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
2207 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
2208 if (limit > base || verb)
2209 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
2210 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
2211 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
2212 }
2213 for(i=0; i<2; i++)
2214 {
2215 int p = 8*i;
2216 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
2217 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
2218 if (!(base & PCI_IO_RANGE_TYPE_32))
2219 {
2220 base &= 0xffff;
2221 limit &= 0xffff;
2222 }
2223 base &= PCI_CB_IO_RANGE_MASK;
2224 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
2225 if (base <= limit || verb)
2226 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
2227 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
2228 }
2229
2230 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
2231 printf("\tSecondary status: SERR\n");
2232 if (verbose > 1)
2233 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
2234 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
2235 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
2236 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
2237 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
2238 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
2239 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
2240 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
2241 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
2242
2243 if (d->config_cached < 128)
2244 {
2245 printf("\t<access denied to the rest>\n");
2246 return;
2247 }
2248
2249 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
2250 if (exca)
2251 printf("\t16-bit legacy interface ports at %04x\n", exca);
2252 }
2253
2254 static void
2255 show_verbose(struct device *d)
2256 {
2257 struct pci_dev *p = d->dev;
2258 word status = get_conf_word(d, PCI_STATUS);
2259 word cmd = get_conf_word(d, PCI_COMMAND);
2260 word class = p->device_class;
2261 byte bist = get_conf_byte(d, PCI_BIST);
2262 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2263 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
2264 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
2265 byte max_lat, min_gnt;
2266 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
2267 unsigned int irq = p->irq;
2268 word subsys_v, subsys_d;
2269 char ssnamebuf[256];
2270
2271 show_terse(d);
2272
2273 switch (htype)
2274 {
2275 case PCI_HEADER_TYPE_NORMAL:
2276 if (class == PCI_CLASS_BRIDGE_PCI)
2277 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2278 max_lat = get_conf_byte(d, PCI_MAX_LAT);
2279 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
2280 break;
2281 case PCI_HEADER_TYPE_BRIDGE:
2282 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2283 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2284 irq = int_pin = min_gnt = max_lat = 0;
2285 break;
2286 case PCI_HEADER_TYPE_CARDBUS:
2287 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2288 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2289 min_gnt = max_lat = 0;
2290 break;
2291 default:
2292 printf("\t!!! Unknown header type %02x\n", htype);
2293 return;
2294 }
2295
2296 get_subid(d, &subsys_v, &subsys_d);
2297 if (subsys_v && subsys_v != 0xffff)
2298 printf("\tSubsystem: %s\n",
2299 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
2300 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2301 p->vendor_id, p->device_id, subsys_v, subsys_d));
2302
2303 if (verbose > 1)
2304 {
2305 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
2306 FLAG(cmd, PCI_COMMAND_IO),
2307 FLAG(cmd, PCI_COMMAND_MEMORY),
2308 FLAG(cmd, PCI_COMMAND_MASTER),
2309 FLAG(cmd, PCI_COMMAND_SPECIAL),
2310 FLAG(cmd, PCI_COMMAND_INVALIDATE),
2311 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
2312 FLAG(cmd, PCI_COMMAND_PARITY),
2313 FLAG(cmd, PCI_COMMAND_WAIT),
2314 FLAG(cmd, PCI_COMMAND_SERR),
2315 FLAG(cmd, PCI_COMMAND_FAST_BACK),
2316 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
2317 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
2318 FLAG(status, PCI_STATUS_CAP_LIST),
2319 FLAG(status, PCI_STATUS_66MHZ),
2320 FLAG(status, PCI_STATUS_UDF),
2321 FLAG(status, PCI_STATUS_FAST_BACK),
2322 FLAG(status, PCI_STATUS_PARITY),
2323 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2324 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2325 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2326 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
2327 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
2328 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
2329 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
2330 FLAG(status, PCI_STATUS_DETECTED_PARITY),
2331 FLAG(status, PCI_STATUS_INTx));
2332 if (cmd & PCI_COMMAND_MASTER)
2333 {
2334 printf("\tLatency: %d", latency);
2335 if (min_gnt || max_lat)
2336 {
2337 printf(" (");
2338 if (min_gnt)
2339 printf("%dns min", min_gnt*250);
2340 if (min_gnt && max_lat)
2341 printf(", ");
2342 if (max_lat)
2343 printf("%dns max", max_lat*250);
2344 putchar(')');
2345 }
2346 if (cache_line)
2347 printf(", Cache Line Size: %d bytes", cache_line * 4);
2348 putchar('\n');
2349 }
2350 if (int_pin || irq)
2351 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
2352 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
2353 }
2354 else
2355 {
2356 printf("\tFlags: ");
2357 if (cmd & PCI_COMMAND_MASTER)
2358 printf("bus master, ");
2359 if (cmd & PCI_COMMAND_VGA_PALETTE)
2360 printf("VGA palette snoop, ");
2361 if (cmd & PCI_COMMAND_WAIT)
2362 printf("stepping, ");
2363 if (cmd & PCI_COMMAND_FAST_BACK)
2364 printf("fast Back2Back, ");
2365 if (status & PCI_STATUS_66MHZ)
2366 printf("66MHz, ");
2367 if (status & PCI_STATUS_UDF)
2368 printf("user-definable features, ");
2369 printf("%s devsel",
2370 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2371 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2372 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
2373 if (cmd & PCI_COMMAND_MASTER)
2374 printf(", latency %d", latency);
2375 if (irq)
2376 printf(", IRQ " PCIIRQ_FMT, irq);
2377 putchar('\n');
2378 }
2379
2380 if (bist & PCI_BIST_CAPABLE)
2381 {
2382 if (bist & PCI_BIST_START)
2383 printf("\tBIST is running\n");
2384 else
2385 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
2386 }
2387
2388 switch (htype)
2389 {
2390 case PCI_HEADER_TYPE_NORMAL:
2391 show_htype0(d);
2392 break;
2393 case PCI_HEADER_TYPE_BRIDGE:
2394 show_htype1(d);
2395 break;
2396 case PCI_HEADER_TYPE_CARDBUS:
2397 show_htype2(d);
2398 break;
2399 }
2400 }
2401
2402 /*** Machine-readable dumps ***/
2403
2404 static void
2405 show_hex_dump(struct device *d)
2406 {
2407 unsigned int i, cnt;
2408
2409 cnt = d->config_cached;
2410 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
2411 {
2412 cnt = 256;
2413 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
2414 cnt = 4096;
2415 }
2416
2417 for(i=0; i<cnt; i++)
2418 {
2419 if (! (i & 15))
2420 printf("%02x:", i);
2421 printf(" %02x", get_conf_byte(d, i));
2422 if ((i & 15) == 15)
2423 putchar('\n');
2424 }
2425 }
2426
2427 static void
2428 print_shell_escaped(char *c)
2429 {
2430 printf(" \"");
2431 while (*c)
2432 {
2433 if (*c == '"' || *c == '\\')
2434 putchar('\\');
2435 putchar(*c++);
2436 }
2437 putchar('"');
2438 }
2439
2440 static void
2441 show_machine(struct device *d)
2442 {
2443 struct pci_dev *p = d->dev;
2444 int c;
2445 word sv_id, sd_id;
2446 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
2447
2448 get_subid(d, &sv_id, &sd_id);
2449
2450 if (verbose)
2451 {
2452 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
2453 show_slot_name(d);
2454 putchar('\n');
2455 printf("Class:\t%s\n",
2456 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2457 printf("Vendor:\t%s\n",
2458 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2459 printf("Device:\t%s\n",
2460 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2461 if (sv_id && sv_id != 0xffff)
2462 {
2463 printf("SVendor:\t%s\n",
2464 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2465 printf("SDevice:\t%s\n",
2466 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2467 }
2468 if (c = get_conf_byte(d, PCI_REVISION_ID))
2469 printf("Rev:\t%02x\n", c);
2470 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2471 printf("ProgIf:\t%02x\n", c);
2472 if (opt_kernel)
2473 show_kernel_machine(d);
2474 }
2475 else
2476 {
2477 show_slot_name(d);
2478 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2479 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2480 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2481 if (c = get_conf_byte(d, PCI_REVISION_ID))
2482 printf(" -r%02x", c);
2483 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2484 printf(" -p%02x", c);
2485 if (sv_id && sv_id != 0xffff)
2486 {
2487 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2488 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2489 }
2490 else
2491 printf(" \"\" \"\"");
2492 putchar('\n');
2493 }
2494 }
2495
2496 /*** Main show function ***/
2497
2498 static void
2499 show_device(struct device *d)
2500 {
2501 if (opt_machine)
2502 show_machine(d);
2503 else
2504 {
2505 if (verbose)
2506 show_verbose(d);
2507 else
2508 show_terse(d);
2509 if (opt_kernel || verbose)
2510 show_kernel(d);
2511 }
2512 if (opt_hex)
2513 show_hex_dump(d);
2514 if (verbose || opt_hex)
2515 putchar('\n');
2516 }
2517
2518 static void
2519 show(void)
2520 {
2521 struct device *d;
2522
2523 for(d=first_dev; d; d=d->next)
2524 show_device(d);
2525 }
2526
2527 /*** Tree output ***/
2528
2529 struct bridge {
2530 struct bridge *chain; /* Single-linked list of bridges */
2531 struct bridge *next, *child; /* Tree of bridges */
2532 struct bus *first_bus; /* List of buses connected to this bridge */
2533 unsigned int domain;
2534 unsigned int primary, secondary, subordinate; /* Bus numbers */
2535 struct device *br_dev;
2536 };
2537
2538 struct bus {
2539 unsigned int domain;
2540 unsigned int number;
2541 struct bus *sibling;
2542 struct device *first_dev, **last_dev;
2543 };
2544
2545 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2546
2547 static struct bus *
2548 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2549 {
2550 struct bus *bus;
2551
2552 for(bus=b->first_bus; bus; bus=bus->sibling)
2553 if (bus->domain == domain && bus->number == n)
2554 break;
2555 return bus;
2556 }
2557
2558 static struct bus *
2559 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2560 {
2561 struct bus *bus = xmalloc(sizeof(struct bus));
2562 bus->domain = domain;
2563 bus->number = n;
2564 bus->sibling = b->first_bus;
2565 bus->first_dev = NULL;
2566 bus->last_dev = &bus->first_dev;
2567 b->first_bus = bus;
2568 return bus;
2569 }
2570
2571 static void
2572 insert_dev(struct device *d, struct bridge *b)
2573 {
2574 struct pci_dev *p = d->dev;
2575 struct bus *bus;
2576
2577 if (! (bus = find_bus(b, p->domain, p->bus)))
2578 {
2579 struct bridge *c;
2580 for(c=b->child; c; c=c->next)
2581 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2582 {
2583 insert_dev(d, c);
2584 return;
2585 }
2586 bus = new_bus(b, p->domain, p->bus);
2587 }
2588 /* Simple insertion at the end _does_ guarantee the correct order as the
2589 * original device list was sorted by (domain, bus, devfn) lexicographically
2590 * and all devices on the new list have the same bus number.
2591 */
2592 *bus->last_dev = d;
2593 bus->last_dev = &d->next;
2594 d->next = NULL;
2595 }
2596
2597 static void
2598 grow_tree(void)
2599 {
2600 struct device *d, *d2;
2601 struct bridge **last_br, *b;
2602
2603 /* Build list of bridges */
2604
2605 last_br = &host_bridge.chain;
2606 for(d=first_dev; d; d=d->next)
2607 {
2608 word class = d->dev->device_class;
2609 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2610 if (class == PCI_CLASS_BRIDGE_PCI &&
2611 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2612 {
2613 b = xmalloc(sizeof(struct bridge));
2614 b->domain = d->dev->domain;
2615 if (ht == PCI_HEADER_TYPE_BRIDGE)
2616 {
2617 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2618 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2619 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2620 }
2621 else
2622 {
2623 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2624 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2625 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2626 }
2627 *last_br = b;
2628 last_br = &b->chain;
2629 b->next = b->child = NULL;
2630 b->first_bus = NULL;
2631 b->br_dev = d;
2632 }
2633 }
2634 *last_br = NULL;
2635
2636 /* Create a bridge tree */
2637
2638 for(b=&host_bridge; b; b=b->chain)
2639 {
2640 struct bridge *c, *best;
2641 best = NULL;
2642 for(c=&host_bridge; c; c=c->chain)
2643 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2644 b->primary >= c->secondary && b->primary <= c->subordinate &&
2645 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2646 best = c;
2647 if (best)
2648 {
2649 b->next = best->child;
2650 best->child = b;
2651 }
2652 }
2653
2654 /* Insert secondary bus for each bridge */
2655
2656 for(b=&host_bridge; b; b=b->chain)
2657 if (!find_bus(b, b->domain, b->secondary))
2658 new_bus(b, b->domain, b->secondary);
2659
2660 /* Create bus structs and link devices */
2661
2662 for(d=first_dev; d;)
2663 {
2664 d2 = d->next;
2665 insert_dev(d, &host_bridge);
2666 d = d2;
2667 }
2668 }
2669
2670 static void
2671 print_it(char *line, char *p)
2672 {
2673 *p++ = '\n';
2674 *p = 0;
2675 fputs(line, stdout);
2676 for(p=line; *p; p++)
2677 if (*p == '+' || *p == '|')
2678 *p = '|';
2679 else
2680 *p = ' ';
2681 }
2682
2683 static void show_tree_bridge(struct bridge *, char *, char *);
2684
2685 static void
2686 show_tree_dev(struct device *d, char *line, char *p)
2687 {
2688 struct pci_dev *q = d->dev;
2689 struct bridge *b;
2690 char namebuf[256];
2691
2692 p += sprintf(p, "%02x.%x", q->dev, q->func);
2693 for(b=&host_bridge; b; b=b->chain)
2694 if (b->br_dev == d)
2695 {
2696 if (b->secondary == b->subordinate)
2697 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2698 else
2699 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2700 show_tree_bridge(b, line, p);
2701 return;
2702 }
2703 if (verbose)
2704 p += sprintf(p, " %s",
2705 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2706 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2707 q->vendor_id, q->device_id));
2708 print_it(line, p);
2709 }
2710
2711 static void
2712 show_tree_bus(struct bus *b, char *line, char *p)
2713 {
2714 if (!b->first_dev)
2715 print_it(line, p);
2716 else if (!b->first_dev->next)
2717 {
2718 *p++ = '-';
2719 *p++ = '-';
2720 show_tree_dev(b->first_dev, line, p);
2721 }
2722 else
2723 {
2724 struct device *d = b->first_dev;
2725 while (d->next)
2726 {
2727 p[0] = '+';
2728 p[1] = '-';
2729 show_tree_dev(d, line, p+2);
2730 d = d->next;
2731 }
2732 p[0] = '\\';
2733 p[1] = '-';
2734 show_tree_dev(d, line, p+2);
2735 }
2736 }
2737
2738 static void
2739 show_tree_bridge(struct bridge *b, char *line, char *p)
2740 {
2741 *p++ = '-';
2742 if (!b->first_bus->sibling)
2743 {
2744 if (b == &host_bridge)
2745 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2746 show_tree_bus(b->first_bus, line, p);
2747 }
2748 else
2749 {
2750 struct bus *u = b->first_bus;
2751 char *k;
2752
2753 while (u->sibling)
2754 {
2755 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2756 show_tree_bus(u, line, k);
2757 u = u->sibling;
2758 }
2759 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2760 show_tree_bus(u, line, k);
2761 }
2762 }
2763
2764 static void
2765 show_forest(void)
2766 {
2767 char line[256];
2768
2769 grow_tree();
2770 show_tree_bridge(&host_bridge, line, line);
2771 }
2772
2773 /*** Bus mapping mode ***/
2774
2775 struct bus_bridge {
2776 struct bus_bridge *next;
2777 byte this, dev, func, first, last, bug;
2778 };
2779
2780 struct bus_info {
2781 byte exists;
2782 byte guestbook;
2783 struct bus_bridge *bridges, *via;
2784 };
2785
2786 static struct bus_info *bus_info;
2787
2788 static void
2789 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2790 {
2791 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2792 struct pci_dev *p = d->dev;
2793
2794 b->next = bi->bridges;
2795 bi->bridges = b;
2796 b->this = get_conf_byte(d, np);
2797 b->dev = p->dev;
2798 b->func = p->func;
2799 b->first = get_conf_byte(d, ns);
2800 b->last = get_conf_byte(d, nl);
2801 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2802 p->bus, p->dev, p->func, b->this, b->first, b->last);
2803 if (b->this != p->bus)
2804 printf("!!! Bridge points to invalid primary bus.\n");
2805 if (b->first > b->last)
2806 {
2807 printf("!!! Bridge points to invalid bus range.\n");
2808 b->last = b->first;
2809 }
2810 }
2811
2812 static void
2813 do_map_bus(int bus)
2814 {
2815 int dev, func;
2816 int verbose = pacc->debugging;
2817 struct bus_info *bi = bus_info + bus;
2818 struct device *d;
2819
2820 if (verbose)
2821 printf("Mapping bus %02x\n", bus);
2822 for(dev = 0; dev < 32; dev++)
2823 if (filter.slot < 0 || filter.slot == dev)
2824 {
2825 int func_limit = 1;
2826 for(func = 0; func < func_limit; func++)
2827 if (filter.func < 0 || filter.func == func)
2828 {
2829 /* XXX: Bus mapping supports only domain 0 */
2830 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2831 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2832 if (vendor && vendor != 0xffff)
2833 {
2834 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2835 func_limit = 8;
2836 if (verbose)
2837 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2838 bi->exists = 1;
2839 if (d = scan_device(p))
2840 {
2841 show_device(d);
2842 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2843 {
2844 case PCI_HEADER_TYPE_BRIDGE:
2845 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2846 break;
2847 case PCI_HEADER_TYPE_CARDBUS:
2848 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2849 break;
2850 }
2851 free(d);
2852 }
2853 else if (verbose)
2854 printf("But it was filtered out.\n");
2855 }
2856 pci_free_dev(p);
2857 }
2858 }
2859 }
2860
2861 static void
2862 do_map_bridges(int bus, int min, int max)
2863 {
2864 struct bus_info *bi = bus_info + bus;
2865 struct bus_bridge *b;
2866
2867 bi->guestbook = 1;
2868 for(b=bi->bridges; b; b=b->next)
2869 {
2870 if (bus_info[b->first].guestbook)
2871 b->bug = 1;
2872 else if (b->first < min || b->last > max)
2873 b->bug = 2;
2874 else
2875 {
2876 bus_info[b->first].via = b;
2877 do_map_bridges(b->first, b->first, b->last);
2878 }
2879 }
2880 }
2881
2882 static void
2883 map_bridges(void)
2884 {
2885 int i;
2886
2887 printf("\nSummary of buses:\n\n");
2888 for(i=0; i<256; i++)
2889 if (bus_info[i].exists && !bus_info[i].guestbook)
2890 do_map_bridges(i, 0, 255);
2891 for(i=0; i<256; i++)
2892 {
2893 struct bus_info *bi = bus_info + i;
2894 struct bus_bridge *b = bi->via;
2895
2896 if (bi->exists)
2897 {
2898 printf("%02x: ", i);
2899 if (b)
2900 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2901 else if (!i)
2902 printf("Primary host bus\n");
2903 else
2904 printf("Secondary host bus (?)\n");
2905 }
2906 for(b=bi->bridges; b; b=b->next)
2907 {
2908 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2909 switch (b->bug)
2910 {
2911 case 1:
2912 printf(" <overlap bug>");
2913 break;
2914 case 2:
2915 printf(" <crossing bug>");
2916 break;
2917 }
2918 putchar('\n');
2919 }
2920 }
2921 }
2922
2923 static void
2924 map_the_bus(void)
2925 {
2926 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2927 pacc->method == PCI_ACCESS_DUMP)
2928 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2929 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2930 memset(bus_info, 0, sizeof(struct bus_info) * 256);
2931 if (filter.bus >= 0)
2932 do_map_bus(filter.bus);
2933 else
2934 {
2935 int bus;
2936 for(bus=0; bus<256; bus++)
2937 do_map_bus(bus);
2938 }
2939 map_bridges();
2940 }
2941
2942 /* Main */
2943
2944 int
2945 main(int argc, char **argv)
2946 {
2947 int i;
2948 char *msg;
2949
2950 if (argc == 2 && !strcmp(argv[1], "--version"))
2951 {
2952 puts("lspci version " PCIUTILS_VERSION);
2953 return 0;
2954 }
2955
2956 pacc = pci_alloc();
2957 pacc->error = die;
2958 pci_filter_init(pacc, &filter);
2959
2960 while ((i = getopt(argc, argv, options)) != -1)
2961 switch (i)
2962 {
2963 case 'n':
2964 pacc->numeric_ids++;
2965 break;
2966 case 'v':
2967 verbose++;
2968 break;
2969 case 'b':
2970 pacc->buscentric = 1;
2971 opt_buscentric = 1;
2972 break;
2973 case 's':
2974 if (msg = pci_filter_parse_slot(&filter, optarg))
2975 die("-s: %s", msg);
2976 break;
2977 case 'd':
2978 if (msg = pci_filter_parse_id(&filter, optarg))
2979 die("-d: %s", msg);
2980 break;
2981 case 'x':
2982 opt_hex++;
2983 break;
2984 case 't':
2985 opt_tree++;
2986 break;
2987 case 'i':
2988 pci_set_name_list_path(pacc, optarg, 0);
2989 break;
2990 case 'm':
2991 opt_machine++;
2992 break;
2993 case 'p':
2994 opt_pcimap = optarg;
2995 break;
2996 #ifdef PCI_OS_LINUX
2997 case 'k':
2998 opt_kernel++;
2999 break;
3000 #endif
3001 case 'M':
3002 opt_map_mode++;
3003 break;
3004 case 'D':
3005 opt_domains = 2;
3006 break;
3007 #ifdef PCI_USE_DNS
3008 case 'q':
3009 opt_query_dns++;
3010 break;
3011 case 'Q':
3012 opt_query_all = 1;
3013 break;
3014 #else
3015 case 'q':
3016 case 'Q':
3017 die("DNS queries are not available in this version");
3018 #endif
3019 default:
3020 if (parse_generic_option(i, pacc, optarg))
3021 break;
3022 bad:
3023 fprintf(stderr, help_msg, pacc->id_file_name);
3024 return 1;
3025 }
3026 if (optind < argc)
3027 goto bad;
3028
3029 if (opt_query_dns)
3030 {
3031 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK;
3032 if (opt_query_dns > 1)
3033 pacc->id_lookup_mode |= PCI_LOOKUP_REFRESH_CACHE;
3034 }
3035 if (opt_query_all)
3036 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK | PCI_LOOKUP_SKIP_LOCAL;
3037
3038 pci_init(pacc);
3039 if (opt_map_mode)
3040 map_the_bus();
3041 else
3042 {
3043 scan_devices();
3044 sort_them();
3045 if (opt_tree)
3046 show_forest();
3047 else
3048 show();
3049 }
3050 pci_cleanup(pacc);
3051
3052 return (seen_errors ? 2 : 0);
3053 }
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