manual/platform.texi

   1 @node Platform, Contributors, Maintenance, Top
   2 @c %MENU% Describe all platform-specific facilities provided
   3 @appendix Platform-specific facilities
   4
   5 @Theglibc{} can provide machine-specific functionality.
   6
   7 @menu
   8 * PowerPC::           Facilities Specific to the PowerPC Architecture
   9 * RISC-V::            Facilities Specific to the RISC-V Architecture
  10 * X86::               Facilities Specific to the X86 Architecture
  11 @end menu
  12
  13 @node PowerPC
  14 @appendixsec PowerPC-specific Facilities
  15
  16 Facilities specific to PowerPC that are not specific to a particular
  17 operating system are declared in @file{sys/platform/ppc.h}.
  18
  19 @deftypefun {uint64_t} __ppc_get_timebase (void)
  20 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  21 Read the current value of the Time Base Register.
  22
  23 The @dfn{Time Base Register} is a 64-bit register that stores a monotonically
  24 incremented value updated at a system-dependent frequency that may be
  25 different from the processor frequency.  More information is available in
  26 @cite{Power ISA 2.06b - Book II - Section 5.2}.
  27
  28 @code{__ppc_get_timebase} uses the processor's time base facility directly
  29 without requiring assistance from the operating system, so it is very
  30 efficient.
  31 @end deftypefun
  32
  33 @deftypefun {uint64_t} __ppc_get_timebase_freq (void)
  34 @safety{@prelim{}@mtunsafe{@mtuinit{}}@asunsafe{@asucorrupt{:init}}@acunsafe{@acucorrupt{:init}}}
  35 @c __ppc_get_timebase_freq=__get_timebase_freq @mtuinit @acsfd
  36 @c  __get_clockfreq @mtuinit @asucorrupt:init @acucorrupt:init @acsfd
  37 @c    the initialization of the static timebase_freq is not exactly
  38 @c    safe, because hp_timing_t cannot be atomically set up.
  39 @c   syscall:get_tbfreq ok
  40 @c   open dup @acsfd
  41 @c   read dup ok
  42 @c   memcpy dup ok
  43 @c   memmem dup ok
  44 @c   close dup @acsfd
  45 Read the current frequency at which the Time Base Register is updated.
  46
  47 This frequency is not related to the processor clock or the bus clock.
  48 It is also possible that this frequency is not constant.  More information is
  49 available in @cite{Power ISA 2.06b - Book II - Section 5.2}.
  50 @end deftypefun
  51
  52 The following functions provide hints about the usage of resources that are
  53 shared with other processors.  They can be used, for example, if a program
  54 waiting on a lock intends to divert the shared resources to be used by other
  55 processors.  More information is available in @cite{Power ISA 2.06b - Book II -
  56 Section 3.2}.
  57
  58 @deftypefun {void} __ppc_yield (void)
  59 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  60 Provide a hint that performance will probably be improved if shared resources
  61 dedicated to the executing processor are released for use by other processors.
  62 @end deftypefun
  63
  64 @deftypefun {void} __ppc_mdoio (void)
  65 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  66 Provide a hint that performance will probably be improved if shared resources
  67 dedicated to the executing processor are released until all outstanding storage
  68 accesses to caching-inhibited storage have been completed.
  69 @end deftypefun
  70
  71 @deftypefun {void} __ppc_mdoom (void)
  72 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  73 Provide a hint that performance will probably be improved if shared resources
  74 dedicated to the executing processor are released until all outstanding storage
  75 accesses to cacheable storage for which the data is not in the cache have been
  76 completed.
  77 @end deftypefun
  78
  79 @deftypefun {void} __ppc_set_ppr_med (void)
  80 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  81 Set the Program Priority Register to medium value (default).
  82
  83 The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls
  84 the program's priority.  By adjusting the PPR value the programmer may
  85 improve system throughput by causing the system resources to be used
  86 more efficiently, especially in contention situations.
  87 The three unprivileged states available are covered by the functions
  88 @code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low)
  89 and @code{__ppc_set_ppc_med_low} (medium low).  More information
  90 available in @cite{Power ISA 2.06b - Book II - Section 3.1}.
  91 @end deftypefun
  92
  93 @deftypefun {void} __ppc_set_ppr_low (void)
  94 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  95 Set the Program Priority Register to low value.
  96 @end deftypefun
  97
  98 @deftypefun {void} __ppc_set_ppr_med_low (void)
  99 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 100 Set the Program Priority Register to medium low value.
 101 @end deftypefun
 102
 103 Power ISA 2.07 extends the priorities that can be set to the Program Priority
 104 Register (PPR).  The following functions implement the new priority levels:
 105 very low and medium high.
 106
 107 @deftypefun {void} __ppc_set_ppr_very_low (void)
 108 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 109 Set the Program Priority Register to very low value.
 110 @end deftypefun
 111
 112 @deftypefun {void} __ppc_set_ppr_med_high (void)
 113 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 114 Set the Program Priority Register to medium high value.  The medium high
 115 priority is privileged and may only be set during certain time intervals by
 116 problem-state programs.  If the program priority is medium high when the time
 117 interval expires or if an attempt is made to set the priority to medium high
 118 when it is not allowed, the priority is set to medium.
 119 @end deftypefun
 120
 121 @node RISC-V
 122 @appendixsec RISC-V-specific Facilities
 123
 124 Cache management facilities specific to RISC-V systems that implement the Linux
 125 ABI are declared in @file{sys/cachectl.h}.
 126
 127 @deftypefun {void} __riscv_flush_icache (void *@var{start}, void *@var{end}, unsigned long int @var{flags})
 128 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 129 Enforce ordering between stores and instruction cache fetches.  The range of
 130 addresses over which ordering is enforced is specified by @var{start} and
 131 @var{end}.  The @var{flags} argument controls the extent of this ordering, with
 132 the default behavior (a @var{flags} value of 0) being to enforce the fence on
 133 all threads in the current process.  Setting the
 134 @code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
 135 ordering on only the current thread is necessary.  All other flag bits are
 136 reserved.
 137 @end deftypefun
 138
 139 @node X86
 140 @appendixsec X86-specific Facilities
 141
 142 Facilities specific to X86 that are not specific to a particular
 143 operating system are declared in @file{sys/platform/x86.h}.
 144
 145 @deftypefun {const struct cpuid_feature *} __x86_get_cpuid_feature_leaf (unsigned int @var{leaf})
 146 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 147 Return a pointer to x86 CPU feature structure used by query macros for x86
 148 CPU feature @var{leaf}.
 149 @end deftypefun
 150
 151 @deftypefn Macro int CPU_FEATURE_PRESENT (@var{name})
 152 This macro returns a nonzero value (true) if the processor has the feature
 153 @var{name}.
 154 @end deftypefn
 155
 156 @deftypefn Macro int CPU_FEATURE_ACTIVE (@var{name})
 157 This macro returns a nonzero value (true) if the processor has the feature
 158 @var{name} and the feature is active.  There may be other preconditions,
 159 like sufficient stack space or further setup for AMX, which must be
 160 satisfied before the feature can be used.
 161 @end deftypefn
 162
 163 The supported processor features are:
 164
 165 @itemize @bullet
 166
 167 @item
 168 @code{ACPI} -- Thermal Monitor and Software Controlled Clock Facilities.
 169
 170 @item
 171 @code{ADX} -- ADX instruction extensions.
 172
 173 @item
 174 @code{APIC} -- APIC On-Chip.
 175
 176 @item
 177 @code{AES} -- The AES instruction extensions.
 178
 179 @item
 180 @code{AESKLE} -- AES Key Locker instructions are enabled by OS.
 181
 182 @item
 183 @code{AMD_IBPB} -- Indirect branch predictor barrier (IBPB) for AMD cpus.
 184
 185 @item
 186 @code{AMD_IBRS} -- Indirect branch restricted speculation (IBPB) for AMD cpus.
 187
 188 @item
 189 @code{AMD_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus.
 190
 191 @item
 192 @code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus.
 193
 194 @item
 195 @code{AMD_VIRT_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus (older systems).
 196
 197 @item
 198 @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
 199
 200 @item
 201 @code{AMX_COMPLEX} -- Tile computational operations on complex FP16 numbers.
 202
 203 @item
 204 @code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
 205
 206 @item
 207 @code{AMX_FP16} -- Tile computational operations on FP16 numbers.
 208
 209 @item
 210 @code{AMX_TILE} -- Tile architecture.
 211
 212 @item
 213 @code{APX_F} -- The APX instruction extensions.
 214
 215 @item
 216 @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
 217
 218 @item
 219 @code{ArchPerfmonExt} -- Architectural Performance Monitoring Extended
 220 Leaf (EAX = 23H).
 221
 222 @item
 223 @code{AVX} -- The AVX instruction extensions.
 224
 225 @item
 226 @code{AVX10} -- The AVX10 instruction extensions.
 227
 228 @item
 229 @code{AVX10_XMM} -- Whether AVX10 includes xmm registers.
 230
 231 @item
 232 @code{AVX10_YMM} -- Whether AVX10 includes ymm registers.
 233
 234 @item
 235 @code{AVX10_ZMM} -- Whether AVX10 includes zmm registers.
 236
 237 @item
 238 @code{AVX2} -- The AVX2 instruction extensions.
 239
 240 @item
 241 @code{AVX_IFMA} -- The AVX-IFMA instruction extensions.
 242
 243 @item
 244 @code{AVX_NE_CONVERT} -- The AVX-NE-CONVERT instruction extensions.
 245
 246 @item
 247 @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
 248
 249 @item
 250 @code{AVX_VNNI_INT8} -- The AVX-VNNI-INT8 instruction extensions.
 251
 252 @item
 253 @code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
 254
 255 @item
 256 @code{AVX512_4VNNIW} -- The AVX512_4VNNIW instruction extensions.
 257
 258 @item
 259 @code{AVX512_BF16} -- The AVX512_BF16 instruction extensions.
 260
 261 @item
 262 @code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions.
 263
 264 @item
 265 @code{AVX512_FP16} -- The AVX512_FP16 instruction extensions.
 266
 267 @item
 268 @code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions.
 269
 270 @item
 271 @code{AVX512_VBMI} -- The AVX512_VBMI instruction extensions.
 272
 273 @item
 274 @code{AVX512_VBMI2} -- The AVX512_VBMI2 instruction extensions.
 275
 276 @item
 277 @code{AVX512_VNNI} -- The AVX512_VNNI instruction extensions.
 278
 279 @item
 280 @code{AVX512_VP2INTERSECT} -- The AVX512_VP2INTERSECT instruction
 281 extensions.
 282
 283 @item
 284 @code{AVX512_VPOPCNTDQ} -- The AVX512_VPOPCNTDQ instruction extensions.
 285
 286 @item
 287 @code{AVX512BW} -- The AVX512BW instruction extensions.
 288
 289 @item
 290 @code{AVX512CD} -- The AVX512CD instruction extensions.
 291
 292 @item
 293 @code{AVX512ER} -- The AVX512ER instruction extensions.
 294
 295 @item
 296 @code{AVX512DQ} -- The AVX512DQ instruction extensions.
 297
 298 @item
 299 @code{AVX512F} -- The AVX512F instruction extensions.
 300
 301 @item
 302 @code{AVX512PF} -- The AVX512PF instruction extensions.
 303
 304 @item
 305 @code{AVX512VL} -- The AVX512VL instruction extensions.
 306
 307 @item
 308 @code{BMI1} -- BMI1 instructions.
 309
 310 @item
 311 @code{BMI2} -- BMI2 instructions.
 312
 313 @item
 314 @code{BUS_LOCK_DETECT} -- Bus lock debug exceptions.
 315
 316 @item
 317 @code{CLDEMOTE} -- CLDEMOTE instruction.
 318
 319 @item
 320 @code{CLFLUSHOPT} -- CLFLUSHOPT instruction.
 321
 322 @item
 323 @code{CLFSH} -- CLFLUSH instruction.
 324
 325 @item
 326 @code{CLWB} -- CLWB instruction.
 327
 328 @item
 329 @code{CMOV} -- Conditional Move instructions.
 330
 331 @item
 332 @code{CMPCCXADD} -- CMPccXADD instruction.
 333
 334 @item
 335 @code{CMPXCHG16B} -- CMPXCHG16B instruction.
 336
 337 @item
 338 @code{CNXT_ID} -- L1 Context ID.
 339
 340 @item
 341 @code{CORE_CAPABILITIES} -- IA32_CORE_CAPABILITIES MSR.
 342
 343 @item
 344 @code{CX8} -- CMPXCHG8B instruction.
 345
 346 @item
 347 @code{DCA} -- Data prefetch from a memory mapped device.
 348
 349 @item
 350 @code{DE} -- Debugging Extensions.
 351
 352 @item
 353 @code{DEPR_FPU_CS_DS} -- Deprecates FPU CS and FPU DS values.
 354
 355 @item
 356 @code{DS} -- Debug Store.
 357
 358 @item
 359 @code{DS_CPL} -- CPL Qualified Debug Store.
 360
 361 @item
 362 @code{DTES64} -- 64-bit DS Area.
 363
 364 @item
 365 @code{EIST} -- Enhanced Intel SpeedStep technology.
 366
 367 @item
 368 @code{ENQCMD} -- Enqueue Stores instructions.
 369
 370 @item
 371 @code{ERMS} -- Enhanced REP MOVSB/STOSB.
 372
 373 @item
 374 @code{F16C} -- 16-bit floating-point conversion instructions.
 375
 376 @item
 377 @code{FMA} -- FMA extensions using YMM state.
 378
 379 @item
 380 @code{FMA4} -- FMA4 instruction extensions.
 381
 382 @item
 383 @code{FPU} -- X87 Floating Point Unit On-Chip.
 384
 385 @item
 386 @code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
 387
 388 @item
 389 @code{FSRCS} -- Fast Short REP CMP and SCA.
 390
 391 @item
 392 @code{FSRM} -- Fast Short REP MOV.
 393
 394 @item
 395 @code{FSRS} -- Fast Short REP STO.
 396
 397 @item
 398 @code{FXSR} -- FXSAVE and FXRSTOR instructions.
 399
 400 @item
 401 @code{FZLRM} -- Fast Zero-Length REP MOV.
 402
 403 @item
 404 @code{GFNI} -- GFNI instruction extensions.
 405
 406 @item
 407 @code{HLE} -- HLE instruction extensions.
 408
 409 @item
 410 @code{HTT} -- Max APIC IDs reserved field is Valid.
 411
 412 @item
 413 @code{HRESET} -- History reset.
 414
 415 @item
 416 @code{HYBRID} -- Hybrid processor.
 417
 418 @item
 419 @code{IBRS_IBPB} -- Indirect branch restricted speculation (IBRS) and
 420 the indirect branch predictor barrier (IBPB).
 421
 422 @item
 423 @code{IBT} -- Intel Indirect Branch Tracking instruction extensions.
 424
 425 @item
 426 @code{INVARIANT_TSC} -- Invariant TSC.
 427
 428 @item
 429 @code{INVPCID} -- INVPCID instruction.
 430
 431 @item
 432 @code{KL} -- AES Key Locker instructions.
 433
 434 @item
 435 @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
 436
 437 @item
 438 @code{LA57} -- 57-bit linear addresses and five-level paging.
 439
 440 @item
 441 @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
 442
 443 @item
 444 @code{LAM} -- Linear Address Masking.
 445
 446 @item
 447 @code{LASS} -- Linear Address Space Separation.
 448
 449 @item
 450 @code{LBR} -- Architectural LBR.
 451
 452 @item
 453 @code{LM} -- Long mode.
 454
 455 @item
 456 @code{LWP} -- Lightweight profiling.
 457
 458 @item
 459 @code{LZCNT} -- LZCNT instruction.
 460
 461 @item
 462 @code{MCA} -- Machine Check Architecture.
 463
 464 @item
 465 @code{MCE} -- Machine Check Exception.
 466
 467 @item
 468 @code{MD_CLEAR} -- MD_CLEAR.
 469
 470 @item
 471 @code{MMX} -- Intel MMX Technology.
 472
 473 @item
 474 @code{MONITOR} --  MONITOR/MWAIT instructions.
 475
 476 @item
 477 @code{MOVBE} -- MOVBE instruction.
 478
 479 @item
 480 @code{MOVDIRI} -- MOVDIRI instruction.
 481
 482 @item
 483 @code{MOVDIR64B} -- MOVDIR64B instruction.
 484
 485 @item
 486 @code{MPX} -- Intel Memory Protection Extensions.
 487
 488 @item
 489 @code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
 490
 491 @item
 492 @code{MSRLIST} -- RDMSRLIST/WRMSRLIST instructions and IA32_BARRIER
 493 MSR.
 494
 495 @item
 496 @code{MTRR} -- Memory Type Range Registers.
 497
 498 @item
 499 @code{NX} -- No-execute page protection.
 500
 501 @item
 502 @code{OSPKE} -- OS has set CR4.PKE to enable protection keys.
 503
 504 @item
 505 @code{OSXSAVE} -- The OS has set CR4.OSXSAVE[bit 18] to enable
 506 XSETBV/XGETBV instructions to access XCR0 and to support processor
 507 extended state management using XSAVE/XRSTOR.
 508
 509 @item
 510 @code{PAE} -- Physical Address Extension.
 511
 512 @item
 513 @code{PAGE1GB} -- 1-GByte page.
 514
 515 @item
 516 @code{PAT} -- Page Attribute Table.
 517
 518 @item
 519 @code{PBE} -- Pending Break Enable.
 520
 521 @item
 522 @code{PCID} -- Process-context identifiers.
 523
 524 @item
 525 @code{PCLMULQDQ} -- PCLMULQDQ instruction.
 526
 527 @item
 528 @code{PCONFIG} -- PCONFIG instruction.
 529
 530 @item
 531 @code{PDCM} -- Perfmon and Debug Capability.
 532
 533 @item
 534 @code{PGE} -- Page Global Bit.
 535
 536 @item
 537 @code{PKS} -- Protection keys for supervisor-mode pages.
 538
 539 @item
 540 @code{PKU} -- Protection keys for user-mode pages.
 541
 542 @item
 543 @code{POPCNT} -- POPCNT instruction.
 544
 545 @item
 546 @code{PREFETCHW} -- PREFETCHW instruction.
 547
 548 @item
 549 @code{PREFETCHWT1} -- PREFETCHWT1 instruction.
 550
 551 @item
 552 @code{PREFETCHI} -- PREFETCHIT0/1 instructions.
 553
 554 @item
 555 @code{PSE} -- Page Size Extension.
 556
 557 @item
 558 @code{PSE_36} -- 36-Bit Page Size Extension.
 559
 560 @item
 561 @code{PSN} -- Processor Serial Number.
 562
 563 @item
 564 @code{PTWRITE} -- PTWRITE instruction.
 565
 566 @item
 567 @code{RAO_INT} -- RAO-INT instructions.
 568
 569 @item
 570 @code{RDPID} -- RDPID instruction.
 571
 572 @item
 573 @code{RDRAND} -- RDRAND instruction.
 574
 575 @item
 576 @code{RDSEED} -- RDSEED instruction.
 577
 578 @item
 579 @code{RDT_A} -- Intel Resource Director Technology (Intel RDT) Allocation
 580 capability.
 581
 582 @item
 583 @code{RDT_M} -- Intel Resource Director Technology (Intel RDT) Monitoring
 584 capability.
 585
 586 @item
 587 @code{RDTSCP} -- RDTSCP instruction.
 588
 589 @item
 590 @code{RTM} -- RTM instruction extensions.
 591
 592 @item
 593 @code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable.
 594
 595 @item
 596 @code{RTM_FORCE_ABORT} -- TSX_FORCE_ABORT MSR.
 597
 598 @item
 599 @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
 600
 601 @item
 602 @code{SEP} -- SYSENTER and SYSEXIT instructions.
 603
 604 @item
 605 @code{SERIALIZE} -- SERIALIZE instruction.
 606
 607 @item
 608 @code{SGX} -- Intel Software Guard Extensions.
 609
 610 @item
 611 @code{SGX_KEYS} -- Attestation Services for SGX.
 612
 613 @item
 614 @code{SGX_LC} -- SGX Launch Configuration.
 615
 616 @item
 617 @code{SHA} -- SHA instruction extensions.
 618
 619 @item
 620 @code{SHSTK} -- Intel Shadow Stack instruction extensions.
 621
 622 @item
 623 @code{SMAP} -- Supervisor-Mode Access Prevention.
 624
 625 @item
 626 @code{SMEP} -- Supervisor-Mode Execution Prevention.
 627
 628 @item
 629 @code{SMX} -- Safer Mode Extensions.
 630
 631 @item
 632 @code{SS} -- Self Snoop.
 633
 634 @item
 635 @code{SSBD} -- Speculative Store Bypass Disable (SSBD).
 636
 637 @item
 638 @code{SSE} -- Streaming SIMD Extensions.
 639
 640 @item
 641 @code{SSE2} -- Streaming SIMD Extensions 2.
 642
 643 @item
 644 @code{SSE3} -- Streaming SIMD Extensions 3.
 645
 646 @item
 647 @code{SSE4_1} -- Streaming SIMD Extensions 4.1.
 648
 649 @item
 650 @code{SSE4_2} -- Streaming SIMD Extensions 4.2.
 651
 652 @item
 653 @code{SSE4A} -- SSE4A instruction extensions.
 654
 655 @item
 656 @code{SSSE3} -- Supplemental Streaming SIMD Extensions 3.
 657
 658 @item
 659 @code{STIBP} -- Single thread indirect branch predictors (STIBP).
 660
 661 @item
 662 @code{SVM} -- Secure Virtual Machine.
 663
 664 @item
 665 @code{SYSCALL_SYSRET} -- SYSCALL/SYSRET instructions.
 666
 667 @item
 668 @code{TBM} -- Trailing bit manipulation instructions.
 669
 670 @item
 671 @code{TM} -- Thermal Monitor.
 672
 673 @item
 674 @code{TM2} -- Thermal Monitor 2.
 675
 676 @item
 677 @code{TRACE} -- Intel Processor Trace.
 678
 679 @item
 680 @code{TSC} -- Time Stamp Counter.  RDTSC instruction.
 681
 682 @item
 683 @code{TSC_ADJUST} -- IA32_TSC_ADJUST MSR.
 684
 685 @item
 686 @code{TSC_DEADLINE} -- Local APIC timer supports one-shot operation
 687 using a TSC deadline value.
 688
 689 @item
 690 @code{TSXLDTRK} -- TSXLDTRK instructions.
 691
 692 @item
 693 @code{UINTR} -- User interrupts.
 694
 695 @item
 696 @code{UMIP} -- User-mode instruction prevention.
 697
 698 @item
 699 @code{VAES} -- VAES instruction extensions.
 700
 701 @item
 702 @code{VME} -- Virtual 8086 Mode Enhancements.
 703
 704 @item
 705 @code{VMX} -- Virtual Machine Extensions.
 706
 707 @item
 708 @code{VPCLMULQDQ} -- VPCLMULQDQ instruction.
 709
 710 @item
 711 @code{WAITPKG} -- WAITPKG instruction extensions.
 712
 713 @item
 714 @code{WBNOINVD} -- WBINVD/WBNOINVD instructions.
 715
 716 @item
 717 @code{WIDE_KL} -- AES wide Key Locker instructions.
 718
 719 @item
 720 @code{WRMSRNS} -- WRMSRNS instruction.
 721
 722 @item
 723 @code{X2APIC} -- x2APIC.
 724
 725 @item
 726 @code{XFD} -- Extended Feature Disable (XFD).
 727
 728 @item
 729 @code{XGETBV_ECX_1} -- XGETBV with ECX = 1.
 730
 731 @item
 732 @code{XOP} -- XOP instruction extensions.
 733
 734 @item
 735 @code{XSAVE} -- The XSAVE/XRSTOR processor extended states feature, the
 736 XSETBV/XGETBV instructions, and XCR0.
 737
 738 @item
 739 @code{XSAVEC} -- XSAVEC instruction.
 740
 741 @item
 742 @code{XSAVEOPT} -- XSAVEOPT instruction.
 743
 744 @item
 745 @code{XSAVES} -- XSAVES/XRSTORS instructions.
 746
 747 @item
 748 @code{XTPRUPDCTRL} -- xTPR Update Control.
 749
 750 @end itemize
 751
 752 You could query if a processor supports @code{AVX} with:
 753
 754 @smallexample
 755 #include <sys/platform/x86.h>
 756
 757 int
 758 avx_present (void)
 759 @{
 760   return CPU_FEATURE_PRESENT (AVX);
 761 @}
 762 @end smallexample
 763
 764 and if @code{AVX} is active and may be used with:
 765
 766 @smallexample
 767 #include <sys/platform/x86.h>
 768
 769 int
 770 avx_active (void)
 771 @{
 772   return CPU_FEATURE_ACTIVE (AVX);
 773 @}
 774 @end smallexample