2 From: http://xenbits.xensource.com/linux-2.6.18-xen.hg (tip 728:832aac894efd)
3 Patch-mainline: obsolete
4 Acked-by: jbeulich@novell.com
6 List of files having Xen derivates (perhaps created during the merging
7 of newer kernel versions), for xen-port-patches.py to pick up (i.e. this
8 must be retained here until the XenSource tree has these in the right
10 +++ linux/arch/x86/kernel/acpi/sleep-xen.c
11 +++ linux/arch/x86/kernel/cpu/common_64-xen.c
12 +++ linux/arch/x86/kernel/e820-xen.c
13 +++ linux/arch/x86/kernel/head-xen.c
14 +++ linux/arch/x86/kernel/head32-xen.c
15 +++ linux/arch/x86/kernel/ioport-xen.c
16 +++ linux/arch/x86/kernel/ipi-xen.c
17 +++ linux/arch/x86/kernel/ldt-xen.c
18 +++ linux/arch/x86/kernel/mpparse-xen.c
19 +++ linux/arch/x86/kernel/pci-nommu-xen.c
20 +++ linux/arch/x86/kernel/process-xen.c
21 +++ linux/arch/x86/kernel/setup-xen.c
22 +++ linux/arch/x86/kernel/setup_percpu-xen.c
23 +++ linux/arch/x86/kernel/smp-xen.c
24 +++ linux/arch/x86/mm/fault-xen.c
25 +++ linux/arch/x86/mm/ioremap-xen.c
26 +++ linux/arch/x86/mm/pageattr-xen.c
27 +++ linux/arch/x86/mm/pat-xen.c
28 +++ linux/arch/x86/mm/pgtable-xen.c
29 +++ linux/arch/x86/vdso/vdso32-setup-xen.c
30 +++ linux/drivers/char/mem-xen.c
31 +++ linux/include/asm-x86/mach-xen/asm/desc.h
32 +++ linux/include/asm-x86/mach-xen/asm/dma-mapping.h
33 +++ linux/include/asm-x86/mach-xen/asm/fixmap.h
34 +++ linux/include/asm-x86/mach-xen/asm/io.h
35 +++ linux/include/asm-x86/mach-xen/asm/irq_vectors.h
36 +++ linux/include/asm-x86/mach-xen/asm/irqflags.h
37 +++ linux/include/asm-x86/mach-xen/asm/mmu_context.h
38 +++ linux/include/asm-x86/mach-xen/asm/page.h
39 +++ linux/include/asm-x86/mach-xen/asm/pci.h
40 +++ linux/include/asm-x86/mach-xen/asm/pgalloc.h
41 +++ linux/include/asm-x86/mach-xen/asm/pgtable.h
42 +++ linux/include/asm-x86/mach-xen/asm/processor.h
43 +++ linux/include/asm-x86/mach-xen/asm/segment.h
44 +++ linux/include/asm-x86/mach-xen/asm/smp.h
45 +++ linux/include/asm-x86/mach-xen/asm/spinlock.h
46 +++ linux/include/asm-x86/mach-xen/asm/swiotlb.h
47 +++ linux/include/asm-x86/mach-xen/asm/system.h
48 +++ linux/include/asm-x86/mach-xen/asm/tlbflush.h
49 +++ linux/include/asm-x86/mach-xen/asm/xor.h
51 List of files folded into their native counterparts (and hence removed
52 from this patch for xen-port-patches.py to not needlessly pick them up;
53 for reference, prefixed with the version the removal occured):
54 2.6.18/include/asm-x86/mach-xen/asm/pgtable-2level.h
55 2.6.18/include/asm-x86/mach-xen/asm/pgtable-2level-defs.h
56 2.6.19/include/asm-x86/mach-xen/asm/ptrace.h
57 2.6.23/arch/x86/kernel/vsyscall-note_32-xen.S
58 2.6.23/include/asm-x86/mach-xen/asm/ptrace_64.h
59 2.6.24/arch/x86/kernel/early_printk_32-xen.c
60 2.6.24/include/asm-x86/mach-xen/asm/arch_hooks_64.h
61 2.6.24/include/asm-x86/mach-xen/asm/bootsetup_64.h
62 2.6.24/include/asm-x86/mach-xen/asm/mmu_32.h
63 2.6.24/include/asm-x86/mach-xen/asm/mmu_64.h
64 2.6.24/include/asm-x86/mach-xen/asm/nmi_64.h
65 2.6.24/include/asm-x86/mach-xen/asm/setup.h
66 2.6.24/include/asm-x86/mach-xen/asm/time_64.h (added in 2.6.20)
67 2.6.24/include/asm-x86/mach-xen/mach_timer.h
68 2.6.25/arch/x86/ia32/syscall32-xen.c
69 2.6.25/arch/x86/ia32/syscall32_syscall-xen.S
70 2.6.25/arch/x86/ia32/vsyscall-int80.S
71 2.6.25/arch/x86/kernel/acpi/boot-xen.c
72 2.6.25/include/asm-x86/mach-xen/asm/msr.h
73 2.6.25/include/asm-x86/mach-xen/asm/page_32.h
74 2.6.25/include/asm-x86/mach-xen/asm/spinlock_32.h
75 2.6.25/include/asm-x86/mach-xen/asm/timer.h (added in 2.6.24)
76 2.6.25/include/asm-x86/mach-xen/asm/timer_64.h
77 2.6.25/include/asm-x86/mach-xen/mach_time.h
78 2.6.26/arch/x86/kernel/pci-dma_32-xen.c
79 2.6.26/arch/x86/kernel/pci-swiotlb_64-xen.c
80 2.6.26/include/asm-x86/mach-xen/asm/dma-mapping_32.h
81 2.6.26/include/asm-x86/mach-xen/asm/dma-mapping_64.h
82 2.6.26/include/asm-x86/mach-xen/asm/nmi.h (added in 2.6.24)
83 2.6.26/include/asm-x86/mach-xen/asm/scatterlist.h (added in 2.6.24)
84 2.6.26/include/asm-x86/mach-xen/asm/scatterlist_32.h
85 2.6.26/include/xen/xencomm.h
86 2.6.27/arch/x86/kernel/e820_32-xen.c
87 2.6.27/include/asm-x86/mach-xen/asm/e820.h (added in 2.6.24)
88 2.6.27/include/asm-x86/mach-xen/asm/e820_64.h
89 2.6.27/include/asm-x86/mach-xen/asm/hw_irq.h (added in 2.6.24)
90 2.6.27/include/asm-x86/mach-xen/asm/hw_irq_32.h
91 2.6.27/include/asm-x86/mach-xen/asm/hw_irq_64.h
92 2.6.27/include/asm-x86/mach-xen/asm/io_32.h
93 2.6.27/include/asm-x86/mach-xen/asm/io_64.h
94 2.6.27/include/asm-x86/mach-xen/asm/irq.h (added in 2.6.24)
95 2.6.27/include/asm-x86/mach-xen/asm/irq_64.h
96 2.6.27.8/include/asm-x86/mach-xen/asm/pci_64.h
98 Index: head-2008-11-25/arch/x86/kernel/acpi/processor_extcntl_xen.c
99 ===================================================================
100 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
101 +++ head-2008-11-25/arch/x86/kernel/acpi/processor_extcntl_xen.c 2008-10-01 15:43:24.000000000 +0200
104 + * processor_extcntl_xen.c - interface to notify Xen
106 + * Copyright (C) 2008, Intel corporation
108 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
110 + * This program is free software; you can redistribute it and/or modify
111 + * it under the terms of the GNU General Public License as published by
112 + * the Free Software Foundation; either version 2 of the License, or (at
113 + * your option) any later version.
115 + * This program is distributed in the hope that it will be useful, but
116 + * WITHOUT ANY WARRANTY; without even the implied warranty of
117 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
118 + * General Public License for more details.
120 + * You should have received a copy of the GNU General Public License along
121 + * with this program; if not, write to the Free Software Foundation, Inc.,
122 + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
126 +#include <linux/kernel.h>
127 +#include <linux/init.h>
128 +#include <linux/types.h>
129 +#include <linux/acpi.h>
130 +#include <linux/pm.h>
131 +#include <linux/cpu.h>
133 +#include <linux/cpufreq.h>
134 +#include <acpi/processor.h>
135 +#include <asm/hypercall.h>
137 +static int xen_cx_notifier(struct acpi_processor *pr, int action)
139 + int ret, count = 0, i;
140 + xen_platform_op_t op = {
141 + .cmd = XENPF_set_processor_pminfo,
142 + .interface_version = XENPF_INTERFACE_VERSION,
143 + .u.set_pminfo.id = pr->acpi_id,
144 + .u.set_pminfo.type = XEN_PM_CX,
146 + struct xen_processor_cx *data, *buf;
147 + struct acpi_processor_cx *cx;
149 + if (action == PROCESSOR_PM_CHANGE)
152 + /* Convert to Xen defined structure and hypercall */
153 + buf = kzalloc(pr->power.count * sizeof(struct xen_processor_cx),
159 + for (i = 1; i <= pr->power.count; i++) {
160 + cx = &pr->power.states[i];
161 + /* Skip invalid cstate entry */
165 + data->type = cx->type;
166 + data->latency = cx->latency;
167 + data->power = cx->power;
168 + data->reg.space_id = cx->reg.space_id;
169 + data->reg.bit_width = cx->reg.bit_width;
170 + data->reg.bit_offset = cx->reg.bit_offset;
171 + data->reg.access_size = cx->reg.reserved;
172 + data->reg.address = cx->reg.address;
174 + /* Get dependency relationships */
175 + if (cx->csd_count) {
176 + printk("Wow! _CSD is found. Not support for now!\n");
181 + set_xen_guest_handle(data->dp, NULL);
189 + printk("No available Cx info for cpu %d\n", pr->acpi_id);
194 + op.u.set_pminfo.power.count = count;
195 + op.u.set_pminfo.power.flags.bm_control = pr->flags.bm_control;
196 + op.u.set_pminfo.power.flags.bm_check = pr->flags.bm_check;
197 + op.u.set_pminfo.power.flags.has_cst = pr->flags.has_cst;
198 + op.u.set_pminfo.power.flags.power_setup_done = pr->flags.power_setup_done;
200 + set_xen_guest_handle(op.u.set_pminfo.power.states, buf);
201 + ret = HYPERVISOR_platform_op(&op);
206 +static int xen_px_notifier(struct acpi_processor *pr, int action)
209 + xen_platform_op_t op = {
210 + .cmd = XENPF_set_processor_pminfo,
211 + .interface_version = XENPF_INTERFACE_VERSION,
212 + .u.set_pminfo.id = pr->acpi_id,
213 + .u.set_pminfo.type = XEN_PM_PX,
215 + struct xen_processor_performance *perf;
216 + struct xen_processor_px *states = NULL;
217 + struct acpi_processor_performance *px;
218 + struct acpi_psd_package *pdomain;
223 + perf = &op.u.set_pminfo.perf;
224 + px = pr->performance;
227 + case PROCESSOR_PM_CHANGE:
228 + /* ppc dynamic handle */
229 + perf->flags = XEN_PX_PPC;
230 + perf->platform_limit = pr->performance_platform_limit;
232 + ret = HYPERVISOR_platform_op(&op);
235 + case PROCESSOR_PM_INIT:
236 + /* px normal init */
237 + perf->flags = XEN_PX_PPC |
243 + perf->platform_limit = pr->performance_platform_limit;
246 + xen_convert_pct_reg(&perf->control_register, &px->control_register);
247 + xen_convert_pct_reg(&perf->status_register, &px->status_register);
250 + perf->state_count = px->state_count;
251 + states = kzalloc(px->state_count*sizeof(xen_processor_px_t),GFP_KERNEL);
254 + xen_convert_pss_states(states, px->states, px->state_count);
255 + set_xen_guest_handle(perf->states, states);
258 + pdomain = &px->domain_info;
259 + xen_convert_psd_pack(&perf->domain_info, pdomain);
260 + if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
261 + perf->shared_type = CPUFREQ_SHARED_TYPE_ALL;
262 + else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
263 + perf->shared_type = CPUFREQ_SHARED_TYPE_ANY;
264 + else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
265 + perf->shared_type = CPUFREQ_SHARED_TYPE_HW;
272 + ret = HYPERVISOR_platform_op(&op);
283 +static int xen_tx_notifier(struct acpi_processor *pr, int action)
287 +static int xen_hotplug_notifier(struct acpi_processor *pr, int event)
292 +static struct processor_extcntl_ops xen_extcntl_ops = {
293 + .hotplug = xen_hotplug_notifier,
296 +void arch_acpi_processor_init_extcntl(const struct processor_extcntl_ops **ops)
298 + unsigned int pmbits = (xen_start_info->flags & SIF_PM_MASK) >> 8;
302 + if (pmbits & XEN_PROCESSOR_PM_CX)
303 + xen_extcntl_ops.pm_ops[PM_TYPE_IDLE] = xen_cx_notifier;
304 + if (pmbits & XEN_PROCESSOR_PM_PX)
305 + xen_extcntl_ops.pm_ops[PM_TYPE_PERF] = xen_px_notifier;
306 + if (pmbits & XEN_PROCESSOR_PM_TX)
307 + xen_extcntl_ops.pm_ops[PM_TYPE_THR] = xen_tx_notifier;
309 + *ops = &xen_extcntl_ops;
311 +EXPORT_SYMBOL(arch_acpi_processor_init_extcntl);
312 Index: head-2008-11-25/arch/x86/kernel/acpi/sleep_32-xen.c
313 ===================================================================
314 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
315 +++ head-2008-11-25/arch/x86/kernel/acpi/sleep_32-xen.c 2008-04-15 09:29:41.000000000 +0200
318 + * sleep.c - x86-specific ACPI sleep support.
320 + * Copyright (C) 2001-2003 Patrick Mochel
321 + * Copyright (C) 2001-2003 Pavel Machek <pavel@suse.cz>
324 +#include <linux/acpi.h>
325 +#include <linux/bootmem.h>
326 +#include <linux/dmi.h>
327 +#include <linux/cpumask.h>
329 +#include <asm/smp.h>
331 +#ifndef CONFIG_ACPI_PV_SLEEP
332 +/* address in low memory of the wakeup routine. */
333 +unsigned long acpi_wakeup_address = 0;
334 +unsigned long acpi_video_flags;
335 +extern char wakeup_start, wakeup_end;
337 +extern unsigned long FASTCALL(acpi_copy_wakeup_routine(unsigned long));
341 + * acpi_save_state_mem - save kernel state
343 + * Create an identity mapped page table and copy the wakeup routine to
346 +int acpi_save_state_mem(void)
348 +#ifndef CONFIG_ACPI_PV_SLEEP
349 + if (!acpi_wakeup_address)
351 + memcpy((void *)acpi_wakeup_address, &wakeup_start,
352 + &wakeup_end - &wakeup_start);
353 + acpi_copy_wakeup_routine(acpi_wakeup_address);
359 + * acpi_restore_state - undo effects of acpi_save_state_mem
361 +void acpi_restore_state_mem(void)
366 + * acpi_reserve_bootmem - do _very_ early ACPI initialisation
368 + * We allocate a page from the first 1MB of memory for the wakeup
369 + * routine for when we come back from a sleep state. The
370 + * runtime allocator allows specification of <16MB pages, but not
373 +void __init acpi_reserve_bootmem(void)
375 +#ifndef CONFIG_ACPI_PV_SLEEP
376 + if ((&wakeup_end - &wakeup_start) > PAGE_SIZE) {
378 + "ACPI: Wakeup code way too big, S3 disabled.\n");
382 + acpi_wakeup_address = (unsigned long)alloc_bootmem_low(PAGE_SIZE);
383 + if (!acpi_wakeup_address)
384 + printk(KERN_ERR "ACPI: Cannot allocate lowmem, S3 disabled.\n");
388 +#ifndef CONFIG_ACPI_PV_SLEEP
389 +static int __init acpi_sleep_setup(char *str)
391 + while ((str != NULL) && (*str != '\0')) {
392 + if (strncmp(str, "s3_bios", 7) == 0)
393 + acpi_video_flags = 1;
394 + if (strncmp(str, "s3_mode", 7) == 0)
395 + acpi_video_flags |= 2;
396 + str = strchr(str, ',');
398 + str += strspn(str, ", \t");
403 +__setup("acpi_sleep=", acpi_sleep_setup);
405 +static __init int reset_videomode_after_s3(struct dmi_system_id *d)
407 + acpi_video_flags |= 2;
411 +static __initdata struct dmi_system_id acpisleep_dmi_table[] = {
412 + { /* Reset video mode after returning from ACPI S3 sleep */
413 + .callback = reset_videomode_after_s3,
414 + .ident = "Toshiba Satellite 4030cdt",
416 + DMI_MATCH(DMI_PRODUCT_NAME, "S4030CDT/4.3"),
422 +static int __init acpisleep_dmi_init(void)
424 + dmi_check_system(acpisleep_dmi_table);
428 +core_initcall(acpisleep_dmi_init);
429 +#endif /* CONFIG_ACPI_PV_SLEEP */
430 Index: head-2008-11-25/arch/x86/kernel/apic_32-xen.c
431 ===================================================================
432 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
433 +++ head-2008-11-25/arch/x86/kernel/apic_32-xen.c 2007-06-12 13:12:48.000000000 +0200
436 + * Local APIC handling, local APIC timers
438 + * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
441 + * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
442 + * thanks to Eric Gilmore
444 + * for testing these extensively.
445 + * Maciej W. Rozycki : Various updates and fixes.
446 + * Mikael Pettersson : Power Management for UP-APIC.
448 + * Mikael Pettersson : PM converted to driver model.
451 +#include <linux/init.h>
453 +#include <linux/mm.h>
454 +#include <linux/delay.h>
455 +#include <linux/bootmem.h>
456 +#include <linux/smp_lock.h>
457 +#include <linux/interrupt.h>
458 +#include <linux/mc146818rtc.h>
459 +#include <linux/kernel_stat.h>
460 +#include <linux/sysdev.h>
461 +#include <linux/cpu.h>
462 +#include <linux/module.h>
464 +#include <asm/atomic.h>
465 +#include <asm/smp.h>
466 +#include <asm/mtrr.h>
467 +#include <asm/mpspec.h>
468 +#include <asm/desc.h>
469 +#include <asm/arch_hooks.h>
470 +#include <asm/hpet.h>
471 +#include <asm/i8253.h>
472 +#include <asm/nmi.h>
474 +#include <mach_apic.h>
475 +#include <mach_apicdef.h>
476 +#include <mach_ipi.h>
478 +#include "io_ports.h"
482 + * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
483 + * IPIs in place of local APIC timers
485 +static cpumask_t timer_bcast_ipi;
489 + * Knob to control our willingness to enable the local APIC.
491 +int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
499 +static int modern_apic(void)
501 + unsigned int lvr, version;
502 + /* AMD systems use old APIC versions, so check the CPU */
503 + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
504 + boot_cpu_data.x86 >= 0xf)
506 + lvr = apic_read(APIC_LVR);
507 + version = GET_APIC_VERSION(lvr);
508 + return version >= 0x14;
510 +#endif /* !CONFIG_XEN */
513 + * 'what should we do if we get a hw irq event on an illegal vector'.
514 + * each architecture has to answer this themselves.
516 +void ack_bad_irq(unsigned int irq)
518 + printk("unexpected IRQ trap at vector %02x\n", irq);
520 + * Currently unexpected vectors happen only on SMP and APIC.
521 + * We _must_ ack these because every local APIC has only N
522 + * irq slots per priority level, and a 'hanging, unacked' IRQ
523 + * holds up an irq slot - in excessive cases (when multiple
524 + * unexpected vectors occur) that might lock up the APIC
526 + * But only ack when the APIC is enabled -AK
532 +int get_physical_broadcast(void)
539 +static void up_apic_timer_interrupt_call(struct pt_regs *regs)
541 + int cpu = smp_processor_id();
544 + * the NMI deadlock-detector uses this.
546 + per_cpu(irq_stat, cpu).apic_timer_irqs++;
548 + smp_local_timer_interrupt(regs);
552 +void smp_send_timer_broadcast_ipi(struct pt_regs *regs)
556 + cpus_and(mask, cpu_online_map, timer_bcast_ipi);
557 + if (!cpus_empty(mask)) {
559 + send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
562 + * We can directly call the apic timer interrupt handler
563 + * in UP case. Minus all irq related functions
565 + up_apic_timer_interrupt_call(regs);
571 +int setup_profiling_timer(unsigned int multiplier)
577 + * This initializes the IO-APIC and APIC hardware if this is
580 +int __init APIC_init_uniprocessor (void)
582 +#ifdef CONFIG_X86_IO_APIC
583 + if (smp_found_config)
584 + if (!skip_ioapic_setup && nr_ioapics)
590 Index: head-2008-11-25/arch/x86/kernel/cpu/common-xen.c
591 ===================================================================
592 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
593 +++ head-2008-11-25/arch/x86/kernel/cpu/common-xen.c 2007-12-10 08:47:31.000000000 +0100
595 +#include <linux/init.h>
596 +#include <linux/string.h>
597 +#include <linux/delay.h>
598 +#include <linux/smp.h>
599 +#include <linux/module.h>
600 +#include <linux/percpu.h>
601 +#include <linux/bootmem.h>
602 +#include <asm/semaphore.h>
603 +#include <asm/processor.h>
604 +#include <asm/i387.h>
605 +#include <asm/msr.h>
607 +#include <asm/mmu_context.h>
608 +#include <asm/mtrr.h>
609 +#include <asm/mce.h>
610 +#ifdef CONFIG_X86_LOCAL_APIC
611 +#include <asm/mpspec.h>
612 +#include <asm/apic.h>
613 +#include <mach_apic.h>
616 +#define phys_pkg_id(a,b) a
619 +#include <asm/hypervisor.h>
623 +DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
624 +EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
627 +DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
628 +EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
631 +static int cachesize_override __cpuinitdata = -1;
632 +static int disable_x86_fxsr __cpuinitdata;
633 +static int disable_x86_serial_nr __cpuinitdata = 1;
634 +static int disable_x86_sep __cpuinitdata;
636 +struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
638 +extern int disable_pse;
640 +static void default_init(struct cpuinfo_x86 * c)
642 + /* Not much we can do here... */
643 + /* Check if at least it has cpuid */
644 + if (c->cpuid_level == -1) {
645 + /* No cpuid. It must be an ancient CPU */
647 + strcpy(c->x86_model_id, "486");
648 + else if (c->x86 == 3)
649 + strcpy(c->x86_model_id, "386");
653 +static struct cpu_dev default_cpu = {
654 + .c_init = default_init,
655 + .c_vendor = "Unknown",
657 +static struct cpu_dev * this_cpu = &default_cpu;
659 +static int __init cachesize_setup(char *str)
661 + get_option (&str, &cachesize_override);
664 +__setup("cachesize=", cachesize_setup);
666 +int __cpuinit get_model_name(struct cpuinfo_x86 *c)
671 + if (cpuid_eax(0x80000000) < 0x80000004)
674 + v = (unsigned int *) c->x86_model_id;
675 + cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
676 + cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
677 + cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
678 + c->x86_model_id[48] = 0;
680 + /* Intel chips right-justify this string for some dumb reason;
681 + undo that brain damage */
682 + p = q = &c->x86_model_id[0];
683 + while ( *p == ' ' )
688 + while ( q <= &c->x86_model_id[48] )
689 + *q++ = '\0'; /* Zero-pad the rest */
696 +void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
698 + unsigned int n, dummy, ecx, edx, l2size;
700 + n = cpuid_eax(0x80000000);
702 + if (n >= 0x80000005) {
703 + cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
704 + printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
705 + edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
706 + c->x86_cache_size=(ecx>>24)+(edx>>24);
709 + if (n < 0x80000006) /* Some chips just has a large L1. */
712 + ecx = cpuid_ecx(0x80000006);
713 + l2size = ecx >> 16;
715 + /* do processor-specific cache resizing */
716 + if (this_cpu->c_size_cache)
717 + l2size = this_cpu->c_size_cache(c,l2size);
719 + /* Allow user to override all this if necessary. */
720 + if (cachesize_override != -1)
721 + l2size = cachesize_override;
724 + return; /* Again, no L2 cache is possible */
726 + c->x86_cache_size = l2size;
728 + printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
729 + l2size, ecx & 0xFF);
732 +/* Naming convention should be: <Name> [(<Codename>)] */
733 +/* This table only is used unless init_<vendor>() below doesn't set it; */
734 +/* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
736 +/* Look up CPU names by table lookup. */
737 +static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
739 + struct cpu_model_info *info;
741 + if ( c->x86_model >= 16 )
742 + return NULL; /* Range check */
747 + info = this_cpu->c_models;
749 + while (info && info->family) {
750 + if (info->family == c->x86)
751 + return info->model_names[c->x86_model];
754 + return NULL; /* Not found */
758 +static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
760 + char *v = c->x86_vendor_id;
762 + static int printed;
764 + for (i = 0; i < X86_VENDOR_NUM; i++) {
766 + if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
767 + (cpu_devs[i]->c_ident[1] &&
768 + !strcmp(v,cpu_devs[i]->c_ident[1]))) {
771 + this_cpu = cpu_devs[i];
778 + printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
779 + printk(KERN_ERR "CPU: Your system may be unstable.\n");
781 + c->x86_vendor = X86_VENDOR_UNKNOWN;
782 + this_cpu = &default_cpu;
786 +static int __init x86_fxsr_setup(char * s)
788 + disable_x86_fxsr = 1;
791 +__setup("nofxsr", x86_fxsr_setup);
794 +static int __init x86_sep_setup(char * s)
796 + disable_x86_sep = 1;
799 +__setup("nosep", x86_sep_setup);
802 +/* Standard macro to see if a specific flag is changeable */
803 +static inline int flag_is_changeable_p(u32 flag)
817 + : "=&r" (f1), "=&r" (f2)
820 + return ((f1^f2) & flag) != 0;
824 +/* Probe for the CPUID instruction */
825 +static int __cpuinit have_cpuid_p(void)
827 + return flag_is_changeable_p(X86_EFLAGS_ID);
830 +/* Do minimum CPU detection early.
831 + Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
832 + The others are not touched to avoid unwanted side effects.
834 + WARNING: this function is only called on the BP. Don't add code here
835 + that is supposed to run on all CPUs. */
836 +static void __init early_cpu_detect(void)
838 + struct cpuinfo_x86 *c = &boot_cpu_data;
840 + c->x86_cache_alignment = 32;
842 + if (!have_cpuid_p())
845 + /* Get vendor name */
846 + cpuid(0x00000000, &c->cpuid_level,
847 + (int *)&c->x86_vendor_id[0],
848 + (int *)&c->x86_vendor_id[8],
849 + (int *)&c->x86_vendor_id[4]);
851 + get_cpu_vendor(c, 1);
854 + if (c->cpuid_level >= 0x00000001) {
855 + u32 junk, tfms, cap0, misc;
856 + cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
857 + c->x86 = (tfms >> 8) & 15;
858 + c->x86_model = (tfms >> 4) & 15;
860 + c->x86 += (tfms >> 20) & 0xff;
862 + c->x86_model += ((tfms >> 16) & 0xF) << 4;
863 + c->x86_mask = tfms & 15;
864 + if (cap0 & (1<<19))
865 + c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
869 +void __cpuinit generic_identify(struct cpuinfo_x86 * c)
874 + if (have_cpuid_p()) {
875 + /* Get vendor name */
876 + cpuid(0x00000000, &c->cpuid_level,
877 + (int *)&c->x86_vendor_id[0],
878 + (int *)&c->x86_vendor_id[8],
879 + (int *)&c->x86_vendor_id[4]);
881 + get_cpu_vendor(c, 0);
882 + /* Initialize the standard set of capabilities */
883 + /* Note that the vendor-specific code below might override */
885 + /* Intel-defined flags: level 0x00000001 */
886 + if ( c->cpuid_level >= 0x00000001 ) {
887 + u32 capability, excap;
888 + cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
889 + c->x86_capability[0] = capability;
890 + c->x86_capability[4] = excap;
891 + c->x86 = (tfms >> 8) & 15;
892 + c->x86_model = (tfms >> 4) & 15;
894 + c->x86 += (tfms >> 20) & 0xff;
896 + c->x86_model += ((tfms >> 16) & 0xF) << 4;
897 + c->x86_mask = tfms & 15;
898 +#ifdef CONFIG_X86_HT
899 + c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
901 + c->apicid = (ebx >> 24) & 0xFF;
904 + /* Have CPUID level 0 only - unheard of */
908 + /* AMD-defined flags: level 0x80000001 */
909 + xlvl = cpuid_eax(0x80000000);
910 + if ( (xlvl & 0xffff0000) == 0x80000000 ) {
911 + if ( xlvl >= 0x80000001 ) {
912 + c->x86_capability[1] = cpuid_edx(0x80000001);
913 + c->x86_capability[6] = cpuid_ecx(0x80000001);
915 + if ( xlvl >= 0x80000004 )
916 + get_model_name(c); /* Default name */
920 + early_intel_workaround(c);
922 +#ifdef CONFIG_X86_HT
923 + c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
927 +static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
929 + if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
930 + /* Disable processor serial number */
931 + unsigned long lo,hi;
932 + rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
934 + wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
935 + printk(KERN_NOTICE "CPU serial number disabled.\n");
936 + clear_bit(X86_FEATURE_PN, c->x86_capability);
938 + /* Disabling the serial number may affect the cpuid level */
939 + c->cpuid_level = cpuid_eax(0);
943 +static int __init x86_serial_nr_setup(char *s)
945 + disable_x86_serial_nr = 0;
948 +__setup("serialnumber", x86_serial_nr_setup);
953 + * This does the hard work of actually picking apart the CPU stuff...
955 +void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
959 + c->loops_per_jiffy = loops_per_jiffy;
960 + c->x86_cache_size = -1;
961 + c->x86_vendor = X86_VENDOR_UNKNOWN;
962 + c->cpuid_level = -1; /* CPUID not detected */
963 + c->x86_model = c->x86_mask = 0; /* So far unknown... */
964 + c->x86_vendor_id[0] = '\0'; /* Unset */
965 + c->x86_model_id[0] = '\0'; /* Unset */
966 + c->x86_max_cores = 1;
967 + memset(&c->x86_capability, 0, sizeof c->x86_capability);
969 + if (!have_cpuid_p()) {
970 + /* First of all, decide if this is a 486 or higher */
971 + /* It's a 486 if we can modify the AC flag */
972 + if ( flag_is_changeable_p(X86_EFLAGS_AC) )
978 + generic_identify(c);
980 + printk(KERN_DEBUG "CPU: After generic identify, caps:");
981 + for (i = 0; i < NCAPINTS; i++)
982 + printk(" %08lx", c->x86_capability[i]);
985 + if (this_cpu->c_identify) {
986 + this_cpu->c_identify(c);
988 + printk(KERN_DEBUG "CPU: After vendor identify, caps:");
989 + for (i = 0; i < NCAPINTS; i++)
990 + printk(" %08lx", c->x86_capability[i]);
995 + * Vendor-specific initialization. In this section we
996 + * canonicalize the feature flags, meaning if there are
997 + * features a certain CPU supports which CPUID doesn't
998 + * tell us, CPUID claiming incorrect flags, or other bugs,
999 + * we handle them here.
1001 + * At the end of this section, c->x86_capability better
1002 + * indicate the features this CPU genuinely supports!
1004 + if (this_cpu->c_init)
1005 + this_cpu->c_init(c);
1007 + /* Disable the PN if appropriate */
1008 + squash_the_stupid_serial_number(c);
1011 + * The vendor-specific functions might have changed features. Now
1012 + * we do "generic changes."
1015 + /* TSC disabled? */
1016 + if ( tsc_disable )
1017 + clear_bit(X86_FEATURE_TSC, c->x86_capability);
1019 + /* FXSR disabled? */
1020 + if (disable_x86_fxsr) {
1021 + clear_bit(X86_FEATURE_FXSR, c->x86_capability);
1022 + clear_bit(X86_FEATURE_XMM, c->x86_capability);
1025 + /* SEP disabled? */
1026 + if (disable_x86_sep)
1027 + clear_bit(X86_FEATURE_SEP, c->x86_capability);
1030 + clear_bit(X86_FEATURE_PSE, c->x86_capability);
1032 + /* If the model name is still unset, do table lookup. */
1033 + if ( !c->x86_model_id[0] ) {
1035 + p = table_lookup_model(c);
1037 + strcpy(c->x86_model_id, p);
1039 + /* Last resort... */
1040 + sprintf(c->x86_model_id, "%02x/%02x",
1041 + c->x86, c->x86_model);
1044 + /* Now the feature flags better reflect actual CPU features! */
1046 + printk(KERN_DEBUG "CPU: After all inits, caps:");
1047 + for (i = 0; i < NCAPINTS; i++)
1048 + printk(" %08lx", c->x86_capability[i]);
1052 + * On SMP, boot_cpu_data holds the common feature set between
1053 + * all CPUs; so make sure that we indicate which features are
1054 + * common between the CPUs. The first time this routine gets
1055 + * executed, c == &boot_cpu_data.
1057 + if ( c != &boot_cpu_data ) {
1058 + /* AND the already accumulated flags with these */
1059 + for ( i = 0 ; i < NCAPINTS ; i++ )
1060 + boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1063 + /* Init Machine Check Exception if available. */
1066 + if (c == &boot_cpu_data)
1070 + if (c == &boot_cpu_data)
1076 +#ifdef CONFIG_X86_HT
1077 +void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1079 + u32 eax, ebx, ecx, edx;
1080 + int index_msb, core_bits;
1082 + cpuid(1, &eax, &ebx, &ecx, &edx);
1084 + if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
1087 + smp_num_siblings = (ebx & 0xff0000) >> 16;
1089 + if (smp_num_siblings == 1) {
1090 + printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
1091 + } else if (smp_num_siblings > 1 ) {
1093 + if (smp_num_siblings > NR_CPUS) {
1094 + printk(KERN_WARNING "CPU: Unsupported number of the "
1095 + "siblings %d", smp_num_siblings);
1096 + smp_num_siblings = 1;
1100 + index_msb = get_count_order(smp_num_siblings);
1101 + c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
1103 + printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
1106 + smp_num_siblings = smp_num_siblings / c->x86_max_cores;
1108 + index_msb = get_count_order(smp_num_siblings) ;
1110 + core_bits = get_count_order(c->x86_max_cores);
1112 + c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
1113 + ((1 << core_bits) - 1);
1115 + if (c->x86_max_cores > 1)
1116 + printk(KERN_INFO "CPU: Processor Core ID: %d\n",
1122 +void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1124 + char *vendor = NULL;
1126 + if (c->x86_vendor < X86_VENDOR_NUM)
1127 + vendor = this_cpu->c_vendor;
1128 + else if (c->cpuid_level >= 0)
1129 + vendor = c->x86_vendor_id;
1131 + if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
1132 + printk("%s ", vendor);
1134 + if (!c->x86_model_id[0])
1135 + printk("%d86", c->x86);
1137 + printk("%s", c->x86_model_id);
1139 + if (c->x86_mask || c->cpuid_level >= 0)
1140 + printk(" stepping %02x\n", c->x86_mask);
1145 +cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
1147 +/* This is hacky. :)
1148 + * We're emulating future behavior.
1149 + * In the future, the cpu-specific init functions will be called implicitly
1150 + * via the magic of initcalls.
1151 + * They will insert themselves into the cpu_devs structure.
1152 + * Then, when cpu_init() is called, we can just iterate over that array.
1155 +extern int intel_cpu_init(void);
1156 +extern int cyrix_init_cpu(void);
1157 +extern int nsc_init_cpu(void);
1158 +extern int amd_init_cpu(void);
1159 +extern int centaur_init_cpu(void);
1160 +extern int transmeta_init_cpu(void);
1161 +extern int rise_init_cpu(void);
1162 +extern int nexgen_init_cpu(void);
1163 +extern int umc_init_cpu(void);
1165 +void __init early_cpu_init(void)
1171 + centaur_init_cpu();
1172 + transmeta_init_cpu();
1174 + nexgen_init_cpu();
1176 + early_cpu_detect();
1178 +#ifdef CONFIG_DEBUG_PAGEALLOC
1179 + /* pse is not compatible with on-the-fly unmapping,
1180 + * disable it even if the cpus claim to support it.
1182 + clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
1187 +static void __cpuinit cpu_gdt_init(const struct Xgt_desc_struct *gdt_descr)
1189 + unsigned long frames[16];
1193 + for (va = gdt_descr->address, f = 0;
1194 + va < gdt_descr->address + gdt_descr->size;
1195 + va += PAGE_SIZE, f++) {
1196 + frames[f] = virt_to_mfn(va);
1197 + make_lowmem_page_readonly(
1198 + (void *)va, XENFEAT_writable_descriptor_tables);
1200 + if (HYPERVISOR_set_gdt(frames, (gdt_descr->size + 1) / 8))
1205 + * cpu_init() initializes state that is per-CPU. Some data is already
1206 + * initialized (naturally) in the bootstrap process, such as the GDT
1207 + * and IDT. We reload them nevertheless, this function acts as a
1208 + * 'CPU state barrier', nothing should get across.
1210 +void __cpuinit cpu_init(void)
1212 + int cpu = smp_processor_id();
1213 +#ifndef CONFIG_X86_NO_TSS
1214 + struct tss_struct * t = &per_cpu(init_tss, cpu);
1216 + struct thread_struct *thread = ¤t->thread;
1217 + struct desc_struct *gdt;
1218 + struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
1220 + if (cpu_test_and_set(cpu, cpu_initialized)) {
1221 + printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1222 + for (;;) local_irq_enable();
1224 + printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1226 + if (cpu_has_vme || cpu_has_de)
1227 + clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1228 + if (tsc_disable && cpu_has_tsc) {
1229 + printk(KERN_NOTICE "Disabling TSC...\n");
1230 + /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
1231 + clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
1232 + set_in_cr4(X86_CR4_TSD);
1236 + /* The CPU hotplug case */
1237 + if (cpu_gdt_descr->address) {
1238 + gdt = (struct desc_struct *)cpu_gdt_descr->address;
1239 + memset(gdt, 0, PAGE_SIZE);
1243 + * This is a horrible hack to allocate the GDT. The problem
1244 + * is that cpu_init() is called really early for the boot CPU
1245 + * (and hence needs bootmem) but much later for the secondary
1246 + * CPUs, when bootmem will have gone away
1248 + if (NODE_DATA(0)->bdata->node_bootmem_map) {
1249 + gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
1250 + /* alloc_bootmem_pages panics on failure, so no check */
1251 + memset(gdt, 0, PAGE_SIZE);
1253 + gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
1254 + if (unlikely(!gdt)) {
1255 + printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
1257 + local_irq_enable();
1262 + * Initialize the per-CPU GDT with the boot GDT,
1263 + * and set up the GDT descriptor:
1265 + memcpy(gdt, cpu_gdt_table, GDT_SIZE);
1267 + /* Set up GDT entry for 16bit stack */
1268 + *(__u64 *)(&gdt[GDT_ENTRY_ESPFIX_SS]) |=
1269 + ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) |
1270 + ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) |
1271 + (CPU_16BIT_STACK_SIZE - 1);
1273 + cpu_gdt_descr->size = GDT_SIZE - 1;
1274 + cpu_gdt_descr->address = (unsigned long)gdt;
1276 + if (cpu == 0 && cpu_gdt_descr->address == 0) {
1277 + gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
1278 + /* alloc_bootmem_pages panics on failure, so no check */
1279 + memset(gdt, 0, PAGE_SIZE);
1281 + memcpy(gdt, cpu_gdt_table, GDT_SIZE);
1283 + cpu_gdt_descr->size = GDT_SIZE;
1284 + cpu_gdt_descr->address = (unsigned long)gdt;
1288 + cpu_gdt_init(cpu_gdt_descr);
1291 + * Set up and load the per-CPU TSS and LDT
1293 + atomic_inc(&init_mm.mm_count);
1294 + current->active_mm = &init_mm;
1297 + enter_lazy_tlb(&init_mm, current);
1299 + load_esp0(t, thread);
1301 + load_LDT(&init_mm.context);
1303 +#ifdef CONFIG_DOUBLEFAULT
1304 + /* Set up doublefault TSS pointer in the GDT */
1305 + __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1308 + /* Clear %fs and %gs. */
1309 + asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
1311 + /* Clear all 6 debug registers: */
1312 + set_debugreg(0, 0);
1313 + set_debugreg(0, 1);
1314 + set_debugreg(0, 2);
1315 + set_debugreg(0, 3);
1316 + set_debugreg(0, 6);
1317 + set_debugreg(0, 7);
1320 + * Force FPU initialization:
1322 + current_thread_info()->status = 0;
1323 + clear_used_math();
1324 + mxcsr_feature_mask_init();
1327 +#ifdef CONFIG_HOTPLUG_CPU
1328 +void __cpuinit cpu_uninit(void)
1330 + int cpu = raw_smp_processor_id();
1331 + cpu_clear(cpu, cpu_initialized);
1333 + /* lazy TLB state */
1334 + per_cpu(cpu_tlbstate, cpu).state = 0;
1335 + per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
1338 Index: head-2008-11-25/arch/x86/kernel/cpu/mtrr/main-xen.c
1339 ===================================================================
1340 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1341 +++ head-2008-11-25/arch/x86/kernel/cpu/mtrr/main-xen.c 2008-01-28 12:24:18.000000000 +0100
1343 +#include <linux/init.h>
1344 +#include <linux/proc_fs.h>
1345 +#include <linux/ctype.h>
1346 +#include <linux/module.h>
1347 +#include <linux/seq_file.h>
1348 +#include <asm/uaccess.h>
1349 +#include <linux/mutex.h>
1351 +#include <asm/mtrr.h>
1354 +static DEFINE_MUTEX(mtrr_mutex);
1356 +void generic_get_mtrr(unsigned int reg, unsigned long *base,
1357 + unsigned int *size, mtrr_type * type)
1359 + struct xen_platform_op op;
1361 + op.cmd = XENPF_read_memtype;
1362 + op.u.read_memtype.reg = reg;
1363 + if (unlikely(HYPERVISOR_platform_op(&op)))
1364 + memset(&op.u.read_memtype, 0, sizeof(op.u.read_memtype));
1366 + *size = op.u.read_memtype.nr_mfns;
1367 + *base = op.u.read_memtype.mfn;
1368 + *type = op.u.read_memtype.type;
1371 +struct mtrr_ops generic_mtrr_ops = {
1372 + .use_intel_if = 1,
1373 + .get = generic_get_mtrr,
1376 +struct mtrr_ops *mtrr_if = &generic_mtrr_ops;
1377 +unsigned int num_var_ranges;
1378 +unsigned int *usage_table;
1380 +static void __init set_num_var_ranges(void)
1382 + struct xen_platform_op op;
1384 + for (num_var_ranges = 0; ; num_var_ranges++) {
1385 + op.cmd = XENPF_read_memtype;
1386 + op.u.read_memtype.reg = num_var_ranges;
1387 + if (HYPERVISOR_platform_op(&op) != 0)
1392 +static void __init init_table(void)
1396 + max = num_var_ranges;
1397 + if ((usage_table = kmalloc(max * sizeof *usage_table, GFP_KERNEL))
1399 + printk(KERN_ERR "mtrr: could not allocate\n");
1402 + for (i = 0; i < max; i++)
1403 + usage_table[i] = 0;
1406 +int mtrr_add_page(unsigned long base, unsigned long size,
1407 + unsigned int type, char increment)
1410 + struct xen_platform_op op;
1412 + mutex_lock(&mtrr_mutex);
1414 + op.cmd = XENPF_add_memtype;
1415 + op.u.add_memtype.mfn = base;
1416 + op.u.add_memtype.nr_mfns = size;
1417 + op.u.add_memtype.type = type;
1418 + error = HYPERVISOR_platform_op(&op);
1420 + mutex_unlock(&mtrr_mutex);
1421 + BUG_ON(error > 0);
1426 + ++usage_table[op.u.add_memtype.reg];
1428 + mutex_unlock(&mtrr_mutex);
1430 + return op.u.add_memtype.reg;
1433 +static int mtrr_check(unsigned long base, unsigned long size)
1435 + if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
1436 + printk(KERN_WARNING
1437 + "mtrr: size and base must be multiples of 4 kiB\n");
1439 + "mtrr: size: 0x%lx base: 0x%lx\n", size, base);
1447 +mtrr_add(unsigned long base, unsigned long size, unsigned int type,
1450 + if (mtrr_check(base, size))
1452 + return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
1456 +int mtrr_del_page(int reg, unsigned long base, unsigned long size)
1460 + unsigned long lbase;
1461 + unsigned int lsize;
1462 + int error = -EINVAL;
1463 + struct xen_platform_op op;
1465 + mutex_lock(&mtrr_mutex);
1468 + /* Search for existing MTRR */
1469 + for (i = 0; i < num_var_ranges; ++i) {
1470 + mtrr_if->get(i, &lbase, &lsize, <ype);
1471 + if (lbase == base && lsize == size) {
1477 + printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base,
1482 + if (usage_table[reg] < 1) {
1483 + printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg);
1486 + if (--usage_table[reg] < 1) {
1487 + op.cmd = XENPF_del_memtype;
1488 + op.u.del_memtype.handle = 0;
1489 + op.u.del_memtype.reg = reg;
1490 + error = HYPERVISOR_platform_op(&op);
1492 + BUG_ON(error > 0);
1498 + mutex_unlock(&mtrr_mutex);
1503 +mtrr_del(int reg, unsigned long base, unsigned long size)
1505 + if (mtrr_check(base, size))
1507 + return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
1510 +EXPORT_SYMBOL(mtrr_add);
1511 +EXPORT_SYMBOL(mtrr_del);
1513 +void __init mtrr_bp_init(void)
1517 +void mtrr_ap_init(void)
1521 +static int __init mtrr_init(void)
1523 + struct cpuinfo_x86 *c = &boot_cpu_data;
1525 + if (!is_initial_xendomain())
1528 + if ((!cpu_has(c, X86_FEATURE_MTRR)) &&
1529 + (!cpu_has(c, X86_FEATURE_K6_MTRR)) &&
1530 + (!cpu_has(c, X86_FEATURE_CYRIX_ARR)) &&
1531 + (!cpu_has(c, X86_FEATURE_CENTAUR_MCR)))
1534 + set_num_var_ranges();
1540 +subsys_initcall(mtrr_init);
1541 Index: head-2008-11-25/arch/x86/kernel/entry_32-xen.S
1542 ===================================================================
1543 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1544 +++ head-2008-11-25/arch/x86/kernel/entry_32-xen.S 2007-12-10 08:47:31.000000000 +0100
1547 + * linux/arch/i386/entry.S
1549 + * Copyright (C) 1991, 1992 Linus Torvalds
1553 + * entry.S contains the system-call and fault low-level handling routines.
1554 + * This also contains the timer-interrupt handler, as well as all interrupts
1555 + * and faults that can result in a task-switch.
1557 + * NOTE: This code handles signal-recognition, which happens every time
1558 + * after a timer-interrupt and after each system call.
1560 + * I changed all the .align's to 4 (16 byte alignment), as that's faster
1563 + * Stack layout in 'ret_from_system_call':
1564 + * ptrace needs to have all regs on the stack.
1565 + * if the order here is changed, it needs to be
1566 + * updated in fork.c:copy_process, signal.c:do_signal,
1567 + * ptrace.c and ptrace.h
1578 + * 24(%esp) - orig_eax
1581 + * 30(%esp) - %eflags
1582 + * 34(%esp) - %oldesp
1583 + * 38(%esp) - %oldss
1585 + * "current" is in register %ebx during any slow entries.
1588 +#include <linux/linkage.h>
1589 +#include <asm/thread_info.h>
1590 +#include <asm/irqflags.h>
1591 +#include <asm/errno.h>
1592 +#include <asm/segment.h>
1593 +#include <asm/smp.h>
1594 +#include <asm/page.h>
1595 +#include <asm/desc.h>
1596 +#include <asm/dwarf2.h>
1597 +#include "irq_vectors.h"
1598 +#include <xen/interface/xen.h>
1600 +#define nr_syscalls ((syscall_table_size)/4)
1618 +CF_MASK = 0x00000001
1619 +TF_MASK = 0x00000100
1620 +IF_MASK = 0x00000200
1621 +DF_MASK = 0x00000400
1622 +NT_MASK = 0x00004000
1623 +VM_MASK = 0x00020000
1624 +/* Pseudo-eflags. */
1625 +NMI_MASK = 0x80000000
1628 +#define DISABLE_INTERRUPTS cli
1629 +#define ENABLE_INTERRUPTS sti
1631 +/* Offsets into shared_info_t. */
1632 +#define evtchn_upcall_pending /* 0 */
1633 +#define evtchn_upcall_mask 1
1635 +#define sizeof_vcpu_shift 6
1638 +#define GET_VCPU_INFO movl TI_cpu(%ebp),%esi ; \
1639 + shl $sizeof_vcpu_shift,%esi ; \
1640 + addl HYPERVISOR_shared_info,%esi
1642 +#define GET_VCPU_INFO movl HYPERVISOR_shared_info,%esi
1645 +#define __DISABLE_INTERRUPTS movb $1,evtchn_upcall_mask(%esi)
1646 +#define __ENABLE_INTERRUPTS movb $0,evtchn_upcall_mask(%esi)
1647 +#define DISABLE_INTERRUPTS GET_VCPU_INFO ; \
1648 + __DISABLE_INTERRUPTS
1649 +#define ENABLE_INTERRUPTS GET_VCPU_INFO ; \
1650 + __ENABLE_INTERRUPTS
1651 +#define __TEST_PENDING testb $0xFF,evtchn_upcall_pending(%esi)
1654 +#ifdef CONFIG_PREEMPT
1655 +#define preempt_stop cli; TRACE_IRQS_OFF
1657 +#define preempt_stop
1658 +#define resume_kernel restore_nocheck
1661 +.macro TRACE_IRQS_IRET
1662 +#ifdef CONFIG_TRACE_IRQFLAGS
1663 + testl $IF_MASK,EFLAGS(%esp) # interrupts off?
1671 +#define resume_userspace_sig check_userspace
1673 +#define resume_userspace_sig resume_userspace
1679 + CFI_ADJUST_CFA_OFFSET 4;\
1680 + /*CFI_REL_OFFSET es, 0;*/\
1682 + CFI_ADJUST_CFA_OFFSET 4;\
1683 + /*CFI_REL_OFFSET ds, 0;*/\
1685 + CFI_ADJUST_CFA_OFFSET 4;\
1686 + CFI_REL_OFFSET eax, 0;\
1688 + CFI_ADJUST_CFA_OFFSET 4;\
1689 + CFI_REL_OFFSET ebp, 0;\
1691 + CFI_ADJUST_CFA_OFFSET 4;\
1692 + CFI_REL_OFFSET edi, 0;\
1694 + CFI_ADJUST_CFA_OFFSET 4;\
1695 + CFI_REL_OFFSET esi, 0;\
1697 + CFI_ADJUST_CFA_OFFSET 4;\
1698 + CFI_REL_OFFSET edx, 0;\
1700 + CFI_ADJUST_CFA_OFFSET 4;\
1701 + CFI_REL_OFFSET ecx, 0;\
1703 + CFI_ADJUST_CFA_OFFSET 4;\
1704 + CFI_REL_OFFSET ebx, 0;\
1705 + movl $(__USER_DS), %edx; \
1709 +#define RESTORE_INT_REGS \
1711 + CFI_ADJUST_CFA_OFFSET -4;\
1714 + CFI_ADJUST_CFA_OFFSET -4;\
1717 + CFI_ADJUST_CFA_OFFSET -4;\
1720 + CFI_ADJUST_CFA_OFFSET -4;\
1723 + CFI_ADJUST_CFA_OFFSET -4;\
1726 + CFI_ADJUST_CFA_OFFSET -4;\
1729 + CFI_ADJUST_CFA_OFFSET -4;\
1732 +#define RESTORE_REGS \
1733 + RESTORE_INT_REGS; \
1735 + CFI_ADJUST_CFA_OFFSET -4;\
1736 + /*CFI_RESTORE ds;*/\
1738 + CFI_ADJUST_CFA_OFFSET -4;\
1739 + /*CFI_RESTORE es;*/\
1740 +.section .fixup,"ax"; \
1741 +3: movl $0,(%esp); \
1743 +4: movl $0,(%esp); \
1746 +.section __ex_table,"a";\
1752 +#define RING0_INT_FRAME \
1753 + CFI_STARTPROC simple;\
1754 + CFI_DEF_CFA esp, 3*4;\
1755 + /*CFI_OFFSET cs, -2*4;*/\
1756 + CFI_OFFSET eip, -3*4
1758 +#define RING0_EC_FRAME \
1759 + CFI_STARTPROC simple;\
1760 + CFI_DEF_CFA esp, 4*4;\
1761 + /*CFI_OFFSET cs, -2*4;*/\
1762 + CFI_OFFSET eip, -3*4
1764 +#define RING0_PTREGS_FRAME \
1765 + CFI_STARTPROC simple;\
1766 + CFI_DEF_CFA esp, OLDESP-EBX;\
1767 + /*CFI_OFFSET cs, CS-OLDESP;*/\
1768 + CFI_OFFSET eip, EIP-OLDESP;\
1769 + /*CFI_OFFSET es, ES-OLDESP;*/\
1770 + /*CFI_OFFSET ds, DS-OLDESP;*/\
1771 + CFI_OFFSET eax, EAX-OLDESP;\
1772 + CFI_OFFSET ebp, EBP-OLDESP;\
1773 + CFI_OFFSET edi, EDI-OLDESP;\
1774 + CFI_OFFSET esi, ESI-OLDESP;\
1775 + CFI_OFFSET edx, EDX-OLDESP;\
1776 + CFI_OFFSET ecx, ECX-OLDESP;\
1777 + CFI_OFFSET ebx, EBX-OLDESP
1779 +ENTRY(ret_from_fork)
1782 + CFI_ADJUST_CFA_OFFSET 4
1783 + call schedule_tail
1784 + GET_THREAD_INFO(%ebp)
1786 + CFI_ADJUST_CFA_OFFSET -4
1787 + pushl $0x0202 # Reset kernel eflags
1788 + CFI_ADJUST_CFA_OFFSET 4
1790 + CFI_ADJUST_CFA_OFFSET -4
1795 + * Return to user mode is not as complex as all this looks,
1796 + * but we want the default path for a system call return to
1797 + * go as quickly as possible which is why some of this is
1798 + * less clear than it otherwise should be.
1801 + # userspace resumption stub bypassing syscall exit tracing
1803 + RING0_PTREGS_FRAME
1804 +ret_from_exception:
1807 + GET_THREAD_INFO(%ebp)
1809 + movl EFLAGS(%esp), %eax # mix EFLAGS and CS
1810 + movb CS(%esp), %al
1811 + testl $(VM_MASK | 2), %eax
1813 +ENTRY(resume_userspace)
1814 + DISABLE_INTERRUPTS # make sure we don't miss an interrupt
1815 + # setting need_resched or sigpending
1816 + # between sampling and the iret
1817 + movl TI_flags(%ebp), %ecx
1818 + andl $_TIF_WORK_MASK, %ecx # is there any work to be done on
1819 + # int/exception return?
1823 +#ifdef CONFIG_PREEMPT
1824 +ENTRY(resume_kernel)
1826 + cmpl $0,TI_preempt_count(%ebp) # non-zero preempt_count ?
1827 + jnz restore_nocheck
1829 + movl TI_flags(%ebp), %ecx # need_resched set ?
1830 + testb $_TIF_NEED_RESCHED, %cl
1832 + testl $IF_MASK,EFLAGS(%esp) # interrupts off (exception path) ?
1834 + call preempt_schedule_irq
1839 +/* SYSENTER_RETURN points to after the "sysenter" instruction in
1840 + the vsyscall page. See vsyscall-sysentry.S, which defines the symbol. */
1842 + # sysenter call handler stub
1843 +ENTRY(sysenter_entry)
1844 + CFI_STARTPROC simple
1845 + CFI_DEF_CFA esp, 0
1846 + CFI_REGISTER esp, ebp
1847 + movl SYSENTER_stack_esp0(%esp),%esp
1850 + * No need to follow this irqs on/off section: the syscall
1851 + * disabled irqs and here we enable it straight after entry:
1854 + pushl $(__USER_DS)
1855 + CFI_ADJUST_CFA_OFFSET 4
1856 + /*CFI_REL_OFFSET ss, 0*/
1858 + CFI_ADJUST_CFA_OFFSET 4
1859 + CFI_REL_OFFSET esp, 0
1861 + CFI_ADJUST_CFA_OFFSET 4
1862 + pushl $(__USER_CS)
1863 + CFI_ADJUST_CFA_OFFSET 4
1864 + /*CFI_REL_OFFSET cs, 0*/
1866 + * Push current_thread_info()->sysenter_return to the stack.
1867 + * A tiny bit of offset fixup is necessary - 4*4 means the 4 words
1868 + * pushed above; +8 corresponds to copy_thread's esp0 setting.
1870 + pushl (TI_sysenter_return-THREAD_SIZE+8+4*4)(%esp)
1871 + CFI_ADJUST_CFA_OFFSET 4
1872 + CFI_REL_OFFSET eip, 0
1875 + * Load the potential sixth argument from user stack.
1876 + * Careful about security.
1878 + cmpl $__PAGE_OFFSET-3,%ebp
1880 +1: movl (%ebp),%ebp
1881 +.section __ex_table,"a"
1883 + .long 1b,syscall_fault
1887 + CFI_ADJUST_CFA_OFFSET 4
1889 + GET_THREAD_INFO(%ebp)
1891 + /* Note, _TIF_SECCOMP is bit number 8, and so it needs testw and not testb */
1892 + testw $(_TIF_SYSCALL_EMU|_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT),TI_flags(%ebp)
1893 + jnz syscall_trace_entry
1894 + cmpl $(nr_syscalls), %eax
1895 + jae syscall_badsys
1896 + call *sys_call_table(,%eax,4)
1897 + movl %eax,EAX(%esp)
1898 + DISABLE_INTERRUPTS
1900 + movl TI_flags(%ebp), %ecx
1901 + testw $_TIF_ALLWORK_MASK, %cx
1902 + jne syscall_exit_work
1903 +/* if something modifies registers it must also disable sysexit */
1904 + movl EIP(%esp), %edx
1905 + movl OLDESP(%esp), %ecx
1909 + __ENABLE_INTERRUPTS
1910 +sysexit_scrit: /**** START OF SYSEXIT CRITICAL REGION ****/
1912 + jnz 14f # process more events if necessary...
1913 + movl ESI(%esp), %esi
1915 +14: __DISABLE_INTERRUPTS
1917 +sysexit_ecrit: /**** END OF SYSEXIT CRITICAL REGION ****/
1919 + call evtchn_do_upcall
1926 +#endif /* !CONFIG_XEN */
1929 + # pv sysenter call handler stub
1930 +ENTRY(sysenter_entry_pv)
1932 + movl $__USER_DS,16(%esp)
1933 + movl %ebp,12(%esp)
1934 + movl $__USER_CS,4(%esp)
1936 + /* +5*4 is SS:ESP,EFLAGS,CS:EIP. +8 is esp0 setting. */
1937 + pushl (TI_sysenter_return-THREAD_SIZE+8+4*4)(%esp)
1939 + * Load the potential sixth argument from user stack.
1940 + * Careful about security.
1942 + cmpl $__PAGE_OFFSET-3,%ebp
1944 +1: movl (%ebp),%ebp
1945 +.section __ex_table,"a"
1947 + .long 1b,syscall_fault
1949 + /* fall through */
1951 +ENDPROC(sysenter_entry_pv)
1953 + # system call handler stub
1955 + RING0_INT_FRAME # can't unwind into user space anyway
1956 + pushl %eax # save orig_eax
1957 + CFI_ADJUST_CFA_OFFSET 4
1959 + GET_THREAD_INFO(%ebp)
1960 + testl $TF_MASK,EFLAGS(%esp)
1962 + orl $_TIF_SINGLESTEP,TI_flags(%ebp)
1964 + # system call tracing in operation / emulation
1965 + /* Note, _TIF_SECCOMP is bit number 8, and so it needs testw and not testb */
1966 + testw $(_TIF_SYSCALL_EMU|_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT),TI_flags(%ebp)
1967 + jnz syscall_trace_entry
1968 + cmpl $(nr_syscalls), %eax
1969 + jae syscall_badsys
1971 + call *sys_call_table(,%eax,4)
1972 + movl %eax,EAX(%esp) # store the return value
1974 + DISABLE_INTERRUPTS # make sure we don't miss an interrupt
1975 + # setting need_resched or sigpending
1976 + # between sampling and the iret
1978 + movl TI_flags(%ebp), %ecx
1979 + testw $_TIF_ALLWORK_MASK, %cx # current->work
1980 + jne syscall_exit_work
1984 + movl EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
1985 + # Warning: OLDSS(%esp) contains the wrong/random values if we
1986 + # are returning to the kernel.
1987 + # See comments in process.c:copy_thread() for details.
1988 + movb OLDSS(%esp), %ah
1989 + movb CS(%esp), %al
1990 + andl $(VM_MASK | (4 << 8) | 3), %eax
1991 + cmpl $((4 << 8) | 3), %eax
1992 + CFI_REMEMBER_STATE
1993 + je ldt_ss # returning to user-space with LDT SS
1997 + movl EFLAGS(%esp), %eax
1998 + testl $(VM_MASK|NMI_MASK), %eax
1999 + CFI_REMEMBER_STATE
2000 + jnz hypervisor_iret
2001 + shr $9, %eax # EAX[0] == IRET_EFLAGS.IF
2003 + andb evtchn_upcall_mask(%esi),%al
2004 + andb $1,%al # EAX[0] == IRET_EFLAGS.IF & event_mask
2005 + CFI_REMEMBER_STATE
2006 + jnz restore_all_enable_events # != 0 => enable event delivery
2009 +restore_nocheck_notrace:
2012 + CFI_ADJUST_CFA_OFFSET -4
2014 +.section .fixup,"ax"
2020 + pushl $0 # no error code
2021 + pushl $do_iret_error
2024 +.section __ex_table,"a"
2032 + larl OLDSS(%esp), %eax
2033 + jnz restore_nocheck
2034 + testl $0x00400000, %eax # returning to 32bit stack?
2035 + jnz restore_nocheck # allright, normal return
2036 + /* If returning to userspace with 16bit stack,
2037 + * try to fix the higher word of ESP, as the CPU
2038 + * won't restore it.
2039 + * This is an "official" bug of all the x86-compatible
2040 + * CPUs, which we can try to work around to make
2041 + * dosemu and wine happy. */
2042 + subl $8, %esp # reserve space for switch16 pointer
2043 + CFI_ADJUST_CFA_OFFSET 8
2047 + /* Set up the 16bit stack frame with switch32 pointer on top,
2048 + * and a switch16 pointer on top of the current frame. */
2049 + call setup_x86_bogus_stack
2050 + CFI_ADJUST_CFA_OFFSET -8 # frame has moved
2053 + lss 20+4(%esp), %esp # switch to 16bit stack
2055 +.section __ex_table,"a"
2061 +restore_all_enable_events:
2063 + __ENABLE_INTERRUPTS
2064 +scrit: /**** START OF CRITICAL REGION ****/
2066 + jnz 14f # process more events if necessary...
2069 + CFI_ADJUST_CFA_OFFSET -4
2071 +.section __ex_table,"a"
2075 +14: __DISABLE_INTERRUPTS
2078 +ecrit: /**** END OF CRITICAL REGION ****/
2082 + andl $~NMI_MASK, EFLAGS(%esp)
2085 + CFI_ADJUST_CFA_OFFSET -4
2086 + jmp hypercall_page + (__HYPERVISOR_iret * 32)
2090 + # perform work that needs to be done immediately before resumption
2092 + RING0_PTREGS_FRAME # can't unwind into user space anyway
2094 + testb $_TIF_NEED_RESCHED, %cl
2098 + DISABLE_INTERRUPTS # make sure we don't miss an interrupt
2099 + # setting need_resched or sigpending
2100 + # between sampling and the iret
2102 + movl TI_flags(%ebp), %ecx
2103 + andl $_TIF_WORK_MASK, %ecx # is there any work to be done other
2104 + # than syscall tracing?
2106 + testb $_TIF_NEED_RESCHED, %cl
2109 +work_notifysig: # deal with pending signals and
2110 + # notify-resume requests
2111 + testl $VM_MASK, EFLAGS(%esp)
2113 + jne work_notifysig_v86 # returning to kernel-space or
2116 + call do_notify_resume
2117 + jmp resume_userspace_sig
2120 +work_notifysig_v86:
2122 + pushl %ecx # save ti_flags for do_notify_resume
2123 + CFI_ADJUST_CFA_OFFSET 4
2124 + call save_v86_state # %eax contains pt_regs pointer
2126 + CFI_ADJUST_CFA_OFFSET -4
2129 + call do_notify_resume
2130 + jmp resume_userspace_sig
2133 + # perform syscall exit tracing
2135 +syscall_trace_entry:
2136 + movl $-ENOSYS,EAX(%esp)
2139 + call do_syscall_trace
2141 + jne resume_userspace # ret != 0 -> running under PTRACE_SYSEMU,
2142 + # so must skip actual syscall
2143 + movl ORIG_EAX(%esp), %eax
2144 + cmpl $(nr_syscalls), %eax
2148 + # perform syscall exit tracing
2151 + testb $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP), %cl
2154 + ENABLE_INTERRUPTS # could let do_syscall_trace() call
2155 + # schedule() instead
2158 + call do_syscall_trace
2159 + jmp resume_userspace
2162 + RING0_INT_FRAME # can't unwind into user space anyway
2164 + pushl %eax # save orig_eax
2165 + CFI_ADJUST_CFA_OFFSET 4
2167 + GET_THREAD_INFO(%ebp)
2168 + movl $-EFAULT,EAX(%esp)
2169 + jmp resume_userspace
2172 + movl $-ENOSYS,EAX(%esp)
2173 + jmp resume_userspace
2177 +#define FIXUP_ESPFIX_STACK \
2178 + movl %esp, %eax; \
2179 + /* switch to 32bit stack using the pointer on top of 16bit stack */ \
2180 + lss %ss:CPU_16BIT_STACK_SIZE-8, %esp; \
2181 + /* copy data from 16bit stack to 32bit stack */ \
2182 + call fixup_x86_bogus_stack; \
2183 + /* put ESP to the proper location */ \
2185 +#define UNWIND_ESPFIX_STACK \
2187 + CFI_ADJUST_CFA_OFFSET 4; \
2189 + /* see if on 16bit stack */ \
2190 + cmpw $__ESPFIX_SS, %ax; \
2193 + CFI_ADJUST_CFA_OFFSET -4; \
2194 +.section .fixup,"ax"; \
2195 +28: movl $__KERNEL_DS, %eax; \
2198 + /* switch to 32bit stack */ \
2199 + FIXUP_ESPFIX_STACK; \
2204 + * Build the entry stubs and pointer table with
2205 + * some assembler magic.
2212 +ENTRY(irq_entries_start)
2217 + CFI_ADJUST_CFA_OFFSET -4
2219 +1: pushl $~(vector)
2220 + CFI_ADJUST_CFA_OFFSET 4
2221 + jmp common_interrupt
2229 + * the CPU automatically disables interrupts when executing an IRQ vector,
2230 + * so IRQ-flags tracing has to follow that:
2241 +#define BUILD_INTERRUPT(name, nr) \
2243 + RING0_INT_FRAME; \
2245 + CFI_ADJUST_CFA_OFFSET 4; \
2249 + call smp_/**/name; \
2250 + jmp ret_from_intr; \
2253 +/* The include is where all of the SMP etc. interrupts come from */
2254 +#include "entry_arch.h"
2256 +#define UNWIND_ESPFIX_STACK
2259 +ENTRY(divide_error)
2261 + pushl $0 # no error code
2262 + CFI_ADJUST_CFA_OFFSET 4
2263 + pushl $do_divide_error
2264 + CFI_ADJUST_CFA_OFFSET 4
2268 + CFI_ADJUST_CFA_OFFSET 4
2269 + /*CFI_REL_OFFSET ds, 0*/
2271 + CFI_ADJUST_CFA_OFFSET 4
2272 + CFI_REL_OFFSET eax, 0
2275 + CFI_ADJUST_CFA_OFFSET 4
2276 + CFI_REL_OFFSET ebp, 0
2278 + CFI_ADJUST_CFA_OFFSET 4
2279 + CFI_REL_OFFSET edi, 0
2281 + CFI_ADJUST_CFA_OFFSET 4
2282 + CFI_REL_OFFSET esi, 0
2284 + CFI_ADJUST_CFA_OFFSET 4
2285 + CFI_REL_OFFSET edx, 0
2286 + decl %eax # eax = -1
2288 + CFI_ADJUST_CFA_OFFSET 4
2289 + CFI_REL_OFFSET ecx, 0
2291 + CFI_ADJUST_CFA_OFFSET 4
2292 + CFI_REL_OFFSET ebx, 0
2295 + CFI_ADJUST_CFA_OFFSET 4
2296 + /*CFI_REL_OFFSET es, 0*/
2297 + UNWIND_ESPFIX_STACK
2299 + CFI_ADJUST_CFA_OFFSET -4
2300 + /*CFI_REGISTER es, ecx*/
2301 + movl ES(%esp), %edi # get the function address
2302 + movl ORIG_EAX(%esp), %edx # get the error code
2303 + movl %eax, ORIG_EAX(%esp)
2304 + movl %ecx, ES(%esp)
2305 + /*CFI_REL_OFFSET es, ES*/
2306 + movl $(__USER_DS), %ecx
2309 + movl %esp,%eax # pt_regs pointer
2311 + jmp ret_from_exception
2315 +# A note on the "critical region" in our callback handler.
2316 +# We want to avoid stacking callback handlers due to events occurring
2317 +# during handling of the last event. To do this, we keep events disabled
2318 +# until we've done all processing. HOWEVER, we must enable events before
2319 +# popping the stack frame (can't be done atomically) and so it would still
2320 +# be possible to get enough handler activations to overflow the stack.
2321 +# Although unlikely, bugs of that kind are hard to track down, so we'd
2322 +# like to avoid the possibility.
2323 +# So, on entry to the handler we detect whether we interrupted an
2324 +# existing activation in its critical region -- if so, we pop the current
2325 +# activation and restart the handler using the previous one.
2327 +# The sysexit critical region is slightly different. sysexit
2328 +# atomically removes the entire stack frame. If we interrupt in the
2329 +# critical region we know that the entire frame is present and correct
2330 +# so we can simply throw away the new one.
2331 +ENTRY(hypervisor_callback)
2334 + CFI_ADJUST_CFA_OFFSET 4
2336 + movl EIP(%esp),%eax
2340 + jb critical_region_fixup
2341 + cmpl $sysexit_scrit,%eax
2343 + cmpl $sysexit_ecrit,%eax
2345 + addl $OLDESP,%esp # Remove eflags...ebx from stack frame.
2347 + CFI_ADJUST_CFA_OFFSET 4
2348 + call evtchn_do_upcall
2350 + CFI_ADJUST_CFA_OFFSET -4
2354 +# [How we do the fixup]. We want to merge the current stack frame with the
2355 +# just-interrupted frame. How we do this depends on where in the critical
2356 +# region the interrupted handler was executing, and so how many saved
2357 +# registers are in each frame. We do this quickly using the lookup table
2358 +# 'critical_fixup_table'. For each byte offset in the critical region, it
2359 +# provides the number of bytes which have already been popped from the
2360 +# interrupted stack frame.
2361 +critical_region_fixup:
2362 + movzbl critical_fixup_table-scrit(%eax),%ecx # %eax contains num bytes popped
2363 + cmpb $0xff,%cl # 0xff => vcpu_info critical region
2366 +15: leal (%esp,%ecx),%esi # %esi points at end of src region
2367 + leal OLDESP(%esp),%edi # %edi points at end of dst region
2368 + shrl $2,%ecx # convert words to bytes
2369 + je 17f # skip loop if nothing to copy
2370 +16: subl $4,%esi # pre-decrementing copy loop
2375 +17: movl %edi,%esp # final %edi is top of merged stack
2378 +.section .rodata,"a"
2379 +critical_fixup_table:
2380 + .byte 0xff,0xff,0xff # testb $0xff,(%esi) = __TEST_PENDING
2381 + .byte 0xff,0xff # jnz 14f
2382 + .byte 0x00 # pop %ebx
2383 + .byte 0x04 # pop %ecx
2384 + .byte 0x08 # pop %edx
2385 + .byte 0x0c # pop %esi
2386 + .byte 0x10 # pop %edi
2387 + .byte 0x14 # pop %ebp
2388 + .byte 0x18 # pop %eax
2389 + .byte 0x1c # pop %ds
2390 + .byte 0x20 # pop %es
2391 + .byte 0x24,0x24,0x24 # add $4,%esp
2393 + .byte 0xff,0xff,0xff,0xff # movb $1,1(%esi)
2394 + .byte 0x00,0x00 # jmp 11b
2397 +# Hypervisor uses this for application faults while it executes.
2398 +# We get here for two reasons:
2399 +# 1. Fault while reloading DS, ES, FS or GS
2400 +# 2. Fault while executing IRET
2401 +# Category 1 we fix up by reattempting the load, and zeroing the segment
2402 +# register if the load fails.
2403 +# Category 2 we fix up by jumping to do_iret_error. We cannot use the
2404 +# normal Linux return path in this case because if we use the IRET hypercall
2405 +# to pop the stack frame we end up in an infinite loop of failsafe callbacks.
2406 +# We distinguish between categories by maintaining a status value in EAX.
2407 +ENTRY(failsafe_callback)
2412 +3: mov 12(%esp),%fs
2413 +4: mov 16(%esp),%gs
2417 + addl $16,%esp # EAX != 0 => Category 2 (Bad IRET)
2419 +5: addl $16,%esp # EAX == 0 => Category 1 (Bad segment)
2423 + jmp ret_from_exception
2424 +.section .fixup,"ax"; \
2425 +6: xorl %eax,%eax; \
2426 + movl %eax,4(%esp); \
2428 +7: xorl %eax,%eax; \
2429 + movl %eax,8(%esp); \
2431 +8: xorl %eax,%eax; \
2432 + movl %eax,12(%esp); \
2434 +9: xorl %eax,%eax; \
2435 + movl %eax,16(%esp); \
2438 +.section __ex_table,"a"; \
2448 +ENTRY(coprocessor_error)
2451 + CFI_ADJUST_CFA_OFFSET 4
2452 + pushl $do_coprocessor_error
2453 + CFI_ADJUST_CFA_OFFSET 4
2457 +ENTRY(simd_coprocessor_error)
2460 + CFI_ADJUST_CFA_OFFSET 4
2461 + pushl $do_simd_coprocessor_error
2462 + CFI_ADJUST_CFA_OFFSET 4
2466 +ENTRY(device_not_available)
2468 + pushl $-1 # mark this as an int
2469 + CFI_ADJUST_CFA_OFFSET 4
2473 + testl $0x4, %eax # EM (math emulation bit)
2474 + je device_available_emulate
2475 + pushl $0 # temporary storage for ORIG_EIP
2476 + CFI_ADJUST_CFA_OFFSET 4
2479 + CFI_ADJUST_CFA_OFFSET -4
2480 + jmp ret_from_exception
2481 +device_available_emulate:
2484 + call math_state_restore
2485 + jmp ret_from_exception
2490 + * Debug traps and NMI can happen at the one SYSENTER instruction
2491 + * that sets up the real kernel stack. Check here, since we can't
2492 + * allow the wrong stack to be used.
2494 + * "SYSENTER_stack_esp0+12" is because the NMI/debug handler will have
2495 + * already pushed 3 words if it hits on the sysenter instruction:
2496 + * eflags, cs and eip.
2498 + * We just load the right stack, and push the three (known) values
2499 + * by hand onto the new stack - while updating the return eip past
2500 + * the instruction that would have done it for sysenter.
2502 +#define FIX_STACK(offset, ok, label) \
2503 + cmpw $__KERNEL_CS,4(%esp); \
2506 + movl SYSENTER_stack_esp0+offset(%esp),%esp; \
2508 + pushl $__KERNEL_CS; \
2509 + pushl $sysenter_past_esp
2510 +#endif /* CONFIG_XEN */
2512 +KPROBE_ENTRY(debug)
2515 + cmpl $sysenter_entry,(%esp)
2516 + jne debug_stack_correct
2517 + FIX_STACK(12, debug_stack_correct, debug_esp_fix_insn)
2518 +debug_stack_correct:
2519 +#endif /* !CONFIG_XEN */
2520 + pushl $-1 # mark this as an int
2521 + CFI_ADJUST_CFA_OFFSET 4
2523 + xorl %edx,%edx # error code 0
2524 + movl %esp,%eax # pt_regs pointer
2526 + jmp ret_from_exception
2531 + * NMI is doubly nasty. It can happen _while_ we're handling
2532 + * a debug fault, and the debug fault hasn't yet been able to
2533 + * clear up the stack. So we first check whether we got an
2534 + * NMI on the sysenter entry path, but after that we need to
2535 + * check whether we got an NMI on the debug path where the debug
2536 + * fault happened on the sysenter path.
2541 + CFI_ADJUST_CFA_OFFSET 4
2543 + cmpw $__ESPFIX_SS, %ax
2545 + CFI_ADJUST_CFA_OFFSET -4
2546 + je nmi_16bit_stack
2547 + cmpl $sysenter_entry,(%esp)
2548 + je nmi_stack_fixup
2550 + CFI_ADJUST_CFA_OFFSET 4
2552 + /* Do not access memory above the end of our stack page,
2553 + * it might not exist.
2555 + andl $(THREAD_SIZE-1),%eax
2556 + cmpl $(THREAD_SIZE-20),%eax
2558 + CFI_ADJUST_CFA_OFFSET -4
2559 + jae nmi_stack_correct
2560 + cmpl $sysenter_entry,12(%esp)
2561 + je nmi_debug_stack_check
2564 + CFI_ADJUST_CFA_OFFSET 4
2566 + xorl %edx,%edx # zero error code
2567 + movl %esp,%eax # pt_regs pointer
2569 + jmp restore_nocheck_notrace
2573 + FIX_STACK(12,nmi_stack_correct, 1)
2574 + jmp nmi_stack_correct
2575 +nmi_debug_stack_check:
2576 + cmpw $__KERNEL_CS,16(%esp)
2577 + jne nmi_stack_correct
2578 + cmpl $debug,(%esp)
2579 + jb nmi_stack_correct
2580 + cmpl $debug_esp_fix_insn,(%esp)
2581 + ja nmi_stack_correct
2582 + FIX_STACK(24,nmi_stack_correct, 1)
2583 + jmp nmi_stack_correct
2587 + /* create the pointer to lss back */
2589 + CFI_ADJUST_CFA_OFFSET 4
2591 + CFI_ADJUST_CFA_OFFSET 4
2594 + /* copy the iret frame of 12 bytes */
2597 + CFI_ADJUST_CFA_OFFSET 4
2600 + CFI_ADJUST_CFA_OFFSET 4
2602 + FIXUP_ESPFIX_STACK # %eax == %esp
2603 + CFI_ADJUST_CFA_OFFSET -20 # the frame has now moved
2604 + xorl %edx,%edx # zero error code
2607 + lss 12+4(%esp), %esp # back to 16bit stack
2610 +.section __ex_table,"a"
2618 + CFI_ADJUST_CFA_OFFSET 4
2620 + xorl %edx,%edx # zero error code
2621 + movl %esp,%eax # pt_regs pointer
2623 + orl $NMI_MASK, EFLAGS(%esp)
2630 + pushl $-1 # mark this as an int
2631 + CFI_ADJUST_CFA_OFFSET 4
2633 + xorl %edx,%edx # zero error code
2634 + movl %esp,%eax # pt_regs pointer
2636 + jmp ret_from_exception
2643 + CFI_ADJUST_CFA_OFFSET 4
2644 + pushl $do_overflow
2645 + CFI_ADJUST_CFA_OFFSET 4
2652 + CFI_ADJUST_CFA_OFFSET 4
2654 + CFI_ADJUST_CFA_OFFSET 4
2661 + CFI_ADJUST_CFA_OFFSET 4
2662 + pushl $do_invalid_op
2663 + CFI_ADJUST_CFA_OFFSET 4
2667 +ENTRY(coprocessor_segment_overrun)
2670 + CFI_ADJUST_CFA_OFFSET 4
2671 + pushl $do_coprocessor_segment_overrun
2672 + CFI_ADJUST_CFA_OFFSET 4
2678 + pushl $do_invalid_TSS
2679 + CFI_ADJUST_CFA_OFFSET 4
2683 +ENTRY(segment_not_present)
2685 + pushl $do_segment_not_present
2686 + CFI_ADJUST_CFA_OFFSET 4
2690 +ENTRY(stack_segment)
2692 + pushl $do_stack_segment
2693 + CFI_ADJUST_CFA_OFFSET 4
2697 +KPROBE_ENTRY(general_protection)
2699 + pushl $do_general_protection
2700 + CFI_ADJUST_CFA_OFFSET 4
2705 +ENTRY(alignment_check)
2707 + pushl $do_alignment_check
2708 + CFI_ADJUST_CFA_OFFSET 4
2712 +KPROBE_ENTRY(page_fault)
2714 + pushl $do_page_fault
2715 + CFI_ADJUST_CFA_OFFSET 4
2720 +#ifdef CONFIG_X86_MCE
2721 +ENTRY(machine_check)
2724 + CFI_ADJUST_CFA_OFFSET 4
2725 + pushl machine_check_vector
2726 + CFI_ADJUST_CFA_OFFSET 4
2732 +ENTRY(spurious_interrupt_bug)
2735 + CFI_ADJUST_CFA_OFFSET 4
2736 + pushl $do_spurious_interrupt_bug
2737 + CFI_ADJUST_CFA_OFFSET 4
2740 +#endif /* !CONFIG_XEN */
2742 +#ifdef CONFIG_STACK_UNWIND
2743 +ENTRY(arch_unwind_init_running)
2745 + movl 4(%esp), %edx
2747 + leal 4(%esp), %eax
2748 + movl %ebx, EBX(%edx)
2750 + movl %ebx, ECX(%edx)
2751 + movl %ebx, EDX(%edx)
2752 + movl %esi, ESI(%edx)
2753 + movl %edi, EDI(%edx)
2754 + movl %ebp, EBP(%edx)
2755 + movl %ebx, EAX(%edx)
2756 + movl $__USER_DS, DS(%edx)
2757 + movl $__USER_DS, ES(%edx)
2758 + movl %ebx, ORIG_EAX(%edx)
2759 + movl %ecx, EIP(%edx)
2760 + movl 12(%esp), %ecx
2761 + movl $__KERNEL_CS, CS(%edx)
2762 + movl %ebx, EFLAGS(%edx)
2763 + movl %eax, OLDESP(%edx)
2764 + movl 8(%esp), %eax
2765 + movl %ecx, 8(%esp)
2766 + movl EBX(%edx), %ebx
2767 + movl $__KERNEL_DS, OLDSS(%edx)
2770 +ENDPROC(arch_unwind_init_running)
2773 +ENTRY(fixup_4gb_segment)
2775 + pushl $do_fixup_4gb_segment
2776 + CFI_ADJUST_CFA_OFFSET 4
2780 +.section .rodata,"a"
2781 +#include "syscall_table.S"
2783 +syscall_table_size=(.-sys_call_table)
2784 Index: head-2008-11-25/arch/x86/kernel/fixup.c
2785 ===================================================================
2786 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2787 +++ head-2008-11-25/arch/x86/kernel/fixup.c 2008-01-28 12:24:18.000000000 +0100
2789 +/******************************************************************************
2792 + * Binary-rewriting of certain IA32 instructions, on notification by Xen.
2793 + * Used to avoid repeated slow emulation of common instructions used by the
2794 + * user-space TLS (Thread-Local Storage) libraries.
2797 + * Issues with the binary rewriting have caused it to be removed. Instead
2798 + * we rely on Xen's emulator to boot the kernel, and then print a banner
2799 + * message recommending that the user disables /lib/tls.
2801 + * Copyright (c) 2004, K A Fraser
2803 + * This program is free software; you can redistribute it and/or modify
2804 + * it under the terms of the GNU General Public License as published by
2805 + * the Free Software Foundation; either version 2 of the License, or
2806 + * (at your option) any later version.
2808 + * This program is distributed in the hope that it will be useful,
2809 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2810 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2811 + * GNU General Public License for more details.
2813 + * You should have received a copy of the GNU General Public License
2814 + * along with this program; if not, write to the Free Software
2815 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2818 +#include <linux/init.h>
2819 +#include <linux/sched.h>
2820 +#include <linux/slab.h>
2821 +#include <linux/kernel.h>
2822 +#include <linux/delay.h>
2823 +#include <linux/version.h>
2825 +#define DP(_f, _args...) printk(KERN_ALERT " " _f "\n" , ## _args )
2827 +fastcall void do_fixup_4gb_segment(struct pt_regs *regs, long error_code)
2829 + static unsigned long printed = 0;
2833 + /* Ignore statically-linked init. */
2834 + if (current->tgid == 1)
2837 + VOID(HYPERVISOR_vm_assist(VMASST_CMD_disable,
2838 + VMASST_TYPE_4gb_segments_notify));
2840 + if (test_and_set_bit(0, &printed))
2843 + sprintf(info, "%s (pid=%d)", current->comm, current->tgid);
2846 + DP("***************************************************************");
2847 + DP("***************************************************************");
2848 + DP("** WARNING: Currently emulating unsupported memory accesses **");
2849 + DP("** in /lib/tls glibc libraries. The emulation is **");
2850 + DP("** slow. To ensure full performance you should **");
2851 + DP("** install a 'xen-friendly' (nosegneg) version of **");
2852 + DP("** the library, or disable tls support by executing **");
2853 + DP("** the following as root: **");
2854 + DP("** mv /lib/tls /lib/tls.disabled **");
2855 + DP("** Offending process: %-38.38s **", info);
2856 + DP("***************************************************************");
2857 + DP("***************************************************************");
2860 + for (i = 5; i > 0; i--) {
2861 + touch_softlockup_watchdog();
2862 + printk("Pausing... %d", i);
2864 + printk("\b\b\b\b\b\b\b\b\b\b\b\b");
2867 + printk("Continuing...\n\n");
2870 +static int __init fixup_init(void)
2872 + WARN_ON(HYPERVISOR_vm_assist(VMASST_CMD_enable,
2873 + VMASST_TYPE_4gb_segments_notify));
2876 +__initcall(fixup_init);
2877 Index: head-2008-11-25/arch/x86/kernel/head_32-xen.S
2878 ===================================================================
2879 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2880 +++ head-2008-11-25/arch/x86/kernel/head_32-xen.S 2007-06-12 13:12:48.000000000 +0200
2885 +#include <linux/elfnote.h>
2886 +#include <linux/threads.h>
2887 +#include <linux/linkage.h>
2888 +#include <asm/segment.h>
2889 +#include <asm/page.h>
2890 +#include <asm/cache.h>
2891 +#include <asm/thread_info.h>
2892 +#include <asm/asm-offsets.h>
2893 +#include <asm/dwarf2.h>
2894 +#include <xen/interface/xen.h>
2895 +#include <xen/interface/elfnote.h>
2898 + * References to members of the new_cpu_data structure.
2901 +#define X86 new_cpu_data+CPUINFO_x86
2902 +#define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
2903 +#define X86_MODEL new_cpu_data+CPUINFO_x86_model
2904 +#define X86_MASK new_cpu_data+CPUINFO_x86_mask
2905 +#define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
2906 +#define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
2907 +#define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
2908 +#define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id
2910 +#define VIRT_ENTRY_OFFSET 0x0
2911 +.org VIRT_ENTRY_OFFSET
2913 + movl %esi,xen_start_info
2916 + /* Set up the stack pointer */
2917 + movl $(init_thread_union+THREAD_SIZE),%esp
2919 + /* get vendor info */
2920 + xorl %eax,%eax # call CPUID with 0 -> return vendor ID
2922 + movl %eax,X86_CPUID # save CPUID level
2923 + movl %ebx,X86_VENDOR_ID # lo 4 chars
2924 + movl %edx,X86_VENDOR_ID+4 # next 4 chars
2925 + movl %ecx,X86_VENDOR_ID+8 # last 4 chars
2927 + movl $1,%eax # Use the CPUID instruction to get CPU type
2929 + movb %al,%cl # save reg for future use
2930 + andb $0x0f,%ah # mask processor family
2932 + andb $0xf0,%al # mask model
2934 + movb %al,X86_MODEL
2935 + andb $0x0f,%cl # mask mask revision
2937 + movl %edx,X86_CAPABILITY
2939 + movb $1,X86_HARD_MATH
2941 + xorl %eax,%eax # Clear FS/GS and LDT
2944 + cld # gcc2 wants the direction flag cleared at all times
2946 + pushl %eax # fake return address
2949 +#define HYPERCALL_PAGE_OFFSET 0x1000
2950 +.org HYPERCALL_PAGE_OFFSET
2951 +ENTRY(hypercall_page)
2957 + * Real beginning of normal "text" segment
2965 +.section ".bss.page_aligned","w"
2966 +ENTRY(empty_zero_page)
2970 + * This starts the data section.
2975 + * The Global Descriptor Table contains 28 quadwords, per-CPU.
2977 + .align L1_CACHE_BYTES
2978 +ENTRY(cpu_gdt_table)
2979 + .quad 0x0000000000000000 /* NULL descriptor */
2980 + .quad 0x0000000000000000 /* 0x0b reserved */
2981 + .quad 0x0000000000000000 /* 0x13 reserved */
2982 + .quad 0x0000000000000000 /* 0x1b reserved */
2983 + .quad 0x0000000000000000 /* 0x20 unused */
2984 + .quad 0x0000000000000000 /* 0x28 unused */
2985 + .quad 0x0000000000000000 /* 0x33 TLS entry 1 */
2986 + .quad 0x0000000000000000 /* 0x3b TLS entry 2 */
2987 + .quad 0x0000000000000000 /* 0x43 TLS entry 3 */
2988 + .quad 0x0000000000000000 /* 0x4b reserved */
2989 + .quad 0x0000000000000000 /* 0x53 reserved */
2990 + .quad 0x0000000000000000 /* 0x5b reserved */
2992 + .quad 0x00cf9a000000ffff /* 0x60 kernel 4GB code at 0x00000000 */
2993 + .quad 0x00cf92000000ffff /* 0x68 kernel 4GB data at 0x00000000 */
2994 + .quad 0x00cffa000000ffff /* 0x73 user 4GB code at 0x00000000 */
2995 + .quad 0x00cff2000000ffff /* 0x7b user 4GB data at 0x00000000 */
2997 + .quad 0x0000000000000000 /* 0x80 TSS descriptor */
2998 + .quad 0x0000000000000000 /* 0x88 LDT descriptor */
3001 + * Segments used for calling PnP BIOS have byte granularity.
3002 + * They code segments and data segments have fixed 64k limits,
3003 + * the transfer segment sizes are set at run time.
3005 + .quad 0x0000000000000000 /* 0x90 32-bit code */
3006 + .quad 0x0000000000000000 /* 0x98 16-bit code */
3007 + .quad 0x0000000000000000 /* 0xa0 16-bit data */
3008 + .quad 0x0000000000000000 /* 0xa8 16-bit data */
3009 + .quad 0x0000000000000000 /* 0xb0 16-bit data */
3012 + * The APM segments have byte granularity and their bases
3013 + * are set at run time. All have 64k limits.
3015 + .quad 0x0000000000000000 /* 0xb8 APM CS code */
3016 + .quad 0x0000000000000000 /* 0xc0 APM CS 16 code (16 bit) */
3017 + .quad 0x0000000000000000 /* 0xc8 APM DS data */
3019 + .quad 0x0000000000000000 /* 0xd0 - ESPFIX 16-bit SS */
3020 + .quad 0x0000000000000000 /* 0xd8 - unused */
3021 + .quad 0x0000000000000000 /* 0xe0 - unused */
3022 + .quad 0x0000000000000000 /* 0xe8 - unused */
3023 + .quad 0x0000000000000000 /* 0xf0 - unused */
3024 + .quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */
3026 +#if CONFIG_XEN_COMPAT <= 0x030002
3028 + * __xen_guest information
3031 + .if (\value) < 0 || (\value) >= 0x10
3032 + utoa (((\value)>>4)&0x0fffffff)
3034 + .if ((\value) & 0xf) < 10
3035 + .byte '0' + ((\value) & 0xf)
3037 + .byte 'A' + ((\value) & 0xf) - 10
3041 +.section __xen_guest
3042 + .ascii "GUEST_OS=linux,GUEST_VER=2.6"
3043 + .ascii ",XEN_VER=xen-3.0"
3044 + .ascii ",VIRT_BASE=0x"
3045 + utoa __PAGE_OFFSET
3046 + .ascii ",ELF_PADDR_OFFSET=0x"
3047 + utoa __PAGE_OFFSET
3048 + .ascii ",VIRT_ENTRY=0x"
3049 + utoa (__PAGE_OFFSET + __PHYSICAL_START + VIRT_ENTRY_OFFSET)
3050 + .ascii ",HYPERCALL_PAGE=0x"
3051 + utoa ((__PHYSICAL_START+HYPERCALL_PAGE_OFFSET)>>PAGE_SHIFT)
3052 + .ascii ",FEATURES=writable_page_tables"
3053 + .ascii "|writable_descriptor_tables"
3054 + .ascii "|auto_translated_physmap"
3055 + .ascii "|pae_pgdir_above_4gb"
3056 + .ascii "|supervisor_mode_kernel"
3057 +#ifdef CONFIG_X86_PAE
3058 + .ascii ",PAE=yes[extended-cr3]"
3062 + .ascii ",LOADER=generic"
3064 +#endif /* CONFIG_XEN_COMPAT <= 0x030002 */
3067 + ELFNOTE(Xen, XEN_ELFNOTE_GUEST_OS, .asciz, "linux")
3068 + ELFNOTE(Xen, XEN_ELFNOTE_GUEST_VERSION, .asciz, "2.6")
3069 + ELFNOTE(Xen, XEN_ELFNOTE_XEN_VERSION, .asciz, "xen-3.0")
3070 + ELFNOTE(Xen, XEN_ELFNOTE_VIRT_BASE, .long, __PAGE_OFFSET)
3071 +#if CONFIG_XEN_COMPAT <= 0x030002
3072 + ELFNOTE(Xen, XEN_ELFNOTE_PADDR_OFFSET, .long, __PAGE_OFFSET)
3074 + ELFNOTE(Xen, XEN_ELFNOTE_PADDR_OFFSET, .long, 0)
3076 + ELFNOTE(Xen, XEN_ELFNOTE_ENTRY, .long, startup_32)
3077 + ELFNOTE(Xen, XEN_ELFNOTE_HYPERCALL_PAGE, .long, hypercall_page)
3078 + ELFNOTE(Xen, XEN_ELFNOTE_HV_START_LOW, .long, HYPERVISOR_VIRT_START)
3079 + ELFNOTE(Xen, XEN_ELFNOTE_FEATURES, .asciz, "writable_page_tables|writable_descriptor_tables|auto_translated_physmap|pae_pgdir_above_4gb|supervisor_mode_kernel")
3080 +#ifdef CONFIG_X86_PAE
3081 + ELFNOTE(Xen, XEN_ELFNOTE_PAE_MODE, .asciz, "yes")
3082 + ELFNOTE(Xen, XEN_ELFNOTE_L1_MFN_VALID, .quad, _PAGE_PRESENT,_PAGE_PRESENT)
3084 + ELFNOTE(Xen, XEN_ELFNOTE_PAE_MODE, .asciz, "no")
3085 + ELFNOTE(Xen, XEN_ELFNOTE_L1_MFN_VALID, .long, _PAGE_PRESENT,_PAGE_PRESENT)
3087 + ELFNOTE(Xen, XEN_ELFNOTE_LOADER, .asciz, "generic")
3088 + ELFNOTE(Xen, XEN_ELFNOTE_SUSPEND_CANCEL, .long, 1)
3089 Index: head-2008-11-25/arch/x86/kernel/init_task-xen.c
3090 ===================================================================
3091 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3092 +++ head-2008-11-25/arch/x86/kernel/init_task-xen.c 2007-06-12 13:12:48.000000000 +0200
3094 +#include <linux/mm.h>
3095 +#include <linux/module.h>
3096 +#include <linux/sched.h>
3097 +#include <linux/init.h>
3098 +#include <linux/init_task.h>
3099 +#include <linux/fs.h>
3100 +#include <linux/mqueue.h>
3102 +#include <asm/uaccess.h>
3103 +#include <asm/pgtable.h>
3104 +#include <asm/desc.h>
3106 +static struct fs_struct init_fs = INIT_FS;
3107 +static struct files_struct init_files = INIT_FILES;
3108 +static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
3109 +static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
3111 +#define swapper_pg_dir ((pgd_t *)NULL)
3112 +struct mm_struct init_mm = INIT_MM(init_mm);
3113 +#undef swapper_pg_dir
3115 +EXPORT_SYMBOL(init_mm);
3118 + * Initial thread structure.
3120 + * We need to make sure that this is THREAD_SIZE aligned due to the
3121 + * way process stacks are handled. This is done by having a special
3122 + * "init_task" linker map entry..
3124 +union thread_union init_thread_union
3125 + __attribute__((__section__(".data.init_task"))) =
3126 + { INIT_THREAD_INFO(init_task) };
3129 + * Initial task structure.
3131 + * All other task structs will be allocated on slabs in fork.c
3133 +struct task_struct init_task = INIT_TASK(init_task);
3135 +EXPORT_SYMBOL(init_task);
3137 +#ifndef CONFIG_X86_NO_TSS
3139 + * per-CPU TSS segments. Threads are completely 'soft' on Linux,
3140 + * no more per-task TSS's.
3142 +DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS;
3145 Index: head-2008-11-25/arch/x86/kernel/io_apic_32-xen.c
3146 ===================================================================
3147 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3148 +++ head-2008-11-25/arch/x86/kernel/io_apic_32-xen.c 2008-11-25 12:22:34.000000000 +0100
3151 + * Intel IO-APIC support for multi-Pentium hosts.
3153 + * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
3155 + * Many thanks to Stig Venaas for trying out countless experimental
3156 + * patches and reporting/debugging problems patiently!
3158 + * (c) 1999, Multiple IO-APIC support, developed by
3159 + * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
3160 + * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
3161 + * further tested and cleaned up by Zach Brown <zab@redhat.com>
3162 + * and Ingo Molnar <mingo@redhat.com>
3165 + * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
3166 + * thanks to Eric Gilmore
3167 + * and Rolf G. Tews
3168 + * for testing these extensively
3169 + * Paul Diefenbaugh : Added full ACPI support
3172 +#include <linux/mm.h>
3173 +#include <linux/interrupt.h>
3174 +#include <linux/init.h>
3175 +#include <linux/delay.h>
3176 +#include <linux/sched.h>
3177 +#include <linux/smp_lock.h>
3178 +#include <linux/mc146818rtc.h>
3179 +#include <linux/compiler.h>
3180 +#include <linux/acpi.h>
3181 +#include <linux/module.h>
3182 +#include <linux/sysdev.h>
3184 +#include <asm/io.h>
3185 +#include <asm/smp.h>
3186 +#include <asm/desc.h>
3187 +#include <asm/timer.h>
3188 +#include <asm/i8259.h>
3189 +#include <asm/nmi.h>
3191 +#include <mach_apic.h>
3193 +#include "io_ports.h"
3197 +#include <xen/interface/xen.h>
3198 +#include <xen/interface/physdev.h>
3199 +#include <xen/evtchn.h>
3202 +#define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
3203 +#define disable_8259A_irq(_irq) ((void)0)
3204 +#define i8259A_irq_pending(_irq) (0)
3206 +unsigned long io_apic_irqs;
3208 +static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
3210 + struct physdev_apic apic_op;
3213 + apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
3214 + apic_op.reg = reg;
3215 + ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
3218 + return apic_op.value;
3221 +static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
3223 + struct physdev_apic apic_op;
3225 + apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
3226 + apic_op.reg = reg;
3227 + apic_op.value = value;
3228 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
3231 +#define io_apic_read(a,r) xen_io_apic_read(a,r)
3232 +#define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
3234 +#endif /* CONFIG_XEN */
3236 +int (*ioapic_renumber_irq)(int ioapic, int irq);
3237 +atomic_t irq_mis_count;
3239 +/* Where if anywhere is the i8259 connect in external int mode */
3240 +static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
3242 +static DEFINE_SPINLOCK(ioapic_lock);
3243 +static DEFINE_SPINLOCK(vector_lock);
3245 +int timer_over_8254 __initdata = 1;
3248 + * Is the SiS APIC rmw bug present ?
3249 + * -1 = don't know, 0 = no, 1 = yes
3251 +int sis_apic_bug = -1;
3254 + * # of IRQ routing registers
3256 +int nr_ioapic_registers[MAX_IO_APICS];
3258 +int disable_timer_pin_1 __initdata;
3261 + * Rough estimation of how many shared IRQs there are, can
3262 + * be changed anytime.
3264 +#define MAX_PLUS_SHARED_IRQS NR_IRQS
3265 +#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
3268 + * This is performance-critical, we want to do it O(1)
3270 + * the indexing order of this array favors 1:1 mappings
3271 + * between pins and IRQs.
3274 +static struct irq_pin_list {
3275 + int apic, pin, next;
3276 +} irq_2_pin[PIN_MAP_SIZE];
3278 +int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
3279 +#ifdef CONFIG_PCI_MSI
3280 +#define vector_to_irq(vector) \
3281 + (platform_legacy_irq(vector) ? vector : vector_irq[vector])
3283 +#define vector_to_irq(vector) (vector)
3287 + * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
3288 + * shared ISA-space IRQs, so we have to support them. We are super
3289 + * fast in the common case, and fast for shared ISA-space IRQs.
3291 +static void add_pin_to_irq(unsigned int irq, int apic, int pin)
3293 + static int first_free_entry = NR_IRQS;
3294 + struct irq_pin_list *entry = irq_2_pin + irq;
3296 + while (entry->next)
3297 + entry = irq_2_pin + entry->next;
3299 + if (entry->pin != -1) {
3300 + entry->next = first_free_entry;
3301 + entry = irq_2_pin + entry->next;
3302 + if (++first_free_entry >= PIN_MAP_SIZE)
3303 + panic("io_apic.c: whoops");
3305 + entry->apic = apic;
3310 +#define clear_IO_APIC() ((void)0)
3313 + * Reroute an IRQ to a different pin.
3315 +static void __init replace_pin_at_irq(unsigned int irq,
3316 + int oldapic, int oldpin,
3317 + int newapic, int newpin)
3319 + struct irq_pin_list *entry = irq_2_pin + irq;
3322 + if (entry->apic == oldapic && entry->pin == oldpin) {
3323 + entry->apic = newapic;
3324 + entry->pin = newpin;
3328 + entry = irq_2_pin + entry->next;
3332 +static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
3334 + struct irq_pin_list *entry = irq_2_pin + irq;
3335 + unsigned int pin, reg;
3341 + reg = io_apic_read(entry->apic, 0x10 + pin*2);
3344 + io_apic_modify(entry->apic, 0x10 + pin*2, reg);
3347 + entry = irq_2_pin + entry->next;
3352 +static void __mask_IO_APIC_irq (unsigned int irq)
3354 + __modify_IO_APIC_irq(irq, 0x00010000, 0);
3358 +static void __unmask_IO_APIC_irq (unsigned int irq)
3360 + __modify_IO_APIC_irq(irq, 0, 0x00010000);
3363 +/* mask = 1, trigger = 0 */
3364 +static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
3366 + __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
3369 +/* mask = 0, trigger = 1 */
3370 +static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
3372 + __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
3375 +static void mask_IO_APIC_irq (unsigned int irq)
3377 + unsigned long flags;
3379 + spin_lock_irqsave(&ioapic_lock, flags);
3380 + __mask_IO_APIC_irq(irq);
3381 + spin_unlock_irqrestore(&ioapic_lock, flags);
3384 +static void unmask_IO_APIC_irq (unsigned int irq)
3386 + unsigned long flags;
3388 + spin_lock_irqsave(&ioapic_lock, flags);
3389 + __unmask_IO_APIC_irq(irq);
3390 + spin_unlock_irqrestore(&ioapic_lock, flags);
3393 +static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
3395 + struct IO_APIC_route_entry entry;
3396 + unsigned long flags;
3398 + /* Check delivery_mode to be sure we're not clearing an SMI pin */
3399 + spin_lock_irqsave(&ioapic_lock, flags);
3400 + *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
3401 + *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
3402 + spin_unlock_irqrestore(&ioapic_lock, flags);
3403 + if (entry.delivery_mode == dest_SMI)
3407 + * Disable it in the IO-APIC irq-routing table:
3409 + memset(&entry, 0, sizeof(entry));
3411 + spin_lock_irqsave(&ioapic_lock, flags);
3412 + io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
3413 + io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
3414 + spin_unlock_irqrestore(&ioapic_lock, flags);
3417 +static void clear_IO_APIC (void)
3421 + for (apic = 0; apic < nr_ioapics; apic++)
3422 + for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
3423 + clear_IO_APIC_pin(apic, pin);
3427 +static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
3429 + unsigned long flags;
3431 + struct irq_pin_list *entry = irq_2_pin + irq;
3432 + unsigned int apicid_value;
3435 + cpus_and(tmp, cpumask, cpu_online_map);
3436 + if (cpus_empty(tmp))
3437 + tmp = TARGET_CPUS;
3439 + cpus_and(cpumask, tmp, CPU_MASK_ALL);
3441 + apicid_value = cpu_mask_to_apicid(cpumask);
3442 + /* Prepare to do the io_apic_write */
3443 + apicid_value = apicid_value << 24;
3444 + spin_lock_irqsave(&ioapic_lock, flags);
3449 + io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
3452 + entry = irq_2_pin + entry->next;
3454 + set_irq_info(irq, cpumask);
3455 + spin_unlock_irqrestore(&ioapic_lock, flags);
3458 +#if defined(CONFIG_IRQBALANCE)
3459 +# include <asm/processor.h> /* kernel_thread() */
3460 +# include <linux/kernel_stat.h> /* kstat */
3461 +# include <linux/slab.h> /* kmalloc() */
3462 +# include <linux/timer.h> /* time_after() */
3464 +#ifdef CONFIG_BALANCED_IRQ_DEBUG
3465 +# define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
3466 +# define Dprintk(x...) do { TDprintk(x); } while (0)
3468 +# define TDprintk(x...)
3469 +# define Dprintk(x...)
3472 +#define IRQBALANCE_CHECK_ARCH -999
3473 +#define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
3474 +#define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
3475 +#define BALANCED_IRQ_MORE_DELTA (HZ/10)
3476 +#define BALANCED_IRQ_LESS_DELTA (HZ)
3478 +static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
3479 +static int physical_balance __read_mostly;
3480 +static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
3482 +static struct irq_cpu_info {
3483 + unsigned long * last_irq;
3484 + unsigned long * irq_delta;
3485 + unsigned long irq;
3486 +} irq_cpu_data[NR_CPUS];
3488 +#define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
3489 +#define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
3490 +#define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
3492 +#define IDLE_ENOUGH(cpu,now) \
3493 + (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
3495 +#define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
3497 +#define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
3499 +static cpumask_t balance_irq_affinity[NR_IRQS] = {
3500 + [0 ... NR_IRQS-1] = CPU_MASK_ALL
3503 +void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
3505 + balance_irq_affinity[irq] = mask;
3508 +static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
3509 + unsigned long now, int direction)
3511 + int search_idle = 1;
3512 + int cpu = curr_cpu;
3517 + if (unlikely(cpu == curr_cpu))
3520 + if (direction == 1) {
3522 + if (cpu >= NR_CPUS)
3529 + } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
3530 + (search_idle && !IDLE_ENOUGH(cpu,now)));
3535 +static inline void balance_irq(int cpu, int irq)
3537 + unsigned long now = jiffies;
3538 + cpumask_t allowed_mask;
3539 + unsigned int new_cpu;
3541 + if (irqbalance_disabled)
3544 + cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
3545 + new_cpu = move(cpu, allowed_mask, now, 1);
3546 + if (cpu != new_cpu) {
3547 + set_pending_irq(irq, cpumask_of_cpu(new_cpu));
3551 +static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
3554 + Dprintk("Rotating IRQs among CPUs.\n");
3555 + for_each_online_cpu(i) {
3556 + for (j = 0; j < NR_IRQS; j++) {
3557 + if (!irq_desc[j].action)
3559 + /* Is it a significant load ? */
3560 + if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
3561 + useful_load_threshold)
3563 + balance_irq(i, j);
3566 + balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
3567 + balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
3571 +static void do_irq_balance(void)
3574 + unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
3575 + unsigned long move_this_load = 0;
3576 + int max_loaded = 0, min_loaded = 0;
3578 + unsigned long useful_load_threshold = balanced_irq_interval + 10;
3580 + int tmp_loaded, first_attempt = 1;
3581 + unsigned long tmp_cpu_irq;
3582 + unsigned long imbalance = 0;
3583 + cpumask_t allowed_mask, target_cpu_mask, tmp;
3585 + for_each_possible_cpu(i) {
3586 + int package_index;
3588 + if (!cpu_online(i))
3590 + package_index = CPU_TO_PACKAGEINDEX(i);
3591 + for (j = 0; j < NR_IRQS; j++) {
3592 + unsigned long value_now, delta;
3593 + /* Is this an active IRQ? */
3594 + if (!irq_desc[j].action)
3596 + if ( package_index == i )
3597 + IRQ_DELTA(package_index,j) = 0;
3598 + /* Determine the total count per processor per IRQ */
3599 + value_now = (unsigned long) kstat_cpu(i).irqs[j];
3601 + /* Determine the activity per processor per IRQ */
3602 + delta = value_now - LAST_CPU_IRQ(i,j);
3604 + /* Update last_cpu_irq[][] for the next time */
3605 + LAST_CPU_IRQ(i,j) = value_now;
3607 + /* Ignore IRQs whose rate is less than the clock */
3608 + if (delta < useful_load_threshold)
3610 + /* update the load for the processor or package total */
3611 + IRQ_DELTA(package_index,j) += delta;
3613 + /* Keep track of the higher numbered sibling as well */
3614 + if (i != package_index)
3615 + CPU_IRQ(i) += delta;
3617 + * We have sibling A and sibling B in the package
3619 + * cpu_irq[A] = load for cpu A + load for cpu B
3620 + * cpu_irq[B] = load for cpu B
3622 + CPU_IRQ(package_index) += delta;
3625 + /* Find the least loaded processor package */
3626 + for_each_online_cpu(i) {
3627 + if (i != CPU_TO_PACKAGEINDEX(i))
3629 + if (min_cpu_irq > CPU_IRQ(i)) {
3630 + min_cpu_irq = CPU_IRQ(i);
3634 + max_cpu_irq = ULONG_MAX;
3637 + /* Look for heaviest loaded processor.
3638 + * We may come back to get the next heaviest loaded processor.
3639 + * Skip processors with trivial loads.
3643 + for_each_online_cpu(i) {
3644 + if (i != CPU_TO_PACKAGEINDEX(i))
3646 + if (max_cpu_irq <= CPU_IRQ(i))
3648 + if (tmp_cpu_irq < CPU_IRQ(i)) {
3649 + tmp_cpu_irq = CPU_IRQ(i);
3654 + if (tmp_loaded == -1) {
3655 + /* In the case of small number of heavy interrupt sources,
3656 + * loading some of the cpus too much. We use Ingo's original
3657 + * approach to rotate them around.
3659 + if (!first_attempt && imbalance >= useful_load_threshold) {
3660 + rotate_irqs_among_cpus(useful_load_threshold);
3663 + goto not_worth_the_effort;
3666 + first_attempt = 0; /* heaviest search */
3667 + max_cpu_irq = tmp_cpu_irq; /* load */
3668 + max_loaded = tmp_loaded; /* processor */
3669 + imbalance = (max_cpu_irq - min_cpu_irq) / 2;
3671 + Dprintk("max_loaded cpu = %d\n", max_loaded);
3672 + Dprintk("min_loaded cpu = %d\n", min_loaded);
3673 + Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
3674 + Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
3675 + Dprintk("load imbalance = %lu\n", imbalance);
3677 + /* if imbalance is less than approx 10% of max load, then
3678 + * observe diminishing returns action. - quit
3680 + if (imbalance < (max_cpu_irq >> 3)) {
3681 + Dprintk("Imbalance too trivial\n");
3682 + goto not_worth_the_effort;
3686 + /* if we select an IRQ to move that can't go where we want, then
3687 + * see if there is another one to try.
3689 + move_this_load = 0;
3690 + selected_irq = -1;
3691 + for (j = 0; j < NR_IRQS; j++) {
3692 + /* Is this an active IRQ? */
3693 + if (!irq_desc[j].action)
3695 + if (imbalance <= IRQ_DELTA(max_loaded,j))
3697 + /* Try to find the IRQ that is closest to the imbalance
3698 + * without going over.
3700 + if (move_this_load < IRQ_DELTA(max_loaded,j)) {
3701 + move_this_load = IRQ_DELTA(max_loaded,j);
3705 + if (selected_irq == -1) {
3706 + goto tryanothercpu;
3709 + imbalance = move_this_load;
3711 + /* For physical_balance case, we accumlated both load
3712 + * values in the one of the siblings cpu_irq[],
3713 + * to use the same code for physical and logical processors
3714 + * as much as possible.
3716 + * NOTE: the cpu_irq[] array holds the sum of the load for
3717 + * sibling A and sibling B in the slot for the lowest numbered
3718 + * sibling (A), _AND_ the load for sibling B in the slot for
3719 + * the higher numbered sibling.
3721 + * We seek the least loaded sibling by making the comparison
3724 + load = CPU_IRQ(min_loaded) >> 1;
3725 + for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
3726 + if (load > CPU_IRQ(j)) {
3727 + /* This won't change cpu_sibling_map[min_loaded] */
3728 + load = CPU_IRQ(j);
3733 + cpus_and(allowed_mask,
3735 + balance_irq_affinity[selected_irq]);
3736 + target_cpu_mask = cpumask_of_cpu(min_loaded);
3737 + cpus_and(tmp, target_cpu_mask, allowed_mask);
3739 + if (!cpus_empty(tmp)) {
3741 + Dprintk("irq = %d moved to cpu = %d\n",
3742 + selected_irq, min_loaded);
3743 + /* mark for change destination */
3744 + set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
3746 + /* Since we made a change, come back sooner to
3747 + * check for more variation.
3749 + balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
3750 + balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
3753 + goto tryanotherirq;
3755 +not_worth_the_effort:
3757 + * if we did not find an IRQ to move, then adjust the time interval
3760 + balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
3761 + balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
3762 + Dprintk("IRQ worth rotating not found\n");
3766 +static int balanced_irq(void *unused)
3769 + unsigned long prev_balance_time = jiffies;
3770 + long time_remaining = balanced_irq_interval;
3772 + daemonize("kirqd");
3774 + /* push everything to CPU 0 to give us a starting point. */
3775 + for (i = 0 ; i < NR_IRQS ; i++) {
3776 + irq_desc[i].pending_mask = cpumask_of_cpu(0);
3777 + set_pending_irq(i, cpumask_of_cpu(0));
3781 + time_remaining = schedule_timeout_interruptible(time_remaining);
3783 + if (time_after(jiffies,
3784 + prev_balance_time+balanced_irq_interval)) {
3785 + preempt_disable();
3787 + prev_balance_time = jiffies;
3788 + time_remaining = balanced_irq_interval;
3795 +static int __init balanced_irq_init(void)
3798 + struct cpuinfo_x86 *c;
3801 + cpus_shift_right(tmp, cpu_online_map, 2);
3802 + c = &boot_cpu_data;
3803 + /* When not overwritten by the command line ask subarchitecture. */
3804 + if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
3805 + irqbalance_disabled = NO_BALANCE_IRQ;
3806 + if (irqbalance_disabled)
3809 + /* disable irqbalance completely if there is only one processor online */
3810 + if (num_online_cpus() < 2) {
3811 + irqbalance_disabled = 1;
3815 + * Enable physical balance only if more than 1 physical processor
3818 + if (smp_num_siblings > 1 && !cpus_empty(tmp))
3819 + physical_balance = 1;
3821 + for_each_online_cpu(i) {
3822 + irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
3823 + irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
3824 + if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
3825 + printk(KERN_ERR "balanced_irq_init: out of memory");
3828 + memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
3829 + memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
3832 + printk(KERN_INFO "Starting balanced_irq\n");
3833 + if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
3836 + printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
3838 + for_each_possible_cpu(i) {
3839 + kfree(irq_cpu_data[i].irq_delta);
3840 + irq_cpu_data[i].irq_delta = NULL;
3841 + kfree(irq_cpu_data[i].last_irq);
3842 + irq_cpu_data[i].last_irq = NULL;
3847 +int __init irqbalance_disable(char *str)
3849 + irqbalance_disabled = 1;
3853 +__setup("noirqbalance", irqbalance_disable);
3855 +late_initcall(balanced_irq_init);
3856 +#endif /* CONFIG_IRQBALANCE */
3857 +#endif /* CONFIG_SMP */
3861 +void fastcall send_IPI_self(int vector)
3869 + apic_wait_icr_idle();
3870 + cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
3872 + * Send the IPI. The write to APIC_ICR fires this off.
3874 + apic_write_around(APIC_ICR, cfg);
3877 +#endif /* !CONFIG_SMP */
3881 + * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
3882 + * specific CPU-side IRQs.
3885 +#define MAX_PIRQS 8
3886 +static int pirq_entries [MAX_PIRQS];
3887 +static int pirqs_enabled;
3888 +int skip_ioapic_setup;
3890 +static int __init ioapic_setup(char *str)
3892 + skip_ioapic_setup = 1;
3896 +__setup("noapic", ioapic_setup);
3898 +static int __init ioapic_pirq_setup(char *str)
3901 + int ints[MAX_PIRQS+1];
3903 + get_options(str, ARRAY_SIZE(ints), ints);
3905 + for (i = 0; i < MAX_PIRQS; i++)
3906 + pirq_entries[i] = -1;
3908 + pirqs_enabled = 1;
3909 + apic_printk(APIC_VERBOSE, KERN_INFO
3910 + "PIRQ redirection, working around broken MP-BIOS.\n");
3912 + if (ints[0] < MAX_PIRQS)
3915 + for (i = 0; i < max; i++) {
3916 + apic_printk(APIC_VERBOSE, KERN_DEBUG
3917 + "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
3919 + * PIRQs are mapped upside down, usually.
3921 + pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
3926 +__setup("pirq=", ioapic_pirq_setup);
3929 + * Find the IRQ entry number of a certain pin.
3931 +static int find_irq_entry(int apic, int pin, int type)
3935 + for (i = 0; i < mp_irq_entries; i++)
3936 + if (mp_irqs[i].mpc_irqtype == type &&
3937 + (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
3938 + mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
3939 + mp_irqs[i].mpc_dstirq == pin)
3946 + * Find the pin to which IRQ[irq] (ISA) is connected
3948 +static int __init find_isa_irq_pin(int irq, int type)
3952 + for (i = 0; i < mp_irq_entries; i++) {
3953 + int lbus = mp_irqs[i].mpc_srcbus;
3955 + if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
3956 + mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
3957 + mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
3958 + mp_bus_id_to_type[lbus] == MP_BUS_NEC98
3960 + (mp_irqs[i].mpc_irqtype == type) &&
3961 + (mp_irqs[i].mpc_srcbusirq == irq))
3963 + return mp_irqs[i].mpc_dstirq;
3968 +static int __init find_isa_irq_apic(int irq, int type)
3972 + for (i = 0; i < mp_irq_entries; i++) {
3973 + int lbus = mp_irqs[i].mpc_srcbus;
3975 + if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
3976 + mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
3977 + mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
3978 + mp_bus_id_to_type[lbus] == MP_BUS_NEC98
3980 + (mp_irqs[i].mpc_irqtype == type) &&
3981 + (mp_irqs[i].mpc_srcbusirq == irq))
3984 + if (i < mp_irq_entries) {
3986 + for(apic = 0; apic < nr_ioapics; apic++) {
3987 + if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
3996 + * Find a specific PCI IRQ entry.
3997 + * Not an __init, possibly needed by modules
3999 +static int pin_2_irq(int idx, int apic, int pin);
4001 +int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
4003 + int apic, i, best_guess = -1;
4005 + apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
4006 + "slot:%d, pin:%d.\n", bus, slot, pin);
4007 + if (mp_bus_id_to_pci_bus[bus] == -1) {
4008 + printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
4011 + for (i = 0; i < mp_irq_entries; i++) {
4012 + int lbus = mp_irqs[i].mpc_srcbus;
4014 + for (apic = 0; apic < nr_ioapics; apic++)
4015 + if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
4016 + mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
4019 + if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
4020 + !mp_irqs[i].mpc_irqtype &&
4022 + (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
4023 + int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
4025 + if (!(apic || IO_APIC_IRQ(irq)))
4028 + if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
4031 + * Use the first all-but-pin matching entry as a
4032 + * best-guess fuzzy result for broken mptables.
4034 + if (best_guess < 0)
4038 + return best_guess;
4040 +EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
4043 + * This function currently is only a helper for the i386 smp boot process where
4044 + * we need to reprogram the ioredtbls to cater for the cpus which have come online
4045 + * so mask in all cases should simply be TARGET_CPUS
4049 +void __init setup_ioapic_dest(void)
4051 + int pin, ioapic, irq, irq_entry;
4053 + if (skip_ioapic_setup == 1)
4056 + for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4057 + for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4058 + irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4059 + if (irq_entry == -1)
4061 + irq = pin_2_irq(irq_entry, ioapic, pin);
4062 + set_ioapic_affinity_irq(irq, TARGET_CPUS);
4067 +#endif /* !CONFIG_XEN */
4071 + * EISA Edge/Level control register, ELCR
4073 +static int EISA_ELCR(unsigned int irq)
4076 + unsigned int port = 0x4d0 + (irq >> 3);
4077 + return (inb(port) >> (irq & 7)) & 1;
4079 + apic_printk(APIC_VERBOSE, KERN_INFO
4080 + "Broken MPtable reports ISA irq %d\n", irq);
4084 +/* EISA interrupts are always polarity zero and can be edge or level
4085 + * trigger depending on the ELCR value. If an interrupt is listed as
4086 + * EISA conforming in the MP table, that means its trigger type must
4087 + * be read in from the ELCR */
4089 +#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
4090 +#define default_EISA_polarity(idx) (0)
4092 +/* ISA interrupts are always polarity zero edge triggered,
4093 + * when listed as conforming in the MP table. */
4095 +#define default_ISA_trigger(idx) (0)
4096 +#define default_ISA_polarity(idx) (0)
4098 +/* PCI interrupts are always polarity one level triggered,
4099 + * when listed as conforming in the MP table. */
4101 +#define default_PCI_trigger(idx) (1)
4102 +#define default_PCI_polarity(idx) (1)
4104 +/* MCA interrupts are always polarity zero level triggered,
4105 + * when listed as conforming in the MP table. */
4107 +#define default_MCA_trigger(idx) (1)
4108 +#define default_MCA_polarity(idx) (0)
4110 +/* NEC98 interrupts are always polarity zero edge triggered,
4111 + * when listed as conforming in the MP table. */
4113 +#define default_NEC98_trigger(idx) (0)
4114 +#define default_NEC98_polarity(idx) (0)
4116 +static int __init MPBIOS_polarity(int idx)
4118 + int bus = mp_irqs[idx].mpc_srcbus;
4122 + * Determine IRQ line polarity (high active or low active):
4124 + switch (mp_irqs[idx].mpc_irqflag & 3)
4126 + case 0: /* conforms, ie. bus-type dependent polarity */
4128 + switch (mp_bus_id_to_type[bus])
4130 + case MP_BUS_ISA: /* ISA pin */
4132 + polarity = default_ISA_polarity(idx);
4135 + case MP_BUS_EISA: /* EISA pin */
4137 + polarity = default_EISA_polarity(idx);
4140 + case MP_BUS_PCI: /* PCI pin */
4142 + polarity = default_PCI_polarity(idx);
4145 + case MP_BUS_MCA: /* MCA pin */
4147 + polarity = default_MCA_polarity(idx);
4150 + case MP_BUS_NEC98: /* NEC 98 pin */
4152 + polarity = default_NEC98_polarity(idx);
4157 + printk(KERN_WARNING "broken BIOS!!\n");
4164 + case 1: /* high active */
4169 + case 2: /* reserved */
4171 + printk(KERN_WARNING "broken BIOS!!\n");
4175 + case 3: /* low active */
4180 + default: /* invalid */
4182 + printk(KERN_WARNING "broken BIOS!!\n");
4190 +static int MPBIOS_trigger(int idx)
4192 + int bus = mp_irqs[idx].mpc_srcbus;
4196 + * Determine IRQ trigger mode (edge or level sensitive):
4198 + switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
4200 + case 0: /* conforms, ie. bus-type dependent */
4202 + switch (mp_bus_id_to_type[bus])
4204 + case MP_BUS_ISA: /* ISA pin */
4206 + trigger = default_ISA_trigger(idx);
4209 + case MP_BUS_EISA: /* EISA pin */
4211 + trigger = default_EISA_trigger(idx);
4214 + case MP_BUS_PCI: /* PCI pin */
4216 + trigger = default_PCI_trigger(idx);
4219 + case MP_BUS_MCA: /* MCA pin */
4221 + trigger = default_MCA_trigger(idx);
4224 + case MP_BUS_NEC98: /* NEC 98 pin */
4226 + trigger = default_NEC98_trigger(idx);
4231 + printk(KERN_WARNING "broken BIOS!!\n");
4238 + case 1: /* edge */
4243 + case 2: /* reserved */
4245 + printk(KERN_WARNING "broken BIOS!!\n");
4249 + case 3: /* level */
4254 + default: /* invalid */
4256 + printk(KERN_WARNING "broken BIOS!!\n");
4264 +static inline int irq_polarity(int idx)
4266 + return MPBIOS_polarity(idx);
4269 +static inline int irq_trigger(int idx)
4271 + return MPBIOS_trigger(idx);
4274 +static int pin_2_irq(int idx, int apic, int pin)
4277 + int bus = mp_irqs[idx].mpc_srcbus;
4280 + * Debugging check, we are in big trouble if this message pops up!
4282 + if (mp_irqs[idx].mpc_dstirq != pin)
4283 + printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
4285 + switch (mp_bus_id_to_type[bus])
4287 + case MP_BUS_ISA: /* ISA pin */
4290 + case MP_BUS_NEC98:
4292 + irq = mp_irqs[idx].mpc_srcbusirq;
4295 + case MP_BUS_PCI: /* PCI pin */
4298 + * PCI IRQs are mapped in order
4302 + irq += nr_ioapic_registers[i++];
4306 + * For MPS mode, so far only needed by ES7000 platform
4308 + if (ioapic_renumber_irq)
4309 + irq = ioapic_renumber_irq(apic, irq);
4315 + printk(KERN_ERR "unknown bus type %d.\n",bus);
4322 + * PCI IRQ command line redirection. Yes, limits are hardcoded.
4324 + if ((pin >= 16) && (pin <= 23)) {
4325 + if (pirq_entries[pin-16] != -1) {
4326 + if (!pirq_entries[pin-16]) {
4327 + apic_printk(APIC_VERBOSE, KERN_DEBUG
4328 + "disabling PIRQ%d\n", pin-16);
4330 + irq = pirq_entries[pin-16];
4331 + apic_printk(APIC_VERBOSE, KERN_DEBUG
4332 + "using PIRQ%d -> IRQ %d\n",
4340 +static inline int IO_APIC_irq_trigger(int irq)
4342 + int apic, idx, pin;
4344 + for (apic = 0; apic < nr_ioapics; apic++) {
4345 + for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
4346 + idx = find_irq_entry(apic,pin,mp_INT);
4347 + if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
4348 + return irq_trigger(idx);
4352 + * nonexistent IRQs are edge default
4357 +/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
4358 +u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
4360 +int assign_irq_vector(int irq)
4362 + unsigned long flags;
4364 + struct physdev_irq irq_op;
4366 + BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
4368 + if (irq < PIRQ_BASE || irq - PIRQ_BASE > NR_PIRQS)
4371 + spin_lock_irqsave(&vector_lock, flags);
4373 + if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
4374 + spin_unlock_irqrestore(&vector_lock, flags);
4375 + return IO_APIC_VECTOR(irq);
4379 + if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
4380 + spin_unlock_irqrestore(&vector_lock, flags);
4384 + vector = irq_op.vector;
4385 + vector_irq[vector] = irq;
4386 + if (irq != AUTO_ASSIGN)
4387 + IO_APIC_VECTOR(irq) = vector;
4389 + spin_unlock_irqrestore(&vector_lock, flags);
4395 +static struct hw_interrupt_type ioapic_level_type;
4396 +static struct hw_interrupt_type ioapic_edge_type;
4398 +#define IOAPIC_AUTO -1
4399 +#define IOAPIC_EDGE 0
4400 +#define IOAPIC_LEVEL 1
4402 +static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
4406 + idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
4408 + if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
4409 + trigger == IOAPIC_LEVEL)
4410 + irq_desc[idx].chip = &ioapic_level_type;
4412 + irq_desc[idx].chip = &ioapic_edge_type;
4413 + set_intr_gate(vector, interrupt[idx]);
4416 +#define ioapic_register_intr(irq, vector, trigger) evtchn_register_pirq(irq)
4419 +static void __init setup_IO_APIC_irqs(void)
4421 + struct IO_APIC_route_entry entry;
4422 + int apic, pin, idx, irq, first_notcon = 1, vector;
4423 + unsigned long flags;
4425 + apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
4427 + for (apic = 0; apic < nr_ioapics; apic++) {
4428 + for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
4431 + * add it to the IO-APIC irq-routing table:
4433 + memset(&entry,0,sizeof(entry));
4435 + entry.delivery_mode = INT_DELIVERY_MODE;
4436 + entry.dest_mode = INT_DEST_MODE;
4437 + entry.mask = 0; /* enable IRQ */
4438 + entry.dest.logical.logical_dest =
4439 + cpu_mask_to_apicid(TARGET_CPUS);
4441 + idx = find_irq_entry(apic,pin,mp_INT);
4443 + if (first_notcon) {
4444 + apic_printk(APIC_VERBOSE, KERN_DEBUG
4445 + " IO-APIC (apicid-pin) %d-%d",
4446 + mp_ioapics[apic].mpc_apicid,
4450 + apic_printk(APIC_VERBOSE, ", %d-%d",
4451 + mp_ioapics[apic].mpc_apicid, pin);
4455 + entry.trigger = irq_trigger(idx);
4456 + entry.polarity = irq_polarity(idx);
4458 + if (irq_trigger(idx)) {
4459 + entry.trigger = 1;
4463 + irq = pin_2_irq(idx, apic, pin);
4465 + * skip adding the timer int on secondary nodes, which causes
4466 + * a small but painful rift in the time-space continuum
4468 + if (multi_timer_check(apic, irq))
4471 + add_pin_to_irq(irq, apic, pin);
4473 + if (/*!apic &&*/ !IO_APIC_IRQ(irq))
4476 + if (IO_APIC_IRQ(irq)) {
4477 + vector = assign_irq_vector(irq);
4478 + entry.vector = vector;
4479 + ioapic_register_intr(irq, vector, IOAPIC_AUTO);
4481 + if (!apic && (irq < 16))
4482 + disable_8259A_irq(irq);
4484 + spin_lock_irqsave(&ioapic_lock, flags);
4485 + io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
4486 + io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
4487 + set_native_irq_info(irq, TARGET_CPUS);
4488 + spin_unlock_irqrestore(&ioapic_lock, flags);
4492 + if (!first_notcon)
4493 + apic_printk(APIC_VERBOSE, " not connected.\n");
4497 + * Set up the 8259A-master output pin:
4500 +static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
4502 + struct IO_APIC_route_entry entry;
4503 + unsigned long flags;
4505 + memset(&entry,0,sizeof(entry));
4507 + disable_8259A_irq(0);
4510 + apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
4513 + * We use logical delivery to get the timer IRQ
4514 + * to the first CPU.
4516 + entry.dest_mode = INT_DEST_MODE;
4517 + entry.mask = 0; /* unmask IRQ now */
4518 + entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
4519 + entry.delivery_mode = INT_DELIVERY_MODE;
4520 + entry.polarity = 0;
4521 + entry.trigger = 0;
4522 + entry.vector = vector;
4525 + * The timer IRQ doesn't have to know that behind the
4526 + * scene we have a 8259A-master in AEOI mode ...
4528 + irq_desc[0].chip = &ioapic_edge_type;
4531 + * Add it to the IO-APIC irq-routing table:
4533 + spin_lock_irqsave(&ioapic_lock, flags);
4534 + io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
4535 + io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
4536 + spin_unlock_irqrestore(&ioapic_lock, flags);
4538 + enable_8259A_irq(0);
4541 +static inline void UNEXPECTED_IO_APIC(void)
4545 +void __init print_IO_APIC(void)
4548 + union IO_APIC_reg_00 reg_00;
4549 + union IO_APIC_reg_01 reg_01;
4550 + union IO_APIC_reg_02 reg_02;
4551 + union IO_APIC_reg_03 reg_03;
4552 + unsigned long flags;
4554 + if (apic_verbosity == APIC_QUIET)
4557 + printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
4558 + for (i = 0; i < nr_ioapics; i++)
4559 + printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
4560 + mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
4563 + * We are a bit conservative about what we expect. We have to
4564 + * know about every hardware change ASAP.
4566 + printk(KERN_INFO "testing the IO APIC.......................\n");
4568 + for (apic = 0; apic < nr_ioapics; apic++) {
4570 + spin_lock_irqsave(&ioapic_lock, flags);
4571 + reg_00.raw = io_apic_read(apic, 0);
4572 + reg_01.raw = io_apic_read(apic, 1);
4573 + if (reg_01.bits.version >= 0x10)
4574 + reg_02.raw = io_apic_read(apic, 2);
4575 + if (reg_01.bits.version >= 0x20)
4576 + reg_03.raw = io_apic_read(apic, 3);
4577 + spin_unlock_irqrestore(&ioapic_lock, flags);
4579 + printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
4580 + printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
4581 + printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
4582 + printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
4583 + printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
4584 + if (reg_00.bits.ID >= get_physical_broadcast())
4585 + UNEXPECTED_IO_APIC();
4586 + if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
4587 + UNEXPECTED_IO_APIC();
4589 + printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
4590 + printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
4591 + if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
4592 + (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
4593 + (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
4594 + (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
4595 + (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
4596 + (reg_01.bits.entries != 0x2E) &&
4597 + (reg_01.bits.entries != 0x3F)
4599 + UNEXPECTED_IO_APIC();
4601 + printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
4602 + printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
4603 + if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
4604 + (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
4605 + (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
4606 + (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
4607 + (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
4609 + UNEXPECTED_IO_APIC();
4610 + if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
4611 + UNEXPECTED_IO_APIC();
4614 + * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
4615 + * but the value of reg_02 is read as the previous read register
4616 + * value, so ignore it if reg_02 == reg_01.
4618 + if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
4619 + printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
4620 + printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
4621 + if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
4622 + UNEXPECTED_IO_APIC();
4626 + * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
4627 + * or reg_03, but the value of reg_0[23] is read as the previous read
4628 + * register value, so ignore it if reg_03 == reg_0[12].
4630 + if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
4631 + reg_03.raw != reg_01.raw) {
4632 + printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
4633 + printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
4634 + if (reg_03.bits.__reserved_1)
4635 + UNEXPECTED_IO_APIC();
4638 + printk(KERN_DEBUG ".... IRQ redirection table:\n");
4640 + printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
4641 + " Stat Dest Deli Vect: \n");
4643 + for (i = 0; i <= reg_01.bits.entries; i++) {
4644 + struct IO_APIC_route_entry entry;
4646 + spin_lock_irqsave(&ioapic_lock, flags);
4647 + *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
4648 + *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
4649 + spin_unlock_irqrestore(&ioapic_lock, flags);
4651 + printk(KERN_DEBUG " %02x %03X %02X ",
4653 + entry.dest.logical.logical_dest,
4654 + entry.dest.physical.physical_dest
4657 + printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
4662 + entry.delivery_status,
4664 + entry.delivery_mode,
4669 + if (use_pci_vector())
4670 + printk(KERN_INFO "Using vector-based indexing\n");
4671 + printk(KERN_DEBUG "IRQ to pin mappings:\n");
4672 + for (i = 0; i < NR_IRQS; i++) {
4673 + struct irq_pin_list *entry = irq_2_pin + i;
4674 + if (entry->pin < 0)
4676 + if (use_pci_vector() && !platform_legacy_irq(i))
4677 + printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
4679 + printk(KERN_DEBUG "IRQ%d ", i);
4681 + printk("-> %d:%d", entry->apic, entry->pin);
4684 + entry = irq_2_pin + entry->next;
4689 + printk(KERN_INFO ".................................... done.\n");
4694 +static void print_APIC_bitfield (int base)
4699 + if (apic_verbosity == APIC_QUIET)
4702 + printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
4703 + for (i = 0; i < 8; i++) {
4704 + v = apic_read(base + i*0x10);
4705 + for (j = 0; j < 32; j++) {
4715 +void /*__init*/ print_local_APIC(void * dummy)
4717 + unsigned int v, ver, maxlvt;
4719 + if (apic_verbosity == APIC_QUIET)
4722 + printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
4723 + smp_processor_id(), hard_smp_processor_id());
4724 + v = apic_read(APIC_ID);
4725 + printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
4726 + v = apic_read(APIC_LVR);
4727 + printk(KERN_INFO "... APIC VERSION: %08x\n", v);
4728 + ver = GET_APIC_VERSION(v);
4729 + maxlvt = get_maxlvt();
4731 + v = apic_read(APIC_TASKPRI);
4732 + printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
4734 + if (APIC_INTEGRATED(ver)) { /* !82489DX */
4735 + v = apic_read(APIC_ARBPRI);
4736 + printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
4737 + v & APIC_ARBPRI_MASK);
4738 + v = apic_read(APIC_PROCPRI);
4739 + printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
4742 + v = apic_read(APIC_EOI);
4743 + printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
4744 + v = apic_read(APIC_RRR);
4745 + printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
4746 + v = apic_read(APIC_LDR);
4747 + printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
4748 + v = apic_read(APIC_DFR);
4749 + printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
4750 + v = apic_read(APIC_SPIV);
4751 + printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
4753 + printk(KERN_DEBUG "... APIC ISR field:\n");
4754 + print_APIC_bitfield(APIC_ISR);
4755 + printk(KERN_DEBUG "... APIC TMR field:\n");
4756 + print_APIC_bitfield(APIC_TMR);
4757 + printk(KERN_DEBUG "... APIC IRR field:\n");
4758 + print_APIC_bitfield(APIC_IRR);
4760 + if (APIC_INTEGRATED(ver)) { /* !82489DX */
4761 + if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
4762 + apic_write(APIC_ESR, 0);
4763 + v = apic_read(APIC_ESR);
4764 + printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
4767 + v = apic_read(APIC_ICR);
4768 + printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
4769 + v = apic_read(APIC_ICR2);
4770 + printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
4772 + v = apic_read(APIC_LVTT);
4773 + printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
4775 + if (maxlvt > 3) { /* PC is LVT#4. */
4776 + v = apic_read(APIC_LVTPC);
4777 + printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
4779 + v = apic_read(APIC_LVT0);
4780 + printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
4781 + v = apic_read(APIC_LVT1);
4782 + printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
4784 + if (maxlvt > 2) { /* ERR is LVT#3. */
4785 + v = apic_read(APIC_LVTERR);
4786 + printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
4789 + v = apic_read(APIC_TMICT);
4790 + printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
4791 + v = apic_read(APIC_TMCCT);
4792 + printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
4793 + v = apic_read(APIC_TDCR);
4794 + printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
4798 +void print_all_local_APICs (void)
4800 + on_each_cpu(print_local_APIC, NULL, 1, 1);
4803 +void /*__init*/ print_PIC(void)
4806 + unsigned long flags;
4808 + if (apic_verbosity == APIC_QUIET)
4811 + printk(KERN_DEBUG "\nprinting PIC contents\n");
4813 + spin_lock_irqsave(&i8259A_lock, flags);
4815 + v = inb(0xa1) << 8 | inb(0x21);
4816 + printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
4818 + v = inb(0xa0) << 8 | inb(0x20);
4819 + printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
4823 + v = inb(0xa0) << 8 | inb(0x20);
4827 + spin_unlock_irqrestore(&i8259A_lock, flags);
4829 + printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
4831 + v = inb(0x4d1) << 8 | inb(0x4d0);
4832 + printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
4834 +#endif /* !CONFIG_XEN */
4836 +static void __init enable_IO_APIC(void)
4838 + union IO_APIC_reg_01 reg_01;
4839 + int i8259_apic, i8259_pin;
4841 + unsigned long flags;
4843 + for (i = 0; i < PIN_MAP_SIZE; i++) {
4844 + irq_2_pin[i].pin = -1;
4845 + irq_2_pin[i].next = 0;
4847 + if (!pirqs_enabled)
4848 + for (i = 0; i < MAX_PIRQS; i++)
4849 + pirq_entries[i] = -1;
4852 + * The number of IO-APIC IRQ registers (== #pins):
4854 + for (apic = 0; apic < nr_ioapics; apic++) {
4855 + spin_lock_irqsave(&ioapic_lock, flags);
4856 + reg_01.raw = io_apic_read(apic, 1);
4857 + spin_unlock_irqrestore(&ioapic_lock, flags);
4858 + nr_ioapic_registers[apic] = reg_01.bits.entries+1;
4860 + for(apic = 0; apic < nr_ioapics; apic++) {
4862 + /* See if any of the pins is in ExtINT mode */
4863 + for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
4864 + struct IO_APIC_route_entry entry;
4865 + spin_lock_irqsave(&ioapic_lock, flags);
4866 + *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
4867 + *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
4868 + spin_unlock_irqrestore(&ioapic_lock, flags);
4871 + /* If the interrupt line is enabled and in ExtInt mode
4872 + * I have found the pin where the i8259 is connected.
4874 + if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
4875 + ioapic_i8259.apic = apic;
4876 + ioapic_i8259.pin = pin;
4882 + /* Look to see what if the MP table has reported the ExtINT */
4883 + /* If we could not find the appropriate pin by looking at the ioapic
4884 + * the i8259 probably is not connected the ioapic but give the
4885 + * mptable a chance anyway.
4887 + i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
4888 + i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
4889 + /* Trust the MP table if nothing is setup in the hardware */
4890 + if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
4891 + printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
4892 + ioapic_i8259.pin = i8259_pin;
4893 + ioapic_i8259.apic = i8259_apic;
4895 + /* Complain if the MP table and the hardware disagree */
4896 + if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
4897 + (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
4899 + printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
4903 + * Do not trust the IO-APIC being empty at bootup
4909 + * Not an __init, needed by the reboot code
4911 +void disable_IO_APIC(void)
4914 + * Clear the IO-APIC before rebooting:
4920 + * If the i8259 is routed through an IOAPIC
4921 + * Put that IOAPIC in virtual wire mode
4922 + * so legacy interrupts can be delivered.
4924 + if (ioapic_i8259.pin != -1) {
4925 + struct IO_APIC_route_entry entry;
4926 + unsigned long flags;
4928 + memset(&entry, 0, sizeof(entry));
4929 + entry.mask = 0; /* Enabled */
4930 + entry.trigger = 0; /* Edge */
4932 + entry.polarity = 0; /* High */
4933 + entry.delivery_status = 0;
4934 + entry.dest_mode = 0; /* Physical */
4935 + entry.delivery_mode = dest_ExtINT; /* ExtInt */
4937 + entry.dest.physical.physical_dest =
4938 + GET_APIC_ID(apic_read(APIC_ID));
4941 + * Add it to the IO-APIC irq-routing table:
4943 + spin_lock_irqsave(&ioapic_lock, flags);
4944 + io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
4945 + *(((int *)&entry)+1));
4946 + io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
4947 + *(((int *)&entry)+0));
4948 + spin_unlock_irqrestore(&ioapic_lock, flags);
4950 + disconnect_bsp_APIC(ioapic_i8259.pin != -1);
4955 + * function to set the IO-APIC physical IDs based on the
4956 + * values stored in the MPC table.
4958 + * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
4961 +#if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
4962 +static void __init setup_ioapic_ids_from_mpc(void)
4964 + union IO_APIC_reg_00 reg_00;
4965 + physid_mask_t phys_id_present_map;
4968 + unsigned char old_id;
4969 + unsigned long flags;
4972 + * Don't check I/O APIC IDs for xAPIC systems. They have
4973 + * no meaning without the serial APIC bus.
4975 + if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
4976 + || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
4979 + * This is broken; anything with a real cpu count has to
4980 + * circumvent this idiocy regardless.
4982 + phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
4985 + * Set the IOAPIC ID to the value stored in the MPC table.
4987 + for (apic = 0; apic < nr_ioapics; apic++) {
4989 + /* Read the register 0 value */
4990 + spin_lock_irqsave(&ioapic_lock, flags);
4991 + reg_00.raw = io_apic_read(apic, 0);
4992 + spin_unlock_irqrestore(&ioapic_lock, flags);
4994 + old_id = mp_ioapics[apic].mpc_apicid;
4996 + if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
4997 + printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
4998 + apic, mp_ioapics[apic].mpc_apicid);
4999 + printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
5001 + mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
5005 + * Sanity check, is the ID really free? Every APIC in a
5006 + * system must have a unique ID or we get lots of nice
5007 + * 'stuck on smp_invalidate_needed IPI wait' messages.
5009 + if (check_apicid_used(phys_id_present_map,
5010 + mp_ioapics[apic].mpc_apicid)) {
5011 + printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
5012 + apic, mp_ioapics[apic].mpc_apicid);
5013 + for (i = 0; i < get_physical_broadcast(); i++)
5014 + if (!physid_isset(i, phys_id_present_map))
5016 + if (i >= get_physical_broadcast())
5017 + panic("Max APIC ID exceeded!\n");
5018 + printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
5020 + physid_set(i, phys_id_present_map);
5021 + mp_ioapics[apic].mpc_apicid = i;
5023 + physid_mask_t tmp;
5024 + tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
5025 + apic_printk(APIC_VERBOSE, "Setting %d in the "
5026 + "phys_id_present_map\n",
5027 + mp_ioapics[apic].mpc_apicid);
5028 + physids_or(phys_id_present_map, phys_id_present_map, tmp);
5033 + * We need to adjust the IRQ routing table
5034 + * if the ID changed.
5036 + if (old_id != mp_ioapics[apic].mpc_apicid)
5037 + for (i = 0; i < mp_irq_entries; i++)
5038 + if (mp_irqs[i].mpc_dstapic == old_id)
5039 + mp_irqs[i].mpc_dstapic
5040 + = mp_ioapics[apic].mpc_apicid;
5043 + * Read the right value from the MPC table and
5044 + * write it into the ID register.
5046 + apic_printk(APIC_VERBOSE, KERN_INFO
5047 + "...changing IO-APIC physical APIC ID to %d ...",
5048 + mp_ioapics[apic].mpc_apicid);
5050 + reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
5051 + spin_lock_irqsave(&ioapic_lock, flags);
5052 + io_apic_write(apic, 0, reg_00.raw);
5053 + spin_unlock_irqrestore(&ioapic_lock, flags);
5058 + spin_lock_irqsave(&ioapic_lock, flags);
5059 + reg_00.raw = io_apic_read(apic, 0);
5060 + spin_unlock_irqrestore(&ioapic_lock, flags);
5061 + if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
5062 + printk("could not set ID!\n");
5064 + apic_printk(APIC_VERBOSE, " ok.\n");
5068 +static void __init setup_ioapic_ids_from_mpc(void) { }
5073 + * There is a nasty bug in some older SMP boards, their mptable lies
5074 + * about the timer IRQ. We do the following to work around the situation:
5076 + * - timer IRQ defaults to IO-APIC IRQ
5077 + * - if this function detects that timer IRQs are defunct, then we fall
5078 + * back to ISA timer IRQs
5080 +static int __init timer_irq_works(void)
5082 + unsigned long t1 = jiffies;
5084 + local_irq_enable();
5085 + /* Let ten ticks pass... */
5086 + mdelay((10 * 1000) / HZ);
5089 + * Expect a few ticks at least, to be sure some possible
5090 + * glue logic does not lock up after one or two first
5091 + * ticks in a non-ExtINT mode. Also the local APIC
5092 + * might have cached one ExtINT interrupt. Finally, at
5093 + * least one tick may be lost due to delays.
5095 + if (jiffies - t1 > 4)
5102 + * In the SMP+IOAPIC case it might happen that there are an unspecified
5103 + * number of pending IRQ events unhandled. These cases are very rare,
5104 + * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
5105 + * better to do it this way as thus we do not have to be aware of
5106 + * 'pending' interrupts in the IRQ path, except at this point.
5109 + * Edge triggered needs to resend any interrupt
5110 + * that was delayed but this is now handled in the device
5111 + * independent code.
5115 + * Starting up a edge-triggered IO-APIC interrupt is
5116 + * nasty - we need to make sure that we get the edge.
5117 + * If it is already asserted for some reason, we need
5118 + * return 1 to indicate that is was pending.
5120 + * This is not complete - we should be able to fake
5121 + * an edge even if it isn't on the 8259A...
5123 +static unsigned int startup_edge_ioapic_irq(unsigned int irq)
5125 + int was_pending = 0;
5126 + unsigned long flags;
5128 + spin_lock_irqsave(&ioapic_lock, flags);
5130 + disable_8259A_irq(irq);
5131 + if (i8259A_irq_pending(irq))
5134 + __unmask_IO_APIC_irq(irq);
5135 + spin_unlock_irqrestore(&ioapic_lock, flags);
5137 + return was_pending;
5141 + * Once we have recorded IRQ_PENDING already, we can mask the
5142 + * interrupt for real. This prevents IRQ storms from unhandled
5145 +static void ack_edge_ioapic_irq(unsigned int irq)
5148 + if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
5149 + == (IRQ_PENDING | IRQ_DISABLED))
5150 + mask_IO_APIC_irq(irq);
5155 + * Level triggered interrupts can just be masked,
5156 + * and shutting down and starting up the interrupt
5157 + * is the same as enabling and disabling them -- except
5158 + * with a startup need to return a "was pending" value.
5160 + * Level triggered interrupts are special because we
5161 + * do not touch any IO-APIC register while handling
5162 + * them. We ack the APIC in the end-IRQ handler, not
5163 + * in the start-IRQ-handler. Protection against reentrance
5164 + * from the same interrupt is still provided, both by the
5165 + * generic IRQ layer and by the fact that an unacked local
5166 + * APIC does not accept IRQs.
5168 +static unsigned int startup_level_ioapic_irq (unsigned int irq)
5170 + unmask_IO_APIC_irq(irq);
5172 + return 0; /* don't check for pending */
5175 +static void end_level_ioapic_irq (unsigned int irq)
5182 + * It appears there is an erratum which affects at least version 0x11
5183 + * of I/O APIC (that's the 82093AA and cores integrated into various
5184 + * chipsets). Under certain conditions a level-triggered interrupt is
5185 + * erroneously delivered as edge-triggered one but the respective IRR
5186 + * bit gets set nevertheless. As a result the I/O unit expects an EOI
5187 + * message but it will never arrive and further interrupts are blocked
5188 + * from the source. The exact reason is so far unknown, but the
5189 + * phenomenon was observed when two consecutive interrupt requests
5190 + * from a given source get delivered to the same CPU and the source is
5191 + * temporarily disabled in between.
5193 + * A workaround is to simulate an EOI message manually. We achieve it
5194 + * by setting the trigger mode to edge and then to level when the edge
5195 + * trigger mode gets detected in the TMR of a local APIC for a
5196 + * level-triggered interrupt. We mask the source for the time of the
5197 + * operation to prevent an edge-triggered interrupt escaping meanwhile.
5198 + * The idea is from Manfred Spraul. --macro
5200 + i = IO_APIC_VECTOR(irq);
5202 + v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
5206 + if (!(v & (1 << (i & 0x1f)))) {
5207 + atomic_inc(&irq_mis_count);
5208 + spin_lock(&ioapic_lock);
5209 + __mask_and_edge_IO_APIC_irq(irq);
5210 + __unmask_and_level_IO_APIC_irq(irq);
5211 + spin_unlock(&ioapic_lock);
5215 +#ifdef CONFIG_PCI_MSI
5216 +static unsigned int startup_edge_ioapic_vector(unsigned int vector)
5218 + int irq = vector_to_irq(vector);
5220 + return startup_edge_ioapic_irq(irq);
5223 +static void ack_edge_ioapic_vector(unsigned int vector)
5225 + int irq = vector_to_irq(vector);
5227 + move_native_irq(vector);
5228 + ack_edge_ioapic_irq(irq);
5231 +static unsigned int startup_level_ioapic_vector (unsigned int vector)
5233 + int irq = vector_to_irq(vector);
5235 + return startup_level_ioapic_irq (irq);
5238 +static void end_level_ioapic_vector (unsigned int vector)
5240 + int irq = vector_to_irq(vector);
5242 + move_native_irq(vector);
5243 + end_level_ioapic_irq(irq);
5246 +static void mask_IO_APIC_vector (unsigned int vector)
5248 + int irq = vector_to_irq(vector);
5250 + mask_IO_APIC_irq(irq);
5253 +static void unmask_IO_APIC_vector (unsigned int vector)
5255 + int irq = vector_to_irq(vector);
5257 + unmask_IO_APIC_irq(irq);
5261 +static void set_ioapic_affinity_vector (unsigned int vector,
5262 + cpumask_t cpu_mask)
5264 + int irq = vector_to_irq(vector);
5266 + set_native_irq_info(vector, cpu_mask);
5267 + set_ioapic_affinity_irq(irq, cpu_mask);
5272 +static int ioapic_retrigger(unsigned int irq)
5274 + send_IPI_self(IO_APIC_VECTOR(irq));
5280 + * Level and edge triggered IO-APIC interrupts need different handling,
5281 + * so we use two separate IRQ descriptors. Edge triggered IRQs can be
5282 + * handled with the level-triggered descriptor, but that one has slightly
5283 + * more overhead. Level-triggered interrupts cannot be handled with the
5284 + * edge-triggered handler, without risking IRQ storms and other ugly
5287 +static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
5288 + .typename = "IO-APIC-edge",
5289 + .startup = startup_edge_ioapic,
5290 + .shutdown = shutdown_edge_ioapic,
5291 + .enable = enable_edge_ioapic,
5292 + .disable = disable_edge_ioapic,
5293 + .ack = ack_edge_ioapic,
5294 + .end = end_edge_ioapic,
5296 + .set_affinity = set_ioapic_affinity,
5298 + .retrigger = ioapic_retrigger,
5301 +static struct hw_interrupt_type ioapic_level_type __read_mostly = {
5302 + .typename = "IO-APIC-level",
5303 + .startup = startup_level_ioapic,
5304 + .shutdown = shutdown_level_ioapic,
5305 + .enable = enable_level_ioapic,
5306 + .disable = disable_level_ioapic,
5307 + .ack = mask_and_ack_level_ioapic,
5308 + .end = end_level_ioapic,
5310 + .set_affinity = set_ioapic_affinity,
5312 + .retrigger = ioapic_retrigger,
5314 +#endif /* !CONFIG_XEN */
5316 +static inline void init_IO_APIC_traps(void)
5321 + * NOTE! The local APIC isn't very good at handling
5322 + * multiple interrupts at the same interrupt level.
5323 + * As the interrupt level is determined by taking the
5324 + * vector number and shifting that right by 4, we
5325 + * want to spread these out a bit so that they don't
5326 + * all fall in the same interrupt level.
5328 + * Also, we've got to be careful not to trash gate
5329 + * 0x80, because int 0x80 is hm, kind of importantish. ;)
5331 + for (irq = 0; irq < NR_IRQS ; irq++) {
5333 + if (use_pci_vector()) {
5334 + if (!platform_legacy_irq(tmp))
5335 + if ((tmp = vector_to_irq(tmp)) == -1)
5338 + if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
5340 + * Hmm.. We don't have an entry for this,
5341 + * so default to an old-fashioned 8259
5342 + * interrupt if we can..
5345 + make_8259A_irq(irq);
5348 + /* Strange. Oh, well.. */
5349 + irq_desc[irq].chip = &no_irq_type;
5356 +static void enable_lapic_irq (unsigned int irq)
5360 + v = apic_read(APIC_LVT0);
5361 + apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
5364 +static void disable_lapic_irq (unsigned int irq)
5368 + v = apic_read(APIC_LVT0);
5369 + apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
5372 +static void ack_lapic_irq (unsigned int irq)
5377 +static void end_lapic_irq (unsigned int i) { /* nothing */ }
5379 +static struct hw_interrupt_type lapic_irq_type __read_mostly = {
5380 + .typename = "local-APIC-edge",
5381 + .startup = NULL, /* startup_irq() not used for IRQ0 */
5382 + .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
5383 + .enable = enable_lapic_irq,
5384 + .disable = disable_lapic_irq,
5385 + .ack = ack_lapic_irq,
5386 + .end = end_lapic_irq
5389 +static void setup_nmi (void)
5392 + * Dirty trick to enable the NMI watchdog ...
5393 + * We put the 8259A master into AEOI mode and
5394 + * unmask on all local APICs LVT0 as NMI.
5396 + * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
5397 + * is from Maciej W. Rozycki - so we do not have to EOI from
5398 + * the NMI handler or the timer interrupt.
5400 + apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
5402 + on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
5404 + apic_printk(APIC_VERBOSE, " done.\n");
5408 + * This looks a bit hackish but it's about the only one way of sending
5409 + * a few INTA cycles to 8259As and any associated glue logic. ICR does
5410 + * not support the ExtINT mode, unfortunately. We need to send these
5411 + * cycles as some i82489DX-based boards have glue logic that keeps the
5412 + * 8259A interrupt line asserted until INTA. --macro
5414 +static inline void unlock_ExtINT_logic(void)
5417 + struct IO_APIC_route_entry entry0, entry1;
5418 + unsigned char save_control, save_freq_select;
5419 + unsigned long flags;
5421 + pin = find_isa_irq_pin(8, mp_INT);
5422 + apic = find_isa_irq_apic(8, mp_INT);
5426 + spin_lock_irqsave(&ioapic_lock, flags);
5427 + *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
5428 + *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
5429 + spin_unlock_irqrestore(&ioapic_lock, flags);
5430 + clear_IO_APIC_pin(apic, pin);
5432 + memset(&entry1, 0, sizeof(entry1));
5434 + entry1.dest_mode = 0; /* physical delivery */
5435 + entry1.mask = 0; /* unmask IRQ now */
5436 + entry1.dest.physical.physical_dest = hard_smp_processor_id();
5437 + entry1.delivery_mode = dest_ExtINT;
5438 + entry1.polarity = entry0.polarity;
5439 + entry1.trigger = 0;
5440 + entry1.vector = 0;
5442 + spin_lock_irqsave(&ioapic_lock, flags);
5443 + io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
5444 + io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
5445 + spin_unlock_irqrestore(&ioapic_lock, flags);
5447 + save_control = CMOS_READ(RTC_CONTROL);
5448 + save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
5449 + CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
5451 + CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
5456 + if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
5460 + CMOS_WRITE(save_control, RTC_CONTROL);
5461 + CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
5462 + clear_IO_APIC_pin(apic, pin);
5464 + spin_lock_irqsave(&ioapic_lock, flags);
5465 + io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
5466 + io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
5467 + spin_unlock_irqrestore(&ioapic_lock, flags);
5470 +int timer_uses_ioapic_pin_0;
5473 + * This code may look a bit paranoid, but it's supposed to cooperate with
5474 + * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
5475 + * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
5476 + * fanatically on his truly buggy board.
5478 +static inline void check_timer(void)
5480 + int apic1, pin1, apic2, pin2;
5484 + * get/set the timer IRQ vector:
5486 + disable_8259A_irq(0);
5487 + vector = assign_irq_vector(0);
5488 + set_intr_gate(vector, interrupt[0]);
5491 + * Subtle, code in do_timer_interrupt() expects an AEOI
5492 + * mode for the 8259A whenever interrupts are routed
5493 + * through I/O APICs. Also IRQ0 has to be enabled in
5494 + * the 8259A which implies the virtual wire has to be
5495 + * disabled in the local APIC.
5497 + apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
5500 + if (timer_over_8254 > 0)
5501 + enable_8259A_irq(0);
5503 + pin1 = find_isa_irq_pin(0, mp_INT);
5504 + apic1 = find_isa_irq_apic(0, mp_INT);
5505 + pin2 = ioapic_i8259.pin;
5506 + apic2 = ioapic_i8259.apic;
5509 + timer_uses_ioapic_pin_0 = 1;
5511 + printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
5512 + vector, apic1, pin1, apic2, pin2);
5516 + * Ok, does IRQ0 through the IOAPIC work?
5518 + unmask_IO_APIC_irq(0);
5519 + if (timer_irq_works()) {
5520 + if (nmi_watchdog == NMI_IO_APIC) {
5521 + disable_8259A_irq(0);
5523 + enable_8259A_irq(0);
5525 + if (disable_timer_pin_1 > 0)
5526 + clear_IO_APIC_pin(0, pin1);
5529 + clear_IO_APIC_pin(apic1, pin1);
5530 + printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
5534 + printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
5536 + printk("\n..... (found pin %d) ...", pin2);
5538 + * legacy devices should be connected to IO APIC #0
5540 + setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
5541 + if (timer_irq_works()) {
5542 + printk("works.\n");
5544 + replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
5546 + add_pin_to_irq(0, apic2, pin2);
5547 + if (nmi_watchdog == NMI_IO_APIC) {
5553 + * Cleanup, just in case ...
5555 + clear_IO_APIC_pin(apic2, pin2);
5557 + printk(" failed.\n");
5559 + if (nmi_watchdog == NMI_IO_APIC) {
5560 + printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
5564 + printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
5566 + disable_8259A_irq(0);
5567 + irq_desc[0].chip = &lapic_irq_type;
5568 + apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
5569 + enable_8259A_irq(0);
5571 + if (timer_irq_works()) {
5572 + printk(" works.\n");
5575 + apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
5576 + printk(" failed.\n");
5578 + printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
5582 + make_8259A_irq(0);
5583 + apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
5585 + unlock_ExtINT_logic();
5587 + if (timer_irq_works()) {
5588 + printk(" works.\n");
5591 + printk(" failed :(.\n");
5592 + panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
5593 + "report. Then try booting with the 'noapic' option");
5596 +int timer_uses_ioapic_pin_0 = 0;
5597 +#define check_timer() ((void)0)
5602 + * IRQ's that are handled by the PIC in the MPS IOAPIC case.
5603 + * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
5604 + * Linux doesn't really care, as it's not actually used
5605 + * for any interrupt handling anyway.
5607 +#define PIC_IRQS (1 << PIC_CASCADE_IR)
5609 +void __init setup_IO_APIC(void)
5614 + io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
5616 + io_apic_irqs = ~PIC_IRQS;
5618 + printk("ENABLING IO-APIC IRQs\n");
5621 + * Set up IO-APIC IRQ routing.
5624 + setup_ioapic_ids_from_mpc();
5628 + setup_IO_APIC_irqs();
5629 + init_IO_APIC_traps();
5635 +static int __init setup_disable_8254_timer(char *s)
5637 + timer_over_8254 = -1;
5640 +static int __init setup_enable_8254_timer(char *s)
5642 + timer_over_8254 = 2;
5646 +__setup("disable_8254_timer", setup_disable_8254_timer);
5647 +__setup("enable_8254_timer", setup_enable_8254_timer);
5650 + * Called after all the initialization is done. If we didnt find any
5651 + * APIC bugs then we can allow the modify fast path
5654 +static int __init io_apic_bug_finalize(void)
5656 + if(sis_apic_bug == -1)
5658 + if (is_initial_xendomain()) {
5659 + struct xen_platform_op op = { .cmd = XENPF_platform_quirk };
5660 + op.u.platform_quirk.quirk_id = sis_apic_bug ?
5661 + QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
5662 + VOID(HYPERVISOR_platform_op(&op));
5667 +late_initcall(io_apic_bug_finalize);
5669 +struct sysfs_ioapic_data {
5670 + struct sys_device dev;
5671 + struct IO_APIC_route_entry entry[0];
5673 +static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
5675 +static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
5677 + struct IO_APIC_route_entry *entry;
5678 + struct sysfs_ioapic_data *data;
5679 + unsigned long flags;
5682 + data = container_of(dev, struct sysfs_ioapic_data, dev);
5683 + entry = data->entry;
5684 + spin_lock_irqsave(&ioapic_lock, flags);
5685 + for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
5686 + *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
5687 + *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
5689 + spin_unlock_irqrestore(&ioapic_lock, flags);
5694 +static int ioapic_resume(struct sys_device *dev)
5696 + struct IO_APIC_route_entry *entry;
5697 + struct sysfs_ioapic_data *data;
5698 + unsigned long flags;
5699 + union IO_APIC_reg_00 reg_00;
5702 + data = container_of(dev, struct sysfs_ioapic_data, dev);
5703 + entry = data->entry;
5705 + spin_lock_irqsave(&ioapic_lock, flags);
5706 + reg_00.raw = io_apic_read(dev->id, 0);
5707 + if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
5708 + reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
5709 + io_apic_write(dev->id, 0, reg_00.raw);
5711 + for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
5712 + io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
5713 + io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
5715 + spin_unlock_irqrestore(&ioapic_lock, flags);
5720 +static struct sysdev_class ioapic_sysdev_class = {
5721 + set_kset_name("ioapic"),
5723 + .suspend = ioapic_suspend,
5724 + .resume = ioapic_resume,
5728 +static int __init ioapic_init_sysfs(void)
5730 + struct sys_device * dev;
5731 + int i, size, error = 0;
5733 + error = sysdev_class_register(&ioapic_sysdev_class);
5737 + for (i = 0; i < nr_ioapics; i++ ) {
5738 + size = sizeof(struct sys_device) + nr_ioapic_registers[i]
5739 + * sizeof(struct IO_APIC_route_entry);
5740 + mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
5741 + if (!mp_ioapic_data[i]) {
5742 + printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
5745 + memset(mp_ioapic_data[i], 0, size);
5746 + dev = &mp_ioapic_data[i]->dev;
5748 + dev->cls = &ioapic_sysdev_class;
5749 + error = sysdev_register(dev);
5751 + kfree(mp_ioapic_data[i]);
5752 + mp_ioapic_data[i] = NULL;
5753 + printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
5761 +device_initcall(ioapic_init_sysfs);
5763 +/* --------------------------------------------------------------------------
5764 + ACPI-based IOAPIC Configuration
5765 + -------------------------------------------------------------------------- */
5769 +int __init io_apic_get_unique_id (int ioapic, int apic_id)
5772 + union IO_APIC_reg_00 reg_00;
5773 + static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
5774 + physid_mask_t tmp;
5775 + unsigned long flags;
5779 + * The P4 platform supports up to 256 APIC IDs on two separate APIC
5780 + * buses (one for LAPICs, one for IOAPICs), where predecessors only
5781 + * supports up to 16 on one shared APIC bus.
5783 + * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
5784 + * advantage of new APIC bus architecture.
5787 + if (physids_empty(apic_id_map))
5788 + apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
5790 + spin_lock_irqsave(&ioapic_lock, flags);
5791 + reg_00.raw = io_apic_read(ioapic, 0);
5792 + spin_unlock_irqrestore(&ioapic_lock, flags);
5794 + if (apic_id >= get_physical_broadcast()) {
5795 + printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
5796 + "%d\n", ioapic, apic_id, reg_00.bits.ID);
5797 + apic_id = reg_00.bits.ID;
5801 + * Every APIC in a system must have a unique ID or we get lots of nice
5802 + * 'stuck on smp_invalidate_needed IPI wait' messages.
5804 + if (check_apicid_used(apic_id_map, apic_id)) {
5806 + for (i = 0; i < get_physical_broadcast(); i++) {
5807 + if (!check_apicid_used(apic_id_map, i))
5811 + if (i == get_physical_broadcast())
5812 + panic("Max apic_id exceeded!\n");
5814 + printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
5815 + "trying %d\n", ioapic, apic_id, i);
5820 + tmp = apicid_to_cpu_present(apic_id);
5821 + physids_or(apic_id_map, apic_id_map, tmp);
5823 + if (reg_00.bits.ID != apic_id) {
5824 + reg_00.bits.ID = apic_id;
5826 + spin_lock_irqsave(&ioapic_lock, flags);
5827 + io_apic_write(ioapic, 0, reg_00.raw);
5828 + reg_00.raw = io_apic_read(ioapic, 0);
5829 + spin_unlock_irqrestore(&ioapic_lock, flags);
5831 + /* Sanity check */
5832 + if (reg_00.bits.ID != apic_id) {
5833 + printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
5838 + apic_printk(APIC_VERBOSE, KERN_INFO
5839 + "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
5840 +#endif /* !CONFIG_XEN */
5846 +int __init io_apic_get_version (int ioapic)
5848 + union IO_APIC_reg_01 reg_01;
5849 + unsigned long flags;
5851 + spin_lock_irqsave(&ioapic_lock, flags);
5852 + reg_01.raw = io_apic_read(ioapic, 1);
5853 + spin_unlock_irqrestore(&ioapic_lock, flags);
5855 + return reg_01.bits.version;
5859 +int __init io_apic_get_redir_entries (int ioapic)
5861 + union IO_APIC_reg_01 reg_01;
5862 + unsigned long flags;
5864 + spin_lock_irqsave(&ioapic_lock, flags);
5865 + reg_01.raw = io_apic_read(ioapic, 1);
5866 + spin_unlock_irqrestore(&ioapic_lock, flags);
5868 + return reg_01.bits.entries;
5872 +int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
5874 + struct IO_APIC_route_entry entry;
5875 + unsigned long flags;
5877 + if (!IO_APIC_IRQ(irq)) {
5878 + printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
5884 + * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
5885 + * Note that we mask (disable) IRQs now -- these get enabled when the
5886 + * corresponding device driver registers for this IRQ.
5889 + memset(&entry,0,sizeof(entry));
5891 + entry.delivery_mode = INT_DELIVERY_MODE;
5892 + entry.dest_mode = INT_DEST_MODE;
5893 + entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
5894 + entry.trigger = edge_level;
5895 + entry.polarity = active_high_low;
5899 + * IRQs < 16 are already in the irq_2_pin[] map
5902 + add_pin_to_irq(irq, ioapic, pin);
5904 + entry.vector = assign_irq_vector(irq);
5906 + apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
5907 + "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
5908 + mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
5909 + edge_level, active_high_low);
5911 + ioapic_register_intr(irq, entry.vector, edge_level);
5913 + if (!ioapic && (irq < 16))
5914 + disable_8259A_irq(irq);
5916 + spin_lock_irqsave(&ioapic_lock, flags);
5917 + io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
5918 + io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
5919 + set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
5920 + spin_unlock_irqrestore(&ioapic_lock, flags);
5925 +#endif /* CONFIG_ACPI */
5926 Index: head-2008-11-25/arch/x86/kernel/ioport_32-xen.c
5927 ===================================================================
5928 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5929 +++ head-2008-11-25/arch/x86/kernel/ioport_32-xen.c 2008-01-28 12:24:19.000000000 +0100
5932 + * linux/arch/i386/kernel/ioport.c
5934 + * This contains the io-permission bitmap code - written by obz, with changes
5938 +#include <linux/sched.h>
5939 +#include <linux/kernel.h>
5940 +#include <linux/capability.h>
5941 +#include <linux/errno.h>
5942 +#include <linux/types.h>
5943 +#include <linux/ioport.h>
5944 +#include <linux/smp.h>
5945 +#include <linux/smp_lock.h>
5946 +#include <linux/stddef.h>
5947 +#include <linux/slab.h>
5948 +#include <linux/thread_info.h>
5949 +#include <xen/interface/physdev.h>
5951 +/* Set EXTENT bits starting at BASE in BITMAP to value TURN_ON. */
5952 +static void set_bitmap(unsigned long *bitmap, unsigned int base, unsigned int extent, int new_value)
5954 + unsigned long mask;
5955 + unsigned long *bitmap_base = bitmap + (base / BITS_PER_LONG);
5956 + unsigned int low_index = base & (BITS_PER_LONG-1);
5957 + int length = low_index + extent;
5959 + if (low_index != 0) {
5960 + mask = (~0UL << low_index);
5961 + if (length < BITS_PER_LONG)
5962 + mask &= ~(~0UL << length);
5964 + *bitmap_base++ |= mask;
5966 + *bitmap_base++ &= ~mask;
5967 + length -= BITS_PER_LONG;
5970 + mask = (new_value ? ~0UL : 0UL);
5971 + while (length >= BITS_PER_LONG) {
5972 + *bitmap_base++ = mask;
5973 + length -= BITS_PER_LONG;
5977 + mask = ~(~0UL << length);
5979 + *bitmap_base++ |= mask;
5981 + *bitmap_base++ &= ~mask;
5987 + * this changes the io permissions bitmap in the current task.
5989 +asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on)
5991 + struct thread_struct * t = ¤t->thread;
5992 + unsigned long *bitmap;
5993 + struct physdev_set_iobitmap set_iobitmap;
5995 + if ((from + num <= from) || (from + num > IO_BITMAP_BITS))
5997 + if (turn_on && !capable(CAP_SYS_RAWIO))
6001 + * If it's the first ioperm() call in this thread's lifetime, set the
6002 + * IO bitmap up. ioperm() is much less timing critical than clone(),
6003 + * this is why we delay this operation until now:
6005 + if (!t->io_bitmap_ptr) {
6006 + bitmap = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
6010 + memset(bitmap, 0xff, IO_BITMAP_BYTES);
6011 + t->io_bitmap_ptr = bitmap;
6012 + set_thread_flag(TIF_IO_BITMAP);
6014 + set_xen_guest_handle(set_iobitmap.bitmap, (char *)bitmap);
6015 + set_iobitmap.nr_ports = IO_BITMAP_BITS;
6016 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap,
6020 + set_bitmap(t->io_bitmap_ptr, from, num, !turn_on);
6026 + * sys_iopl has to be used when you want to access the IO ports
6027 + * beyond the 0x3ff range: to get the full 65536 ports bitmapped
6028 + * you'd need 8kB of bitmaps/process, which is a bit excessive.
6030 + * Here we just change the eflags value on the stack: we allow
6031 + * only the super-user to do it. This depends on the stack-layout
6032 + * on system-call entry - see also fork() and the signal handling
6036 +asmlinkage long sys_iopl(unsigned long unused)
6038 + volatile struct pt_regs * regs = (struct pt_regs *) &unused;
6039 + unsigned int level = regs->ebx;
6040 + struct thread_struct *t = ¤t->thread;
6041 + unsigned int old = (t->iopl >> 12) & 3;
6045 + /* Trying to gain more privileges? */
6046 + if (level > old) {
6047 + if (!capable(CAP_SYS_RAWIO))
6050 + t->iopl = level << 12;
6051 + set_iopl_mask(t->iopl);
6054 Index: head-2008-11-25/arch/x86/kernel/irq_32-xen.c
6055 ===================================================================
6056 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6057 +++ head-2008-11-25/arch/x86/kernel/irq_32-xen.c 2008-10-29 09:55:56.000000000 +0100
6060 + * linux/arch/i386/kernel/irq.c
6062 + * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
6064 + * This file contains the lowest level x86-specific interrupt
6065 + * entry, irq-stacks and irq statistics code. All the remaining
6066 + * irq logic is done by the generic kernel/irq/ code and
6067 + * by the x86-specific irq controller code. (e.g. i8259.c and
6071 +#include <asm/uaccess.h>
6072 +#include <linux/module.h>
6073 +#include <linux/seq_file.h>
6074 +#include <linux/interrupt.h>
6075 +#include <linux/kernel_stat.h>
6076 +#include <linux/notifier.h>
6077 +#include <linux/cpu.h>
6078 +#include <linux/delay.h>
6080 +DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
6081 +EXPORT_PER_CPU_SYMBOL(irq_stat);
6083 +#ifndef CONFIG_X86_LOCAL_APIC
6085 + * 'what should we do if we get a hw irq event on an illegal vector'.
6086 + * each architecture has to answer this themselves.
6088 +void ack_bad_irq(unsigned int irq)
6090 + printk("unexpected IRQ trap at vector %02x\n", irq);
6094 +#ifdef CONFIG_4KSTACKS
6096 + * per-CPU IRQ handling contexts (thread information and stack)
6099 + struct thread_info tinfo;
6100 + u32 stack[THREAD_SIZE/sizeof(u32)];
6103 +static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
6104 +static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
6108 + * do_IRQ handles all normal device IRQ's (the special
6109 + * SMP cross-CPU interrupts have their own specific
6112 +fastcall unsigned int do_IRQ(struct pt_regs *regs)
6114 + /* high bit used in ret_from_ code */
6115 + int irq = ~regs->orig_eax;
6116 +#ifdef CONFIG_4KSTACKS
6117 + union irq_ctx *curctx, *irqctx;
6121 + if (unlikely((unsigned)irq >= NR_IRQS)) {
6122 + printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
6123 + __FUNCTION__, irq);
6128 +#ifdef CONFIG_DEBUG_STACKOVERFLOW
6129 + /* Debugging check for stack overflow: is there less than 1KB free? */
6133 + __asm__ __volatile__("andl %%esp,%0" :
6134 + "=r" (esp) : "0" (THREAD_SIZE - 1));
6135 + if (unlikely(esp < (sizeof(struct thread_info) + STACK_WARN))) {
6136 + printk("do_IRQ: stack overflow: %ld\n",
6137 + esp - sizeof(struct thread_info));
6143 +#ifdef CONFIG_4KSTACKS
6145 + curctx = (union irq_ctx *) current_thread_info();
6146 + irqctx = hardirq_ctx[smp_processor_id()];
6149 + * this is where we switch to the IRQ stack. However, if we are
6150 + * already using the IRQ stack (because we interrupted a hardirq
6151 + * handler) we can't do that and just have to keep using the
6152 + * current stack (which is the irq stack already after all)
6154 + if (curctx != irqctx) {
6155 + int arg1, arg2, ebx;
6157 + /* build the stack frame on the IRQ stack */
6158 + isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
6159 + irqctx->tinfo.task = curctx->tinfo.task;
6160 + irqctx->tinfo.previous_esp = current_stack_pointer;
6163 + * Copy the softirq bits in preempt_count so that the
6164 + * softirq checks work in the hardirq context.
6166 + irqctx->tinfo.preempt_count =
6167 + (irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
6168 + (curctx->tinfo.preempt_count & SOFTIRQ_MASK);
6171 + " xchgl %%ebx,%%esp \n"
6172 + " call __do_IRQ \n"
6173 + " movl %%ebx,%%esp \n"
6174 + : "=a" (arg1), "=d" (arg2), "=b" (ebx)
6175 + : "0" (irq), "1" (regs), "2" (isp)
6176 + : "memory", "cc", "ecx"
6180 + __do_IRQ(irq, regs);
6187 +#ifdef CONFIG_4KSTACKS
6190 + * These should really be __section__(".bss.page_aligned") as well, but
6191 + * gcc's 3.0 and earlier don't handle that correctly.
6193 +static char softirq_stack[NR_CPUS * THREAD_SIZE]
6194 + __attribute__((__aligned__(THREAD_SIZE)));
6196 +static char hardirq_stack[NR_CPUS * THREAD_SIZE]
6197 + __attribute__((__aligned__(THREAD_SIZE)));
6200 + * allocate per-cpu stacks for hardirq and for softirq processing
6202 +void irq_ctx_init(int cpu)
6204 + union irq_ctx *irqctx;
6206 + if (hardirq_ctx[cpu])
6209 + irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
6210 + irqctx->tinfo.task = NULL;
6211 + irqctx->tinfo.exec_domain = NULL;
6212 + irqctx->tinfo.cpu = cpu;
6213 + irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
6214 + irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
6216 + hardirq_ctx[cpu] = irqctx;
6218 + irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
6219 + irqctx->tinfo.task = NULL;
6220 + irqctx->tinfo.exec_domain = NULL;
6221 + irqctx->tinfo.cpu = cpu;
6222 + irqctx->tinfo.preempt_count = 0;
6223 + irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
6225 + softirq_ctx[cpu] = irqctx;
6227 + printk("CPU %u irqstacks, hard=%p soft=%p\n",
6228 + cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
6231 +void irq_ctx_exit(int cpu)
6233 + hardirq_ctx[cpu] = NULL;
6236 +extern asmlinkage void __do_softirq(void);
6238 +asmlinkage void do_softirq(void)
6240 + unsigned long flags;
6241 + struct thread_info *curctx;
6242 + union irq_ctx *irqctx;
6245 + if (in_interrupt())
6248 + local_irq_save(flags);
6250 + if (local_softirq_pending()) {
6251 + curctx = current_thread_info();
6252 + irqctx = softirq_ctx[smp_processor_id()];
6253 + irqctx->tinfo.task = curctx->task;
6254 + irqctx->tinfo.previous_esp = current_stack_pointer;
6256 + /* build the stack frame on the softirq stack */
6257 + isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
6260 + " xchgl %%ebx,%%esp \n"
6261 + " call __do_softirq \n"
6262 + " movl %%ebx,%%esp \n"
6265 + : "memory", "cc", "edx", "ecx", "eax"
6268 + * Shouldnt happen, we returned above if in_interrupt():
6270 + WARN_ON_ONCE(softirq_count());
6273 + local_irq_restore(flags);
6276 +EXPORT_SYMBOL(do_softirq);
6280 + * Interrupt statistics:
6283 +atomic_t irq_err_count;
6286 + * /proc/interrupts printing:
6289 +int show_interrupts(struct seq_file *p, void *v)
6291 + int i = *(loff_t *) v, j;
6292 + struct irqaction * action;
6293 + unsigned long flags;
6296 + seq_printf(p, " ");
6297 + for_each_online_cpu(j)
6298 + seq_printf(p, "CPU%-8d",j);
6299 + seq_putc(p, '\n');
6302 + if (i < NR_IRQS) {
6303 + spin_lock_irqsave(&irq_desc[i].lock, flags);
6304 + action = irq_desc[i].action;
6307 + seq_printf(p, "%3d: ",i);
6309 + seq_printf(p, "%10u ", kstat_irqs(i));
6311 + for_each_online_cpu(j)
6312 + seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
6314 + seq_printf(p, " %14s", irq_desc[i].chip->typename);
6315 + seq_printf(p, " %s", action->name);
6317 + for (action=action->next; action; action = action->next)
6318 + seq_printf(p, ", %s", action->name);
6320 + seq_putc(p, '\n');
6322 + spin_unlock_irqrestore(&irq_desc[i].lock, flags);
6323 + } else if (i == NR_IRQS) {
6324 + seq_printf(p, "NMI: ");
6325 + for_each_online_cpu(j)
6326 + seq_printf(p, "%10u ", nmi_count(j));
6327 + seq_putc(p, '\n');
6328 +#ifdef CONFIG_X86_LOCAL_APIC
6329 + seq_printf(p, "LOC: ");
6330 + for_each_online_cpu(j)
6331 + seq_printf(p, "%10u ",
6332 + per_cpu(irq_stat,j).apic_timer_irqs);
6333 + seq_putc(p, '\n');
6335 + seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
6336 +#if defined(CONFIG_X86_IO_APIC)
6337 + seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
6343 +#ifdef CONFIG_HOTPLUG_CPU
6345 +void fixup_irqs(cpumask_t map)
6348 + static int warned;
6350 + for (irq = 0; irq < NR_IRQS; irq++) {
6355 + cpus_and(mask, irq_desc[irq].affinity, map);
6356 + if (any_online_cpu(mask) == NR_CPUS) {
6357 + /*printk("Breaking affinity for irq %i\n", irq);*/
6360 + if (irq_desc[irq].chip->set_affinity)
6361 + irq_desc[irq].chip->set_affinity(irq, mask);
6362 + else if (irq_desc[irq].action && !(warned++))
6363 + printk("Cannot set affinity for irq %i\n", irq);
6368 + /* Ingo Molnar says: "after the IO-APIC masks have been redirected
6369 + [note the nop - the interrupt-enable boundary on x86 is two
6370 + instructions from sti] - to flush out pending hardirqs and
6371 + IPIs. After this point nothing is supposed to reach this CPU." */
6372 + __asm__ __volatile__("sti; nop; cli");
6375 + /* That doesn't seem sufficient. Give it 1ms. */
6376 + local_irq_enable();
6378 + local_irq_disable();
6383 Index: head-2008-11-25/arch/x86/kernel/ldt_32-xen.c
6384 ===================================================================
6385 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6386 +++ head-2008-11-25/arch/x86/kernel/ldt_32-xen.c 2007-06-12 13:12:48.000000000 +0200
6389 + * linux/kernel/ldt.c
6391 + * Copyright (C) 1992 Krishna Balasubramanian and Linus Torvalds
6392 + * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
6395 +#include <linux/errno.h>
6396 +#include <linux/sched.h>
6397 +#include <linux/string.h>
6398 +#include <linux/mm.h>
6399 +#include <linux/smp.h>
6400 +#include <linux/smp_lock.h>
6401 +#include <linux/vmalloc.h>
6402 +#include <linux/slab.h>
6404 +#include <asm/uaccess.h>
6405 +#include <asm/system.h>
6406 +#include <asm/ldt.h>
6407 +#include <asm/desc.h>
6408 +#include <asm/mmu_context.h>
6410 +#ifdef CONFIG_SMP /* avoids "defined but not used" warnig */
6411 +static void flush_ldt(void *null)
6413 + if (current->active_mm)
6414 + load_LDT(¤t->active_mm->context);
6418 +static int alloc_ldt(mm_context_t *pc, int mincount, int reload)
6424 + if (mincount <= pc->size)
6426 + oldsize = pc->size;
6427 + mincount = (mincount+511)&(~511);
6428 + if (mincount*LDT_ENTRY_SIZE > PAGE_SIZE)
6429 + newldt = vmalloc(mincount*LDT_ENTRY_SIZE);
6431 + newldt = kmalloc(mincount*LDT_ENTRY_SIZE, GFP_KERNEL);
6437 + memcpy(newldt, pc->ldt, oldsize*LDT_ENTRY_SIZE);
6439 + memset(newldt+oldsize*LDT_ENTRY_SIZE, 0, (mincount-oldsize)*LDT_ENTRY_SIZE);
6442 + pc->size = mincount;
6448 + preempt_disable();
6450 + make_pages_readonly(
6452 + (pc->size * LDT_ENTRY_SIZE) / PAGE_SIZE,
6453 + XENFEAT_writable_descriptor_tables);
6456 + mask = cpumask_of_cpu(smp_processor_id());
6457 + if (!cpus_equal(current->mm->cpu_vm_mask, mask))
6458 + smp_call_function(flush_ldt, NULL, 1, 1);
6463 + make_pages_writable(
6465 + (oldsize * LDT_ENTRY_SIZE) / PAGE_SIZE,
6466 + XENFEAT_writable_descriptor_tables);
6467 + if (oldsize*LDT_ENTRY_SIZE > PAGE_SIZE)
6475 +static inline int copy_ldt(mm_context_t *new, mm_context_t *old)
6477 + int err = alloc_ldt(new, old->size, 0);
6480 + memcpy(new->ldt, old->ldt, old->size*LDT_ENTRY_SIZE);
6481 + make_pages_readonly(
6483 + (new->size * LDT_ENTRY_SIZE) / PAGE_SIZE,
6484 + XENFEAT_writable_descriptor_tables);
6489 + * we do not have to muck with descriptors here, that is
6490 + * done in switch_mm() as needed.
6492 +int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
6494 + struct mm_struct * old_mm;
6497 + init_MUTEX(&mm->context.sem);
6498 + mm->context.size = 0;
6499 + mm->context.has_foreign_mappings = 0;
6500 + old_mm = current->mm;
6501 + if (old_mm && old_mm->context.size > 0) {
6502 + down(&old_mm->context.sem);
6503 + retval = copy_ldt(&mm->context, &old_mm->context);
6504 + up(&old_mm->context.sem);
6510 + * No need to lock the MM as we are the last user
6512 +void destroy_context(struct mm_struct *mm)
6514 + if (mm->context.size) {
6515 + if (mm == current->active_mm)
6517 + make_pages_writable(
6519 + (mm->context.size * LDT_ENTRY_SIZE) / PAGE_SIZE,
6520 + XENFEAT_writable_descriptor_tables);
6521 + if (mm->context.size*LDT_ENTRY_SIZE > PAGE_SIZE)
6522 + vfree(mm->context.ldt);
6524 + kfree(mm->context.ldt);
6525 + mm->context.size = 0;
6529 +static int read_ldt(void __user * ptr, unsigned long bytecount)
6532 + unsigned long size;
6533 + struct mm_struct * mm = current->mm;
6535 + if (!mm->context.size)
6537 + if (bytecount > LDT_ENTRY_SIZE*LDT_ENTRIES)
6538 + bytecount = LDT_ENTRY_SIZE*LDT_ENTRIES;
6540 + down(&mm->context.sem);
6541 + size = mm->context.size*LDT_ENTRY_SIZE;
6542 + if (size > bytecount)
6546 + if (copy_to_user(ptr, mm->context.ldt, size))
6548 + up(&mm->context.sem);
6550 + goto error_return;
6551 + if (size != bytecount) {
6552 + /* zero-fill the rest */
6553 + if (clear_user(ptr+size, bytecount-size) != 0) {
6555 + goto error_return;
6563 +static int read_default_ldt(void __user * ptr, unsigned long bytecount)
6566 + unsigned long size;
6570 + address = &default_ldt[0];
6571 + size = 5*sizeof(struct desc_struct);
6572 + if (size > bytecount)
6576 + if (copy_to_user(ptr, address, size))
6582 +static int write_ldt(void __user * ptr, unsigned long bytecount, int oldmode)
6584 + struct mm_struct * mm = current->mm;
6585 + __u32 entry_1, entry_2;
6587 + struct user_desc ldt_info;
6590 + if (bytecount != sizeof(ldt_info))
6593 + if (copy_from_user(&ldt_info, ptr, sizeof(ldt_info)))
6597 + if (ldt_info.entry_number >= LDT_ENTRIES)
6599 + if (ldt_info.contents == 3) {
6602 + if (ldt_info.seg_not_present == 0)
6606 + down(&mm->context.sem);
6607 + if (ldt_info.entry_number >= mm->context.size) {
6608 + error = alloc_ldt(¤t->mm->context, ldt_info.entry_number+1, 1);
6613 + /* Allow LDTs to be cleared by the user. */
6614 + if (ldt_info.base_addr == 0 && ldt_info.limit == 0) {
6615 + if (oldmode || LDT_empty(&ldt_info)) {
6622 + entry_1 = LDT_entry_a(&ldt_info);
6623 + entry_2 = LDT_entry_b(&ldt_info);
6625 + entry_2 &= ~(1 << 20);
6627 + /* Install the new entry ... */
6629 + error = write_ldt_entry(mm->context.ldt, ldt_info.entry_number,
6630 + entry_1, entry_2);
6633 + up(&mm->context.sem);
6638 +asmlinkage int sys_modify_ldt(int func, void __user *ptr, unsigned long bytecount)
6640 + int ret = -ENOSYS;
6644 + ret = read_ldt(ptr, bytecount);
6647 + ret = write_ldt(ptr, bytecount, 1);
6650 + ret = read_default_ldt(ptr, bytecount);
6653 + ret = write_ldt(ptr, bytecount, 0);
6658 Index: head-2008-11-25/arch/x86/kernel/microcode-xen.c
6659 ===================================================================
6660 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6661 +++ head-2008-11-25/arch/x86/kernel/microcode-xen.c 2007-06-12 13:12:48.000000000 +0200
6664 + * Intel CPU Microcode Update Driver for Linux
6666 + * Copyright (C) 2000-2004 Tigran Aivazian
6668 + * This driver allows to upgrade microcode on Intel processors
6669 + * belonging to IA-32 family - PentiumPro, Pentium II,
6670 + * Pentium III, Xeon, Pentium 4, etc.
6672 + * Reference: Section 8.10 of Volume III, Intel Pentium 4 Manual,
6673 + * Order Number 245472 or free download from:
6675 + * http://developer.intel.com/design/pentium4/manuals/245472.htm
6677 + * For more information, go to http://www.urbanmyth.org/microcode
6679 + * This program is free software; you can redistribute it and/or
6680 + * modify it under the terms of the GNU General Public License
6681 + * as published by the Free Software Foundation; either version
6682 + * 2 of the License, or (at your option) any later version.
6685 +//#define DEBUG /* pr_debug */
6686 +#include <linux/capability.h>
6687 +#include <linux/kernel.h>
6688 +#include <linux/init.h>
6689 +#include <linux/sched.h>
6690 +#include <linux/cpumask.h>
6691 +#include <linux/module.h>
6692 +#include <linux/slab.h>
6693 +#include <linux/vmalloc.h>
6694 +#include <linux/miscdevice.h>
6695 +#include <linux/spinlock.h>
6696 +#include <linux/mm.h>
6697 +#include <linux/mutex.h>
6698 +#include <linux/syscalls.h>
6700 +#include <asm/msr.h>
6701 +#include <asm/uaccess.h>
6702 +#include <asm/processor.h>
6704 +MODULE_DESCRIPTION("Intel CPU (IA-32) Microcode Update Driver");
6705 +MODULE_AUTHOR("Tigran Aivazian <tigran@veritas.com>");
6706 +MODULE_LICENSE("GPL");
6708 +static int verbose;
6709 +module_param(verbose, int, 0644);
6711 +#define MICROCODE_VERSION "1.14a-xen"
6713 +#define DEFAULT_UCODE_DATASIZE (2000) /* 2000 bytes */
6714 +#define MC_HEADER_SIZE (sizeof (microcode_header_t)) /* 48 bytes */
6715 +#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) /* 2048 bytes */
6717 +/* no concurrent ->write()s are allowed on /dev/cpu/microcode */
6718 +static DEFINE_MUTEX(microcode_mutex);
6720 +static int microcode_open (struct inode *unused1, struct file *unused2)
6722 + return capable(CAP_SYS_RAWIO) ? 0 : -EPERM;
6726 +static int do_microcode_update (const void __user *ubuf, size_t len)
6731 + kbuf = vmalloc(len);
6735 + if (copy_from_user(kbuf, ubuf, len) == 0) {
6736 + struct xen_platform_op op;
6738 + op.cmd = XENPF_microcode_update;
6739 + set_xen_guest_handle(op.u.microcode.data, kbuf);
6740 + op.u.microcode.length = len;
6741 + err = HYPERVISOR_platform_op(&op);
6750 +static ssize_t microcode_write (struct file *file, const char __user *buf, size_t len, loff_t *ppos)
6754 + if (len < MC_HEADER_SIZE) {
6755 + printk(KERN_ERR "microcode: not enough data\n");
6759 + mutex_lock(µcode_mutex);
6761 + ret = do_microcode_update(buf, len);
6763 + ret = (ssize_t)len;
6765 + mutex_unlock(µcode_mutex);
6770 +static struct file_operations microcode_fops = {
6771 + .owner = THIS_MODULE,
6772 + .write = microcode_write,
6773 + .open = microcode_open,
6776 +static struct miscdevice microcode_dev = {
6777 + .minor = MICROCODE_MINOR,
6778 + .name = "microcode",
6779 + .fops = µcode_fops,
6782 +static int __init microcode_init (void)
6786 + error = misc_register(µcode_dev);
6789 + "microcode: can't misc_register on minor=%d\n",
6795 + "IA-32 Microcode Update Driver: v" MICROCODE_VERSION " <tigran@veritas.com>\n");
6799 +static void __exit microcode_exit (void)
6801 + misc_deregister(µcode_dev);
6804 +module_init(microcode_init)
6805 +module_exit(microcode_exit)
6806 +MODULE_ALIAS_MISCDEV(MICROCODE_MINOR);
6807 Index: head-2008-11-25/arch/x86/kernel/mpparse_32-xen.c
6808 ===================================================================
6809 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6810 +++ head-2008-11-25/arch/x86/kernel/mpparse_32-xen.c 2007-06-12 13:12:48.000000000 +0200
6813 + * Intel Multiprocessor Specification 1.1 and 1.4
6814 + * compliant MP-table parsing routines.
6816 + * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6817 + * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6820 + * Erich Boleyn : MP v1.4 and additional changes.
6821 + * Alan Cox : Added EBDA scanning
6822 + * Ingo Molnar : various cleanups and rewrites
6823 + * Maciej W. Rozycki: Bits for default MP configurations
6824 + * Paul Diefenbaugh: Added full ACPI support
6827 +#include <linux/mm.h>
6828 +#include <linux/init.h>
6829 +#include <linux/acpi.h>
6830 +#include <linux/delay.h>
6831 +#include <linux/bootmem.h>
6832 +#include <linux/smp_lock.h>
6833 +#include <linux/kernel_stat.h>
6834 +#include <linux/mc146818rtc.h>
6835 +#include <linux/bitops.h>
6837 +#include <asm/smp.h>
6838 +#include <asm/acpi.h>
6839 +#include <asm/mtrr.h>
6840 +#include <asm/mpspec.h>
6841 +#include <asm/io_apic.h>
6843 +#include <mach_apic.h>
6844 +#include <mach_mpparse.h>
6845 +#include <bios_ebda.h>
6847 +/* Have we found an MP table */
6848 +int smp_found_config;
6849 +unsigned int __initdata maxcpus = NR_CPUS;
6852 + * Various Linux-internal data structures created from the
6855 +int apic_version [MAX_APICS];
6856 +int mp_bus_id_to_type [MAX_MP_BUSSES];
6857 +int mp_bus_id_to_node [MAX_MP_BUSSES];
6858 +int mp_bus_id_to_local [MAX_MP_BUSSES];
6859 +int quad_local_to_mp_bus_id [NR_CPUS/4][4];
6860 +int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
6861 +static int mp_current_pci_id;
6863 +/* I/O APIC entries */
6864 +struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
6866 +/* # of MP IRQ source entries */
6867 +struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
6869 +/* MP IRQ source entries */
6870 +int mp_irq_entries;
6875 +unsigned long mp_lapic_addr;
6877 +unsigned int def_to_bigsmp = 0;
6879 +/* Processor that is doing the boot up */
6880 +unsigned int boot_cpu_physical_apicid = -1U;
6881 +/* Internal processor count */
6882 +static unsigned int __devinitdata num_processors;
6884 +/* Bitmask of physically existing CPUs */
6885 +physid_mask_t phys_cpu_present_map;
6887 +u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
6890 + * Intel MP BIOS table parsing routines:
6895 + * Checksum an MP configuration block.
6898 +static int __init mpf_checksum(unsigned char *mp, int len)
6905 + return sum & 0xFF;
6909 + * Have to match translation table entries to main table entries by counter
6910 + * hence the mpc_record variable .... can't see a less disgusting way of
6914 +static int mpc_record;
6915 +static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
6918 +static void __devinit MP_processor_info (struct mpc_config_processor *m)
6921 + physid_mask_t phys_cpu;
6923 + if (!(m->mpc_cpuflag & CPU_ENABLED))
6926 + apicid = mpc_apic_id(m, translation_table[mpc_record]);
6928 + if (m->mpc_featureflag&(1<<0))
6929 + Dprintk(" Floating point unit present.\n");
6930 + if (m->mpc_featureflag&(1<<7))
6931 + Dprintk(" Machine Exception supported.\n");
6932 + if (m->mpc_featureflag&(1<<8))
6933 + Dprintk(" 64 bit compare & exchange supported.\n");
6934 + if (m->mpc_featureflag&(1<<9))
6935 + Dprintk(" Internal APIC present.\n");
6936 + if (m->mpc_featureflag&(1<<11))
6937 + Dprintk(" SEP present.\n");
6938 + if (m->mpc_featureflag&(1<<12))
6939 + Dprintk(" MTRR present.\n");
6940 + if (m->mpc_featureflag&(1<<13))
6941 + Dprintk(" PGE present.\n");
6942 + if (m->mpc_featureflag&(1<<14))
6943 + Dprintk(" MCA present.\n");
6944 + if (m->mpc_featureflag&(1<<15))
6945 + Dprintk(" CMOV present.\n");
6946 + if (m->mpc_featureflag&(1<<16))
6947 + Dprintk(" PAT present.\n");
6948 + if (m->mpc_featureflag&(1<<17))
6949 + Dprintk(" PSE present.\n");
6950 + if (m->mpc_featureflag&(1<<18))
6951 + Dprintk(" PSN present.\n");
6952 + if (m->mpc_featureflag&(1<<19))
6953 + Dprintk(" Cache Line Flush Instruction present.\n");
6955 + if (m->mpc_featureflag&(1<<21))
6956 + Dprintk(" Debug Trace and EMON Store present.\n");
6957 + if (m->mpc_featureflag&(1<<22))
6958 + Dprintk(" ACPI Thermal Throttle Registers present.\n");
6959 + if (m->mpc_featureflag&(1<<23))
6960 + Dprintk(" MMX present.\n");
6961 + if (m->mpc_featureflag&(1<<24))
6962 + Dprintk(" FXSR present.\n");
6963 + if (m->mpc_featureflag&(1<<25))
6964 + Dprintk(" XMM present.\n");
6965 + if (m->mpc_featureflag&(1<<26))
6966 + Dprintk(" Willamette New Instructions present.\n");
6967 + if (m->mpc_featureflag&(1<<27))
6968 + Dprintk(" Self Snoop present.\n");
6969 + if (m->mpc_featureflag&(1<<28))
6970 + Dprintk(" HT present.\n");
6971 + if (m->mpc_featureflag&(1<<29))
6972 + Dprintk(" Thermal Monitor present.\n");
6973 + /* 30, 31 Reserved */
6976 + if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
6977 + Dprintk(" Bootup CPU\n");
6978 + boot_cpu_physical_apicid = m->mpc_apicid;
6981 + ver = m->mpc_apicver;
6984 + * Validate version
6987 + printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
6988 + "fixing up to 0x10. (tell your hw vendor)\n",
6992 + apic_version[m->mpc_apicid] = ver;
6994 + phys_cpu = apicid_to_cpu_present(apicid);
6995 + physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
6997 + if (num_processors >= NR_CPUS) {
6998 + printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
6999 + " Processor ignored.\n", NR_CPUS);
7003 + if (num_processors >= maxcpus) {
7004 + printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
7005 + " Processor ignored.\n", maxcpus);
7009 + cpu_set(num_processors, cpu_possible_map);
7013 + * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
7014 + * but we need to work other dependencies like SMP_SUSPEND etc
7015 + * before this can be done without some confusion.
7016 + * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
7017 + * - Ashok Raj <ashok.raj@intel.com>
7019 + if (num_processors > 8) {
7020 + switch (boot_cpu_data.x86_vendor) {
7021 + case X86_VENDOR_INTEL:
7022 + if (!APIC_XAPIC(ver)) {
7023 + def_to_bigsmp = 0;
7026 + /* If P4 and above fall through */
7027 + case X86_VENDOR_AMD:
7028 + def_to_bigsmp = 1;
7031 + bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
7034 +void __init MP_processor_info (struct mpc_config_processor *m)
7038 +#endif /* CONFIG_XEN */
7040 +static void __init MP_bus_info (struct mpc_config_bus *m)
7044 + memcpy(str, m->mpc_bustype, 6);
7047 + mpc_oem_bus_info(m, str, translation_table[mpc_record]);
7049 + if (m->mpc_busid >= MAX_MP_BUSSES) {
7050 + printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
7051 + " is too large, max. supported is %d\n",
7052 + m->mpc_busid, str, MAX_MP_BUSSES - 1);
7056 + if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
7057 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
7058 + } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
7059 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
7060 + } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
7061 + mpc_oem_pci_bus(m, translation_table[mpc_record]);
7062 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
7063 + mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
7064 + mp_current_pci_id++;
7065 + } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
7066 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
7067 + } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
7068 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
7070 + printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
7074 +static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
7076 + if (!(m->mpc_flags & MPC_APIC_USABLE))
7079 + printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
7080 + m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
7081 + if (nr_ioapics >= MAX_IO_APICS) {
7082 + printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
7083 + MAX_IO_APICS, nr_ioapics);
7084 + panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
7086 + if (!m->mpc_apicaddr) {
7087 + printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
7088 + " found in MP table, skipping!\n");
7091 + mp_ioapics[nr_ioapics] = *m;
7095 +static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
7097 + mp_irqs [mp_irq_entries] = *m;
7098 + Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
7099 + " IRQ %02x, APIC ID %x, APIC INT %02x\n",
7100 + m->mpc_irqtype, m->mpc_irqflag & 3,
7101 + (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
7102 + m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
7103 + if (++mp_irq_entries == MAX_IRQ_SOURCES)
7104 + panic("Max # of irq sources exceeded!!\n");
7107 +static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
7109 + Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
7110 + " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
7111 + m->mpc_irqtype, m->mpc_irqflag & 3,
7112 + (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
7113 + m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
7115 + * Well it seems all SMP boards in existence
7116 + * use ExtINT/LVT1 == LINT0 and
7117 + * NMI/LVT2 == LINT1 - the following check
7118 + * will show us if this assumptions is false.
7119 + * Until then we do not have to add baggage.
7121 + if ((m->mpc_irqtype == mp_ExtINT) &&
7122 + (m->mpc_destapiclint != 0))
7124 + if ((m->mpc_irqtype == mp_NMI) &&
7125 + (m->mpc_destapiclint != 1))
7129 +#ifdef CONFIG_X86_NUMAQ
7130 +static void __init MP_translation_info (struct mpc_config_translation *m)
7132 + printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
7134 + if (mpc_record >= MAX_MPC_ENTRY)
7135 + printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
7137 + translation_table[mpc_record] = m; /* stash this for later */
7138 + if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
7139 + node_set_online(m->trans_quad);
7143 + * Read/parse the MPC oem tables
7146 +static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
7147 + unsigned short oemsize)
7149 + int count = sizeof (*oemtable); /* the header size */
7150 + unsigned char *oemptr = ((unsigned char *)oemtable)+count;
7153 + printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
7154 + if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
7156 + printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
7157 + oemtable->oem_signature[0],
7158 + oemtable->oem_signature[1],
7159 + oemtable->oem_signature[2],
7160 + oemtable->oem_signature[3]);
7163 + if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
7165 + printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
7168 + while (count < oemtable->oem_length) {
7169 + switch (*oemptr) {
7170 + case MP_TRANSLATION:
7172 + struct mpc_config_translation *m=
7173 + (struct mpc_config_translation *)oemptr;
7174 + MP_translation_info(m);
7175 + oemptr += sizeof(*m);
7176 + count += sizeof(*m);
7182 + printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
7189 +static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
7192 + if (strncmp(oem, "IBM NUMA", 8))
7193 + printk("Warning! May not be a NUMA-Q system!\n");
7194 + if (mpc->mpc_oemptr)
7195 + smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
7196 + mpc->mpc_oemsize);
7198 +#endif /* CONFIG_X86_NUMAQ */
7201 + * Read/parse the MPC
7204 +static int __init smp_read_mpc(struct mp_config_table *mpc)
7208 + int count=sizeof(*mpc);
7209 + unsigned char *mpt=((unsigned char *)mpc)+count;
7211 + if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
7212 + printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
7213 + *(u32 *)mpc->mpc_signature);
7216 + if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
7217 + printk(KERN_ERR "SMP mptable: checksum error!\n");
7220 + if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
7221 + printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
7225 + if (!mpc->mpc_lapic) {
7226 + printk(KERN_ERR "SMP mptable: null local APIC address!\n");
7229 + memcpy(oem,mpc->mpc_oem,8);
7231 + printk(KERN_INFO "OEM ID: %s ",oem);
7233 + memcpy(str,mpc->mpc_productid,12);
7235 + printk("Product ID: %s ",str);
7237 + mps_oem_check(mpc, oem, str);
7239 + printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
7242 + * Save the local APIC address (it might be non-default) -- but only
7243 + * if we're not using ACPI.
7246 + mp_lapic_addr = mpc->mpc_lapic;
7249 + * Now process the configuration blocks.
7252 + while (count < mpc->mpc_length) {
7254 + case MP_PROCESSOR:
7256 + struct mpc_config_processor *m=
7257 + (struct mpc_config_processor *)mpt;
7258 + /* ACPI may have already provided this data */
7260 + MP_processor_info(m);
7261 + mpt += sizeof(*m);
7262 + count += sizeof(*m);
7267 + struct mpc_config_bus *m=
7268 + (struct mpc_config_bus *)mpt;
7270 + mpt += sizeof(*m);
7271 + count += sizeof(*m);
7276 + struct mpc_config_ioapic *m=
7277 + (struct mpc_config_ioapic *)mpt;
7278 + MP_ioapic_info(m);
7280 + count+=sizeof(*m);
7285 + struct mpc_config_intsrc *m=
7286 + (struct mpc_config_intsrc *)mpt;
7288 + MP_intsrc_info(m);
7290 + count+=sizeof(*m);
7295 + struct mpc_config_lintsrc *m=
7296 + (struct mpc_config_lintsrc *)mpt;
7297 + MP_lintsrc_info(m);
7299 + count+=sizeof(*m);
7304 + count = mpc->mpc_length;
7310 + clustered_apic_check();
7311 + if (!num_processors)
7312 + printk(KERN_ERR "SMP mptable: no processors registered!\n");
7313 + return num_processors;
7316 +static int __init ELCR_trigger(unsigned int irq)
7318 + unsigned int port;
7320 + port = 0x4d0 + (irq >> 3);
7321 + return (inb(port) >> (irq & 7)) & 1;
7324 +static void __init construct_default_ioirq_mptable(int mpc_default_type)
7326 + struct mpc_config_intsrc intsrc;
7328 + int ELCR_fallback = 0;
7330 + intsrc.mpc_type = MP_INTSRC;
7331 + intsrc.mpc_irqflag = 0; /* conforming */
7332 + intsrc.mpc_srcbus = 0;
7333 + intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
7335 + intsrc.mpc_irqtype = mp_INT;
7338 + * If true, we have an ISA/PCI system with no IRQ entries
7339 + * in the MP table. To prevent the PCI interrupts from being set up
7340 + * incorrectly, we try to use the ELCR. The sanity check to see if
7341 + * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
7342 + * never be level sensitive, so we simply see if the ELCR agrees.
7343 + * If it does, we assume it's valid.
7345 + if (mpc_default_type == 5) {
7346 + printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
7348 + if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
7349 + printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
7351 + printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
7352 + ELCR_fallback = 1;
7356 + for (i = 0; i < 16; i++) {
7357 + switch (mpc_default_type) {
7359 + if (i == 0 || i == 13)
7360 + continue; /* IRQ0 & IRQ13 not connected */
7361 + /* fall through */
7364 + continue; /* IRQ2 is never connected */
7367 + if (ELCR_fallback) {
7369 + * If the ELCR indicates a level-sensitive interrupt, we
7370 + * copy that information over to the MP table in the
7371 + * irqflag field (level sensitive, active high polarity).
7373 + if (ELCR_trigger(i))
7374 + intsrc.mpc_irqflag = 13;
7376 + intsrc.mpc_irqflag = 0;
7379 + intsrc.mpc_srcbusirq = i;
7380 + intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
7381 + MP_intsrc_info(&intsrc);
7384 + intsrc.mpc_irqtype = mp_ExtINT;
7385 + intsrc.mpc_srcbusirq = 0;
7386 + intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
7387 + MP_intsrc_info(&intsrc);
7390 +static inline void __init construct_default_ISA_mptable(int mpc_default_type)
7392 + struct mpc_config_processor processor;
7393 + struct mpc_config_bus bus;
7394 + struct mpc_config_ioapic ioapic;
7395 + struct mpc_config_lintsrc lintsrc;
7396 + int linttypes[2] = { mp_ExtINT, mp_NMI };
7400 + * local APIC has default address
7402 + mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
7405 + * 2 CPUs, numbered 0 & 1.
7407 + processor.mpc_type = MP_PROCESSOR;
7408 + /* Either an integrated APIC or a discrete 82489DX. */
7409 + processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
7410 + processor.mpc_cpuflag = CPU_ENABLED;
7411 + processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
7412 + (boot_cpu_data.x86_model << 4) |
7413 + boot_cpu_data.x86_mask;
7414 + processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
7415 + processor.mpc_reserved[0] = 0;
7416 + processor.mpc_reserved[1] = 0;
7417 + for (i = 0; i < 2; i++) {
7418 + processor.mpc_apicid = i;
7419 + MP_processor_info(&processor);
7422 + bus.mpc_type = MP_BUS;
7423 + bus.mpc_busid = 0;
7424 + switch (mpc_default_type) {
7427 + printk(KERN_ERR "Unknown standard configuration %d\n",
7428 + mpc_default_type);
7429 + /* fall through */
7432 + memcpy(bus.mpc_bustype, "ISA ", 6);
7437 + memcpy(bus.mpc_bustype, "EISA ", 6);
7441 + memcpy(bus.mpc_bustype, "MCA ", 6);
7443 + MP_bus_info(&bus);
7444 + if (mpc_default_type > 4) {
7445 + bus.mpc_busid = 1;
7446 + memcpy(bus.mpc_bustype, "PCI ", 6);
7447 + MP_bus_info(&bus);
7450 + ioapic.mpc_type = MP_IOAPIC;
7451 + ioapic.mpc_apicid = 2;
7452 + ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
7453 + ioapic.mpc_flags = MPC_APIC_USABLE;
7454 + ioapic.mpc_apicaddr = 0xFEC00000;
7455 + MP_ioapic_info(&ioapic);
7458 + * We set up most of the low 16 IO-APIC pins according to MPS rules.
7460 + construct_default_ioirq_mptable(mpc_default_type);
7462 + lintsrc.mpc_type = MP_LINTSRC;
7463 + lintsrc.mpc_irqflag = 0; /* conforming */
7464 + lintsrc.mpc_srcbusid = 0;
7465 + lintsrc.mpc_srcbusirq = 0;
7466 + lintsrc.mpc_destapic = MP_APIC_ALL;
7467 + for (i = 0; i < 2; i++) {
7468 + lintsrc.mpc_irqtype = linttypes[i];
7469 + lintsrc.mpc_destapiclint = i;
7470 + MP_lintsrc_info(&lintsrc);
7474 +static struct intel_mp_floating *mpf_found;
7477 + * Scan the memory blocks for an SMP configuration block.
7479 +void __init get_smp_config (void)
7481 + struct intel_mp_floating *mpf = mpf_found;
7484 + * ACPI supports both logical (e.g. Hyper-Threading) and physical
7485 + * processors, where MPS only supports physical.
7487 + if (acpi_lapic && acpi_ioapic) {
7488 + printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
7491 + else if (acpi_lapic)
7492 + printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
7494 + printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
7495 + if (mpf->mpf_feature2 & (1<<7)) {
7496 + printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
7499 + printk(KERN_INFO " Virtual Wire compatibility mode.\n");
7504 + * Now see if we need to read further.
7506 + if (mpf->mpf_feature1 != 0) {
7508 + printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
7509 + construct_default_ISA_mptable(mpf->mpf_feature1);
7511 + } else if (mpf->mpf_physptr) {
7514 + * Read the physical hardware table. Anything here will
7515 + * override the defaults.
7517 + if (!smp_read_mpc(isa_bus_to_virt(mpf->mpf_physptr))) {
7518 + smp_found_config = 0;
7519 + printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
7520 + printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
7524 + * If there are no explicit MP IRQ entries, then we are
7525 + * broken. We set up most of the low 16 IO-APIC pins to
7526 + * ISA defaults and hope it will work.
7528 + if (!mp_irq_entries) {
7529 + struct mpc_config_bus bus;
7531 + printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
7533 + bus.mpc_type = MP_BUS;
7534 + bus.mpc_busid = 0;
7535 + memcpy(bus.mpc_bustype, "ISA ", 6);
7536 + MP_bus_info(&bus);
7538 + construct_default_ioirq_mptable(0);
7544 + printk(KERN_INFO "Processors: %d\n", num_processors);
7546 + * Only use the first configuration found.
7550 +static int __init smp_scan_config (unsigned long base, unsigned long length)
7552 + unsigned long *bp = isa_bus_to_virt(base);
7553 + struct intel_mp_floating *mpf;
7555 + Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
7556 + if (sizeof(*mpf) != 16)
7557 + printk("Error: MPF size\n");
7559 + while (length > 0) {
7560 + mpf = (struct intel_mp_floating *)bp;
7561 + if ((*bp == SMP_MAGIC_IDENT) &&
7562 + (mpf->mpf_length == 1) &&
7563 + !mpf_checksum((unsigned char *)bp, 16) &&
7564 + ((mpf->mpf_specification == 1)
7565 + || (mpf->mpf_specification == 4)) ) {
7567 + smp_found_config = 1;
7569 + printk(KERN_INFO "found SMP MP-table at %08lx\n",
7570 + virt_to_phys(mpf));
7571 + reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
7572 + if (mpf->mpf_physptr) {
7574 + * We cannot access to MPC table to compute
7575 + * table size yet, as only few megabytes from
7576 + * the bottom is mapped now.
7577 + * PC-9800's MPC table places on the very last
7578 + * of physical memory; so that simply reserving
7579 + * PAGE_SIZE from mpg->mpf_physptr yields BUG()
7580 + * in reserve_bootmem.
7582 + unsigned long size = PAGE_SIZE;
7583 + unsigned long end = max_low_pfn * PAGE_SIZE;
7584 + if (mpf->mpf_physptr + size > end)
7585 + size = end - mpf->mpf_physptr;
7586 + reserve_bootmem(mpf->mpf_physptr, size);
7589 + printk(KERN_INFO "found SMP MP-table at %08lx\n",
7590 + ((unsigned long)bp - (unsigned long)isa_bus_to_virt(base)) + base);
7602 +void __init find_smp_config (void)
7605 + unsigned int address;
7609 + * FIXME: Linux assumes you have 640K of base ram..
7610 + * this continues the error...
7612 + * 1) Scan the bottom 1K for a signature
7613 + * 2) Scan the top 1K of base RAM
7614 + * 3) Scan the 64K of bios
7616 + if (smp_scan_config(0x0,0x400) ||
7617 + smp_scan_config(639*0x400,0x400) ||
7618 + smp_scan_config(0xF0000,0x10000))
7621 + * If it is an SMP machine we should know now, unless the
7622 + * configuration is in an EISA/MCA bus machine with an
7623 + * extended bios data area.
7625 + * there is a real-mode segmented pointer pointing to the
7626 + * 4K EBDA area at 0x40E, calculate and scan it here.
7628 + * NOTE! There are Linux loaders that will corrupt the EBDA
7629 + * area, and as such this kind of SMP config may be less
7630 + * trustworthy, simply because the SMP table may have been
7631 + * stomped on during early boot. These loaders are buggy and
7632 + * should be fixed.
7634 + * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
7638 + address = get_bios_ebda();
7640 + smp_scan_config(address, 0x400);
7646 +/* --------------------------------------------------------------------------
7647 + ACPI-based MP Configuration
7648 + -------------------------------------------------------------------------- */
7652 +void __init mp_register_lapic_address (
7656 + mp_lapic_addr = (unsigned long) address;
7658 + set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
7660 + if (boot_cpu_physical_apicid == -1U)
7661 + boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
7663 + Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
7668 +void __devinit mp_register_lapic (
7672 + struct mpc_config_processor processor;
7675 + if (MAX_APICS - id <= 0) {
7676 + printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
7681 + if (id == boot_cpu_physical_apicid)
7685 + processor.mpc_type = MP_PROCESSOR;
7686 + processor.mpc_apicid = id;
7687 + processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
7688 + processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
7689 + processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
7690 + processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
7691 + (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
7692 + processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
7693 + processor.mpc_reserved[0] = 0;
7694 + processor.mpc_reserved[1] = 0;
7697 + MP_processor_info(&processor);
7700 +#ifdef CONFIG_X86_IO_APIC
7702 +#define MP_ISA_BUS 0
7703 +#define MP_MAX_IOAPIC_PIN 127
7705 +static struct mp_ioapic_routing {
7709 + u32 pin_programmed[4];
7710 +} mp_ioapic_routing[MAX_IO_APICS];
7713 +static int mp_find_ioapic (
7718 + /* Find the IOAPIC that manages this GSI. */
7719 + for (i = 0; i < nr_ioapics; i++) {
7720 + if ((gsi >= mp_ioapic_routing[i].gsi_base)
7721 + && (gsi <= mp_ioapic_routing[i].gsi_end))
7725 + printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
7731 +void __init mp_register_ioapic (
7739 + if (nr_ioapics >= MAX_IO_APICS) {
7740 + printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
7741 + "(found %d)\n", MAX_IO_APICS, nr_ioapics);
7742 + panic("Recompile kernel with bigger MAX_IO_APICS!\n");
7745 + printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
7746 + " found in MADT table, skipping!\n");
7750 + idx = nr_ioapics++;
7752 + mp_ioapics[idx].mpc_type = MP_IOAPIC;
7753 + mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
7754 + mp_ioapics[idx].mpc_apicaddr = address;
7757 + set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
7759 + if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
7760 + && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
7761 + tmpid = io_apic_get_unique_id(idx, id);
7764 + if (tmpid == -1) {
7768 + mp_ioapics[idx].mpc_apicid = tmpid;
7769 + mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
7772 + * Build basic GSI lookup table to facilitate gsi->io_apic lookups
7773 + * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
7775 + mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
7776 + mp_ioapic_routing[idx].gsi_base = gsi_base;
7777 + mp_ioapic_routing[idx].gsi_end = gsi_base +
7778 + io_apic_get_redir_entries(idx);
7780 + printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
7781 + "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
7782 + mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
7783 + mp_ioapic_routing[idx].gsi_base,
7784 + mp_ioapic_routing[idx].gsi_end);
7790 +void __init mp_override_legacy_irq (
7796 + struct mpc_config_intsrc intsrc;
7801 + * Convert 'gsi' to 'ioapic.pin'.
7803 + ioapic = mp_find_ioapic(gsi);
7806 + pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
7809 + * TBD: This check is for faulty timer entries, where the override
7810 + * erroneously sets the trigger to level, resulting in a HUGE
7811 + * increase of timer interrupts!
7813 + if ((bus_irq == 0) && (trigger == 3))
7816 + intsrc.mpc_type = MP_INTSRC;
7817 + intsrc.mpc_irqtype = mp_INT;
7818 + intsrc.mpc_irqflag = (trigger << 2) | polarity;
7819 + intsrc.mpc_srcbus = MP_ISA_BUS;
7820 + intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
7821 + intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
7822 + intsrc.mpc_dstirq = pin; /* INTIN# */
7824 + Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
7825 + intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
7826 + (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
7827 + intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
7829 + mp_irqs[mp_irq_entries] = intsrc;
7830 + if (++mp_irq_entries == MAX_IRQ_SOURCES)
7831 + panic("Max # of irq sources exceeded!\n");
7836 +void __init mp_config_acpi_legacy_irqs (void)
7838 + struct mpc_config_intsrc intsrc;
7843 + * Fabricate the legacy ISA bus (bus #31).
7845 + mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
7846 + Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
7849 + * Older generations of ES7000 have no legacy identity mappings
7851 + if (es7000_plat == 1)
7855 + * Locate the IOAPIC that manages the ISA IRQs (0-15).
7857 + ioapic = mp_find_ioapic(0);
7861 + intsrc.mpc_type = MP_INTSRC;
7862 + intsrc.mpc_irqflag = 0; /* Conforming */
7863 + intsrc.mpc_srcbus = MP_ISA_BUS;
7864 + intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
7867 + * Use the default configuration for the IRQs 0-15. Unless
7868 + * overriden by (MADT) interrupt source override entries.
7870 + for (i = 0; i < 16; i++) {
7873 + for (idx = 0; idx < mp_irq_entries; idx++) {
7874 + struct mpc_config_intsrc *irq = mp_irqs + idx;
7876 + /* Do we already have a mapping for this ISA IRQ? */
7877 + if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
7880 + /* Do we already have a mapping for this IOAPIC pin */
7881 + if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
7882 + (irq->mpc_dstirq == i))
7886 + if (idx != mp_irq_entries) {
7887 + printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
7888 + continue; /* IRQ already used */
7891 + intsrc.mpc_irqtype = mp_INT;
7892 + intsrc.mpc_srcbusirq = i; /* Identity mapped */
7893 + intsrc.mpc_dstirq = i;
7895 + Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
7896 + "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
7897 + (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
7898 + intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
7899 + intsrc.mpc_dstirq);
7901 + mp_irqs[mp_irq_entries] = intsrc;
7902 + if (++mp_irq_entries == MAX_IRQ_SOURCES)
7903 + panic("Max # of irq sources exceeded!\n");
7907 +#define MAX_GSI_NUM 4096
7909 +int mp_register_gsi (u32 gsi, int triggering, int polarity)
7912 + int ioapic_pin = 0;
7914 + static int pci_irq = 16;
7916 + * Mapping between Global System Interrups, which
7917 + * represent all possible interrupts, and IRQs
7918 + * assigned to actual devices.
7920 + static int gsi_to_irq[MAX_GSI_NUM];
7922 + /* Don't set up the ACPI SCI because it's already set up */
7923 + if (acpi_fadt.sci_int == gsi)
7926 + ioapic = mp_find_ioapic(gsi);
7928 + printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
7932 + ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
7934 + if (ioapic_renumber_irq)
7935 + gsi = ioapic_renumber_irq(ioapic, gsi);
7938 + * Avoid pin reprogramming. PRTs typically include entries
7939 + * with redundant pin->gsi mappings (but unique PCI devices);
7940 + * we only program the IOAPIC on the first.
7942 + bit = ioapic_pin % 32;
7943 + idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
7945 + printk(KERN_ERR "Invalid reference to IOAPIC pin "
7946 + "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
7950 + if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
7951 + Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
7952 + mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
7953 + return gsi_to_irq[gsi];
7956 + mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
7958 + if (triggering == ACPI_LEVEL_SENSITIVE) {
7960 + * For PCI devices assign IRQs in order, avoiding gaps
7961 + * due to unused I/O APIC pins.
7964 + if (gsi < MAX_GSI_NUM) {
7966 + * Retain the VIA chipset work-around (gsi > 15), but
7967 + * avoid a problem where the 8254 timer (IRQ0) is setup
7968 + * via an override (so it's not on pin 0 of the ioapic),
7969 + * and at the same time, the pin 0 interrupt is a PCI
7970 + * type. The gsi > 15 test could cause these two pins
7971 + * to be shared as IRQ0, and they are not shareable.
7972 + * So test for this condition, and if necessary, avoid
7973 + * the pin collision.
7975 + if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
7978 + * Don't assign IRQ used by ACPI SCI
7980 + if (gsi == acpi_fadt.sci_int)
7982 + gsi_to_irq[irq] = gsi;
7984 + printk(KERN_ERR "GSI %u is too high\n", gsi);
7989 + io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
7990 + triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
7991 + polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
7995 +#endif /* CONFIG_X86_IO_APIC */
7996 +#endif /* CONFIG_ACPI */
7997 Index: head-2008-11-25/arch/x86/kernel/pci-dma-xen.c
7998 ===================================================================
7999 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8000 +++ head-2008-11-25/arch/x86/kernel/pci-dma-xen.c 2008-10-29 09:55:56.000000000 +0100
8003 + * Dynamic DMA mapping support.
8005 + * On i386 there is no hardware dynamic DMA address translation,
8006 + * so consistent alloc/free are merely page allocation/freeing.
8007 + * The rest of the dynamic DMA mapping interface is implemented
8011 +#include <linux/types.h>
8012 +#include <linux/mm.h>
8013 +#include <linux/string.h>
8014 +#include <linux/pci.h>
8015 +#include <linux/module.h>
8016 +#include <linux/version.h>
8017 +#include <asm/io.h>
8018 +#include <xen/balloon.h>
8019 +#include <xen/gnttab.h>
8020 +#include <asm/swiotlb.h>
8021 +#include <asm/tlbflush.h>
8022 +#include <asm-i386/mach-xen/asm/swiotlb.h>
8023 +#include <asm-i386/mach-xen/asm/gnttab_dma.h>
8024 +#include <asm/bug.h>
8027 +#include <asm/proto.h>
8029 +int iommu_merge __read_mostly = 0;
8030 +EXPORT_SYMBOL(iommu_merge);
8032 +dma_addr_t bad_dma_address __read_mostly;
8033 +EXPORT_SYMBOL(bad_dma_address);
8035 +/* This tells the BIO block layer to assume merging. Default to off
8036 + because we cannot guarantee merging later. */
8037 +int iommu_bio_merge __read_mostly = 0;
8038 +EXPORT_SYMBOL(iommu_bio_merge);
8040 +int force_iommu __read_mostly= 0;
8042 +__init int iommu_setup(char *p)
8047 +void __init pci_iommu_alloc(void)
8049 +#ifdef CONFIG_SWIOTLB
8050 + pci_swiotlb_init();
8054 +static int __init pci_iommu_init(void)
8060 +/* Must execute after PCI subsystem */
8061 +fs_initcall(pci_iommu_init);
8064 +struct dma_coherent_mem {
8069 + unsigned long *bitmap;
8072 +#define IOMMU_BUG_ON(test) \
8074 + if (unlikely(test)) { \
8075 + printk(KERN_ALERT "Fatal DMA error! " \
8076 + "Please use 'swiotlb=force'\n"); \
8081 +static int check_pages_physically_contiguous(unsigned long pfn,
8082 + unsigned int offset,
8085 + unsigned long next_mfn;
8089 + next_mfn = pfn_to_mfn(pfn);
8090 + nr_pages = (offset + length + PAGE_SIZE-1) >> PAGE_SHIFT;
8092 + for (i = 1; i < nr_pages; i++) {
8093 + if (pfn_to_mfn(++pfn) != ++next_mfn)
8099 +int range_straddles_page_boundary(paddr_t p, size_t size)
8101 + unsigned long pfn = p >> PAGE_SHIFT;
8102 + unsigned int offset = p & ~PAGE_MASK;
8104 + return ((offset + size > PAGE_SIZE) &&
8105 + !check_pages_physically_contiguous(pfn, offset, size));
8109 +dma_map_sg(struct device *hwdev, struct scatterlist *sg, int nents,
8110 + enum dma_data_direction direction)
8114 + if (direction == DMA_NONE)
8116 + WARN_ON(nents == 0 || sg[0].length == 0);
8119 + rc = swiotlb_map_sg(hwdev, sg, nents, direction);
8121 + for (i = 0; i < nents; i++ ) {
8122 + BUG_ON(!sg[i].page);
8123 + sg[i].dma_address =
8124 + gnttab_dma_map_page(sg[i].page) + sg[i].offset;
8125 + sg[i].dma_length = sg[i].length;
8126 + IOMMU_BUG_ON(address_needs_mapping(
8127 + hwdev, sg[i].dma_address));
8128 + IOMMU_BUG_ON(range_straddles_page_boundary(
8129 + page_to_pseudophys(sg[i].page) + sg[i].offset,
8135 + flush_write_buffers();
8138 +EXPORT_SYMBOL(dma_map_sg);
8141 +dma_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
8142 + enum dma_data_direction direction)
8146 + BUG_ON(direction == DMA_NONE);
8148 + swiotlb_unmap_sg(hwdev, sg, nents, direction);
8150 + for (i = 0; i < nents; i++ )
8151 + gnttab_dma_unmap_page(sg[i].dma_address);
8154 +EXPORT_SYMBOL(dma_unmap_sg);
8156 +#ifdef CONFIG_HIGHMEM
8158 +dma_map_page(struct device *dev, struct page *page, unsigned long offset,
8159 + size_t size, enum dma_data_direction direction)
8161 + dma_addr_t dma_addr;
8163 + BUG_ON(direction == DMA_NONE);
8166 + dma_addr = swiotlb_map_page(
8167 + dev, page, offset, size, direction);
8169 + dma_addr = gnttab_dma_map_page(page) + offset;
8170 + IOMMU_BUG_ON(address_needs_mapping(dev, dma_addr));
8175 +EXPORT_SYMBOL(dma_map_page);
8178 +dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
8179 + enum dma_data_direction direction)
8181 + BUG_ON(direction == DMA_NONE);
8183 + swiotlb_unmap_page(dev, dma_address, size, direction);
8185 + gnttab_dma_unmap_page(dma_address);
8187 +EXPORT_SYMBOL(dma_unmap_page);
8188 +#endif /* CONFIG_HIGHMEM */
8191 +dma_mapping_error(dma_addr_t dma_addr)
8194 + return swiotlb_dma_mapping_error(dma_addr);
8197 +EXPORT_SYMBOL(dma_mapping_error);
8200 +dma_supported(struct device *dev, u64 mask)
8203 + return swiotlb_dma_supported(dev, mask);
8205 + * By default we'll BUG when an infeasible DMA is requested, and
8206 + * request swiotlb=force (see IOMMU_BUG_ON).
8210 +EXPORT_SYMBOL(dma_supported);
8212 +void *dma_alloc_coherent(struct device *dev, size_t size,
8213 + dma_addr_t *dma_handle, gfp_t gfp)
8216 + struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
8217 + unsigned int order = get_order(size);
8218 + unsigned long vstart;
8221 + /* ignore region specifiers */
8222 + gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
8225 + int page = bitmap_find_free_region(mem->bitmap, mem->size,
8228 + *dma_handle = mem->device_base + (page << PAGE_SHIFT);
8229 + ret = mem->virt_base + (page << PAGE_SHIFT);
8230 + memset(ret, 0, size);
8233 + if (mem->flags & DMA_MEMORY_EXCLUSIVE)
8237 + if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
8240 + vstart = __get_free_pages(gfp, order);
8241 + ret = (void *)vstart;
8243 + if (dev != NULL && dev->coherent_dma_mask)
8244 + mask = dev->coherent_dma_mask;
8246 + mask = 0xffffffff;
8248 + if (ret != NULL) {
8249 + if (xen_create_contiguous_region(vstart, order,
8250 + fls64(mask)) != 0) {
8251 + free_pages(vstart, order);
8254 + memset(ret, 0, size);
8255 + *dma_handle = virt_to_bus(ret);
8259 +EXPORT_SYMBOL(dma_alloc_coherent);
8261 +void dma_free_coherent(struct device *dev, size_t size,
8262 + void *vaddr, dma_addr_t dma_handle)
8264 + struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
8265 + int order = get_order(size);
8267 + if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) {
8268 + int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
8270 + bitmap_release_region(mem->bitmap, page, order);
8272 + xen_destroy_contiguous_region((unsigned long)vaddr, order);
8273 + free_pages((unsigned long)vaddr, order);
8276 +EXPORT_SYMBOL(dma_free_coherent);
8278 +#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
8279 +int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
8280 + dma_addr_t device_addr, size_t size, int flags)
8282 + void __iomem *mem_base;
8283 + int pages = size >> PAGE_SHIFT;
8284 + int bitmap_size = (pages + 31)/32;
8286 + if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
8293 + /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
8295 + mem_base = ioremap(bus_addr, size);
8299 + dev->dma_mem = kmalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
8300 + if (!dev->dma_mem)
8302 + memset(dev->dma_mem, 0, sizeof(struct dma_coherent_mem));
8303 + dev->dma_mem->bitmap = kmalloc(bitmap_size, GFP_KERNEL);
8304 + if (!dev->dma_mem->bitmap)
8306 + memset(dev->dma_mem->bitmap, 0, bitmap_size);
8308 + dev->dma_mem->virt_base = mem_base;
8309 + dev->dma_mem->device_base = device_addr;
8310 + dev->dma_mem->size = pages;
8311 + dev->dma_mem->flags = flags;
8313 + if (flags & DMA_MEMORY_MAP)
8314 + return DMA_MEMORY_MAP;
8316 + return DMA_MEMORY_IO;
8319 + kfree(dev->dma_mem->bitmap);
8323 +EXPORT_SYMBOL(dma_declare_coherent_memory);
8325 +void dma_release_declared_memory(struct device *dev)
8327 + struct dma_coherent_mem *mem = dev->dma_mem;
8331 + dev->dma_mem = NULL;
8332 + iounmap(mem->virt_base);
8333 + kfree(mem->bitmap);
8336 +EXPORT_SYMBOL(dma_release_declared_memory);
8338 +void *dma_mark_declared_memory_occupied(struct device *dev,
8339 + dma_addr_t device_addr, size_t size)
8341 + struct dma_coherent_mem *mem = dev->dma_mem;
8342 + int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT;
8346 + return ERR_PTR(-EINVAL);
8348 + pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
8349 + err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
8351 + return ERR_PTR(err);
8352 + return mem->virt_base + (pos << PAGE_SHIFT);
8354 +EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
8355 +#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
8358 +dma_map_single(struct device *dev, void *ptr, size_t size,
8359 + enum dma_data_direction direction)
8363 + if (direction == DMA_NONE)
8365 + WARN_ON(size == 0);
8368 + dma = swiotlb_map_single(dev, ptr, size, direction);
8370 + dma = gnttab_dma_map_page(virt_to_page(ptr)) +
8371 + offset_in_page(ptr);
8372 + IOMMU_BUG_ON(range_straddles_page_boundary(__pa(ptr), size));
8373 + IOMMU_BUG_ON(address_needs_mapping(dev, dma));
8376 + flush_write_buffers();
8379 +EXPORT_SYMBOL(dma_map_single);
8382 +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
8383 + enum dma_data_direction direction)
8385 + if (direction == DMA_NONE)
8388 + swiotlb_unmap_single(dev, dma_addr, size, direction);
8390 + gnttab_dma_unmap_page(dma_addr);
8392 +EXPORT_SYMBOL(dma_unmap_single);
8395 +dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
8396 + enum dma_data_direction direction)
8399 + swiotlb_sync_single_for_cpu(dev, dma_handle, size, direction);
8401 +EXPORT_SYMBOL(dma_sync_single_for_cpu);
8404 +dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
8405 + enum dma_data_direction direction)
8408 + swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
8410 +EXPORT_SYMBOL(dma_sync_single_for_device);
8411 Index: head-2008-11-25/arch/x86/kernel/process_32-xen.c
8412 ===================================================================
8413 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8414 +++ head-2008-11-25/arch/x86/kernel/process_32-xen.c 2008-07-21 11:00:32.000000000 +0200
8417 + * linux/arch/i386/kernel/process.c
8419 + * Copyright (C) 1995 Linus Torvalds
8421 + * Pentium III FXSR, SSE support
8422 + * Gareth Hughes <gareth@valinux.com>, May 2000
8426 + * This file handles the architecture-dependent parts of process handling..
8429 +#include <stdarg.h>
8431 +#include <linux/cpu.h>
8432 +#include <linux/errno.h>
8433 +#include <linux/sched.h>
8434 +#include <linux/fs.h>
8435 +#include <linux/kernel.h>
8436 +#include <linux/mm.h>
8437 +#include <linux/elfcore.h>
8438 +#include <linux/smp.h>
8439 +#include <linux/smp_lock.h>
8440 +#include <linux/stddef.h>
8441 +#include <linux/slab.h>
8442 +#include <linux/vmalloc.h>
8443 +#include <linux/user.h>
8444 +#include <linux/a.out.h>
8445 +#include <linux/interrupt.h>
8446 +#include <linux/utsname.h>
8447 +#include <linux/delay.h>
8448 +#include <linux/reboot.h>
8449 +#include <linux/init.h>
8450 +#include <linux/mc146818rtc.h>
8451 +#include <linux/module.h>
8452 +#include <linux/kallsyms.h>
8453 +#include <linux/ptrace.h>
8454 +#include <linux/random.h>
8456 +#include <asm/uaccess.h>
8457 +#include <asm/pgtable.h>
8458 +#include <asm/system.h>
8459 +#include <asm/io.h>
8460 +#include <asm/ldt.h>
8461 +#include <asm/processor.h>
8462 +#include <asm/i387.h>
8463 +#include <asm/desc.h>
8464 +#include <asm/vm86.h>
8465 +#ifdef CONFIG_MATH_EMULATION
8466 +#include <asm/math_emu.h>
8469 +#include <xen/interface/physdev.h>
8470 +#include <xen/interface/vcpu.h>
8471 +#include <xen/cpu_hotplug.h>
8473 +#include <linux/err.h>
8475 +#include <asm/tlbflush.h>
8476 +#include <asm/cpu.h>
8478 +asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
8480 +static int hlt_counter;
8482 +unsigned long boot_option_idle_override = 0;
8483 +EXPORT_SYMBOL(boot_option_idle_override);
8486 + * Return saved PC of a blocked thread.
8488 +unsigned long thread_saved_pc(struct task_struct *tsk)
8490 + return ((unsigned long *)tsk->thread.esp)[3];
8494 + * Powermanagement idle function, if any..
8496 +void (*pm_idle)(void);
8497 +EXPORT_SYMBOL(pm_idle);
8498 +static DEFINE_PER_CPU(unsigned int, cpu_idle_state);
8500 +void disable_hlt(void)
8505 +EXPORT_SYMBOL(disable_hlt);
8507 +void enable_hlt(void)
8512 +EXPORT_SYMBOL(enable_hlt);
8515 + * On SMP it's slightly faster (but much more power-consuming!)
8516 + * to poll the ->work.need_resched flag instead of waiting for the
8517 + * cross-CPU IPI to arrive. Use this option with caution.
8519 +static void poll_idle (void)
8521 + local_irq_enable();
8528 + : : "i"(_TIF_NEED_RESCHED), "m" (current_thread_info()->flags));
8531 +static void xen_idle(void)
8533 + local_irq_disable();
8535 + if (need_resched())
8536 + local_irq_enable();
8538 + current_thread_info()->status &= ~TS_POLLING;
8539 + smp_mb__after_clear_bit();
8541 + current_thread_info()->status |= TS_POLLING;
8544 +#ifdef CONFIG_APM_MODULE
8545 +EXPORT_SYMBOL(default_idle);
8548 +#ifdef CONFIG_HOTPLUG_CPU
8549 +extern cpumask_t cpu_initialized;
8550 +static inline void play_dead(void)
8553 + local_irq_disable();
8554 + cpu_clear(smp_processor_id(), cpu_initialized);
8555 + preempt_enable_no_resched();
8556 + VOID(HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL));
8560 +static inline void play_dead(void)
8564 +#endif /* CONFIG_HOTPLUG_CPU */
8567 + * The idle thread. There's no useful work to be
8568 + * done, so just try to conserve power and have a
8569 + * low exit latency (ie sit in a loop waiting for
8570 + * somebody to say that they'd like to reschedule)
8572 +void cpu_idle(void)
8574 + int cpu = smp_processor_id();
8576 + current_thread_info()->status |= TS_POLLING;
8578 + /* endless idle loop with no priority at all */
8580 + while (!need_resched()) {
8581 + void (*idle)(void);
8583 + if (__get_cpu_var(cpu_idle_state))
8584 + __get_cpu_var(cpu_idle_state) = 0;
8587 + idle = xen_idle; /* no alternatives */
8589 + if (cpu_is_offline(cpu))
8592 + __get_cpu_var(irq_stat).idle_timestamp = jiffies;
8595 + preempt_enable_no_resched();
8597 + preempt_disable();
8601 +void cpu_idle_wait(void)
8603 + unsigned int cpu, this_cpu = get_cpu();
8606 + set_cpus_allowed(current, cpumask_of_cpu(this_cpu));
8610 + for_each_online_cpu(cpu) {
8611 + per_cpu(cpu_idle_state, cpu) = 1;
8612 + cpu_set(cpu, map);
8615 + __get_cpu_var(cpu_idle_state) = 0;
8620 + for_each_online_cpu(cpu) {
8621 + if (cpu_isset(cpu, map) && !per_cpu(cpu_idle_state, cpu))
8622 + cpu_clear(cpu, map);
8624 + cpus_and(map, map, cpu_online_map);
8625 + } while (!cpus_empty(map));
8627 +EXPORT_SYMBOL_GPL(cpu_idle_wait);
8629 +void __devinit select_idle_routine(const struct cpuinfo_x86 *c)
8633 +static int __init idle_setup (char *str)
8635 + if (!strncmp(str, "poll", 4)) {
8636 + printk("using polling idle threads.\n");
8637 + pm_idle = poll_idle;
8640 + boot_option_idle_override = 1;
8644 +__setup("idle=", idle_setup);
8646 +void show_regs(struct pt_regs * regs)
8648 + unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
8651 + printk("Pid: %d, comm: %20s\n", current->pid, current->comm);
8652 + printk("EIP: %04x:[<%08lx>] CPU: %d\n",0xffff & regs->xcs,regs->eip, smp_processor_id());
8653 + print_symbol("EIP is at %s\n", regs->eip);
8655 + if (user_mode_vm(regs))
8656 + printk(" ESP: %04x:%08lx",0xffff & regs->xss,regs->esp);
8657 + printk(" EFLAGS: %08lx %s (%s %.*s)\n",
8658 + regs->eflags, print_tainted(), system_utsname.release,
8659 + (int)strcspn(system_utsname.version, " "),
8660 + system_utsname.version);
8661 + printk("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
8662 + regs->eax,regs->ebx,regs->ecx,regs->edx);
8663 + printk("ESI: %08lx EDI: %08lx EBP: %08lx",
8664 + regs->esi, regs->edi, regs->ebp);
8665 + printk(" DS: %04x ES: %04x\n",
8666 + 0xffff & regs->xds,0xffff & regs->xes);
8671 + cr4 = read_cr4_safe();
8672 + printk("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", cr0, cr2, cr3, cr4);
8673 + show_trace(NULL, regs, ®s->esp);
8677 + * This gets run with %ebx containing the
8678 + * function to call, and %edx containing
8681 +extern void kernel_thread_helper(void);
8682 +__asm__(".section .text\n"
8684 + "kernel_thread_helper:\n\t"
8685 + "movl %edx,%eax\n\t"
8693 + * Create a kernel thread
8695 +int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
8697 + struct pt_regs regs;
8699 + memset(®s, 0, sizeof(regs));
8701 + regs.ebx = (unsigned long) fn;
8702 + regs.edx = (unsigned long) arg;
8704 + regs.xds = __USER_DS;
8705 + regs.xes = __USER_DS;
8706 + regs.orig_eax = -1;
8707 + regs.eip = (unsigned long) kernel_thread_helper;
8708 + regs.xcs = GET_KERNEL_CS();
8709 + regs.eflags = X86_EFLAGS_IF | X86_EFLAGS_SF | X86_EFLAGS_PF | 0x2;
8711 + /* Ok, create the new process.. */
8712 + return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
8714 +EXPORT_SYMBOL(kernel_thread);
8717 + * Free current thread data structures etc..
8719 +void exit_thread(void)
8721 + /* The process may have allocated an io port bitmap... nuke it. */
8722 + if (unlikely(test_thread_flag(TIF_IO_BITMAP))) {
8723 + struct task_struct *tsk = current;
8724 + struct thread_struct *t = &tsk->thread;
8725 + struct physdev_set_iobitmap set_iobitmap;
8726 + memset(&set_iobitmap, 0, sizeof(set_iobitmap));
8727 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap,
8729 + kfree(t->io_bitmap_ptr);
8730 + t->io_bitmap_ptr = NULL;
8731 + clear_thread_flag(TIF_IO_BITMAP);
8735 +void flush_thread(void)
8737 + struct task_struct *tsk = current;
8739 + memset(tsk->thread.debugreg, 0, sizeof(unsigned long)*8);
8740 + memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
8741 + clear_tsk_thread_flag(tsk, TIF_DEBUG);
8743 + * Forget coprocessor state..
8746 + clear_used_math();
8749 +void release_thread(struct task_struct *dead_task)
8751 + BUG_ON(dead_task->mm);
8752 + release_vm86_irqs(dead_task);
8756 + * This gets called before we allocate a new thread and copy
8757 + * the current task into it.
8759 +void prepare_to_copy(struct task_struct *tsk)
8764 +int copy_thread(int nr, unsigned long clone_flags, unsigned long esp,
8765 + unsigned long unused,
8766 + struct task_struct * p, struct pt_regs * regs)
8768 + struct pt_regs * childregs;
8769 + struct task_struct *tsk;
8772 + childregs = task_pt_regs(p);
8773 + *childregs = *regs;
8774 + childregs->eax = 0;
8775 + childregs->esp = esp;
8777 + p->thread.esp = (unsigned long) childregs;
8778 + p->thread.esp0 = (unsigned long) (childregs+1);
8780 + p->thread.eip = (unsigned long) ret_from_fork;
8782 + savesegment(fs,p->thread.fs);
8783 + savesegment(gs,p->thread.gs);
8786 + if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
8787 + p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
8788 + if (!p->thread.io_bitmap_ptr) {
8789 + p->thread.io_bitmap_max = 0;
8792 + memcpy(p->thread.io_bitmap_ptr, tsk->thread.io_bitmap_ptr,
8794 + set_tsk_thread_flag(p, TIF_IO_BITMAP);
8798 + * Set a new TLS for the child thread?
8800 + if (clone_flags & CLONE_SETTLS) {
8801 + struct desc_struct *desc;
8802 + struct user_desc info;
8806 + if (copy_from_user(&info, (void __user *)childregs->esi, sizeof(info)))
8809 + if (LDT_empty(&info))
8812 + idx = info.entry_number;
8813 + if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
8816 + desc = p->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;
8817 + desc->a = LDT_entry_a(&info);
8818 + desc->b = LDT_entry_b(&info);
8821 + p->thread.iopl = current->thread.iopl;
8825 + if (err && p->thread.io_bitmap_ptr) {
8826 + kfree(p->thread.io_bitmap_ptr);
8827 + p->thread.io_bitmap_max = 0;
8833 + * fill in the user structure for a core dump..
8835 +void dump_thread(struct pt_regs * regs, struct user * dump)
8839 +/* changed the size calculations - should hopefully work better. lbt */
8840 + dump->magic = CMAGIC;
8841 + dump->start_code = 0;
8842 + dump->start_stack = regs->esp & ~(PAGE_SIZE - 1);
8843 + dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
8844 + dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT;
8845 + dump->u_dsize -= dump->u_tsize;
8846 + dump->u_ssize = 0;
8847 + for (i = 0; i < 8; i++)
8848 + dump->u_debugreg[i] = current->thread.debugreg[i];
8850 + if (dump->start_stack < TASK_SIZE)
8851 + dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
8853 + dump->regs.ebx = regs->ebx;
8854 + dump->regs.ecx = regs->ecx;
8855 + dump->regs.edx = regs->edx;
8856 + dump->regs.esi = regs->esi;
8857 + dump->regs.edi = regs->edi;
8858 + dump->regs.ebp = regs->ebp;
8859 + dump->regs.eax = regs->eax;
8860 + dump->regs.ds = regs->xds;
8861 + dump->regs.es = regs->xes;
8862 + savesegment(fs,dump->regs.fs);
8863 + savesegment(gs,dump->regs.gs);
8864 + dump->regs.orig_eax = regs->orig_eax;
8865 + dump->regs.eip = regs->eip;
8866 + dump->regs.cs = regs->xcs;
8867 + dump->regs.eflags = regs->eflags;
8868 + dump->regs.esp = regs->esp;
8869 + dump->regs.ss = regs->xss;
8871 + dump->u_fpvalid = dump_fpu (regs, &dump->i387);
8873 +EXPORT_SYMBOL(dump_thread);
8876 + * Capture the user space registers if the task is not running (in user space)
8878 +int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
8880 + struct pt_regs ptregs = *task_pt_regs(tsk);
8881 + ptregs.xcs &= 0xffff;
8882 + ptregs.xds &= 0xffff;
8883 + ptregs.xes &= 0xffff;
8884 + ptregs.xss &= 0xffff;
8886 + elf_core_copy_regs(regs, &ptregs);
8891 +static noinline void __switch_to_xtra(struct task_struct *next_p)
8893 + struct thread_struct *next;
8895 + next = &next_p->thread;
8897 + if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
8898 + set_debugreg(next->debugreg[0], 0);
8899 + set_debugreg(next->debugreg[1], 1);
8900 + set_debugreg(next->debugreg[2], 2);
8901 + set_debugreg(next->debugreg[3], 3);
8903 + set_debugreg(next->debugreg[6], 6);
8904 + set_debugreg(next->debugreg[7], 7);
8909 + * This function selects if the context switch from prev to next
8910 + * has to tweak the TSC disable bit in the cr4.
8912 +static inline void disable_tsc(struct task_struct *prev_p,
8913 + struct task_struct *next_p)
8915 + struct thread_info *prev, *next;
8918 + * gcc should eliminate the ->thread_info dereference if
8919 + * has_secure_computing returns 0 at compile time (SECCOMP=n).
8921 + prev = task_thread_info(prev_p);
8922 + next = task_thread_info(next_p);
8924 + if (has_secure_computing(prev) || has_secure_computing(next)) {
8925 + /* slow path here */
8926 + if (has_secure_computing(prev) &&
8927 + !has_secure_computing(next)) {
8928 + write_cr4(read_cr4() & ~X86_CR4_TSD);
8929 + } else if (!has_secure_computing(prev) &&
8930 + has_secure_computing(next))
8931 + write_cr4(read_cr4() | X86_CR4_TSD);
8936 + * switch_to(x,yn) should switch tasks from x to y.
8938 + * We fsave/fwait so that an exception goes off at the right time
8939 + * (as a call from the fsave or fwait in effect) rather than to
8940 + * the wrong process. Lazy FP saving no longer makes any sense
8941 + * with modern CPU's, and this simplifies a lot of things (SMP
8942 + * and UP become the same).
8944 + * NOTE! We used to use the x86 hardware context switching. The
8945 + * reason for not using it any more becomes apparent when you
8946 + * try to recover gracefully from saved state that is no longer
8947 + * valid (stale segment register values in particular). With the
8948 + * hardware task-switch, there is no way to fix up bad state in
8949 + * a reasonable manner.
8951 + * The fact that Intel documents the hardware task-switching to
8952 + * be slow is a fairly red herring - this code is not noticeably
8953 + * faster. However, there _is_ some room for improvement here,
8954 + * so the performance issues may eventually be a valid point.
8955 + * More important, however, is the fact that this allows us much
8956 + * more flexibility.
8958 + * The return value (in %eax) will be the "prev" task after
8959 + * the task-switch, and shows up in ret_from_fork in entry.S,
8962 +struct task_struct fastcall * __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
8964 + struct thread_struct *prev = &prev_p->thread,
8965 + *next = &next_p->thread;
8966 + int cpu = smp_processor_id();
8967 +#ifndef CONFIG_X86_NO_TSS
8968 + struct tss_struct *tss = &per_cpu(init_tss, cpu);
8970 +#if CONFIG_XEN_COMPAT > 0x030002
8971 + struct physdev_set_iopl iopl_op;
8972 + struct physdev_set_iobitmap iobmp_op;
8974 + struct physdev_op _pdo[2], *pdo = _pdo;
8975 +#define iopl_op pdo->u.set_iopl
8976 +#define iobmp_op pdo->u.set_iobitmap
8978 + multicall_entry_t _mcl[8], *mcl = _mcl;
8980 + /* XEN NOTE: FS/GS saved in switch_mm(), not here. */
8983 + * This is basically '__unlazy_fpu', except that we queue a
8984 + * multicall to indicate FPU task switch, rather than
8985 + * synchronously trapping to Xen.
8987 + if (prev_p->thread_info->status & TS_USEDFPU) {
8988 + __save_init_fpu(prev_p); /* _not_ save_init_fpu() */
8989 + mcl->op = __HYPERVISOR_fpu_taskswitch;
8993 +#if 0 /* lazy fpu sanity check */
8994 + else BUG_ON(!(read_cr0() & 8));
8999 + * This is load_esp0(tss, next) with a multicall.
9001 + mcl->op = __HYPERVISOR_stack_switch;
9002 + mcl->args[0] = __KERNEL_DS;
9003 + mcl->args[1] = next->esp0;
9007 + * Load the per-thread Thread-Local Storage descriptor.
9008 + * This is load_TLS(next, cpu) with multicalls.
9010 +#define C(i) do { \
9011 + if (unlikely(next->tls_array[i].a != prev->tls_array[i].a || \
9012 + next->tls_array[i].b != prev->tls_array[i].b)) { \
9013 + mcl->op = __HYPERVISOR_update_descriptor; \
9014 + *(u64 *)&mcl->args[0] = virt_to_machine( \
9015 + &get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i]);\
9016 + *(u64 *)&mcl->args[2] = *(u64 *)&next->tls_array[i]; \
9023 + if (unlikely(prev->iopl != next->iopl)) {
9024 + iopl_op.iopl = (next->iopl == 0) ? 1 : (next->iopl >> 12) & 3;
9025 +#if CONFIG_XEN_COMPAT > 0x030002
9026 + mcl->op = __HYPERVISOR_physdev_op;
9027 + mcl->args[0] = PHYSDEVOP_set_iopl;
9028 + mcl->args[1] = (unsigned long)&iopl_op;
9030 + mcl->op = __HYPERVISOR_physdev_op_compat;
9031 + pdo->cmd = PHYSDEVOP_set_iopl;
9032 + mcl->args[0] = (unsigned long)pdo++;
9037 + if (unlikely(prev->io_bitmap_ptr || next->io_bitmap_ptr)) {
9038 + set_xen_guest_handle(iobmp_op.bitmap,
9039 + (char *)next->io_bitmap_ptr);
9040 + iobmp_op.nr_ports = next->io_bitmap_ptr ? IO_BITMAP_BITS : 0;
9041 +#if CONFIG_XEN_COMPAT > 0x030002
9042 + mcl->op = __HYPERVISOR_physdev_op;
9043 + mcl->args[0] = PHYSDEVOP_set_iobitmap;
9044 + mcl->args[1] = (unsigned long)&iobmp_op;
9046 + mcl->op = __HYPERVISOR_physdev_op_compat;
9047 + pdo->cmd = PHYSDEVOP_set_iobitmap;
9048 + mcl->args[0] = (unsigned long)pdo++;
9053 +#if CONFIG_XEN_COMPAT <= 0x030002
9054 + BUG_ON(pdo > _pdo + ARRAY_SIZE(_pdo));
9056 + BUG_ON(mcl > _mcl + ARRAY_SIZE(_mcl));
9057 + if (unlikely(HYPERVISOR_multicall_check(_mcl, mcl - _mcl, NULL)))
9061 + * Restore %fs and %gs if needed.
9063 + * Glibc normally makes %fs be zero, and %gs is one of
9064 + * the TLS segments.
9066 + if (unlikely(next->fs))
9067 + loadsegment(fs, next->fs);
9070 + loadsegment(gs, next->gs);
9073 + * Now maybe handle debug registers
9075 + if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW))
9076 + __switch_to_xtra(next_p);
9078 + disable_tsc(prev_p, next_p);
9083 +asmlinkage int sys_fork(struct pt_regs regs)
9085 + return do_fork(SIGCHLD, regs.esp, ®s, 0, NULL, NULL);
9088 +asmlinkage int sys_clone(struct pt_regs regs)
9090 + unsigned long clone_flags;
9091 + unsigned long newsp;
9092 + int __user *parent_tidptr, *child_tidptr;
9094 + clone_flags = regs.ebx;
9096 + parent_tidptr = (int __user *)regs.edx;
9097 + child_tidptr = (int __user *)regs.edi;
9100 + return do_fork(clone_flags, newsp, ®s, 0, parent_tidptr, child_tidptr);
9104 + * This is trivial, and on the face of it looks like it
9105 + * could equally well be done in user mode.
9107 + * Not so, for quite unobvious reasons - register pressure.
9108 + * In user mode vfork() cannot have a stack frame, and if
9109 + * done by calling the "clone()" system call directly, you
9110 + * do not have enough call-clobbered registers to hold all
9111 + * the information you need.
9113 +asmlinkage int sys_vfork(struct pt_regs regs)
9115 + return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs.esp, ®s, 0, NULL, NULL);
9119 + * sys_execve() executes a new program.
9121 +asmlinkage int sys_execve(struct pt_regs regs)
9126 + filename = getname((char __user *) regs.ebx);
9127 + error = PTR_ERR(filename);
9128 + if (IS_ERR(filename))
9130 + error = do_execve(filename,
9131 + (char __user * __user *) regs.ecx,
9132 + (char __user * __user *) regs.edx,
9135 + task_lock(current);
9136 + current->ptrace &= ~PT_DTRACE;
9137 + task_unlock(current);
9138 + /* Make sure we don't return using sysenter.. */
9139 + set_thread_flag(TIF_IRET);
9141 + putname(filename);
9146 +#define top_esp (THREAD_SIZE - sizeof(unsigned long))
9147 +#define top_ebp (THREAD_SIZE - 2*sizeof(unsigned long))
9149 +unsigned long get_wchan(struct task_struct *p)
9151 + unsigned long ebp, esp, eip;
9152 + unsigned long stack_page;
9154 + if (!p || p == current || p->state == TASK_RUNNING)
9156 + stack_page = (unsigned long)task_stack_page(p);
9157 + esp = p->thread.esp;
9158 + if (!stack_page || esp < stack_page || esp > top_esp+stack_page)
9160 + /* include/asm-i386/system.h:switch_to() pushes ebp last. */
9161 + ebp = *(unsigned long *) esp;
9163 + if (ebp < stack_page || ebp > top_ebp+stack_page)
9165 + eip = *(unsigned long *) (ebp+4);
9166 + if (!in_sched_functions(eip))
9168 + ebp = *(unsigned long *) ebp;
9169 + } while (count++ < 16);
9174 + * sys_alloc_thread_area: get a yet unused TLS descriptor index.
9176 +static int get_free_idx(void)
9178 + struct thread_struct *t = ¤t->thread;
9181 + for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++)
9182 + if (desc_empty(t->tls_array + idx))
9183 + return idx + GDT_ENTRY_TLS_MIN;
9188 + * Set a given TLS descriptor:
9190 +asmlinkage int sys_set_thread_area(struct user_desc __user *u_info)
9192 + struct thread_struct *t = ¤t->thread;
9193 + struct user_desc info;
9194 + struct desc_struct *desc;
9197 + if (copy_from_user(&info, u_info, sizeof(info)))
9199 + idx = info.entry_number;
9202 + * index -1 means the kernel should try to find and
9203 + * allocate an empty descriptor:
9206 + idx = get_free_idx();
9209 + if (put_user(idx, &u_info->entry_number))
9213 + if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
9216 + desc = t->tls_array + idx - GDT_ENTRY_TLS_MIN;
9219 + * We must not get preempted while modifying the TLS.
9223 + if (LDT_empty(&info)) {
9227 + desc->a = LDT_entry_a(&info);
9228 + desc->b = LDT_entry_b(&info);
9238 + * Get the current Thread-Local Storage area:
9241 +#define GET_BASE(desc) ( \
9242 + (((desc)->a >> 16) & 0x0000ffff) | \
9243 + (((desc)->b << 16) & 0x00ff0000) | \
9244 + ( (desc)->b & 0xff000000) )
9246 +#define GET_LIMIT(desc) ( \
9247 + ((desc)->a & 0x0ffff) | \
9248 + ((desc)->b & 0xf0000) )
9250 +#define GET_32BIT(desc) (((desc)->b >> 22) & 1)
9251 +#define GET_CONTENTS(desc) (((desc)->b >> 10) & 3)
9252 +#define GET_WRITABLE(desc) (((desc)->b >> 9) & 1)
9253 +#define GET_LIMIT_PAGES(desc) (((desc)->b >> 23) & 1)
9254 +#define GET_PRESENT(desc) (((desc)->b >> 15) & 1)
9255 +#define GET_USEABLE(desc) (((desc)->b >> 20) & 1)
9257 +asmlinkage int sys_get_thread_area(struct user_desc __user *u_info)
9259 + struct user_desc info;
9260 + struct desc_struct *desc;
9263 + if (get_user(idx, &u_info->entry_number))
9265 + if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
9268 + memset(&info, 0, sizeof(info));
9270 + desc = current->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;
9272 + info.entry_number = idx;
9273 + info.base_addr = GET_BASE(desc);
9274 + info.limit = GET_LIMIT(desc);
9275 + info.seg_32bit = GET_32BIT(desc);
9276 + info.contents = GET_CONTENTS(desc);
9277 + info.read_exec_only = !GET_WRITABLE(desc);
9278 + info.limit_in_pages = GET_LIMIT_PAGES(desc);
9279 + info.seg_not_present = !GET_PRESENT(desc);
9280 + info.useable = GET_USEABLE(desc);
9282 + if (copy_to_user(u_info, &info, sizeof(info)))
9287 +unsigned long arch_align_stack(unsigned long sp)
9289 + if (randomize_va_space)
9290 + sp -= get_random_int() % 8192;
9293 Index: head-2008-11-25/arch/x86/kernel/quirks-xen.c
9294 ===================================================================
9295 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9296 +++ head-2008-11-25/arch/x86/kernel/quirks-xen.c 2008-01-28 12:24:19.000000000 +0100
9299 + * This file contains work-arounds for x86 and x86_64 platform bugs.
9301 +#include <linux/pci.h>
9302 +#include <linux/irq.h>
9304 +#if defined(CONFIG_X86_IO_APIC) && (defined(CONFIG_SMP) || defined(CONFIG_XEN)) && defined(CONFIG_PCI)
9306 +static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
9311 + /* BIOS may enable hardware IRQ balancing for
9312 + * E7520/E7320/E7525(revision ID 0x9 and below)
9313 + * based platforms.
9314 + * Disable SW irqbalance/affinity on those platforms.
9316 + pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
9320 + printk(KERN_INFO "Intel E7520/7320/7525 detected.");
9322 + /* enable access to config space*/
9323 + pci_read_config_byte(dev, 0xf4, &config);
9324 + pci_write_config_byte(dev, 0xf4, config|0x2);
9326 + /* read xTPR register */
9327 + raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);
9329 + if (!(word & (1 << 13))) {
9330 + struct xen_platform_op op;
9331 + printk(KERN_INFO "Disabling irq balancing and affinity\n");
9332 + op.cmd = XENPF_platform_quirk;
9333 + op.u.platform_quirk.quirk_id = QUIRK_NOIRQBALANCING;
9334 + WARN_ON(HYPERVISOR_platform_op(&op));
9337 + /* put back the original value for config space*/
9338 + if (!(config & 0x2))
9339 + pci_write_config_byte(dev, 0xf4, config);
9341 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_intel_irqbalance);
9342 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_intel_irqbalance);
9343 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_intel_irqbalance);
9345 Index: head-2008-11-25/arch/x86/kernel/setup_32-xen.c
9346 ===================================================================
9347 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9348 +++ head-2008-11-25/arch/x86/kernel/setup_32-xen.c 2008-04-22 15:41:51.000000000 +0200
9351 + * linux/arch/i386/kernel/setup.c
9353 + * Copyright (C) 1995 Linus Torvalds
9355 + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
9357 + * Memory region support
9358 + * David Parsons <orc@pell.chi.il.us>, July-August 1999
9360 + * Added E820 sanitization routine (removes overlapping memory regions);
9361 + * Brian Moyle <bmoyle@mvista.com>, February 2001
9363 + * Moved CPU detection code to cpu/${cpu}.c
9364 + * Patrick Mochel <mochel@osdl.org>, March 2002
9366 + * Provisions for empty E820 memory regions (reported by certain BIOSes).
9367 + * Alex Achenbach <xela@slit.de>, December 2002.
9372 + * This file handles the architecture-dependent parts of initialization
9375 +#include <linux/sched.h>
9376 +#include <linux/mm.h>
9377 +#include <linux/mmzone.h>
9378 +#include <linux/screen_info.h>
9379 +#include <linux/ioport.h>
9380 +#include <linux/acpi.h>
9381 +#include <linux/apm_bios.h>
9382 +#include <linux/initrd.h>
9383 +#include <linux/bootmem.h>
9384 +#include <linux/seq_file.h>
9385 +#include <linux/platform_device.h>
9386 +#include <linux/console.h>
9387 +#include <linux/mca.h>
9388 +#include <linux/root_dev.h>
9389 +#include <linux/highmem.h>
9390 +#include <linux/module.h>
9391 +#include <linux/efi.h>
9392 +#include <linux/init.h>
9393 +#include <linux/edd.h>
9394 +#include <linux/nodemask.h>
9395 +#include <linux/kernel.h>
9396 +#include <linux/percpu.h>
9397 +#include <linux/notifier.h>
9398 +#include <linux/kexec.h>
9399 +#include <linux/crash_dump.h>
9400 +#include <linux/dmi.h>
9401 +#include <linux/pfn.h>
9403 +#include <video/edid.h>
9405 +#include <asm/apic.h>
9406 +#include <asm/e820.h>
9407 +#include <asm/mpspec.h>
9408 +#include <asm/setup.h>
9409 +#include <asm/arch_hooks.h>
9410 +#include <asm/sections.h>
9411 +#include <asm/io_apic.h>
9412 +#include <asm/ist.h>
9413 +#include <asm/io.h>
9414 +#include <asm/hypervisor.h>
9415 +#include <xen/interface/physdev.h>
9416 +#include <xen/interface/memory.h>
9417 +#include <xen/features.h>
9418 +#include <xen/firmware.h>
9419 +#include <xen/xencons.h>
9420 +#include <setup_arch.h>
9421 +#include <bios_ebda.h>
9424 +#include <xen/interface/kexec.h>
9427 +/* Forward Declaration. */
9428 +void __init find_max_pfn(void);
9430 +static int xen_panic_event(struct notifier_block *, unsigned long, void *);
9431 +static struct notifier_block xen_panic_block = {
9432 + xen_panic_event, NULL, 0 /* try to go last */
9435 +extern char hypercall_page[PAGE_SIZE];
9436 +EXPORT_SYMBOL(hypercall_page);
9438 +int disable_pse __devinitdata = 0;
9445 +int efi_enabled = 0;
9446 +EXPORT_SYMBOL(efi_enabled);
9449 +/* cpu data as detected by the assembly code in head.S */
9450 +struct cpuinfo_x86 new_cpu_data __initdata = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
9451 +/* common cpu data for all cpus */
9452 +struct cpuinfo_x86 boot_cpu_data __read_mostly = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
9453 +EXPORT_SYMBOL(boot_cpu_data);
9455 +unsigned long mmu_cr4_features;
9458 + int acpi_disabled = 0;
9460 + int acpi_disabled = 1;
9462 +EXPORT_SYMBOL(acpi_disabled);
9465 +int __initdata acpi_force = 0;
9466 +extern acpi_interrupt_flags acpi_sci_flags;
9469 +/* for MCA, but anyone else can use it if they want */
9470 +unsigned int machine_id;
9472 +EXPORT_SYMBOL(machine_id);
9474 +unsigned int machine_submodel_id;
9475 +unsigned int BIOS_revision;
9476 +unsigned int mca_pentium_flag;
9478 +/* For PCI or other memory-mapped resources */
9479 +unsigned long pci_mem_start = 0x10000000;
9481 +EXPORT_SYMBOL(pci_mem_start);
9484 +/* Boot loader ID as an integer, for the benefit of proc_dointvec */
9485 +int bootloader_type;
9487 +/* user-defined highmem size */
9488 +static unsigned int highmem_pages = -1;
9493 +struct drive_info_struct { char dummy[32]; } drive_info;
9494 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_HD) || \
9495 + defined(CONFIG_BLK_DEV_IDE_MODULE) || defined(CONFIG_BLK_DEV_HD_MODULE)
9496 +EXPORT_SYMBOL(drive_info);
9498 +struct screen_info screen_info;
9499 +EXPORT_SYMBOL(screen_info);
9500 +struct apm_info apm_info;
9501 +EXPORT_SYMBOL(apm_info);
9502 +struct sys_desc_table_struct {
9503 + unsigned short length;
9504 + unsigned char table[0];
9506 +struct edid_info edid_info;
9507 +EXPORT_SYMBOL_GPL(edid_info);
9509 +#define copy_edid() (edid_info = EDID_INFO)
9511 +struct ist_info ist_info;
9512 +#if defined(CONFIG_X86_SPEEDSTEP_SMI) || \
9513 + defined(CONFIG_X86_SPEEDSTEP_SMI_MODULE)
9514 +EXPORT_SYMBOL(ist_info);
9516 +struct e820map e820;
9518 +struct e820map machine_e820;
9521 +extern void early_cpu_init(void);
9522 +extern void generic_apic_probe(char *);
9523 +extern int root_mountflags;
9525 +unsigned long saved_videomode;
9527 +#define RAMDISK_IMAGE_START_MASK 0x07FF
9528 +#define RAMDISK_PROMPT_FLAG 0x8000
9529 +#define RAMDISK_LOAD_FLAG 0x4000
9531 +static char command_line[COMMAND_LINE_SIZE];
9533 +unsigned char __initdata boot_params[PARAM_SIZE];
9535 +static struct resource data_resource = {
9536 + .name = "Kernel data",
9539 + .flags = IORESOURCE_BUSY | IORESOURCE_MEM
9542 +static struct resource code_resource = {
9543 + .name = "Kernel code",
9546 + .flags = IORESOURCE_BUSY | IORESOURCE_MEM
9549 +static struct resource system_rom_resource = {
9550 + .name = "System ROM",
9553 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9556 +static struct resource extension_rom_resource = {
9557 + .name = "Extension ROM",
9560 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9563 +static struct resource adapter_rom_resources[] = { {
9564 + .name = "Adapter ROM",
9567 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9569 + .name = "Adapter ROM",
9572 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9574 + .name = "Adapter ROM",
9577 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9579 + .name = "Adapter ROM",
9582 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9584 + .name = "Adapter ROM",
9587 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9589 + .name = "Adapter ROM",
9592 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9595 +#define ADAPTER_ROM_RESOURCES \
9596 + (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
9598 +static struct resource video_rom_resource = {
9599 + .name = "Video ROM",
9602 + .flags = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
9605 +static struct resource video_ram_resource = {
9606 + .name = "Video RAM area",
9609 + .flags = IORESOURCE_BUSY | IORESOURCE_MEM
9612 +static struct resource standard_io_resources[] = { {
9616 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9621 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9626 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9631 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9633 + .name = "keyboard",
9636 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9638 + .name = "dma page reg",
9641 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9646 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9651 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9656 + .flags = IORESOURCE_BUSY | IORESOURCE_IO
9659 +#define STANDARD_IO_RESOURCES \
9660 + (sizeof standard_io_resources / sizeof standard_io_resources[0])
9662 +#define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
9664 +static int __init romchecksum(unsigned char *rom, unsigned long length)
9666 + unsigned char *p, sum = 0;
9668 + for (p = rom; p < rom + length; p++)
9673 +static void __init probe_roms(void)
9675 + unsigned long start, length, upper;
9676 + unsigned char *rom;
9680 + /* Nothing to do if not running in dom0. */
9681 + if (!is_initial_xendomain())
9686 + upper = adapter_rom_resources[0].start;
9687 + for (start = video_rom_resource.start; start < upper; start += 2048) {
9688 + rom = isa_bus_to_virt(start);
9689 + if (!romsignature(rom))
9692 + video_rom_resource.start = start;
9694 + /* 0 < length <= 0x7f * 512, historically */
9695 + length = rom[2] * 512;
9697 + /* if checksum okay, trust length byte */
9698 + if (length && romchecksum(rom, length))
9699 + video_rom_resource.end = start + length - 1;
9701 + request_resource(&iomem_resource, &video_rom_resource);
9705 + start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
9706 + if (start < upper)
9710 + request_resource(&iomem_resource, &system_rom_resource);
9711 + upper = system_rom_resource.start;
9713 + /* check for extension rom (ignore length byte!) */
9714 + rom = isa_bus_to_virt(extension_rom_resource.start);
9715 + if (romsignature(rom)) {
9716 + length = extension_rom_resource.end - extension_rom_resource.start + 1;
9717 + if (romchecksum(rom, length)) {
9718 + request_resource(&iomem_resource, &extension_rom_resource);
9719 + upper = extension_rom_resource.start;
9723 + /* check for adapter roms on 2k boundaries */
9724 + for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
9725 + rom = isa_bus_to_virt(start);
9726 + if (!romsignature(rom))
9729 + /* 0 < length <= 0x7f * 512, historically */
9730 + length = rom[2] * 512;
9732 + /* but accept any length that fits if checksum okay */
9733 + if (!length || start + length > upper || !romchecksum(rom, length))
9736 + adapter_rom_resources[i].start = start;
9737 + adapter_rom_resources[i].end = start + length - 1;
9738 + request_resource(&iomem_resource, &adapter_rom_resources[i]);
9740 + start = adapter_rom_resources[i++].end & ~2047UL;
9745 + * Point at the empty zero page to start with. We map the real shared_info
9746 + * page as soon as fixmap is up and running.
9748 +shared_info_t *HYPERVISOR_shared_info = (shared_info_t *)empty_zero_page;
9749 +EXPORT_SYMBOL(HYPERVISOR_shared_info);
9751 +unsigned long *phys_to_machine_mapping;
9752 +unsigned long *pfn_to_mfn_frame_list_list, *pfn_to_mfn_frame_list[16];
9753 +EXPORT_SYMBOL(phys_to_machine_mapping);
9755 +/* Raw start-of-day parameters from the hypervisor. */
9756 +start_info_t *xen_start_info;
9757 +EXPORT_SYMBOL(xen_start_info);
9759 +void __init add_memory_region(unsigned long long start,
9760 + unsigned long long size, int type)
9764 + if (!efi_enabled) {
9767 + if (x == E820MAX) {
9768 + printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
9772 + e820.map[x].addr = start;
9773 + e820.map[x].size = size;
9774 + e820.map[x].type = type;
9777 +} /* add_memory_region */
9779 +static void __init limit_regions(unsigned long long size)
9781 + unsigned long long current_addr = 0;
9784 + if (efi_enabled) {
9785 + efi_memory_desc_t *md;
9788 + for (p = memmap.map, i = 0; p < memmap.map_end;
9789 + p += memmap.desc_size, i++) {
9791 + current_addr = md->phys_addr + (md->num_pages << 12);
9792 + if (md->type == EFI_CONVENTIONAL_MEMORY) {
9793 + if (current_addr >= size) {
9795 + (((current_addr-size) + PAGE_SIZE-1) >> PAGE_SHIFT);
9796 + memmap.nr_map = i + 1;
9802 + for (i = 0; i < e820.nr_map; i++) {
9803 + current_addr = e820.map[i].addr + e820.map[i].size;
9804 + if (current_addr < size)
9807 + if (e820.map[i].type != E820_RAM)
9810 + if (e820.map[i].addr >= size) {
9812 + * This region starts past the end of the
9813 + * requested size, skip it completely.
9817 + e820.nr_map = i + 1;
9818 + e820.map[i].size -= current_addr - size;
9823 + if (i==e820.nr_map && current_addr < size) {
9825 + * The e820 map finished before our requested size so
9826 + * extend the final entry to the requested address.
9829 + if (e820.map[i].type == E820_RAM)
9830 + e820.map[i].size -= current_addr - size;
9832 + add_memory_region(current_addr, size - current_addr, E820_RAM);
9837 +#define E820_DEBUG 1
9839 +static void __init print_memory_map(char *who)
9843 + for (i = 0; i < e820.nr_map; i++) {
9844 + printk(" %s: %016Lx - %016Lx ", who,
9846 + e820.map[i].addr + e820.map[i].size);
9847 + switch (e820.map[i].type) {
9848 + case E820_RAM: printk("(usable)\n");
9850 + case E820_RESERVED:
9851 + printk("(reserved)\n");
9854 + printk("(ACPI data)\n");
9857 + printk("(ACPI NVS)\n");
9859 + default: printk("type %lu\n", e820.map[i].type);
9866 + * Sanitize the BIOS e820 map.
9868 + * Some e820 responses include overlapping entries. The following
9869 + * replaces the original e820 map with a new one, removing overlaps.
9872 +struct change_member {
9873 + struct e820entry *pbios; /* pointer to original bios entry */
9874 + unsigned long long addr; /* address for this change point */
9876 +static struct change_member change_point_list[2*E820MAX] __initdata;
9877 +static struct change_member *change_point[2*E820MAX] __initdata;
9878 +static struct e820entry *overlap_list[E820MAX] __initdata;
9879 +static struct e820entry new_bios[E820MAX] __initdata;
9881 +int __init sanitize_e820_map(struct e820entry * biosmap, char * pnr_map)
9883 + struct change_member *change_tmp;
9884 + unsigned long current_type, last_type;
9885 + unsigned long long last_addr;
9886 + int chgidx, still_changing;
9887 + int overlap_entries;
9888 + int new_bios_entry;
9889 + int old_nr, new_nr, chg_nr;
9893 + Visually we're performing the following (1,2,3,4 = memory types)...
9895 + Sample memory map (w/overlaps):
9896 + ____22__________________
9897 + ______________________4_
9898 + ____1111________________
9899 + _44_____________________
9900 + 11111111________________
9901 + ____________________33__
9902 + ___________44___________
9903 + __________33333_________
9904 + ______________22________
9905 + ___________________2222_
9906 + _________111111111______
9907 + _____________________11_
9908 + _________________4______
9910 + Sanitized equivalent (no overlap):
9911 + 1_______________________
9912 + _44_____________________
9913 + ___1____________________
9914 + ____22__________________
9915 + ______11________________
9916 + _________1______________
9917 + __________3_____________
9918 + ___________44___________
9919 + _____________33_________
9920 + _______________2________
9921 + ________________1_______
9922 + _________________4______
9923 + ___________________2____
9924 + ____________________33__
9925 + ______________________4_
9928 + /* if there's only one memory region, don't bother */
9932 + old_nr = *pnr_map;
9934 + /* bail out if we find any unreasonable addresses in bios map */
9935 + for (i=0; i<old_nr; i++)
9936 + if (biosmap[i].addr + biosmap[i].size < biosmap[i].addr)
9939 + /* create pointers for initial change-point information (for sorting) */
9940 + for (i=0; i < 2*old_nr; i++)
9941 + change_point[i] = &change_point_list[i];
9943 + /* record all known change-points (starting and ending addresses),
9944 + omitting those that are for empty memory regions */
9946 + for (i=0; i < old_nr; i++) {
9947 + if (biosmap[i].size != 0) {
9948 + change_point[chgidx]->addr = biosmap[i].addr;
9949 + change_point[chgidx++]->pbios = &biosmap[i];
9950 + change_point[chgidx]->addr = biosmap[i].addr + biosmap[i].size;
9951 + change_point[chgidx++]->pbios = &biosmap[i];
9954 + chg_nr = chgidx; /* true number of change-points */
9956 + /* sort change-point list by memory addresses (low -> high) */
9957 + still_changing = 1;
9958 + while (still_changing) {
9959 + still_changing = 0;
9960 + for (i=1; i < chg_nr; i++) {
9961 + /* if <current_addr> > <last_addr>, swap */
9962 + /* or, if current=<start_addr> & last=<end_addr>, swap */
9963 + if ((change_point[i]->addr < change_point[i-1]->addr) ||
9964 + ((change_point[i]->addr == change_point[i-1]->addr) &&
9965 + (change_point[i]->addr == change_point[i]->pbios->addr) &&
9966 + (change_point[i-1]->addr != change_point[i-1]->pbios->addr))
9969 + change_tmp = change_point[i];
9970 + change_point[i] = change_point[i-1];
9971 + change_point[i-1] = change_tmp;
9977 + /* create a new bios memory map, removing overlaps */
9978 + overlap_entries=0; /* number of entries in the overlap table */
9979 + new_bios_entry=0; /* index for creating new bios map entries */
9980 + last_type = 0; /* start with undefined memory type */
9981 + last_addr = 0; /* start with 0 as last starting address */
9982 + /* loop through change-points, determining affect on the new bios map */
9983 + for (chgidx=0; chgidx < chg_nr; chgidx++)
9985 + /* keep track of all overlapping bios entries */
9986 + if (change_point[chgidx]->addr == change_point[chgidx]->pbios->addr)
9988 + /* add map entry to overlap list (> 1 entry implies an overlap) */
9989 + overlap_list[overlap_entries++]=change_point[chgidx]->pbios;
9993 + /* remove entry from list (order independent, so swap with last) */
9994 + for (i=0; i<overlap_entries; i++)
9996 + if (overlap_list[i] == change_point[chgidx]->pbios)
9997 + overlap_list[i] = overlap_list[overlap_entries-1];
9999 + overlap_entries--;
10001 + /* if there are overlapping entries, decide which "type" to use */
10002 + /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
10003 + current_type = 0;
10004 + for (i=0; i<overlap_entries; i++)
10005 + if (overlap_list[i]->type > current_type)
10006 + current_type = overlap_list[i]->type;
10007 + /* continue building up new bios map based on this information */
10008 + if (current_type != last_type) {
10009 + if (last_type != 0) {
10010 + new_bios[new_bios_entry].size =
10011 + change_point[chgidx]->addr - last_addr;
10012 + /* move forward only if the new size was non-zero */
10013 + if (new_bios[new_bios_entry].size != 0)
10014 + if (++new_bios_entry >= E820MAX)
10015 + break; /* no more space left for new bios entries */
10017 + if (current_type != 0) {
10018 + new_bios[new_bios_entry].addr = change_point[chgidx]->addr;
10019 + new_bios[new_bios_entry].type = current_type;
10020 + last_addr=change_point[chgidx]->addr;
10022 + last_type = current_type;
10025 + new_nr = new_bios_entry; /* retain count for new bios entries */
10027 + /* copy new bios mapping into original location */
10028 + memcpy(biosmap, new_bios, new_nr*sizeof(struct e820entry));
10029 + *pnr_map = new_nr;
10035 + * Copy the BIOS e820 map into a safe place.
10037 + * Sanity-check it while we're at it..
10039 + * If we're lucky and live on a modern system, the setup code
10040 + * will have given us a memory map that we can use to properly
10041 + * set up memory. If we aren't, we'll fake a memory map.
10043 + * We check to see that the memory map contains at least 2 elements
10044 + * before we'll use it, because the detection code in setup.S may
10045 + * not be perfect and most every PC known to man has two memory
10046 + * regions: one from 0 to 640k, and one from 1mb up. (The IBM
10047 + * thinkpad 560x, for example, does not cooperate with the memory
10048 + * detection code.)
10050 +int __init copy_e820_map(struct e820entry * biosmap, int nr_map)
10052 +#ifndef CONFIG_XEN
10053 + /* Only one memory region (or negative)? Ignore it */
10057 + BUG_ON(nr_map < 1);
10061 + unsigned long long start = biosmap->addr;
10062 + unsigned long long size = biosmap->size;
10063 + unsigned long long end = start + size;
10064 + unsigned long type = biosmap->type;
10066 + /* Overflow in 64 bits? Ignore the memory map. */
10070 +#ifndef CONFIG_XEN
10072 + * Some BIOSes claim RAM in the 640k - 1M region.
10073 + * Not right. Fix it up.
10075 + if (type == E820_RAM) {
10076 + if (start < 0x100000ULL && end > 0xA0000ULL) {
10077 + if (start < 0xA0000ULL)
10078 + add_memory_region(start, 0xA0000ULL-start, type);
10079 + if (end <= 0x100000ULL)
10081 + start = 0x100000ULL;
10082 + size = end - start;
10086 + add_memory_region(start, size, type);
10087 + } while (biosmap++,--nr_map);
10090 + if (is_initial_xendomain()) {
10091 + struct xen_memory_map memmap;
10093 + memmap.nr_entries = E820MAX;
10094 + set_xen_guest_handle(memmap.buffer, machine_e820.map);
10096 + if (HYPERVISOR_memory_op(XENMEM_machine_memory_map, &memmap))
10098 + machine_e820.nr_map = memmap.nr_entries;
10100 + machine_e820 = e820;
10106 +#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
10108 +#ifdef CONFIG_EDD_MODULE
10109 +EXPORT_SYMBOL(edd);
10111 +#ifndef CONFIG_XEN
10113 + * copy_edd() - Copy the BIOS EDD information
10114 + * from boot_params into a safe place.
10117 +static inline void copy_edd(void)
10119 + memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
10120 + memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
10121 + edd.mbr_signature_nr = EDD_MBR_SIG_NR;
10122 + edd.edd_info_nr = EDD_NR;
10126 +static inline void copy_edd(void)
10131 +static void __init parse_cmdline_early (char ** cmdline_p)
10133 + char c = ' ', *to = command_line, *from = saved_command_line;
10134 + int len = 0, max_cmdline;
10137 + if ((max_cmdline = MAX_GUEST_CMDLINE) > COMMAND_LINE_SIZE)
10138 + max_cmdline = COMMAND_LINE_SIZE;
10139 + memcpy(saved_command_line, xen_start_info->cmd_line, max_cmdline);
10140 + /* Save unparsed command line copy for /proc/cmdline */
10141 + saved_command_line[max_cmdline-1] = '\0';
10147 + * "mem=nopentium" disables the 4MB page tables.
10148 + * "mem=XXX[kKmM]" defines a memory region from HIGH_MEM
10149 + * to <mem>, overriding the bios size.
10150 + * "memmap=XXX[KkmM]@XXX[KkmM]" defines a memory region from
10151 + * <start> to <start>+<mem>, overriding the bios size.
10153 + * HPA tells me bootloaders need to parse mem=, so no new
10154 + * option should be mem= [also see Documentation/i386/boot.txt]
10156 + if (!memcmp(from, "mem=", 4)) {
10157 + if (to != command_line)
10159 + if (!memcmp(from+4, "nopentium", 9)) {
10161 + clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
10164 + /* If the user specifies memory size, we
10165 + * limit the BIOS-provided memory map to
10166 + * that size. exactmap can be used to specify
10167 + * the exact map. mem=number can be used to
10168 + * trim the existing memory map.
10170 + unsigned long long mem_size;
10172 + mem_size = memparse(from+4, &from);
10173 + limit_regions(mem_size);
10178 + else if (!memcmp(from, "memmap=", 7)) {
10179 + if (to != command_line)
10181 + if (!memcmp(from+7, "exactmap", 8)) {
10182 +#ifdef CONFIG_CRASH_DUMP
10183 + /* If we are doing a crash dump, we
10184 + * still need to know the real mem
10185 + * size before original memory map is
10189 + saved_max_pfn = max_pfn;
10195 + /* If the user specifies memory size, we
10196 + * limit the BIOS-provided memory map to
10197 + * that size. exactmap can be used to specify
10198 + * the exact map. mem=number can be used to
10199 + * trim the existing memory map.
10201 + unsigned long long start_at, mem_size;
10203 + mem_size = memparse(from+7, &from);
10204 + if (*from == '@') {
10205 + start_at = memparse(from+1, &from);
10206 + add_memory_region(start_at, mem_size, E820_RAM);
10207 + } else if (*from == '#') {
10208 + start_at = memparse(from+1, &from);
10209 + add_memory_region(start_at, mem_size, E820_ACPI);
10210 + } else if (*from == '$') {
10211 + start_at = memparse(from+1, &from);
10212 + add_memory_region(start_at, mem_size, E820_RESERVED);
10214 + limit_regions(mem_size);
10220 + else if (!memcmp(from, "noexec=", 7))
10221 + noexec_setup(from + 7);
10224 +#ifdef CONFIG_X86_MPPARSE
10226 + * If the BIOS enumerates physical processors before logical,
10227 + * maxcpus=N at enumeration-time can be used to disable HT.
10229 + else if (!memcmp(from, "maxcpus=", 8)) {
10230 + extern unsigned int maxcpus;
10232 + maxcpus = simple_strtoul(from + 8, NULL, 0);
10236 +#ifdef CONFIG_ACPI
10237 + /* "acpi=off" disables both ACPI table parsing and interpreter */
10238 + else if (!memcmp(from, "acpi=off", 8)) {
10242 + /* acpi=force to over-ride black-list */
10243 + else if (!memcmp(from, "acpi=force", 10)) {
10246 + acpi_disabled = 0;
10249 + /* acpi=strict disables out-of-spec workarounds */
10250 + else if (!memcmp(from, "acpi=strict", 11)) {
10254 + /* Limit ACPI just to boot-time to enable HT */
10255 + else if (!memcmp(from, "acpi=ht", 7)) {
10261 + /* "pci=noacpi" disable ACPI IRQ routing and PCI scan */
10262 + else if (!memcmp(from, "pci=noacpi", 10)) {
10263 + acpi_disable_pci();
10265 + /* "acpi=noirq" disables ACPI interrupt routing */
10266 + else if (!memcmp(from, "acpi=noirq", 10)) {
10267 + acpi_noirq_set();
10270 + else if (!memcmp(from, "acpi_sci=edge", 13))
10271 + acpi_sci_flags.trigger = 1;
10273 + else if (!memcmp(from, "acpi_sci=level", 14))
10274 + acpi_sci_flags.trigger = 3;
10276 + else if (!memcmp(from, "acpi_sci=high", 13))
10277 + acpi_sci_flags.polarity = 1;
10279 + else if (!memcmp(from, "acpi_sci=low", 12))
10280 + acpi_sci_flags.polarity = 3;
10282 +#ifdef CONFIG_X86_IO_APIC
10283 + else if (!memcmp(from, "acpi_skip_timer_override", 24))
10284 + acpi_skip_timer_override = 1;
10286 + if (!memcmp(from, "disable_timer_pin_1", 19))
10287 + disable_timer_pin_1 = 1;
10288 + if (!memcmp(from, "enable_timer_pin_1", 18))
10289 + disable_timer_pin_1 = -1;
10291 + /* disable IO-APIC */
10292 + else if (!memcmp(from, "noapic", 6))
10293 + disable_ioapic_setup();
10294 +#endif /* CONFIG_X86_IO_APIC */
10295 +#endif /* CONFIG_ACPI */
10297 +#ifdef CONFIG_X86_LOCAL_APIC
10298 + /* enable local APIC */
10299 + else if (!memcmp(from, "lapic", 5))
10302 + /* disable local APIC */
10303 + else if (!memcmp(from, "nolapic", 6))
10305 +#endif /* CONFIG_X86_LOCAL_APIC */
10307 +#ifdef CONFIG_KEXEC
10308 + /* crashkernel=size@addr specifies the location to reserve for
10309 + * a crash kernel. By reserving this memory we guarantee
10310 + * that linux never set's it up as a DMA target.
10311 + * Useful for holding code to do something appropriate
10312 + * after a kernel panic.
10314 + else if (!memcmp(from, "crashkernel=", 12)) {
10315 +#ifndef CONFIG_XEN
10316 + unsigned long size, base;
10317 + size = memparse(from+12, &from);
10318 + if (*from == '@') {
10319 + base = memparse(from+1, &from);
10320 + /* FIXME: Do I want a sanity check
10321 + * to validate the memory range?
10323 + crashk_res.start = base;
10324 + crashk_res.end = base + size - 1;
10327 + printk("Ignoring crashkernel command line, "
10328 + "parameter will be supplied by xen\n");
10332 +#ifdef CONFIG_PROC_VMCORE
10333 + /* elfcorehdr= specifies the location of elf core header
10334 + * stored by the crashed kernel.
10336 + else if (!memcmp(from, "elfcorehdr=", 11))
10337 + elfcorehdr_addr = memparse(from+11, &from);
10341 + * highmem=size forces highmem to be exactly 'size' bytes.
10342 + * This works even on boxes that have no highmem otherwise.
10343 + * This also works to reduce highmem size on bigger boxes.
10345 + else if (!memcmp(from, "highmem=", 8))
10346 + highmem_pages = memparse(from+8, &from) >> PAGE_SHIFT;
10349 + * vmalloc=size forces the vmalloc area to be exactly 'size'
10350 + * bytes. This can be used to increase (or decrease) the
10351 + * vmalloc area - the default is 128m.
10353 + else if (!memcmp(from, "vmalloc=", 8))
10354 + __VMALLOC_RESERVE = memparse(from+8, &from);
10360 + if (COMMAND_LINE_SIZE <= ++len)
10365 + *cmdline_p = command_line;
10367 + printk(KERN_INFO "user-defined physical RAM map:\n");
10368 + print_memory_map("user");
10373 + * Callback for efi_memory_walk.
10376 +efi_find_max_pfn(unsigned long start, unsigned long end, void *arg)
10378 + unsigned long *max_pfn = arg, pfn;
10380 + if (start < end) {
10381 + pfn = PFN_UP(end -1);
10382 + if (pfn > *max_pfn)
10389 +efi_memory_present_wrapper(unsigned long start, unsigned long end, void *arg)
10391 + memory_present(0, start, end);
10396 + * This function checks if any part of the range <start,end> is mapped
10400 +e820_any_mapped(u64 start, u64 end, unsigned type)
10404 +#ifndef CONFIG_XEN
10405 + for (i = 0; i < e820.nr_map; i++) {
10406 + const struct e820entry *ei = &e820.map[i];
10408 + if (!is_initial_xendomain())
10410 + for (i = 0; i < machine_e820.nr_map; ++i) {
10411 + const struct e820entry *ei = &machine_e820.map[i];
10414 + if (type && ei->type != type)
10416 + if (ei->addr >= end || ei->addr + ei->size <= start)
10422 +EXPORT_SYMBOL_GPL(e820_any_mapped);
10425 + * This function checks if the entire range <start,end> is mapped with type.
10427 + * Note: this function only works correct if the e820 table is sorted and
10428 + * not-overlapping, which is the case
10431 +e820_all_mapped(unsigned long s, unsigned long e, unsigned type)
10437 +#ifndef CONFIG_XEN
10438 + for (i = 0; i < e820.nr_map; i++) {
10439 + struct e820entry *ei = &e820.map[i];
10441 + if (!is_initial_xendomain())
10443 + for (i = 0; i < machine_e820.nr_map; ++i) {
10444 + const struct e820entry *ei = &machine_e820.map[i];
10446 + if (type && ei->type != type)
10448 + /* is the region (part) in overlap with the current region ?*/
10449 + if (ei->addr >= end || ei->addr + ei->size <= start)
10451 + /* if the region is at the beginning of <start,end> we move
10452 + * start to the end of the region since it's ok until there
10454 + if (ei->addr <= start)
10455 + start = ei->addr + ei->size;
10456 + /* if start is now at or beyond end, we're done, full
10458 + if (start >= end)
10459 + return 1; /* we're done */
10465 + * Find the highest page frame number we have available
10467 +void __init find_max_pfn(void)
10472 + if (efi_enabled) {
10473 + efi_memmap_walk(efi_find_max_pfn, &max_pfn);
10474 + efi_memmap_walk(efi_memory_present_wrapper, NULL);
10478 + for (i = 0; i < e820.nr_map; i++) {
10479 + unsigned long start, end;
10481 + if (e820.map[i].type != E820_RAM)
10483 + start = PFN_UP(e820.map[i].addr);
10484 + end = PFN_DOWN(e820.map[i].addr + e820.map[i].size);
10485 + if (start >= end)
10487 + if (end > max_pfn)
10489 + memory_present(0, start, end);
10494 + * Determine low and high memory ranges:
10496 +unsigned long __init find_max_low_pfn(void)
10498 + unsigned long max_low_pfn;
10500 + max_low_pfn = max_pfn;
10501 + if (max_low_pfn > MAXMEM_PFN) {
10502 + if (highmem_pages == -1)
10503 + highmem_pages = max_pfn - MAXMEM_PFN;
10504 + if (highmem_pages + MAXMEM_PFN < max_pfn)
10505 + max_pfn = MAXMEM_PFN + highmem_pages;
10506 + if (highmem_pages + MAXMEM_PFN > max_pfn) {
10507 + printk("only %luMB highmem pages available, ignoring highmem size of %uMB.\n", pages_to_mb(max_pfn - MAXMEM_PFN), pages_to_mb(highmem_pages));
10508 + highmem_pages = 0;
10510 + max_low_pfn = MAXMEM_PFN;
10511 +#ifndef CONFIG_HIGHMEM
10512 + /* Maximum memory usable is what is directly addressable */
10513 + printk(KERN_WARNING "Warning only %ldMB will be used.\n",
10515 + if (max_pfn > MAX_NONPAE_PFN)
10516 + printk(KERN_WARNING "Use a PAE enabled kernel.\n");
10518 + printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
10519 + max_pfn = MAXMEM_PFN;
10520 +#else /* !CONFIG_HIGHMEM */
10521 +#ifndef CONFIG_X86_PAE
10522 + if (max_pfn > MAX_NONPAE_PFN) {
10523 + max_pfn = MAX_NONPAE_PFN;
10524 + printk(KERN_WARNING "Warning only 4GB will be used.\n");
10525 + printk(KERN_WARNING "Use a PAE enabled kernel.\n");
10527 +#endif /* !CONFIG_X86_PAE */
10528 +#endif /* !CONFIG_HIGHMEM */
10530 + if (highmem_pages == -1)
10531 + highmem_pages = 0;
10532 +#ifdef CONFIG_HIGHMEM
10533 + if (highmem_pages >= max_pfn) {
10534 + printk(KERN_ERR "highmem size specified (%uMB) is bigger than pages available (%luMB)!.\n", pages_to_mb(highmem_pages), pages_to_mb(max_pfn));
10535 + highmem_pages = 0;
10537 + if (highmem_pages) {
10538 + if (max_low_pfn-highmem_pages < 64*1024*1024/PAGE_SIZE){
10539 + printk(KERN_ERR "highmem size %uMB results in smaller than 64MB lowmem, ignoring it.\n", pages_to_mb(highmem_pages));
10540 + highmem_pages = 0;
10542 + max_low_pfn -= highmem_pages;
10545 + if (highmem_pages)
10546 + printk(KERN_ERR "ignoring highmem size on non-highmem kernel!\n");
10549 + return max_low_pfn;
10553 + * Free all available memory for boot time allocation. Used
10554 + * as a callback function by efi_memory_walk()
10558 +free_available_memory(unsigned long start, unsigned long end, void *arg)
10560 + /* check max_low_pfn */
10561 + if (start >= (max_low_pfn << PAGE_SHIFT))
10563 + if (end >= (max_low_pfn << PAGE_SHIFT))
10564 + end = max_low_pfn << PAGE_SHIFT;
10566 + free_bootmem(start, end - start);
10571 + * Register fully available low RAM pages with the bootmem allocator.
10573 +static void __init register_bootmem_low_pages(unsigned long max_low_pfn)
10577 + if (efi_enabled) {
10578 + efi_memmap_walk(free_available_memory, NULL);
10581 + for (i = 0; i < e820.nr_map; i++) {
10582 + unsigned long curr_pfn, last_pfn, size;
10584 + * Reserve usable low memory
10586 + if (e820.map[i].type != E820_RAM)
10589 + * We are rounding up the start address of usable memory:
10591 + curr_pfn = PFN_UP(e820.map[i].addr);
10592 + if (curr_pfn >= max_low_pfn)
10595 + * ... and at the end of the usable range downwards:
10597 + last_pfn = PFN_DOWN(e820.map[i].addr + e820.map[i].size);
10601 + * Truncate to the number of actual pages currently
10604 + if (last_pfn > xen_start_info->nr_pages)
10605 + last_pfn = xen_start_info->nr_pages;
10608 + if (last_pfn > max_low_pfn)
10609 + last_pfn = max_low_pfn;
10612 + * .. finally, did all the rounding and playing
10613 + * around just make the area go away?
10615 + if (last_pfn <= curr_pfn)
10618 + size = last_pfn - curr_pfn;
10619 + free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
10623 +#ifndef CONFIG_XEN
10625 + * workaround for Dell systems that neglect to reserve EBDA
10627 +static void __init reserve_ebda_region(void)
10629 + unsigned int addr;
10630 + addr = get_bios_ebda();
10632 + reserve_bootmem(addr, PAGE_SIZE);
10636 +#ifndef CONFIG_NEED_MULTIPLE_NODES
10637 +void __init setup_bootmem_allocator(void);
10638 +static unsigned long __init setup_memory(void)
10641 + * partially used pages are not usable - thus
10642 + * we are rounding upwards:
10644 + min_low_pfn = PFN_UP(__pa(xen_start_info->pt_base)) +
10645 + xen_start_info->nr_pt_frames;
10649 + max_low_pfn = find_max_low_pfn();
10651 +#ifdef CONFIG_HIGHMEM
10652 + highstart_pfn = highend_pfn = max_pfn;
10653 + if (max_pfn > max_low_pfn) {
10654 + highstart_pfn = max_low_pfn;
10656 + printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
10657 + pages_to_mb(highend_pfn - highstart_pfn));
10659 + printk(KERN_NOTICE "%ldMB LOWMEM available.\n",
10660 + pages_to_mb(max_low_pfn));
10662 + setup_bootmem_allocator();
10664 + return max_low_pfn;
10667 +void __init zone_sizes_init(void)
10669 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
10670 + unsigned int max_dma, low;
10672 + max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
10673 + low = max_low_pfn;
10675 + if (low < max_dma)
10676 + zones_size[ZONE_DMA] = low;
10678 + zones_size[ZONE_DMA] = max_dma;
10679 + zones_size[ZONE_NORMAL] = low - max_dma;
10680 +#ifdef CONFIG_HIGHMEM
10681 + zones_size[ZONE_HIGHMEM] = highend_pfn - low;
10684 + free_area_init(zones_size);
10687 +extern unsigned long __init setup_memory(void);
10688 +extern void zone_sizes_init(void);
10689 +#endif /* !CONFIG_NEED_MULTIPLE_NODES */
10691 +void __init setup_bootmem_allocator(void)
10693 + unsigned long bootmap_size;
10695 + * Initialize the boot-time allocator (with low memory only):
10697 + bootmap_size = init_bootmem(min_low_pfn, max_low_pfn);
10699 + register_bootmem_low_pages(max_low_pfn);
10702 + * Reserve the bootmem bitmap itself as well. We do this in two
10703 + * steps (first step was init_bootmem()) because this catches
10704 + * the (very unlikely) case of us accidentally initializing the
10705 + * bootmem allocator with an invalid RAM area.
10707 + reserve_bootmem(__PHYSICAL_START, (PFN_PHYS(min_low_pfn) +
10708 + bootmap_size + PAGE_SIZE-1) - (__PHYSICAL_START));
10710 +#ifndef CONFIG_XEN
10712 + * reserve physical page 0 - it's a special BIOS page on many boxes,
10713 + * enabling clean reboots, SMP operation, laptop functions.
10715 + reserve_bootmem(0, PAGE_SIZE);
10717 + /* reserve EBDA region, it's a 4K region */
10718 + reserve_ebda_region();
10720 + /* could be an AMD 768MPX chipset. Reserve a page before VGA to prevent
10721 + PCI prefetch into it (errata #56). Usually the page is reserved anyways,
10722 + unless you have no PS/2 mouse plugged in. */
10723 + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
10724 + boot_cpu_data.x86 == 6)
10725 + reserve_bootmem(0xa0000 - 4096, 4096);
10729 + * But first pinch a few for the stack/trampoline stuff
10730 + * FIXME: Don't need the extra page at 4K, but need to fix
10731 + * trampoline before removing it. (see the GDT stuff)
10733 + reserve_bootmem(PAGE_SIZE, PAGE_SIZE);
10735 +#ifdef CONFIG_ACPI_SLEEP
10737 + * Reserve low memory region for sleep support.
10739 + acpi_reserve_bootmem();
10741 +#endif /* !CONFIG_XEN */
10743 +#ifdef CONFIG_BLK_DEV_INITRD
10744 + if (xen_start_info->mod_start) {
10745 + if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) {
10746 + /*reserve_bootmem(INITRD_START, INITRD_SIZE);*/
10747 + initrd_start = INITRD_START + PAGE_OFFSET;
10748 + initrd_end = initrd_start+INITRD_SIZE;
10749 + initrd_below_start_ok = 1;
10752 + printk(KERN_ERR "initrd extends beyond end of memory "
10753 + "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
10754 + INITRD_START + INITRD_SIZE,
10755 + max_low_pfn << PAGE_SHIFT);
10756 + initrd_start = 0;
10760 +#ifdef CONFIG_KEXEC
10762 + xen_machine_kexec_setup_resources();
10764 + if (crashk_res.start != crashk_res.end)
10765 + reserve_bootmem(crashk_res.start,
10766 + crashk_res.end - crashk_res.start + 1);
10772 + * The node 0 pgdat is initialized before all of these because
10773 + * it's needed for bootmem. node>0 pgdats have their virtual
10774 + * space allocated before the pagetables are in place to access
10775 + * them, so they can't be cleared then.
10777 + * This should all compile down to nothing when NUMA is off.
10779 +void __init remapped_pgdat_init(void)
10783 + for_each_online_node(nid) {
10785 + memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
10790 + * Request address space for all standard RAM and ROM resources
10791 + * and also for regions reported as reserved by the e820.
10793 +static void __init
10794 +legacy_init_iomem_resources(struct e820entry *e820, int nr_map,
10795 + struct resource *code_resource,
10796 + struct resource *data_resource)
10802 + for (i = 0; i < nr_map; i++) {
10803 + struct resource *res;
10804 +#ifndef CONFIG_RESOURCES_64BIT
10805 + if (e820[i].addr + e820[i].size > 0x100000000ULL)
10808 + res = kzalloc(sizeof(struct resource), GFP_ATOMIC);
10809 + switch (e820[i].type) {
10810 + case E820_RAM: res->name = "System RAM"; break;
10811 + case E820_ACPI: res->name = "ACPI Tables"; break;
10812 + case E820_NVS: res->name = "ACPI Non-volatile Storage"; break;
10813 + default: res->name = "reserved";
10815 + res->start = e820[i].addr;
10816 + res->end = res->start + e820[i].size - 1;
10817 + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
10818 + if (request_resource(&iomem_resource, res)) {
10822 + if (e820[i].type == E820_RAM) {
10824 + * We don't know which RAM region contains kernel data,
10825 + * so we try it repeatedly and let the resource manager
10828 +#ifndef CONFIG_XEN
10829 + request_resource(res, code_resource);
10830 + request_resource(res, data_resource);
10832 +#ifdef CONFIG_KEXEC
10833 + if (crashk_res.start != crashk_res.end)
10834 + request_resource(res, &crashk_res);
10836 + xen_machine_kexec_register_resources(res);
10844 + * Locate a unused range of the physical address space below 4G which
10845 + * can be used for PCI mappings.
10847 +static void __init
10848 +e820_setup_gap(struct e820entry *e820, int nr_map)
10850 + unsigned long gapstart, gapsize, round;
10851 + unsigned long long last;
10855 + * Search for the bigest gap in the low 32 bits of the e820
10858 + last = 0x100000000ull;
10859 + gapstart = 0x10000000;
10860 + gapsize = 0x400000;
10862 + while (--i >= 0) {
10863 + unsigned long long start = e820[i].addr;
10864 + unsigned long long end = start + e820[i].size;
10867 + * Since "last" is at most 4GB, we know we'll
10868 + * fit in 32 bits if this condition is true
10870 + if (last > end) {
10871 + unsigned long gap = last - end;
10873 + if (gap > gapsize) {
10878 + if (start < last)
10883 + * See how much we want to round up: start off with
10884 + * rounding to the next 1MB area.
10886 + round = 0x100000;
10887 + while ((gapsize >> 4) > round)
10889 + /* Fun with two's complement */
10890 + pci_mem_start = (gapstart + round) & -round;
10892 + printk("Allocating PCI resources starting at %08lx (gap: %08lx:%08lx)\n",
10893 + pci_mem_start, gapstart, gapsize);
10897 + * Request address space for all standard resources
10899 + * This is called just before pcibios_init(), which is also a
10900 + * subsys_initcall, but is linked in later (in arch/i386/pci/common.c).
10902 +static int __init request_standard_resources(void)
10906 + /* Nothing to do if not running in dom0. */
10907 + if (!is_initial_xendomain())
10910 + printk("Setting up standard PCI resources\n");
10912 + legacy_init_iomem_resources(machine_e820.map, machine_e820.nr_map,
10913 + &code_resource, &data_resource);
10916 + efi_initialize_iomem_resources(&code_resource, &data_resource);
10918 + legacy_init_iomem_resources(e820.map, e820.nr_map,
10919 + &code_resource, &data_resource);
10922 + /* EFI systems may still have VGA */
10923 + request_resource(&iomem_resource, &video_ram_resource);
10925 + /* request I/O space for devices used on all i[345]86 PCs */
10926 + for (i = 0; i < STANDARD_IO_RESOURCES; i++)
10927 + request_resource(&ioport_resource, &standard_io_resources[i]);
10931 +subsys_initcall(request_standard_resources);
10933 +static void __init register_memory(void)
10936 + if (is_initial_xendomain())
10937 + e820_setup_gap(machine_e820.map, machine_e820.nr_map);
10940 + e820_setup_gap(e820.map, e820.nr_map);
10944 +static void set_mca_bus(int x)
10949 +static void set_mca_bus(int x) { }
10953 + * Determine if we were loaded by an EFI loader. If so, then we have also been
10954 + * passed the efi memmap, systab, etc., so we should use these data structures
10955 + * for initialization. Note, the efi init code path is determined by the
10956 + * global efi_enabled. This allows the same kernel image to be used on existing
10957 + * systems (with a traditional BIOS) as well as on EFI systems.
10959 +void __init setup_arch(char **cmdline_p)
10961 + int i, j, k, fpp;
10962 + struct physdev_set_iopl set_iopl;
10963 + unsigned long max_low_pfn;
10964 + unsigned long p2m_pages;
10966 + /* Force a quick death if the kernel panics (not domain 0). */
10967 + extern int panic_timeout;
10968 + if (!panic_timeout && !is_initial_xendomain())
10969 + panic_timeout = 1;
10971 + /* Register a call for panic conditions. */
10972 + atomic_notifier_chain_register(&panic_notifier_list, &xen_panic_block);
10974 + WARN_ON(HYPERVISOR_vm_assist(VMASST_CMD_enable,
10975 + VMASST_TYPE_4gb_segments));
10976 + WARN_ON(HYPERVISOR_vm_assist(VMASST_CMD_enable,
10977 + VMASST_TYPE_writable_pagetables));
10979 + memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data));
10980 + pre_setup_arch_hook();
10981 + early_cpu_init();
10983 + prefill_possible_map();
10987 + * FIXME: This isn't an official loader_type right
10988 + * now but does currently work with elilo.
10989 + * If we were configured as an EFI kernel, check to make
10990 + * sure that we were loaded correctly from elilo and that
10991 + * the system table is valid. If not, then initialize normally.
10994 + if ((LOADER_TYPE == 0x50) && EFI_SYSTAB)
10998 + /* This must be initialized to UNNAMED_MAJOR for ipconfig to work
10999 + properly. Setting ROOT_DEV to default to /dev/ram0 breaks initrd.
11001 + ROOT_DEV = MKDEV(UNNAMED_MAJOR,0);
11002 + drive_info = DRIVE_INFO;
11003 + screen_info = SCREEN_INFO;
11005 + apm_info.bios = APM_BIOS_INFO;
11006 + ist_info = IST_INFO;
11007 + saved_videomode = VIDEO_MODE;
11008 + if( SYS_DESC_TABLE.length != 0 ) {
11009 + set_mca_bus(SYS_DESC_TABLE.table[3] & 0x2);
11010 + machine_id = SYS_DESC_TABLE.table[0];
11011 + machine_submodel_id = SYS_DESC_TABLE.table[1];
11012 + BIOS_revision = SYS_DESC_TABLE.table[2];
11014 + bootloader_type = LOADER_TYPE;
11016 + if (is_initial_xendomain()) {
11017 + const struct dom0_vga_console_info *info =
11018 + (void *)((char *)xen_start_info +
11019 + xen_start_info->console.dom0.info_off);
11021 + dom0_init_screen_info(info,
11022 + xen_start_info->console.dom0.info_size);
11023 + xen_start_info->console.domU.mfn = 0;
11024 + xen_start_info->console.domU.evtchn = 0;
11026 + screen_info.orig_video_isVGA = 0;
11028 +#ifdef CONFIG_BLK_DEV_RAM
11029 + rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
11030 + rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
11031 + rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
11038 + printk(KERN_INFO "BIOS-provided physical RAM map:\n");
11039 + print_memory_map(machine_specific_memory_setup());
11044 + if (!MOUNT_ROOT_RDONLY)
11045 + root_mountflags &= ~MS_RDONLY;
11046 + init_mm.start_code = (unsigned long) _text;
11047 + init_mm.end_code = (unsigned long) _etext;
11048 + init_mm.end_data = (unsigned long) _edata;
11049 + init_mm.brk = (PFN_UP(__pa(xen_start_info->pt_base)) +
11050 + xen_start_info->nr_pt_frames) << PAGE_SHIFT;
11052 + code_resource.start = virt_to_phys(_text);
11053 + code_resource.end = virt_to_phys(_etext)-1;
11054 + data_resource.start = virt_to_phys(_etext);
11055 + data_resource.end = virt_to_phys(_edata)-1;
11057 + parse_cmdline_early(cmdline_p);
11059 +#ifdef CONFIG_EARLY_PRINTK
11061 + char *s = strstr(*cmdline_p, "earlyprintk=");
11063 + setup_early_printk(strchr(s, '=') + 1);
11064 + printk("early console enabled\n");
11069 + max_low_pfn = setup_memory();
11072 + * NOTE: before this point _nobody_ is allowed to allocate
11073 + * any memory using the bootmem allocator. Although the
11074 + * alloctor is now initialised only the first 8Mb of the kernel
11075 + * virtual address space has been mapped. All allocations before
11076 + * paging_init() has completed must use the alloc_bootmem_low_pages()
11077 + * variant (which allocates DMA'able memory) and care must be taken
11078 + * not to exceed the 8Mb limit.
11082 + smp_alloc_memory(); /* AP processor realmode stacks in low memory*/
11085 + remapped_pgdat_init();
11087 + zone_sizes_init();
11089 +#ifdef CONFIG_X86_FIND_SMP_CONFIG
11091 + * Find and reserve possible boot-time SMP configuration:
11093 + find_smp_config();
11096 + p2m_pages = max_pfn;
11097 + if (xen_start_info->nr_pages > max_pfn) {
11099 + * the max_pfn was shrunk (probably by mem= or highmem=
11100 + * kernel parameter); shrink reservation with the HV
11102 + struct xen_memory_reservation reservation = {
11103 + .address_bits = 0,
11104 + .extent_order = 0,
11105 + .domid = DOMID_SELF
11107 + unsigned int difference;
11110 + difference = xen_start_info->nr_pages - max_pfn;
11112 + set_xen_guest_handle(reservation.extent_start,
11113 + ((unsigned long *)xen_start_info->mfn_list) + max_pfn);
11114 + reservation.nr_extents = difference;
11115 + ret = HYPERVISOR_memory_op(XENMEM_decrease_reservation,
11117 + BUG_ON (ret != difference);
11119 + else if (max_pfn > xen_start_info->nr_pages)
11120 + p2m_pages = xen_start_info->nr_pages;
11122 + /* Make sure we have a correctly sized P->M table. */
11123 + if (!xen_feature(XENFEAT_auto_translated_physmap)) {
11124 + phys_to_machine_mapping = alloc_bootmem_low_pages(
11125 + max_pfn * sizeof(unsigned long));
11126 + memset(phys_to_machine_mapping, ~0,
11127 + max_pfn * sizeof(unsigned long));
11128 + memcpy(phys_to_machine_mapping,
11129 + (unsigned long *)xen_start_info->mfn_list,
11130 + p2m_pages * sizeof(unsigned long));
11132 + __pa(xen_start_info->mfn_list),
11133 + PFN_PHYS(PFN_UP(xen_start_info->nr_pages *
11134 + sizeof(unsigned long))));
11137 + * Initialise the list of the frames that specify the list of
11138 + * frames that make up the p2m table. Used by save/restore
11140 + pfn_to_mfn_frame_list_list = alloc_bootmem_low_pages(PAGE_SIZE);
11142 + fpp = PAGE_SIZE/sizeof(unsigned long);
11143 + for (i=0, j=0, k=-1; i< max_pfn; i+=fpp, j++) {
11144 + if ((j % fpp) == 0) {
11147 + pfn_to_mfn_frame_list[k] =
11148 + alloc_bootmem_low_pages(PAGE_SIZE);
11149 + pfn_to_mfn_frame_list_list[k] =
11150 + virt_to_mfn(pfn_to_mfn_frame_list[k]);
11153 + pfn_to_mfn_frame_list[k][j] =
11154 + virt_to_mfn(&phys_to_machine_mapping[i]);
11156 + HYPERVISOR_shared_info->arch.max_pfn = max_pfn;
11157 + HYPERVISOR_shared_info->arch.pfn_to_mfn_frame_list_list =
11158 + virt_to_mfn(pfn_to_mfn_frame_list_list);
11161 + /* Mark all ISA DMA channels in-use - using them wouldn't work. */
11162 + for (i = 0; i < MAX_DMA_CHANNELS; ++i)
11163 + if (i != 4 && request_dma(i, "xen") != 0)
11167 + * NOTE: at this point the bootmem allocator is fully available.
11170 + if (is_initial_xendomain())
11171 + dmi_scan_machine();
11173 +#ifdef CONFIG_X86_GENERICARCH
11174 + generic_apic_probe(*cmdline_p);
11177 + efi_map_memmap();
11179 + set_iopl.iopl = 1;
11180 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl));
11182 +#ifdef CONFIG_ACPI
11183 + if (!is_initial_xendomain()) {
11184 + printk(KERN_INFO "ACPI in unprivileged domain disabled\n");
11185 + acpi_disabled = 1;
11190 + * Parse the ACPI tables for possible boot-time SMP configuration.
11192 + acpi_boot_table_init();
11195 +#ifdef CONFIG_X86_IO_APIC
11196 + check_acpi_pci(); /* Checks more than just ACPI actually */
11199 +#ifdef CONFIG_ACPI
11200 + acpi_boot_init();
11202 +#if defined(CONFIG_SMP) && defined(CONFIG_X86_PC)
11203 + if (def_to_bigsmp)
11204 + printk(KERN_WARNING "More than 8 CPUs detected and "
11205 + "CONFIG_X86_PC cannot handle it.\nUse "
11206 + "CONFIG_X86_GENERICARCH or CONFIG_X86_BIGSMP.\n");
11209 +#ifdef CONFIG_X86_LOCAL_APIC
11210 + if (smp_found_config)
11211 + get_smp_config();
11214 + register_memory();
11216 + if (is_initial_xendomain()) {
11218 +#if defined(CONFIG_VGA_CONSOLE)
11219 + if (!efi_enabled ||
11220 + (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
11221 + conswitchp = &vga_con;
11222 +#elif defined(CONFIG_DUMMY_CONSOLE)
11223 + conswitchp = &dummy_con;
11227 +#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
11228 + conswitchp = &dummy_con;
11235 +xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
11237 + HYPERVISOR_shutdown(SHUTDOWN_crash);
11238 + /* we're never actually going to get here... */
11239 + return NOTIFY_DONE;
11242 +static __init int add_pcspkr(void)
11244 + struct platform_device *pd;
11247 + if (!is_initial_xendomain())
11250 + pd = platform_device_alloc("pcspkr", -1);
11254 + ret = platform_device_add(pd);
11256 + platform_device_put(pd);
11260 +device_initcall(add_pcspkr);
11263 + * Local Variables:
11265 + * c-file-style:"k&r"
11266 + * c-basic-offset:8
11269 Index: head-2008-11-25/arch/x86/kernel/smp_32-xen.c
11270 ===================================================================
11271 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
11272 +++ head-2008-11-25/arch/x86/kernel/smp_32-xen.c 2007-12-10 08:47:31.000000000 +0100
11275 + * Intel SMP support routines.
11277 + * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
11278 + * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
11280 + * This code is released under the GNU General Public License version 2 or
11284 +#include <linux/init.h>
11286 +#include <linux/mm.h>
11287 +#include <linux/delay.h>
11288 +#include <linux/spinlock.h>
11289 +#include <linux/smp_lock.h>
11290 +#include <linux/kernel_stat.h>
11291 +#include <linux/mc146818rtc.h>
11292 +#include <linux/cache.h>
11293 +#include <linux/interrupt.h>
11294 +#include <linux/cpu.h>
11295 +#include <linux/module.h>
11297 +#include <asm/mtrr.h>
11298 +#include <asm/tlbflush.h>
11300 +#include <mach_apic.h>
11302 +#include <xen/evtchn.h>
11305 + * Some notes on x86 processor bugs affecting SMP operation:
11307 + * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
11308 + * The Linux implications for SMP are handled as follows:
11310 + * Pentium III / [Xeon]
11311 + * None of the E1AP-E3AP errata are visible to the user.
11313 + * E1AP. see PII A1AP
11314 + * E2AP. see PII A2AP
11315 + * E3AP. see PII A3AP
11317 + * Pentium II / [Xeon]
11318 + * None of the A1AP-A3AP errata are visible to the user.
11320 + * A1AP. see PPro 1AP
11321 + * A2AP. see PPro 2AP
11322 + * A3AP. see PPro 7AP
11325 + * None of 1AP-9AP errata are visible to the normal user,
11326 + * except occasional delivery of 'spurious interrupt' as trap #15.
11327 + * This is very rare and a non-problem.
11329 + * 1AP. Linux maps APIC as non-cacheable
11330 + * 2AP. worked around in hardware
11331 + * 3AP. fixed in C0 and above steppings microcode update.
11332 + * Linux does not use excessive STARTUP_IPIs.
11333 + * 4AP. worked around in hardware
11334 + * 5AP. symmetric IO mode (normal Linux operation) not affected.
11335 + * 'noapic' mode has vector 0xf filled out properly.
11336 + * 6AP. 'noapic' mode might be affected - fixed in later steppings
11337 + * 7AP. We do not assume writes to the LVT deassering IRQs
11338 + * 8AP. We do not enable low power mode (deep sleep) during MP bootup
11339 + * 9AP. We do not use mixed mode
11342 + * There is a marginal case where REP MOVS on 100MHz SMP
11343 + * machines with B stepping processors can fail. XXX should provide
11344 + * an L1cache=Writethrough or L1cache=off option.
11346 + * B stepping CPUs may hang. There are hardware work arounds
11347 + * for this. We warn about it in case your board doesn't have the work
11348 + * arounds. Basically thats so I can tell anyone with a B stepping
11349 + * CPU and SMP problems "tough".
11351 + * Specific items [From Pentium Processor Specification Update]
11353 + * 1AP. Linux doesn't use remote read
11354 + * 2AP. Linux doesn't trust APIC errors
11355 + * 3AP. We work around this
11356 + * 4AP. Linux never generated 3 interrupts of the same priority
11357 + * to cause a lost local interrupt.
11358 + * 5AP. Remote read is never used
11359 + * 6AP. not affected - worked around in hardware
11360 + * 7AP. not affected - worked around in hardware
11361 + * 8AP. worked around in hardware - we get explicit CS errors if not
11362 + * 9AP. only 'noapic' mode affected. Might generate spurious
11363 + * interrupts, we log only the first one and count the
11365 + * 10AP. not affected - worked around in hardware
11366 + * 11AP. Linux reads the APIC between writes to avoid this, as per
11367 + * the documentation. Make sure you preserve this as it affects
11368 + * the C stepping chips too.
11369 + * 12AP. not affected - worked around in hardware
11370 + * 13AP. not affected - worked around in hardware
11371 + * 14AP. we always deassert INIT during bootup
11372 + * 15AP. not affected - worked around in hardware
11373 + * 16AP. not affected - worked around in hardware
11374 + * 17AP. not affected - worked around in hardware
11375 + * 18AP. not affected - worked around in hardware
11376 + * 19AP. not affected - worked around in BIOS
11378 + * If this sounds worrying believe me these bugs are either ___RARE___,
11379 + * or are signal timing bugs worked around in hardware and there's
11380 + * about nothing of note with C stepping upwards.
11383 +DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
11386 + * the following functions deal with sending IPIs between CPUs.
11388 + * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
11391 +static inline int __prepare_ICR (unsigned int shortcut, int vector)
11393 + unsigned int icr = shortcut | APIC_DEST_LOGICAL;
11395 + switch (vector) {
11397 + icr |= APIC_DM_FIXED | vector;
11400 + icr |= APIC_DM_NMI;
11406 +static inline int __prepare_ICR2 (unsigned int mask)
11408 + return SET_APIC_DEST_FIELD(mask);
11411 +DECLARE_PER_CPU(int, ipi_to_irq[NR_IPIS]);
11413 +static inline void __send_IPI_one(unsigned int cpu, int vector)
11415 + int irq = per_cpu(ipi_to_irq, cpu)[vector];
11417 + notify_remote_via_irq(irq);
11420 +void __send_IPI_shortcut(unsigned int shortcut, int vector)
11424 + switch (shortcut) {
11425 + case APIC_DEST_SELF:
11426 + __send_IPI_one(smp_processor_id(), vector);
11428 + case APIC_DEST_ALLBUT:
11429 + for (cpu = 0; cpu < NR_CPUS; ++cpu) {
11430 + if (cpu == smp_processor_id())
11432 + if (cpu_isset(cpu, cpu_online_map)) {
11433 + __send_IPI_one(cpu, vector);
11438 + printk("XXXXXX __send_IPI_shortcut %08x vector %d\n", shortcut,
11444 +void fastcall send_IPI_self(int vector)
11446 + __send_IPI_shortcut(APIC_DEST_SELF, vector);
11450 + * This is only used on smaller machines.
11452 +void send_IPI_mask_bitmask(cpumask_t mask, int vector)
11454 + unsigned long flags;
11455 + unsigned int cpu;
11457 + local_irq_save(flags);
11458 + WARN_ON(cpus_addr(mask)[0] & ~cpus_addr(cpu_online_map)[0]);
11460 + for (cpu = 0; cpu < NR_CPUS; ++cpu) {
11461 + if (cpu_isset(cpu, mask)) {
11462 + __send_IPI_one(cpu, vector);
11466 + local_irq_restore(flags);
11469 +void send_IPI_mask_sequence(cpumask_t mask, int vector)
11472 + send_IPI_mask_bitmask(mask, vector);
11475 +#include <mach_ipi.h> /* must come after the send_IPI functions above for inlining */
11479 + * Smarter SMP flushing macros.
11480 + * c/o Linus Torvalds.
11482 + * These mean you can really definitely utterly forget about
11483 + * writing to user space from interrupts. (Its not allowed anyway).
11485 + * Optimizations Manfred Spraul <manfred@colorfullife.com>
11488 +static cpumask_t flush_cpumask;
11489 +static struct mm_struct * flush_mm;
11490 +static unsigned long flush_va;
11491 +static DEFINE_SPINLOCK(tlbstate_lock);
11492 +#define FLUSH_ALL 0xffffffff
11495 + * We cannot call mmdrop() because we are in interrupt context,
11496 + * instead update mm->cpu_vm_mask.
11498 + * We need to reload %cr3 since the page tables may be going
11499 + * away from under us..
11501 +static inline void leave_mm (unsigned long cpu)
11503 + if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
11505 + cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
11506 + load_cr3(swapper_pg_dir);
11511 + * The flush IPI assumes that a thread switch happens in this order:
11512 + * [cpu0: the cpu that switches]
11513 + * 1) switch_mm() either 1a) or 1b)
11514 + * 1a) thread switch to a different mm
11515 + * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
11516 + * Stop ipi delivery for the old mm. This is not synchronized with
11517 + * the other cpus, but smp_invalidate_interrupt ignore flush ipis
11518 + * for the wrong mm, and in the worst case we perform a superflous
11520 + * 1a2) set cpu_tlbstate to TLBSTATE_OK
11521 + * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
11522 + * was in lazy tlb mode.
11523 + * 1a3) update cpu_tlbstate[].active_mm
11524 + * Now cpu0 accepts tlb flushes for the new mm.
11525 + * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
11526 + * Now the other cpus will send tlb flush ipis.
11527 + * 1a4) change cr3.
11528 + * 1b) thread switch without mm change
11529 + * cpu_tlbstate[].active_mm is correct, cpu0 already handles
11531 + * 1b1) set cpu_tlbstate to TLBSTATE_OK
11532 + * 1b2) test_and_set the cpu bit in cpu_vm_mask.
11533 + * Atomically set the bit [other cpus will start sending flush ipis],
11534 + * and test the bit.
11535 + * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
11536 + * 2) switch %%esp, ie current
11538 + * The interrupt must handle 2 special cases:
11539 + * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
11540 + * - the cpu performs speculative tlb reads, i.e. even if the cpu only
11541 + * runs in kernel space, the cpu could load tlb entries for user space
11544 + * The good news is that cpu_tlbstate is local to each cpu, no
11545 + * write/read ordering problems.
11551 + * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
11552 + * 2) Leave the mm if we are in the lazy tlb mode.
11555 +irqreturn_t smp_invalidate_interrupt(int irq, void *dev_id,
11556 + struct pt_regs *regs)
11558 + unsigned long cpu;
11562 + if (!cpu_isset(cpu, flush_cpumask))
11565 + * This was a BUG() but until someone can quote me the
11566 + * line from the intel manual that guarantees an IPI to
11567 + * multiple CPUs is retried _only_ on the erroring CPUs
11568 + * its staying as a return
11573 + if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
11574 + if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
11575 + if (flush_va == FLUSH_ALL)
11576 + local_flush_tlb();
11578 + __flush_tlb_one(flush_va);
11582 + smp_mb__before_clear_bit();
11583 + cpu_clear(cpu, flush_cpumask);
11584 + smp_mb__after_clear_bit();
11586 + put_cpu_no_resched();
11588 + return IRQ_HANDLED;
11591 +static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
11592 + unsigned long va)
11595 + * A couple of (to be removed) sanity checks:
11597 + * - current CPU must not be in mask
11598 + * - mask must exist :)
11600 + BUG_ON(cpus_empty(cpumask));
11601 + BUG_ON(cpu_isset(smp_processor_id(), cpumask));
11604 + /* If a CPU which we ran on has gone down, OK. */
11605 + cpus_and(cpumask, cpumask, cpu_online_map);
11606 + if (cpus_empty(cpumask))
11610 + * i'm not happy about this global shared spinlock in the
11611 + * MM hot path, but we'll see how contended it is.
11612 + * Temporarily this turns IRQs off, so that lockups are
11613 + * detected by the NMI watchdog.
11615 + spin_lock(&tlbstate_lock);
11619 +#if NR_CPUS <= BITS_PER_LONG
11620 + atomic_set_mask(cpumask, &flush_cpumask);
11624 + unsigned long *flush_mask = (unsigned long *)&flush_cpumask;
11625 + unsigned long *cpu_mask = (unsigned long *)&cpumask;
11626 + for (k = 0; k < BITS_TO_LONGS(NR_CPUS); ++k)
11627 + atomic_set_mask(cpu_mask[k], &flush_mask[k]);
11631 + * We have to send the IPI only to
11634 + send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
11636 + while (!cpus_empty(flush_cpumask))
11637 + /* nothing. lockup detection does not belong here */
11642 + spin_unlock(&tlbstate_lock);
11645 +void flush_tlb_current_task(void)
11647 + struct mm_struct *mm = current->mm;
11648 + cpumask_t cpu_mask;
11650 + preempt_disable();
11651 + cpu_mask = mm->cpu_vm_mask;
11652 + cpu_clear(smp_processor_id(), cpu_mask);
11654 + local_flush_tlb();
11655 + if (!cpus_empty(cpu_mask))
11656 + flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
11657 + preempt_enable();
11660 +void flush_tlb_mm (struct mm_struct * mm)
11662 + cpumask_t cpu_mask;
11664 + preempt_disable();
11665 + cpu_mask = mm->cpu_vm_mask;
11666 + cpu_clear(smp_processor_id(), cpu_mask);
11668 + if (current->active_mm == mm) {
11670 + local_flush_tlb();
11672 + leave_mm(smp_processor_id());
11674 + if (!cpus_empty(cpu_mask))
11675 + flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
11677 + preempt_enable();
11680 +void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
11682 + struct mm_struct *mm = vma->vm_mm;
11683 + cpumask_t cpu_mask;
11685 + preempt_disable();
11686 + cpu_mask = mm->cpu_vm_mask;
11687 + cpu_clear(smp_processor_id(), cpu_mask);
11689 + if (current->active_mm == mm) {
11691 + __flush_tlb_one(va);
11693 + leave_mm(smp_processor_id());
11696 + if (!cpus_empty(cpu_mask))
11697 + flush_tlb_others(cpu_mask, mm, va);
11699 + preempt_enable();
11701 +EXPORT_SYMBOL(flush_tlb_page);
11703 +static void do_flush_tlb_all(void* info)
11705 + unsigned long cpu = smp_processor_id();
11707 + __flush_tlb_all();
11708 + if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
11712 +void flush_tlb_all(void)
11714 + on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
11720 + * this function sends a 'reschedule' IPI to another CPU.
11721 + * it goes straight through and wastes no time serializing
11722 + * anything. Worst case is that we lose a reschedule ...
11724 +void smp_send_reschedule(int cpu)
11726 + WARN_ON(cpu_is_offline(cpu));
11727 + send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
11731 + * Structure and data for smp_call_function(). This is designed to minimise
11732 + * static memory requirements. It also looks cleaner.
11734 +static DEFINE_SPINLOCK(call_lock);
11736 +struct call_data_struct {
11737 + void (*func) (void *info);
11739 + atomic_t started;
11740 + atomic_t finished;
11744 +void lock_ipi_call_lock(void)
11746 + spin_lock_irq(&call_lock);
11749 +void unlock_ipi_call_lock(void)
11751 + spin_unlock_irq(&call_lock);
11754 +static struct call_data_struct *call_data;
11757 + * smp_call_function(): Run a function on all other CPUs.
11758 + * @func: The function to run. This must be fast and non-blocking.
11759 + * @info: An arbitrary pointer to pass to the function.
11760 + * @nonatomic: currently unused.
11761 + * @wait: If true, wait (atomically) until function has completed on other CPUs.
11763 + * Returns 0 on success, else a negative status code. Does not return until
11764 + * remote CPUs are nearly ready to execute <<func>> or are or have executed.
11766 + * You must not call this function with disabled interrupts or from a
11767 + * hardware interrupt handler or from a bottom half handler.
11769 +int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
11772 + struct call_data_struct data;
11775 + /* Holding any lock stops cpus from going down. */
11776 + spin_lock(&call_lock);
11777 + cpus = num_online_cpus() - 1;
11779 + spin_unlock(&call_lock);
11783 + /* Can deadlock when called with interrupts disabled */
11784 + WARN_ON(irqs_disabled());
11786 + data.func = func;
11787 + data.info = info;
11788 + atomic_set(&data.started, 0);
11789 + data.wait = wait;
11791 + atomic_set(&data.finished, 0);
11793 + call_data = &data;
11796 + /* Send a message to all other CPUs and wait for them to respond */
11797 + send_IPI_allbutself(CALL_FUNCTION_VECTOR);
11799 + /* Wait for response */
11800 + while (atomic_read(&data.started) != cpus)
11804 + while (atomic_read(&data.finished) != cpus)
11806 + spin_unlock(&call_lock);
11810 +EXPORT_SYMBOL(smp_call_function);
11812 +static void stop_this_cpu (void * dummy)
11815 + * Remove this CPU:
11817 + cpu_clear(smp_processor_id(), cpu_online_map);
11818 + local_irq_disable();
11819 + disable_all_local_evtchn();
11820 + if (cpu_data[smp_processor_id()].hlt_works_ok)
11826 + * this function calls the 'stop' function on all other CPUs in the system.
11829 +void smp_send_stop(void)
11831 + smp_call_function(stop_this_cpu, NULL, 1, 0);
11833 + local_irq_disable();
11834 + disable_all_local_evtchn();
11835 + local_irq_enable();
11839 + * Reschedule call back. Nothing to do,
11840 + * all the work is done automatically when
11841 + * we return from the interrupt.
11843 +irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id,
11844 + struct pt_regs *regs)
11847 + return IRQ_HANDLED;
11850 +#include <linux/kallsyms.h>
11851 +irqreturn_t smp_call_function_interrupt(int irq, void *dev_id,
11852 + struct pt_regs *regs)
11854 + void (*func) (void *info) = call_data->func;
11855 + void *info = call_data->info;
11856 + int wait = call_data->wait;
11859 + * Notify initiating CPU that I've grabbed the data and am
11860 + * about to execute the function
11863 + atomic_inc(&call_data->started);
11865 + * At this point the info structure may be out of scope unless wait==1
11873 + atomic_inc(&call_data->finished);
11876 + return IRQ_HANDLED;
11879 Index: head-2008-11-25/arch/x86/kernel/time_32-xen.c
11880 ===================================================================
11881 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
11882 +++ head-2008-11-25/arch/x86/kernel/time_32-xen.c 2008-09-01 12:07:31.000000000 +0200
11885 + * linux/arch/i386/kernel/time.c
11887 + * Copyright (C) 1991, 1992, 1995 Linus Torvalds
11889 + * This file contains the PC-specific time handling details:
11890 + * reading the RTC at bootup, etc..
11891 + * 1994-07-02 Alan Modra
11892 + * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
11893 + * 1995-03-26 Markus Kuhn
11894 + * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
11895 + * precision CMOS clock update
11896 + * 1996-05-03 Ingo Molnar
11897 + * fixed time warps in do_[slow|fast]_gettimeoffset()
11898 + * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
11899 + * "A Kernel Model for Precision Timekeeping" by Dave Mills
11900 + * 1998-09-05 (Various)
11901 + * More robust do_fast_gettimeoffset() algorithm implemented
11902 + * (works with APM, Cyrix 6x86MX and Centaur C6),
11903 + * monotonic gettimeofday() with fast_get_timeoffset(),
11904 + * drift-proof precision TSC calibration on boot
11905 + * (C. Scott Ananian <cananian@alumni.princeton.edu>, Andrew D.
11906 + * Balsa <andrebalsa@altern.org>, Philip Gladstone <philip@raptor.com>;
11907 + * ported from 2.0.35 Jumbo-9 by Michael Krause <m.krause@tu-harburg.de>).
11908 + * 1998-12-16 Andrea Arcangeli
11909 + * Fixed Jumbo-9 code in 2.1.131: do_gettimeofday was missing 1 jiffy
11910 + * because was not accounting lost_ticks.
11911 + * 1998-12-24 Copyright (C) 1998 Andrea Arcangeli
11912 + * Fixed a xtime SMP race (we need the xtime_lock rw spinlock to
11913 + * serialize accesses to xtime/lost_ticks).
11916 +#include <linux/errno.h>
11917 +#include <linux/sched.h>
11918 +#include <linux/kernel.h>
11919 +#include <linux/param.h>
11920 +#include <linux/string.h>
11921 +#include <linux/mm.h>
11922 +#include <linux/interrupt.h>
11923 +#include <linux/time.h>
11924 +#include <linux/delay.h>
11925 +#include <linux/init.h>
11926 +#include <linux/smp.h>
11927 +#include <linux/module.h>
11928 +#include <linux/sysdev.h>
11929 +#include <linux/bcd.h>
11930 +#include <linux/efi.h>
11931 +#include <linux/mca.h>
11932 +#include <linux/sysctl.h>
11933 +#include <linux/percpu.h>
11934 +#include <linux/kernel_stat.h>
11935 +#include <linux/posix-timers.h>
11936 +#include <linux/cpufreq.h>
11938 +#include <asm/io.h>
11939 +#include <asm/smp.h>
11940 +#include <asm/irq.h>
11941 +#include <asm/msr.h>
11942 +#include <asm/delay.h>
11943 +#include <asm/mpspec.h>
11944 +#include <asm/uaccess.h>
11945 +#include <asm/processor.h>
11946 +#include <asm/timer.h>
11947 +#include <asm/sections.h>
11949 +#include "mach_time.h"
11951 +#include <linux/timex.h>
11953 +#include <asm/hpet.h>
11955 +#include <asm/arch_hooks.h>
11957 +#include <xen/evtchn.h>
11958 +#include <xen/interface/vcpu.h>
11960 +#if defined (__i386__)
11961 +#include <asm/i8259.h>
11964 +int pit_latch_buggy; /* extern */
11966 +#if defined(__x86_64__)
11967 +unsigned long vxtime_hz = PIT_TICK_RATE;
11968 +struct vxtime_data __vxtime __section_vxtime; /* for vsyscalls */
11969 +volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;
11970 +unsigned long __wall_jiffies __section_wall_jiffies = INITIAL_JIFFIES;
11971 +struct timespec __xtime __section_xtime;
11972 +struct timezone __sys_tz __section_sys_tz;
11975 +unsigned int cpu_khz; /* Detected as we calibrate the TSC */
11976 +EXPORT_SYMBOL(cpu_khz);
11978 +extern unsigned long wall_jiffies;
11980 +DEFINE_SPINLOCK(rtc_lock);
11981 +EXPORT_SYMBOL(rtc_lock);
11983 +extern struct init_timer_opts timer_tsc_init;
11984 +extern struct timer_opts timer_tsc;
11985 +#define timer_none timer_tsc
11987 +/* These are peridically updated in shared_info, and then copied here. */
11988 +struct shadow_time_info {
11989 + u64 tsc_timestamp; /* TSC at last update of time vals. */
11990 + u64 system_timestamp; /* Time, in nanosecs, since boot. */
11991 + u32 tsc_to_nsec_mul;
11992 + u32 tsc_to_usec_mul;
11996 +static DEFINE_PER_CPU(struct shadow_time_info, shadow_time);
11997 +static struct timespec shadow_tv;
11998 +static u32 shadow_tv_version;
12000 +static struct timeval monotonic_tv;
12001 +static spinlock_t monotonic_lock = SPIN_LOCK_UNLOCKED;
12003 +/* Keep track of last time we did processing/updating of jiffies and xtime. */
12004 +static u64 processed_system_time; /* System time (ns) at last processing. */
12005 +static DEFINE_PER_CPU(u64, processed_system_time);
12007 +/* How much CPU time was spent blocked and how much was 'stolen'? */
12008 +static DEFINE_PER_CPU(u64, processed_stolen_time);
12009 +static DEFINE_PER_CPU(u64, processed_blocked_time);
12011 +/* Current runstate of each CPU (updated automatically by the hypervisor). */
12012 +static DEFINE_PER_CPU(struct vcpu_runstate_info, runstate);
12014 +/* Must be signed, as it's compared with s64 quantities which can be -ve. */
12015 +#define NS_PER_TICK (1000000000LL/HZ)
12017 +static void __clock_was_set(void *unused)
12021 +static DECLARE_WORK(clock_was_set_work, __clock_was_set, NULL);
12024 + * GCC 4.3 can turn loops over an induction variable into division. We do
12025 + * not support arbitrary 64-bit division, and so must break the induction.
12027 +#define clobber_induction_variable(v) asm ( "" : "+r" (v) )
12029 +static inline void __normalize_time(time_t *sec, s64 *nsec)
12031 + while (*nsec >= NSEC_PER_SEC) {
12032 + clobber_induction_variable(*nsec);
12033 + (*nsec) -= NSEC_PER_SEC;
12036 + while (*nsec < 0) {
12037 + clobber_induction_variable(*nsec);
12038 + (*nsec) += NSEC_PER_SEC;
12043 +/* Does this guest OS track Xen time, or set its wall clock independently? */
12044 +static int independent_wallclock = 0;
12045 +static int __init __independent_wallclock(char *str)
12047 + independent_wallclock = 1;
12050 +__setup("independent_wallclock", __independent_wallclock);
12052 +/* Permitted clock jitter, in nsecs, beyond which a warning will be printed. */
12053 +static unsigned long permitted_clock_jitter = 10000000UL; /* 10ms */
12054 +static int __init __permitted_clock_jitter(char *str)
12056 + permitted_clock_jitter = simple_strtoul(str, NULL, 0);
12059 +__setup("permitted_clock_jitter=", __permitted_clock_jitter);
12062 +static void delay_tsc(unsigned long loops)
12064 + unsigned long bclock, now;
12070 + } while ((now - bclock) < loops);
12073 +struct timer_opts timer_tsc = {
12075 + .delay = delay_tsc,
12080 + * Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction,
12081 + * yielding a 64-bit result.
12083 +static inline u64 scale_delta(u64 delta, u32 mul_frac, int shift)
12091 + delta >>= -shift;
12098 + "mov %4,%%eax ; "
12099 + "mov %%edx,%4 ; "
12102 + "add %4,%%eax ; "
12103 + "adc %5,%%edx ; "
12104 + : "=A" (product), "=r" (tmp1), "=r" (tmp2)
12105 + : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) );
12108 + "mul %%rdx ; shrd $32,%%rdx,%%rax"
12109 + : "=a" (product) : "0" (delta), "d" ((u64)mul_frac) );
12115 +#if 0 /* defined (__i386__) */
12116 +int read_current_timer(unsigned long *timer_val)
12118 + rdtscl(*timer_val);
12123 +void init_cpu_khz(void)
12125 + u64 __cpu_khz = 1000000ULL << 32;
12126 + struct vcpu_time_info *info = &vcpu_info(0)->time;
12127 + do_div(__cpu_khz, info->tsc_to_system_mul);
12128 + if (info->tsc_shift < 0)
12129 + cpu_khz = __cpu_khz << -info->tsc_shift;
12131 + cpu_khz = __cpu_khz >> info->tsc_shift;
12134 +static u64 get_nsec_offset(struct shadow_time_info *shadow)
12138 + delta = now - shadow->tsc_timestamp;
12139 + return scale_delta(delta, shadow->tsc_to_nsec_mul, shadow->tsc_shift);
12142 +static unsigned long get_usec_offset(struct shadow_time_info *shadow)
12146 + delta = now - shadow->tsc_timestamp;
12147 + return scale_delta(delta, shadow->tsc_to_usec_mul, shadow->tsc_shift);
12150 +static void __update_wallclock(time_t sec, long nsec)
12152 + long wtm_nsec, xtime_nsec;
12153 + time_t wtm_sec, xtime_sec;
12154 + u64 tmp, wc_nsec;
12156 + /* Adjust wall-clock time base based on wall_jiffies ticks. */
12157 + wc_nsec = processed_system_time;
12158 + wc_nsec += sec * (u64)NSEC_PER_SEC;
12160 + wc_nsec -= (jiffies - wall_jiffies) * (u64)NS_PER_TICK;
12162 + /* Split wallclock base into seconds and nanoseconds. */
12164 + xtime_nsec = do_div(tmp, 1000000000);
12165 + xtime_sec = (time_t)tmp;
12167 + wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - xtime_sec);
12168 + wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - xtime_nsec);
12170 + set_normalized_timespec(&xtime, xtime_sec, xtime_nsec);
12171 + set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
12176 +static void update_wallclock(void)
12178 + shared_info_t *s = HYPERVISOR_shared_info;
12181 + shadow_tv_version = s->wc_version;
12183 + shadow_tv.tv_sec = s->wc_sec;
12184 + shadow_tv.tv_nsec = s->wc_nsec;
12186 + } while ((s->wc_version & 1) | (shadow_tv_version ^ s->wc_version));
12188 + if (!independent_wallclock)
12189 + __update_wallclock(shadow_tv.tv_sec, shadow_tv.tv_nsec);
12193 + * Reads a consistent set of time-base values from Xen, into a shadow data
12196 +static void get_time_values_from_xen(unsigned int cpu)
12198 + struct vcpu_time_info *src;
12199 + struct shadow_time_info *dst;
12200 + unsigned long flags;
12201 + u32 pre_version, post_version;
12203 + src = &vcpu_info(cpu)->time;
12204 + dst = &per_cpu(shadow_time, cpu);
12206 + local_irq_save(flags);
12209 + pre_version = dst->version = src->version;
12211 + dst->tsc_timestamp = src->tsc_timestamp;
12212 + dst->system_timestamp = src->system_time;
12213 + dst->tsc_to_nsec_mul = src->tsc_to_system_mul;
12214 + dst->tsc_shift = src->tsc_shift;
12216 + post_version = src->version;
12217 + } while ((pre_version & 1) | (pre_version ^ post_version));
12219 + dst->tsc_to_usec_mul = dst->tsc_to_nsec_mul / 1000;
12221 + local_irq_restore(flags);
12224 +static inline int time_values_up_to_date(unsigned int cpu)
12226 + struct vcpu_time_info *src;
12227 + struct shadow_time_info *dst;
12229 + src = &vcpu_info(cpu)->time;
12230 + dst = &per_cpu(shadow_time, cpu);
12233 + return (dst->version == src->version);
12237 + * This is a special lock that is owned by the CPU and holds the index
12238 + * register we are working with. It is required for NMI access to the
12239 + * CMOS/RTC registers. See include/asm-i386/mc146818rtc.h for details.
12241 +volatile unsigned long cmos_lock = 0;
12242 +EXPORT_SYMBOL(cmos_lock);
12244 +/* Routines for accessing the CMOS RAM/RTC. */
12245 +unsigned char rtc_cmos_read(unsigned char addr)
12247 + unsigned char val;
12248 + lock_cmos_prefix(addr);
12249 + outb_p(addr, RTC_PORT(0));
12250 + val = inb_p(RTC_PORT(1));
12251 + lock_cmos_suffix(addr);
12254 +EXPORT_SYMBOL(rtc_cmos_read);
12256 +void rtc_cmos_write(unsigned char val, unsigned char addr)
12258 + lock_cmos_prefix(addr);
12259 + outb_p(addr, RTC_PORT(0));
12260 + outb_p(val, RTC_PORT(1));
12261 + lock_cmos_suffix(addr);
12263 +EXPORT_SYMBOL(rtc_cmos_write);
12266 + * This version of gettimeofday has microsecond resolution
12267 + * and better than microsecond precision on fast x86 machines with TSC.
12269 +void do_gettimeofday(struct timeval *tv)
12271 + unsigned long seq;
12272 + unsigned long usec, sec;
12273 + unsigned long flags;
12275 + unsigned int cpu;
12276 + struct shadow_time_info *shadow;
12277 + u32 local_time_version;
12280 + shadow = &per_cpu(shadow_time, cpu);
12283 + unsigned long lost;
12285 + local_time_version = shadow->version;
12286 + seq = read_seqbegin(&xtime_lock);
12288 + usec = get_usec_offset(shadow);
12289 + lost = jiffies - wall_jiffies;
12291 + if (unlikely(lost))
12292 + usec += lost * (USEC_PER_SEC / HZ);
12294 + sec = xtime.tv_sec;
12295 + usec += (xtime.tv_nsec / NSEC_PER_USEC);
12297 + nsec = shadow->system_timestamp - processed_system_time;
12298 + __normalize_time(&sec, &nsec);
12299 + usec += (long)nsec / NSEC_PER_USEC;
12301 + if (unlikely(!time_values_up_to_date(cpu))) {
12303 + * We may have blocked for a long time,
12304 + * rendering our calculations invalid
12305 + * (e.g. the time delta may have
12306 + * overflowed). Detect that and recalculate
12307 + * with fresh values.
12309 + get_time_values_from_xen(cpu);
12312 + } while (read_seqretry(&xtime_lock, seq) ||
12313 + (local_time_version != shadow->version));
12317 + while (usec >= USEC_PER_SEC) {
12318 + usec -= USEC_PER_SEC;
12322 + spin_lock_irqsave(&monotonic_lock, flags);
12323 + if ((sec > monotonic_tv.tv_sec) ||
12324 + ((sec == monotonic_tv.tv_sec) && (usec > monotonic_tv.tv_usec)))
12326 + monotonic_tv.tv_sec = sec;
12327 + monotonic_tv.tv_usec = usec;
12329 + sec = monotonic_tv.tv_sec;
12330 + usec = monotonic_tv.tv_usec;
12332 + spin_unlock_irqrestore(&monotonic_lock, flags);
12334 + tv->tv_sec = sec;
12335 + tv->tv_usec = usec;
12338 +EXPORT_SYMBOL(do_gettimeofday);
12340 +int do_settimeofday(struct timespec *tv)
12344 + unsigned int cpu;
12345 + struct shadow_time_info *shadow;
12346 + struct xen_platform_op op;
12348 + if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
12352 + shadow = &per_cpu(shadow_time, cpu);
12354 + write_seqlock_irq(&xtime_lock);
12357 + * Ensure we don't get blocked for a long time so that our time delta
12358 + * overflows. If that were to happen then our shadow time values would
12359 + * be stale, so we can retry with fresh ones.
12362 + nsec = tv->tv_nsec - get_nsec_offset(shadow);
12363 + if (time_values_up_to_date(cpu))
12365 + get_time_values_from_xen(cpu);
12367 + sec = tv->tv_sec;
12368 + __normalize_time(&sec, &nsec);
12370 + if (is_initial_xendomain() && !independent_wallclock) {
12371 + op.cmd = XENPF_settime;
12372 + op.u.settime.secs = sec;
12373 + op.u.settime.nsecs = nsec;
12374 + op.u.settime.system_time = shadow->system_timestamp;
12375 + WARN_ON(HYPERVISOR_platform_op(&op));
12376 + update_wallclock();
12377 + } else if (independent_wallclock) {
12378 + nsec -= shadow->system_timestamp;
12379 + __normalize_time(&sec, &nsec);
12380 + __update_wallclock(sec, nsec);
12383 + /* Reset monotonic gettimeofday() timeval. */
12384 + spin_lock(&monotonic_lock);
12385 + monotonic_tv.tv_sec = 0;
12386 + monotonic_tv.tv_usec = 0;
12387 + spin_unlock(&monotonic_lock);
12389 + write_sequnlock_irq(&xtime_lock);
12397 +EXPORT_SYMBOL(do_settimeofday);
12399 +static void sync_xen_wallclock(unsigned long dummy);
12400 +static DEFINE_TIMER(sync_xen_wallclock_timer, sync_xen_wallclock, 0, 0);
12401 +static void sync_xen_wallclock(unsigned long dummy)
12405 + struct xen_platform_op op;
12407 + if (!ntp_synced() || independent_wallclock || !is_initial_xendomain())
12410 + write_seqlock_irq(&xtime_lock);
12412 + sec = xtime.tv_sec;
12413 + nsec = xtime.tv_nsec + ((jiffies - wall_jiffies) * (u64)NS_PER_TICK);
12414 + __normalize_time(&sec, &nsec);
12416 + op.cmd = XENPF_settime;
12417 + op.u.settime.secs = sec;
12418 + op.u.settime.nsecs = nsec;
12419 + op.u.settime.system_time = processed_system_time;
12420 + WARN_ON(HYPERVISOR_platform_op(&op));
12422 + update_wallclock();
12424 + write_sequnlock_irq(&xtime_lock);
12426 + /* Once per minute. */
12427 + mod_timer(&sync_xen_wallclock_timer, jiffies + 60*HZ);
12430 +static int set_rtc_mmss(unsigned long nowtime)
12433 + unsigned long flags;
12435 + if (independent_wallclock || !is_initial_xendomain())
12438 + /* gets recalled with irq locally disabled */
12439 + /* XXX - does irqsave resolve this? -johnstul */
12440 + spin_lock_irqsave(&rtc_lock, flags);
12442 + retval = efi_set_rtc_mmss(nowtime);
12444 + retval = mach_set_rtc_mmss(nowtime);
12445 + spin_unlock_irqrestore(&rtc_lock, flags);
12450 +/* monotonic_clock(): returns # of nanoseconds passed since time_init()
12451 + * Note: This function is required to return accurate
12452 + * time even in the absence of multiple timer ticks.
12454 +unsigned long long monotonic_clock(void)
12456 + unsigned int cpu = get_cpu();
12457 + struct shadow_time_info *shadow = &per_cpu(shadow_time, cpu);
12459 + u32 local_time_version;
12462 + local_time_version = shadow->version;
12464 + time = shadow->system_timestamp + get_nsec_offset(shadow);
12465 + if (!time_values_up_to_date(cpu))
12466 + get_time_values_from_xen(cpu);
12468 + } while (local_time_version != shadow->version);
12474 +EXPORT_SYMBOL(monotonic_clock);
12477 +unsigned long long sched_clock(void)
12479 + return monotonic_clock();
12483 +#if defined(CONFIG_SMP) && defined(CONFIG_FRAME_POINTER)
12484 +unsigned long profile_pc(struct pt_regs *regs)
12486 + unsigned long pc = instruction_pointer(regs);
12489 + /* Assume the lock function has either no stack frame or only a single word.
12490 + This checks if the address on the stack looks like a kernel text address.
12491 + There is a small window for false hits, but in that case the tick
12492 + is just accounted to the spinlock function.
12493 + Better would be to write these functions in assembler again
12494 + and check exactly. */
12495 + if (!user_mode_vm(regs) && in_lock_functions(pc)) {
12496 + char *v = *(char **)regs->rsp;
12497 + if ((v >= _stext && v <= _etext) ||
12498 + (v >= _sinittext && v <= _einittext) ||
12499 + (v >= (char *)MODULES_VADDR && v <= (char *)MODULES_END))
12500 + return (unsigned long)v;
12501 + return ((unsigned long *)regs->rsp)[1];
12504 + if (!user_mode_vm(regs) && in_lock_functions(pc))
12505 + return *(unsigned long *)(regs->ebp + 4);
12510 +EXPORT_SYMBOL(profile_pc);
12514 + * This is the same as the above, except we _also_ save the current
12515 + * Time Stamp Counter value at the time of the timer interrupt, so that
12516 + * we later on can estimate the time of day more exactly.
12518 +irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
12520 + s64 delta, delta_cpu, stolen, blocked;
12522 + unsigned int i, cpu = smp_processor_id();
12523 + struct shadow_time_info *shadow = &per_cpu(shadow_time, cpu);
12524 + struct vcpu_runstate_info *runstate = &per_cpu(runstate, cpu);
12527 + * Here we are in the timer irq handler. We just have irqs locally
12528 + * disabled but we don't know if the timer_bh is running on the other
12529 + * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
12530 + * the irq version of write_lock because as just said we have irq
12531 + * locally disabled. -arca
12533 + write_seqlock(&xtime_lock);
12536 + get_time_values_from_xen(cpu);
12538 + /* Obtain a consistent snapshot of elapsed wallclock cycles. */
12539 + delta = delta_cpu =
12540 + shadow->system_timestamp + get_nsec_offset(shadow);
12541 + delta -= processed_system_time;
12542 + delta_cpu -= per_cpu(processed_system_time, cpu);
12545 + * Obtain a consistent snapshot of stolen/blocked cycles. We
12546 + * can use state_entry_time to detect if we get preempted here.
12549 + sched_time = runstate->state_entry_time;
12551 + stolen = runstate->time[RUNSTATE_runnable] +
12552 + runstate->time[RUNSTATE_offline] -
12553 + per_cpu(processed_stolen_time, cpu);
12554 + blocked = runstate->time[RUNSTATE_blocked] -
12555 + per_cpu(processed_blocked_time, cpu);
12557 + } while (sched_time != runstate->state_entry_time);
12558 + } while (!time_values_up_to_date(cpu));
12560 + if ((unlikely(delta < -(s64)permitted_clock_jitter) ||
12561 + unlikely(delta_cpu < -(s64)permitted_clock_jitter))
12562 + && printk_ratelimit()) {
12563 + printk("Timer ISR/%u: Time went backwards: "
12564 + "delta=%lld delta_cpu=%lld shadow=%lld "
12565 + "off=%lld processed=%lld cpu_processed=%lld\n",
12566 + cpu, delta, delta_cpu, shadow->system_timestamp,
12567 + (s64)get_nsec_offset(shadow),
12568 + processed_system_time,
12569 + per_cpu(processed_system_time, cpu));
12570 + for (i = 0; i < num_online_cpus(); i++)
12571 + printk(" %d: %lld\n", i,
12572 + per_cpu(processed_system_time, i));
12575 + /* System-wide jiffy work. */
12576 + while (delta >= NS_PER_TICK) {
12577 + delta -= NS_PER_TICK;
12578 + processed_system_time += NS_PER_TICK;
12582 + if (shadow_tv_version != HYPERVISOR_shared_info->wc_version) {
12583 + update_wallclock();
12584 + if (keventd_up())
12585 + schedule_work(&clock_was_set_work);
12588 + write_sequnlock(&xtime_lock);
12591 + * Account stolen ticks.
12592 + * HACK: Passing NULL to account_steal_time()
12593 + * ensures that the ticks are accounted as stolen.
12595 + if ((stolen > 0) && (delta_cpu > 0)) {
12596 + delta_cpu -= stolen;
12597 + if (unlikely(delta_cpu < 0))
12598 + stolen += delta_cpu; /* clamp local-time progress */
12599 + do_div(stolen, NS_PER_TICK);
12600 + per_cpu(processed_stolen_time, cpu) += stolen * NS_PER_TICK;
12601 + per_cpu(processed_system_time, cpu) += stolen * NS_PER_TICK;
12602 + account_steal_time(NULL, (cputime_t)stolen);
12606 + * Account blocked ticks.
12607 + * HACK: Passing idle_task to account_steal_time()
12608 + * ensures that the ticks are accounted as idle/wait.
12610 + if ((blocked > 0) && (delta_cpu > 0)) {
12611 + delta_cpu -= blocked;
12612 + if (unlikely(delta_cpu < 0))
12613 + blocked += delta_cpu; /* clamp local-time progress */
12614 + do_div(blocked, NS_PER_TICK);
12615 + per_cpu(processed_blocked_time, cpu) += blocked * NS_PER_TICK;
12616 + per_cpu(processed_system_time, cpu) += blocked * NS_PER_TICK;
12617 + account_steal_time(idle_task(cpu), (cputime_t)blocked);
12620 + /* Account user/system ticks. */
12621 + if (delta_cpu > 0) {
12622 + do_div(delta_cpu, NS_PER_TICK);
12623 + per_cpu(processed_system_time, cpu) += delta_cpu * NS_PER_TICK;
12624 + if (user_mode_vm(regs))
12625 + account_user_time(current, (cputime_t)delta_cpu);
12627 + account_system_time(current, HARDIRQ_OFFSET,
12628 + (cputime_t)delta_cpu);
12631 + /* Offlined for more than a few seconds? Avoid lockup warnings. */
12632 + if (stolen > 5*HZ)
12633 + touch_softlockup_watchdog();
12635 + /* Local timer processing (see update_process_times()). */
12636 + run_local_timers();
12637 + if (rcu_pending(cpu))
12638 + rcu_check_callbacks(cpu, user_mode_vm(regs));
12639 + scheduler_tick();
12640 + run_posix_cpu_timers(current);
12641 + profile_tick(CPU_PROFILING, regs);
12643 + return IRQ_HANDLED;
12646 +static void init_missing_ticks_accounting(unsigned int cpu)
12648 + struct vcpu_register_runstate_memory_area area;
12649 + struct vcpu_runstate_info *runstate = &per_cpu(runstate, cpu);
12652 + memset(runstate, 0, sizeof(*runstate));
12654 + area.addr.v = runstate;
12655 + rc = HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area, cpu, &area);
12656 + WARN_ON(rc && rc != -ENOSYS);
12658 + per_cpu(processed_blocked_time, cpu) =
12659 + runstate->time[RUNSTATE_blocked];
12660 + per_cpu(processed_stolen_time, cpu) =
12661 + runstate->time[RUNSTATE_runnable] +
12662 + runstate->time[RUNSTATE_offline];
12665 +/* not static: needed by APM */
12666 +unsigned long get_cmos_time(void)
12668 + unsigned long retval;
12669 + unsigned long flags;
12671 + spin_lock_irqsave(&rtc_lock, flags);
12674 + retval = efi_get_time();
12676 + retval = mach_get_cmos_time();
12678 + spin_unlock_irqrestore(&rtc_lock, flags);
12682 +EXPORT_SYMBOL(get_cmos_time);
12684 +static void sync_cmos_clock(unsigned long dummy);
12686 +static DEFINE_TIMER(sync_cmos_timer, sync_cmos_clock, 0, 0);
12688 +static void sync_cmos_clock(unsigned long dummy)
12690 + struct timeval now, next;
12694 + * If we have an externally synchronized Linux clock, then update
12695 + * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
12696 + * called as close as possible to 500 ms before the new second starts.
12697 + * This code is run on a timer. If the clock is set, that timer
12698 + * may not expire at the correct time. Thus, we adjust...
12700 + if (!ntp_synced())
12702 + * Not synced, exit, do not restart a timer (if one is
12703 + * running, let it run out).
12707 + do_gettimeofday(&now);
12708 + if (now.tv_usec >= USEC_AFTER - ((unsigned) TICK_SIZE) / 2 &&
12709 + now.tv_usec <= USEC_BEFORE + ((unsigned) TICK_SIZE) / 2)
12710 + fail = set_rtc_mmss(now.tv_sec);
12712 + next.tv_usec = USEC_AFTER - now.tv_usec;
12713 + if (next.tv_usec <= 0)
12714 + next.tv_usec += USEC_PER_SEC;
12717 + next.tv_sec = 659;
12721 + if (next.tv_usec >= USEC_PER_SEC) {
12723 + next.tv_usec -= USEC_PER_SEC;
12725 + mod_timer(&sync_cmos_timer, jiffies + timeval_to_jiffies(&next));
12728 +void notify_arch_cmos_timer(void)
12730 + mod_timer(&sync_cmos_timer, jiffies + 1);
12731 + mod_timer(&sync_xen_wallclock_timer, jiffies + 1);
12734 +static int timer_resume(struct sys_device *dev)
12736 + extern void time_resume(void);
12741 +static struct sysdev_class timer_sysclass = {
12742 + .resume = timer_resume,
12743 + set_kset_name("timer"),
12747 +/* XXX this driverfs stuff should probably go elsewhere later -john */
12748 +static struct sys_device device_timer = {
12750 + .cls = &timer_sysclass,
12753 +static int time_init_device(void)
12755 + int error = sysdev_class_register(&timer_sysclass);
12757 + error = sysdev_register(&device_timer);
12761 +device_initcall(time_init_device);
12763 +#ifdef CONFIG_HPET_TIMER
12764 +extern void (*late_time_init)(void);
12765 +/* Duplicate of time_init() below, with hpet_enable part added */
12766 +static void __init hpet_time_init(void)
12768 + xtime.tv_sec = get_cmos_time();
12769 + xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
12770 + set_normalized_timespec(&wall_to_monotonic,
12771 + -xtime.tv_sec, -xtime.tv_nsec);
12773 + if ((hpet_enable() >= 0) && hpet_use_timer) {
12774 + printk("Using HPET for base-timer\n");
12777 + time_init_hook();
12781 +/* Dynamically-mapped IRQ. */
12782 +DEFINE_PER_CPU(int, timer_irq);
12784 +extern void (*late_time_init)(void);
12785 +static void setup_cpu0_timer_irq(void)
12787 + per_cpu(timer_irq, 0) =
12788 + bind_virq_to_irqhandler(
12795 + BUG_ON(per_cpu(timer_irq, 0) < 0);
12798 +static struct vcpu_set_periodic_timer xen_set_periodic_tick = {
12799 + .period_ns = NS_PER_TICK
12802 +void __init time_init(void)
12804 +#ifdef CONFIG_HPET_TIMER
12805 + if (is_hpet_capable()) {
12807 + * HPET initialization needs to do memory-mapped io. So, let
12808 + * us do a late initialization after mem_init().
12810 + late_time_init = hpet_time_init;
12815 + switch (HYPERVISOR_vcpu_op(VCPUOP_set_periodic_timer, 0,
12816 + &xen_set_periodic_tick)) {
12818 +#if CONFIG_XEN_COMPAT <= 0x030004
12826 + get_time_values_from_xen(0);
12828 + processed_system_time = per_cpu(shadow_time, 0).system_timestamp;
12829 + per_cpu(processed_system_time, 0) = processed_system_time;
12830 + init_missing_ticks_accounting(0);
12832 + update_wallclock();
12835 + printk(KERN_INFO "Xen reported: %u.%03u MHz processor.\n",
12836 + cpu_khz / 1000, cpu_khz % 1000);
12838 +#if defined(__x86_64__)
12839 + vxtime.mode = VXTIME_TSC;
12840 + vxtime.quot = (1000000L << 32) / vxtime_hz;
12841 + vxtime.tsc_quot = (1000L << 32) / cpu_khz;
12843 + rdtscll(vxtime.last_tsc);
12846 + /* Cannot request_irq() until kmem is initialised. */
12847 + late_time_init = setup_cpu0_timer_irq;
12850 +/* Convert jiffies to system time. */
12851 +u64 jiffies_to_st(unsigned long j)
12853 + unsigned long seq;
12858 + seq = read_seqbegin(&xtime_lock);
12859 + delta = j - jiffies;
12861 + /* Triggers in some wrap-around cases, but that's okay:
12862 + * we just end up with a shorter timeout. */
12863 + st = processed_system_time + NS_PER_TICK;
12864 + } else if (((unsigned long)delta >> (BITS_PER_LONG-3)) != 0) {
12865 + /* Very long timeout means there is no pending timer.
12866 + * We indicate this to Xen by passing zero timeout. */
12869 + st = processed_system_time + delta * (u64)NS_PER_TICK;
12871 + } while (read_seqretry(&xtime_lock, seq));
12875 +EXPORT_SYMBOL(jiffies_to_st);
12878 + * stop_hz_timer / start_hz_timer - enter/exit 'tickless mode' on an idle cpu
12879 + * These functions are based on implementations from arch/s390/kernel/time.c
12881 +static void stop_hz_timer(void)
12883 + struct vcpu_set_singleshot_timer singleshot;
12884 + unsigned int cpu = smp_processor_id();
12888 + cpu_set(cpu, nohz_cpu_mask);
12890 + /* See matching smp_mb in rcu_start_batch in rcupdate.c. These mbs */
12891 + /* ensure that if __rcu_pending (nested in rcu_needs_cpu) fetches a */
12892 + /* value of rcp->cur that matches rdp->quiescbatch and allows us to */
12893 + /* stop the hz timer then the cpumasks created for subsequent values */
12894 + /* of cur in rcu_start_batch are guaranteed to pick up the updated */
12895 + /* nohz_cpu_mask and so will not depend on this cpu. */
12899 + /* Leave ourselves in tick mode if rcu or softirq or timer pending. */
12900 + if (rcu_needs_cpu(cpu) || local_softirq_pending() ||
12901 + (j = next_timer_interrupt(), time_before_eq(j, jiffies))) {
12902 + cpu_clear(cpu, nohz_cpu_mask);
12906 + singleshot.timeout_abs_ns = jiffies_to_st(j) + NS_PER_TICK/2;
12907 + singleshot.flags = 0;
12908 + rc = HYPERVISOR_vcpu_op(VCPUOP_set_singleshot_timer, cpu, &singleshot);
12909 +#if CONFIG_XEN_COMPAT <= 0x030004
12911 + BUG_ON(rc != -ENOSYS);
12912 + rc = HYPERVISOR_set_timer_op(singleshot.timeout_abs_ns);
12918 +static void start_hz_timer(void)
12920 + cpu_clear(smp_processor_id(), nohz_cpu_mask);
12923 +void raw_safe_halt(void)
12926 + /* Blocking includes an implicit local_irq_enable(). */
12927 + HYPERVISOR_block();
12928 + start_hz_timer();
12930 +EXPORT_SYMBOL(raw_safe_halt);
12934 + if (irqs_disabled())
12935 + VOID(HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL));
12937 +EXPORT_SYMBOL(halt);
12939 +/* No locking required. Interrupts are disabled on all CPUs. */
12940 +void time_resume(void)
12942 + unsigned int cpu;
12946 + for_each_online_cpu(cpu) {
12947 + switch (HYPERVISOR_vcpu_op(VCPUOP_set_periodic_timer, cpu,
12948 + &xen_set_periodic_tick)) {
12950 +#if CONFIG_XEN_COMPAT <= 0x030004
12957 + get_time_values_from_xen(cpu);
12958 + per_cpu(processed_system_time, cpu) =
12959 + per_cpu(shadow_time, 0).system_timestamp;
12960 + init_missing_ticks_accounting(cpu);
12963 + processed_system_time = per_cpu(shadow_time, 0).system_timestamp;
12965 + update_wallclock();
12969 +static char timer_name[NR_CPUS][15];
12971 +int __cpuinit local_setup_timer(unsigned int cpu)
12975 + BUG_ON(cpu == 0);
12977 + switch (HYPERVISOR_vcpu_op(VCPUOP_set_periodic_timer, cpu,
12978 + &xen_set_periodic_tick)) {
12980 +#if CONFIG_XEN_COMPAT <= 0x030004
12989 + seq = read_seqbegin(&xtime_lock);
12990 + /* Use cpu0 timestamp: cpu's shadow is not initialised yet. */
12991 + per_cpu(processed_system_time, cpu) =
12992 + per_cpu(shadow_time, 0).system_timestamp;
12993 + init_missing_ticks_accounting(cpu);
12994 + } while (read_seqretry(&xtime_lock, seq));
12996 + sprintf(timer_name[cpu], "timer%u", cpu);
12997 + irq = bind_virq_to_irqhandler(VIRQ_TIMER,
13005 + per_cpu(timer_irq, cpu) = irq;
13010 +void __cpuexit local_teardown_timer(unsigned int cpu)
13012 + BUG_ON(cpu == 0);
13013 + unbind_from_irqhandler(per_cpu(timer_irq, cpu), NULL);
13017 +#ifdef CONFIG_CPU_FREQ
13018 +static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
13021 + struct cpufreq_freqs *freq = data;
13022 + struct xen_platform_op op;
13024 + if (cpu_has(&cpu_data[freq->cpu], X86_FEATURE_CONSTANT_TSC))
13027 + if (val == CPUFREQ_PRECHANGE)
13030 + op.cmd = XENPF_change_freq;
13031 + op.u.change_freq.flags = 0;
13032 + op.u.change_freq.cpu = freq->cpu;
13033 + op.u.change_freq.freq = (u64)freq->new * 1000;
13034 + WARN_ON(HYPERVISOR_platform_op(&op));
13039 +static struct notifier_block time_cpufreq_notifier_block = {
13040 + .notifier_call = time_cpufreq_notifier
13043 +static int __init cpufreq_time_setup(void)
13045 + if (!cpufreq_register_notifier(&time_cpufreq_notifier_block,
13046 + CPUFREQ_TRANSITION_NOTIFIER)) {
13047 + printk(KERN_ERR "failed to set up cpufreq notifier\n");
13053 +core_initcall(cpufreq_time_setup);
13057 + * /proc/sys/xen: This really belongs in another file. It can stay here for
13060 +static ctl_table xen_subtable[] = {
13063 + .procname = "independent_wallclock",
13064 + .data = &independent_wallclock,
13065 + .maxlen = sizeof(independent_wallclock),
13067 + .proc_handler = proc_dointvec
13071 + .procname = "permitted_clock_jitter",
13072 + .data = &permitted_clock_jitter,
13073 + .maxlen = sizeof(permitted_clock_jitter),
13075 + .proc_handler = proc_doulongvec_minmax
13079 +static ctl_table xen_table[] = {
13082 + .procname = "xen",
13084 + .child = xen_subtable},
13087 +static int __init xen_sysctl_init(void)
13089 + (void)register_sysctl_table(xen_table, 0);
13092 +__initcall(xen_sysctl_init);
13093 Index: head-2008-11-25/arch/x86/kernel/traps_32-xen.c
13094 ===================================================================
13095 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
13096 +++ head-2008-11-25/arch/x86/kernel/traps_32-xen.c 2008-04-02 12:34:02.000000000 +0200
13099 + * linux/arch/i386/traps.c
13101 + * Copyright (C) 1991, 1992 Linus Torvalds
13103 + * Pentium III FXSR, SSE support
13104 + * Gareth Hughes <gareth@valinux.com>, May 2000
13108 + * 'Traps.c' handles hardware traps and faults after we have saved some
13109 + * state in 'asm.s'.
13111 +#include <linux/sched.h>
13112 +#include <linux/kernel.h>
13113 +#include <linux/string.h>
13114 +#include <linux/errno.h>
13115 +#include <linux/timer.h>
13116 +#include <linux/mm.h>
13117 +#include <linux/init.h>
13118 +#include <linux/delay.h>
13119 +#include <linux/spinlock.h>
13120 +#include <linux/interrupt.h>
13121 +#include <linux/highmem.h>
13122 +#include <linux/kallsyms.h>
13123 +#include <linux/ptrace.h>
13124 +#include <linux/utsname.h>
13125 +#include <linux/kprobes.h>
13126 +#include <linux/kexec.h>
13127 +#include <linux/unwind.h>
13129 +#ifdef CONFIG_EISA
13130 +#include <linux/ioport.h>
13131 +#include <linux/eisa.h>
13135 +#include <linux/mca.h>
13138 +#include <asm/processor.h>
13139 +#include <asm/system.h>
13140 +#include <asm/uaccess.h>
13141 +#include <asm/io.h>
13142 +#include <asm/atomic.h>
13143 +#include <asm/debugreg.h>
13144 +#include <asm/desc.h>
13145 +#include <asm/i387.h>
13146 +#include <asm/nmi.h>
13147 +#include <asm/unwind.h>
13148 +#include <asm/smp.h>
13149 +#include <asm/arch_hooks.h>
13150 +#include <asm/kdebug.h>
13152 +#include <linux/module.h>
13154 +#include "mach_traps.h"
13156 +asmlinkage int system_call(void);
13158 +struct desc_struct default_ldt[] = { { 0, 0 }, { 0, 0 }, { 0, 0 },
13159 + { 0, 0 }, { 0, 0 } };
13161 +/* Do we ignore FPU interrupts ? */
13162 +char ignore_fpu_irq = 0;
13164 +#ifndef CONFIG_X86_NO_IDT
13166 + * The IDT has to be page-aligned to simplify the Pentium
13167 + * F0 0F bug workaround.. We have a special link segment
13170 +struct desc_struct idt_table[256] __attribute__((__section__(".data.idt"))) = { {0, 0}, };
13173 +asmlinkage void divide_error(void);
13174 +asmlinkage void debug(void);
13175 +asmlinkage void nmi(void);
13176 +asmlinkage void int3(void);
13177 +asmlinkage void overflow(void);
13178 +asmlinkage void bounds(void);
13179 +asmlinkage void invalid_op(void);
13180 +asmlinkage void device_not_available(void);
13181 +asmlinkage void coprocessor_segment_overrun(void);
13182 +asmlinkage void invalid_TSS(void);
13183 +asmlinkage void segment_not_present(void);
13184 +asmlinkage void stack_segment(void);
13185 +asmlinkage void general_protection(void);
13186 +asmlinkage void page_fault(void);
13187 +asmlinkage void coprocessor_error(void);
13188 +asmlinkage void simd_coprocessor_error(void);
13189 +asmlinkage void alignment_check(void);
13190 +#ifndef CONFIG_XEN
13191 +asmlinkage void spurious_interrupt_bug(void);
13193 +asmlinkage void fixup_4gb_segment(void);
13195 +asmlinkage void machine_check(void);
13197 +static int kstack_depth_to_print = 24;
13198 +#ifdef CONFIG_STACK_UNWIND
13199 +static int call_trace = 1;
13201 +#define call_trace (-1)
13203 +ATOMIC_NOTIFIER_HEAD(i386die_chain);
13205 +int register_die_notifier(struct notifier_block *nb)
13207 + vmalloc_sync_all();
13208 + return atomic_notifier_chain_register(&i386die_chain, nb);
13210 +EXPORT_SYMBOL(register_die_notifier); /* used modular by kdb */
13212 +int unregister_die_notifier(struct notifier_block *nb)
13214 + return atomic_notifier_chain_unregister(&i386die_chain, nb);
13216 +EXPORT_SYMBOL(unregister_die_notifier); /* used modular by kdb */
13218 +static inline int valid_stack_ptr(struct thread_info *tinfo, void *p)
13220 + return p > (void *)tinfo &&
13221 + p < (void *)tinfo + THREAD_SIZE - 3;
13225 + * Print one address/symbol entries per line.
13227 +static inline void print_addr_and_symbol(unsigned long addr, char *log_lvl)
13229 + printk(" [<%08lx>] ", addr);
13231 + print_symbol("%s\n", addr);
13234 +static inline unsigned long print_context_stack(struct thread_info *tinfo,
13235 + unsigned long *stack, unsigned long ebp,
13238 + unsigned long addr;
13240 +#ifdef CONFIG_FRAME_POINTER
13241 + while (valid_stack_ptr(tinfo, (void *)ebp)) {
13242 + addr = *(unsigned long *)(ebp + 4);
13243 + print_addr_and_symbol(addr, log_lvl);
13245 + * break out of recursive entries (such as
13246 + * end_of_stack_stop_unwind_function):
13248 + if (ebp == *(unsigned long *)ebp)
13250 + ebp = *(unsigned long *)ebp;
13253 + while (valid_stack_ptr(tinfo, stack)) {
13255 + if (__kernel_text_address(addr))
13256 + print_addr_and_symbol(addr, log_lvl);
13262 +static asmlinkage int
13263 +show_trace_unwind(struct unwind_frame_info *info, void *log_lvl)
13267 + while (unwind(info) == 0 && UNW_PC(info)) {
13269 + print_addr_and_symbol(UNW_PC(info), log_lvl);
13270 + if (arch_unw_user_mode(info))
13276 +static void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
13277 + unsigned long *stack, char *log_lvl)
13279 + unsigned long ebp;
13284 + if (call_trace >= 0) {
13286 + struct unwind_frame_info info;
13289 + if (unwind_init_frame_info(&info, task, regs) == 0)
13290 + unw_ret = show_trace_unwind(&info, log_lvl);
13291 + } else if (task == current)
13292 + unw_ret = unwind_init_running(&info, show_trace_unwind, log_lvl);
13294 + if (unwind_init_blocked(&info, task) == 0)
13295 + unw_ret = show_trace_unwind(&info, log_lvl);
13297 + if (unw_ret > 0) {
13298 + if (call_trace == 1 && !arch_unw_user_mode(&info)) {
13299 + print_symbol("DWARF2 unwinder stuck at %s\n",
13301 + if (UNW_SP(&info) >= PAGE_OFFSET) {
13302 + printk("Leftover inexact backtrace:\n");
13303 + stack = (void *)UNW_SP(&info);
13305 + printk("Full inexact backtrace again:\n");
13306 + } else if (call_trace >= 1)
13309 + printk("Full inexact backtrace again:\n");
13311 + printk("Inexact backtrace:\n");
13314 + if (task == current) {
13315 + /* Grab ebp right from our regs */
13316 + asm ("movl %%ebp, %0" : "=r" (ebp) : );
13318 + /* ebp is the last reg pushed by switch_to */
13319 + ebp = *(unsigned long *) task->thread.esp;
13323 + struct thread_info *context;
13324 + context = (struct thread_info *)
13325 + ((unsigned long)stack & (~(THREAD_SIZE - 1)));
13326 + ebp = print_context_stack(context, stack, ebp, log_lvl);
13327 + stack = (unsigned long*)context->previous_esp;
13330 + printk("%s =======================\n", log_lvl);
13334 +void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long * stack)
13336 + show_trace_log_lvl(task, regs, stack, "");
13339 +static void show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
13340 + unsigned long *esp, char *log_lvl)
13342 + unsigned long *stack;
13345 + if (esp == NULL) {
13347 + esp = (unsigned long*)task->thread.esp;
13349 + esp = (unsigned long *)&esp;
13353 + for(i = 0; i < kstack_depth_to_print; i++) {
13354 + if (kstack_end(stack))
13356 + if (i && ((i % 8) == 0))
13357 + printk("\n%s ", log_lvl);
13358 + printk("%08lx ", *stack++);
13360 + printk("\n%sCall Trace:\n", log_lvl);
13361 + show_trace_log_lvl(task, regs, esp, log_lvl);
13364 +void show_stack(struct task_struct *task, unsigned long *esp)
13367 + show_stack_log_lvl(task, NULL, esp, "");
13371 + * The architecture-independent dump_stack generator
13373 +void dump_stack(void)
13375 + unsigned long stack;
13377 + show_trace(current, NULL, &stack);
13380 +EXPORT_SYMBOL(dump_stack);
13382 +void show_registers(struct pt_regs *regs)
13385 + int in_kernel = 1;
13386 + unsigned long esp;
13387 + unsigned short ss;
13389 + esp = (unsigned long) (®s->esp);
13390 + savesegment(ss, ss);
13391 + if (user_mode_vm(regs)) {
13394 + ss = regs->xss & 0xffff;
13397 + printk(KERN_EMERG "CPU: %d\nEIP: %04x:[<%08lx>] %s VLI\n"
13398 + "EFLAGS: %08lx (%s %.*s) \n",
13399 + smp_processor_id(), 0xffff & regs->xcs, regs->eip,
13400 + print_tainted(), regs->eflags, system_utsname.release,
13401 + (int)strcspn(system_utsname.version, " "),
13402 + system_utsname.version);
13403 + print_symbol(KERN_EMERG "EIP is at %s\n", regs->eip);
13404 + printk(KERN_EMERG "eax: %08lx ebx: %08lx ecx: %08lx edx: %08lx\n",
13405 + regs->eax, regs->ebx, regs->ecx, regs->edx);
13406 + printk(KERN_EMERG "esi: %08lx edi: %08lx ebp: %08lx esp: %08lx\n",
13407 + regs->esi, regs->edi, regs->ebp, esp);
13408 + printk(KERN_EMERG "ds: %04x es: %04x ss: %04x\n",
13409 + regs->xds & 0xffff, regs->xes & 0xffff, ss);
13410 + printk(KERN_EMERG "Process %.*s (pid: %d, ti=%p task=%p task.ti=%p)",
13411 + TASK_COMM_LEN, current->comm, current->pid,
13412 + current_thread_info(), current, current->thread_info);
13414 + * When in-kernel, we also print out the stack and code at the
13415 + * time of the fault..
13420 + printk("\n" KERN_EMERG "Stack: ");
13421 + show_stack_log_lvl(NULL, regs, (unsigned long *)esp, KERN_EMERG);
13423 + printk(KERN_EMERG "Code: ");
13425 + eip = (u8 __user *)regs->eip - 43;
13426 + for (i = 0; i < 64; i++, eip++) {
13429 + if (eip < (u8 __user *)PAGE_OFFSET || __get_user(c, eip)) {
13430 + printk(" Bad EIP value.");
13433 + if (eip == (u8 __user *)regs->eip)
13434 + printk("<%02x> ", c);
13436 + printk("%02x ", c);
13442 +static void handle_BUG(struct pt_regs *regs)
13444 + unsigned long eip = regs->eip;
13445 + unsigned short ud2;
13447 + if (eip < PAGE_OFFSET)
13449 + if (__get_user(ud2, (unsigned short __user *)eip))
13451 + if (ud2 != 0x0b0f)
13454 + printk(KERN_EMERG "------------[ cut here ]------------\n");
13456 +#ifdef CONFIG_DEBUG_BUGVERBOSE
13458 + unsigned short line;
13462 + if (__get_user(line, (unsigned short __user *)(eip + 2)))
13464 + if (__get_user(file, (char * __user *)(eip + 4)) ||
13465 + (unsigned long)file < PAGE_OFFSET || __get_user(c, file))
13466 + file = "<bad filename>";
13468 + printk(KERN_EMERG "kernel BUG at %s:%d!\n", file, line);
13472 + printk(KERN_EMERG "Kernel BUG at [verbose debug info unavailable]\n");
13475 +/* This is gone through when something in the kernel
13476 + * has done something bad and is about to be terminated.
13478 +void die(const char * str, struct pt_regs * regs, long err)
13483 + int lock_owner_depth;
13485 + .lock = SPIN_LOCK_UNLOCKED,
13486 + .lock_owner = -1,
13487 + .lock_owner_depth = 0
13489 + static int die_counter;
13490 + unsigned long flags;
13494 + if (die.lock_owner != raw_smp_processor_id()) {
13495 + console_verbose();
13496 + spin_lock_irqsave(&die.lock, flags);
13497 + die.lock_owner = smp_processor_id();
13498 + die.lock_owner_depth = 0;
13499 + bust_spinlocks(1);
13502 + local_save_flags(flags);
13504 + if (++die.lock_owner_depth < 3) {
13506 + unsigned long esp;
13507 + unsigned short ss;
13509 + handle_BUG(regs);
13510 + printk(KERN_EMERG "%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
13511 +#ifdef CONFIG_PREEMPT
13512 + printk(KERN_EMERG "PREEMPT ");
13517 + printk(KERN_EMERG);
13521 +#ifdef CONFIG_DEBUG_PAGEALLOC
13523 + printk(KERN_EMERG);
13524 + printk("DEBUG_PAGEALLOC");
13529 + if (notify_die(DIE_OOPS, str, regs, err,
13530 + current->thread.trap_no, SIGSEGV) !=
13532 + show_registers(regs);
13533 + /* Executive summary in case the oops scrolled away */
13534 + esp = (unsigned long) (®s->esp);
13535 + savesegment(ss, ss);
13536 + if (user_mode(regs)) {
13538 + ss = regs->xss & 0xffff;
13540 + printk(KERN_EMERG "EIP: [<%08lx>] ", regs->eip);
13541 + print_symbol("%s", regs->eip);
13542 + printk(" SS:ESP %04x:%08lx\n", ss, esp);
13547 + printk(KERN_EMERG "Recursive die() failure, output suppressed\n");
13549 + bust_spinlocks(0);
13550 + die.lock_owner = -1;
13551 + spin_unlock_irqrestore(&die.lock, flags);
13556 + if (kexec_should_crash(current))
13557 + crash_kexec(regs);
13559 + if (in_interrupt())
13560 + panic("Fatal exception in interrupt");
13562 + if (panic_on_oops)
13563 + panic("Fatal exception");
13566 + do_exit(SIGSEGV);
13569 +static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
13571 + if (!user_mode_vm(regs))
13572 + die(str, regs, err);
13575 +static void __kprobes do_trap(int trapnr, int signr, char *str, int vm86,
13576 + struct pt_regs * regs, long error_code,
13579 + struct task_struct *tsk = current;
13580 + tsk->thread.error_code = error_code;
13581 + tsk->thread.trap_no = trapnr;
13583 + if (regs->eflags & VM_MASK) {
13586 + goto trap_signal;
13589 + if (!user_mode(regs))
13590 + goto kernel_trap;
13594 + force_sig_info(signr, info, tsk);
13596 + force_sig(signr, tsk);
13601 + if (!fixup_exception(regs))
13602 + die(str, regs, error_code);
13607 + int ret = handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, trapnr);
13608 + if (ret) goto trap_signal;
13613 +#define DO_ERROR(trapnr, signr, str, name) \
13614 +fastcall void do_##name(struct pt_regs * regs, long error_code) \
13616 + if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
13617 + == NOTIFY_STOP) \
13619 + do_trap(trapnr, signr, str, 0, regs, error_code, NULL); \
13622 +#define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
13623 +fastcall void do_##name(struct pt_regs * regs, long error_code) \
13625 + siginfo_t info; \
13626 + info.si_signo = signr; \
13627 + info.si_errno = 0; \
13628 + info.si_code = sicode; \
13629 + info.si_addr = (void __user *)siaddr; \
13630 + if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
13631 + == NOTIFY_STOP) \
13633 + do_trap(trapnr, signr, str, 0, regs, error_code, &info); \
13636 +#define DO_VM86_ERROR(trapnr, signr, str, name) \
13637 +fastcall void do_##name(struct pt_regs * regs, long error_code) \
13639 + if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
13640 + == NOTIFY_STOP) \
13642 + do_trap(trapnr, signr, str, 1, regs, error_code, NULL); \
13645 +#define DO_VM86_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
13646 +fastcall void do_##name(struct pt_regs * regs, long error_code) \
13648 + siginfo_t info; \
13649 + info.si_signo = signr; \
13650 + info.si_errno = 0; \
13651 + info.si_code = sicode; \
13652 + info.si_addr = (void __user *)siaddr; \
13653 + if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
13654 + == NOTIFY_STOP) \
13656 + do_trap(trapnr, signr, str, 1, regs, error_code, &info); \
13659 +DO_VM86_ERROR_INFO( 0, SIGFPE, "divide error", divide_error, FPE_INTDIV, regs->eip)
13660 +#ifndef CONFIG_KPROBES
13661 +DO_VM86_ERROR( 3, SIGTRAP, "int3", int3)
13663 +DO_VM86_ERROR( 4, SIGSEGV, "overflow", overflow)
13664 +DO_VM86_ERROR( 5, SIGSEGV, "bounds", bounds)
13665 +DO_ERROR_INFO( 6, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN, regs->eip)
13666 +DO_ERROR( 9, SIGFPE, "coprocessor segment overrun", coprocessor_segment_overrun)
13667 +DO_ERROR(10, SIGSEGV, "invalid TSS", invalid_TSS)
13668 +DO_ERROR(11, SIGBUS, "segment not present", segment_not_present)
13669 +DO_ERROR(12, SIGBUS, "stack segment", stack_segment)
13670 +DO_ERROR_INFO(17, SIGBUS, "alignment check", alignment_check, BUS_ADRALN, 0)
13671 +DO_ERROR_INFO(32, SIGSEGV, "iret exception", iret_error, ILL_BADSTK, 0)
13673 +fastcall void __kprobes do_general_protection(struct pt_regs * regs,
13676 + current->thread.error_code = error_code;
13677 + current->thread.trap_no = 13;
13679 + if (regs->eflags & VM_MASK)
13682 + if (!user_mode(regs))
13683 + goto gp_in_kernel;
13685 + current->thread.error_code = error_code;
13686 + current->thread.trap_no = 13;
13687 + force_sig(SIGSEGV, current);
13691 + local_irq_enable();
13692 + handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
13696 + if (!fixup_exception(regs)) {
13697 + if (notify_die(DIE_GPF, "general protection fault", regs,
13698 + error_code, 13, SIGSEGV) == NOTIFY_STOP)
13700 + die("general protection fault", regs, error_code);
13704 +static void mem_parity_error(unsigned char reason, struct pt_regs * regs)
13706 + printk(KERN_EMERG "Uhhuh. NMI received. Dazed and confused, but trying "
13707 + "to continue\n");
13708 + printk(KERN_EMERG "You probably have a hardware problem with your RAM "
13711 + /* Clear and disable the memory parity error line. */
13712 + clear_mem_error(reason);
13715 +static void io_check_error(unsigned char reason, struct pt_regs * regs)
13717 + printk(KERN_EMERG "NMI: IOCK error (debug interrupt?)\n");
13718 + show_registers(regs);
13720 + /* Re-enable the IOCK line, wait for a few seconds */
13721 + clear_io_check_error(reason);
13724 +static void unknown_nmi_error(unsigned char reason, struct pt_regs * regs)
13727 + /* Might actually be able to figure out what the guilty party
13730 + mca_handle_nmi();
13734 + printk("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
13735 + reason, smp_processor_id());
13736 + printk("Dazed and confused, but trying to continue\n");
13737 + printk("Do you have a strange power saving mode enabled?\n");
13740 +static DEFINE_SPINLOCK(nmi_print_lock);
13742 +void die_nmi (struct pt_regs *regs, const char *msg)
13744 + if (notify_die(DIE_NMIWATCHDOG, msg, regs, 0, 2, SIGINT) ==
13748 + spin_lock(&nmi_print_lock);
13750 + * We are in trouble anyway, lets at least try
13751 + * to get a message out.
13753 + bust_spinlocks(1);
13754 + printk(KERN_EMERG "%s", msg);
13755 + printk(" on CPU%d, eip %08lx, registers:\n",
13756 + smp_processor_id(), regs->eip);
13757 + show_registers(regs);
13758 + printk(KERN_EMERG "console shuts up ...\n");
13759 + console_silent();
13760 + spin_unlock(&nmi_print_lock);
13761 + bust_spinlocks(0);
13763 + /* If we are in kernel we are probably nested up pretty bad
13764 + * and might aswell get out now while we still can.
13766 + if (!user_mode_vm(regs)) {
13767 + current->thread.trap_no = 2;
13768 + crash_kexec(regs);
13771 + do_exit(SIGSEGV);
13774 +static void default_do_nmi(struct pt_regs * regs)
13776 + unsigned char reason = 0;
13778 + /* Only the BSP gets external NMIs from the system. */
13779 + if (!smp_processor_id())
13780 + reason = get_nmi_reason();
13782 + if (!(reason & 0xc0)) {
13783 + if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT)
13786 +#ifdef CONFIG_X86_LOCAL_APIC
13788 + * Ok, so this is none of the documented NMI sources,
13789 + * so it must be the NMI watchdog.
13791 + if (nmi_watchdog) {
13792 + nmi_watchdog_tick(regs);
13796 + unknown_nmi_error(reason, regs);
13799 + if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
13801 + if (reason & 0x80)
13802 + mem_parity_error(reason, regs);
13803 + if (reason & 0x40)
13804 + io_check_error(reason, regs);
13806 + * Reassert NMI in case it became active meanwhile
13807 + * as it's edge-triggered.
13812 +static int dummy_nmi_callback(struct pt_regs * regs, int cpu)
13817 +static nmi_callback_t nmi_callback = dummy_nmi_callback;
13819 +fastcall void do_nmi(struct pt_regs * regs, long error_code)
13825 + cpu = smp_processor_id();
13827 + ++nmi_count(cpu);
13829 + if (!rcu_dereference(nmi_callback)(regs, cpu))
13830 + default_do_nmi(regs);
13835 +void set_nmi_callback(nmi_callback_t callback)
13837 + vmalloc_sync_all();
13838 + rcu_assign_pointer(nmi_callback, callback);
13840 +EXPORT_SYMBOL_GPL(set_nmi_callback);
13842 +void unset_nmi_callback(void)
13844 + nmi_callback = dummy_nmi_callback;
13846 +EXPORT_SYMBOL_GPL(unset_nmi_callback);
13848 +#ifdef CONFIG_KPROBES
13849 +fastcall void __kprobes do_int3(struct pt_regs *regs, long error_code)
13851 + if (notify_die(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP)
13854 + /* This is an interrupt gate, because kprobes wants interrupts
13855 + disabled. Normal trap handlers don't. */
13856 + restore_interrupts(regs);
13857 + do_trap(3, SIGTRAP, "int3", 1, regs, error_code, NULL);
13862 + * Our handling of the processor debug registers is non-trivial.
13863 + * We do not clear them on entry and exit from the kernel. Therefore
13864 + * it is possible to get a watchpoint trap here from inside the kernel.
13865 + * However, the code in ./ptrace.c has ensured that the user can
13866 + * only set watchpoints on userspace addresses. Therefore the in-kernel
13867 + * watchpoint trap can only occur in code which is reading/writing
13868 + * from user space. Such code must not hold kernel locks (since it
13869 + * can equally take a page fault), therefore it is safe to call
13870 + * force_sig_info even though that claims and releases locks.
13872 + * Code in ./signal.c ensures that the debug control register
13873 + * is restored before we deliver any signal, and therefore that
13874 + * user code runs with the correct debug control register even though
13875 + * we clear it here.
13877 + * Being careful here means that we don't have to be as careful in a
13878 + * lot of more complicated places (task switching can be a bit lazy
13879 + * about restoring all the debug state, and ptrace doesn't have to
13880 + * find every occurrence of the TF bit that could be saved away even
13883 +fastcall void __kprobes do_debug(struct pt_regs * regs, long error_code)
13885 + unsigned int condition;
13886 + struct task_struct *tsk = current;
13888 + get_debugreg(condition, 6);
13890 + if (notify_die(DIE_DEBUG, "debug", regs, condition, error_code,
13891 + SIGTRAP) == NOTIFY_STOP)
13893 + /* It's safe to allow irq's after DR6 has been saved */
13894 + if (regs->eflags & X86_EFLAGS_IF)
13895 + local_irq_enable();
13897 + /* Mask out spurious debug traps due to lazy DR7 setting */
13898 + if (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)) {
13899 + if (!tsk->thread.debugreg[7])
13903 + if (regs->eflags & VM_MASK)
13906 + /* Save debug status register where ptrace can see it */
13907 + tsk->thread.debugreg[6] = condition;
13910 + * Single-stepping through TF: make sure we ignore any events in
13911 + * kernel space (but re-enable TF when returning to user mode).
13913 + if (condition & DR_STEP) {
13915 + * We already checked v86 mode above, so we can
13916 + * check for kernel mode by just checking the CPL
13919 + if (!user_mode(regs))
13920 + goto clear_TF_reenable;
13923 + /* Ok, finally something we can handle */
13924 + send_sigtrap(tsk, regs, error_code);
13926 + /* Disable additional traps. They'll be re-enabled when
13927 + * the signal is delivered.
13930 + set_debugreg(0, 7);
13934 + handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, 1);
13937 +clear_TF_reenable:
13938 + set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
13939 + regs->eflags &= ~TF_MASK;
13944 + * Note that we play around with the 'TS' bit in an attempt to get
13945 + * the correct behaviour even in the presence of the asynchronous
13946 + * IRQ13 behaviour
13948 +void math_error(void __user *eip)
13950 + struct task_struct * task;
13952 + unsigned short cwd, swd;
13955 + * Save the info for the exception handler and clear the error.
13958 + save_init_fpu(task);
13959 + task->thread.trap_no = 16;
13960 + task->thread.error_code = 0;
13961 + info.si_signo = SIGFPE;
13962 + info.si_errno = 0;
13963 + info.si_code = __SI_FAULT;
13964 + info.si_addr = eip;
13966 + * (~cwd & swd) will mask out exceptions that are not set to unmasked
13967 + * status. 0x3f is the exception bits in these regs, 0x200 is the
13968 + * C1 reg you need in case of a stack fault, 0x040 is the stack
13969 + * fault bit. We should only be taking one exception at a time,
13970 + * so if this combination doesn't produce any single exception,
13971 + * then we have a bad program that isn't syncronizing its FPU usage
13972 + * and it will suffer the consequences since we won't be able to
13973 + * fully reproduce the context of the exception
13975 + cwd = get_fpu_cwd(task);
13976 + swd = get_fpu_swd(task);
13977 + switch (swd & ~cwd & 0x3f) {
13978 + case 0x000: /* No unmasked exception */
13980 + default: /* Multiple exceptions */
13982 + case 0x001: /* Invalid Op */
13984 + * swd & 0x240 == 0x040: Stack Underflow
13985 + * swd & 0x240 == 0x240: Stack Overflow
13986 + * User must clear the SF bit (0x40) if set
13988 + info.si_code = FPE_FLTINV;
13990 + case 0x002: /* Denormalize */
13991 + case 0x010: /* Underflow */
13992 + info.si_code = FPE_FLTUND;
13994 + case 0x004: /* Zero Divide */
13995 + info.si_code = FPE_FLTDIV;
13997 + case 0x008: /* Overflow */
13998 + info.si_code = FPE_FLTOVF;
14000 + case 0x020: /* Precision */
14001 + info.si_code = FPE_FLTRES;
14004 + force_sig_info(SIGFPE, &info, task);
14007 +fastcall void do_coprocessor_error(struct pt_regs * regs, long error_code)
14009 + ignore_fpu_irq = 1;
14010 + math_error((void __user *)regs->eip);
14013 +static void simd_math_error(void __user *eip)
14015 + struct task_struct * task;
14017 + unsigned short mxcsr;
14020 + * Save the info for the exception handler and clear the error.
14023 + save_init_fpu(task);
14024 + task->thread.trap_no = 19;
14025 + task->thread.error_code = 0;
14026 + info.si_signo = SIGFPE;
14027 + info.si_errno = 0;
14028 + info.si_code = __SI_FAULT;
14029 + info.si_addr = eip;
14031 + * The SIMD FPU exceptions are handled a little differently, as there
14032 + * is only a single status/control register. Thus, to determine which
14033 + * unmasked exception was caught we must mask the exception mask bits
14034 + * at 0x1f80, and then use these to mask the exception bits at 0x3f.
14036 + mxcsr = get_fpu_mxcsr(task);
14037 + switch (~((mxcsr & 0x1f80) >> 7) & (mxcsr & 0x3f)) {
14041 + case 0x001: /* Invalid Op */
14042 + info.si_code = FPE_FLTINV;
14044 + case 0x002: /* Denormalize */
14045 + case 0x010: /* Underflow */
14046 + info.si_code = FPE_FLTUND;
14048 + case 0x004: /* Zero Divide */
14049 + info.si_code = FPE_FLTDIV;
14051 + case 0x008: /* Overflow */
14052 + info.si_code = FPE_FLTOVF;
14054 + case 0x020: /* Precision */
14055 + info.si_code = FPE_FLTRES;
14058 + force_sig_info(SIGFPE, &info, task);
14061 +fastcall void do_simd_coprocessor_error(struct pt_regs * regs,
14064 + if (cpu_has_xmm) {
14065 + /* Handle SIMD FPU exceptions on PIII+ processors. */
14066 + ignore_fpu_irq = 1;
14067 + simd_math_error((void __user *)regs->eip);
14070 + * Handle strange cache flush from user space exception
14071 + * in all other cases. This is undocumented behaviour.
14073 + if (regs->eflags & VM_MASK) {
14074 + handle_vm86_fault((struct kernel_vm86_regs *)regs,
14078 + current->thread.trap_no = 19;
14079 + current->thread.error_code = error_code;
14080 + die_if_kernel("cache flush denied", regs, error_code);
14081 + force_sig(SIGSEGV, current);
14085 +#ifndef CONFIG_XEN
14086 +fastcall void do_spurious_interrupt_bug(struct pt_regs * regs,
14090 + /* No need to warn about this any longer. */
14091 + printk("Ignoring P6 Local APIC Spurious Interrupt Bug...\n");
14095 +fastcall void setup_x86_bogus_stack(unsigned char * stk)
14097 + unsigned long *switch16_ptr, *switch32_ptr;
14098 + struct pt_regs *regs;
14099 + unsigned long stack_top, stack_bot;
14100 + unsigned short iret_frame16_off;
14101 + int cpu = smp_processor_id();
14102 + /* reserve the space on 32bit stack for the magic switch16 pointer */
14103 + memmove(stk, stk + 8, sizeof(struct pt_regs));
14104 + switch16_ptr = (unsigned long *)(stk + sizeof(struct pt_regs));
14105 + regs = (struct pt_regs *)stk;
14106 + /* now the switch32 on 16bit stack */
14107 + stack_bot = (unsigned long)&per_cpu(cpu_16bit_stack, cpu);
14108 + stack_top = stack_bot + CPU_16BIT_STACK_SIZE;
14109 + switch32_ptr = (unsigned long *)(stack_top - 8);
14110 + iret_frame16_off = CPU_16BIT_STACK_SIZE - 8 - 20;
14111 + /* copy iret frame on 16bit stack */
14112 + memcpy((void *)(stack_bot + iret_frame16_off), ®s->eip, 20);
14113 + /* fill in the switch pointers */
14114 + switch16_ptr[0] = (regs->esp & 0xffff0000) | iret_frame16_off;
14115 + switch16_ptr[1] = __ESPFIX_SS;
14116 + switch32_ptr[0] = (unsigned long)stk + sizeof(struct pt_regs) +
14117 + 8 - CPU_16BIT_STACK_SIZE;
14118 + switch32_ptr[1] = __KERNEL_DS;
14121 +fastcall unsigned char * fixup_x86_bogus_stack(unsigned short sp)
14123 + unsigned long *switch32_ptr;
14124 + unsigned char *stack16, *stack32;
14125 + unsigned long stack_top, stack_bot;
14127 + int cpu = smp_processor_id();
14128 + stack_bot = (unsigned long)&per_cpu(cpu_16bit_stack, cpu);
14129 + stack_top = stack_bot + CPU_16BIT_STACK_SIZE;
14130 + switch32_ptr = (unsigned long *)(stack_top - 8);
14131 + /* copy the data from 16bit stack to 32bit stack */
14132 + len = CPU_16BIT_STACK_SIZE - 8 - sp;
14133 + stack16 = (unsigned char *)(stack_bot + sp);
14134 + stack32 = (unsigned char *)
14135 + (switch32_ptr[0] + CPU_16BIT_STACK_SIZE - 8 - len);
14136 + memcpy(stack32, stack16, len);
14142 + * 'math_state_restore()' saves the current math information in the
14143 + * old math state array, and gets the new ones from the current task
14145 + * Careful.. There are problems with IBM-designed IRQ13 behaviour.
14146 + * Don't touch unless you *really* know how it works.
14148 + * Must be called with kernel preemption disabled (in this case,
14149 + * local interrupts are disabled at the call-site in entry.S).
14151 +asmlinkage void math_state_restore(struct pt_regs regs)
14153 + struct thread_info *thread = current_thread_info();
14154 + struct task_struct *tsk = thread->task;
14156 + /* NB. 'clts' is done for us by Xen during virtual trap. */
14157 + if (!tsk_used_math(tsk))
14159 + restore_fpu(tsk);
14160 + thread->status |= TS_USEDFPU; /* So we fnsave on switch_to() */
14163 +#ifndef CONFIG_MATH_EMULATION
14165 +asmlinkage void math_emulate(long arg)
14167 + printk(KERN_EMERG "math-emulation not enabled and no coprocessor found.\n");
14168 + printk(KERN_EMERG "killing %s.\n",current->comm);
14169 + force_sig(SIGFPE,current);
14173 +#endif /* CONFIG_MATH_EMULATION */
14175 +#ifdef CONFIG_X86_F00F_BUG
14176 +void __init trap_init_f00f_bug(void)
14178 + __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
14181 + * Update the IDT descriptor and reload the IDT so that
14182 + * it uses the read-only mapped virtual address.
14184 + idt_descr.address = fix_to_virt(FIX_F00F_IDT);
14185 + load_idt(&idt_descr);
14191 + * NB. All these are "trap gates" (i.e. events_mask isn't set) except
14192 + * for those that specify <dpl>|4 in the second field.
14194 +static trap_info_t __cpuinitdata trap_table[] = {
14195 + { 0, 0, __KERNEL_CS, (unsigned long)divide_error },
14196 + { 1, 0|4, __KERNEL_CS, (unsigned long)debug },
14197 + { 3, 3|4, __KERNEL_CS, (unsigned long)int3 },
14198 + { 4, 3, __KERNEL_CS, (unsigned long)overflow },
14199 + { 5, 0, __KERNEL_CS, (unsigned long)bounds },
14200 + { 6, 0, __KERNEL_CS, (unsigned long)invalid_op },
14201 + { 7, 0|4, __KERNEL_CS, (unsigned long)device_not_available },
14202 + { 9, 0, __KERNEL_CS, (unsigned long)coprocessor_segment_overrun },
14203 + { 10, 0, __KERNEL_CS, (unsigned long)invalid_TSS },
14204 + { 11, 0, __KERNEL_CS, (unsigned long)segment_not_present },
14205 + { 12, 0, __KERNEL_CS, (unsigned long)stack_segment },
14206 + { 13, 0, __KERNEL_CS, (unsigned long)general_protection },
14207 + { 14, 0|4, __KERNEL_CS, (unsigned long)page_fault },
14208 + { 15, 0, __KERNEL_CS, (unsigned long)fixup_4gb_segment },
14209 + { 16, 0, __KERNEL_CS, (unsigned long)coprocessor_error },
14210 + { 17, 0, __KERNEL_CS, (unsigned long)alignment_check },
14211 +#ifdef CONFIG_X86_MCE
14212 + { 18, 0, __KERNEL_CS, (unsigned long)machine_check },
14214 + { 19, 0, __KERNEL_CS, (unsigned long)simd_coprocessor_error },
14215 + { SYSCALL_VECTOR, 3, __KERNEL_CS, (unsigned long)system_call },
14219 +void __init trap_init(void)
14223 + ret = HYPERVISOR_set_trap_table(trap_table);
14225 + printk("HYPERVISOR_set_trap_table failed: error %d\n", ret);
14227 + if (cpu_has_fxsr) {
14229 + * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned.
14230 + * Generates a compile-time "error: zero width for bit-field" if
14231 + * the alignment is wrong.
14233 + struct fxsrAlignAssert {
14234 + int _:!(offsetof(struct task_struct,
14235 + thread.i387.fxsave) & 15);
14238 + printk(KERN_INFO "Enabling fast FPU save and restore... ");
14239 + set_in_cr4(X86_CR4_OSFXSR);
14240 + printk("done.\n");
14242 + if (cpu_has_xmm) {
14243 + printk(KERN_INFO "Enabling unmasked SIMD FPU exception "
14245 + set_in_cr4(X86_CR4_OSXMMEXCPT);
14246 + printk("done.\n");
14250 + * Should be a barrier for any external CPU state.
14255 +void __cpuinit smp_trap_init(trap_info_t *trap_ctxt)
14257 + const trap_info_t *t = trap_table;
14259 + for (t = trap_table; t->address; t++) {
14260 + trap_ctxt[t->vector].flags = t->flags;
14261 + trap_ctxt[t->vector].cs = t->cs;
14262 + trap_ctxt[t->vector].address = t->address;
14266 +static int __init kstack_setup(char *s)
14268 + kstack_depth_to_print = simple_strtoul(s, NULL, 0);
14271 +__setup("kstack=", kstack_setup);
14273 +#ifdef CONFIG_STACK_UNWIND
14274 +static int __init call_trace_setup(char *s)
14276 + if (strcmp(s, "old") == 0)
14278 + else if (strcmp(s, "both") == 0)
14280 + else if (strcmp(s, "newfallback") == 0)
14282 + else if (strcmp(s, "new") == 2)
14286 +__setup("call_trace=", call_trace_setup);
14288 Index: head-2008-11-25/arch/x86/mach-xen/Makefile
14289 ===================================================================
14290 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
14291 +++ head-2008-11-25/arch/x86/mach-xen/Makefile 2007-06-12 13:12:48.000000000 +0200
14294 +# Makefile for the linux kernel.
14298 Index: head-2008-11-25/arch/x86/mach-xen/setup.c
14299 ===================================================================
14300 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
14301 +++ head-2008-11-25/arch/x86/mach-xen/setup.c 2008-04-02 12:34:02.000000000 +0200
14304 + * Machine specific setup for generic
14307 +#include <linux/mm.h>
14308 +#include <linux/smp.h>
14309 +#include <linux/init.h>
14310 +#include <linux/interrupt.h>
14311 +#include <linux/module.h>
14312 +#include <asm/acpi.h>
14313 +#include <asm/arch_hooks.h>
14314 +#include <asm/e820.h>
14315 +#include <asm/setup.h>
14316 +#include <asm/fixmap.h>
14318 +#include <xen/interface/callback.h>
14319 +#include <xen/interface/memory.h>
14321 +#ifdef CONFIG_HOTPLUG_CPU
14322 +#define DEFAULT_SEND_IPI (1)
14324 +#define DEFAULT_SEND_IPI (0)
14327 +int no_broadcast=DEFAULT_SEND_IPI;
14329 +static __init int no_ipi_broadcast(char *str)
14331 + get_option(&str, &no_broadcast);
14332 + printk ("Using %s mode\n", no_broadcast ? "No IPI Broadcast" :
14333 + "IPI Broadcast");
14337 +__setup("no_ipi_broadcast", no_ipi_broadcast);
14339 +static int __init print_ipi_mode(void)
14341 + printk ("Using IPI %s mode\n", no_broadcast ? "No-Shortcut" :
14346 +late_initcall(print_ipi_mode);
14349 + * machine_specific_memory_setup - Hook for machine specific memory setup.
14352 + * This is included late in kernel/setup.c so that it can make
14353 + * use of all of the static functions.
14356 +char * __init machine_specific_memory_setup(void)
14359 + struct xen_memory_map memmap;
14361 + * This is rather large for a stack variable but this early in
14362 + * the boot process we know we have plenty slack space.
14364 + struct e820entry map[E820MAX];
14366 + memmap.nr_entries = E820MAX;
14367 + set_xen_guest_handle(memmap.buffer, map);
14369 + rc = HYPERVISOR_memory_op(XENMEM_memory_map, &memmap);
14370 + if ( rc == -ENOSYS ) {
14371 + memmap.nr_entries = 1;
14372 + map[0].addr = 0ULL;
14373 + map[0].size = PFN_PHYS((unsigned long long)xen_start_info->nr_pages);
14374 + /* 8MB slack (to balance backend allocations). */
14375 + map[0].size += 8ULL << 20;
14376 + map[0].type = E820_RAM;
14381 + sanitize_e820_map(map, (char *)&memmap.nr_entries);
14383 + BUG_ON(copy_e820_map(map, (char)memmap.nr_entries) < 0);
14389 +extern void hypervisor_callback(void);
14390 +extern void failsafe_callback(void);
14391 +extern void nmi(void);
14393 +unsigned long *machine_to_phys_mapping = (void *)MACH2PHYS_VIRT_START;
14394 +EXPORT_SYMBOL(machine_to_phys_mapping);
14395 +unsigned int machine_to_phys_order;
14396 +EXPORT_SYMBOL(machine_to_phys_order);
14398 +void __init pre_setup_arch_hook(void)
14400 + struct xen_machphys_mapping mapping;
14401 + unsigned long machine_to_phys_nr_ents;
14402 + struct xen_platform_parameters pp;
14404 + init_mm.pgd = swapper_pg_dir = (pgd_t *)xen_start_info->pt_base;
14406 + setup_xen_features();
14408 + if (HYPERVISOR_xen_version(XENVER_platform_parameters, &pp) == 0)
14409 + set_fixaddr_top(pp.virt_start);
14411 + if (HYPERVISOR_memory_op(XENMEM_machphys_mapping, &mapping) == 0) {
14412 + machine_to_phys_mapping = (unsigned long *)mapping.v_start;
14413 + machine_to_phys_nr_ents = mapping.max_mfn + 1;
14415 + machine_to_phys_nr_ents = MACH2PHYS_NR_ENTRIES;
14416 + machine_to_phys_order = fls(machine_to_phys_nr_ents - 1);
14418 + if (!xen_feature(XENFEAT_auto_translated_physmap))
14419 + phys_to_machine_mapping =
14420 + (unsigned long *)xen_start_info->mfn_list;
14423 +void __init machine_specific_arch_setup(void)
14426 + static struct callback_register __initdata event = {
14427 + .type = CALLBACKTYPE_event,
14428 + .address = { __KERNEL_CS, (unsigned long)hypervisor_callback },
14430 + static struct callback_register __initdata failsafe = {
14431 + .type = CALLBACKTYPE_failsafe,
14432 + .address = { __KERNEL_CS, (unsigned long)failsafe_callback },
14434 + static struct callback_register __initdata nmi_cb = {
14435 + .type = CALLBACKTYPE_nmi,
14436 + .address = { __KERNEL_CS, (unsigned long)nmi },
14439 + ret = HYPERVISOR_callback_op(CALLBACKOP_register, &event);
14441 + ret = HYPERVISOR_callback_op(CALLBACKOP_register, &failsafe);
14442 +#if CONFIG_XEN_COMPAT <= 0x030002
14443 + if (ret == -ENOSYS)
14444 + ret = HYPERVISOR_set_callbacks(
14445 + event.address.cs, event.address.eip,
14446 + failsafe.address.cs, failsafe.address.eip);
14450 + ret = HYPERVISOR_callback_op(CALLBACKOP_register, &nmi_cb);
14451 +#if CONFIG_XEN_COMPAT <= 0x030002
14452 + if (ret == -ENOSYS) {
14453 + static struct xennmi_callback __initdata cb = {
14454 + .handler_address = (unsigned long)nmi
14457 + HYPERVISOR_nmi_op(XENNMI_register_callback, &cb);
14461 Index: head-2008-11-25/arch/x86/lib/scrub.c
14462 ===================================================================
14463 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
14464 +++ head-2008-11-25/arch/x86/lib/scrub.c 2008-02-08 12:30:51.000000000 +0100
14466 +#include <asm/cpufeature.h>
14467 +#include <asm/page.h>
14468 +#include <asm/processor.h>
14470 +void scrub_pages(void *v, unsigned int count)
14472 + if (likely(cpu_has_xmm2)) {
14473 + unsigned long n = count * (PAGE_SIZE / sizeof(long) / 4);
14475 + for (; n--; v += sizeof(long) * 4)
14476 + asm("movnti %1,(%0)\n\t"
14477 + "movnti %1,%c2(%0)\n\t"
14478 + "movnti %1,2*%c2(%0)\n\t"
14479 + "movnti %1,3*%c2(%0)\n\t"
14480 + : : "r" (v), "r" (0L), "i" (sizeof(long))
14482 + asm volatile("sfence" : : : "memory");
14484 + for (; count--; v += PAGE_SIZE)
14487 Index: head-2008-11-25/arch/x86/mm/fault_32-xen.c
14488 ===================================================================
14489 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
14490 +++ head-2008-11-25/arch/x86/mm/fault_32-xen.c 2007-12-10 08:47:31.000000000 +0100
14493 + * linux/arch/i386/mm/fault.c
14495 + * Copyright (C) 1995 Linus Torvalds
14498 +#include <linux/signal.h>
14499 +#include <linux/sched.h>
14500 +#include <linux/kernel.h>
14501 +#include <linux/errno.h>
14502 +#include <linux/string.h>
14503 +#include <linux/types.h>
14504 +#include <linux/ptrace.h>
14505 +#include <linux/mman.h>
14506 +#include <linux/mm.h>
14507 +#include <linux/smp.h>
14508 +#include <linux/smp_lock.h>
14509 +#include <linux/interrupt.h>
14510 +#include <linux/init.h>
14511 +#include <linux/tty.h>
14512 +#include <linux/vt_kern.h> /* For unblank_screen() */
14513 +#include <linux/highmem.h>
14514 +#include <linux/module.h>
14515 +#include <linux/kprobes.h>
14517 +#include <asm/system.h>
14518 +#include <asm/uaccess.h>
14519 +#include <asm/desc.h>
14520 +#include <asm/kdebug.h>
14522 +extern void die(const char *,struct pt_regs *,long);
14524 +#ifdef CONFIG_KPROBES
14525 +ATOMIC_NOTIFIER_HEAD(notify_page_fault_chain);
14526 +int register_page_fault_notifier(struct notifier_block *nb)
14528 + vmalloc_sync_all();
14529 + return atomic_notifier_chain_register(¬ify_page_fault_chain, nb);
14532 +int unregister_page_fault_notifier(struct notifier_block *nb)
14534 + return atomic_notifier_chain_unregister(¬ify_page_fault_chain, nb);
14537 +static inline int notify_page_fault(enum die_val val, const char *str,
14538 + struct pt_regs *regs, long err, int trap, int sig)
14540 + struct die_args args = {
14547 + return atomic_notifier_call_chain(¬ify_page_fault_chain, val, &args);
14550 +static inline int notify_page_fault(enum die_val val, const char *str,
14551 + struct pt_regs *regs, long err, int trap, int sig)
14553 + return NOTIFY_DONE;
14559 + * Unlock any spinlocks which will prevent us from getting the
14562 +void bust_spinlocks(int yes)
14564 + int loglevel_save = console_loglevel;
14567 + oops_in_progress = 1;
14571 + unblank_screen();
14573 + oops_in_progress = 0;
14575 + * OK, the message is on the console. Now we call printk()
14576 + * without oops_in_progress set so that printk will give klogd
14577 + * a poke. Hold onto your hats...
14579 + console_loglevel = 15; /* NMI oopser may have shut the console up */
14581 + console_loglevel = loglevel_save;
14585 + * Return EIP plus the CS segment base. The segment limit is also
14586 + * adjusted, clamped to the kernel/user address space (whichever is
14587 + * appropriate), and returned in *eip_limit.
14589 + * The segment is checked, because it might have been changed by another
14590 + * task between the original faulting instruction and here.
14592 + * If CS is no longer a valid code segment, or if EIP is beyond the
14593 + * limit, or if it is a kernel address when CS is not a kernel segment,
14594 + * then the returned value will be greater than *eip_limit.
14596 + * This is slow, but is very rarely executed.
14598 +static inline unsigned long get_segment_eip(struct pt_regs *regs,
14599 + unsigned long *eip_limit)
14601 + unsigned long eip = regs->eip;
14602 + unsigned seg = regs->xcs & 0xffff;
14603 + u32 seg_ar, seg_limit, base, *desc;
14605 + /* Unlikely, but must come before segment checks. */
14606 + if (unlikely(regs->eflags & VM_MASK)) {
14608 + *eip_limit = base + 0xffff;
14609 + return base + (eip & 0xffff);
14612 + /* The standard kernel/user address space limit. */
14613 + *eip_limit = (seg & 2) ? USER_DS.seg : KERNEL_DS.seg;
14615 + /* By far the most common cases. */
14616 + if (likely(seg == __USER_CS || seg == GET_KERNEL_CS()))
14619 + /* Check the segment exists, is within the current LDT/GDT size,
14620 + that kernel/user (ring 0..3) has the appropriate privilege,
14621 + that it's a code segment, and get the limit. */
14622 + __asm__ ("larl %3,%0; lsll %3,%1"
14623 + : "=&r" (seg_ar), "=r" (seg_limit) : "0" (0), "rm" (seg));
14624 + if ((~seg_ar & 0x9800) || eip > seg_limit) {
14626 + return 1; /* So that returned eip > *eip_limit. */
14629 + /* Get the GDT/LDT descriptor base.
14630 + When you look for races in this code remember that
14631 + LDT and other horrors are only used in user space. */
14632 + if (seg & (1<<2)) {
14633 + /* Must lock the LDT while reading it. */
14634 + down(¤t->mm->context.sem);
14635 + desc = current->mm->context.ldt;
14636 + desc = (void *)desc + (seg & ~7);
14638 + /* Must disable preemption while reading the GDT. */
14639 + desc = (u32 *)get_cpu_gdt_table(get_cpu());
14640 + desc = (void *)desc + (seg & ~7);
14643 + /* Decode the code segment base from the descriptor */
14644 + base = get_desc_base((unsigned long *)desc);
14646 + if (seg & (1<<2)) {
14647 + up(¤t->mm->context.sem);
14651 + /* Adjust EIP and segment limit, and clamp at the kernel limit.
14652 + It's legitimate for segments to wrap at 0xffffffff. */
14653 + seg_limit += base;
14654 + if (seg_limit < *eip_limit && seg_limit >= base)
14655 + *eip_limit = seg_limit;
14656 + return eip + base;
14660 + * Sometimes AMD Athlon/Opteron CPUs report invalid exceptions on prefetch.
14661 + * Check that here and ignore it.
14663 +static int __is_prefetch(struct pt_regs *regs, unsigned long addr)
14665 + unsigned long limit;
14666 + unsigned long instr = get_segment_eip (regs, &limit);
14667 + int scan_more = 1;
14668 + int prefetch = 0;
14671 + for (i = 0; scan_more && i < 15; i++) {
14672 + unsigned char opcode;
14673 + unsigned char instr_hi;
14674 + unsigned char instr_lo;
14676 + if (instr > limit)
14678 + if (__get_user(opcode, (unsigned char __user *) instr))
14681 + instr_hi = opcode & 0xf0;
14682 + instr_lo = opcode & 0x0f;
14685 + switch (instr_hi) {
14688 + /* Values 0x26,0x2E,0x36,0x3E are valid x86 prefixes. */
14689 + scan_more = ((instr_lo & 7) == 0x6);
14693 + /* 0x64 thru 0x67 are valid prefixes in all modes. */
14694 + scan_more = (instr_lo & 0xC) == 0x4;
14697 + /* 0xF0, 0xF2, and 0xF3 are valid prefixes */
14698 + scan_more = !instr_lo || (instr_lo>>1) == 1;
14701 + /* Prefetch instruction is 0x0F0D or 0x0F18 */
14703 + if (instr > limit)
14705 + if (__get_user(opcode, (unsigned char __user *) instr))
14707 + prefetch = (instr_lo == 0xF) &&
14708 + (opcode == 0x0D || opcode == 0x18);
14718 +static inline int is_prefetch(struct pt_regs *regs, unsigned long addr,
14719 + unsigned long error_code)
14721 + if (unlikely(boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
14722 + boot_cpu_data.x86 >= 6)) {
14723 + /* Catch an obscure case of prefetch inside an NX page. */
14724 + if (nx_enabled && (error_code & 16))
14726 + return __is_prefetch(regs, addr);
14731 +static noinline void force_sig_info_fault(int si_signo, int si_code,
14732 + unsigned long address, struct task_struct *tsk)
14736 + info.si_signo = si_signo;
14737 + info.si_errno = 0;
14738 + info.si_code = si_code;
14739 + info.si_addr = (void __user *)address;
14740 + force_sig_info(si_signo, &info, tsk);
14743 +fastcall void do_invalid_op(struct pt_regs *, unsigned long);
14745 +#ifdef CONFIG_X86_PAE
14746 +static void dump_fault_path(unsigned long address)
14748 + unsigned long *p, page;
14749 + unsigned long mfn;
14751 + page = read_cr3();
14752 + p = (unsigned long *)__va(page);
14753 + p += (address >> 30) * 2;
14754 + printk(KERN_ALERT "%08lx -> *pde = %08lx:%08lx\n", page, p[1], p[0]);
14755 + if (p[0] & _PAGE_PRESENT) {
14756 + mfn = (p[0] >> PAGE_SHIFT) | (p[1] << 20);
14757 + page = mfn_to_pfn(mfn) << PAGE_SHIFT;
14758 + p = (unsigned long *)__va(page);
14759 + address &= 0x3fffffff;
14760 + p += (address >> 21) * 2;
14761 + printk(KERN_ALERT "%08lx -> *pme = %08lx:%08lx\n",
14762 + page, p[1], p[0]);
14763 + mfn = (p[0] >> PAGE_SHIFT) | (p[1] << 20);
14764 +#ifdef CONFIG_HIGHPTE
14765 + if (mfn_to_pfn(mfn) >= highstart_pfn)
14768 + if (p[0] & _PAGE_PRESENT) {
14769 + page = mfn_to_pfn(mfn) << PAGE_SHIFT;
14770 + p = (unsigned long *) __va(page);
14771 + address &= 0x001fffff;
14772 + p += (address >> 12) * 2;
14773 + printk(KERN_ALERT "%08lx -> *pte = %08lx:%08lx\n",
14774 + page, p[1], p[0]);
14779 +static void dump_fault_path(unsigned long address)
14781 + unsigned long page;
14783 + page = read_cr3();
14784 + page = ((unsigned long *) __va(page))[address >> 22];
14785 + if (oops_may_print())
14786 + printk(KERN_ALERT "*pde = ma %08lx pa %08lx\n", page,
14787 + machine_to_phys(page));
14789 + * We must not directly access the pte in the highpte
14790 + * case if the page table is located in highmem.
14791 + * And lets rather not kmap-atomic the pte, just in case
14792 + * it's allocated already.
14794 +#ifdef CONFIG_HIGHPTE
14795 + if ((page >> PAGE_SHIFT) >= highstart_pfn)
14798 + if ((page & 1) && oops_may_print()) {
14799 + page &= PAGE_MASK;
14800 + address &= 0x003ff000;
14801 + page = machine_to_phys(page);
14802 + page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT];
14803 + printk(KERN_ALERT "*pte = ma %08lx pa %08lx\n", page,
14804 + machine_to_phys(page));
14809 +static int spurious_fault(struct pt_regs *regs,
14810 + unsigned long address,
14811 + unsigned long error_code)
14818 + /* Reserved-bit violation or user access to kernel space? */
14819 + if (error_code & 0x0c)
14822 + pgd = init_mm.pgd + pgd_index(address);
14823 + if (!pgd_present(*pgd))
14826 + pud = pud_offset(pgd, address);
14827 + if (!pud_present(*pud))
14830 + pmd = pmd_offset(pud, address);
14831 + if (!pmd_present(*pmd))
14834 + pte = pte_offset_kernel(pmd, address);
14835 + if (!pte_present(*pte))
14837 + if ((error_code & 0x02) && !pte_write(*pte))
14839 +#ifdef CONFIG_X86_PAE
14840 + if ((error_code & 0x10) && (__pte_val(*pte) & _PAGE_NX))
14847 +static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address)
14849 + unsigned index = pgd_index(address);
14851 + pud_t *pud, *pud_k;
14852 + pmd_t *pmd, *pmd_k;
14855 + pgd_k = init_mm.pgd + index;
14857 + if (!pgd_present(*pgd_k))
14861 + * set_pgd(pgd, *pgd_k); here would be useless on PAE
14862 + * and redundant with the set_pmd() on non-PAE. As would
14866 + pud = pud_offset(pgd, address);
14867 + pud_k = pud_offset(pgd_k, address);
14868 + if (!pud_present(*pud_k))
14871 + pmd = pmd_offset(pud, address);
14872 + pmd_k = pmd_offset(pud_k, address);
14873 + if (!pmd_present(*pmd_k))
14875 + if (!pmd_present(*pmd))
14876 +#if CONFIG_XEN_COMPAT > 0x030002
14877 + set_pmd(pmd, *pmd_k);
14880 + * When running on older Xen we must launder *pmd_k through
14881 + * pmd_val() to ensure that _PAGE_PRESENT is correctly set.
14883 + set_pmd(pmd, __pmd(pmd_val(*pmd_k)));
14886 + BUG_ON(pmd_page(*pmd) != pmd_page(*pmd_k));
14891 + * Handle a fault on the vmalloc or module mapping area
14893 + * This assumes no large pages in there.
14895 +static inline int vmalloc_fault(unsigned long address)
14897 + unsigned long pgd_paddr;
14901 + * Synchronize this task's top level page-table
14902 + * with the 'reference' page table.
14904 + * Do _not_ use "current" here. We might be inside
14905 + * an interrupt in the middle of a task switch..
14907 + pgd_paddr = read_cr3();
14908 + pmd_k = vmalloc_sync_one(__va(pgd_paddr), address);
14911 + pte_k = pte_offset_kernel(pmd_k, address);
14912 + if (!pte_present(*pte_k))
14918 + * This routine handles page faults. It determines the address,
14919 + * and the problem, and then passes it off to one of the appropriate
14923 + * bit 0 == 0 means no page found, 1 means protection fault
14924 + * bit 1 == 0 means read, 1 means write
14925 + * bit 2 == 0 means kernel, 1 means user-mode
14926 + * bit 3 == 1 means use of reserved bit detected
14927 + * bit 4 == 1 means fault was an instruction fetch
14929 +fastcall void __kprobes do_page_fault(struct pt_regs *regs,
14930 + unsigned long error_code)
14932 + struct task_struct *tsk;
14933 + struct mm_struct *mm;
14934 + struct vm_area_struct * vma;
14935 + unsigned long address;
14936 + int write, si_code;
14938 + /* get the address */
14939 + address = read_cr2();
14941 + /* Set the "privileged fault" bit to something sane. */
14942 + error_code &= ~4;
14943 + error_code |= (regs->xcs & 2) << 1;
14944 + if (regs->eflags & X86_EFLAGS_VM)
14949 + si_code = SEGV_MAPERR;
14952 + * We fault-in kernel-space virtual memory on-demand. The
14953 + * 'reference' page table is init_mm.pgd.
14955 + * NOTE! We MUST NOT take any locks for this case. We may
14956 + * be in an interrupt or a critical region, and should
14957 + * only copy the information from the master page table,
14960 + * This verifies that the fault happens in kernel space
14961 + * (error_code & 4) == 0, and that the fault was not a
14962 + * protection error (error_code & 9) == 0.
14964 + if (unlikely(address >= TASK_SIZE)) {
14966 + /* Faults in hypervisor area can never be patched up. */
14967 + if (address >= hypervisor_virt_start)
14968 + goto bad_area_nosemaphore;
14970 + if (!(error_code & 0x0000000d) && vmalloc_fault(address) >= 0)
14972 + /* Can take a spurious fault if mapping changes R/O -> R/W. */
14973 + if (spurious_fault(regs, address, error_code))
14975 + if (notify_page_fault(DIE_PAGE_FAULT, "page fault", regs, error_code, 14,
14976 + SIGSEGV) == NOTIFY_STOP)
14979 + * Don't take the mm semaphore here. If we fixup a prefetch
14980 + * fault we could otherwise deadlock.
14982 + goto bad_area_nosemaphore;
14985 + if (notify_page_fault(DIE_PAGE_FAULT, "page fault", regs, error_code, 14,
14986 + SIGSEGV) == NOTIFY_STOP)
14989 + /* It's safe to allow irq's after cr2 has been saved and the vmalloc
14990 + fault has been handled. */
14991 + if (regs->eflags & (X86_EFLAGS_IF|VM_MASK))
14992 + local_irq_enable();
14997 + * If we're in an interrupt, have no user context or are running in an
14998 + * atomic region then we must not take the fault..
15000 + if (in_atomic() || !mm)
15001 + goto bad_area_nosemaphore;
15003 + /* When running in the kernel we expect faults to occur only to
15004 + * addresses in user space. All other faults represent errors in the
15005 + * kernel and should generate an OOPS. Unfortunatly, in the case of an
15006 + * erroneous fault occurring in a code path which already holds mmap_sem
15007 + * we will deadlock attempting to validate the fault against the
15008 + * address space. Luckily the kernel only validly references user
15009 + * space from well defined areas of code, which are listed in the
15010 + * exceptions table.
15012 + * As the vast majority of faults will be valid we will only perform
15013 + * the source reference check when there is a possibilty of a deadlock.
15014 + * Attempt to lock the address space, if we cannot we then validate the
15015 + * source. If this is invalid we can skip the address space check,
15016 + * thus avoiding the deadlock.
15018 + if (!down_read_trylock(&mm->mmap_sem)) {
15019 + if ((error_code & 4) == 0 &&
15020 + !search_exception_tables(regs->eip))
15021 + goto bad_area_nosemaphore;
15022 + down_read(&mm->mmap_sem);
15025 + vma = find_vma(mm, address);
15028 + if (vma->vm_start <= address)
15030 + if (!(vma->vm_flags & VM_GROWSDOWN))
15032 + if (error_code & 4) {
15034 + * Accessing the stack below %esp is always a bug.
15035 + * The large cushion allows instructions like enter
15036 + * and pusha to work. ("enter $65535,$31" pushes
15037 + * 32 pointers and then decrements %esp by 65535.)
15039 + if (address + 65536 + 32 * sizeof(unsigned long) < regs->esp)
15042 + if (expand_stack(vma, address))
15045 + * Ok, we have a good vm_area for this memory access, so
15046 + * we can handle it..
15049 + si_code = SEGV_ACCERR;
15051 + switch (error_code & 3) {
15052 + default: /* 3: write, present */
15053 +#ifdef TEST_VERIFY_AREA
15054 + if (regs->cs == GET_KERNEL_CS())
15055 + printk("WP fault at %08lx\n", regs->eip);
15057 + /* fall through */
15058 + case 2: /* write, not present */
15059 + if (!(vma->vm_flags & VM_WRITE))
15063 + case 1: /* read, present */
15065 + case 0: /* read, not present */
15066 + if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
15072 + * If for any reason at all we couldn't handle the fault,
15073 + * make sure we exit gracefully rather than endlessly redo
15076 + switch (handle_mm_fault(mm, vma, address, write)) {
15077 + case VM_FAULT_MINOR:
15080 + case VM_FAULT_MAJOR:
15083 + case VM_FAULT_SIGBUS:
15085 + case VM_FAULT_OOM:
15086 + goto out_of_memory;
15092 + * Did it hit the DOS screen memory VA from vm86 mode?
15094 + if (regs->eflags & VM_MASK) {
15095 + unsigned long bit = (address - 0xA0000) >> PAGE_SHIFT;
15097 + tsk->thread.screen_bitmap |= 1 << bit;
15099 + up_read(&mm->mmap_sem);
15103 + * Something tried to access memory that isn't in our memory map..
15104 + * Fix it, but check if it's kernel or user first..
15107 + up_read(&mm->mmap_sem);
15109 +bad_area_nosemaphore:
15110 + /* User mode accesses just cause a SIGSEGV */
15111 + if (error_code & 4) {
15113 + * Valid to do another page fault here because this one came
15114 + * from user space.
15116 + if (is_prefetch(regs, address, error_code))
15119 + tsk->thread.cr2 = address;
15120 + /* Kernel addresses are always protection faults */
15121 + tsk->thread.error_code = error_code | (address >= TASK_SIZE);
15122 + tsk->thread.trap_no = 14;
15123 + force_sig_info_fault(SIGSEGV, si_code, address, tsk);
15127 +#ifdef CONFIG_X86_F00F_BUG
15129 + * Pentium F0 0F C7 C8 bug workaround.
15131 + if (boot_cpu_data.f00f_bug) {
15132 + unsigned long nr;
15134 + nr = (address - idt_descr.address) >> 3;
15137 + do_invalid_op(regs, 0);
15144 + /* Are we prepared to handle this kernel fault? */
15145 + if (fixup_exception(regs))
15149 + * Valid to do another page fault here, because if this fault
15150 + * had been triggered by is_prefetch fixup_exception would have
15153 + if (is_prefetch(regs, address, error_code))
15157 + * Oops. The kernel tried to access some bad page. We'll have to
15158 + * terminate things with extreme prejudice.
15161 + bust_spinlocks(1);
15163 + if (oops_may_print()) {
15164 + #ifdef CONFIG_X86_PAE
15165 + if (error_code & 16) {
15166 + pte_t *pte = lookup_address(address);
15168 + if (pte && pte_present(*pte) && !pte_exec_kernel(*pte))
15169 + printk(KERN_CRIT "kernel tried to execute "
15170 + "NX-protected page - exploit attempt? "
15171 + "(uid: %d)\n", current->uid);
15174 + if (address < PAGE_SIZE)
15175 + printk(KERN_ALERT "BUG: unable to handle kernel NULL "
15176 + "pointer dereference");
15178 + printk(KERN_ALERT "BUG: unable to handle kernel paging"
15180 + printk(" at virtual address %08lx\n",address);
15181 + printk(KERN_ALERT " printing eip:\n");
15182 + printk("%08lx\n", regs->eip);
15184 + dump_fault_path(address);
15185 + tsk->thread.cr2 = address;
15186 + tsk->thread.trap_no = 14;
15187 + tsk->thread.error_code = error_code;
15188 + die("Oops", regs, error_code);
15189 + bust_spinlocks(0);
15190 + do_exit(SIGKILL);
15193 + * We ran out of memory, or some other thing happened to us that made
15194 + * us unable to handle the page fault gracefully.
15197 + up_read(&mm->mmap_sem);
15198 + if (tsk->pid == 1) {
15200 + down_read(&mm->mmap_sem);
15203 + printk("VM: killing process %s\n", tsk->comm);
15204 + if (error_code & 4)
15205 + do_exit(SIGKILL);
15209 + up_read(&mm->mmap_sem);
15211 + /* Kernel mode? Handle exceptions or die */
15212 + if (!(error_code & 4))
15215 + /* User space => ok to do another page fault */
15216 + if (is_prefetch(regs, address, error_code))
15219 + tsk->thread.cr2 = address;
15220 + tsk->thread.error_code = error_code;
15221 + tsk->thread.trap_no = 14;
15222 + force_sig_info_fault(SIGBUS, BUS_ADRERR, address, tsk);
15225 +#if !HAVE_SHARED_KERNEL_PMD
15226 +void vmalloc_sync_all(void)
15229 + * Note that races in the updates of insync and start aren't
15230 + * problematic: insync can only get set bits added, and updates to
15231 + * start are only improving performance (without affecting correctness
15233 + * XEN: To work on PAE, we need to iterate over PMDs rather than PGDs.
15234 + * This change works just fine with 2-level paging too.
15236 +#define sync_index(a) ((a) >> PMD_SHIFT)
15237 + static DECLARE_BITMAP(insync, PTRS_PER_PGD*PTRS_PER_PMD);
15238 + static unsigned long start = TASK_SIZE;
15239 + unsigned long address;
15241 + BUILD_BUG_ON(TASK_SIZE & ~PGDIR_MASK);
15242 + for (address = start;
15243 + address >= TASK_SIZE && address < hypervisor_virt_start;
15244 + address += 1UL << PMD_SHIFT) {
15245 + if (!test_bit(sync_index(address), insync)) {
15246 + unsigned long flags;
15247 + struct page *page;
15249 + spin_lock_irqsave(&pgd_lock, flags);
15250 + /* XEN: failure path assumes non-empty pgd_list. */
15251 + if (unlikely(!pgd_list)) {
15252 + spin_unlock_irqrestore(&pgd_lock, flags);
15255 + for (page = pgd_list; page; page =
15256 + (struct page *)page->index)
15257 + if (!vmalloc_sync_one(page_address(page),
15259 + BUG_ON(page != pgd_list);
15262 + spin_unlock_irqrestore(&pgd_lock, flags);
15264 + set_bit(sync_index(address), insync);
15266 + if (address == start && test_bit(sync_index(address), insync))
15267 + start = address + (1UL << PMD_SHIFT);
15271 Index: head-2008-11-25/arch/x86/mm/highmem_32-xen.c
15272 ===================================================================
15273 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
15274 +++ head-2008-11-25/arch/x86/mm/highmem_32-xen.c 2008-10-29 09:55:56.000000000 +0100
15276 +#include <linux/highmem.h>
15277 +#include <linux/module.h>
15279 +void *kmap(struct page *page)
15282 + if (!PageHighMem(page))
15283 + return page_address(page);
15284 + return kmap_high(page);
15287 +void kunmap(struct page *page)
15289 + if (in_interrupt())
15291 + if (!PageHighMem(page))
15293 + kunmap_high(page);
15297 + * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because
15298 + * no global lock is needed and because the kmap code must perform a global TLB
15299 + * invalidation when the kmap pool wraps.
15301 + * However when holding an atomic kmap is is not legal to sleep, so atomic
15302 + * kmaps are appropriate for short, tight code paths only.
15304 +static void *__kmap_atomic(struct page *page, enum km_type type, pgprot_t prot)
15306 + enum fixed_addresses idx;
15307 + unsigned long vaddr;
15309 + /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
15310 + inc_preempt_count();
15311 + if (!PageHighMem(page))
15312 + return page_address(page);
15314 + idx = type + KM_TYPE_NR*smp_processor_id();
15315 + vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
15316 +#ifdef CONFIG_DEBUG_HIGHMEM
15317 + if (!pte_none(*(kmap_pte-idx)))
15320 + set_pte_at_sync(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
15322 + return (void*) vaddr;
15325 +void *kmap_atomic(struct page *page, enum km_type type)
15327 + return __kmap_atomic(page, type, kmap_prot);
15330 +/* Same as kmap_atomic but with PAGE_KERNEL_RO page protection. */
15331 +void *kmap_atomic_pte(struct page *page, enum km_type type)
15333 + return __kmap_atomic(page, type,
15334 + test_bit(PG_pinned, &page->flags)
15335 + ? PAGE_KERNEL_RO : kmap_prot);
15338 +void kunmap_atomic(void *kvaddr, enum km_type type)
15340 +#if defined(CONFIG_DEBUG_HIGHMEM) || defined(CONFIG_XEN)
15341 + unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
15342 + enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
15344 + if (vaddr < FIXADDR_START) { // FIXME
15345 + dec_preempt_count();
15346 + preempt_check_resched();
15351 +#if defined(CONFIG_DEBUG_HIGHMEM)
15352 + if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx))
15356 + * force other mappings to Oops if they'll try to access
15357 + * this pte without first remap it
15359 + pte_clear(&init_mm, vaddr, kmap_pte-idx);
15360 + __flush_tlb_one(vaddr);
15361 +#elif defined(CONFIG_XEN)
15363 + * We must ensure there are no dangling pagetable references when
15364 + * returning memory to Xen (decrease_reservation).
15365 + * XXX TODO: We could make this faster by only zapping when
15366 + * kmap_flush_unused is called but that is trickier and more invasive.
15368 + pte_clear(&init_mm, vaddr, kmap_pte-idx);
15371 + dec_preempt_count();
15372 + preempt_check_resched();
15375 +/* This is the same as kmap_atomic() but can map memory that doesn't
15376 + * have a struct page associated with it.
15378 +void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
15380 + enum fixed_addresses idx;
15381 + unsigned long vaddr;
15383 + inc_preempt_count();
15385 + idx = type + KM_TYPE_NR*smp_processor_id();
15386 + vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
15387 + set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot));
15388 + __flush_tlb_one(vaddr);
15390 + return (void*) vaddr;
15393 +struct page *kmap_atomic_to_page(void *ptr)
15395 + unsigned long idx, vaddr = (unsigned long)ptr;
15398 + if (vaddr < FIXADDR_START)
15399 + return virt_to_page(ptr);
15401 + idx = virt_to_fix(vaddr);
15402 + pte = kmap_pte - (idx - FIX_KMAP_BEGIN);
15403 + return pte_page(*pte);
15406 +void clear_highpage(struct page *page)
15410 + if (likely(xen_feature(XENFEAT_highmem_assist))
15411 + && PageHighMem(page)) {
15412 + struct mmuext_op meo;
15414 + meo.cmd = MMUEXT_CLEAR_PAGE;
15415 + meo.arg1.mfn = pfn_to_mfn(page_to_pfn(page));
15416 + if (HYPERVISOR_mmuext_op(&meo, 1, NULL, DOMID_SELF) == 0)
15420 + kaddr = kmap_atomic(page, KM_USER0);
15421 + clear_page(kaddr);
15422 + kunmap_atomic(kaddr, KM_USER0);
15425 +void copy_highpage(struct page *to, struct page *from)
15427 + void *vfrom, *vto;
15429 + if (likely(xen_feature(XENFEAT_highmem_assist))
15430 + && (PageHighMem(from) || PageHighMem(to))) {
15431 + unsigned long from_pfn = page_to_pfn(from);
15432 + unsigned long to_pfn = page_to_pfn(to);
15433 + struct mmuext_op meo;
15435 + meo.cmd = MMUEXT_COPY_PAGE;
15436 + meo.arg1.mfn = pfn_to_mfn(to_pfn);
15437 + meo.arg2.src_mfn = pfn_to_mfn(from_pfn);
15438 + if (mfn_to_pfn(meo.arg2.src_mfn) == from_pfn
15439 + && mfn_to_pfn(meo.arg1.mfn) == to_pfn
15440 + && HYPERVISOR_mmuext_op(&meo, 1, NULL, DOMID_SELF) == 0)
15444 + vfrom = kmap_atomic(from, KM_USER0);
15445 + vto = kmap_atomic(to, KM_USER1);
15446 + copy_page(vto, vfrom);
15447 + kunmap_atomic(vfrom, KM_USER0);
15448 + kunmap_atomic(vto, KM_USER1);
15451 +EXPORT_SYMBOL(kmap);
15452 +EXPORT_SYMBOL(kunmap);
15453 +EXPORT_SYMBOL(kmap_atomic);
15454 +EXPORT_SYMBOL(kmap_atomic_pte);
15455 +EXPORT_SYMBOL(kunmap_atomic);
15456 +EXPORT_SYMBOL(kmap_atomic_to_page);
15457 +EXPORT_SYMBOL(clear_highpage);
15458 +EXPORT_SYMBOL(copy_highpage);
15459 Index: head-2008-11-25/arch/x86/mm/hypervisor.c
15460 ===================================================================
15461 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
15462 +++ head-2008-11-25/arch/x86/mm/hypervisor.c 2008-10-29 09:55:56.000000000 +0100
15464 +/******************************************************************************
15465 + * mm/hypervisor.c
15467 + * Update page tables via the hypervisor.
15469 + * Copyright (c) 2002-2004, K A Fraser
15471 + * This program is free software; you can redistribute it and/or
15472 + * modify it under the terms of the GNU General Public License version 2
15473 + * as published by the Free Software Foundation; or, when distributed
15474 + * separately from the Linux kernel or incorporated into other
15475 + * software packages, subject to the following license:
15477 + * Permission is hereby granted, free of charge, to any person obtaining a copy
15478 + * of this source file (the "Software"), to deal in the Software without
15479 + * restriction, including without limitation the rights to use, copy, modify,
15480 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
15481 + * and to permit persons to whom the Software is furnished to do so, subject to
15482 + * the following conditions:
15484 + * The above copyright notice and this permission notice shall be included in
15485 + * all copies or substantial portions of the Software.
15487 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15488 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15489 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
15490 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
15491 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
15492 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
15493 + * IN THE SOFTWARE.
15496 +#include <linux/sched.h>
15497 +#include <linux/mm.h>
15498 +#include <linux/vmalloc.h>
15499 +#include <asm/page.h>
15500 +#include <asm/pgtable.h>
15501 +#include <asm/hypervisor.h>
15502 +#include <xen/balloon.h>
15503 +#include <xen/features.h>
15504 +#include <xen/interface/memory.h>
15505 +#include <linux/module.h>
15506 +#include <linux/percpu.h>
15507 +#include <asm/tlbflush.h>
15508 +#include <linux/highmem.h>
15510 +void xen_l1_entry_update(pte_t *ptr, pte_t val)
15513 +#ifdef CONFIG_HIGHPTE
15514 + u.ptr = ((unsigned long)ptr >= (unsigned long)high_memory) ?
15515 + arbitrary_virt_to_machine(ptr) : virt_to_machine(ptr);
15517 + u.ptr = virt_to_machine(ptr);
15519 + u.val = __pte_val(val);
15520 + BUG_ON(HYPERVISOR_mmu_update(&u, 1, NULL, DOMID_SELF) < 0);
15522 +EXPORT_SYMBOL_GPL(xen_l1_entry_update);
15524 +void xen_l2_entry_update(pmd_t *ptr, pmd_t val)
15527 + u.ptr = virt_to_machine(ptr);
15528 + u.val = __pmd_val(val);
15529 + BUG_ON(HYPERVISOR_mmu_update(&u, 1, NULL, DOMID_SELF) < 0);
15532 +#if defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64)
15533 +void xen_l3_entry_update(pud_t *ptr, pud_t val)
15536 + u.ptr = virt_to_machine(ptr);
15537 + u.val = __pud_val(val);
15538 + BUG_ON(HYPERVISOR_mmu_update(&u, 1, NULL, DOMID_SELF) < 0);
15542 +#ifdef CONFIG_X86_64
15543 +void xen_l4_entry_update(pgd_t *ptr, pgd_t val)
15546 + u.ptr = virt_to_machine(ptr);
15547 + u.val = __pgd_val(val);
15548 + BUG_ON(HYPERVISOR_mmu_update(&u, 1, NULL, DOMID_SELF) < 0);
15550 +#endif /* CONFIG_X86_64 */
15552 +void xen_pt_switch(unsigned long ptr)
15554 + struct mmuext_op op;
15555 + op.cmd = MMUEXT_NEW_BASEPTR;
15556 + op.arg1.mfn = pfn_to_mfn(ptr >> PAGE_SHIFT);
15557 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15560 +void xen_new_user_pt(unsigned long ptr)
15562 + struct mmuext_op op;
15563 + op.cmd = MMUEXT_NEW_USER_BASEPTR;
15564 + op.arg1.mfn = pfn_to_mfn(ptr >> PAGE_SHIFT);
15565 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15568 +void xen_tlb_flush(void)
15570 + struct mmuext_op op;
15571 + op.cmd = MMUEXT_TLB_FLUSH_LOCAL;
15572 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15574 +EXPORT_SYMBOL(xen_tlb_flush);
15576 +void xen_invlpg(unsigned long ptr)
15578 + struct mmuext_op op;
15579 + op.cmd = MMUEXT_INVLPG_LOCAL;
15580 + op.arg1.linear_addr = ptr & PAGE_MASK;
15581 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15583 +EXPORT_SYMBOL(xen_invlpg);
15587 +void xen_tlb_flush_all(void)
15589 + struct mmuext_op op;
15590 + op.cmd = MMUEXT_TLB_FLUSH_ALL;
15591 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15594 +void xen_tlb_flush_mask(cpumask_t *mask)
15596 + struct mmuext_op op;
15597 + if ( cpus_empty(*mask) )
15599 + op.cmd = MMUEXT_TLB_FLUSH_MULTI;
15600 + set_xen_guest_handle(op.arg2.vcpumask, mask->bits);
15601 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15604 +void xen_invlpg_all(unsigned long ptr)
15606 + struct mmuext_op op;
15607 + op.cmd = MMUEXT_INVLPG_ALL;
15608 + op.arg1.linear_addr = ptr & PAGE_MASK;
15609 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15612 +void xen_invlpg_mask(cpumask_t *mask, unsigned long ptr)
15614 + struct mmuext_op op;
15615 + if ( cpus_empty(*mask) )
15617 + op.cmd = MMUEXT_INVLPG_MULTI;
15618 + op.arg1.linear_addr = ptr & PAGE_MASK;
15619 + set_xen_guest_handle(op.arg2.vcpumask, mask->bits);
15620 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15623 +#endif /* CONFIG_SMP */
15625 +void xen_pgd_pin(unsigned long ptr)
15627 + struct mmuext_op op;
15628 +#ifdef CONFIG_X86_64
15629 + op.cmd = MMUEXT_PIN_L4_TABLE;
15630 +#elif defined(CONFIG_X86_PAE)
15631 + op.cmd = MMUEXT_PIN_L3_TABLE;
15633 + op.cmd = MMUEXT_PIN_L2_TABLE;
15635 + op.arg1.mfn = pfn_to_mfn(ptr >> PAGE_SHIFT);
15636 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15639 +void xen_pgd_unpin(unsigned long ptr)
15641 + struct mmuext_op op;
15642 + op.cmd = MMUEXT_UNPIN_TABLE;
15643 + op.arg1.mfn = pfn_to_mfn(ptr >> PAGE_SHIFT);
15644 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15647 +void xen_set_ldt(const void *ptr, unsigned int ents)
15649 + struct mmuext_op op;
15650 + op.cmd = MMUEXT_SET_LDT;
15651 + op.arg1.linear_addr = (unsigned long)ptr;
15652 + op.arg2.nr_ents = ents;
15653 + BUG_ON(HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0);
15656 +/* Protected by balloon_lock. */
15657 +#define MAX_CONTIG_ORDER 9 /* 2MB */
15658 +static unsigned long discontig_frames[1<<MAX_CONTIG_ORDER];
15659 +static unsigned long limited_frames[1<<MAX_CONTIG_ORDER];
15660 +static multicall_entry_t cr_mcl[1<<MAX_CONTIG_ORDER];
15662 +/* Ensure multi-page extents are contiguous in machine memory. */
15663 +int xen_create_contiguous_region(
15664 + unsigned long vstart, unsigned int order, unsigned int address_bits)
15666 + unsigned long *in_frames = discontig_frames, out_frame;
15667 + unsigned long frame, flags;
15670 + struct xen_memory_exchange exchange = {
15672 + .nr_extents = 1UL << order,
15673 + .extent_order = 0,
15674 + .domid = DOMID_SELF
15678 + .extent_order = order,
15679 + .address_bits = address_bits,
15680 + .domid = DOMID_SELF
15685 + * Currently an auto-translated guest will not perform I/O, nor will
15686 + * it require PAE page directories below 4GB. Therefore any calls to
15687 + * this function are redundant and can be ignored.
15689 + if (xen_feature(XENFEAT_auto_translated_physmap))
15692 + if (unlikely(order > MAX_CONTIG_ORDER))
15695 + set_xen_guest_handle(exchange.in.extent_start, in_frames);
15696 + set_xen_guest_handle(exchange.out.extent_start, &out_frame);
15698 + scrub_pages((void *)vstart, 1 << order);
15700 + balloon_lock(flags);
15702 + /* 1. Zap current PTEs, remembering MFNs. */
15703 + for (i = 0; i < (1U<<order); i++) {
15704 + in_frames[i] = pfn_to_mfn((__pa(vstart) >> PAGE_SHIFT) + i);
15705 + MULTI_update_va_mapping(cr_mcl + i, vstart + (i*PAGE_SIZE),
15707 + set_phys_to_machine((__pa(vstart)>>PAGE_SHIFT)+i,
15708 + INVALID_P2M_ENTRY);
15710 + if (HYPERVISOR_multicall_check(cr_mcl, i, NULL))
15713 + /* 2. Get a new contiguous memory extent. */
15714 + out_frame = __pa(vstart) >> PAGE_SHIFT;
15715 + rc = HYPERVISOR_memory_op(XENMEM_exchange, &exchange);
15716 + success = (exchange.nr_exchanged == (1UL << order));
15717 + BUG_ON(!success && ((exchange.nr_exchanged != 0) || (rc == 0)));
15718 + BUG_ON(success && (rc != 0));
15719 +#if CONFIG_XEN_COMPAT <= 0x030002
15720 + if (unlikely(rc == -ENOSYS)) {
15721 + /* Compatibility when XENMEM_exchange is unsupported. */
15722 + if (HYPERVISOR_memory_op(XENMEM_decrease_reservation,
15723 + &exchange.in) != (1UL << order))
15725 + success = (HYPERVISOR_memory_op(XENMEM_populate_physmap,
15726 + &exchange.out) == 1);
15728 + /* Couldn't get special memory: fall back to normal. */
15729 + for (i = 0; i < (1U<<order); i++)
15730 + in_frames[i] = (__pa(vstart)>>PAGE_SHIFT) + i;
15731 + if (HYPERVISOR_memory_op(XENMEM_populate_physmap,
15732 + &exchange.in) != (1UL<<order))
15738 + /* 3. Map the new extent in place of old pages. */
15739 + for (i = 0; i < (1U<<order); i++) {
15740 + frame = success ? (out_frame + i) : in_frames[i];
15741 + MULTI_update_va_mapping(cr_mcl + i, vstart + (i*PAGE_SIZE),
15742 + pfn_pte_ma(frame, PAGE_KERNEL), 0);
15743 + set_phys_to_machine((__pa(vstart)>>PAGE_SHIFT)+i, frame);
15746 + cr_mcl[i - 1].args[MULTI_UVMFLAGS_INDEX] = order
15747 + ? UVMF_TLB_FLUSH|UVMF_ALL
15748 + : UVMF_INVLPG|UVMF_ALL;
15749 + if (HYPERVISOR_multicall_check(cr_mcl, i, NULL))
15752 + balloon_unlock(flags);
15754 + return success ? 0 : -ENOMEM;
15756 +EXPORT_SYMBOL_GPL(xen_create_contiguous_region);
15758 +void xen_destroy_contiguous_region(unsigned long vstart, unsigned int order)
15760 + unsigned long *out_frames = discontig_frames, in_frame;
15761 + unsigned long frame, flags;
15764 + struct xen_memory_exchange exchange = {
15767 + .extent_order = order,
15768 + .domid = DOMID_SELF
15771 + .nr_extents = 1UL << order,
15772 + .extent_order = 0,
15773 + .domid = DOMID_SELF
15777 + if (xen_feature(XENFEAT_auto_translated_physmap))
15780 + if (unlikely(order > MAX_CONTIG_ORDER))
15783 + set_xen_guest_handle(exchange.in.extent_start, &in_frame);
15784 + set_xen_guest_handle(exchange.out.extent_start, out_frames);
15786 + scrub_pages((void *)vstart, 1 << order);
15788 + balloon_lock(flags);
15790 + /* 1. Find start MFN of contiguous extent. */
15791 + in_frame = pfn_to_mfn(__pa(vstart) >> PAGE_SHIFT);
15793 + /* 2. Zap current PTEs. */
15794 + for (i = 0; i < (1U<<order); i++) {
15795 + MULTI_update_va_mapping(cr_mcl + i, vstart + (i*PAGE_SIZE),
15797 + set_phys_to_machine((__pa(vstart)>>PAGE_SHIFT)+i,
15798 + INVALID_P2M_ENTRY);
15799 + out_frames[i] = (__pa(vstart) >> PAGE_SHIFT) + i;
15801 + if (HYPERVISOR_multicall_check(cr_mcl, i, NULL))
15804 + /* 3. Do the exchange for non-contiguous MFNs. */
15805 + rc = HYPERVISOR_memory_op(XENMEM_exchange, &exchange);
15806 + success = (exchange.nr_exchanged == 1);
15807 + BUG_ON(!success && ((exchange.nr_exchanged != 0) || (rc == 0)));
15808 + BUG_ON(success && (rc != 0));
15809 +#if CONFIG_XEN_COMPAT <= 0x030002
15810 + if (unlikely(rc == -ENOSYS)) {
15811 + /* Compatibility when XENMEM_exchange is unsupported. */
15812 + if (HYPERVISOR_memory_op(XENMEM_decrease_reservation,
15813 + &exchange.in) != 1)
15815 + if (HYPERVISOR_memory_op(XENMEM_populate_physmap,
15816 + &exchange.out) != (1UL << order))
15822 + /* 4. Map new pages in place of old pages. */
15823 + for (i = 0; i < (1U<<order); i++) {
15824 + frame = success ? out_frames[i] : (in_frame + i);
15825 + MULTI_update_va_mapping(cr_mcl + i, vstart + (i*PAGE_SIZE),
15826 + pfn_pte_ma(frame, PAGE_KERNEL), 0);
15827 + set_phys_to_machine((__pa(vstart)>>PAGE_SHIFT)+i, frame);
15830 + cr_mcl[i - 1].args[MULTI_UVMFLAGS_INDEX] = order
15831 + ? UVMF_TLB_FLUSH|UVMF_ALL
15832 + : UVMF_INVLPG|UVMF_ALL;
15833 + if (HYPERVISOR_multicall_check(cr_mcl, i, NULL))
15836 + balloon_unlock(flags);
15838 +EXPORT_SYMBOL_GPL(xen_destroy_contiguous_region);
15840 +int xen_limit_pages_to_max_mfn(
15841 + struct page *pages, unsigned int order, unsigned int address_bits)
15843 + unsigned long flags, frame;
15844 + unsigned long *in_frames = discontig_frames, *out_frames = limited_frames;
15845 + struct page *page;
15846 + unsigned int i, n, nr_mcl;
15848 + DECLARE_BITMAP(limit_map, 1 << MAX_CONTIG_ORDER);
15850 + struct xen_memory_exchange exchange = {
15852 + .extent_order = 0,
15853 + .domid = DOMID_SELF
15856 + .extent_order = 0,
15857 + .address_bits = address_bits,
15858 + .domid = DOMID_SELF
15862 + if (xen_feature(XENFEAT_auto_translated_physmap))
15865 + if (unlikely(order > MAX_CONTIG_ORDER))
15868 + bitmap_zero(limit_map, 1U << order);
15869 + set_xen_guest_handle(exchange.in.extent_start, in_frames);
15870 + set_xen_guest_handle(exchange.out.extent_start, out_frames);
15872 + /* 0. Scrub the pages. */
15873 + for (i = 0, n = 0; i < 1U<<order ; i++) {
15874 + page = &pages[i];
15875 + if (!(pfn_to_mfn(page_to_pfn(page)) >> (address_bits - PAGE_SHIFT)))
15877 + __set_bit(i, limit_map);
15879 + if (!PageHighMem(page))
15880 + scrub_pages(page_address(page), 1);
15881 +#ifdef CONFIG_XEN_SCRUB_PAGES
15883 + scrub_pages(kmap(page), 1);
15889 + if (bitmap_empty(limit_map, 1U << order))
15893 + kmap_flush_unused();
15895 + balloon_lock(flags);
15897 + /* 1. Zap current PTEs (if any), remembering MFNs. */
15898 + for (i = 0, n = 0, nr_mcl = 0; i < (1U<<order); i++) {
15899 + if(!test_bit(i, limit_map))
15901 + page = &pages[i];
15903 + out_frames[n] = page_to_pfn(page);
15904 + in_frames[n] = pfn_to_mfn(out_frames[n]);
15906 + if (!PageHighMem(page))
15907 + MULTI_update_va_mapping(cr_mcl + nr_mcl++,
15908 + (unsigned long)page_address(page),
15911 + set_phys_to_machine(out_frames[n], INVALID_P2M_ENTRY);
15914 + if (nr_mcl && HYPERVISOR_multicall_check(cr_mcl, nr_mcl, NULL))
15917 + /* 2. Get new memory below the required limit. */
15918 + exchange.in.nr_extents = n;
15919 + exchange.out.nr_extents = n;
15920 + rc = HYPERVISOR_memory_op(XENMEM_exchange, &exchange);
15921 + success = (exchange.nr_exchanged == n);
15922 + BUG_ON(!success && ((exchange.nr_exchanged != 0) || (rc == 0)));
15923 + BUG_ON(success && (rc != 0));
15924 +#if CONFIG_XEN_COMPAT <= 0x030002
15925 + if (unlikely(rc == -ENOSYS)) {
15926 + /* Compatibility when XENMEM_exchange is unsupported. */
15927 + if (HYPERVISOR_memory_op(XENMEM_decrease_reservation,
15928 + &exchange.in) != n)
15930 + if (HYPERVISOR_memory_op(XENMEM_populate_physmap,
15931 + &exchange.out) != n)
15937 + /* 3. Map the new pages in place of old pages. */
15938 + for (i = 0, n = 0, nr_mcl = 0; i < (1U<<order); i++) {
15939 + if(!test_bit(i, limit_map))
15941 + page = &pages[i];
15943 + frame = success ? out_frames[n] : in_frames[n];
15945 + if (!PageHighMem(page))
15946 + MULTI_update_va_mapping(cr_mcl + nr_mcl++,
15947 + (unsigned long)page_address(page),
15948 + pfn_pte_ma(frame, PAGE_KERNEL), 0);
15950 + set_phys_to_machine(page_to_pfn(page), frame);
15954 + cr_mcl[nr_mcl - 1].args[MULTI_UVMFLAGS_INDEX] = order
15955 + ? UVMF_TLB_FLUSH|UVMF_ALL
15956 + : UVMF_INVLPG|UVMF_ALL;
15957 + if (HYPERVISOR_multicall_check(cr_mcl, nr_mcl, NULL))
15961 + balloon_unlock(flags);
15963 + return success ? 0 : -ENOMEM;
15965 +EXPORT_SYMBOL_GPL(xen_limit_pages_to_max_mfn);
15968 +int write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 entry_b)
15970 + __u32 *lp = (__u32 *)((char *)ldt + entry * 8);
15971 + maddr_t mach_lp = arbitrary_virt_to_machine(lp);
15972 + return HYPERVISOR_update_descriptor(
15973 + mach_lp, (u64)entry_a | ((u64)entry_b<<32));
15977 +#define MAX_BATCHED_FULL_PTES 32
15979 +int xen_change_pte_range(struct mm_struct *mm, pmd_t *pmd,
15980 + unsigned long addr, unsigned long end, pgprot_t newprot)
15982 + int rc = 0, i = 0;
15983 + mmu_update_t u[MAX_BATCHED_FULL_PTES];
15987 + if (!xen_feature(XENFEAT_mmu_pt_update_preserve_ad))
15990 + pte = pte_offset_map_lock(mm, pmd, addr, &ptl);
15992 + if (pte_present(*pte)) {
15993 + u[i].ptr = (__pmd_val(*pmd) & PHYSICAL_PAGE_MASK)
15994 + | ((unsigned long)pte & ~PAGE_MASK)
15995 + | MMU_PT_UPDATE_PRESERVE_AD;
15996 + u[i].val = __pte_val(pte_modify(*pte, newprot));
15997 + if (++i == MAX_BATCHED_FULL_PTES) {
15998 + if ((rc = HYPERVISOR_mmu_update(
15999 + &u[0], i, NULL, DOMID_SELF)) != 0)
16004 + } while (pte++, addr += PAGE_SIZE, addr != end);
16006 + rc = HYPERVISOR_mmu_update( &u[0], i, NULL, DOMID_SELF);
16007 + pte_unmap_unlock(pte - 1, ptl);
16008 + BUG_ON(rc && rc != -ENOSYS);
16011 Index: head-2008-11-25/arch/x86/mm/init_32-xen.c
16012 ===================================================================
16013 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
16014 +++ head-2008-11-25/arch/x86/mm/init_32-xen.c 2008-10-29 09:55:56.000000000 +0100
16017 + * linux/arch/i386/mm/init.c
16019 + * Copyright (C) 1995 Linus Torvalds
16021 + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
16024 +#include <linux/module.h>
16025 +#include <linux/signal.h>
16026 +#include <linux/sched.h>
16027 +#include <linux/kernel.h>
16028 +#include <linux/errno.h>
16029 +#include <linux/string.h>
16030 +#include <linux/types.h>
16031 +#include <linux/ptrace.h>
16032 +#include <linux/mman.h>
16033 +#include <linux/mm.h>
16034 +#include <linux/hugetlb.h>
16035 +#include <linux/swap.h>
16036 +#include <linux/smp.h>
16037 +#include <linux/init.h>
16038 +#include <linux/highmem.h>
16039 +#include <linux/pagemap.h>
16040 +#include <linux/poison.h>
16041 +#include <linux/bootmem.h>
16042 +#include <linux/slab.h>
16043 +#include <linux/proc_fs.h>
16044 +#include <linux/efi.h>
16045 +#include <linux/memory_hotplug.h>
16046 +#include <linux/initrd.h>
16047 +#include <linux/cpumask.h>
16048 +#include <linux/dma-mapping.h>
16049 +#include <linux/scatterlist.h>
16051 +#include <asm/processor.h>
16052 +#include <asm/system.h>
16053 +#include <asm/uaccess.h>
16054 +#include <asm/pgtable.h>
16055 +#include <asm/dma.h>
16056 +#include <asm/fixmap.h>
16057 +#include <asm/e820.h>
16058 +#include <asm/apic.h>
16059 +#include <asm/tlb.h>
16060 +#include <asm/tlbflush.h>
16061 +#include <asm/sections.h>
16062 +#include <asm/hypervisor.h>
16063 +#include <asm/swiotlb.h>
16065 +unsigned int __VMALLOC_RESERVE = 128 << 20;
16067 +DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
16068 +unsigned long highstart_pfn, highend_pfn;
16070 +static int noinline do_test_wp_bit(void);
16073 + * Creates a middle page table and puts a pointer to it in the
16074 + * given global directory entry. This only returns the gd entry
16075 + * in non-PAE compilation mode, since the middle layer is folded.
16077 +static pmd_t * __init one_md_table_init(pgd_t *pgd)
16080 + pmd_t *pmd_table;
16082 +#ifdef CONFIG_X86_PAE
16083 + pmd_table = (pmd_t *) alloc_bootmem_low_pages(PAGE_SIZE);
16084 + make_lowmem_page_readonly(pmd_table, XENFEAT_writable_page_tables);
16085 + set_pgd(pgd, __pgd(__pa(pmd_table) | _PAGE_PRESENT));
16086 + pud = pud_offset(pgd, 0);
16087 + if (pmd_table != pmd_offset(pud, 0))
16090 + pud = pud_offset(pgd, 0);
16091 + pmd_table = pmd_offset(pud, 0);
16094 + return pmd_table;
16098 + * Create a page table and place a pointer to it in a middle page
16099 + * directory entry.
16101 +static pte_t * __init one_page_table_init(pmd_t *pmd)
16103 + if (pmd_none(*pmd)) {
16104 + pte_t *page_table = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
16105 + make_lowmem_page_readonly(page_table,
16106 + XENFEAT_writable_page_tables);
16107 + set_pmd(pmd, __pmd(__pa(page_table) | _PAGE_TABLE));
16108 + if (page_table != pte_offset_kernel(pmd, 0))
16111 + return page_table;
16114 + return pte_offset_kernel(pmd, 0);
16118 + * This function initializes a certain range of kernel virtual memory
16119 + * with new bootmem page tables, everywhere page tables are missing in
16120 + * the given range.
16124 + * NOTE: The pagetables are allocated contiguous on the physical space
16125 + * so we can cache the place of the first one and move around without
16126 + * checking the pgd every time.
16128 +static void __init page_table_range_init (unsigned long start, unsigned long end, pgd_t *pgd_base)
16133 + int pgd_idx, pmd_idx;
16134 + unsigned long vaddr;
16137 + pgd_idx = pgd_index(vaddr);
16138 + pmd_idx = pmd_index(vaddr);
16139 + pgd = pgd_base + pgd_idx;
16141 + for ( ; (pgd_idx < PTRS_PER_PGD) && (vaddr != end); pgd++, pgd_idx++) {
16142 + if (pgd_none(*pgd))
16143 + one_md_table_init(pgd);
16144 + pud = pud_offset(pgd, vaddr);
16145 + pmd = pmd_offset(pud, vaddr);
16146 + for (; (pmd_idx < PTRS_PER_PMD) && (vaddr != end); pmd++, pmd_idx++) {
16147 + if (vaddr < hypervisor_virt_start && pmd_none(*pmd))
16148 + one_page_table_init(pmd);
16150 + vaddr += PMD_SIZE;
16156 +static inline int is_kernel_text(unsigned long addr)
16158 + if (addr >= PAGE_OFFSET && addr <= (unsigned long)__init_end)
16164 + * This maps the physical memory to kernel virtual address space, a total
16165 + * of max_low_pfn pages, by creating page tables starting from address
16168 +static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
16170 + unsigned long pfn;
16174 + int pgd_idx, pmd_idx, pte_ofs;
16176 + unsigned long max_ram_pfn = xen_start_info->nr_pages;
16177 + if (max_ram_pfn > max_low_pfn)
16178 + max_ram_pfn = max_low_pfn;
16180 + pgd_idx = pgd_index(PAGE_OFFSET);
16181 + pgd = pgd_base + pgd_idx;
16183 + pmd_idx = pmd_index(PAGE_OFFSET);
16184 + pte_ofs = pte_index(PAGE_OFFSET);
16186 + for (; pgd_idx < PTRS_PER_PGD; pgd++, pgd_idx++) {
16189 + * Native linux hasn't PAE-paging enabled yet at this
16190 + * point. When running as xen domain we are in PAE
16191 + * mode already, thus we can't simply hook a empty
16192 + * pmd. That would kill the mappings we are currently
16195 + pmd = pmd_offset(pud_offset(pgd, PAGE_OFFSET), PAGE_OFFSET);
16197 + pmd = one_md_table_init(pgd);
16199 + if (pfn >= max_low_pfn)
16202 + for (; pmd_idx < PTRS_PER_PMD && pfn < max_low_pfn; pmd++, pmd_idx++) {
16203 + unsigned int address = pfn * PAGE_SIZE + PAGE_OFFSET;
16204 + if (address >= hypervisor_virt_start)
16207 + /* Map with big pages if possible, otherwise create normal page tables. */
16208 + if (cpu_has_pse) {
16209 + unsigned int address2 = (pfn + PTRS_PER_PTE - 1) * PAGE_SIZE + PAGE_OFFSET + PAGE_SIZE-1;
16211 + if (is_kernel_text(address) || is_kernel_text(address2))
16212 + set_pmd(pmd, pfn_pmd(pfn, PAGE_KERNEL_LARGE_EXEC));
16214 + set_pmd(pmd, pfn_pmd(pfn, PAGE_KERNEL_LARGE));
16215 + pfn += PTRS_PER_PTE;
16217 + pte = one_page_table_init(pmd);
16220 + for (; pte_ofs < PTRS_PER_PTE && pfn < max_low_pfn; pte++, pfn++, pte_ofs++) {
16221 + /* XEN: Only map initial RAM allocation. */
16222 + if ((pfn >= max_ram_pfn) || pte_present(*pte))
16224 + if (is_kernel_text(address))
16225 + set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC));
16227 + set_pte(pte, pfn_pte(pfn, PAGE_KERNEL));
16236 +#ifndef CONFIG_XEN
16238 +static inline int page_kills_ppro(unsigned long pagenr)
16240 + if (pagenr >= 0x70000 && pagenr <= 0x7003F)
16247 +#define page_kills_ppro(p) 0
16251 +extern int is_available_memory(efi_memory_desc_t *);
16253 +int page_is_ram(unsigned long pagenr)
16256 + unsigned long addr, end;
16258 + if (efi_enabled) {
16259 + efi_memory_desc_t *md;
16262 + for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
16264 + if (!is_available_memory(md))
16266 + addr = (md->phys_addr+PAGE_SIZE-1) >> PAGE_SHIFT;
16267 + end = (md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT)) >> PAGE_SHIFT;
16269 + if ((pagenr >= addr) && (pagenr < end))
16275 + for (i = 0; i < e820.nr_map; i++) {
16277 + if (e820.map[i].type != E820_RAM) /* not usable memory */
16280 + * !!!FIXME!!! Some BIOSen report areas as RAM that
16281 + * are not. Notably the 640->1Mb area. We need a sanity
16284 + addr = (e820.map[i].addr+PAGE_SIZE-1) >> PAGE_SHIFT;
16285 + end = (e820.map[i].addr+e820.map[i].size) >> PAGE_SHIFT;
16286 + if ((pagenr >= addr) && (pagenr < end))
16292 +#ifdef CONFIG_HIGHMEM
16294 +pgprot_t kmap_prot;
16296 +#define kmap_get_fixmap_pte(vaddr) \
16297 + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), vaddr), (vaddr)), (vaddr))
16299 +static void __init kmap_init(void)
16301 + unsigned long kmap_vstart;
16303 + /* cache the first kmap pte */
16304 + kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN);
16305 + kmap_pte = kmap_get_fixmap_pte(kmap_vstart);
16307 + kmap_prot = PAGE_KERNEL;
16310 +static void __init permanent_kmaps_init(pgd_t *pgd_base)
16316 + unsigned long vaddr;
16318 + vaddr = PKMAP_BASE;
16319 + page_table_range_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
16321 + pgd = swapper_pg_dir + pgd_index(vaddr);
16322 + pud = pud_offset(pgd, vaddr);
16323 + pmd = pmd_offset(pud, vaddr);
16324 + pte = pte_offset_kernel(pmd, vaddr);
16325 + pkmap_page_table = pte;
16328 +static void __meminit free_new_highpage(struct page *page, int pfn)
16330 + init_page_count(page);
16331 + if (pfn < xen_start_info->nr_pages)
16332 + __free_page(page);
16333 + totalhigh_pages++;
16336 +void __init add_one_highpage_init(struct page *page, int pfn, int bad_ppro)
16338 + if (page_is_ram(pfn) && !(bad_ppro && page_kills_ppro(pfn))) {
16339 + ClearPageReserved(page);
16340 + free_new_highpage(page, pfn);
16342 + SetPageReserved(page);
16345 +static int add_one_highpage_hotplug(struct page *page, unsigned long pfn)
16347 + free_new_highpage(page, pfn);
16348 + totalram_pages++;
16349 +#ifdef CONFIG_FLATMEM
16350 + max_mapnr = max(pfn, max_mapnr);
16357 + * Not currently handling the NUMA case.
16358 + * Assuming single node and all memory that
16359 + * has been added dynamically that would be
16360 + * onlined here is in HIGHMEM
16362 +void online_page(struct page *page)
16364 + ClearPageReserved(page);
16365 + add_one_highpage_hotplug(page, page_to_pfn(page));
16369 +#ifdef CONFIG_NUMA
16370 +extern void set_highmem_pages_init(int);
16372 +static void __init set_highmem_pages_init(int bad_ppro)
16375 + for (pfn = highstart_pfn; pfn < highend_pfn; pfn++)
16376 + add_one_highpage_init(pfn_to_page(pfn), pfn, bad_ppro);
16377 + totalram_pages += totalhigh_pages;
16379 +#endif /* CONFIG_FLATMEM */
16382 +#define kmap_init() do { } while (0)
16383 +#define permanent_kmaps_init(pgd_base) do { } while (0)
16384 +#define set_highmem_pages_init(bad_ppro) do { } while (0)
16385 +#endif /* CONFIG_HIGHMEM */
16387 +unsigned long long __PAGE_KERNEL = _PAGE_KERNEL;
16388 +EXPORT_SYMBOL(__PAGE_KERNEL);
16389 +unsigned long long __PAGE_KERNEL_EXEC = _PAGE_KERNEL_EXEC;
16391 +#ifdef CONFIG_NUMA
16392 +extern void __init remap_numa_kva(void);
16394 +#define remap_numa_kva() do {} while (0)
16397 +pgd_t *swapper_pg_dir;
16399 +static void __init pagetable_init (void)
16401 + unsigned long vaddr;
16402 + pgd_t *pgd_base = (pgd_t *)xen_start_info->pt_base;
16404 + /* Enable PSE if available */
16405 + if (cpu_has_pse) {
16406 + set_in_cr4(X86_CR4_PSE);
16409 + /* Enable PGE if available */
16410 + if (cpu_has_pge) {
16411 + set_in_cr4(X86_CR4_PGE);
16412 + __PAGE_KERNEL |= _PAGE_GLOBAL;
16413 + __PAGE_KERNEL_EXEC |= _PAGE_GLOBAL;
16416 + kernel_physical_mapping_init(pgd_base);
16417 + remap_numa_kva();
16420 + * Fixed mappings, only the page table structure has to be
16421 + * created - mappings will be set by set_fixmap():
16423 + vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
16424 + page_table_range_init(vaddr, hypervisor_virt_start, pgd_base);
16426 + permanent_kmaps_init(pgd_base);
16429 +#if defined(CONFIG_SOFTWARE_SUSPEND) || defined(CONFIG_ACPI_SLEEP)
16431 + * Swap suspend & friends need this for resume because things like the intel-agp
16432 + * driver might have split up a kernel 4MB mapping.
16434 +char __nosavedata swsusp_pg_dir[PAGE_SIZE]
16435 + __attribute__ ((aligned (PAGE_SIZE)));
16437 +static inline void save_pg_dir(void)
16439 + memcpy(swsusp_pg_dir, swapper_pg_dir, PAGE_SIZE);
16442 +static inline void save_pg_dir(void)
16447 +void zap_low_mappings (void)
16454 + * Zap initial low-memory mappings.
16456 + * Note that "pgd_clear()" doesn't do it for
16457 + * us, because pgd_clear() is a no-op on i386.
16459 + for (i = 0; i < USER_PTRS_PER_PGD; i++)
16460 +#if defined(CONFIG_X86_PAE) && !defined(CONFIG_XEN)
16461 + set_pgd(swapper_pg_dir+i, __pgd(1 + __pa(empty_zero_page)));
16463 + set_pgd(swapper_pg_dir+i, __pgd(0));
16468 +static int disable_nx __initdata = 0;
16469 +u64 __supported_pte_mask __read_mostly = ~_PAGE_NX;
16470 +EXPORT_SYMBOL(__supported_pte_mask);
16473 + * noexec = on|off
16475 + * Control non executable mappings.
16480 +void __init noexec_setup(const char *str)
16482 + if (!strncmp(str, "on",2) && cpu_has_nx) {
16483 + __supported_pte_mask |= _PAGE_NX;
16485 + } else if (!strncmp(str,"off",3)) {
16487 + __supported_pte_mask &= ~_PAGE_NX;
16491 +int nx_enabled = 0;
16492 +#ifdef CONFIG_X86_PAE
16494 +static void __init set_nx(void)
16496 + unsigned int v[4], l, h;
16498 + if (cpu_has_pae && (cpuid_eax(0x80000000) > 0x80000001)) {
16499 + cpuid(0x80000001, &v[0], &v[1], &v[2], &v[3]);
16500 + if ((v[3] & (1 << 20)) && !disable_nx) {
16501 + rdmsr(MSR_EFER, l, h);
16503 + wrmsr(MSR_EFER, l, h);
16505 + __supported_pte_mask |= _PAGE_NX;
16511 + * Enables/disables executability of a given kernel page and
16512 + * returns the previous setting.
16514 +int __init set_kernel_exec(unsigned long vaddr, int enable)
16522 + pte = lookup_address(vaddr);
16525 + if (!pte_exec_kernel(*pte))
16529 + pte->pte_high &= ~(1 << (_PAGE_BIT_NX - 32));
16531 + pte->pte_high |= 1 << (_PAGE_BIT_NX - 32);
16532 + __flush_tlb_all();
16540 + * paging_init() sets up the page tables - note that the first 8MB are
16541 + * already mapped by head.S.
16543 + * This routines also unmaps the page at virtual kernel address 0, so
16544 + * that we can trap those pesky NULL-reference errors in the kernel.
16546 +void __init paging_init(void)
16550 +#ifdef CONFIG_X86_PAE
16553 + printk("NX (Execute Disable) protection: active\n");
16556 + pagetable_init();
16558 +#if defined(CONFIG_X86_PAE) && !defined(CONFIG_XEN)
16560 + * We will bail out later - printk doesn't work right now so
16561 + * the user would just see a hanging kernel.
16562 + * when running as xen domain we are already in PAE mode at
16566 + set_in_cr4(X86_CR4_PAE);
16568 + __flush_tlb_all();
16572 + /* Switch to the real shared_info page, and clear the
16574 + set_fixmap(FIX_SHARED_INFO, xen_start_info->shared_info);
16575 + HYPERVISOR_shared_info = (shared_info_t *)fix_to_virt(FIX_SHARED_INFO);
16576 + memset(empty_zero_page, 0, sizeof(empty_zero_page));
16578 + /* Setup mapping of lower 1st MB */
16579 + for (i = 0; i < NR_FIX_ISAMAPS; i++)
16580 + if (is_initial_xendomain())
16581 + set_fixmap(FIX_ISAMAP_BEGIN - i, i * PAGE_SIZE);
16583 + __set_fixmap(FIX_ISAMAP_BEGIN - i,
16584 + virt_to_machine(empty_zero_page),
16589 + * Test if the WP bit works in supervisor mode. It isn't supported on 386's
16590 + * and also on some strange 486's (NexGen etc.). All 586+'s are OK. This
16591 + * used to involve black magic jumps to work around some nasty CPU bugs,
16592 + * but fortunately the switch to using exceptions got rid of all that.
16595 +static void __init test_wp_bit(void)
16597 + printk("Checking if this processor honours the WP bit even in supervisor mode... ");
16599 + /* Any page-aligned address will do, the test is non-destructive */
16600 + __set_fixmap(FIX_WP_TEST, __pa(&swapper_pg_dir), PAGE_READONLY);
16601 + boot_cpu_data.wp_works_ok = do_test_wp_bit();
16602 + clear_fixmap(FIX_WP_TEST);
16604 + if (!boot_cpu_data.wp_works_ok) {
16606 +#ifdef CONFIG_X86_WP_WORKS_OK
16607 + panic("This kernel doesn't support CPU's with broken WP. Recompile it for a 386!");
16614 +static void __init set_max_mapnr_init(void)
16616 +#ifdef CONFIG_HIGHMEM
16617 + num_physpages = highend_pfn;
16619 + num_physpages = max_low_pfn;
16621 +#ifdef CONFIG_FLATMEM
16622 + max_mapnr = num_physpages;
16626 +static struct kcore_list kcore_mem, kcore_vmalloc;
16628 +void __init mem_init(void)
16630 + extern int ppro_with_ram_bug(void);
16631 + int codesize, reservedpages, datasize, initsize;
16634 + unsigned long pfn;
16636 +#if defined(CONFIG_SWIOTLB)
16640 +#ifdef CONFIG_FLATMEM
16645 + bad_ppro = ppro_with_ram_bug();
16647 +#ifdef CONFIG_HIGHMEM
16648 + /* check that fixmap and pkmap do not overlap */
16649 + if (PKMAP_BASE+LAST_PKMAP*PAGE_SIZE >= FIXADDR_START) {
16650 + printk(KERN_ERR "fixmap and kmap areas overlap - this will crash\n");
16651 + printk(KERN_ERR "pkstart: %lxh pkend: %lxh fixstart %lxh\n",
16652 + PKMAP_BASE, PKMAP_BASE+LAST_PKMAP*PAGE_SIZE, FIXADDR_START);
16657 + set_max_mapnr_init();
16659 +#ifdef CONFIG_HIGHMEM
16660 + high_memory = (void *) __va(highstart_pfn * PAGE_SIZE - 1) + 1;
16662 + high_memory = (void *) __va(max_low_pfn * PAGE_SIZE - 1) + 1;
16664 + printk("vmalloc area: %lx-%lx, maxmem %lx\n",
16665 + VMALLOC_START,VMALLOC_END,MAXMEM);
16666 + BUG_ON(VMALLOC_START > VMALLOC_END);
16668 + /* this will put all low memory onto the freelists */
16669 + totalram_pages += free_all_bootmem();
16670 + /* XEN: init and count low-mem pages outside initial allocation. */
16671 + for (pfn = xen_start_info->nr_pages; pfn < max_low_pfn; pfn++) {
16672 + ClearPageReserved(pfn_to_page(pfn));
16673 + init_page_count(pfn_to_page(pfn));
16674 + totalram_pages++;
16677 + reservedpages = 0;
16678 + for (tmp = 0; tmp < max_low_pfn; tmp++)
16680 + * Only count reserved RAM pages
16682 + if (page_is_ram(tmp) && PageReserved(pfn_to_page(tmp)))
16685 + set_highmem_pages_init(bad_ppro);
16687 + codesize = (unsigned long) &_etext - (unsigned long) &_text;
16688 + datasize = (unsigned long) &_edata - (unsigned long) &_etext;
16689 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
16691 + kclist_add(&kcore_mem, __va(0), max_low_pfn << PAGE_SHIFT);
16692 + kclist_add(&kcore_vmalloc, (void *)VMALLOC_START,
16693 + VMALLOC_END-VMALLOC_START);
16695 + printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init, %ldk highmem)\n",
16696 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
16697 + num_physpages << (PAGE_SHIFT-10),
16699 + reservedpages << (PAGE_SHIFT-10),
16702 + (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))
16705 +#ifdef CONFIG_X86_PAE
16706 + if (!cpu_has_pae)
16707 + panic("cannot execute a PAE-enabled kernel on a PAE-less CPU!");
16709 + if (boot_cpu_data.wp_works_ok < 0)
16713 + * Subtle. SMP is doing it's boot stuff late (because it has to
16714 + * fork idle threads) - but it also needs low mappings for the
16715 + * protected-mode entry to work. We zap these entries only after
16716 + * the WP-bit has been tested.
16718 +#ifndef CONFIG_SMP
16719 + zap_low_mappings();
16722 + set_bit(PG_pinned, &virt_to_page(init_mm.pgd)->flags);
16726 + * this is for the non-NUMA, single node SMP system case.
16727 + * Specifically, in the case of x86, we will always add
16728 + * memory to the highmem for now.
16730 +#ifdef CONFIG_MEMORY_HOTPLUG
16731 +#ifndef CONFIG_NEED_MULTIPLE_NODES
16732 +int arch_add_memory(int nid, u64 start, u64 size)
16734 + struct pglist_data *pgdata = &contig_page_data;
16735 + struct zone *zone = pgdata->node_zones + MAX_NR_ZONES-1;
16736 + unsigned long start_pfn = start >> PAGE_SHIFT;
16737 + unsigned long nr_pages = size >> PAGE_SHIFT;
16739 + return __add_pages(zone, start_pfn, nr_pages);
16742 +int remove_memory(u64 start, u64 size)
16749 +kmem_cache_t *pgd_cache;
16750 +kmem_cache_t *pmd_cache;
16752 +void __init pgtable_cache_init(void)
16754 + if (PTRS_PER_PMD > 1) {
16755 + pmd_cache = kmem_cache_create("pmd",
16756 + PTRS_PER_PMD*sizeof(pmd_t),
16757 + PTRS_PER_PMD*sizeof(pmd_t),
16762 + panic("pgtable_cache_init(): cannot create pmd cache");
16764 + pgd_cache = kmem_cache_create("pgd",
16765 +#ifndef CONFIG_XEN
16766 + PTRS_PER_PGD*sizeof(pgd_t),
16767 + PTRS_PER_PGD*sizeof(pgd_t),
16774 + PTRS_PER_PMD == 1 ? pgd_dtor : NULL);
16776 + panic("pgtable_cache_init(): Cannot create pgd cache");
16780 + * This function cannot be __init, since exceptions don't work in that
16781 + * section. Put this after the callers, so that it cannot be inlined.
16783 +static int noinline do_test_wp_bit(void)
16788 + __asm__ __volatile__(
16790 + "1: movb %1,%0 \n"
16793 + ".section __ex_table,\"a\"\n"
16795 + " .long 1b,2b \n"
16797 + :"=m" (*(char *)fix_to_virt(FIX_WP_TEST)),
16806 +#ifdef CONFIG_DEBUG_RODATA
16808 +void mark_rodata_ro(void)
16810 + unsigned long addr = (unsigned long)__start_rodata;
16812 + for (; addr < (unsigned long)__end_rodata; addr += PAGE_SIZE)
16813 + change_page_attr(virt_to_page(addr), 1, PAGE_KERNEL_RO);
16815 + printk("Write protecting the kernel read-only data: %uk\n",
16816 + (__end_rodata - __start_rodata) >> 10);
16819 + * change_page_attr() requires a global_flush_tlb() call after it.
16820 + * We do this after the printk so that if something went wrong in the
16821 + * change, the printk gets out at least to give a better debug hint
16822 + * of who is the culprit.
16824 + global_flush_tlb();
16828 +void free_init_pages(char *what, unsigned long begin, unsigned long end)
16830 + unsigned long addr;
16832 + for (addr = begin; addr < end; addr += PAGE_SIZE) {
16833 + ClearPageReserved(virt_to_page(addr));
16834 + init_page_count(virt_to_page(addr));
16835 + memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
16837 + totalram_pages++;
16839 + printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
16842 +void free_initmem(void)
16844 + free_init_pages("unused kernel memory",
16845 + (unsigned long)(&__init_begin),
16846 + (unsigned long)(&__init_end));
16849 +#ifdef CONFIG_BLK_DEV_INITRD
16850 +void free_initrd_mem(unsigned long start, unsigned long end)
16852 + free_init_pages("initrd memory", start, end);
16856 Index: head-2008-11-25/arch/x86/mm/ioremap_32-xen.c
16857 ===================================================================
16858 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
16859 +++ head-2008-11-25/arch/x86/mm/ioremap_32-xen.c 2008-04-02 12:34:02.000000000 +0200
16862 + * arch/i386/mm/ioremap.c
16864 + * Re-map IO memory to kernel address space so that we can access it.
16865 + * This is needed for high PCI addresses that aren't mapped in the
16866 + * 640k-1MB IO memory area on PC's
16868 + * (C) Copyright 1995 1996 Linus Torvalds
16871 +#include <linux/vmalloc.h>
16872 +#include <linux/init.h>
16873 +#include <linux/slab.h>
16874 +#include <linux/module.h>
16875 +#include <asm/io.h>
16876 +#include <asm/fixmap.h>
16877 +#include <asm/cacheflush.h>
16878 +#include <asm/tlbflush.h>
16879 +#include <asm/pgtable.h>
16880 +#include <asm/pgalloc.h>
16882 +#define ISA_START_ADDRESS 0x0
16883 +#define ISA_END_ADDRESS 0x100000
16885 +static int direct_remap_area_pte_fn(pte_t *pte,
16886 + struct page *pmd_page,
16887 + unsigned long address,
16890 + mmu_update_t **v = (mmu_update_t **)data;
16892 + BUG_ON(!pte_none(*pte));
16894 + (*v)->ptr = ((u64)pfn_to_mfn(page_to_pfn(pmd_page)) <<
16895 + PAGE_SHIFT) | ((unsigned long)pte & ~PAGE_MASK);
16901 +static int __direct_remap_pfn_range(struct mm_struct *mm,
16902 + unsigned long address,
16903 + unsigned long mfn,
16904 + unsigned long size,
16909 + unsigned long i, start_address;
16910 + mmu_update_t *u, *v, *w;
16912 + u = v = w = (mmu_update_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT);
16916 + start_address = address;
16918 + flush_cache_all();
16920 + for (i = 0; i < size; i += PAGE_SIZE) {
16921 + if ((v - u) == (PAGE_SIZE / sizeof(mmu_update_t))) {
16922 + /* Flush a full batch after filling in the PTE ptrs. */
16923 + rc = apply_to_page_range(mm, start_address,
16924 + address - start_address,
16925 + direct_remap_area_pte_fn, &w);
16929 + if (HYPERVISOR_mmu_update(u, v - u, NULL, domid) < 0)
16932 + start_address = address;
16936 + * Fill in the machine address: PTE ptr is done later by
16937 + * apply_to_page_range().
16939 + v->val = __pte_val(pfn_pte_ma(mfn, prot)) | _PAGE_IO;
16942 + address += PAGE_SIZE;
16947 + /* Final batch. */
16948 + rc = apply_to_page_range(mm, start_address,
16949 + address - start_address,
16950 + direct_remap_area_pte_fn, &w);
16954 + if (unlikely(HYPERVISOR_mmu_update(u, v - u, NULL, domid) < 0))
16963 + free_page((unsigned long)u);
16968 +int direct_remap_pfn_range(struct vm_area_struct *vma,
16969 + unsigned long address,
16970 + unsigned long mfn,
16971 + unsigned long size,
16975 + if (xen_feature(XENFEAT_auto_translated_physmap))
16976 + return remap_pfn_range(vma, address, mfn, size, prot);
16978 + if (domid == DOMID_SELF)
16981 + vma->vm_flags |= VM_IO | VM_RESERVED;
16983 + vma->vm_mm->context.has_foreign_mappings = 1;
16985 + return __direct_remap_pfn_range(
16986 + vma->vm_mm, address, mfn, size, prot, domid);
16988 +EXPORT_SYMBOL(direct_remap_pfn_range);
16990 +int direct_kernel_remap_pfn_range(unsigned long address,
16991 + unsigned long mfn,
16992 + unsigned long size,
16996 + return __direct_remap_pfn_range(
16997 + &init_mm, address, mfn, size, prot, domid);
16999 +EXPORT_SYMBOL(direct_kernel_remap_pfn_range);
17001 +static int lookup_pte_fn(
17002 + pte_t *pte, struct page *pmd_page, unsigned long addr, void *data)
17004 + uint64_t *ptep = (uint64_t *)data;
17006 + *ptep = ((uint64_t)pfn_to_mfn(page_to_pfn(pmd_page)) <<
17007 + PAGE_SHIFT) | ((unsigned long)pte & ~PAGE_MASK);
17011 +int create_lookup_pte_addr(struct mm_struct *mm,
17012 + unsigned long address,
17015 + return apply_to_page_range(mm, address, PAGE_SIZE,
17016 + lookup_pte_fn, ptep);
17019 +EXPORT_SYMBOL(create_lookup_pte_addr);
17021 +static int noop_fn(
17022 + pte_t *pte, struct page *pmd_page, unsigned long addr, void *data)
17027 +int touch_pte_range(struct mm_struct *mm,
17028 + unsigned long address,
17029 + unsigned long size)
17031 + return apply_to_page_range(mm, address, size, noop_fn, NULL);
17034 +EXPORT_SYMBOL(touch_pte_range);
17037 + * Does @address reside within a non-highmem page that is local to this virtual
17038 + * machine (i.e., not an I/O page, nor a memory page belonging to another VM).
17039 + * See the comment that accompanies mfn_to_local_pfn() in page.h to understand
17040 + * why this works.
17042 +static inline int is_local_lowmem(unsigned long address)
17044 + extern unsigned long max_low_pfn;
17045 + return (mfn_to_local_pfn(address >> PAGE_SHIFT) < max_low_pfn);
17049 + * Generic mapping function (not visible outside):
17053 + * Remap an arbitrary physical address space into the kernel virtual
17054 + * address space. Needed when the kernel wants to access high addresses
17057 + * NOTE! We need to allow non-page-aligned mappings too: we will obviously
17058 + * have to convert them into an offset in a page-aligned mapping, but the
17059 + * caller shouldn't need to know that small detail.
17061 +void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
17063 + void __iomem * addr;
17064 + struct vm_struct * area;
17065 + unsigned long offset, last_addr;
17066 + domid_t domid = DOMID_IO;
17068 + /* Don't allow wraparound or zero size */
17069 + last_addr = phys_addr + size - 1;
17070 + if (!size || last_addr < phys_addr)
17074 + * Don't remap the low PCI/ISA area, it's always mapped..
17076 + if (is_initial_xendomain() &&
17077 + phys_addr >= ISA_START_ADDRESS && last_addr < ISA_END_ADDRESS)
17078 + return (void __iomem *) isa_bus_to_virt(phys_addr);
17081 + * Don't allow anybody to remap normal RAM that we're using..
17083 + if (is_local_lowmem(phys_addr)) {
17084 + char *t_addr, *t_end;
17085 + struct page *page;
17087 + t_addr = bus_to_virt(phys_addr);
17088 + t_end = t_addr + (size - 1);
17090 + for(page = virt_to_page(t_addr); page <= virt_to_page(t_end); page++)
17091 + if(!PageReserved(page))
17094 + domid = DOMID_SELF;
17098 + * Mappings have to be page-aligned
17100 + offset = phys_addr & ~PAGE_MASK;
17101 + phys_addr &= PAGE_MASK;
17102 + size = PAGE_ALIGN(last_addr+1) - phys_addr;
17105 + * Ok, go for it..
17107 + area = get_vm_area(size, VM_IOREMAP | (flags << 20));
17110 + area->phys_addr = phys_addr;
17111 + addr = (void __iomem *) area->addr;
17112 + flags |= _KERNPG_TABLE;
17113 + if (__direct_remap_pfn_range(&init_mm, (unsigned long)addr,
17114 + phys_addr>>PAGE_SHIFT,
17115 + size, __pgprot(flags), domid)) {
17116 + vunmap((void __force *) addr);
17119 + return (void __iomem *) (offset + (char __iomem *)addr);
17121 +EXPORT_SYMBOL(__ioremap);
17124 + * ioremap_nocache - map bus memory into CPU space
17125 + * @offset: bus address of the memory
17126 + * @size: size of the resource to map
17128 + * ioremap_nocache performs a platform specific sequence of operations to
17129 + * make bus memory CPU accessible via the readb/readw/readl/writeb/
17130 + * writew/writel functions and the other mmio helpers. The returned
17131 + * address is not guaranteed to be usable directly as a virtual
17134 + * This version of ioremap ensures that the memory is marked uncachable
17135 + * on the CPU as well as honouring existing caching rules from things like
17136 + * the PCI bus. Note that there are other caches and buffers on many
17137 + * busses. In particular driver authors should read up on PCI writes
17139 + * It's useful if some control registers are in such an area and
17140 + * write combining or read caching is not desirable:
17142 + * Must be freed with iounmap.
17145 +void __iomem *ioremap_nocache (unsigned long phys_addr, unsigned long size)
17147 + unsigned long last_addr;
17148 + void __iomem *p = __ioremap(phys_addr, size, _PAGE_PCD);
17152 + /* Guaranteed to be > phys_addr, as per __ioremap() */
17153 + last_addr = phys_addr + size - 1;
17155 + if (is_local_lowmem(last_addr)) {
17156 + struct page *ppage = virt_to_page(bus_to_virt(phys_addr));
17157 + unsigned long npages;
17159 + phys_addr &= PAGE_MASK;
17161 + /* This might overflow and become zero.. */
17162 + last_addr = PAGE_ALIGN(last_addr);
17164 + /* .. but that's ok, because modulo-2**n arithmetic will make
17165 + * the page-aligned "last - first" come out right.
17167 + npages = (last_addr - phys_addr) >> PAGE_SHIFT;
17169 + if (change_page_attr(ppage, npages, PAGE_KERNEL_NOCACHE) < 0) {
17173 + global_flush_tlb();
17178 +EXPORT_SYMBOL(ioremap_nocache);
17181 + * iounmap - Free a IO remapping
17182 + * @addr: virtual address from ioremap_*
17184 + * Caller must ensure there is only one unmapping for the same pointer.
17186 +void iounmap(volatile void __iomem *addr)
17188 + struct vm_struct *p, *o;
17190 + if ((void __force *)addr <= high_memory)
17194 + * __ioremap special-cases the PCI/ISA range by not instantiating a
17195 + * vm_area and by simply returning an address into the kernel mapping
17196 + * of ISA space. So handle that here.
17198 + if ((unsigned long) addr >= fix_to_virt(FIX_ISAMAP_BEGIN))
17201 + addr = (volatile void __iomem *)(PAGE_MASK & (unsigned long __force)addr);
17203 + /* Use the vm area unlocked, assuming the caller
17204 + ensures there isn't another iounmap for the same address
17205 + in parallel. Reuse of the virtual address is prevented by
17206 + leaving it in the global lists until we're done with it.
17207 + cpa takes care of the direct mappings. */
17208 + read_lock(&vmlist_lock);
17209 + for (p = vmlist; p; p = p->next) {
17210 + if (p->addr == addr)
17213 + read_unlock(&vmlist_lock);
17216 + printk("iounmap: bad address %p\n", addr);
17221 + /* Reset the direct mapping. Can block */
17222 + if ((p->flags >> 20) && is_local_lowmem(p->phys_addr)) {
17223 + /* p->size includes the guard page, but cpa doesn't like that */
17224 + change_page_attr(virt_to_page(bus_to_virt(p->phys_addr)),
17225 + (p->size - PAGE_SIZE) >> PAGE_SHIFT,
17227 + global_flush_tlb();
17230 + /* Finally remove it */
17231 + o = remove_vm_area((void *)addr);
17232 + BUG_ON(p != o || o == NULL);
17235 +EXPORT_SYMBOL(iounmap);
17237 +void __init *bt_ioremap(unsigned long phys_addr, unsigned long size)
17239 + unsigned long offset, last_addr;
17240 + unsigned int nrpages;
17241 + enum fixed_addresses idx;
17243 + /* Don't allow wraparound or zero size */
17244 + last_addr = phys_addr + size - 1;
17245 + if (!size || last_addr < phys_addr)
17249 + * Don't remap the low PCI/ISA area, it's always mapped..
17251 + if (is_initial_xendomain() &&
17252 + phys_addr >= ISA_START_ADDRESS && last_addr < ISA_END_ADDRESS)
17253 + return isa_bus_to_virt(phys_addr);
17256 + * Mappings have to be page-aligned
17258 + offset = phys_addr & ~PAGE_MASK;
17259 + phys_addr &= PAGE_MASK;
17260 + size = PAGE_ALIGN(last_addr) - phys_addr;
17263 + * Mappings have to fit in the FIX_BTMAP area.
17265 + nrpages = size >> PAGE_SHIFT;
17266 + if (nrpages > NR_FIX_BTMAPS)
17270 + * Ok, go for it..
17272 + idx = FIX_BTMAP_BEGIN;
17273 + while (nrpages > 0) {
17274 + set_fixmap(idx, phys_addr);
17275 + phys_addr += PAGE_SIZE;
17279 + return (void*) (offset + fix_to_virt(FIX_BTMAP_BEGIN));
17282 +void __init bt_iounmap(void *addr, unsigned long size)
17284 + unsigned long virt_addr;
17285 + unsigned long offset;
17286 + unsigned int nrpages;
17287 + enum fixed_addresses idx;
17289 + virt_addr = (unsigned long)addr;
17290 + if (virt_addr < fix_to_virt(FIX_BTMAP_BEGIN))
17292 + if (virt_addr >= fix_to_virt(FIX_ISAMAP_BEGIN))
17294 + offset = virt_addr & ~PAGE_MASK;
17295 + nrpages = PAGE_ALIGN(offset + size - 1) >> PAGE_SHIFT;
17297 + idx = FIX_BTMAP_BEGIN;
17298 + while (nrpages > 0) {
17299 + clear_fixmap(idx);
17304 Index: head-2008-11-25/arch/x86/mm/pgtable_32-xen.c
17305 ===================================================================
17306 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
17307 +++ head-2008-11-25/arch/x86/mm/pgtable_32-xen.c 2007-10-09 11:48:25.000000000 +0200
17310 + * linux/arch/i386/mm/pgtable.c
17313 +#include <linux/sched.h>
17314 +#include <linux/kernel.h>
17315 +#include <linux/errno.h>
17316 +#include <linux/mm.h>
17317 +#include <linux/swap.h>
17318 +#include <linux/smp.h>
17319 +#include <linux/highmem.h>
17320 +#include <linux/slab.h>
17321 +#include <linux/pagemap.h>
17322 +#include <linux/spinlock.h>
17323 +#include <linux/module.h>
17325 +#include <asm/system.h>
17326 +#include <asm/pgtable.h>
17327 +#include <asm/pgalloc.h>
17328 +#include <asm/fixmap.h>
17329 +#include <asm/e820.h>
17330 +#include <asm/tlb.h>
17331 +#include <asm/tlbflush.h>
17332 +#include <asm/io.h>
17333 +#include <asm/mmu_context.h>
17335 +#include <xen/features.h>
17336 +#include <asm/hypervisor.h>
17338 +static void pgd_test_and_unpin(pgd_t *pgd);
17340 +void show_mem(void)
17342 + int total = 0, reserved = 0;
17343 + int shared = 0, cached = 0;
17345 + struct page *page;
17346 + pg_data_t *pgdat;
17348 + unsigned long flags;
17350 + printk(KERN_INFO "Mem-info:\n");
17351 + show_free_areas();
17352 + printk(KERN_INFO "Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
17353 + for_each_online_pgdat(pgdat) {
17354 + pgdat_resize_lock(pgdat, &flags);
17355 + for (i = 0; i < pgdat->node_spanned_pages; ++i) {
17356 + page = pgdat_page_nr(pgdat, i);
17358 + if (PageHighMem(page))
17360 + if (PageReserved(page))
17362 + else if (PageSwapCache(page))
17364 + else if (page_count(page))
17365 + shared += page_count(page) - 1;
17367 + pgdat_resize_unlock(pgdat, &flags);
17369 + printk(KERN_INFO "%d pages of RAM\n", total);
17370 + printk(KERN_INFO "%d pages of HIGHMEM\n", highmem);
17371 + printk(KERN_INFO "%d reserved pages\n", reserved);
17372 + printk(KERN_INFO "%d pages shared\n", shared);
17373 + printk(KERN_INFO "%d pages swap cached\n", cached);
17375 + printk(KERN_INFO "%lu pages dirty\n", global_page_state(NR_FILE_DIRTY));
17376 + printk(KERN_INFO "%lu pages writeback\n",
17377 + global_page_state(NR_WRITEBACK));
17378 + printk(KERN_INFO "%lu pages mapped\n", global_page_state(NR_FILE_MAPPED));
17379 + printk(KERN_INFO "%lu pages slab\n", global_page_state(NR_SLAB));
17380 + printk(KERN_INFO "%lu pages pagetables\n",
17381 + global_page_state(NR_PAGETABLE));
17385 + * Associate a large virtual page frame with a given physical page frame
17386 + * and protection flags for that frame. pfn is for the base of the page,
17387 + * vaddr is what the page gets mapped to - both must be properly aligned.
17388 + * The pmd must already be instantiated. Assumes PAE mode.
17390 +void set_pmd_pfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags)
17396 + if (vaddr & (PMD_SIZE-1)) { /* vaddr is misaligned */
17397 + printk(KERN_WARNING "set_pmd_pfn: vaddr misaligned\n");
17398 + return; /* BUG(); */
17400 + if (pfn & (PTRS_PER_PTE-1)) { /* pfn is misaligned */
17401 + printk(KERN_WARNING "set_pmd_pfn: pfn misaligned\n");
17402 + return; /* BUG(); */
17404 + pgd = swapper_pg_dir + pgd_index(vaddr);
17405 + if (pgd_none(*pgd)) {
17406 + printk(KERN_WARNING "set_pmd_pfn: pgd_none\n");
17407 + return; /* BUG(); */
17409 + pud = pud_offset(pgd, vaddr);
17410 + pmd = pmd_offset(pud, vaddr);
17411 + set_pmd(pmd, pfn_pmd(pfn, flags));
17413 + * It's enough to flush this one mapping.
17414 + * (PGE mappings get flushed as well)
17416 + __flush_tlb_one(vaddr);
17419 +static int nr_fixmaps = 0;
17420 +unsigned long hypervisor_virt_start = HYPERVISOR_VIRT_START;
17421 +unsigned long __FIXADDR_TOP = (HYPERVISOR_VIRT_START - 2 * PAGE_SIZE);
17422 +EXPORT_SYMBOL(__FIXADDR_TOP);
17424 +void __init set_fixaddr_top(unsigned long top)
17426 + BUG_ON(nr_fixmaps > 0);
17427 + hypervisor_virt_start = top;
17428 + __FIXADDR_TOP = hypervisor_virt_start - 2 * PAGE_SIZE;
17431 +void __set_fixmap (enum fixed_addresses idx, maddr_t phys, pgprot_t flags)
17433 + unsigned long address = __fix_to_virt(idx);
17436 + if (idx >= __end_of_fixed_addresses) {
17441 + case FIX_WP_TEST:
17443 + pte = pfn_pte(phys >> PAGE_SHIFT, flags);
17446 + pte = pfn_pte_ma(phys >> PAGE_SHIFT, flags);
17449 + if (HYPERVISOR_update_va_mapping(address, pte,
17450 + UVMF_INVLPG|UVMF_ALL))
17455 +pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
17457 + pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
17459 + make_lowmem_page_readonly(pte, XENFEAT_writable_page_tables);
17463 +struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
17465 + struct page *pte;
17467 +#ifdef CONFIG_HIGHPTE
17468 + pte = alloc_pages(GFP_KERNEL|__GFP_HIGHMEM|__GFP_REPEAT|__GFP_ZERO, 0);
17470 + pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
17473 + SetPageForeign(pte, pte_free);
17474 + init_page_count(pte);
17479 +void pte_free(struct page *pte)
17481 + unsigned long pfn = page_to_pfn(pte);
17483 + if (!PageHighMem(pte)) {
17484 + unsigned long va = (unsigned long)__va(pfn << PAGE_SHIFT);
17486 + if (!pte_write(*virt_to_ptep(va)))
17487 + if (HYPERVISOR_update_va_mapping(
17488 + va, pfn_pte(pfn, PAGE_KERNEL), 0))
17491 + clear_bit(PG_pinned, &pte->flags);
17493 + ClearPageForeign(pte);
17494 + init_page_count(pte);
17496 + __free_page(pte);
17499 +void pmd_ctor(void *pmd, kmem_cache_t *cache, unsigned long flags)
17501 + memset(pmd, 0, PTRS_PER_PMD*sizeof(pmd_t));
17505 + * List of all pgd's needed for non-PAE so it can invalidate entries
17506 + * in both cached and uncached pgd's; not needed for PAE since the
17507 + * kernel pmd is shared. If PAE were not to share the pmd a similar
17508 + * tactic would be needed. This is essentially codepath-based locking
17509 + * against pageattr.c; it is the unique case in which a valid change
17510 + * of kernel pagetables can't be lazily synchronized by vmalloc faults.
17511 + * vmalloc faults work because attached pagetables are never freed.
17512 + * The locking scheme was chosen on the basis of manfred's
17513 + * recommendations and having no core impact whatsoever.
17516 +DEFINE_SPINLOCK(pgd_lock);
17517 +struct page *pgd_list;
17519 +static inline void pgd_list_add(pgd_t *pgd)
17521 + struct page *page = virt_to_page(pgd);
17522 + page->index = (unsigned long)pgd_list;
17524 + set_page_private(pgd_list, (unsigned long)&page->index);
17526 + set_page_private(page, (unsigned long)&pgd_list);
17529 +static inline void pgd_list_del(pgd_t *pgd)
17531 + struct page *next, **pprev, *page = virt_to_page(pgd);
17532 + next = (struct page *)page->index;
17533 + pprev = (struct page **)page_private(page);
17536 + set_page_private(next, (unsigned long)pprev);
17539 +void pgd_ctor(void *pgd, kmem_cache_t *cache, unsigned long unused)
17541 + unsigned long flags;
17543 + if (PTRS_PER_PMD > 1) {
17544 + if (HAVE_SHARED_KERNEL_PMD)
17545 + clone_pgd_range((pgd_t *)pgd + USER_PTRS_PER_PGD,
17546 + swapper_pg_dir + USER_PTRS_PER_PGD,
17547 + KERNEL_PGD_PTRS);
17549 + spin_lock_irqsave(&pgd_lock, flags);
17550 + clone_pgd_range((pgd_t *)pgd + USER_PTRS_PER_PGD,
17551 + swapper_pg_dir + USER_PTRS_PER_PGD,
17552 + KERNEL_PGD_PTRS);
17553 + memset(pgd, 0, USER_PTRS_PER_PGD*sizeof(pgd_t));
17554 + pgd_list_add(pgd);
17555 + spin_unlock_irqrestore(&pgd_lock, flags);
17559 +/* never called when PTRS_PER_PMD > 1 */
17560 +void pgd_dtor(void *pgd, kmem_cache_t *cache, unsigned long unused)
17562 + unsigned long flags; /* can be called from interrupt context */
17564 + spin_lock_irqsave(&pgd_lock, flags);
17565 + pgd_list_del(pgd);
17566 + spin_unlock_irqrestore(&pgd_lock, flags);
17568 + pgd_test_and_unpin(pgd);
17571 +pgd_t *pgd_alloc(struct mm_struct *mm)
17574 + pgd_t *pgd = kmem_cache_alloc(pgd_cache, GFP_KERNEL);
17576 + unsigned long flags;
17578 + pgd_test_and_unpin(pgd);
17580 + if (PTRS_PER_PMD == 1 || !pgd)
17583 + if (HAVE_SHARED_KERNEL_PMD) {
17584 + for (i = 0; i < USER_PTRS_PER_PGD; ++i) {
17585 + pmd_t *pmd = kmem_cache_alloc(pmd_cache, GFP_KERNEL);
17588 + set_pgd(&pgd[i], __pgd(1 + __pa(pmd)));
17594 + * We can race save/restore (if we sleep during a GFP_KERNEL memory
17595 + * allocation). We therefore store virtual addresses of pmds as they
17596 + * do not change across save/restore, and poke the machine addresses
17597 + * into the pgdir under the pgd_lock.
17599 + pmd = kmalloc(PTRS_PER_PGD * sizeof(pmd_t *), GFP_KERNEL);
17601 + kmem_cache_free(pgd_cache, pgd);
17605 + /* Allocate pmds, remember virtual addresses. */
17606 + for (i = 0; i < PTRS_PER_PGD; ++i) {
17607 + pmd[i] = kmem_cache_alloc(pmd_cache, GFP_KERNEL);
17612 + spin_lock_irqsave(&pgd_lock, flags);
17614 + /* Protect against save/restore: move below 4GB under pgd_lock. */
17615 + if (!xen_feature(XENFEAT_pae_pgdir_above_4gb)) {
17616 + int rc = xen_create_contiguous_region(
17617 + (unsigned long)pgd, 0, 32);
17619 + spin_unlock_irqrestore(&pgd_lock, flags);
17624 + /* Copy kernel pmd contents and write-protect the new pmds. */
17625 + for (i = USER_PTRS_PER_PGD; i < PTRS_PER_PGD; i++) {
17626 + unsigned long v = (unsigned long)i << PGDIR_SHIFT;
17627 + pgd_t *kpgd = pgd_offset_k(v);
17628 + pud_t *kpud = pud_offset(kpgd, v);
17629 + pmd_t *kpmd = pmd_offset(kpud, v);
17630 + memcpy(pmd[i], kpmd, PAGE_SIZE);
17631 + make_lowmem_page_readonly(
17632 + pmd[i], XENFEAT_writable_page_tables);
17635 + /* It is safe to poke machine addresses of pmds under the pmd_lock. */
17636 + for (i = 0; i < PTRS_PER_PGD; i++)
17637 + set_pgd(&pgd[i], __pgd(1 + __pa(pmd[i])));
17639 + /* Ensure this pgd gets picked up and pinned on save/restore. */
17640 + pgd_list_add(pgd);
17642 + spin_unlock_irqrestore(&pgd_lock, flags);
17649 + if (HAVE_SHARED_KERNEL_PMD) {
17650 + for (i--; i >= 0; i--)
17651 + kmem_cache_free(pmd_cache,
17652 + (void *)__va(pgd_val(pgd[i])-1));
17654 + for (i--; i >= 0; i--)
17655 + kmem_cache_free(pmd_cache, pmd[i]);
17658 + kmem_cache_free(pgd_cache, pgd);
17662 +void pgd_free(pgd_t *pgd)
17667 + * After this the pgd should not be pinned for the duration of this
17668 + * function's execution. We should never sleep and thus never race:
17669 + * 1. User pmds will not become write-protected under our feet due
17670 + * to a concurrent mm_pin_all().
17671 + * 2. The machine addresses in PGD entries will not become invalid
17672 + * due to a concurrent save/restore.
17674 + pgd_test_and_unpin(pgd);
17676 + /* in the PAE case user pgd entries are overwritten before usage */
17677 + if (PTRS_PER_PMD > 1) {
17678 + for (i = 0; i < USER_PTRS_PER_PGD; ++i) {
17679 + pmd_t *pmd = (void *)__va(pgd_val(pgd[i])-1);
17680 + kmem_cache_free(pmd_cache, pmd);
17683 + if (!HAVE_SHARED_KERNEL_PMD) {
17684 + unsigned long flags;
17685 + spin_lock_irqsave(&pgd_lock, flags);
17686 + pgd_list_del(pgd);
17687 + spin_unlock_irqrestore(&pgd_lock, flags);
17689 + for (i = USER_PTRS_PER_PGD; i < PTRS_PER_PGD; i++) {
17690 + pmd_t *pmd = (void *)__va(pgd_val(pgd[i])-1);
17691 + make_lowmem_page_writable(
17692 + pmd, XENFEAT_writable_page_tables);
17693 + memset(pmd, 0, PTRS_PER_PMD*sizeof(pmd_t));
17694 + kmem_cache_free(pmd_cache, pmd);
17697 + if (!xen_feature(XENFEAT_pae_pgdir_above_4gb))
17698 + xen_destroy_contiguous_region(
17699 + (unsigned long)pgd, 0);
17703 + /* in the non-PAE case, free_pgtables() clears user pgd entries */
17704 + kmem_cache_free(pgd_cache, pgd);
17707 +void make_lowmem_page_readonly(void *va, unsigned int feature)
17712 + if (xen_feature(feature))
17715 + pte = virt_to_ptep(va);
17716 + rc = HYPERVISOR_update_va_mapping(
17717 + (unsigned long)va, pte_wrprotect(*pte), 0);
17721 +void make_lowmem_page_writable(void *va, unsigned int feature)
17726 + if (xen_feature(feature))
17729 + pte = virt_to_ptep(va);
17730 + rc = HYPERVISOR_update_va_mapping(
17731 + (unsigned long)va, pte_mkwrite(*pte), 0);
17735 +void make_page_readonly(void *va, unsigned int feature)
17740 + if (xen_feature(feature))
17743 + pte = virt_to_ptep(va);
17744 + rc = HYPERVISOR_update_va_mapping(
17745 + (unsigned long)va, pte_wrprotect(*pte), 0);
17746 + if (rc) /* fallback? */
17747 + xen_l1_entry_update(pte, pte_wrprotect(*pte));
17748 + if ((unsigned long)va >= (unsigned long)high_memory) {
17749 + unsigned long pfn = pte_pfn(*pte);
17750 +#ifdef CONFIG_HIGHMEM
17751 + if (pfn >= highstart_pfn)
17752 + kmap_flush_unused(); /* flush stale writable kmaps */
17755 + make_lowmem_page_readonly(
17756 + phys_to_virt(pfn << PAGE_SHIFT), feature);
17760 +void make_page_writable(void *va, unsigned int feature)
17765 + if (xen_feature(feature))
17768 + pte = virt_to_ptep(va);
17769 + rc = HYPERVISOR_update_va_mapping(
17770 + (unsigned long)va, pte_mkwrite(*pte), 0);
17771 + if (rc) /* fallback? */
17772 + xen_l1_entry_update(pte, pte_mkwrite(*pte));
17773 + if ((unsigned long)va >= (unsigned long)high_memory) {
17774 + unsigned long pfn = pte_pfn(*pte);
17775 +#ifdef CONFIG_HIGHMEM
17776 + if (pfn < highstart_pfn)
17778 + make_lowmem_page_writable(
17779 + phys_to_virt(pfn << PAGE_SHIFT), feature);
17783 +void make_pages_readonly(void *va, unsigned int nr, unsigned int feature)
17785 + if (xen_feature(feature))
17788 + while (nr-- != 0) {
17789 + make_page_readonly(va, feature);
17790 + va = (void *)((unsigned long)va + PAGE_SIZE);
17794 +void make_pages_writable(void *va, unsigned int nr, unsigned int feature)
17796 + if (xen_feature(feature))
17799 + while (nr-- != 0) {
17800 + make_page_writable(va, feature);
17801 + va = (void *)((unsigned long)va + PAGE_SIZE);
17805 +static void _pin_lock(struct mm_struct *mm, int lock) {
17807 + spin_lock(&mm->page_table_lock);
17808 +#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
17809 + /* While mm->page_table_lock protects us against insertions and
17810 + * removals of higher level page table pages, it doesn't protect
17811 + * against updates of pte-s. Such updates, however, require the
17812 + * pte pages to be in consistent state (unpinned+writable or
17813 + * pinned+readonly). The pinning and attribute changes, however
17814 + * cannot be done atomically, which is why such updates must be
17815 + * prevented from happening concurrently.
17816 + * Note that no pte lock can ever elsewhere be acquired nesting
17817 + * with an already acquired one in the same mm, or with the mm's
17818 + * page_table_lock already acquired, as that would break in the
17819 + * non-split case (where all these are actually resolving to the
17820 + * one page_table_lock). Thus acquiring all of them here is not
17821 + * going to result in dead locks, and the order of acquires
17822 + * doesn't matter.
17825 + pgd_t *pgd = mm->pgd;
17828 + for (g = 0; g < USER_PTRS_PER_PGD; g++, pgd++) {
17832 + if (pgd_none(*pgd))
17834 + pud = pud_offset(pgd, 0);
17835 + for (u = 0; u < PTRS_PER_PUD; u++, pud++) {
17839 + if (pud_none(*pud))
17841 + pmd = pmd_offset(pud, 0);
17842 + for (m = 0; m < PTRS_PER_PMD; m++, pmd++) {
17845 + if (pmd_none(*pmd))
17847 + ptl = pte_lockptr(0, pmd);
17851 + spin_unlock(ptl);
17858 + spin_unlock(&mm->page_table_lock);
17860 +#define pin_lock(mm) _pin_lock(mm, 1)
17861 +#define pin_unlock(mm) _pin_lock(mm, 0)
17863 +#define PIN_BATCH 4
17864 +static DEFINE_PER_CPU(multicall_entry_t[PIN_BATCH], pb_mcl);
17866 +static inline unsigned int pgd_walk_set_prot(struct page *page, pgprot_t flags,
17867 + unsigned int cpu, unsigned seq)
17869 + unsigned long pfn = page_to_pfn(page);
17871 + if (PageHighMem(page)) {
17872 + if (pgprot_val(flags) & _PAGE_RW)
17873 + clear_bit(PG_pinned, &page->flags);
17875 + set_bit(PG_pinned, &page->flags);
17877 + MULTI_update_va_mapping(per_cpu(pb_mcl, cpu) + seq,
17878 + (unsigned long)__va(pfn << PAGE_SHIFT),
17879 + pfn_pte(pfn, flags), 0);
17880 + if (unlikely(++seq == PIN_BATCH)) {
17881 + if (unlikely(HYPERVISOR_multicall_check(per_cpu(pb_mcl, cpu),
17882 + PIN_BATCH, NULL)))
17891 +static void pgd_walk(pgd_t *pgd_base, pgprot_t flags)
17893 + pgd_t *pgd = pgd_base;
17897 + unsigned int cpu, seq;
17899 + if (xen_feature(XENFEAT_auto_translated_physmap))
17904 + for (g = 0, seq = 0; g < USER_PTRS_PER_PGD; g++, pgd++) {
17905 + if (pgd_none(*pgd))
17907 + pud = pud_offset(pgd, 0);
17908 + if (PTRS_PER_PUD > 1) /* not folded */
17909 + seq = pgd_walk_set_prot(virt_to_page(pud),flags,cpu,seq);
17910 + for (u = 0; u < PTRS_PER_PUD; u++, pud++) {
17911 + if (pud_none(*pud))
17913 + pmd = pmd_offset(pud, 0);
17914 + if (PTRS_PER_PMD > 1) /* not folded */
17915 + seq = pgd_walk_set_prot(virt_to_page(pmd),flags,cpu,seq);
17916 + for (m = 0; m < PTRS_PER_PMD; m++, pmd++) {
17917 + if (pmd_none(*pmd))
17919 + seq = pgd_walk_set_prot(pmd_page(*pmd),flags,cpu,seq);
17924 + if (likely(seq != 0)) {
17925 + MULTI_update_va_mapping(per_cpu(pb_mcl, cpu) + seq,
17926 + (unsigned long)pgd_base,
17927 + pfn_pte(virt_to_phys(pgd_base)>>PAGE_SHIFT, flags),
17929 + if (unlikely(HYPERVISOR_multicall_check(per_cpu(pb_mcl, cpu),
17932 + } else if(HYPERVISOR_update_va_mapping((unsigned long)pgd_base,
17933 + pfn_pte(virt_to_phys(pgd_base)>>PAGE_SHIFT, flags),
17940 +static void __pgd_pin(pgd_t *pgd)
17942 + pgd_walk(pgd, PAGE_KERNEL_RO);
17943 + kmap_flush_unused();
17944 + xen_pgd_pin(__pa(pgd));
17945 + set_bit(PG_pinned, &virt_to_page(pgd)->flags);
17948 +static void __pgd_unpin(pgd_t *pgd)
17950 + xen_pgd_unpin(__pa(pgd));
17951 + pgd_walk(pgd, PAGE_KERNEL);
17952 + clear_bit(PG_pinned, &virt_to_page(pgd)->flags);
17955 +static void pgd_test_and_unpin(pgd_t *pgd)
17957 + if (test_bit(PG_pinned, &virt_to_page(pgd)->flags))
17958 + __pgd_unpin(pgd);
17961 +void mm_pin(struct mm_struct *mm)
17963 + if (xen_feature(XENFEAT_writable_page_tables))
17966 + __pgd_pin(mm->pgd);
17970 +void mm_unpin(struct mm_struct *mm)
17972 + if (xen_feature(XENFEAT_writable_page_tables))
17975 + __pgd_unpin(mm->pgd);
17979 +void mm_pin_all(void)
17981 + struct page *page;
17982 + unsigned long flags;
17984 + if (xen_feature(XENFEAT_writable_page_tables))
17988 + * Allow uninterrupted access to the pgd_list. Also protects
17989 + * __pgd_pin() by disabling preemption.
17990 + * All other CPUs must be at a safe point (e.g., in stop_machine
17991 + * or offlined entirely).
17993 + spin_lock_irqsave(&pgd_lock, flags);
17994 + for (page = pgd_list; page; page = (struct page *)page->index) {
17995 + if (!test_bit(PG_pinned, &page->flags))
17996 + __pgd_pin((pgd_t *)page_address(page));
17998 + spin_unlock_irqrestore(&pgd_lock, flags);
18001 +void _arch_dup_mmap(struct mm_struct *mm)
18003 + if (!test_bit(PG_pinned, &virt_to_page(mm->pgd)->flags))
18007 +void _arch_exit_mmap(struct mm_struct *mm)
18009 + struct task_struct *tsk = current;
18014 + * We aggressively remove defunct pgd from cr3. We execute unmap_vmas()
18015 + * *much* faster this way, as no tlb flushes means bigger wrpt batches.
18017 + if (tsk->active_mm == mm) {
18018 + tsk->active_mm = &init_mm;
18019 + atomic_inc(&init_mm.mm_count);
18021 + switch_mm(mm, &init_mm, tsk);
18023 + atomic_dec(&mm->mm_count);
18024 + BUG_ON(atomic_read(&mm->mm_count) == 0);
18027 + task_unlock(tsk);
18029 + if (test_bit(PG_pinned, &virt_to_page(mm->pgd)->flags) &&
18030 + (atomic_read(&mm->mm_count) == 1) &&
18031 + !mm->context.has_foreign_mappings)
18034 Index: head-2008-11-25/arch/x86/oprofile/xenoprof.c
18035 ===================================================================
18036 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
18037 +++ head-2008-11-25/arch/x86/oprofile/xenoprof.c 2008-01-28 12:24:19.000000000 +0100
18040 + * @file xenoprof.c
18042 + * @remark Copyright 2002 OProfile authors
18043 + * @remark Read the file COPYING
18045 + * @author John Levon <levon@movementarian.org>
18047 + * Modified by Aravind Menon and Jose Renato Santos for Xen
18048 + * These modifications are:
18049 + * Copyright (C) 2005 Hewlett-Packard Co.
18051 + * x86-specific part
18052 + * Copyright (c) 2006 Isaku Yamahata <yamahata at valinux co jp>
18053 + * VA Linux Systems Japan K.K.
18056 +#include <linux/init.h>
18057 +#include <linux/oprofile.h>
18058 +#include <linux/sched.h>
18059 +#include <asm/pgtable.h>
18061 +#include <xen/driver_util.h>
18062 +#include <xen/interface/xen.h>
18063 +#include <xen/interface/xenoprof.h>
18064 +#include <xen/xenoprof.h>
18065 +#include "op_counter.h"
18067 +static unsigned int num_events = 0;
18069 +void __init xenoprof_arch_init_counter(struct xenoprof_init *init)
18071 + num_events = init->num_events;
18072 + /* just in case - make sure we do not overflow event list
18073 + (i.e. counter_config list) */
18074 + if (num_events > OP_MAX_COUNTER) {
18075 + num_events = OP_MAX_COUNTER;
18076 + init->num_events = num_events;
18080 +void xenoprof_arch_counter(void)
18083 + struct xenoprof_counter counter;
18085 + for (i=0; i<num_events; i++) {
18087 + counter.count = (uint64_t)counter_config[i].count;
18088 + counter.enabled = (uint32_t)counter_config[i].enabled;
18089 + counter.event = (uint32_t)counter_config[i].event;
18090 + counter.kernel = (uint32_t)counter_config[i].kernel;
18091 + counter.user = (uint32_t)counter_config[i].user;
18092 + counter.unit_mask = (uint64_t)counter_config[i].unit_mask;
18093 + WARN_ON(HYPERVISOR_xenoprof_op(XENOPROF_counter,
18098 +void xenoprof_arch_start(void)
18103 +void xenoprof_arch_stop(void)
18108 +void xenoprof_arch_unmap_shared_buffer(struct xenoprof_shared_buffer * sbuf)
18110 + if (sbuf->buffer) {
18111 + vunmap(sbuf->buffer);
18112 + sbuf->buffer = NULL;
18116 +int xenoprof_arch_map_shared_buffer(struct xenoprof_get_buffer * get_buffer,
18117 + struct xenoprof_shared_buffer * sbuf)
18120 + struct vm_struct *area;
18122 + sbuf->buffer = NULL;
18123 + if ( (ret = HYPERVISOR_xenoprof_op(XENOPROF_get_buffer, get_buffer)) )
18126 + npages = (get_buffer->bufsize * get_buffer->nbuf - 1) / PAGE_SIZE + 1;
18128 + area = alloc_vm_area(npages * PAGE_SIZE);
18129 + if (area == NULL)
18132 + if ( (ret = direct_kernel_remap_pfn_range(
18133 + (unsigned long)area->addr,
18134 + get_buffer->buf_gmaddr >> PAGE_SHIFT,
18135 + npages * PAGE_SIZE, __pgprot(_KERNPG_TABLE),
18137 + vunmap(area->addr);
18141 + sbuf->buffer = area->addr;
18145 +int xenoprof_arch_set_passive(struct xenoprof_passive * pdomain,
18146 + struct xenoprof_shared_buffer * sbuf)
18150 + struct vm_struct *area;
18151 + pgprot_t prot = __pgprot(_KERNPG_TABLE);
18153 + sbuf->buffer = NULL;
18154 + ret = HYPERVISOR_xenoprof_op(XENOPROF_set_passive, pdomain);
18158 + npages = (pdomain->bufsize * pdomain->nbuf - 1) / PAGE_SIZE + 1;
18160 + area = alloc_vm_area(npages * PAGE_SIZE);
18161 + if (area == NULL) {
18166 + ret = direct_kernel_remap_pfn_range(
18167 + (unsigned long)area->addr,
18168 + pdomain->buf_gmaddr >> PAGE_SHIFT,
18169 + npages * PAGE_SIZE, prot, DOMID_SELF);
18171 + vunmap(area->addr);
18174 + sbuf->buffer = area->addr;
18180 +struct op_counter_config counter_config[OP_MAX_COUNTER];
18182 +int xenoprof_create_files(struct super_block * sb, struct dentry * root)
18186 + for (i = 0; i < num_events; ++i) {
18187 + struct dentry * dir;
18190 + snprintf(buf, 2, "%d", i);
18191 + dir = oprofilefs_mkdir(sb, root, buf);
18192 + oprofilefs_create_ulong(sb, dir, "enabled",
18193 + &counter_config[i].enabled);
18194 + oprofilefs_create_ulong(sb, dir, "event",
18195 + &counter_config[i].event);
18196 + oprofilefs_create_ulong(sb, dir, "count",
18197 + &counter_config[i].count);
18198 + oprofilefs_create_ulong(sb, dir, "unit_mask",
18199 + &counter_config[i].unit_mask);
18200 + oprofilefs_create_ulong(sb, dir, "kernel",
18201 + &counter_config[i].kernel);
18202 + oprofilefs_create_ulong(sb, dir, "user",
18203 + &counter_config[i].user);
18209 +int __init oprofile_arch_init(struct oprofile_operations * ops)
18211 + return xenoprofile_init(ops);
18214 +void oprofile_arch_exit(void)
18216 + xenoprofile_exit();
18218 Index: head-2008-11-25/arch/x86/pci/irq-xen.c
18219 ===================================================================
18220 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
18221 +++ head-2008-11-25/arch/x86/pci/irq-xen.c 2008-03-06 08:54:32.000000000 +0100
18224 + * Low-Level PCI Support for PC -- Routing of Interrupts
18226 + * (c) 1999--2000 Martin Mares <mj@ucw.cz>
18229 +#include <linux/types.h>
18230 +#include <linux/kernel.h>
18231 +#include <linux/pci.h>
18232 +#include <linux/init.h>
18233 +#include <linux/slab.h>
18234 +#include <linux/interrupt.h>
18235 +#include <linux/dmi.h>
18236 +#include <asm/io.h>
18237 +#include <asm/smp.h>
18238 +#include <asm/io_apic.h>
18239 +#include <linux/irq.h>
18240 +#include <linux/acpi.h>
18244 +#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
18245 +#define PIRQ_VERSION 0x0100
18247 +static int broken_hp_bios_irq9;
18248 +static int acer_tm360_irqrouting;
18250 +static struct irq_routing_table *pirq_table;
18252 +static int pirq_enable_irq(struct pci_dev *dev);
18255 + * Never use: 0, 1, 2 (timer, keyboard, and cascade)
18256 + * Avoid using: 13, 14 and 15 (FP error and IDE).
18257 + * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
18259 +unsigned int pcibios_irq_mask = 0xfff8;
18261 +static int pirq_penalty[16] = {
18262 + 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
18263 + 0, 0, 0, 0, 1000, 100000, 100000, 100000
18266 +struct irq_router {
18268 + u16 vendor, device;
18269 + int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
18270 + int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
18273 +struct irq_router_handler {
18275 + int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
18278 +int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
18279 +void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
18282 + * Check passed address for the PCI IRQ Routing Table signature
18283 + * and perform checksum verification.
18286 +static inline struct irq_routing_table * pirq_check_routing_table(u8 *addr)
18288 + struct irq_routing_table *rt;
18292 + rt = (struct irq_routing_table *) addr;
18293 + if (rt->signature != PIRQ_SIGNATURE ||
18294 + rt->version != PIRQ_VERSION ||
18296 + rt->size < sizeof(struct irq_routing_table))
18299 + for (i=0; i < rt->size; i++)
18302 + DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", rt);
18311 + * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
18314 +static struct irq_routing_table * __init pirq_find_routing_table(void)
18317 + struct irq_routing_table *rt;
18320 + if (!is_initial_xendomain())
18323 + if (pirq_table_addr) {
18324 + rt = pirq_check_routing_table((u8 *) isa_bus_to_virt(pirq_table_addr));
18327 + printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
18329 + for(addr = (u8 *) isa_bus_to_virt(0xf0000); addr < (u8 *) isa_bus_to_virt(0x100000); addr += 16) {
18330 + rt = pirq_check_routing_table(addr);
18338 + * If we have a IRQ routing table, use it to search for peer host
18339 + * bridges. It's a gross hack, but since there are no other known
18340 + * ways how to get a list of buses, we have to go this way.
18343 +static void __init pirq_peer_trick(void)
18345 + struct irq_routing_table *rt = pirq_table;
18348 + struct irq_info *e;
18350 + memset(busmap, 0, sizeof(busmap));
18351 + for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
18352 + e = &rt->slots[i];
18356 + DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
18357 + for(j=0; j<4; j++)
18358 + DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
18362 + busmap[e->bus] = 1;
18364 + for(i = 1; i < 256; i++) {
18365 + if (!busmap[i] || pci_find_bus(0, i))
18367 + if (pci_scan_bus(i, &pci_root_ops, NULL))
18368 + printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
18370 + pcibios_last_bus = -1;
18374 + * Code for querying and setting of IRQ routes on various interrupt routers.
18377 +void eisa_set_level_irq(unsigned int irq)
18379 + unsigned char mask = 1 << (irq & 7);
18380 + unsigned int port = 0x4d0 + (irq >> 3);
18381 + unsigned char val;
18382 + static u16 eisa_irq_mask;
18384 + if (irq >= 16 || (1 << irq) & eisa_irq_mask)
18387 + eisa_irq_mask |= (1 << irq);
18388 + printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
18390 + if (!(val & mask)) {
18391 + DBG(KERN_DEBUG " -> edge");
18392 + outb(val | mask, port);
18397 + * Common IRQ routing practice: nybbles in config space,
18398 + * offset by some magic constant.
18400 +static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
18403 + unsigned reg = offset + (nr >> 1);
18405 + pci_read_config_byte(router, reg, &x);
18406 + return (nr & 1) ? (x >> 4) : (x & 0xf);
18409 +static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
18412 + unsigned reg = offset + (nr >> 1);
18414 + pci_read_config_byte(router, reg, &x);
18415 + x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
18416 + pci_write_config_byte(router, reg, x);
18420 + * ALI pirq entries are damn ugly, and completely undocumented.
18421 + * This has been figured out from pirq tables, and it's not a pretty
18424 +static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18426 + static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
18428 + return irqmap[read_config_nybble(router, 0x48, pirq-1)];
18431 +static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18433 + static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
18434 + unsigned int val = irqmap[irq];
18437 + write_config_nybble(router, 0x48, pirq-1, val);
18444 + * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
18445 + * just a pointer to the config space.
18447 +static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18451 + pci_read_config_byte(router, pirq, &x);
18452 + return (x < 16) ? x : 0;
18455 +static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18457 + pci_write_config_byte(router, pirq, irq);
18462 + * The VIA pirq rules are nibble-based, like ALI,
18463 + * but without the ugly irq number munging.
18464 + * However, PIRQD is in the upper instead of lower 4 bits.
18466 +static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18468 + return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
18471 +static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18473 + write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
18478 + * The VIA pirq rules are nibble-based, like ALI,
18479 + * but without the ugly irq number munging.
18480 + * However, for 82C586, nibble map is different .
18482 +static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18484 + static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
18485 + return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
18488 +static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18490 + static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
18491 + write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
18496 + * ITE 8330G pirq rules are nibble-based
18497 + * FIXME: pirqmap may be { 1, 0, 3, 2 },
18498 + * 2+3 are both mapped to irq 9 on my system
18500 +static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18502 + static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
18503 + return read_config_nybble(router,0x43, pirqmap[pirq-1]);
18506 +static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18508 + static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
18509 + write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
18514 + * OPTI: high four bits are nibble pointer..
18515 + * I wonder what the low bits do?
18517 +static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18519 + return read_config_nybble(router, 0xb8, pirq >> 4);
18522 +static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18524 + write_config_nybble(router, 0xb8, pirq >> 4, irq);
18529 + * Cyrix: nibble offset 0x5C
18530 + * 0x5C bits 7:4 is INTB bits 3:0 is INTA
18531 + * 0x5D bits 7:4 is INTD bits 3:0 is INTC
18533 +static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18535 + return read_config_nybble(router, 0x5C, (pirq-1)^1);
18538 +static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18540 + write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
18545 + * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
18546 + * We have to deal with the following issues here:
18547 + * - vendors have different ideas about the meaning of link values
18548 + * - some onboard devices (integrated in the chipset) have special
18549 + * links and are thus routed differently (i.e. not via PCI INTA-INTD)
18550 + * - different revision of the router have a different layout for
18551 + * the routing registers, particularly for the onchip devices
18553 + * For all routing registers the common thing is we have one byte
18554 + * per routeable link which is defined as:
18555 + * bit 7 IRQ mapping enabled (0) or disabled (1)
18556 + * bits [6:4] reserved (sometimes used for onchip devices)
18557 + * bits [3:0] IRQ to map to
18558 + * allowed: 3-7, 9-12, 14-15
18559 + * reserved: 0, 1, 2, 8, 13
18561 + * The config-space registers located at 0x41/0x42/0x43/0x44 are
18562 + * always used to route the normal PCI INT A/B/C/D respectively.
18563 + * Apparently there are systems implementing PCI routing table using
18564 + * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
18565 + * We try our best to handle both link mappings.
18567 + * Currently (2003-05-21) it appears most SiS chipsets follow the
18568 + * definition of routing registers from the SiS-5595 southbridge.
18569 + * According to the SiS 5595 datasheets the revision id's of the
18570 + * router (ISA-bridge) should be 0x01 or 0xb0.
18572 + * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
18573 + * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
18574 + * They seem to work with the current routing code. However there is
18575 + * some concern because of the two USB-OHCI HCs (original SiS 5595
18576 + * had only one). YMMV.
18578 + * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
18581 + * bits [6:5] must be written 01
18582 + * bit 4 channel-select primary (0), secondary (1)
18585 + * bit 6 OHCI function disabled (0), enabled (1)
18587 + * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
18589 + * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
18591 + * We support USBIRQ (in addition to INTA-INTD) and keep the
18592 + * IDE, ACPI and DAQ routing untouched as set by the BIOS.
18594 + * Currently the only reported exception is the new SiS 65x chipset
18595 + * which includes the SiS 69x southbridge. Here we have the 85C503
18596 + * router revision 0x04 and there are changes in the register layout
18597 + * mostly related to the different USB HCs with USB 2.0 support.
18599 + * Onchip routing for router rev-id 0x04 (try-and-error observation)
18601 + * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
18602 + * bit 6-4 are probably unused, not like 5595
18605 +#define PIRQ_SIS_IRQ_MASK 0x0f
18606 +#define PIRQ_SIS_IRQ_DISABLE 0x80
18607 +#define PIRQ_SIS_USB_ENABLE 0x40
18609 +static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18615 + if (reg >= 0x01 && reg <= 0x04)
18617 + pci_read_config_byte(router, reg, &x);
18618 + return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
18621 +static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18627 + if (reg >= 0x01 && reg <= 0x04)
18629 + pci_read_config_byte(router, reg, &x);
18630 + x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
18631 + x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
18632 + pci_write_config_byte(router, reg, x);
18638 + * VLSI: nibble offset 0x74 - educated guess due to routing table and
18639 + * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
18640 + * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
18641 + * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
18642 + * for the busbridge to the docking station.
18645 +static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18648 + printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
18651 + return read_config_nybble(router, 0x74, pirq-1);
18654 +static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18657 + printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
18660 + write_config_nybble(router, 0x74, pirq-1, irq);
18665 + * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
18666 + * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
18667 + * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
18668 + * register is a straight binary coding of desired PIC IRQ (low nibble).
18670 + * The 'link' value in the PIRQ table is already in the correct format
18671 + * for the Index register. There are some special index values:
18672 + * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
18673 + * and 0x03 for SMBus.
18675 +static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18677 + outb_p(pirq, 0xc00);
18678 + return inb(0xc01) & 0xf;
18681 +static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18683 + outb_p(pirq, 0xc00);
18684 + outb_p(irq, 0xc01);
18688 +/* Support for AMD756 PCI IRQ Routing
18689 + * Jhon H. Caicedo <jhcaiced@osso.org.co>
18690 + * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
18691 + * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
18692 + * The AMD756 pirq rules are nibble-based
18693 + * offset 0x56 0-3 PIRQA 4-7 PIRQB
18694 + * offset 0x57 0-3 PIRQC 4-7 PIRQD
18696 +static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
18702 + irq = read_config_nybble(router, 0x56, pirq - 1);
18704 + printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
18705 + dev->vendor, dev->device, pirq, irq);
18709 +static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18711 + printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
18712 + dev->vendor, dev->device, pirq, irq);
18715 + write_config_nybble(router, 0x56, pirq - 1, irq);
18720 +#ifdef CONFIG_PCI_BIOS
18722 +static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
18724 + struct pci_dev *bridge;
18725 + int pin = pci_get_interrupt_pin(dev, &bridge);
18726 + return pcibios_set_irq_routing(bridge, pin, irq);
18731 +static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18733 + static struct pci_device_id __initdata pirq_440gx[] = {
18734 + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
18735 + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
18739 + /* 440GX has a proprietary PIRQ router -- don't use it */
18740 + if (pci_dev_present(pirq_440gx))
18745 + case PCI_DEVICE_ID_INTEL_82371FB_0:
18746 + case PCI_DEVICE_ID_INTEL_82371SB_0:
18747 + case PCI_DEVICE_ID_INTEL_82371AB_0:
18748 + case PCI_DEVICE_ID_INTEL_82371MX:
18749 + case PCI_DEVICE_ID_INTEL_82443MX_0:
18750 + case PCI_DEVICE_ID_INTEL_82801AA_0:
18751 + case PCI_DEVICE_ID_INTEL_82801AB_0:
18752 + case PCI_DEVICE_ID_INTEL_82801BA_0:
18753 + case PCI_DEVICE_ID_INTEL_82801BA_10:
18754 + case PCI_DEVICE_ID_INTEL_82801CA_0:
18755 + case PCI_DEVICE_ID_INTEL_82801CA_12:
18756 + case PCI_DEVICE_ID_INTEL_82801DB_0:
18757 + case PCI_DEVICE_ID_INTEL_82801E_0:
18758 + case PCI_DEVICE_ID_INTEL_82801EB_0:
18759 + case PCI_DEVICE_ID_INTEL_ESB_1:
18760 + case PCI_DEVICE_ID_INTEL_ICH6_0:
18761 + case PCI_DEVICE_ID_INTEL_ICH6_1:
18762 + case PCI_DEVICE_ID_INTEL_ICH7_0:
18763 + case PCI_DEVICE_ID_INTEL_ICH7_1:
18764 + case PCI_DEVICE_ID_INTEL_ICH7_30:
18765 + case PCI_DEVICE_ID_INTEL_ICH7_31:
18766 + case PCI_DEVICE_ID_INTEL_ESB2_0:
18767 + case PCI_DEVICE_ID_INTEL_ICH8_0:
18768 + case PCI_DEVICE_ID_INTEL_ICH8_1:
18769 + case PCI_DEVICE_ID_INTEL_ICH8_2:
18770 + case PCI_DEVICE_ID_INTEL_ICH8_3:
18771 + case PCI_DEVICE_ID_INTEL_ICH8_4:
18772 + case PCI_DEVICE_ID_INTEL_ICH9_0:
18773 + case PCI_DEVICE_ID_INTEL_ICH9_1:
18774 + case PCI_DEVICE_ID_INTEL_ICH9_2:
18775 + case PCI_DEVICE_ID_INTEL_ICH9_3:
18776 + case PCI_DEVICE_ID_INTEL_ICH9_4:
18777 + case PCI_DEVICE_ID_INTEL_ICH9_5:
18778 + r->name = "PIIX/ICH";
18779 + r->get = pirq_piix_get;
18780 + r->set = pirq_piix_set;
18786 +static __init int via_router_probe(struct irq_router *r,
18787 + struct pci_dev *router, u16 device)
18789 + /* FIXME: We should move some of the quirk fixup stuff here */
18792 + * work arounds for some buggy BIOSes
18794 + if (device == PCI_DEVICE_ID_VIA_82C586_0) {
18795 + switch(router->device) {
18796 + case PCI_DEVICE_ID_VIA_82C686:
18798 + * Asus k7m bios wrongly reports 82C686A
18799 + * as 586-compatible
18801 + device = PCI_DEVICE_ID_VIA_82C686;
18803 + case PCI_DEVICE_ID_VIA_8235:
18805 + * Asus a7v-x bios wrongly reports 8235
18806 + * as 586-compatible
18808 + device = PCI_DEVICE_ID_VIA_8235;
18814 + case PCI_DEVICE_ID_VIA_82C586_0:
18816 + r->get = pirq_via586_get;
18817 + r->set = pirq_via586_set;
18819 + case PCI_DEVICE_ID_VIA_82C596:
18820 + case PCI_DEVICE_ID_VIA_82C686:
18821 + case PCI_DEVICE_ID_VIA_8231:
18822 + case PCI_DEVICE_ID_VIA_8233A:
18823 + case PCI_DEVICE_ID_VIA_8235:
18824 + case PCI_DEVICE_ID_VIA_8237:
18825 + /* FIXME: add new ones for 8233/5 */
18827 + r->get = pirq_via_get;
18828 + r->set = pirq_via_set;
18834 +static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18838 + case PCI_DEVICE_ID_VLSI_82C534:
18839 + r->name = "VLSI 82C534";
18840 + r->get = pirq_vlsi_get;
18841 + r->set = pirq_vlsi_set;
18848 +static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18852 + case PCI_DEVICE_ID_SERVERWORKS_OSB4:
18853 + case PCI_DEVICE_ID_SERVERWORKS_CSB5:
18854 + r->name = "ServerWorks";
18855 + r->get = pirq_serverworks_get;
18856 + r->set = pirq_serverworks_set;
18862 +static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18864 + if (device != PCI_DEVICE_ID_SI_503)
18868 + r->get = pirq_sis_get;
18869 + r->set = pirq_sis_set;
18873 +static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18877 + case PCI_DEVICE_ID_CYRIX_5520:
18878 + r->name = "NatSemi";
18879 + r->get = pirq_cyrix_get;
18880 + r->set = pirq_cyrix_set;
18886 +static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18890 + case PCI_DEVICE_ID_OPTI_82C700:
18891 + r->name = "OPTI";
18892 + r->get = pirq_opti_get;
18893 + r->set = pirq_opti_set;
18899 +static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18903 + case PCI_DEVICE_ID_ITE_IT8330G_0:
18905 + r->get = pirq_ite_get;
18906 + r->set = pirq_ite_set;
18912 +static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18916 + case PCI_DEVICE_ID_AL_M1533:
18917 + case PCI_DEVICE_ID_AL_M1563:
18918 + printk(KERN_DEBUG "PCI: Using ALI IRQ Router\n");
18920 + r->get = pirq_ali_get;
18921 + r->set = pirq_ali_set;
18927 +static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
18931 + case PCI_DEVICE_ID_AMD_VIPER_740B:
18932 + r->name = "AMD756";
18934 + case PCI_DEVICE_ID_AMD_VIPER_7413:
18935 + r->name = "AMD766";
18937 + case PCI_DEVICE_ID_AMD_VIPER_7443:
18938 + r->name = "AMD768";
18943 + r->get = pirq_amd756_get;
18944 + r->set = pirq_amd756_set;
18948 +static __initdata struct irq_router_handler pirq_routers[] = {
18949 + { PCI_VENDOR_ID_INTEL, intel_router_probe },
18950 + { PCI_VENDOR_ID_AL, ali_router_probe },
18951 + { PCI_VENDOR_ID_ITE, ite_router_probe },
18952 + { PCI_VENDOR_ID_VIA, via_router_probe },
18953 + { PCI_VENDOR_ID_OPTI, opti_router_probe },
18954 + { PCI_VENDOR_ID_SI, sis_router_probe },
18955 + { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
18956 + { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
18957 + { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
18958 + { PCI_VENDOR_ID_AMD, amd_router_probe },
18959 + /* Someone with docs needs to add the ATI Radeon IGP */
18962 +static struct irq_router pirq_router;
18963 +static struct pci_dev *pirq_router_dev;
18967 + * FIXME: should we have an option to say "generic for
18971 +static void __init pirq_find_router(struct irq_router *r)
18973 + struct irq_routing_table *rt = pirq_table;
18974 + struct irq_router_handler *h;
18976 +#ifdef CONFIG_PCI_BIOS
18977 + if (!rt->signature) {
18978 + printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
18979 + r->set = pirq_bios_set;
18980 + r->name = "BIOS";
18985 + /* Default unless a driver reloads it */
18986 + r->name = "default";
18990 + DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for %04x:%04x\n",
18991 + rt->rtr_vendor, rt->rtr_device);
18993 + pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
18994 + if (!pirq_router_dev) {
18995 + DBG(KERN_DEBUG "PCI: Interrupt router not found at "
18996 + "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
19000 + for( h = pirq_routers; h->vendor; h++) {
19001 + /* First look for a router match */
19002 + if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
19004 + /* Fall back to a device match */
19005 + if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
19008 + printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
19009 + pirq_router.name,
19010 + pirq_router_dev->vendor,
19011 + pirq_router_dev->device,
19012 + pci_name(pirq_router_dev));
19015 +static struct irq_info *pirq_get_info(struct pci_dev *dev)
19017 + struct irq_routing_table *rt = pirq_table;
19018 + int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
19019 + struct irq_info *info;
19021 + for (info = rt->slots; entries--; info++)
19022 + if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
19027 +static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
19030 + struct irq_info *info;
19031 + int i, pirq, newirq;
19034 + struct irq_router *r = &pirq_router;
19035 + struct pci_dev *dev2 = NULL;
19036 + char *msg = NULL;
19038 + /* Find IRQ pin */
19039 + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
19041 + DBG(KERN_DEBUG " -> no interrupt pin\n");
19046 + /* Find IRQ routing entry */
19051 + DBG(KERN_DEBUG "IRQ for %s[%c]", pci_name(dev), 'A' + pin);
19052 + info = pirq_get_info(dev);
19054 + DBG(" -> not found in routing table\n" KERN_DEBUG);
19057 + pirq = info->irq[pin].link;
19058 + mask = info->irq[pin].bitmap;
19060 + DBG(" -> not routed\n" KERN_DEBUG);
19063 + DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
19064 + mask &= pcibios_irq_mask;
19066 + /* Work around broken HP Pavilion Notebooks which assign USB to
19067 + IRQ 9 even though it is actually wired to IRQ 11 */
19069 + if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
19071 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
19072 + r->set(pirq_router_dev, dev, pirq, 11);
19075 + /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
19076 + if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
19079 + dev->irq = r->get(pirq_router_dev, dev, pirq);
19080 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
19084 + * Find the best IRQ to assign: use the one
19085 + * reported by the device if possible.
19087 + newirq = dev->irq;
19088 + if (newirq && !((1 << newirq) & mask)) {
19089 + if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
19090 + else printk("\n" KERN_WARNING
19091 + "PCI: IRQ %i for device %s doesn't match PIRQ mask "
19092 + "- try pci=usepirqmask\n" KERN_DEBUG, newirq,
19095 + if (!newirq && assign) {
19096 + for (i = 0; i < 16; i++) {
19097 + if (!(mask & (1 << i)))
19099 + if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, IRQF_SHARED))
19103 + DBG(" -> newirq=%d", newirq);
19105 + /* Check if it is hardcoded */
19106 + if ((pirq & 0xf0) == 0xf0) {
19107 + irq = pirq & 0xf;
19108 + DBG(" -> hardcoded IRQ %d\n", irq);
19109 + msg = "Hardcoded";
19110 + } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
19111 + ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
19112 + DBG(" -> got IRQ %d\n", irq);
19114 + eisa_set_level_irq(irq);
19115 + } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
19116 + DBG(" -> assigning IRQ %d", newirq);
19117 + if (r->set(pirq_router_dev, dev, pirq, newirq)) {
19118 + eisa_set_level_irq(newirq);
19119 + DBG(" ... OK\n");
19120 + msg = "Assigned";
19126 + DBG(" ... failed\n");
19127 + if (newirq && mask == (1 << newirq)) {
19133 + printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
19135 + /* Update IRQ for all devices with the same pirq value */
19136 + while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
19137 + pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
19141 + info = pirq_get_info(dev2);
19144 + if (info->irq[pin].link == pirq) {
19145 + /* We refuse to override the dev->irq information. Give a warning! */
19146 + if ( dev2->irq && dev2->irq != irq && \
19147 + (!(pci_probe & PCI_USE_PIRQ_MASK) || \
19148 + ((1 << dev2->irq) & mask)) ) {
19149 +#ifndef CONFIG_PCI_MSI
19150 + printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
19151 + pci_name(dev2), dev2->irq, irq);
19156 + pirq_penalty[irq]++;
19158 + printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
19164 +static void __init pcibios_fixup_irqs(void)
19166 + struct pci_dev *dev = NULL;
19169 + DBG(KERN_DEBUG "PCI: IRQ fixup\n");
19170 + while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
19172 + * If the BIOS has set an out of range IRQ number, just ignore it.
19173 + * Also keep track of which IRQ's are already in use.
19175 + if (dev->irq >= 16) {
19176 + DBG(KERN_DEBUG "%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
19179 + /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
19180 + if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
19181 + pirq_penalty[dev->irq] = 0;
19182 + pirq_penalty[dev->irq]++;
19186 + while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
19187 + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
19188 +#ifdef CONFIG_X86_IO_APIC
19190 + * Recalculate IRQ numbers if we use the I/O APIC.
19192 + if (io_apic_assign_pci_irqs)
19197 + pin--; /* interrupt pins are numbered starting from 1 */
19198 + irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
19200 + * Busses behind bridges are typically not listed in the MP-table.
19201 + * In this case we have to look up the IRQ based on the parent bus,
19202 + * parent slot, and pin number. The SMP code detects such bridged
19203 + * busses itself so we should get into this branch reliably.
19205 + if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
19206 + struct pci_dev * bridge = dev->bus->self;
19208 + pin = (pin + PCI_SLOT(dev->devfn)) % 4;
19209 + irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
19210 + PCI_SLOT(bridge->devfn), pin);
19212 + printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
19213 + pci_name(bridge), 'A' + pin, irq);
19216 + if (use_pci_vector() &&
19217 + !platform_legacy_irq(irq))
19218 + irq = IO_APIC_VECTOR(irq);
19220 + printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
19221 + pci_name(dev), 'A' + pin, irq);
19228 + * Still no IRQ? Try to lookup one...
19230 + if (pin && !dev->irq)
19231 + pcibios_lookup_irq(dev, 0);
19236 + * Work around broken HP Pavilion Notebooks which assign USB to
19237 + * IRQ 9 even though it is actually wired to IRQ 11
19239 +static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
19241 + if (!broken_hp_bios_irq9) {
19242 + broken_hp_bios_irq9 = 1;
19243 + printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
19249 + * Work around broken Acer TravelMate 360 Notebooks which assign
19250 + * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
19252 +static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
19254 + if (!acer_tm360_irqrouting) {
19255 + acer_tm360_irqrouting = 1;
19256 + printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
19261 +static struct dmi_system_id __initdata pciirq_dmi_table[] = {
19263 + .callback = fix_broken_hp_bios_irq9,
19264 + .ident = "HP Pavilion N5400 Series Laptop",
19266 + DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
19267 + DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
19268 + DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
19269 + DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
19273 + .callback = fix_acer_tm360_irqrouting,
19274 + .ident = "Acer TravelMate 36x Laptop",
19276 + DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
19277 + DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
19283 +static int __init pcibios_irq_init(void)
19285 + DBG(KERN_DEBUG "PCI: IRQ init\n");
19287 + if (pcibios_enable_irq || raw_pci_ops == NULL)
19290 + dmi_check_system(pciirq_dmi_table);
19292 + pirq_table = pirq_find_routing_table();
19294 +#ifdef CONFIG_PCI_BIOS
19295 + if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
19296 + pirq_table = pcibios_get_irq_routing_table();
19298 + if (pirq_table) {
19299 + pirq_peer_trick();
19300 + pirq_find_router(&pirq_router);
19301 + if (pirq_table->exclusive_irqs) {
19303 + for (i=0; i<16; i++)
19304 + if (!(pirq_table->exclusive_irqs & (1 << i)))
19305 + pirq_penalty[i] += 100;
19307 + /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
19308 + if (io_apic_assign_pci_irqs)
19309 + pirq_table = NULL;
19312 + pcibios_enable_irq = pirq_enable_irq;
19314 + pcibios_fixup_irqs();
19318 +subsys_initcall(pcibios_irq_init);
19321 +static void pirq_penalize_isa_irq(int irq, int active)
19324 + * If any ISAPnP device reports an IRQ in its list of possible
19325 + * IRQ's, we try to avoid assigning it to PCI devices.
19329 + pirq_penalty[irq] += 1000;
19331 + pirq_penalty[irq] += 100;
19335 +void pcibios_penalize_isa_irq(int irq, int active)
19337 +#ifdef CONFIG_ACPI
19339 + acpi_penalize_isa_irq(irq, active);
19342 + pirq_penalize_isa_irq(irq, active);
19345 +static int pirq_enable_irq(struct pci_dev *dev)
19348 + struct pci_dev *temp_dev;
19350 + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
19351 + if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
19354 + pin--; /* interrupt pins are numbered starting from 1 */
19356 + if (io_apic_assign_pci_irqs) {
19359 + irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
19361 + * Busses behind bridges are typically not listed in the MP-table.
19362 + * In this case we have to look up the IRQ based on the parent bus,
19363 + * parent slot, and pin number. The SMP code detects such bridged
19364 + * busses itself so we should get into this branch reliably.
19367 + while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
19368 + struct pci_dev * bridge = dev->bus->self;
19370 + pin = (pin + PCI_SLOT(dev->devfn)) % 4;
19371 + irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
19372 + PCI_SLOT(bridge->devfn), pin);
19374 + printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
19375 + pci_name(bridge), 'A' + pin, irq);
19380 +#ifdef CONFIG_PCI_MSI
19381 + if (!platform_legacy_irq(irq))
19382 + irq = IO_APIC_VECTOR(irq);
19384 + printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
19385 + pci_name(dev), 'A' + pin, irq);
19389 + msg = " Probably buggy MP table.";
19390 + } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
19393 + msg = " Please try using pci=biosirq.";
19395 + /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
19396 + if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
19399 + printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
19400 + 'A' + pin, pci_name(dev), msg);
19405 +int pci_vector_resources(int last, int nr_released)
19407 + int count = nr_released;
19410 + int offset = (last % 8);
19412 + while (next < FIRST_SYSTEM_VECTOR) {
19414 +#ifdef CONFIG_X86_64
19415 + if (next == IA32_SYSCALL_VECTOR)
19418 + if (next == SYSCALL_VECTOR)
19422 + if (next >= FIRST_SYSTEM_VECTOR) {
19424 + next = FIRST_DEVICE_VECTOR + offset;
19434 Index: head-2008-11-25/arch/x86/pci/pcifront.c
19435 ===================================================================
19436 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
19437 +++ head-2008-11-25/arch/x86/pci/pcifront.c 2007-06-12 13:12:49.000000000 +0200
19440 + * PCI Frontend Stub - puts some "dummy" functions in to the Linux x86 PCI core
19441 + * to support the Xen PCI Frontend's operation
19443 + * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
19445 +#include <linux/module.h>
19446 +#include <linux/init.h>
19447 +#include <linux/pci.h>
19448 +#include <asm/acpi.h>
19451 +static int pcifront_enable_irq(struct pci_dev *dev)
19454 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
19460 +extern u8 pci_cache_line_size;
19462 +static int __init pcifront_x86_stub_init(void)
19464 + struct cpuinfo_x86 *c = &boot_cpu_data;
19466 + /* Only install our method if we haven't found real hardware already */
19470 + printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
19472 + /* Copied from arch/i386/pci/common.c */
19473 + pci_cache_line_size = 32 >> 2;
19474 + if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
19475 + pci_cache_line_size = 64 >> 2; /* K7 & K8 */
19476 + else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
19477 + pci_cache_line_size = 128 >> 2; /* P4 */
19479 + /* On x86, we need to disable the normal IRQ routing table and
19480 + * just ask the backend
19482 + pcibios_enable_irq = pcifront_enable_irq;
19483 + pcibios_disable_irq = NULL;
19485 +#ifdef CONFIG_ACPI
19486 + /* Keep ACPI out of the picture */
19493 +arch_initcall(pcifront_x86_stub_init);
19494 Index: head-2008-11-25/arch/x86/ia32/ia32entry-xen.S
19495 ===================================================================
19496 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
19497 +++ head-2008-11-25/arch/x86/ia32/ia32entry-xen.S 2008-04-02 12:34:02.000000000 +0200
19500 + * Compatibility mode system call entry point for x86-64.
19502 + * Copyright 2000-2002 Andi Kleen, SuSE Labs.
19505 +#include <asm/dwarf2.h>
19506 +#include <asm/calling.h>
19507 +#include <asm/asm-offsets.h>
19508 +#include <asm/current.h>
19509 +#include <asm/errno.h>
19510 +#include <asm/ia32_unistd.h>
19511 +#include <asm/thread_info.h>
19512 +#include <asm/segment.h>
19513 +#include <asm/vsyscall32.h>
19514 +#include <asm/irqflags.h>
19515 +#include <linux/linkage.h>
19517 +#define IA32_NR_syscalls ((ia32_syscall_end - ia32_sys_call_table)/8)
19519 + .macro IA32_ARG_FIXUP noebp=0
19527 + movl %edx,%edx /* zero extension */
19530 + /* clobbers %eax */
19531 + .macro CLEAR_RREGS
19533 + movq %rax,R11(%rsp)
19534 + movq %rax,R10(%rsp)
19535 + movq %rax,R9(%rsp)
19536 + movq %rax,R8(%rsp)
19539 + .macro LOAD_ARGS32 offset
19540 + movl \offset(%rsp),%r11d
19541 + movl \offset+8(%rsp),%r10d
19542 + movl \offset+16(%rsp),%r9d
19543 + movl \offset+24(%rsp),%r8d
19544 + movl \offset+40(%rsp),%ecx
19545 + movl \offset+48(%rsp),%edx
19546 + movl \offset+56(%rsp),%esi
19547 + movl \offset+64(%rsp),%edi
19548 + movl \offset+72(%rsp),%eax
19551 + .macro CFI_STARTPROC32 simple
19552 + CFI_STARTPROC \simple
19555 + CFI_UNDEFINED r10
19556 + CFI_UNDEFINED r11
19557 + CFI_UNDEFINED r12
19558 + CFI_UNDEFINED r13
19559 + CFI_UNDEFINED r14
19560 + CFI_UNDEFINED r15
19564 + * 32bit SYSENTER instruction entry.
19567 + * %eax System call number.
19573 + * %ebp user stack
19578 + * This is purely a fast path. For anything complicated we use the int 0x80
19579 + * path below. Set up a complete hardware stack frame to share code
19580 + * with the int 0x80 path.
19582 +ENTRY(ia32_sysenter_target)
19583 + CFI_STARTPROC32 simple
19584 + CFI_DEF_CFA rsp,SS+8-RIP+16
19585 + /*CFI_REL_OFFSET ss,SS-RIP+16*/
19586 + CFI_REL_OFFSET rsp,RSP-RIP+16
19587 + /*CFI_REL_OFFSET rflags,EFLAGS-RIP+16*/
19588 + /*CFI_REL_OFFSET cs,CS-RIP+16*/
19589 + CFI_REL_OFFSET rip,RIP-RIP+16
19590 + CFI_REL_OFFSET r11,8
19591 + CFI_REL_OFFSET rcx,0
19592 + movq 8(%rsp),%r11
19595 + CFI_ADJUST_CFA_OFFSET -8
19597 + movl %ebp,%ebp /* zero extension */
19599 + movl $__USER32_DS,40(%rsp)
19600 + movq %rbp,32(%rsp)
19601 + movl $__USER32_CS,16(%rsp)
19602 + movl $VSYSCALL32_SYSEXIT,8(%rsp)
19606 + /* no need to do an access_ok check here because rbp has been
19607 + 32bit zero extended */
19608 +1: movl (%rbp),%r9d
19609 + .section __ex_table,"a"
19610 + .quad 1b,ia32_badarg
19612 + GET_THREAD_INFO(%r10)
19613 + orl $TS_COMPAT,threadinfo_status(%r10)
19614 + testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP),threadinfo_flags(%r10)
19615 + jnz sysenter_tracesys
19617 + cmpl $(IA32_NR_syscalls-1),%eax
19620 + call *ia32_sys_call_table(,%rax,8)
19621 + movq %rax,RAX-ARGOFFSET(%rsp)
19622 + jmp int_ret_from_sys_call
19624 +sysenter_tracesys:
19627 + movq $-ENOSYS,RAX(%rsp) /* really needed? */
19628 + movq %rsp,%rdi /* &pt_regs -> arg1 */
19629 + call syscall_trace_enter
19630 + LOAD_ARGS32 ARGOFFSET /* reload args from stack in case ptrace changed it */
19633 + /* no need to do an access_ok check here because rbp has been
19634 + 32bit zero extended */
19635 +1: movl (%rbp),%r9d
19636 + .section __ex_table,"a"
19637 + .quad 1b,ia32_badarg
19639 + jmp sysenter_do_call
19641 +ENDPROC(ia32_sysenter_target)
19644 + * 32bit SYSCALL instruction entry.
19647 + * %eax System call number.
19649 + * %ecx return EIP
19653 + * %ebp Arg2 [note: not saved in the stack frame, should not be touched]
19654 + * %esp user stack
19659 + * This is purely a fast path. For anything complicated we use the int 0x80
19660 + * path below. Set up a complete hardware stack frame to share code
19661 + * with the int 0x80 path.
19663 +ENTRY(ia32_cstar_target)
19664 + CFI_STARTPROC32 simple
19665 + CFI_DEF_CFA rsp,SS+8-RIP+16
19666 + /*CFI_REL_OFFSET ss,SS-RIP+16*/
19667 + CFI_REL_OFFSET rsp,RSP-RIP+16
19668 + /*CFI_REL_OFFSET rflags,EFLAGS-RIP+16*/
19669 + /*CFI_REL_OFFSET cs,CS-RIP+16*/
19670 + CFI_REL_OFFSET rip,RIP-RIP+16
19671 + movl %eax,%eax /* zero extension */
19672 + movl RSP-RIP+16(%rsp),%r8d
19674 + movq %rax,ORIG_RAX-ARGOFFSET(%rsp)
19675 + movq %rbp,RCX-ARGOFFSET(%rsp) /* this lies slightly to ptrace */
19677 + movl $__USER32_CS,CS-ARGOFFSET(%rsp)
19678 + movl $__USER32_DS,SS-ARGOFFSET(%rsp)
19679 + /* no need to do an access_ok check here because r8 has been
19680 + 32bit zero extended */
19681 + /* hardware stack frame is complete now */
19682 +1: movl (%r8),%r9d
19683 + .section __ex_table,"a"
19684 + .quad 1b,ia32_badarg
19686 + GET_THREAD_INFO(%r10)
19687 + orl $TS_COMPAT,threadinfo_status(%r10)
19688 + testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP),threadinfo_flags(%r10)
19689 + jnz cstar_tracesys
19691 + cmpl $IA32_NR_syscalls-1,%eax
19694 + call *ia32_sys_call_table(,%rax,8)
19695 + movq %rax,RAX-ARGOFFSET(%rsp)
19696 + jmp int_ret_from_sys_call
19701 + movq $-ENOSYS,RAX(%rsp) /* really needed? */
19702 + movq %rsp,%rdi /* &pt_regs -> arg1 */
19703 + call syscall_trace_enter
19704 + LOAD_ARGS32 ARGOFFSET /* reload args from stack in case ptrace changed it */
19706 + movl RSP-ARGOFFSET(%rsp), %r8d
19707 + /* no need to do an access_ok check here because r8 has been
19708 + 32bit zero extended */
19709 +1: movl (%r8),%r9d
19710 + .section __ex_table,"a"
19711 + .quad 1b,ia32_badarg
19713 + jmp cstar_do_call
19714 +END(ia32_cstar_target)
19717 + movq $-EFAULT,%rax
19722 + * Emulated IA32 system calls via int 0x80.
19725 + * %eax System call number.
19731 + * %ebp Arg6 [note: not saved in the stack frame, should not be touched]
19734 + * Uses the same stack frame as the x86-64 version.
19735 + * All registers except %eax must be saved (but ptrace may violate that)
19736 + * Arguments are zero extended. For system calls that want sign extension and
19737 + * take long arguments a wrapper is needed. Most calls can just be called
19739 + * Assumes it is only called from user space and entered with interrupts on.
19742 +ENTRY(ia32_syscall)
19743 + CFI_STARTPROC simple
19744 + CFI_DEF_CFA rsp,SS+8-RIP+16
19745 + /*CFI_REL_OFFSET ss,SS-RIP+16*/
19746 + CFI_REL_OFFSET rsp,RSP-RIP+16
19747 + /*CFI_REL_OFFSET rflags,EFLAGS-RIP+16*/
19748 + /*CFI_REL_OFFSET cs,CS-RIP+16*/
19749 + CFI_REL_OFFSET rip,RIP-RIP+16
19750 + CFI_REL_OFFSET r11,8
19751 + CFI_REL_OFFSET rcx,0
19752 + movq 8(%rsp),%r11
19755 + CFI_ADJUST_CFA_OFFSET -8
19760 + /* note the registers are not zero extended to the sf.
19761 + this could be a problem. */
19763 + GET_THREAD_INFO(%r10)
19764 + orl $TS_COMPAT,threadinfo_status(%r10)
19765 + testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP),threadinfo_flags(%r10)
19766 + jnz ia32_tracesys
19768 + cmpl $(IA32_NR_syscalls-1),%eax
19771 + call *ia32_sys_call_table(,%rax,8) # xxx: rip relative
19773 + movq %rax,RAX-ARGOFFSET(%rsp)
19774 + jmp int_ret_from_sys_call
19778 + movq $-ENOSYS,RAX(%rsp) /* really needed? */
19779 + movq %rsp,%rdi /* &pt_regs -> arg1 */
19780 + call syscall_trace_enter
19781 + LOAD_ARGS32 ARGOFFSET /* reload args from stack in case ptrace changed it */
19783 + jmp ia32_do_syscall
19787 + movq $0,ORIG_RAX-ARGOFFSET(%rsp)
19788 + movq $-ENOSYS,RAX-ARGOFFSET(%rsp)
19789 + jmp int_ret_from_sys_call
19792 + movq $-ENOSYS,%rax
19796 + .macro PTREGSCALL label, func, arg
19799 + leaq \func(%rip),%rax
19800 + leaq -ARGOFFSET+8(%rsp),\arg /* 8 for return address */
19801 + jmp ia32_ptregs_common
19806 + PTREGSCALL stub32_rt_sigreturn, sys32_rt_sigreturn, %rdi
19807 + PTREGSCALL stub32_sigreturn, sys32_sigreturn, %rdi
19808 + PTREGSCALL stub32_sigaltstack, sys32_sigaltstack, %rdx
19809 + PTREGSCALL stub32_sigsuspend, sys32_sigsuspend, %rcx
19810 + PTREGSCALL stub32_execve, sys32_execve, %rcx
19811 + PTREGSCALL stub32_fork, sys_fork, %rdi
19812 + PTREGSCALL stub32_clone, sys32_clone, %rdx
19813 + PTREGSCALL stub32_vfork, sys_vfork, %rdi
19814 + PTREGSCALL stub32_iopl, sys_iopl, %rsi
19815 + PTREGSCALL stub32_rt_sigsuspend, sys_rt_sigsuspend, %rdx
19817 +ENTRY(ia32_ptregs_common)
19820 + CFI_STARTPROC32 simple
19821 + CFI_DEF_CFA rsp,SS+8-ARGOFFSET
19822 + CFI_REL_OFFSET rax,RAX-ARGOFFSET
19823 + CFI_REL_OFFSET rcx,RCX-ARGOFFSET
19824 + CFI_REL_OFFSET rdx,RDX-ARGOFFSET
19825 + CFI_REL_OFFSET rsi,RSI-ARGOFFSET
19826 + CFI_REL_OFFSET rdi,RDI-ARGOFFSET
19827 + CFI_REL_OFFSET rip,RIP-ARGOFFSET
19828 +/* CFI_REL_OFFSET cs,CS-ARGOFFSET*/
19829 +/* CFI_REL_OFFSET rflags,EFLAGS-ARGOFFSET*/
19830 + CFI_REL_OFFSET rsp,RSP-ARGOFFSET
19831 +/* CFI_REL_OFFSET ss,SS-ARGOFFSET*/
19835 + jmp ia32_sysret /* misbalances the return cache */
19837 +END(ia32_ptregs_common)
19839 + .section .rodata,"a"
19841 +ia32_sys_call_table:
19842 + .quad sys_restart_syscall
19844 + .quad stub32_fork
19847 + .quad compat_sys_open /* 5 */
19849 + .quad sys32_waitpid
19852 + .quad sys_unlink /* 10 */
19853 + .quad stub32_execve
19855 + .quad compat_sys_time
19857 + .quad sys_chmod /* 15 */
19858 + .quad sys_lchown16
19859 + .quad quiet_ni_syscall /* old break syscall holder */
19861 + .quad sys32_lseek
19862 + .quad sys_getpid /* 20 */
19863 + .quad compat_sys_mount /* mount */
19864 + .quad sys_oldumount /* old_umount */
19865 + .quad sys_setuid16
19866 + .quad sys_getuid16
19867 + .quad compat_sys_stime /* stime */ /* 25 */
19868 + .quad sys32_ptrace /* ptrace */
19870 + .quad sys_fstat /* (old)fstat */
19872 + .quad compat_sys_utime /* 30 */
19873 + .quad quiet_ni_syscall /* old stty syscall holder */
19874 + .quad quiet_ni_syscall /* old gtty syscall holder */
19877 + .quad quiet_ni_syscall /* 35 */ /* old ftime syscall holder */
19882 + .quad sys_rmdir /* 40 */
19885 + .quad compat_sys_times
19886 + .quad quiet_ni_syscall /* old prof syscall holder */
19887 + .quad sys_brk /* 45 */
19888 + .quad sys_setgid16
19889 + .quad sys_getgid16
19891 + .quad sys_geteuid16
19892 + .quad sys_getegid16 /* 50 */
19894 + .quad sys_umount /* new_umount */
19895 + .quad quiet_ni_syscall /* old lock syscall holder */
19896 + .quad compat_sys_ioctl
19897 + .quad compat_sys_fcntl64 /* 55 */
19898 + .quad quiet_ni_syscall /* old mpx syscall holder */
19899 + .quad sys_setpgid
19900 + .quad quiet_ni_syscall /* old ulimit syscall holder */
19901 + .quad sys32_olduname
19902 + .quad sys_umask /* 60 */
19904 + .quad sys32_ustat
19906 + .quad sys_getppid
19907 + .quad sys_getpgrp /* 65 */
19909 + .quad sys32_sigaction
19910 + .quad sys_sgetmask
19911 + .quad sys_ssetmask
19912 + .quad sys_setreuid16 /* 70 */
19913 + .quad sys_setregid16
19914 + .quad stub32_sigsuspend
19915 + .quad compat_sys_sigpending
19916 + .quad sys_sethostname
19917 + .quad compat_sys_setrlimit /* 75 */
19918 + .quad compat_sys_old_getrlimit /* old_getrlimit */
19919 + .quad compat_sys_getrusage
19920 + .quad sys32_gettimeofday
19921 + .quad sys32_settimeofday
19922 + .quad sys_getgroups16 /* 80 */
19923 + .quad sys_setgroups16
19924 + .quad sys32_old_select
19925 + .quad sys_symlink
19927 + .quad sys_readlink /* 85 */
19928 +#ifdef CONFIG_IA32_AOUT
19931 + .quad quiet_ni_syscall
19935 + .quad compat_sys_old_readdir
19936 + .quad sys32_mmap /* 90 */
19938 + .quad sys_truncate
19939 + .quad sys_ftruncate
19941 + .quad sys_fchown16 /* 95 */
19942 + .quad sys_getpriority
19943 + .quad sys_setpriority
19944 + .quad quiet_ni_syscall /* old profil syscall holder */
19945 + .quad compat_sys_statfs
19946 + .quad compat_sys_fstatfs /* 100 */
19948 + .quad compat_sys_socketcall
19950 + .quad compat_sys_setitimer
19951 + .quad compat_sys_getitimer /* 105 */
19952 + .quad compat_sys_newstat
19953 + .quad compat_sys_newlstat
19954 + .quad compat_sys_newfstat
19955 + .quad sys32_uname
19956 + .quad stub32_iopl /* 110 */
19957 + .quad sys_vhangup
19958 + .quad quiet_ni_syscall /* old "idle" system call */
19959 + .quad sys32_vm86_warning /* vm86old */
19960 + .quad compat_sys_wait4
19961 + .quad sys_swapoff /* 115 */
19962 + .quad sys32_sysinfo
19965 + .quad stub32_sigreturn
19966 + .quad stub32_clone /* 120 */
19967 + .quad sys_setdomainname
19969 + .quad sys_modify_ldt
19970 + .quad compat_sys_adjtimex
19971 + .quad sys32_mprotect /* 125 */
19972 + .quad compat_sys_sigprocmask
19973 + .quad quiet_ni_syscall /* create_module */
19974 + .quad sys_init_module
19975 + .quad sys_delete_module
19976 + .quad quiet_ni_syscall /* 130 get_kernel_syms */
19977 + .quad sys_quotactl
19978 + .quad sys_getpgid
19980 + .quad quiet_ni_syscall /* bdflush */
19981 + .quad sys_sysfs /* 135 */
19982 + .quad sys_personality
19983 + .quad quiet_ni_syscall /* for afs_syscall */
19984 + .quad sys_setfsuid16
19985 + .quad sys_setfsgid16
19986 + .quad sys_llseek /* 140 */
19987 + .quad compat_sys_getdents
19988 + .quad compat_sys_select
19991 + .quad compat_sys_readv /* 145 */
19992 + .quad compat_sys_writev
19994 + .quad sys_fdatasync
19995 + .quad sys32_sysctl /* sysctl */
19996 + .quad sys_mlock /* 150 */
19997 + .quad sys_munlock
19998 + .quad sys_mlockall
19999 + .quad sys_munlockall
20000 + .quad sys_sched_setparam
20001 + .quad sys_sched_getparam /* 155 */
20002 + .quad sys_sched_setscheduler
20003 + .quad sys_sched_getscheduler
20004 + .quad sys_sched_yield
20005 + .quad sys_sched_get_priority_max
20006 + .quad sys_sched_get_priority_min /* 160 */
20007 + .quad sys_sched_rr_get_interval
20008 + .quad compat_sys_nanosleep
20010 + .quad sys_setresuid16
20011 + .quad sys_getresuid16 /* 165 */
20012 + .quad sys32_vm86_warning /* vm86 */
20013 + .quad quiet_ni_syscall /* query_module */
20015 + .quad compat_sys_nfsservctl
20016 + .quad sys_setresgid16 /* 170 */
20017 + .quad sys_getresgid16
20019 + .quad stub32_rt_sigreturn
20020 + .quad sys32_rt_sigaction
20021 + .quad sys32_rt_sigprocmask /* 175 */
20022 + .quad sys32_rt_sigpending
20023 + .quad compat_sys_rt_sigtimedwait
20024 + .quad sys32_rt_sigqueueinfo
20025 + .quad stub32_rt_sigsuspend
20026 + .quad sys32_pread /* 180 */
20027 + .quad sys32_pwrite
20028 + .quad sys_chown16
20032 + .quad stub32_sigaltstack
20033 + .quad sys32_sendfile
20034 + .quad quiet_ni_syscall /* streams1 */
20035 + .quad quiet_ni_syscall /* streams2 */
20036 + .quad stub32_vfork /* 190 */
20037 + .quad compat_sys_getrlimit
20038 + .quad sys32_mmap2
20039 + .quad sys32_truncate64
20040 + .quad sys32_ftruncate64
20041 + .quad sys32_stat64 /* 195 */
20042 + .quad sys32_lstat64
20043 + .quad sys32_fstat64
20046 + .quad sys_getgid /* 200 */
20047 + .quad sys_geteuid
20048 + .quad sys_getegid
20049 + .quad sys_setreuid
20050 + .quad sys_setregid
20051 + .quad sys_getgroups /* 205 */
20052 + .quad sys_setgroups
20054 + .quad sys_setresuid
20055 + .quad sys_getresuid
20056 + .quad sys_setresgid /* 210 */
20057 + .quad sys_getresgid
20061 + .quad sys_setfsuid /* 215 */
20062 + .quad sys_setfsgid
20063 + .quad sys_pivot_root
20064 + .quad sys_mincore
20065 + .quad sys_madvise
20066 + .quad compat_sys_getdents64 /* 220 getdents64 */
20067 + .quad compat_sys_fcntl64
20068 + .quad quiet_ni_syscall /* tux */
20069 + .quad quiet_ni_syscall /* security */
20071 + .quad sys_readahead /* 225 */
20072 + .quad sys_setxattr
20073 + .quad sys_lsetxattr
20074 + .quad sys_fsetxattr
20075 + .quad sys_getxattr
20076 + .quad sys_lgetxattr /* 230 */
20077 + .quad sys_fgetxattr
20078 + .quad sys_listxattr
20079 + .quad sys_llistxattr
20080 + .quad sys_flistxattr
20081 + .quad sys_removexattr /* 235 */
20082 + .quad sys_lremovexattr
20083 + .quad sys_fremovexattr
20085 + .quad sys_sendfile64
20086 + .quad compat_sys_futex /* 240 */
20087 + .quad compat_sys_sched_setaffinity
20088 + .quad compat_sys_sched_getaffinity
20089 + .quad sys32_set_thread_area
20090 + .quad sys32_get_thread_area
20091 + .quad compat_sys_io_setup /* 245 */
20092 + .quad sys_io_destroy
20093 + .quad compat_sys_io_getevents
20094 + .quad compat_sys_io_submit
20095 + .quad sys_io_cancel
20096 + .quad sys_fadvise64 /* 250 */
20097 + .quad quiet_ni_syscall /* free_huge_pages */
20098 + .quad sys_exit_group
20099 + .quad sys32_lookup_dcookie
20100 + .quad sys_epoll_create
20101 + .quad sys_epoll_ctl /* 255 */
20102 + .quad sys_epoll_wait
20103 + .quad sys_remap_file_pages
20104 + .quad sys_set_tid_address
20105 + .quad compat_sys_timer_create
20106 + .quad compat_sys_timer_settime /* 260 */
20107 + .quad compat_sys_timer_gettime
20108 + .quad sys_timer_getoverrun
20109 + .quad sys_timer_delete
20110 + .quad compat_sys_clock_settime
20111 + .quad compat_sys_clock_gettime /* 265 */
20112 + .quad compat_sys_clock_getres
20113 + .quad compat_sys_clock_nanosleep
20114 + .quad compat_sys_statfs64
20115 + .quad compat_sys_fstatfs64
20116 + .quad sys_tgkill /* 270 */
20117 + .quad compat_sys_utimes
20118 + .quad sys32_fadvise64_64
20119 + .quad quiet_ni_syscall /* sys_vserver */
20121 + .quad compat_sys_get_mempolicy /* 275 */
20122 + .quad sys_set_mempolicy
20123 + .quad compat_sys_mq_open
20124 + .quad sys_mq_unlink
20125 + .quad compat_sys_mq_timedsend
20126 + .quad compat_sys_mq_timedreceive /* 280 */
20127 + .quad compat_sys_mq_notify
20128 + .quad compat_sys_mq_getsetattr
20129 + .quad compat_sys_kexec_load /* reserved for kexec */
20130 + .quad compat_sys_waitid
20131 + .quad quiet_ni_syscall /* 285: sys_altroot */
20132 + .quad sys_add_key
20133 + .quad sys_request_key
20135 + .quad sys_ioprio_set
20136 + .quad sys_ioprio_get /* 290 */
20137 + .quad sys_inotify_init
20138 + .quad sys_inotify_add_watch
20139 + .quad sys_inotify_rm_watch
20140 + .quad sys_migrate_pages
20141 + .quad compat_sys_openat /* 295 */
20142 + .quad sys_mkdirat
20143 + .quad sys_mknodat
20144 + .quad sys_fchownat
20145 + .quad compat_sys_futimesat
20146 + .quad sys32_fstatat /* 300 */
20147 + .quad sys_unlinkat
20148 + .quad sys_renameat
20150 + .quad sys_symlinkat
20151 + .quad sys_readlinkat /* 305 */
20152 + .quad sys_fchmodat
20153 + .quad sys_faccessat
20154 + .quad quiet_ni_syscall /* pselect6 for now */
20155 + .quad quiet_ni_syscall /* ppoll for now */
20156 + .quad sys_unshare /* 310 */
20157 + .quad compat_sys_set_robust_list
20158 + .quad compat_sys_get_robust_list
20160 + .quad sys_sync_file_range
20162 + .quad compat_sys_vmsplice
20163 + .quad compat_sys_move_pages
20165 Index: head-2008-11-25/arch/x86/kernel/acpi/sleep_64-xen.c
20166 ===================================================================
20167 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
20168 +++ head-2008-11-25/arch/x86/kernel/acpi/sleep_64-xen.c 2008-04-15 09:29:41.000000000 +0200
20171 + * acpi.c - Architecture-Specific Low-Level ACPI Support
20173 + * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
20174 + * Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com>
20175 + * Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
20176 + * Copyright (C) 2002 Andi Kleen, SuSE Labs (x86-64 port)
20177 + * Copyright (C) 2003 Pavel Machek, SuSE Labs
20179 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
20181 + * This program is free software; you can redistribute it and/or modify
20182 + * it under the terms of the GNU General Public License as published by
20183 + * the Free Software Foundation; either version 2 of the License, or
20184 + * (at your option) any later version.
20186 + * This program is distributed in the hope that it will be useful,
20187 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
20188 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20189 + * GNU General Public License for more details.
20191 + * You should have received a copy of the GNU General Public License
20192 + * along with this program; if not, write to the Free Software
20193 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20195 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
20198 +#include <linux/kernel.h>
20199 +#include <linux/init.h>
20200 +#include <linux/types.h>
20201 +#include <linux/stddef.h>
20202 +#include <linux/slab.h>
20203 +#include <linux/pci.h>
20204 +#include <linux/bootmem.h>
20205 +#include <linux/acpi.h>
20206 +#include <linux/cpumask.h>
20208 +#include <asm/mpspec.h>
20209 +#include <asm/io.h>
20210 +#include <asm/apic.h>
20211 +#include <asm/apicdef.h>
20212 +#include <asm/page.h>
20213 +#include <asm/pgtable.h>
20214 +#include <asm/pgalloc.h>
20215 +#include <asm/io_apic.h>
20216 +#include <asm/proto.h>
20217 +#include <asm/tlbflush.h>
20219 +/* --------------------------------------------------------------------------
20220 + Low-Level Sleep Support
20221 + -------------------------------------------------------------------------- */
20223 +#ifdef CONFIG_ACPI_SLEEP
20225 +#ifndef CONFIG_ACPI_PV_SLEEP
20226 +/* address in low memory of the wakeup routine. */
20227 +unsigned long acpi_wakeup_address = 0;
20228 +unsigned long acpi_video_flags;
20229 +extern char wakeup_start, wakeup_end;
20231 +extern unsigned long FASTCALL(acpi_copy_wakeup_routine(unsigned long));
20233 +static pgd_t low_ptr;
20235 +static void init_low_mapping(void)
20237 + pgd_t *slot0 = pgd_offset(current->mm, 0UL);
20238 + low_ptr = *slot0;
20239 + set_pgd(slot0, *pgd_offset(current->mm, PAGE_OFFSET));
20240 + WARN_ON(num_online_cpus() != 1);
20241 + local_flush_tlb();
20246 + * acpi_save_state_mem - save kernel state
20248 + * Create an identity mapped page table and copy the wakeup routine to
20251 +int acpi_save_state_mem(void)
20253 +#ifndef CONFIG_ACPI_PV_SLEEP
20254 + init_low_mapping();
20256 + memcpy((void *)acpi_wakeup_address, &wakeup_start,
20257 + &wakeup_end - &wakeup_start);
20258 + acpi_copy_wakeup_routine(acpi_wakeup_address);
20264 + * acpi_restore_state
20266 +void acpi_restore_state_mem(void)
20268 +#ifndef CONFIG_ACPI_PV_SLEEP
20269 + set_pgd(pgd_offset(current->mm, 0UL), low_ptr);
20270 + local_flush_tlb();
20275 + * acpi_reserve_bootmem - do _very_ early ACPI initialisation
20277 + * We allocate a page in low memory for the wakeup
20278 + * routine for when we come back from a sleep state. The
20279 + * runtime allocator allows specification of <16M pages, but not
20282 +void __init acpi_reserve_bootmem(void)
20284 +#ifndef CONFIG_ACPI_PV_SLEEP
20285 + acpi_wakeup_address = (unsigned long)alloc_bootmem_low(PAGE_SIZE);
20286 + if ((&wakeup_end - &wakeup_start) > PAGE_SIZE)
20288 + "ACPI: Wakeup code way too big, will crash on attempt to suspend\n");
20292 +#ifndef CONFIG_ACPI_PV_SLEEP
20293 +static int __init acpi_sleep_setup(char *str)
20295 + while ((str != NULL) && (*str != '\0')) {
20296 + if (strncmp(str, "s3_bios", 7) == 0)
20297 + acpi_video_flags = 1;
20298 + if (strncmp(str, "s3_mode", 7) == 0)
20299 + acpi_video_flags |= 2;
20300 + str = strchr(str, ',');
20302 + str += strspn(str, ", \t");
20308 +__setup("acpi_sleep=", acpi_sleep_setup);
20309 +#endif /* CONFIG_ACPI_PV_SLEEP */
20311 +#endif /*CONFIG_ACPI_SLEEP */
20313 +void acpi_pci_link_exit(void)
20316 Index: head-2008-11-25/arch/x86/kernel/apic_64-xen.c
20317 ===================================================================
20318 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
20319 +++ head-2008-11-25/arch/x86/kernel/apic_64-xen.c 2007-06-12 13:13:01.000000000 +0200
20322 + * Local APIC handling, local APIC timers
20324 + * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
20327 + * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
20328 + * thanks to Eric Gilmore
20329 + * and Rolf G. Tews
20330 + * for testing these extensively.
20331 + * Maciej W. Rozycki : Various updates and fixes.
20332 + * Mikael Pettersson : Power Management for UP-APIC.
20333 + * Pavel Machek and
20334 + * Mikael Pettersson : PM converted to driver model.
20337 +#include <linux/init.h>
20339 +#include <linux/mm.h>
20340 +#include <linux/delay.h>
20341 +#include <linux/bootmem.h>
20342 +#include <linux/smp_lock.h>
20343 +#include <linux/interrupt.h>
20344 +#include <linux/mc146818rtc.h>
20345 +#include <linux/kernel_stat.h>
20346 +#include <linux/sysdev.h>
20347 +#include <linux/module.h>
20349 +#include <asm/atomic.h>
20350 +#include <asm/smp.h>
20351 +#include <asm/mtrr.h>
20352 +#include <asm/mpspec.h>
20353 +#include <asm/desc.h>
20354 +#include <asm/arch_hooks.h>
20355 +#include <asm/hpet.h>
20356 +#include <asm/idle.h>
20358 +int apic_verbosity;
20361 + * 'what should we do if we get a hw irq event on an illegal vector'.
20362 + * each architecture has to answer this themselves.
20364 +void ack_bad_irq(unsigned int irq)
20366 + printk("unexpected IRQ trap at vector %02x\n", irq);
20368 + * Currently unexpected vectors happen only on SMP and APIC.
20369 + * We _must_ ack these because every local APIC has only N
20370 + * irq slots per priority level, and a 'hanging, unacked' IRQ
20371 + * holds up an irq slot - in excessive cases (when multiple
20372 + * unexpected vectors occur) that might lock up the APIC
20374 + * But don't ack when the APIC is disabled. -AK
20376 + if (!disable_apic)
20380 +int setup_profiling_timer(unsigned int multiplier)
20385 +void smp_local_timer_interrupt(struct pt_regs *regs)
20387 + profile_tick(CPU_PROFILING, regs);
20388 +#ifndef CONFIG_XEN
20390 + update_process_times(user_mode(regs));
20394 + * We take the 'long' return path, and there every subsystem
20395 + * grabs the appropriate locks (kernel lock/ irq lock).
20397 + * we might want to decouple profiling from the 'long path',
20398 + * and do the profiling totally in assembly.
20400 + * Currently this isn't too much of an issue (performance wise),
20401 + * we can take more than 100K local irqs per second on a 100 MHz P5.
20406 + * Local APIC timer interrupt. This is the most natural way for doing
20407 + * local interrupts, but local timer interrupts can be emulated by
20408 + * broadcast interrupts too. [in case the hw doesn't support APIC timers]
20410 + * [ if a single-CPU system runs an SMP kernel then we call the local
20411 + * interrupt as well. Thus we cannot inline the local irq ... ]
20413 +void smp_apic_timer_interrupt(struct pt_regs *regs)
20416 + * the NMI deadlock-detector uses this.
20418 + add_pda(apic_timer_irqs, 1);
20421 + * NOTE! We'd better ACK the irq immediately,
20422 + * because timer handling can be slow.
20426 + * update_process_times() expects us to have done irq_enter().
20427 + * Besides, if we don't timer interrupts ignore the global
20428 + * interrupt lock, which is the WrongThing (tm) to do.
20432 + smp_local_timer_interrupt(regs);
20437 + * This interrupt should _never_ happen with our APIC/SMP architecture
20439 +asmlinkage void smp_spurious_interrupt(void)
20445 + * Check if this really is a spurious interrupt and ACK it
20446 + * if it is a vectored one. Just in case...
20447 + * Spurious interrupts should not be ACKed.
20449 + v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
20450 + if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
20454 + static unsigned long last_warning;
20455 + static unsigned long skipped;
20457 + /* see sw-dev-man vol 3, chapter 7.4.13.5 */
20458 + if (time_before(last_warning+30*HZ,jiffies)) {
20459 + printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
20460 + smp_processor_id(), skipped);
20461 + last_warning = jiffies;
20471 + * This interrupt should never happen with our APIC/SMP architecture
20474 +asmlinkage void smp_error_interrupt(void)
20476 + unsigned int v, v1;
20480 + /* First tickle the hardware, only then report what went on. -- REW */
20481 + v = apic_read(APIC_ESR);
20482 + apic_write(APIC_ESR, 0);
20483 + v1 = apic_read(APIC_ESR);
20485 + atomic_inc(&irq_err_count);
20487 + /* Here is what the APIC error bits mean:
20489 + 1: Receive CS error
20490 + 2: Send accept error
20491 + 3: Receive accept error
20493 + 5: Send illegal vector
20494 + 6: Received illegal vector
20495 + 7: Illegal register address
20497 + printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
20498 + smp_processor_id(), v , v1);
20505 + * This initializes the IO-APIC and APIC hardware if this is
20508 +int __init APIC_init_uniprocessor (void)
20510 +#ifdef CONFIG_X86_IO_APIC
20511 + if (smp_found_config)
20512 + if (!skip_ioapic_setup && nr_ioapics)
20518 Index: head-2008-11-25/arch/x86/kernel/e820_64-xen.c
20519 ===================================================================
20520 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
20521 +++ head-2008-11-25/arch/x86/kernel/e820_64-xen.c 2008-04-22 19:56:27.000000000 +0200
20524 + * Handle the memory map.
20525 + * The functions here do the job until bootmem takes over.
20527 + * Getting sanitize_e820_map() in sync with i386 version by applying change:
20528 + * - Provisions for empty E820 memory regions (reported by certain BIOSes).
20529 + * Alex Achenbach <xela@slit.de>, December 2002.
20530 + * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
20533 +#include <linux/kernel.h>
20534 +#include <linux/types.h>
20535 +#include <linux/init.h>
20536 +#include <linux/bootmem.h>
20537 +#include <linux/ioport.h>
20538 +#include <linux/string.h>
20539 +#include <linux/kexec.h>
20540 +#include <linux/module.h>
20542 +#include <asm/pgtable.h>
20543 +#include <asm/page.h>
20544 +#include <asm/e820.h>
20545 +#include <asm/proto.h>
20546 +#include <asm/bootsetup.h>
20547 +#include <asm/sections.h>
20548 +#include <xen/interface/memory.h>
20551 + * PFN of last memory page.
20553 +unsigned long end_pfn;
20554 +EXPORT_SYMBOL(end_pfn);
20557 + * end_pfn only includes RAM, while end_pfn_map includes all e820 entries.
20558 + * The direct mapping extends to end_pfn_map, so that we can directly access
20559 + * apertures, ACPI and other tables without having to play with fixmaps.
20561 +unsigned long end_pfn_map;
20564 + * Last pfn which the user wants to use.
20566 +unsigned long end_user_pfn = MAXMEM>>PAGE_SHIFT;
20568 +extern struct resource code_resource, data_resource;
20571 +extern struct e820map machine_e820;
20574 +/* Check for some hardcoded bad areas that early boot is not allowed to touch */
20575 +static inline int bad_addr(unsigned long *addrp, unsigned long size)
20577 + unsigned long addr = *addrp, last = addr + size;
20579 +#ifndef CONFIG_XEN
20580 + /* various gunk below that needed for SMP startup */
20581 + if (addr < 0x8000) {
20586 + /* direct mapping tables of the kernel */
20587 + if (last >= table_start<<PAGE_SHIFT && addr < table_end<<PAGE_SHIFT) {
20588 + *addrp = table_end << PAGE_SHIFT;
20593 +#ifdef CONFIG_BLK_DEV_INITRD
20594 + if (LOADER_TYPE && INITRD_START && last >= INITRD_START &&
20595 + addr < INITRD_START+INITRD_SIZE) {
20596 + *addrp = INITRD_START + INITRD_SIZE;
20600 + /* kernel code + 640k memory hole (later should not be needed, but
20601 + be paranoid for now) */
20602 + if (last >= 640*1024 && addr < 1024*1024) {
20603 + *addrp = 1024*1024;
20606 + if (last >= __pa_symbol(&_text) && last < __pa_symbol(&_end)) {
20607 + *addrp = __pa_symbol(&_end);
20611 + if (last >= ebda_addr && addr < ebda_addr + ebda_size) {
20612 + *addrp = ebda_addr + ebda_size;
20616 + /* XXX ramdisk image here? */
20618 + if (last < (table_end<<PAGE_SHIFT)) {
20619 + *addrp = table_end << PAGE_SHIFT;
20627 + * This function checks if any part of the range <start,end> is mapped
20630 +int e820_any_mapped(unsigned long start, unsigned long end, unsigned type)
20634 +#ifndef CONFIG_XEN
20635 + for (i = 0; i < e820.nr_map; i++) {
20636 + struct e820entry *ei = &e820.map[i];
20638 + if (!is_initial_xendomain())
20640 + for (i = 0; i < machine_e820.nr_map; i++) {
20641 + const struct e820entry *ei = &machine_e820.map[i];
20644 + if (type && ei->type != type)
20646 + if (ei->addr >= end || ei->addr + ei->size <= start)
20652 +EXPORT_SYMBOL_GPL(e820_any_mapped);
20655 + * This function checks if the entire range <start,end> is mapped with type.
20657 + * Note: this function only works correct if the e820 table is sorted and
20658 + * not-overlapping, which is the case
20660 +int __init e820_all_mapped(unsigned long start, unsigned long end, unsigned type)
20664 +#ifndef CONFIG_XEN
20665 + for (i = 0; i < e820.nr_map; i++) {
20666 + struct e820entry *ei = &e820.map[i];
20668 + if (!is_initial_xendomain())
20670 + for (i = 0; i < machine_e820.nr_map; i++) {
20671 + const struct e820entry *ei = &machine_e820.map[i];
20674 + if (type && ei->type != type)
20676 + /* is the region (part) in overlap with the current region ?*/
20677 + if (ei->addr >= end || ei->addr + ei->size <= start)
20680 + /* if the region is at the beginning of <start,end> we move
20681 + * start to the end of the region since it's ok until there
20683 + if (ei->addr <= start)
20684 + start = ei->addr + ei->size;
20685 + /* if start is now at or beyond end, we're done, full coverage */
20686 + if (start >= end)
20687 + return 1; /* we're done */
20693 + * Find a free area in a specific range.
20695 +unsigned long __init find_e820_area(unsigned long start, unsigned long end, unsigned size)
20698 + for (i = 0; i < e820.nr_map; i++) {
20699 + struct e820entry *ei = &e820.map[i];
20700 + unsigned long addr = ei->addr, last;
20701 + if (ei->type != E820_RAM)
20703 + if (addr < start)
20705 + if (addr > ei->addr + ei->size)
20707 + while (bad_addr(&addr, size) && addr+size <= ei->addr+ei->size)
20709 + last = addr + size;
20710 + if (last > ei->addr + ei->size)
20720 + * Free bootmem based on the e820 table for a node.
20722 +void __init e820_bootmem_free(pg_data_t *pgdat, unsigned long start,unsigned long end)
20725 + for (i = 0; i < e820.nr_map; i++) {
20726 + struct e820entry *ei = &e820.map[i];
20727 + unsigned long last, addr;
20729 + if (ei->type != E820_RAM ||
20730 + ei->addr+ei->size <= start ||
20734 + addr = round_up(ei->addr, PAGE_SIZE);
20735 + if (addr < start)
20738 + last = round_down(ei->addr + ei->size, PAGE_SIZE);
20742 + if (last > addr && last-addr >= PAGE_SIZE)
20743 + free_bootmem_node(pgdat, addr, last-addr);
20748 + * Find the highest page frame number we have available
20750 +unsigned long __init e820_end_of_ram(void)
20753 + unsigned long end_pfn = 0;
20755 + for (i = 0; i < e820.nr_map; i++) {
20756 + struct e820entry *ei = &e820.map[i];
20757 + unsigned long start, end;
20759 + start = round_up(ei->addr, PAGE_SIZE);
20760 + end = round_down(ei->addr + ei->size, PAGE_SIZE);
20761 + if (start >= end)
20763 + if (ei->type == E820_RAM) {
20764 + if (end > end_pfn<<PAGE_SHIFT)
20765 + end_pfn = end>>PAGE_SHIFT;
20767 + if (end > end_pfn_map<<PAGE_SHIFT)
20768 + end_pfn_map = end>>PAGE_SHIFT;
20772 + if (end_pfn > end_pfn_map)
20773 + end_pfn_map = end_pfn;
20774 + if (end_pfn_map > MAXMEM>>PAGE_SHIFT)
20775 + end_pfn_map = MAXMEM>>PAGE_SHIFT;
20776 + if (end_pfn > end_user_pfn)
20777 + end_pfn = end_user_pfn;
20778 + if (end_pfn > end_pfn_map)
20779 + end_pfn = end_pfn_map;
20785 + * Compute how much memory is missing in a range.
20786 + * Unlike the other functions in this file the arguments are in page numbers.
20788 +unsigned long __init
20789 +e820_hole_size(unsigned long start_pfn, unsigned long end_pfn)
20791 + unsigned long ram = 0;
20792 + unsigned long start = start_pfn << PAGE_SHIFT;
20793 + unsigned long end = end_pfn << PAGE_SHIFT;
20795 + for (i = 0; i < e820.nr_map; i++) {
20796 + struct e820entry *ei = &e820.map[i];
20797 + unsigned long last, addr;
20799 + if (ei->type != E820_RAM ||
20800 + ei->addr+ei->size <= start ||
20804 + addr = round_up(ei->addr, PAGE_SIZE);
20805 + if (addr < start)
20808 + last = round_down(ei->addr + ei->size, PAGE_SIZE);
20813 + ram += last - addr;
20815 + return ((end - start) - ram) >> PAGE_SHIFT;
20819 + * Mark e820 reserved areas as busy for the resource manager.
20821 +void __init e820_reserve_resources(struct e820entry *e820, int nr_map)
20824 + for (i = 0; i < nr_map; i++) {
20825 + struct resource *res;
20826 + res = alloc_bootmem_low(sizeof(struct resource));
20827 + switch (e820[i].type) {
20828 + case E820_RAM: res->name = "System RAM"; break;
20829 + case E820_ACPI: res->name = "ACPI Tables"; break;
20830 + case E820_NVS: res->name = "ACPI Non-volatile Storage"; break;
20831 + default: res->name = "reserved";
20833 + res->start = e820[i].addr;
20834 + res->end = res->start + e820[i].size - 1;
20835 + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
20836 + request_resource(&iomem_resource, res);
20837 + if (e820[i].type == E820_RAM) {
20839 + * We don't know which RAM region contains kernel data,
20840 + * so we try it repeatedly and let the resource manager
20843 +#ifndef CONFIG_XEN
20844 + request_resource(res, &code_resource);
20845 + request_resource(res, &data_resource);
20847 +#ifdef CONFIG_KEXEC
20848 + if (crashk_res.start != crashk_res.end)
20849 + request_resource(res, &crashk_res);
20851 + xen_machine_kexec_register_resources(res);
20859 + * Add a memory region to the kernel e820 map.
20861 +void __init add_memory_region(unsigned long start, unsigned long size, int type)
20863 + int x = e820.nr_map;
20865 + if (x == E820MAX) {
20866 + printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
20870 + e820.map[x].addr = start;
20871 + e820.map[x].size = size;
20872 + e820.map[x].type = type;
20876 +void __init e820_print_map(char *who)
20880 + for (i = 0; i < e820.nr_map; i++) {
20881 + printk(" %s: %016Lx - %016Lx ", who,
20882 + (unsigned long long) e820.map[i].addr,
20883 + (unsigned long long) (e820.map[i].addr + e820.map[i].size));
20884 + switch (e820.map[i].type) {
20885 + case E820_RAM: printk("(usable)\n");
20887 + case E820_RESERVED:
20888 + printk("(reserved)\n");
20891 + printk("(ACPI data)\n");
20894 + printk("(ACPI NVS)\n");
20896 + default: printk("type %u\n", e820.map[i].type);
20903 + * Sanitize the BIOS e820 map.
20905 + * Some e820 responses include overlapping entries. The following
20906 + * replaces the original e820 map with a new one, removing overlaps.
20909 +static int __init sanitize_e820_map(struct e820entry * biosmap, char * pnr_map)
20911 + struct change_member {
20912 + struct e820entry *pbios; /* pointer to original bios entry */
20913 + unsigned long long addr; /* address for this change point */
20915 + static struct change_member change_point_list[2*E820MAX] __initdata;
20916 + static struct change_member *change_point[2*E820MAX] __initdata;
20917 + static struct e820entry *overlap_list[E820MAX] __initdata;
20918 + static struct e820entry new_bios[E820MAX] __initdata;
20919 + struct change_member *change_tmp;
20920 + unsigned long current_type, last_type;
20921 + unsigned long long last_addr;
20922 + int chgidx, still_changing;
20923 + int overlap_entries;
20924 + int new_bios_entry;
20925 + int old_nr, new_nr, chg_nr;
20929 + Visually we're performing the following (1,2,3,4 = memory types)...
20931 + Sample memory map (w/overlaps):
20932 + ____22__________________
20933 + ______________________4_
20934 + ____1111________________
20935 + _44_____________________
20936 + 11111111________________
20937 + ____________________33__
20938 + ___________44___________
20939 + __________33333_________
20940 + ______________22________
20941 + ___________________2222_
20942 + _________111111111______
20943 + _____________________11_
20944 + _________________4______
20946 + Sanitized equivalent (no overlap):
20947 + 1_______________________
20948 + _44_____________________
20949 + ___1____________________
20950 + ____22__________________
20951 + ______11________________
20952 + _________1______________
20953 + __________3_____________
20954 + ___________44___________
20955 + _____________33_________
20956 + _______________2________
20957 + ________________1_______
20958 + _________________4______
20959 + ___________________2____
20960 + ____________________33__
20961 + ______________________4_
20964 + /* if there's only one memory region, don't bother */
20965 + if (*pnr_map < 2)
20968 + old_nr = *pnr_map;
20970 + /* bail out if we find any unreasonable addresses in bios map */
20971 + for (i=0; i<old_nr; i++)
20972 + if (biosmap[i].addr + biosmap[i].size < biosmap[i].addr)
20975 + /* create pointers for initial change-point information (for sorting) */
20976 + for (i=0; i < 2*old_nr; i++)
20977 + change_point[i] = &change_point_list[i];
20979 + /* record all known change-points (starting and ending addresses),
20980 + omitting those that are for empty memory regions */
20982 + for (i=0; i < old_nr; i++) {
20983 + if (biosmap[i].size != 0) {
20984 + change_point[chgidx]->addr = biosmap[i].addr;
20985 + change_point[chgidx++]->pbios = &biosmap[i];
20986 + change_point[chgidx]->addr = biosmap[i].addr + biosmap[i].size;
20987 + change_point[chgidx++]->pbios = &biosmap[i];
20992 + /* sort change-point list by memory addresses (low -> high) */
20993 + still_changing = 1;
20994 + while (still_changing) {
20995 + still_changing = 0;
20996 + for (i=1; i < chg_nr; i++) {
20997 + /* if <current_addr> > <last_addr>, swap */
20998 + /* or, if current=<start_addr> & last=<end_addr>, swap */
20999 + if ((change_point[i]->addr < change_point[i-1]->addr) ||
21000 + ((change_point[i]->addr == change_point[i-1]->addr) &&
21001 + (change_point[i]->addr == change_point[i]->pbios->addr) &&
21002 + (change_point[i-1]->addr != change_point[i-1]->pbios->addr))
21005 + change_tmp = change_point[i];
21006 + change_point[i] = change_point[i-1];
21007 + change_point[i-1] = change_tmp;
21008 + still_changing=1;
21013 + /* create a new bios memory map, removing overlaps */
21014 + overlap_entries=0; /* number of entries in the overlap table */
21015 + new_bios_entry=0; /* index for creating new bios map entries */
21016 + last_type = 0; /* start with undefined memory type */
21017 + last_addr = 0; /* start with 0 as last starting address */
21018 + /* loop through change-points, determining affect on the new bios map */
21019 + for (chgidx=0; chgidx < chg_nr; chgidx++)
21021 + /* keep track of all overlapping bios entries */
21022 + if (change_point[chgidx]->addr == change_point[chgidx]->pbios->addr)
21024 + /* add map entry to overlap list (> 1 entry implies an overlap) */
21025 + overlap_list[overlap_entries++]=change_point[chgidx]->pbios;
21029 + /* remove entry from list (order independent, so swap with last) */
21030 + for (i=0; i<overlap_entries; i++)
21032 + if (overlap_list[i] == change_point[chgidx]->pbios)
21033 + overlap_list[i] = overlap_list[overlap_entries-1];
21035 + overlap_entries--;
21037 + /* if there are overlapping entries, decide which "type" to use */
21038 + /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
21039 + current_type = 0;
21040 + for (i=0; i<overlap_entries; i++)
21041 + if (overlap_list[i]->type > current_type)
21042 + current_type = overlap_list[i]->type;
21043 + /* continue building up new bios map based on this information */
21044 + if (current_type != last_type) {
21045 + if (last_type != 0) {
21046 + new_bios[new_bios_entry].size =
21047 + change_point[chgidx]->addr - last_addr;
21048 + /* move forward only if the new size was non-zero */
21049 + if (new_bios[new_bios_entry].size != 0)
21050 + if (++new_bios_entry >= E820MAX)
21051 + break; /* no more space left for new bios entries */
21053 + if (current_type != 0) {
21054 + new_bios[new_bios_entry].addr = change_point[chgidx]->addr;
21055 + new_bios[new_bios_entry].type = current_type;
21056 + last_addr=change_point[chgidx]->addr;
21058 + last_type = current_type;
21061 + new_nr = new_bios_entry; /* retain count for new bios entries */
21063 + /* copy new bios mapping into original location */
21064 + memcpy(biosmap, new_bios, new_nr*sizeof(struct e820entry));
21065 + *pnr_map = new_nr;
21071 + * Copy the BIOS e820 map into a safe place.
21073 + * Sanity-check it while we're at it..
21075 + * If we're lucky and live on a modern system, the setup code
21076 + * will have given us a memory map that we can use to properly
21077 + * set up memory. If we aren't, we'll fake a memory map.
21079 + * We check to see that the memory map contains at least 2 elements
21080 + * before we'll use it, because the detection code in setup.S may
21081 + * not be perfect and most every PC known to man has two memory
21082 + * regions: one from 0 to 640k, and one from 1mb up. (The IBM
21083 + * thinkpad 560x, for example, does not cooperate with the memory
21084 + * detection code.)
21086 +static int __init copy_e820_map(struct e820entry * biosmap, int nr_map)
21088 +#ifndef CONFIG_XEN
21089 + /* Only one memory region (or negative)? Ignore it */
21093 + BUG_ON(nr_map < 1);
21097 + unsigned long start = biosmap->addr;
21098 + unsigned long size = biosmap->size;
21099 + unsigned long end = start + size;
21100 + unsigned long type = biosmap->type;
21102 + /* Overflow in 64 bits? Ignore the memory map. */
21106 +#ifndef CONFIG_XEN
21108 + * Some BIOSes claim RAM in the 640k - 1M region.
21109 + * Not right. Fix it up.
21111 + * This should be removed on Hammer which is supposed to not
21112 + * have non e820 covered ISA mappings there, but I had some strange
21113 + * problems so it stays for now. -AK
21115 + if (type == E820_RAM) {
21116 + if (start < 0x100000ULL && end > 0xA0000ULL) {
21117 + if (start < 0xA0000ULL)
21118 + add_memory_region(start, 0xA0000ULL-start, type);
21119 + if (end <= 0x100000ULL)
21121 + start = 0x100000ULL;
21122 + size = end - start;
21127 + add_memory_region(start, size, type);
21128 + } while (biosmap++,--nr_map);
21131 + if (is_initial_xendomain()) {
21132 + struct xen_memory_map memmap;
21134 + memmap.nr_entries = E820MAX;
21135 + set_xen_guest_handle(memmap.buffer, machine_e820.map);
21137 + if (HYPERVISOR_memory_op(XENMEM_machine_memory_map, &memmap))
21139 + machine_e820.nr_map = memmap.nr_entries;
21141 + machine_e820 = e820;
21147 +#ifndef CONFIG_XEN
21148 +void __init setup_memory_region(void)
21150 + char *who = "BIOS-e820";
21153 + * Try to copy the BIOS-supplied E820-map.
21155 + * Otherwise fake a memory map; one section from 0k->640k,
21156 + * the next section from 1mb->appropriate_mem_k
21158 + sanitize_e820_map(E820_MAP, &E820_MAP_NR);
21159 + if (copy_e820_map(E820_MAP, E820_MAP_NR) < 0) {
21160 + unsigned long mem_size;
21162 + /* compare results from other methods and take the greater */
21163 + if (ALT_MEM_K < EXT_MEM_K) {
21164 + mem_size = EXT_MEM_K;
21167 + mem_size = ALT_MEM_K;
21168 + who = "BIOS-e801";
21172 + add_memory_region(0, LOWMEMSIZE(), E820_RAM);
21173 + add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM);
21175 + printk(KERN_INFO "BIOS-provided physical RAM map:\n");
21176 + e820_print_map(who);
21179 +#else /* CONFIG_XEN */
21181 +void __init setup_memory_region(void)
21184 + struct xen_memory_map memmap;
21186 + * This is rather large for a stack variable but this early in
21187 + * the boot process we know we have plenty slack space.
21189 + struct e820entry map[E820MAX];
21191 + memmap.nr_entries = E820MAX;
21192 + set_xen_guest_handle(memmap.buffer, map);
21194 + rc = HYPERVISOR_memory_op(XENMEM_memory_map, &memmap);
21195 + if ( rc == -ENOSYS ) {
21196 + memmap.nr_entries = 1;
21197 + map[0].addr = 0ULL;
21198 + map[0].size = xen_start_info->nr_pages << PAGE_SHIFT;
21199 + /* 8MB slack (to balance backend allocations). */
21200 + map[0].size += 8 << 20;
21201 + map[0].type = E820_RAM;
21206 + sanitize_e820_map(map, (char *)&memmap.nr_entries);
21208 + BUG_ON(copy_e820_map(map, (char)memmap.nr_entries) < 0);
21210 + printk(KERN_INFO "BIOS-provided physical RAM map:\n");
21211 + e820_print_map("Xen");
21215 +void __init parse_memopt(char *p, char **from)
21218 + unsigned long current_end;
21219 + unsigned long end;
21221 + end_user_pfn = memparse(p, from);
21222 + end_user_pfn >>= PAGE_SHIFT;
21224 + end = end_user_pfn<<PAGE_SHIFT;
21225 + i = e820.nr_map-1;
21226 + current_end = e820.map[i].addr + e820.map[i].size;
21228 + if (current_end < end) {
21230 + * The e820 map ends before our requested size so
21231 + * extend the final entry to the requested address.
21233 + if (e820.map[i].type == E820_RAM)
21234 + e820.map[i].size = end - e820.map[i].addr;
21236 + add_memory_region(current_end, end - current_end, E820_RAM);
21240 +void __init parse_memmapopt(char *p, char **from)
21242 + unsigned long long start_at, mem_size;
21244 + mem_size = memparse(p, from);
21247 + start_at = memparse(p+1, from);
21248 + add_memory_region(start_at, mem_size, E820_RAM);
21249 + } else if (*p == '#') {
21250 + start_at = memparse(p+1, from);
21251 + add_memory_region(start_at, mem_size, E820_ACPI);
21252 + } else if (*p == '$') {
21253 + start_at = memparse(p+1, from);
21254 + add_memory_region(start_at, mem_size, E820_RESERVED);
21256 + end_user_pfn = (mem_size >> PAGE_SHIFT);
21261 +unsigned long pci_mem_start = 0xaeedbabe;
21262 +EXPORT_SYMBOL(pci_mem_start);
21265 + * Search for the biggest gap in the low 32 bits of the e820
21266 + * memory space. We pass this space to PCI to assign MMIO resources
21267 + * for hotplug or unconfigured devices in.
21268 + * Hopefully the BIOS let enough space left.
21270 +__init void e820_setup_gap(struct e820entry *e820, int nr_map)
21272 + unsigned long gapstart, gapsize, round;
21273 + unsigned long last;
21277 + last = 0x100000000ull;
21278 + gapstart = 0x10000000;
21279 + gapsize = 0x400000;
21281 + while (--i >= 0) {
21282 + unsigned long long start = e820[i].addr;
21283 + unsigned long long end = start + e820[i].size;
21286 + * Since "last" is at most 4GB, we know we'll
21287 + * fit in 32 bits if this condition is true
21289 + if (last > end) {
21290 + unsigned long gap = last - end;
21292 + if (gap > gapsize) {
21298 + if (start < last)
21303 + gapstart = (end_pfn << PAGE_SHIFT) + 1024*1024;
21304 + printk(KERN_ERR "PCI: Warning: Cannot find a gap in the 32bit address range\n"
21305 + KERN_ERR "PCI: Unassigned devices with 32bit resource registers may break!\n");
21309 + * See how much we want to round up: start off with
21310 + * rounding to the next 1MB area.
21312 + round = 0x100000;
21313 + while ((gapsize >> 4) > round)
21315 + /* Fun with two's complement */
21316 + pci_mem_start = (gapstart + round) & -round;
21318 + printk(KERN_INFO "Allocating PCI resources starting at %lx (gap: %lx:%lx)\n",
21319 + pci_mem_start, gapstart, gapsize);
21321 Index: head-2008-11-25/arch/x86/kernel/early_printk-xen.c
21322 ===================================================================
21323 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
21324 +++ head-2008-11-25/arch/x86/kernel/early_printk-xen.c 2007-06-12 13:13:01.000000000 +0200
21326 +#include <linux/console.h>
21327 +#include <linux/kernel.h>
21328 +#include <linux/init.h>
21329 +#include <linux/string.h>
21330 +#include <linux/screen_info.h>
21331 +#include <asm/io.h>
21332 +#include <asm/processor.h>
21333 +#include <asm/fcntl.h>
21335 +/* Simple VGA output */
21338 +#include <asm/setup.h>
21339 +#define VGABASE (__ISA_IO_base + 0xb8000)
21341 +#include <asm/bootsetup.h>
21342 +#define VGABASE ((void __iomem *)0xffffffff800b8000UL)
21345 +#ifndef CONFIG_XEN
21346 +static int max_ypos = 25, max_xpos = 80;
21347 +static int current_ypos = 25, current_xpos = 0;
21349 +static void early_vga_write(struct console *con, const char *str, unsigned n)
21354 + while ((c = *str++) != '\0' && n-- > 0) {
21355 + if (current_ypos >= max_ypos) {
21356 + /* scroll 1 line up */
21357 + for (k = 1, j = 0; k < max_ypos; k++, j++) {
21358 + for (i = 0; i < max_xpos; i++) {
21359 + writew(readw(VGABASE+2*(max_xpos*k+i)),
21360 + VGABASE + 2*(max_xpos*j + i));
21363 + for (i = 0; i < max_xpos; i++)
21364 + writew(0x720, VGABASE + 2*(max_xpos*j + i));
21365 + current_ypos = max_ypos-1;
21368 + current_xpos = 0;
21370 + } else if (c != '\r') {
21371 + writew(((0x7 << 8) | (unsigned short) c),
21372 + VGABASE + 2*(max_xpos*current_ypos +
21373 + current_xpos++));
21374 + if (current_xpos >= max_xpos) {
21375 + current_xpos = 0;
21382 +static struct console early_vga_console = {
21383 + .name = "earlyvga",
21384 + .write = early_vga_write,
21385 + .flags = CON_PRINTBUFFER,
21389 +/* Serial functions loosely based on a similar package from Klaus P. Gerlicher */
21391 +static int early_serial_base = 0x3f8; /* ttyS0 */
21393 +#define XMTRDY 0x20
21397 +#define TXR 0 /* Transmit register (WRITE) */
21398 +#define RXR 0 /* Receive register (READ) */
21399 +#define IER 1 /* Interrupt Enable */
21400 +#define IIR 2 /* Interrupt ID */
21401 +#define FCR 2 /* FIFO control */
21402 +#define LCR 3 /* Line control */
21403 +#define MCR 4 /* Modem control */
21404 +#define LSR 5 /* Line Status */
21405 +#define MSR 6 /* Modem Status */
21406 +#define DLL 0 /* Divisor Latch Low */
21407 +#define DLH 1 /* Divisor latch High */
21409 +static int early_serial_putc(unsigned char ch)
21411 + unsigned timeout = 0xffff;
21412 + while ((inb(early_serial_base + LSR) & XMTRDY) == 0 && --timeout)
21414 + outb(ch, early_serial_base + TXR);
21415 + return timeout ? 0 : -1;
21418 +static void early_serial_write(struct console *con, const char *s, unsigned n)
21420 + while (*s && n-- > 0) {
21421 + early_serial_putc(*s);
21423 + early_serial_putc('\r');
21428 +#define DEFAULT_BAUD 9600
21430 +static __init void early_serial_init(char *s)
21433 + unsigned divisor;
21434 + unsigned baud = DEFAULT_BAUD;
21442 + if (!strncmp(s,"0x",2)) {
21443 + early_serial_base = simple_strtoul(s, &e, 16);
21445 + static int bases[] = { 0x3f8, 0x2f8 };
21447 + if (!strncmp(s,"ttyS",4))
21449 + port = simple_strtoul(s, &e, 10);
21450 + if (port > 1 || s == e)
21452 + early_serial_base = bases[port];
21454 + s += strcspn(s, ",");
21459 + outb(0x3, early_serial_base + LCR); /* 8n1 */
21460 + outb(0, early_serial_base + IER); /* no interrupt */
21461 + outb(0, early_serial_base + FCR); /* no fifo */
21462 + outb(0x3, early_serial_base + MCR); /* DTR + RTS */
21465 + baud = simple_strtoul(s, &e, 0);
21466 + if (baud == 0 || s == e)
21467 + baud = DEFAULT_BAUD;
21470 + divisor = 115200 / baud;
21471 + c = inb(early_serial_base + LCR);
21472 + outb(c | DLAB, early_serial_base + LCR);
21473 + outb(divisor & 0xff, early_serial_base + DLL);
21474 + outb((divisor >> 8) & 0xff, early_serial_base + DLH);
21475 + outb(c & ~DLAB, early_serial_base + LCR);
21478 +#else /* CONFIG_XEN */
21481 +early_serial_write(struct console *con, const char *s, unsigned count)
21485 + while (count > 0) {
21486 + n = HYPERVISOR_console_io(CONSOLEIO_write, count, (char *)s);
21494 +static __init void early_serial_init(char *s)
21499 + * No early VGA console on Xen, as we do not have convenient ISA-space
21500 + * mappings. Someone should fix this for domain 0. For now, use fake serial.
21502 +#define early_vga_console early_serial_console
21506 +static struct console early_serial_console = {
21507 + .name = "earlyser",
21508 + .write = early_serial_write,
21509 + .flags = CON_PRINTBUFFER,
21513 +/* Console interface to a host file on AMD's SimNow! */
21515 +static int simnow_fd;
21518 + MAGIC1 = 0xBACCD00A,
21519 + MAGIC2 = 0xCA110000,
21524 +static noinline long simnow(long cmd, long a, long b, long c)
21527 + asm volatile("cpuid" :
21529 + "b" (a), "c" (b), "d" (c), "0" (MAGIC1), "D" (cmd + MAGIC2));
21533 +void __init simnow_init(char *str)
21535 + char *fn = "klog";
21538 + /* error ignored */
21539 + simnow_fd = simnow(XOPEN, (unsigned long)fn, O_WRONLY|O_APPEND|O_CREAT, 0644);
21542 +static void simnow_write(struct console *con, const char *s, unsigned n)
21544 + simnow(XWRITE, simnow_fd, (unsigned long)s, n);
21547 +static struct console simnow_console = {
21548 + .name = "simnow",
21549 + .write = simnow_write,
21550 + .flags = CON_PRINTBUFFER,
21554 +/* Direct interface for emergencies */
21555 +struct console *early_console = &early_vga_console;
21556 +static int early_console_initialized = 0;
21558 +void early_printk(const char *fmt, ...)
21564 + va_start(ap,fmt);
21565 + n = vscnprintf(buf,512,fmt,ap);
21566 + early_console->write(early_console,buf,n);
21570 +static int __initdata keep_early;
21572 +int __init setup_early_printk(char *opt)
21577 + if (early_console_initialized)
21580 + strlcpy(buf,opt,sizeof(buf));
21581 + space = strchr(buf, ' ');
21585 + if (strstr(buf,"keep"))
21588 + if (!strncmp(buf, "serial", 6)) {
21589 + early_serial_init(buf + 6);
21590 + early_console = &early_serial_console;
21591 + } else if (!strncmp(buf, "ttyS", 4)) {
21592 + early_serial_init(buf);
21593 + early_console = &early_serial_console;
21594 + } else if (!strncmp(buf, "vga", 3)
21595 +#ifndef CONFIG_XEN
21596 + && SCREEN_INFO.orig_video_isVGA == 1) {
21597 + max_xpos = SCREEN_INFO.orig_video_cols;
21598 + max_ypos = SCREEN_INFO.orig_video_lines;
21599 + current_ypos = SCREEN_INFO.orig_y;
21601 + || !strncmp(buf, "xen", 3)) {
21603 + early_console = &early_vga_console;
21604 + } else if (!strncmp(buf, "simnow", 6)) {
21605 + simnow_init(buf + 6);
21606 + early_console = &simnow_console;
21609 + early_console_initialized = 1;
21610 + register_console(early_console);
21614 +void __init disable_early_printk(void)
21616 + if (!early_console_initialized || !early_console)
21618 + if (!keep_early) {
21619 + printk("disabling early console\n");
21620 + unregister_console(early_console);
21621 + early_console_initialized = 0;
21623 + printk("keeping early console\n");
21627 +__setup("earlyprintk=", setup_early_printk);
21628 Index: head-2008-11-25/arch/x86/kernel/entry_64-xen.S
21629 ===================================================================
21630 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
21631 +++ head-2008-11-25/arch/x86/kernel/entry_64-xen.S 2008-10-29 09:55:56.000000000 +0100
21634 + * linux/arch/x86_64/entry.S
21636 + * Copyright (C) 1991, 1992 Linus Torvalds
21637 + * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
21638 + * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
21642 + * Jun Nakajima <jun.nakajima@intel.com>
21643 + * Asit Mallick <asit.k.mallick@intel.com>
21644 + * Modified for Xen
21648 + * entry.S contains the system-call and fault low-level handling routines.
21650 + * NOTE: This code handles signal-recognition, which happens every time
21651 + * after an interrupt and after each system call.
21653 + * Normal syscalls and interrupts don't save a full stack frame, this is
21654 + * only done for syscall tracing, signals or fork/exec et.al.
21656 + * A note on terminology:
21657 + * - top of stack: Architecture defined interrupt frame from SS to RIP
21658 + * at the top of the kernel process stack.
21659 + * - partial stack frame: partially saved registers upto R11.
21660 + * - full stack frame: Like partial stack frame, but all register saved.
21663 + * - schedule it carefully for the final hardware.
21666 +#define ASSEMBLY 1
21667 +#include <linux/linkage.h>
21668 +#include <asm/segment.h>
21669 +#include <asm/smp.h>
21670 +#include <asm/cache.h>
21671 +#include <asm/errno.h>
21672 +#include <asm/dwarf2.h>
21673 +#include <asm/calling.h>
21674 +#include <asm/asm-offsets.h>
21675 +#include <asm/msr.h>
21676 +#include <asm/unistd.h>
21677 +#include <asm/thread_info.h>
21678 +#include <asm/hw_irq.h>
21679 +#include <asm/page.h>
21680 +#include <asm/irqflags.h>
21681 +#include <asm/errno.h>
21682 +#include <xen/interface/arch-x86_64.h>
21683 +#include <xen/interface/features.h>
21685 +#include "xen_entry.S"
21689 +#ifndef CONFIG_PREEMPT
21690 +#define retint_kernel retint_restore_args
21694 +.macro TRACE_IRQS_IRETQ offset=ARGOFFSET
21695 +#ifdef CONFIG_TRACE_IRQFLAGS
21696 + bt $9,EFLAGS-\offset(%rsp) /* interrupts off? */
21703 +NMI_MASK = 0x80000000
21706 + * C code is not supposed to know about undefined top of stack. Every time
21707 + * a C function with an pt_regs argument is called from the SYSCALL based
21708 + * fast path FIXUP_TOP_OF_STACK is needed.
21709 + * RESTORE_TOP_OF_STACK syncs the syscall state after any possible ptregs
21713 + /* %rsp:at FRAMEEND */
21714 + .macro FIXUP_TOP_OF_STACK tmp
21715 + movq $__USER_CS,CS(%rsp)
21716 + movq $-1,RCX(%rsp)
21719 + .macro RESTORE_TOP_OF_STACK tmp,offset=0
21722 + .macro FAKE_STACK_FRAME child_rip
21723 + /* push in order ss, rsp, eflags, cs, rip */
21725 + pushq %rax /* ss */
21726 + CFI_ADJUST_CFA_OFFSET 8
21727 + /*CFI_REL_OFFSET ss,0*/
21728 + pushq %rax /* rsp */
21729 + CFI_ADJUST_CFA_OFFSET 8
21730 + CFI_REL_OFFSET rsp,0
21731 + pushq $(1<<9) /* eflags - interrupts on */
21732 + CFI_ADJUST_CFA_OFFSET 8
21733 + /*CFI_REL_OFFSET rflags,0*/
21734 + pushq $__KERNEL_CS /* cs */
21735 + CFI_ADJUST_CFA_OFFSET 8
21736 + /*CFI_REL_OFFSET cs,0*/
21737 + pushq \child_rip /* rip */
21738 + CFI_ADJUST_CFA_OFFSET 8
21739 + CFI_REL_OFFSET rip,0
21740 + pushq %rax /* orig rax */
21741 + CFI_ADJUST_CFA_OFFSET 8
21744 + .macro UNFAKE_STACK_FRAME
21746 + CFI_ADJUST_CFA_OFFSET -(6*8)
21749 + .macro CFI_DEFAULT_STACK start=1,adj=0
21751 + CFI_STARTPROC simple
21752 + CFI_DEF_CFA rsp,SS+8 - \adj*ARGOFFSET
21754 + CFI_DEF_CFA_OFFSET SS+8 - \adj*ARGOFFSET
21757 + CFI_REL_OFFSET r15,R15
21758 + CFI_REL_OFFSET r14,R14
21759 + CFI_REL_OFFSET r13,R13
21760 + CFI_REL_OFFSET r12,R12
21761 + CFI_REL_OFFSET rbp,RBP
21762 + CFI_REL_OFFSET rbx,RBX
21764 + CFI_REL_OFFSET r11,R11 - \adj*ARGOFFSET
21765 + CFI_REL_OFFSET r10,R10 - \adj*ARGOFFSET
21766 + CFI_REL_OFFSET r9,R9 - \adj*ARGOFFSET
21767 + CFI_REL_OFFSET r8,R8 - \adj*ARGOFFSET
21768 + CFI_REL_OFFSET rax,RAX - \adj*ARGOFFSET
21769 + CFI_REL_OFFSET rcx,RCX - \adj*ARGOFFSET
21770 + CFI_REL_OFFSET rdx,RDX - \adj*ARGOFFSET
21771 + CFI_REL_OFFSET rsi,RSI - \adj*ARGOFFSET
21772 + CFI_REL_OFFSET rdi,RDI - \adj*ARGOFFSET
21773 + CFI_REL_OFFSET rip,RIP - \adj*ARGOFFSET
21774 + /*CFI_REL_OFFSET cs,CS - \adj*ARGOFFSET*/
21775 + /*CFI_REL_OFFSET rflags,EFLAGS - \adj*ARGOFFSET*/
21776 + CFI_REL_OFFSET rsp,RSP - \adj*ARGOFFSET
21777 + /*CFI_REL_OFFSET ss,SS - \adj*ARGOFFSET*/
21781 + * Must be consistent with the definition in arch-x86/xen-x86_64.h:
21782 + * struct iret_context {
21783 + * u64 rax, r11, rcx, flags, rip, cs, rflags, rsp, ss;
21785 + * with rax, r11, and rcx being taken care of in the hypercall stub.
21787 + .macro HYPERVISOR_IRET flag
21788 + testb $3,1*8(%rsp)
21790 + testl $NMI_MASK,2*8(%rsp)
21793 + cmpb $0,(xen_features+XENFEAT_supervisor_mode_kernel)(%rip)
21796 + /* Direct iret to kernel space. Correct CS and SS. */
21801 +2: /* Slow iret via hypervisor. */
21802 + andl $~NMI_MASK, 2*8(%rsp)
21804 + jmp hypercall_page + (__HYPERVISOR_iret * 32)
21808 + * A newly forked process directly context switches into this.
21811 +ENTRY(ret_from_fork)
21812 + CFI_DEFAULT_STACK
21813 + push kernel_eflags(%rip)
21814 + CFI_ADJUST_CFA_OFFSET 4
21815 + popf # reset kernel eflags
21816 + CFI_ADJUST_CFA_OFFSET -4
21817 + call schedule_tail
21818 + GET_THREAD_INFO(%rcx)
21819 + testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT),threadinfo_flags(%rcx)
21823 + testl $3,CS-ARGOFFSET(%rsp) # from kernel_thread?
21824 + je int_ret_from_sys_call
21825 + testl $_TIF_IA32,threadinfo_flags(%rcx)
21826 + jnz int_ret_from_sys_call
21827 + RESTORE_TOP_OF_STACK %rdi,ARGOFFSET
21828 + jmp ret_from_sys_call
21831 + call syscall_trace_leave
21832 + GET_THREAD_INFO(%rcx)
21835 +END(ret_from_fork)
21838 + * initial frame state for interrupts and exceptions
21840 + .macro _frame ref
21841 + CFI_STARTPROC simple
21842 + CFI_DEF_CFA rsp,SS+8-\ref
21843 + /*CFI_REL_OFFSET ss,SS-\ref*/
21844 + CFI_REL_OFFSET rsp,RSP-\ref
21845 + /*CFI_REL_OFFSET rflags,EFLAGS-\ref*/
21846 + /*CFI_REL_OFFSET cs,CS-\ref*/
21847 + CFI_REL_OFFSET rip,RIP-\ref
21851 + * System call entry. Upto 6 arguments in registers are supported.
21853 + * SYSCALL does not save anything on the stack and does not change the
21858 + * Register setup:
21859 + * rax system call number
21861 + * rcx return address for syscall/sysret, C arg3
21864 + * r10 arg3 (--> moved to rcx for C)
21867 + * r11 eflags for syscall/sysret, temporary for C
21868 + * r12-r15,rbp,rbx saved by C code, not touched.
21870 + * Interrupts are enabled on entry.
21871 + * Only called from user space.
21873 + * XXX if we had a free scratch register we could save the RSP into the stack frame
21874 + * and report it properly in ps. Unfortunately we haven't.
21876 + * When user can change the frames always force IRET. That is because
21877 + * it deals with uncanonical addresses better. SYSRET has trouble
21878 + * with them due to bugs in both AMD and Intel CPUs.
21881 +ENTRY(system_call)
21882 + _frame (RIP-0x10)
21884 + movq %rax,ORIG_RAX-ARGOFFSET(%rsp)
21885 + GET_THREAD_INFO(%rcx)
21886 + testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP),threadinfo_flags(%rcx)
21887 + CFI_REMEMBER_STATE
21889 + cmpq $__NR_syscall_max,%rax
21892 + call *sys_call_table(,%rax,8) # XXX: rip relative
21893 + movq %rax,RAX-ARGOFFSET(%rsp)
21895 + * Syscall return path ending with SYSRET (fast path)
21896 + * Has incomplete stack frame and undefined top of stack.
21898 + .globl ret_from_sys_call
21899 +ret_from_sys_call:
21900 + movl $_TIF_ALLWORK_MASK,%edi
21901 + /* edi: flagmask */
21903 + GET_THREAD_INFO(%rcx)
21904 + XEN_BLOCK_EVENTS(%rsi)
21906 + movl threadinfo_flags(%rcx),%edx
21908 + CFI_REMEMBER_STATE
21909 + jnz sysret_careful
21911 + * sysretq will re-enable interrupts:
21914 + XEN_UNBLOCK_EVENTS(%rsi)
21915 + RESTORE_ARGS 0,8,0
21916 + HYPERVISOR_IRET VGCF_IN_SYSCALL
21918 + /* Handle reschedules */
21919 + /* edx: work, edi: workmask */
21921 + CFI_RESTORE_STATE
21922 + bt $TIF_NEED_RESCHED,%edx
21923 + jnc sysret_signal
21925 + XEN_UNBLOCK_EVENTS(%rsi)
21927 + CFI_ADJUST_CFA_OFFSET 8
21930 + CFI_ADJUST_CFA_OFFSET -8
21933 + /* Handle a signal */
21937 + XEN_UNBLOCK_EVENTS(%rsi)
21938 + testl $(_TIF_SIGPENDING|_TIF_NOTIFY_RESUME|_TIF_SINGLESTEP),%edx
21941 + /* Really a signal */
21942 + /* edx: work flags (arg3) */
21943 + leaq do_notify_resume(%rip),%rax
21944 + leaq -ARGOFFSET(%rsp),%rdi # &pt_regs -> arg1
21945 + xorl %esi,%esi # oldset -> arg2
21946 + call ptregscall_common
21947 +1: movl $_TIF_NEED_RESCHED,%edi
21948 + /* Use IRET because user could have changed frame. This
21949 + works because ptregscall_common has called FIXUP_TOP_OF_STACK. */
21950 + XEN_BLOCK_EVENTS(%rsi)
21952 + jmp int_with_check
21955 + movq $-ENOSYS,RAX-ARGOFFSET(%rsp)
21956 + jmp ret_from_sys_call
21958 + /* Do syscall tracing */
21960 + CFI_RESTORE_STATE
21962 + movq $-ENOSYS,RAX(%rsp)
21963 + FIXUP_TOP_OF_STACK %rdi
21965 + call syscall_trace_enter
21966 + LOAD_ARGS ARGOFFSET /* reload args from stack in case ptrace changed it */
21968 + cmpq $__NR_syscall_max,%rax
21970 + movq %r10,%rcx /* fixup for C */
21971 + call *sys_call_table(,%rax,8)
21972 +1: movq %rax,RAX-ARGOFFSET(%rsp)
21973 + /* Use IRET because user could have changed frame */
21974 + jmp int_ret_from_sys_call
21979 + * Syscall return path ending with IRET.
21980 + * Has correct top of stack, but partial stack frame.
21982 +ENTRY(int_ret_from_sys_call)
21983 + CFI_STARTPROC simple
21984 + CFI_DEF_CFA rsp,SS+8-ARGOFFSET
21985 + /*CFI_REL_OFFSET ss,SS-ARGOFFSET*/
21986 + CFI_REL_OFFSET rsp,RSP-ARGOFFSET
21987 + /*CFI_REL_OFFSET rflags,EFLAGS-ARGOFFSET*/
21988 + /*CFI_REL_OFFSET cs,CS-ARGOFFSET*/
21989 + CFI_REL_OFFSET rip,RIP-ARGOFFSET
21990 + CFI_REL_OFFSET rdx,RDX-ARGOFFSET
21991 + CFI_REL_OFFSET rcx,RCX-ARGOFFSET
21992 + CFI_REL_OFFSET rax,RAX-ARGOFFSET
21993 + CFI_REL_OFFSET rdi,RDI-ARGOFFSET
21994 + CFI_REL_OFFSET rsi,RSI-ARGOFFSET
21995 + CFI_REL_OFFSET r8,R8-ARGOFFSET
21996 + CFI_REL_OFFSET r9,R9-ARGOFFSET
21997 + CFI_REL_OFFSET r10,R10-ARGOFFSET
21998 + CFI_REL_OFFSET r11,R11-ARGOFFSET
21999 + XEN_BLOCK_EVENTS(%rsi)
22001 + testb $3,CS-ARGOFFSET(%rsp)
22003 + /* Need to set the proper %ss (not NULL) for ring 3 iretq */
22004 + movl $__KERNEL_DS,SS-ARGOFFSET(%rsp)
22005 + jmp retint_restore_args # retrun from ring3 kernel
22007 + movl $_TIF_ALLWORK_MASK,%edi
22008 + /* edi: mask to check */
22010 + GET_THREAD_INFO(%rcx)
22011 + movl threadinfo_flags(%rcx),%edx
22014 + andl $~TS_COMPAT,threadinfo_status(%rcx)
22015 + jmp retint_restore_args
22017 + /* Either reschedule or signal or syscall exit tracking needed. */
22018 + /* First do a reschedule test. */
22019 + /* edx: work, edi: workmask */
22021 + bt $TIF_NEED_RESCHED,%edx
22022 + jnc int_very_careful
22025 + XEN_UNBLOCK_EVENTS(%rsi)
22027 + CFI_ADJUST_CFA_OFFSET 8
22030 + CFI_ADJUST_CFA_OFFSET -8
22031 + XEN_BLOCK_EVENTS(%rsi)
22033 + jmp int_with_check
22035 + /* handle signals and tracing -- both require a full stack frame */
22039 + XEN_UNBLOCK_EVENTS(%rsi)
22041 + /* Check for syscall exit trace */
22042 + testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP),%edx
22045 + CFI_ADJUST_CFA_OFFSET 8
22046 + leaq 8(%rsp),%rdi # &ptregs -> arg1
22047 + call syscall_trace_leave
22049 + CFI_ADJUST_CFA_OFFSET -8
22050 + andl $~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP),%edi
22051 + XEN_BLOCK_EVENTS(%rsi)
22053 + jmp int_restore_rest
22056 + testl $(_TIF_NOTIFY_RESUME|_TIF_SIGPENDING|_TIF_SINGLESTEP),%edx
22058 + movq %rsp,%rdi # &ptregs -> arg1
22059 + xorl %esi,%esi # oldset -> arg2
22060 + call do_notify_resume
22061 +1: movl $_TIF_NEED_RESCHED,%edi
22064 + XEN_BLOCK_EVENTS(%rsi)
22066 + jmp int_with_check
22068 +END(int_ret_from_sys_call)
22071 + * Certain special system calls that need to save a complete full stack frame.
22074 + .macro PTREGSCALL label,func,arg
22077 + leaq \func(%rip),%rax
22078 + leaq -ARGOFFSET+8(%rsp),\arg /* 8 for return address */
22079 + jmp ptregscall_common
22085 + PTREGSCALL stub_clone, sys_clone, %r8
22086 + PTREGSCALL stub_fork, sys_fork, %rdi
22087 + PTREGSCALL stub_vfork, sys_vfork, %rdi
22088 + PTREGSCALL stub_rt_sigsuspend, sys_rt_sigsuspend, %rdx
22089 + PTREGSCALL stub_sigaltstack, sys_sigaltstack, %rdx
22090 + PTREGSCALL stub_iopl, sys_iopl, %rsi
22092 +ENTRY(ptregscall_common)
22094 + CFI_ADJUST_CFA_OFFSET -8
22095 + CFI_REGISTER rip, r11
22098 + CFI_REGISTER rip, r15
22099 + FIXUP_TOP_OF_STACK %r11
22101 + RESTORE_TOP_OF_STACK %r11
22103 + CFI_REGISTER rip, r11
22106 + CFI_ADJUST_CFA_OFFSET 8
22107 + CFI_REL_OFFSET rip, 0
22110 +END(ptregscall_common)
22112 +ENTRY(stub_execve)
22115 + CFI_ADJUST_CFA_OFFSET -8
22116 + CFI_REGISTER rip, r11
22118 + FIXUP_TOP_OF_STACK %r11
22120 + RESTORE_TOP_OF_STACK %r11
22121 + movq %rax,RAX(%rsp)
22123 + jmp int_ret_from_sys_call
22128 + * sigreturn is special because it needs to restore all registers on return.
22129 + * This cannot be done with SYSRET, so use the IRET return path instead.
22131 +ENTRY(stub_rt_sigreturn)
22134 + CFI_ADJUST_CFA_OFFSET -8
22137 + FIXUP_TOP_OF_STACK %r11
22138 + call sys_rt_sigreturn
22139 + movq %rax,RAX(%rsp) # fixme, this could be done at the higher layer
22141 + jmp int_ret_from_sys_call
22143 +END(stub_rt_sigreturn)
22145 +/* initial frame state for interrupts (and exceptions without error code) */
22146 +#define INTR_FRAME _frame (RIP-0x10); \
22147 + CFI_REL_OFFSET rcx,0; \
22148 + CFI_REL_OFFSET r11,8
22150 +/* initial frame state for exceptions with error code (and interrupts with
22151 + vector already pushed) */
22152 +#define XCPT_FRAME _frame (RIP-0x18); \
22153 + CFI_REL_OFFSET rcx,0; \
22154 + CFI_REL_OFFSET r11,8
22157 + * Interrupt exit.
22162 + CFI_DEFAULT_STACK adj=1
22163 + movl threadinfo_flags(%rcx),%edx
22165 + CFI_REMEMBER_STATE
22166 + jnz retint_careful
22167 +retint_restore_args:
22168 + movl EFLAGS-REST_SKIP(%rsp), %eax
22169 + shr $9, %eax # EAX[0] == IRET_EFLAGS.IF
22170 + XEN_GET_VCPU_INFO(%rsi)
22171 + andb evtchn_upcall_mask(%rsi),%al
22172 + andb $1,%al # EAX[0] == IRET_EFLAGS.IF & event_mask
22173 + jnz restore_all_enable_events # != 0 => enable event delivery
22174 + XEN_PUT_VCPU_INFO(%rsi)
22176 + RESTORE_ARGS 0,8,0
22177 + HYPERVISOR_IRET 0
22179 + /* edi: workmask, edx: work */
22181 + CFI_RESTORE_STATE
22182 + bt $TIF_NEED_RESCHED,%edx
22183 + jnc retint_signal
22185 + XEN_UNBLOCK_EVENTS(%rsi)
22188 + CFI_ADJUST_CFA_OFFSET 8
22191 + CFI_ADJUST_CFA_OFFSET -8
22192 + GET_THREAD_INFO(%rcx)
22193 + XEN_BLOCK_EVENTS(%rsi)
22199 + testl $(_TIF_SIGPENDING|_TIF_NOTIFY_RESUME|_TIF_SINGLESTEP),%edx
22200 + jz retint_restore_args
22202 + XEN_UNBLOCK_EVENTS(%rsi)
22204 + movq $-1,ORIG_RAX(%rsp)
22205 + xorl %esi,%esi # oldset
22206 + movq %rsp,%rdi # &pt_regs
22207 + call do_notify_resume
22209 + XEN_BLOCK_EVENTS(%rsi)
22211 + movl $_TIF_NEED_RESCHED,%edi
22212 + GET_THREAD_INFO(%rcx)
22215 +#ifdef CONFIG_PREEMPT
22216 + /* Returning to kernel space. Check if we need preemption */
22217 + /* rcx: threadinfo. interrupts off. */
22220 + cmpl $0,threadinfo_preempt_count(%rcx)
22221 + jnz retint_restore_args
22222 + bt $TIF_NEED_RESCHED,threadinfo_flags(%rcx)
22223 + jnc retint_restore_args
22224 + bt $9,EFLAGS-ARGOFFSET(%rsp) /* interrupts off? */
22225 + jnc retint_restore_args
22226 + call preempt_schedule_irq
22227 + jmp retint_kernel /* check again */
22233 +#ifndef CONFIG_XEN
22235 + * APIC interrupts.
22237 + .macro apicinterrupt num,func
22240 + CFI_ADJUST_CFA_OFFSET 8
22246 +ENTRY(thermal_interrupt)
22247 + apicinterrupt THERMAL_APIC_VECTOR,smp_thermal_interrupt
22248 +END(thermal_interrupt)
22250 +ENTRY(threshold_interrupt)
22251 + apicinterrupt THRESHOLD_APIC_VECTOR,mce_threshold_interrupt
22252 +END(threshold_interrupt)
22255 +ENTRY(reschedule_interrupt)
22256 + apicinterrupt RESCHEDULE_VECTOR,smp_reschedule_interrupt
22257 +END(reschedule_interrupt)
22259 + .macro INVALIDATE_ENTRY num
22260 +ENTRY(invalidate_interrupt\num)
22261 + apicinterrupt INVALIDATE_TLB_VECTOR_START+\num,smp_invalidate_interrupt
22262 +END(invalidate_interrupt\num)
22265 + INVALIDATE_ENTRY 0
22266 + INVALIDATE_ENTRY 1
22267 + INVALIDATE_ENTRY 2
22268 + INVALIDATE_ENTRY 3
22269 + INVALIDATE_ENTRY 4
22270 + INVALIDATE_ENTRY 5
22271 + INVALIDATE_ENTRY 6
22272 + INVALIDATE_ENTRY 7
22274 +ENTRY(call_function_interrupt)
22275 + apicinterrupt CALL_FUNCTION_VECTOR,smp_call_function_interrupt
22276 +END(call_function_interrupt)
22279 +#ifdef CONFIG_X86_LOCAL_APIC
22280 +ENTRY(apic_timer_interrupt)
22281 + apicinterrupt LOCAL_TIMER_VECTOR,smp_apic_timer_interrupt
22282 +END(apic_timer_interrupt)
22284 +ENTRY(error_interrupt)
22285 + apicinterrupt ERROR_APIC_VECTOR,smp_error_interrupt
22286 +END(error_interrupt)
22288 +ENTRY(spurious_interrupt)
22289 + apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
22290 +END(spurious_interrupt)
22292 +#endif /* !CONFIG_XEN */
22295 + * Exception entry points.
22297 + .macro zeroentry sym
22301 + movq 8(%rsp),%r11
22303 + addq $0x10,%rsp /* skip rcx and r11 */
22304 + CFI_ADJUST_CFA_OFFSET -0x10
22305 + pushq $0 /* push error code/oldrax */
22306 + CFI_ADJUST_CFA_OFFSET 8
22307 + pushq %rax /* push real oldrax to the rdi slot */
22308 + CFI_ADJUST_CFA_OFFSET 8
22309 + CFI_REL_OFFSET rax,0
22310 + leaq \sym(%rip),%rax
22315 + .macro errorentry sym
22319 + movq 8(%rsp),%r11
22321 + addq $0x10,%rsp /* rsp points to the error code */
22322 + CFI_ADJUST_CFA_OFFSET -0x10
22324 + CFI_ADJUST_CFA_OFFSET 8
22325 + CFI_REL_OFFSET rax,0
22326 + leaq \sym(%rip),%rax
22331 +#if 0 /* not XEN */
22332 + /* error code is on the stack already */
22333 + /* handle NMI like exceptions that can happen everywhere */
22334 + .macro paranoidentry sym, ist=0, irqtrace=1
22336 + movq 8(%rsp),%r11
22337 + addq $0x10,%rsp /* skip rcx and r11 */
22340 +#if 0 /* not XEN */
22342 + movl $MSR_GS_BASE,%ecx
22351 + movq %gs:pda_data_offset, %rbp
22354 + movq ORIG_RAX(%rsp),%rsi
22355 + movq $-1,ORIG_RAX(%rsp)
22357 + subq $EXCEPTION_STKSZ, per_cpu__init_tss + TSS_ist + (\ist - 1) * 8(%rbp)
22361 + addq $EXCEPTION_STKSZ, per_cpu__init_tss + TSS_ist + (\ist - 1) * 8(%rbp)
22364 + XEN_BLOCK_EVENTS(%rsi)
22371 + * "Paranoid" exit path from exception stack.
22372 + * Paranoid because this is used by NMIs and cannot take
22373 + * any kernel state for granted.
22374 + * We don't do kernel preemption checks here, because only
22375 + * NMI should be common and it does not enable IRQs and
22376 + * cannot get reschedule ticks.
22378 + * "trace" is 0 for the NMI handler only, because irq-tracing
22379 + * is fundamentally NMI-unsafe. (we cannot change the soft and
22380 + * hard flags at once, atomically)
22382 + .macro paranoidexit trace=1
22383 + /* ebx: no swapgs flag */
22384 +paranoid_exit\trace:
22385 + testl %ebx,%ebx /* swapgs needed? */
22386 + jnz paranoid_restore\trace
22387 + testl $3,CS(%rsp)
22388 + jnz paranoid_userspace\trace
22389 +paranoid_swapgs\trace:
22390 + TRACE_IRQS_IRETQ 0
22392 +paranoid_restore\trace:
22395 +paranoid_userspace\trace:
22396 + GET_THREAD_INFO(%rcx)
22397 + movl threadinfo_flags(%rcx),%ebx
22398 + andl $_TIF_WORK_MASK,%ebx
22399 + jz paranoid_swapgs\trace
22400 + movq %rsp,%rdi /* &pt_regs */
22402 + movq %rax,%rsp /* switch stack for scheduling */
22403 + testl $_TIF_NEED_RESCHED,%ebx
22404 + jnz paranoid_schedule\trace
22405 + movl %ebx,%edx /* arg3: thread flags */
22410 + xorl %esi,%esi /* arg2: oldset */
22411 + movq %rsp,%rdi /* arg1: &pt_regs */
22412 + call do_notify_resume
22417 + jmp paranoid_userspace\trace
22418 +paranoid_schedule\trace:
22428 + jmp paranoid_userspace\trace
22434 + * Exception entry point. This expects an error code/orig_rax on the stack
22435 + * and the exception handler in %rax.
22437 +ENTRY(error_entry)
22439 + CFI_REL_OFFSET rax,0
22440 + /* rdi slot contains rax, oldrax contains error code */
22443 + CFI_ADJUST_CFA_OFFSET (14*8)
22444 + movq %rsi,13*8(%rsp)
22445 + CFI_REL_OFFSET rsi,RSI
22446 + movq 14*8(%rsp),%rsi /* load rax from rdi slot */
22447 + CFI_REGISTER rax,rsi
22448 + movq %rdx,12*8(%rsp)
22449 + CFI_REL_OFFSET rdx,RDX
22450 + movq %rcx,11*8(%rsp)
22451 + CFI_REL_OFFSET rcx,RCX
22452 + movq %rsi,10*8(%rsp) /* store rax */
22453 + CFI_REL_OFFSET rax,RAX
22454 + movq %r8, 9*8(%rsp)
22455 + CFI_REL_OFFSET r8,R8
22456 + movq %r9, 8*8(%rsp)
22457 + CFI_REL_OFFSET r9,R9
22458 + movq %r10,7*8(%rsp)
22459 + CFI_REL_OFFSET r10,R10
22460 + movq %r11,6*8(%rsp)
22461 + CFI_REL_OFFSET r11,R11
22462 + movq %rbx,5*8(%rsp)
22463 + CFI_REL_OFFSET rbx,RBX
22464 + movq %rbp,4*8(%rsp)
22465 + CFI_REL_OFFSET rbp,RBP
22466 + movq %r12,3*8(%rsp)
22467 + CFI_REL_OFFSET r12,R12
22468 + movq %r13,2*8(%rsp)
22469 + CFI_REL_OFFSET r13,R13
22470 + movq %r14,1*8(%rsp)
22471 + CFI_REL_OFFSET r14,R14
22473 + CFI_REL_OFFSET r15,R15
22475 + cmpl $__KERNEL_CS,CS(%rsp)
22476 + CFI_REMEMBER_STATE
22477 + je error_kernelspace
22479 +error_call_handler:
22480 + movq %rdi, RDI(%rsp)
22481 + CFI_REL_OFFSET rdi,RDI
22483 + movq ORIG_RAX(%rsp),%rsi # get error code
22484 + movq $-1,ORIG_RAX(%rsp)
22489 + XEN_BLOCK_EVENTS(%rsi)
22491 + GET_THREAD_INFO(%rcx)
22492 + testb $3,CS-ARGOFFSET(%rsp)
22494 + movl threadinfo_flags(%rcx),%edx
22495 + movl $_TIF_WORK_MASK,%edi
22497 + jnz retint_careful
22499 + * The iret might restore flags:
22502 + jmp retint_restore_args
22506 + * We need to re-write the logic here because we don't do iretq to
22507 + * to return to user mode. It's still possible that we get trap/fault
22508 + * in the kernel (when accessing buffers pointed to by system calls,
22512 + CFI_RESTORE_STATE
22513 +error_kernelspace:
22515 + /* There are two places in the kernel that can potentially fault with
22516 + usergs. Handle them here. The exception handlers after
22517 + iret run with kernel gs again, so don't set the user space flag.
22518 + B stepping K8s sometimes report an truncated RIP for IRET
22519 + exceptions returning to compat mode. Check for these here too. */
22520 + leaq iret_label(%rip),%rbp
22521 + cmpq %rbp,RIP(%rsp)
22523 + movl %ebp,%ebp /* zero extend */
22524 + cmpq %rbp,RIP(%rsp)
22526 + cmpq $gs_change,RIP(%rsp)
22533 +ENTRY(hypervisor_callback)
22534 + zeroentry do_hypervisor_callback
22535 +END(hypervisor_callback)
22538 + * Copied from arch/xen/i386/kernel/entry.S
22540 +# A note on the "critical region" in our callback handler.
22541 +# We want to avoid stacking callback handlers due to events occurring
22542 +# during handling of the last event. To do this, we keep events disabled
22543 +# until we've done all processing. HOWEVER, we must enable events before
22544 +# popping the stack frame (can't be done atomically) and so it would still
22545 +# be possible to get enough handler activations to overflow the stack.
22546 +# Although unlikely, bugs of that kind are hard to track down, so we'd
22547 +# like to avoid the possibility.
22548 +# So, on entry to the handler we detect whether we interrupted an
22549 +# existing activation in its critical region -- if so, we pop the current
22550 +# activation and restart the handler using the previous one.
22551 +ENTRY(do_hypervisor_callback) # do_hypervisor_callback(struct *pt_regs)
22553 +# Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
22554 +# see the correct pointer to the pt_regs
22555 + movq %rdi, %rsp # we don't return, adjust the stack frame
22557 + CFI_DEFAULT_STACK
22558 +11: incl %gs:pda_irqcount
22560 + CFI_DEF_CFA_REGISTER rbp
22561 + cmovzq %gs:pda_irqstackptr,%rsp
22562 + pushq %rbp # backlink for old unwinder
22563 + call evtchn_do_upcall
22565 + CFI_DEF_CFA_REGISTER rsp
22566 + decl %gs:pda_irqcount
22569 +END(do_hypervisor_callback)
22571 +#ifdef CONFIG_X86_LOCAL_APIC
22573 + zeroentry do_nmi_callback
22574 +ENTRY(do_nmi_callback)
22578 + CFI_DEFAULT_STACK
22580 + orl $NMI_MASK,EFLAGS(%rsp)
22582 + XEN_BLOCK_EVENTS(%rsi)
22584 + GET_THREAD_INFO(%rcx)
22585 + jmp retint_restore_args
22592 +restore_all_enable_events:
22593 + CFI_DEFAULT_STACK adj=1
22595 + XEN_UNBLOCK_EVENTS(%rsi) # %rsi is already set up...
22597 +scrit: /**** START OF CRITICAL REGION ****/
22598 + XEN_TEST_PENDING(%rsi)
22599 + CFI_REMEMBER_STATE
22600 + jnz 14f # process more events if necessary...
22601 + XEN_PUT_VCPU_INFO(%rsi)
22602 + RESTORE_ARGS 0,8,0
22603 + HYPERVISOR_IRET 0
22605 + CFI_RESTORE_STATE
22606 +14: XEN_LOCKED_BLOCK_EVENTS(%rsi)
22607 + XEN_PUT_VCPU_INFO(%rsi)
22609 + movq %rsp,%rdi # set the argument again
22612 +ecrit: /**** END OF CRITICAL REGION ****/
22613 +# At this point, unlike on x86-32, we don't do the fixup to simplify the
22614 +# code and the stack frame is more complex on x86-64.
22615 +# When the kernel is interrupted in the critical section, the kernel
22616 +# will do IRET in that case, and everything will be restored at that point,
22617 +# i.e. it just resumes from the next instruction interrupted with the same context.
22619 +# Hypervisor uses this for application faults while it executes.
22620 +# We get here for two reasons:
22621 +# 1. Fault while reloading DS, ES, FS or GS
22622 +# 2. Fault while executing IRET
22623 +# Category 1 we do not need to fix up as Xen has already reloaded all segment
22624 +# registers that could be reloaded and zeroed the others.
22625 +# Category 2 we fix up by killing the current process. We cannot use the
22626 +# normal Linux return path in this case because if we use the IRET hypercall
22627 +# to pop the stack frame we end up in an infinite loop of failsafe callbacks.
22628 +# We distinguish between categories by comparing each saved segment register
22629 +# with its current contents: any discrepancy means we in category 1.
22630 +ENTRY(failsafe_callback)
22631 + _frame (RIP-0x30)
22632 + CFI_REL_OFFSET rcx, 0
22633 + CFI_REL_OFFSET r11, 8
22635 + cmpw %cx,0x10(%rsp)
22636 + CFI_REMEMBER_STATE
22639 + cmpw %cx,0x18(%rsp)
22642 + cmpw %cx,0x20(%rsp)
22645 + cmpw %cx,0x28(%rsp)
22647 + /* All segments match their saved values => Category 2 (Bad IRET). */
22650 + movq 8(%rsp),%r11
22653 + CFI_ADJUST_CFA_OFFSET -0x30
22654 + movq $11,%rdi /* SIGSEGV */
22656 + CFI_RESTORE_STATE
22657 +1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
22660 + movq 8(%rsp),%r11
22663 + CFI_ADJUST_CFA_OFFSET -0x30
22665 + CFI_ADJUST_CFA_OFFSET 8
22670 + .section __ex_table,"a"
22672 + .quad gs_change,bad_gs
22674 + .section .fixup,"ax"
22675 + /* running with kernelgs */
22677 +/* swapgs */ /* switch back to user gs */
22685 + * Create a kernel thread.
22687 + * C extern interface:
22688 + * extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
22690 + * asm input arguments:
22691 + * rdi: fn, rsi: arg, rdx: flags
22693 +ENTRY(kernel_thread)
22695 + FAKE_STACK_FRAME $child_rip
22698 + # rdi: flags, rsi: usp, rdx: will be &pt_regs
22700 + orq kernel_thread_flags(%rip),%rdi
22709 + movq %rax,RAX(%rsp)
22713 + * It isn't worth to check for reschedule here,
22714 + * so internally to the x86_64 port you can rely on kernel_thread()
22715 + * not to reschedule the child before returning, this avoids the need
22716 + * of hacks for example to fork off the per-CPU idle tasks.
22717 + * [Hopefully no generic code relies on the reschedule -AK]
22720 + UNFAKE_STACK_FRAME
22723 +ENDPROC(kernel_thread)
22726 + pushq $0 # fake return address
22729 + * Here we are in the child and the registers are set as they were
22730 + * at kernel_thread() invocation in the parent.
22739 +ENDPROC(child_rip)
22742 + * execve(). This function needs to use IRET, not SYSRET, to set up all state properly.
22744 + * C extern interface:
22745 + * extern long execve(char *name, char **argv, char **envp)
22747 + * asm input arguments:
22748 + * rdi: name, rsi: argv, rdx: envp
22750 + * We want to fallback into:
22751 + * extern long sys_execve(char *name, char **argv,char **envp, struct pt_regs regs)
22753 + * do_sys_execve asm fallback arguments:
22754 + * rdi: name, rsi: argv, rdx: envp, fake frame on the stack
22758 + FAKE_STACK_FRAME $0
22761 + movq %rax, RAX(%rsp)
22765 + jmp int_ret_from_sys_call
22767 + UNFAKE_STACK_FRAME
22772 +KPROBE_ENTRY(page_fault)
22773 + errorentry do_page_fault
22777 +ENTRY(coprocessor_error)
22778 + zeroentry do_coprocessor_error
22779 +END(coprocessor_error)
22781 +ENTRY(simd_coprocessor_error)
22782 + zeroentry do_simd_coprocessor_error
22783 +END(simd_coprocessor_error)
22785 +ENTRY(device_not_available)
22786 + zeroentry math_state_restore
22787 +END(device_not_available)
22789 + /* runs on exception stack */
22790 +KPROBE_ENTRY(debug)
22793 + CFI_ADJUST_CFA_OFFSET 8 */
22794 + zeroentry do_debug
22801 + /* runs on exception stack */
22805 + CFI_ADJUST_CFA_OFFSET 8
22806 + paranoidentry do_nmi, 0, 0
22807 +#ifdef CONFIG_TRACE_IRQFLAGS
22810 + jmp paranoid_exit1
22817 +KPROBE_ENTRY(int3)
22820 + CFI_ADJUST_CFA_OFFSET 8 */
22821 + zeroentry do_int3
22822 +/* jmp paranoid_exit1
22828 + zeroentry do_overflow
22832 + zeroentry do_bounds
22836 + zeroentry do_invalid_op
22839 +ENTRY(coprocessor_segment_overrun)
22840 + zeroentry do_coprocessor_segment_overrun
22841 +END(coprocessor_segment_overrun)
22844 + zeroentry do_reserved
22848 + /* runs on exception stack */
22849 +ENTRY(double_fault)
22851 + paranoidentry do_double_fault
22852 + jmp paranoid_exit1
22857 +ENTRY(invalid_TSS)
22858 + errorentry do_invalid_TSS
22861 +ENTRY(segment_not_present)
22862 + errorentry do_segment_not_present
22863 +END(segment_not_present)
22865 + /* runs on exception stack */
22866 +ENTRY(stack_segment)
22868 + paranoidentry do_stack_segment */
22869 + errorentry do_stack_segment
22870 +/* jmp paranoid_exit1
22872 +END(stack_segment)
22874 +KPROBE_ENTRY(general_protection)
22875 + errorentry do_general_protection
22876 +END(general_protection)
22879 +ENTRY(alignment_check)
22880 + errorentry do_alignment_check
22881 +END(alignment_check)
22883 +ENTRY(divide_error)
22884 + zeroentry do_divide_error
22887 +ENTRY(spurious_interrupt_bug)
22888 + zeroentry do_spurious_interrupt_bug
22889 +END(spurious_interrupt_bug)
22891 +#ifdef CONFIG_X86_MCE
22892 + /* runs on exception stack */
22893 +ENTRY(machine_check)
22896 + CFI_ADJUST_CFA_OFFSET 8
22897 + paranoidentry do_machine_check
22898 + jmp paranoid_exit1
22900 +END(machine_check)
22903 +/* Call softirq on interrupt stack. Interrupts are off. */
22904 +ENTRY(call_softirq)
22907 + CFI_ADJUST_CFA_OFFSET 8
22908 + CFI_REL_OFFSET rbp,0
22910 + CFI_DEF_CFA_REGISTER rbp
22911 + incl %gs:pda_irqcount
22912 + cmove %gs:pda_irqstackptr,%rsp
22913 + push %rbp # backlink for old unwinder
22914 + call __do_softirq
22916 + CFI_DEF_CFA_REGISTER rsp
22917 + CFI_ADJUST_CFA_OFFSET -8
22918 + decl %gs:pda_irqcount
22921 +ENDPROC(call_softirq)
22923 +#ifdef CONFIG_STACK_UNWIND
22924 +ENTRY(arch_unwind_init_running)
22926 + movq %r15, R15(%rdi)
22927 + movq %r14, R14(%rdi)
22929 + movq %r13, R13(%rdi)
22930 + movq %r12, R12(%rdi)
22932 + movq %rbp, RBP(%rdi)
22933 + movq %rbx, RBX(%rdi)
22934 + movq (%rsp), %rcx
22935 + movq %rax, R11(%rdi)
22936 + movq %rax, R10(%rdi)
22937 + movq %rax, R9(%rdi)
22938 + movq %rax, R8(%rdi)
22939 + movq %rax, RAX(%rdi)
22940 + movq %rax, RCX(%rdi)
22941 + movq %rax, RDX(%rdi)
22942 + movq %rax, RSI(%rdi)
22943 + movq %rax, RDI(%rdi)
22944 + movq %rax, ORIG_RAX(%rdi)
22945 + movq %rcx, RIP(%rdi)
22946 + leaq 8(%rsp), %rcx
22947 + movq $__KERNEL_CS, CS(%rdi)
22948 + movq %rax, EFLAGS(%rdi)
22949 + movq %rcx, RSP(%rdi)
22950 + movq $__KERNEL_DS, SS(%rdi)
22953 +ENDPROC(arch_unwind_init_running)
22955 Index: head-2008-11-25/arch/x86/kernel/genapic_64-xen.c
22956 ===================================================================
22957 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
22958 +++ head-2008-11-25/arch/x86/kernel/genapic_64-xen.c 2007-06-12 13:13:01.000000000 +0200
22961 + * Copyright 2004 James Cleverdon, IBM.
22962 + * Subject to the GNU Public License, v.2
22964 + * Generic APIC sub-arch probe layer.
22966 + * Hacked for x86-64 by James Cleverdon from i386 architecture code by
22967 + * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
22968 + * James Cleverdon.
22970 +#include <linux/threads.h>
22971 +#include <linux/cpumask.h>
22972 +#include <linux/string.h>
22973 +#include <linux/kernel.h>
22974 +#include <linux/ctype.h>
22975 +#include <linux/init.h>
22976 +#include <linux/module.h>
22978 +#include <asm/smp.h>
22979 +#include <asm/ipi.h>
22981 +#if defined(CONFIG_ACPI)
22982 +#include <acpi/acpi_bus.h>
22985 +/* which logical CPU number maps to which CPU (physical APIC ID) */
22986 +u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
22987 +EXPORT_SYMBOL(x86_cpu_to_apicid);
22988 +u8 x86_cpu_to_log_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
22990 +extern struct genapic apic_cluster;
22991 +extern struct genapic apic_flat;
22992 +extern struct genapic apic_physflat;
22994 +#ifndef CONFIG_XEN
22995 +struct genapic *genapic = &apic_flat;
22997 +extern struct genapic apic_xen;
22998 +struct genapic *genapic = &apic_xen;
23003 + * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode.
23005 +void __init clustered_apic_check(void)
23007 +#ifndef CONFIG_XEN
23009 + u8 clusters, max_cluster;
23011 + u8 cluster_cnt[NUM_APIC_CLUSTERS];
23012 + int max_apic = 0;
23014 +#if defined(CONFIG_ACPI)
23016 + * Some x86_64 machines use physical APIC mode regardless of how many
23017 + * procs/clusters are present (x86_64 ES7000 is an example).
23019 + if (acpi_fadt.revision > FADT2_REVISION_ID)
23020 + if (acpi_fadt.force_apic_physical_destination_mode) {
23021 + genapic = &apic_cluster;
23026 + memset(cluster_cnt, 0, sizeof(cluster_cnt));
23027 + for (i = 0; i < NR_CPUS; i++) {
23028 + id = bios_cpu_apicid[i];
23029 + if (id == BAD_APICID)
23031 + if (id > max_apic)
23033 + cluster_cnt[APIC_CLUSTERID(id)]++;
23036 + /* Don't use clustered mode on AMD platforms. */
23037 + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
23038 + genapic = &apic_physflat;
23039 +#ifndef CONFIG_HOTPLUG_CPU
23040 + /* In the CPU hotplug case we cannot use broadcast mode
23041 + because that opens a race when a CPU is removed.
23042 + Stay at physflat mode in this case.
23043 + It is bad to do this unconditionally though. Once
23044 + we have ACPI platform support for CPU hotplug
23045 + we should detect hotplug capablity from ACPI tables and
23046 + only do this when really needed. -AK */
23047 + if (max_apic <= 8)
23048 + genapic = &apic_flat;
23056 + for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
23057 + if (cluster_cnt[i] > 0) {
23059 + if (cluster_cnt[i] > max_cluster)
23060 + max_cluster = cluster_cnt[i];
23065 + * If we have clusters <= 1 and CPUs <= 8 in cluster 0, then flat mode,
23066 + * else if max_cluster <= 4 and cluster_cnt[15] == 0, clustered logical
23067 + * else physical mode.
23068 + * (We don't use lowest priority delivery + HW APIC IRQ steering, so
23069 + * can ignore the clustered logical case and go straight to physical.)
23071 + if (clusters <= 1 && max_cluster <= 8 && cluster_cnt[0] == max_cluster) {
23072 +#ifdef CONFIG_HOTPLUG_CPU
23073 + /* Don't use APIC shortcuts in CPU hotplug to avoid races */
23074 + genapic = &apic_physflat;
23076 + genapic = &apic_flat;
23079 + genapic = &apic_cluster;
23083 + /* hardcode to xen apic functions */
23084 + genapic = &apic_xen;
23086 + printk(KERN_INFO "Setting APIC routing to %s\n", genapic->name);
23089 +/* Same for both flat and clustered. */
23092 +extern void xen_send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest);
23095 +void send_IPI_self(int vector)
23097 +#ifndef CONFIG_XEN
23098 + __send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
23100 + xen_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
23103 Index: head-2008-11-25/arch/x86/kernel/genapic_xen_64.c
23104 ===================================================================
23105 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
23106 +++ head-2008-11-25/arch/x86/kernel/genapic_xen_64.c 2007-06-12 13:13:01.000000000 +0200
23109 + * Copyright 2004 James Cleverdon, IBM.
23110 + * Subject to the GNU Public License, v.2
23112 + * Xen APIC subarch code. Maximum 8 CPUs, logical delivery.
23114 + * Hacked for x86-64 by James Cleverdon from i386 architecture code by
23115 + * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
23116 + * James Cleverdon.
23118 + * Hacked to pieces for Xen by Chris Wright.
23120 +#include <linux/threads.h>
23121 +#include <linux/cpumask.h>
23122 +#include <linux/string.h>
23123 +#include <linux/kernel.h>
23124 +#include <linux/ctype.h>
23125 +#include <linux/init.h>
23126 +#ifdef CONFIG_XEN_PRIVILEGED_GUEST
23127 +#include <asm/smp.h>
23128 +#include <asm/ipi.h>
23130 +#include <asm/apic.h>
23131 +#include <asm/apicdef.h>
23132 +#include <asm/genapic.h>
23134 +#include <xen/evtchn.h>
23136 +DECLARE_PER_CPU(int, ipi_to_irq[NR_IPIS]);
23138 +static inline void __send_IPI_one(unsigned int cpu, int vector)
23140 + int irq = per_cpu(ipi_to_irq, cpu)[vector];
23142 + notify_remote_via_irq(irq);
23145 +void xen_send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest)
23149 + switch (shortcut) {
23150 + case APIC_DEST_SELF:
23151 + __send_IPI_one(smp_processor_id(), vector);
23153 + case APIC_DEST_ALLBUT:
23154 + for (cpu = 0; cpu < NR_CPUS; ++cpu) {
23155 + if (cpu == smp_processor_id())
23157 + if (cpu_isset(cpu, cpu_online_map)) {
23158 + __send_IPI_one(cpu, vector);
23162 + case APIC_DEST_ALLINC:
23163 + for (cpu = 0; cpu < NR_CPUS; ++cpu) {
23164 + if (cpu_isset(cpu, cpu_online_map)) {
23165 + __send_IPI_one(cpu, vector);
23170 + printk("XXXXXX __send_IPI_shortcut %08x vector %d\n", shortcut,
23176 +static cpumask_t xen_target_cpus(void)
23178 + return cpu_online_map;
23182 + * Set up the logical destination ID.
23183 + * Do nothing, not called now.
23185 +static void xen_init_apic_ldr(void)
23187 + Dprintk("%s\n", __FUNCTION__);
23191 +static void xen_send_IPI_allbutself(int vector)
23194 + * if there are no other CPUs in the system then
23195 + * we get an APIC send error if we try to broadcast.
23196 + * thus we have to avoid sending IPIs in this case.
23198 + Dprintk("%s\n", __FUNCTION__);
23199 + if (num_online_cpus() > 1)
23200 + xen_send_IPI_shortcut(APIC_DEST_ALLBUT, vector, APIC_DEST_LOGICAL);
23203 +static void xen_send_IPI_all(int vector)
23205 + Dprintk("%s\n", __FUNCTION__);
23206 + xen_send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
23209 +static void xen_send_IPI_mask(cpumask_t cpumask, int vector)
23211 + unsigned long mask = cpus_addr(cpumask)[0];
23212 + unsigned int cpu;
23213 + unsigned long flags;
23215 + Dprintk("%s\n", __FUNCTION__);
23216 + local_irq_save(flags);
23217 + WARN_ON(mask & ~cpus_addr(cpu_online_map)[0]);
23219 + for (cpu = 0; cpu < NR_CPUS; ++cpu) {
23220 + if (cpu_isset(cpu, cpumask)) {
23221 + __send_IPI_one(cpu, vector);
23224 + local_irq_restore(flags);
23227 +#ifdef CONFIG_XEN_PRIVILEGED_GUEST
23228 +static int xen_apic_id_registered(void)
23230 + /* better be set */
23231 + Dprintk("%s\n", __FUNCTION__);
23232 + return physid_isset(smp_processor_id(), phys_cpu_present_map);
23236 +static unsigned int xen_cpu_mask_to_apicid(cpumask_t cpumask)
23238 + Dprintk("%s\n", __FUNCTION__);
23239 + return cpus_addr(cpumask)[0] & APIC_ALL_CPUS;
23242 +static unsigned int phys_pkg_id(int index_msb)
23246 + Dprintk("%s\n", __FUNCTION__);
23247 + ebx = cpuid_ebx(1);
23248 + return ((ebx >> 24) & 0xFF) >> index_msb;
23251 +struct genapic apic_xen = {
23253 +#ifdef CONFIG_XEN_PRIVILEGED_GUEST
23254 + .int_delivery_mode = dest_LowestPrio,
23256 + .int_dest_mode = (APIC_DEST_LOGICAL != 0),
23257 + .int_delivery_dest = APIC_DEST_LOGICAL | APIC_DM_LOWEST,
23258 + .target_cpus = xen_target_cpus,
23259 +#ifdef CONFIG_XEN_PRIVILEGED_GUEST
23260 + .apic_id_registered = xen_apic_id_registered,
23262 + .init_apic_ldr = xen_init_apic_ldr,
23263 + .send_IPI_all = xen_send_IPI_all,
23264 + .send_IPI_allbutself = xen_send_IPI_allbutself,
23265 + .send_IPI_mask = xen_send_IPI_mask,
23266 + .cpu_mask_to_apicid = xen_cpu_mask_to_apicid,
23267 + .phys_pkg_id = phys_pkg_id,
23269 Index: head-2008-11-25/arch/x86/kernel/head_64-xen.S
23270 ===================================================================
23271 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
23272 +++ head-2008-11-25/arch/x86/kernel/head_64-xen.S 2007-08-06 15:10:49.000000000 +0200
23275 + * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
23277 + * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
23278 + * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
23279 + * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
23280 + * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
23282 + * $Id: head.S,v 1.49 2002/03/19 17:39:25 ak Exp $
23284 + * Jun Nakajima <jun.nakajima@intel.com>
23285 + * Modified for Xen
23289 +#include <linux/linkage.h>
23290 +#include <linux/threads.h>
23291 +#include <linux/init.h>
23292 +#include <linux/elfnote.h>
23293 +#include <asm/desc.h>
23294 +#include <asm/segment.h>
23295 +#include <asm/page.h>
23296 +#include <asm/msr.h>
23297 +#include <asm/cache.h>
23298 +#include <asm/dwarf2.h>
23299 +#include <xen/interface/elfnote.h>
23301 + .section .bootstrap.text, "ax", @progbits
23303 + .globl startup_64
23305 + movq $(init_thread_union+THREAD_SIZE-8),%rsp
23307 + /* rsi is pointer to startup info structure.
23310 + pushq $0 # fake return address
23311 + jmp x86_64_start_kernel
23313 +#ifdef CONFIG_ACPI_SLEEP
23317 + .word gdt_end-cpu_gdt_table-1
23318 + .long cpu_gdt_table-__START_KERNEL_map
23324 +#define NEXT_PAGE(name) \
23325 + $page = $page + 1; \
23326 + .org $page * 0x1000; \
23327 + phys_##name = $page * 0x1000 + __PHYSICAL_START; \
23330 +NEXT_PAGE(init_level4_pgt)
23331 + /* This gets initialized in x86_64_start_kernel */
23333 +NEXT_PAGE(init_level4_user_pgt)
23335 + * We update two pgd entries to make kernel and user pgd consistent
23336 + * at pgd_populate(). It can be used for kernel modules. So we place
23337 + * this page here for those cases to avoid memory corruption.
23338 + * We also use this page to establish the initial mapping for the
23343 +NEXT_PAGE(level3_kernel_pgt)
23347 + * This is used for vsyscall area mapping as we have a different
23348 + * level4 page table for user.
23350 +NEXT_PAGE(level3_user_pgt)
23353 +NEXT_PAGE(level2_kernel_pgt)
23356 +NEXT_PAGE(hypercall_page)
23358 + .rept 0x1000 / 0x20
23359 + .skip 1 /* push %rcx */
23360 + CFI_ADJUST_CFA_OFFSET 8
23361 + CFI_REL_OFFSET rcx,0
23362 + .skip 2 /* push %r11 */
23363 + CFI_ADJUST_CFA_OFFSET 8
23364 + CFI_REL_OFFSET rcx,0
23365 + .skip 5 /* mov $#,%eax */
23366 + .skip 2 /* syscall */
23367 + .skip 2 /* pop %r11 */
23368 + CFI_ADJUST_CFA_OFFSET -8
23370 + .skip 1 /* pop %rcx */
23371 + CFI_ADJUST_CFA_OFFSET -8
23373 + .align 0x20,0 /* ret */
23380 +/* Just dummy symbol to allow compilation. Not used in sleep path */
23381 +#ifdef CONFIG_ACPI_SLEEP
23383 +ENTRY(wakeup_level4_pgt)
23390 + .globl cpu_gdt_descr
23392 + .word gdt_end-cpu_gdt_table-1
23394 + .quad cpu_gdt_table
23402 +/* We need valid kernel segments for data and code in long mode too
23403 + * IRET will check the segment types kkeil 2000/10/28
23404 + * Also sysret mandates a special GDT layout
23407 + .section .data.page_aligned, "aw"
23410 +/* The TLS descriptors are currently at a different place compared to i386.
23411 + Hopefully nobody expects them at a fixed place (Wine?) */
23413 +ENTRY(cpu_gdt_table)
23414 + .quad 0x0000000000000000 /* NULL descriptor */
23415 + .quad 0x0 /* unused */
23416 + .quad 0x00af9a000000ffff /* __KERNEL_CS */
23417 + .quad 0x00cf92000000ffff /* __KERNEL_DS */
23418 + .quad 0x00cffa000000ffff /* __USER32_CS */
23419 + .quad 0x00cff2000000ffff /* __USER_DS, __USER32_DS */
23420 + .quad 0x00affa000000ffff /* __USER_CS */
23421 + .quad 0x00cf9a000000ffff /* __KERNEL32_CS */
23422 + .quad 0,0 /* TSS */
23423 + .quad 0,0 /* LDT */
23424 + .quad 0,0,0 /* three TLS descriptors */
23425 + .quad 0 /* unused */
23427 + /* asm/segment.h:GDT_ENTRIES must match this */
23428 + /* This should be a multiple of the cache line size */
23429 + /* GDTs of other CPUs are now dynamically allocated */
23431 + /* zero the remaining page */
23432 + .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
23434 + .section .bss.page_aligned, "aw", @nobits
23436 +ENTRY(empty_zero_page)
23439 +#if CONFIG_XEN_COMPAT <= 0x030002
23441 + * __xen_guest information
23444 + .if (\value) < 0 || (\value) >= 0x10
23445 + utoh (((\value)>>4)&0x0fffffffffffffff)
23447 + .if ((\value) & 0xf) < 10
23448 + .byte '0' + ((\value) & 0xf)
23450 + .byte 'A' + ((\value) & 0xf) - 10
23454 +.section __xen_guest
23455 + .ascii "GUEST_OS=linux,GUEST_VER=2.6"
23456 + .ascii ",XEN_VER=xen-3.0"
23457 + .ascii ",VIRT_BASE=0x"
23458 + utoh __START_KERNEL_map
23459 + .ascii ",ELF_PADDR_OFFSET=0x"
23460 + utoh __START_KERNEL_map
23461 + .ascii ",VIRT_ENTRY=0x"
23462 + utoh (__START_KERNEL_map + __PHYSICAL_START)
23463 + .ascii ",HYPERCALL_PAGE=0x"
23464 + utoh (phys_hypercall_page >> PAGE_SHIFT)
23465 + .ascii ",FEATURES=writable_page_tables"
23466 + .ascii "|writable_descriptor_tables"
23467 + .ascii "|auto_translated_physmap"
23468 + .ascii "|supervisor_mode_kernel"
23469 + .ascii ",LOADER=generic"
23471 +#endif /* CONFIG_XEN_COMPAT <= 0x030002 */
23473 + ELFNOTE(Xen, XEN_ELFNOTE_GUEST_OS, .asciz, "linux")
23474 + ELFNOTE(Xen, XEN_ELFNOTE_GUEST_VERSION, .asciz, "2.6")
23475 + ELFNOTE(Xen, XEN_ELFNOTE_XEN_VERSION, .asciz, "xen-3.0")
23476 + ELFNOTE(Xen, XEN_ELFNOTE_VIRT_BASE, .quad, __START_KERNEL_map)
23477 +#if CONFIG_XEN_COMPAT <= 0x030002
23478 + ELFNOTE(Xen, XEN_ELFNOTE_PADDR_OFFSET, .quad, __START_KERNEL_map)
23480 + ELFNOTE(Xen, XEN_ELFNOTE_PADDR_OFFSET, .quad, 0)
23482 + ELFNOTE(Xen, XEN_ELFNOTE_ENTRY, .quad, startup_64)
23483 + ELFNOTE(Xen, XEN_ELFNOTE_HYPERCALL_PAGE, .quad, hypercall_page)
23484 + ELFNOTE(Xen, XEN_ELFNOTE_L1_MFN_VALID, .quad, _PAGE_PRESENT,_PAGE_PRESENT)
23485 + ELFNOTE(Xen, XEN_ELFNOTE_FEATURES, .asciz, "writable_page_tables|writable_descriptor_tables|auto_translated_physmap|pae_pgdir_above_4gb|supervisor_mode_kernel")
23486 + ELFNOTE(Xen, XEN_ELFNOTE_LOADER, .asciz, "generic")
23487 + ELFNOTE(Xen, XEN_ELFNOTE_SUSPEND_CANCEL, .long, 1)
23488 Index: head-2008-11-25/arch/x86/kernel/head64-xen.c
23489 ===================================================================
23490 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
23491 +++ head-2008-11-25/arch/x86/kernel/head64-xen.c 2007-06-12 13:13:01.000000000 +0200
23494 + * linux/arch/x86_64/kernel/head64.c -- prepare to run common code
23496 + * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
23498 + * Jun Nakajima <jun.nakajima@intel.com>
23499 + * Modified for Xen.
23502 +#include <linux/init.h>
23503 +#include <linux/linkage.h>
23504 +#include <linux/types.h>
23505 +#include <linux/kernel.h>
23506 +#include <linux/string.h>
23507 +#include <linux/percpu.h>
23508 +#include <linux/module.h>
23510 +#include <asm/processor.h>
23511 +#include <asm/proto.h>
23512 +#include <asm/smp.h>
23513 +#include <asm/bootsetup.h>
23514 +#include <asm/setup.h>
23515 +#include <asm/desc.h>
23516 +#include <asm/pgtable.h>
23517 +#include <asm/sections.h>
23519 +unsigned long start_pfn;
23521 +/* Don't add a printk in there. printk relies on the PDA which is not initialized
23524 +static void __init clear_bss(void)
23526 + memset(__bss_start, 0,
23527 + (unsigned long) __bss_stop - (unsigned long) __bss_start);
23531 +#define NEW_CL_POINTER 0x228 /* Relative to real mode data */
23532 +#define OLD_CL_MAGIC_ADDR 0x90020
23533 +#define OLD_CL_MAGIC 0xA33F
23534 +#define OLD_CL_BASE_ADDR 0x90000
23535 +#define OLD_CL_OFFSET 0x90022
23537 +extern char saved_command_line[];
23539 +static void __init copy_bootdata(char *real_mode_data)
23541 +#ifndef CONFIG_XEN
23543 + char * command_line;
23545 + memcpy(x86_boot_params, real_mode_data, BOOT_PARAM_SIZE);
23546 + new_data = *(int *) (x86_boot_params + NEW_CL_POINTER);
23548 + if (OLD_CL_MAGIC != * (u16 *) OLD_CL_MAGIC_ADDR) {
23549 + printk("so old bootloader that it does not support commandline?!\n");
23552 + new_data = OLD_CL_BASE_ADDR + * (u16 *) OLD_CL_OFFSET;
23553 + printk("old bootloader convention, maybe loadlin?\n");
23555 + command_line = (char *) ((u64)(new_data));
23556 + memcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
23560 + if ((max_cmdline = MAX_GUEST_CMDLINE) > COMMAND_LINE_SIZE)
23561 + max_cmdline = COMMAND_LINE_SIZE;
23562 + memcpy(saved_command_line, xen_start_info->cmd_line, max_cmdline);
23563 + saved_command_line[max_cmdline-1] = '\0';
23565 + printk("Bootdata ok (command line is %s)\n", saved_command_line);
23568 +static void __init setup_boot_cpu_data(void)
23570 + unsigned int dummy, eax;
23572 + /* get vendor info */
23573 + cpuid(0, (unsigned int *)&boot_cpu_data.cpuid_level,
23574 + (unsigned int *)&boot_cpu_data.x86_vendor_id[0],
23575 + (unsigned int *)&boot_cpu_data.x86_vendor_id[8],
23576 + (unsigned int *)&boot_cpu_data.x86_vendor_id[4]);
23578 + /* get cpu type */
23579 + cpuid(1, &eax, &dummy, &dummy,
23580 + (unsigned int *) &boot_cpu_data.x86_capability);
23581 + boot_cpu_data.x86 = (eax >> 8) & 0xf;
23582 + boot_cpu_data.x86_model = (eax >> 4) & 0xf;
23583 + boot_cpu_data.x86_mask = eax & 0xf;
23586 +#include <xen/interface/memory.h>
23587 +unsigned long *machine_to_phys_mapping;
23588 +EXPORT_SYMBOL(machine_to_phys_mapping);
23589 +unsigned int machine_to_phys_order;
23590 +EXPORT_SYMBOL(machine_to_phys_order);
23592 +void __init x86_64_start_kernel(char * real_mode_data)
23594 + struct xen_machphys_mapping mapping;
23595 + unsigned long machine_to_phys_nr_ents;
23599 + setup_xen_features();
23601 + xen_start_info = (struct start_info *)real_mode_data;
23602 + if (!xen_feature(XENFEAT_auto_translated_physmap))
23603 + phys_to_machine_mapping =
23604 + (unsigned long *)xen_start_info->mfn_list;
23605 + start_pfn = (__pa(xen_start_info->pt_base) >> PAGE_SHIFT) +
23606 + xen_start_info->nr_pt_frames;
23608 + machine_to_phys_mapping = (unsigned long *)MACH2PHYS_VIRT_START;
23609 + machine_to_phys_nr_ents = MACH2PHYS_NR_ENTRIES;
23610 + if (HYPERVISOR_memory_op(XENMEM_machphys_mapping, &mapping) == 0) {
23611 + machine_to_phys_mapping = (unsigned long *)mapping.v_start;
23612 + machine_to_phys_nr_ents = mapping.max_mfn + 1;
23614 + while ((1UL << machine_to_phys_order) < machine_to_phys_nr_ents )
23615 + machine_to_phys_order++;
23618 + for (i = 0; i < 256; i++)
23619 + set_intr_gate(i, early_idt_handler);
23620 + asm volatile("lidt %0" :: "m" (idt_descr));
23624 + * This must be called really, really early:
23628 + for (i = 0; i < NR_CPUS; i++)
23629 + cpu_pda(i) = &boot_cpu_pda[i];
23632 + copy_bootdata(real_mode_data);
23634 + cpu_set(0, cpu_online_map);
23636 + s = strstr(saved_command_line, "earlyprintk=");
23638 + setup_early_printk(strchr(s, '=') + 1);
23639 +#ifdef CONFIG_NUMA
23640 + s = strstr(saved_command_line, "numa=");
23644 +#ifdef CONFIG_X86_IO_APIC
23645 + if (strstr(saved_command_line, "disableapic"))
23646 + disable_apic = 1;
23648 + /* You need early console to see that */
23649 + if (__pa_symbol(&_end) >= KERNEL_TEXT_SIZE)
23650 + panic("Kernel too big for kernel mapping\n");
23652 + setup_boot_cpu_data();
23655 Index: head-2008-11-25/arch/x86/kernel/io_apic_64-xen.c
23656 ===================================================================
23657 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
23658 +++ head-2008-11-25/arch/x86/kernel/io_apic_64-xen.c 2008-11-25 12:22:34.000000000 +0100
23661 + * Intel IO-APIC support for multi-Pentium hosts.
23663 + * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
23665 + * Many thanks to Stig Venaas for trying out countless experimental
23666 + * patches and reporting/debugging problems patiently!
23668 + * (c) 1999, Multiple IO-APIC support, developed by
23669 + * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
23670 + * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
23671 + * further tested and cleaned up by Zach Brown <zab@redhat.com>
23672 + * and Ingo Molnar <mingo@redhat.com>
23675 + * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
23676 + * thanks to Eric Gilmore
23677 + * and Rolf G. Tews
23678 + * for testing these extensively
23679 + * Paul Diefenbaugh : Added full ACPI support
23682 +#include <linux/mm.h>
23683 +#include <linux/interrupt.h>
23684 +#include <linux/init.h>
23685 +#include <linux/delay.h>
23686 +#include <linux/sched.h>
23687 +#include <linux/smp_lock.h>
23688 +#include <linux/mc146818rtc.h>
23689 +#include <linux/acpi.h>
23690 +#include <linux/sysdev.h>
23691 +#ifdef CONFIG_ACPI
23692 +#include <acpi/acpi_bus.h>
23695 +#include <asm/io.h>
23696 +#include <asm/smp.h>
23697 +#include <asm/desc.h>
23698 +#include <asm/proto.h>
23699 +#include <asm/mach_apic.h>
23700 +#include <asm/acpi.h>
23701 +#include <asm/dma.h>
23702 +#include <asm/nmi.h>
23704 +#define __apicdebuginit __init
23706 +int sis_apic_bug; /* not actually supported, dummy for compile */
23708 +static int no_timer_check;
23710 +int disable_timer_pin_1 __initdata;
23712 +#ifndef CONFIG_XEN
23713 +int timer_over_8254 __initdata = 0;
23715 +/* Where if anywhere is the i8259 connect in external int mode */
23716 +static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
23719 +static DEFINE_SPINLOCK(ioapic_lock);
23720 +static DEFINE_SPINLOCK(vector_lock);
23723 + * # of IRQ routing registers
23725 +int nr_ioapic_registers[MAX_IO_APICS];
23728 + * Rough estimation of how many shared IRQs there are, can
23729 + * be changed anytime.
23731 +#define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
23732 +#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
23735 + * This is performance-critical, we want to do it O(1)
23737 + * the indexing order of this array favors 1:1 mappings
23738 + * between pins and IRQs.
23741 +static struct irq_pin_list {
23742 + short apic, pin, next;
23743 +} irq_2_pin[PIN_MAP_SIZE];
23745 +int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
23746 +#ifdef CONFIG_PCI_MSI
23747 +#define vector_to_irq(vector) \
23748 + (platform_legacy_irq(vector) ? vector : vector_irq[vector])
23750 +#define vector_to_irq(vector) (vector)
23755 +#include <xen/interface/xen.h>
23756 +#include <xen/interface/physdev.h>
23757 +#include <xen/evtchn.h>
23760 +#define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
23761 +#define disable_8259A_irq(_irq) ((void)0)
23762 +#define i8259A_irq_pending(_irq) (0)
23764 +unsigned long io_apic_irqs;
23766 +static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
23768 + struct physdev_apic apic_op;
23771 + apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
23772 + apic_op.reg = reg;
23773 + ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
23776 + return apic_op.value;
23779 +static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
23781 + struct physdev_apic apic_op;
23783 + apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
23784 + apic_op.reg = reg;
23785 + apic_op.value = value;
23786 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
23789 +#define io_apic_read(a,r) xen_io_apic_read(a,r)
23790 +#define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
23792 +#define clear_IO_APIC() ((void)0)
23797 +static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
23799 + unsigned long flags;
23800 + unsigned int dest;
23803 + cpus_and(tmp, mask, cpu_online_map);
23804 + if (cpus_empty(tmp))
23805 + tmp = TARGET_CPUS;
23807 + cpus_and(mask, tmp, CPU_MASK_ALL);
23809 + dest = cpu_mask_to_apicid(mask);
23812 + * Only the high 8 bits are valid.
23814 + dest = SET_APIC_LOGICAL_ID(dest);
23816 + spin_lock_irqsave(&ioapic_lock, flags);
23817 + __DO_ACTION(1, = dest, )
23818 + set_irq_info(irq, mask);
23819 + spin_unlock_irqrestore(&ioapic_lock, flags);
23823 +#endif /* !CONFIG_XEN */
23826 + * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
23827 + * shared ISA-space IRQs, so we have to support them. We are super
23828 + * fast in the common case, and fast for shared ISA-space IRQs.
23830 +static void add_pin_to_irq(unsigned int irq, int apic, int pin)
23832 + static int first_free_entry = NR_IRQS;
23833 + struct irq_pin_list *entry = irq_2_pin + irq;
23835 + BUG_ON(irq >= NR_IRQS);
23836 + while (entry->next)
23837 + entry = irq_2_pin + entry->next;
23839 + if (entry->pin != -1) {
23840 + entry->next = first_free_entry;
23841 + entry = irq_2_pin + entry->next;
23842 + if (++first_free_entry >= PIN_MAP_SIZE)
23843 + panic("io_apic.c: ran out of irq_2_pin entries!");
23845 + entry->apic = apic;
23846 + entry->pin = pin;
23849 +#ifndef CONFIG_XEN
23850 +#define __DO_ACTION(R, ACTION, FINAL) \
23854 + struct irq_pin_list *entry = irq_2_pin + irq; \
23856 + BUG_ON(irq >= NR_IRQS); \
23858 + unsigned int reg; \
23859 + pin = entry->pin; \
23862 + reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
23864 + io_apic_modify(entry->apic, reg); \
23865 + if (!entry->next) \
23867 + entry = irq_2_pin + entry->next; \
23872 +#define DO_ACTION(name,R,ACTION, FINAL) \
23874 + static void name##_IO_APIC_irq (unsigned int irq) \
23875 + __DO_ACTION(R, ACTION, FINAL)
23877 +DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
23879 +DO_ACTION( __unmask, 0, &= 0xfffeffff, )
23882 +static void mask_IO_APIC_irq (unsigned int irq)
23884 + unsigned long flags;
23886 + spin_lock_irqsave(&ioapic_lock, flags);
23887 + __mask_IO_APIC_irq(irq);
23888 + spin_unlock_irqrestore(&ioapic_lock, flags);
23891 +static void unmask_IO_APIC_irq (unsigned int irq)
23893 + unsigned long flags;
23895 + spin_lock_irqsave(&ioapic_lock, flags);
23896 + __unmask_IO_APIC_irq(irq);
23897 + spin_unlock_irqrestore(&ioapic_lock, flags);
23900 +static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
23902 + struct IO_APIC_route_entry entry;
23903 + unsigned long flags;
23905 + /* Check delivery_mode to be sure we're not clearing an SMI pin */
23906 + spin_lock_irqsave(&ioapic_lock, flags);
23907 + *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
23908 + *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
23909 + spin_unlock_irqrestore(&ioapic_lock, flags);
23910 + if (entry.delivery_mode == dest_SMI)
23913 + * Disable it in the IO-APIC irq-routing table:
23915 + memset(&entry, 0, sizeof(entry));
23917 + spin_lock_irqsave(&ioapic_lock, flags);
23918 + io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
23919 + io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
23920 + spin_unlock_irqrestore(&ioapic_lock, flags);
23923 +static void clear_IO_APIC (void)
23927 + for (apic = 0; apic < nr_ioapics; apic++)
23928 + for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
23929 + clear_IO_APIC_pin(apic, pin);
23932 +#endif /* !CONFIG_XEN */
23934 +static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
23937 + * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
23938 + * specific CPU-side IRQs.
23941 +#define MAX_PIRQS 8
23942 +static int pirq_entries [MAX_PIRQS];
23943 +static int pirqs_enabled;
23944 +int skip_ioapic_setup;
23947 +/* dummy parsing: see setup.c */
23949 +static int __init disable_ioapic_setup(char *str)
23951 + skip_ioapic_setup = 1;
23955 +static int __init enable_ioapic_setup(char *str)
23957 + ioapic_force = 1;
23958 + skip_ioapic_setup = 0;
23962 +__setup("noapic", disable_ioapic_setup);
23963 +__setup("apic", enable_ioapic_setup);
23965 +#ifndef CONFIG_XEN
23966 +static int __init setup_disable_8254_timer(char *s)
23968 + timer_over_8254 = -1;
23971 +static int __init setup_enable_8254_timer(char *s)
23973 + timer_over_8254 = 2;
23977 +__setup("disable_8254_timer", setup_disable_8254_timer);
23978 +__setup("enable_8254_timer", setup_enable_8254_timer);
23979 +#endif /* !CONFIG_XEN */
23981 +#include <asm/pci-direct.h>
23982 +#include <linux/pci_ids.h>
23983 +#include <linux/pci.h>
23986 +#ifdef CONFIG_ACPI
23988 +static int nvidia_hpet_detected __initdata;
23990 +static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
23992 + nvidia_hpet_detected = 1;
23997 +/* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
23998 + off. Check for an Nvidia or VIA PCI bridge and turn it off.
23999 + Use pci direct infrastructure because this runs before the PCI subsystem.
24001 + Can be overwritten with "apic"
24003 + And another hack to disable the IOMMU on VIA chipsets.
24005 + ... and others. Really should move this somewhere else.
24007 + Kludge-O-Rama. */
24008 +void __init check_ioapic(void)
24010 + int num,slot,func;
24011 + /* Poor man's PCI discovery */
24012 + for (num = 0; num < 32; num++) {
24013 + for (slot = 0; slot < 32; slot++) {
24014 + for (func = 0; func < 8; func++) {
24018 + class = read_pci_config(num,slot,func,
24019 + PCI_CLASS_REVISION);
24020 + if (class == 0xffffffff)
24023 + if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
24026 + vendor = read_pci_config(num, slot, func,
24028 + vendor &= 0xffff;
24029 + switch (vendor) {
24030 + case PCI_VENDOR_ID_VIA:
24031 +#ifdef CONFIG_IOMMU
24032 + if ((end_pfn > MAX_DMA32_PFN ||
24034 + !iommu_aperture_allowed) {
24036 + "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
24037 + iommu_aperture_disabled = 1;
24041 + case PCI_VENDOR_ID_NVIDIA:
24042 +#ifdef CONFIG_ACPI
24044 + * All timer overrides on Nvidia are
24045 + * wrong unless HPET is enabled.
24047 + nvidia_hpet_detected = 0;
24048 + acpi_table_parse(ACPI_HPET,
24049 + nvidia_hpet_check);
24050 + if (nvidia_hpet_detected == 0) {
24051 + acpi_skip_timer_override = 1;
24052 + printk(KERN_INFO "Nvidia board "
24053 + "detected. Ignoring ACPI "
24054 + "timer override.\n");
24057 + /* RED-PEN skip them on mptables too? */
24059 + case PCI_VENDOR_ID_ATI:
24061 + /* This should be actually default, but
24062 + for 2.6.16 let's do it for ATI only where
24063 + it's really needed. */
24064 +#ifndef CONFIG_XEN
24065 + if (timer_over_8254 == 1) {
24066 + timer_over_8254 = 0;
24068 + "ATI board detected. Disabling timer routing over 8254.\n");
24075 + /* No multi-function device? */
24076 + type = read_pci_config_byte(num,slot,func,
24077 + PCI_HEADER_TYPE);
24078 + if (!(type & 0x80))
24085 +static int __init ioapic_pirq_setup(char *str)
24088 + int ints[MAX_PIRQS+1];
24090 + get_options(str, ARRAY_SIZE(ints), ints);
24092 + for (i = 0; i < MAX_PIRQS; i++)
24093 + pirq_entries[i] = -1;
24095 + pirqs_enabled = 1;
24096 + apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
24098 + if (ints[0] < MAX_PIRQS)
24101 + for (i = 0; i < max; i++) {
24102 + apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
24104 + * PIRQs are mapped upside down, usually.
24106 + pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
24111 +__setup("pirq=", ioapic_pirq_setup);
24114 + * Find the IRQ entry number of a certain pin.
24116 +static int find_irq_entry(int apic, int pin, int type)
24120 + for (i = 0; i < mp_irq_entries; i++)
24121 + if (mp_irqs[i].mpc_irqtype == type &&
24122 + (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
24123 + mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
24124 + mp_irqs[i].mpc_dstirq == pin)
24130 +#ifndef CONFIG_XEN
24132 + * Find the pin to which IRQ[irq] (ISA) is connected
24134 +static int __init find_isa_irq_pin(int irq, int type)
24138 + for (i = 0; i < mp_irq_entries; i++) {
24139 + int lbus = mp_irqs[i].mpc_srcbus;
24141 + if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
24142 + mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
24143 + mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
24144 + (mp_irqs[i].mpc_irqtype == type) &&
24145 + (mp_irqs[i].mpc_srcbusirq == irq))
24147 + return mp_irqs[i].mpc_dstirq;
24152 +static int __init find_isa_irq_apic(int irq, int type)
24156 + for (i = 0; i < mp_irq_entries; i++) {
24157 + int lbus = mp_irqs[i].mpc_srcbus;
24159 + if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
24160 + mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
24161 + mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
24162 + (mp_irqs[i].mpc_irqtype == type) &&
24163 + (mp_irqs[i].mpc_srcbusirq == irq))
24166 + if (i < mp_irq_entries) {
24168 + for(apic = 0; apic < nr_ioapics; apic++) {
24169 + if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
24179 + * Find a specific PCI IRQ entry.
24180 + * Not an __init, possibly needed by modules
24182 +static int pin_2_irq(int idx, int apic, int pin);
24184 +int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
24186 + int apic, i, best_guess = -1;
24188 + apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
24190 + if (mp_bus_id_to_pci_bus[bus] == -1) {
24191 + apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
24194 + for (i = 0; i < mp_irq_entries; i++) {
24195 + int lbus = mp_irqs[i].mpc_srcbus;
24197 + for (apic = 0; apic < nr_ioapics; apic++)
24198 + if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
24199 + mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
24202 + if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
24203 + !mp_irqs[i].mpc_irqtype &&
24205 + (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
24206 + int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
24208 + if (!(apic || IO_APIC_IRQ(irq)))
24211 + if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
24214 + * Use the first all-but-pin matching entry as a
24215 + * best-guess fuzzy result for broken mptables.
24217 + if (best_guess < 0)
24218 + best_guess = irq;
24221 + BUG_ON(best_guess >= NR_IRQS);
24222 + return best_guess;
24226 + * EISA Edge/Level control register, ELCR
24228 +static int EISA_ELCR(unsigned int irq)
24231 + unsigned int port = 0x4d0 + (irq >> 3);
24232 + return (inb(port) >> (irq & 7)) & 1;
24234 + apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
24238 +/* EISA interrupts are always polarity zero and can be edge or level
24239 + * trigger depending on the ELCR value. If an interrupt is listed as
24240 + * EISA conforming in the MP table, that means its trigger type must
24241 + * be read in from the ELCR */
24243 +#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
24244 +#define default_EISA_polarity(idx) (0)
24246 +/* ISA interrupts are always polarity zero edge triggered,
24247 + * when listed as conforming in the MP table. */
24249 +#define default_ISA_trigger(idx) (0)
24250 +#define default_ISA_polarity(idx) (0)
24252 +/* PCI interrupts are always polarity one level triggered,
24253 + * when listed as conforming in the MP table. */
24255 +#define default_PCI_trigger(idx) (1)
24256 +#define default_PCI_polarity(idx) (1)
24258 +/* MCA interrupts are always polarity zero level triggered,
24259 + * when listed as conforming in the MP table. */
24261 +#define default_MCA_trigger(idx) (1)
24262 +#define default_MCA_polarity(idx) (0)
24264 +static int __init MPBIOS_polarity(int idx)
24266 + int bus = mp_irqs[idx].mpc_srcbus;
24270 + * Determine IRQ line polarity (high active or low active):
24272 + switch (mp_irqs[idx].mpc_irqflag & 3)
24274 + case 0: /* conforms, ie. bus-type dependent polarity */
24276 + switch (mp_bus_id_to_type[bus])
24278 + case MP_BUS_ISA: /* ISA pin */
24280 + polarity = default_ISA_polarity(idx);
24283 + case MP_BUS_EISA: /* EISA pin */
24285 + polarity = default_EISA_polarity(idx);
24288 + case MP_BUS_PCI: /* PCI pin */
24290 + polarity = default_PCI_polarity(idx);
24293 + case MP_BUS_MCA: /* MCA pin */
24295 + polarity = default_MCA_polarity(idx);
24300 + printk(KERN_WARNING "broken BIOS!!\n");
24307 + case 1: /* high active */
24312 + case 2: /* reserved */
24314 + printk(KERN_WARNING "broken BIOS!!\n");
24318 + case 3: /* low active */
24323 + default: /* invalid */
24325 + printk(KERN_WARNING "broken BIOS!!\n");
24333 +static int MPBIOS_trigger(int idx)
24335 + int bus = mp_irqs[idx].mpc_srcbus;
24339 + * Determine IRQ trigger mode (edge or level sensitive):
24341 + switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
24343 + case 0: /* conforms, ie. bus-type dependent */
24345 + switch (mp_bus_id_to_type[bus])
24347 + case MP_BUS_ISA: /* ISA pin */
24349 + trigger = default_ISA_trigger(idx);
24352 + case MP_BUS_EISA: /* EISA pin */
24354 + trigger = default_EISA_trigger(idx);
24357 + case MP_BUS_PCI: /* PCI pin */
24359 + trigger = default_PCI_trigger(idx);
24362 + case MP_BUS_MCA: /* MCA pin */
24364 + trigger = default_MCA_trigger(idx);
24369 + printk(KERN_WARNING "broken BIOS!!\n");
24376 + case 1: /* edge */
24381 + case 2: /* reserved */
24383 + printk(KERN_WARNING "broken BIOS!!\n");
24387 + case 3: /* level */
24392 + default: /* invalid */
24394 + printk(KERN_WARNING "broken BIOS!!\n");
24402 +static inline int irq_polarity(int idx)
24404 + return MPBIOS_polarity(idx);
24407 +static inline int irq_trigger(int idx)
24409 + return MPBIOS_trigger(idx);
24412 +static int next_irq = 16;
24415 + * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
24416 + * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
24417 + * from ACPI, which can reach 800 in large boxen.
24419 + * Compact the sparse GSI space into a sequential IRQ series and reuse
24420 + * vectors if possible.
24422 +int gsi_irq_sharing(int gsi)
24424 + int i, tries, vector;
24426 + BUG_ON(gsi >= NR_IRQ_VECTORS);
24428 + if (platform_legacy_irq(gsi))
24431 + if (gsi_2_irq[gsi] != 0xFF)
24432 + return (int)gsi_2_irq[gsi];
24436 + vector = assign_irq_vector(gsi);
24439 + * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
24440 + * use of vector and if found, return that IRQ. However, we never want
24441 + * to share legacy IRQs, which usually have a different trigger mode
24444 + for (i = 0; i < NR_IRQS; i++)
24445 + if (IO_APIC_VECTOR(i) == vector)
24447 + if (platform_legacy_irq(i)) {
24448 + if (--tries >= 0) {
24449 + IO_APIC_VECTOR(i) = 0;
24452 + panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
24454 + if (i < NR_IRQS) {
24455 + gsi_2_irq[gsi] = i;
24456 + printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
24462 + BUG_ON(i >= NR_IRQS);
24463 + gsi_2_irq[gsi] = i;
24464 + IO_APIC_VECTOR(i) = vector;
24465 + printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
24470 +static int pin_2_irq(int idx, int apic, int pin)
24473 + int bus = mp_irqs[idx].mpc_srcbus;
24476 + * Debugging check, we are in big trouble if this message pops up!
24478 + if (mp_irqs[idx].mpc_dstirq != pin)
24479 + printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
24481 + switch (mp_bus_id_to_type[bus])
24483 + case MP_BUS_ISA: /* ISA pin */
24484 + case MP_BUS_EISA:
24487 + irq = mp_irqs[idx].mpc_srcbusirq;
24490 + case MP_BUS_PCI: /* PCI pin */
24493 + * PCI IRQs are mapped in order
24497 + irq += nr_ioapic_registers[i++];
24499 + irq = gsi_irq_sharing(irq);
24504 + printk(KERN_ERR "unknown bus type %d.\n",bus);
24509 + BUG_ON(irq >= NR_IRQS);
24512 + * PCI IRQ command line redirection. Yes, limits are hardcoded.
24514 + if ((pin >= 16) && (pin <= 23)) {
24515 + if (pirq_entries[pin-16] != -1) {
24516 + if (!pirq_entries[pin-16]) {
24517 + apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
24519 + irq = pirq_entries[pin-16];
24520 + apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
24525 + BUG_ON(irq >= NR_IRQS);
24529 +static inline int IO_APIC_irq_trigger(int irq)
24531 + int apic, idx, pin;
24533 + for (apic = 0; apic < nr_ioapics; apic++) {
24534 + for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
24535 + idx = find_irq_entry(apic,pin,mp_INT);
24536 + if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
24537 + return irq_trigger(idx);
24541 + * nonexistent IRQs are edge default
24546 +/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
24547 +u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
24549 +int assign_irq_vector(int irq)
24551 + unsigned long flags;
24553 + struct physdev_irq irq_op;
24555 + BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
24557 + if (irq < PIRQ_BASE || irq - PIRQ_BASE > NR_PIRQS)
24560 + spin_lock_irqsave(&vector_lock, flags);
24562 + if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
24563 + spin_unlock_irqrestore(&vector_lock, flags);
24564 + return IO_APIC_VECTOR(irq);
24567 + irq_op.irq = irq;
24568 + if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
24569 + spin_unlock_irqrestore(&vector_lock, flags);
24573 + vector = irq_op.vector;
24574 + vector_irq[vector] = irq;
24575 + if (irq != AUTO_ASSIGN)
24576 + IO_APIC_VECTOR(irq) = vector;
24578 + spin_unlock_irqrestore(&vector_lock, flags);
24583 +extern void (*interrupt[NR_IRQS])(void);
24584 +#ifndef CONFIG_XEN
24585 +static struct hw_interrupt_type ioapic_level_type;
24586 +static struct hw_interrupt_type ioapic_edge_type;
24588 +#define IOAPIC_AUTO -1
24589 +#define IOAPIC_EDGE 0
24590 +#define IOAPIC_LEVEL 1
24592 +static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
24596 + idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
24598 + if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
24599 + trigger == IOAPIC_LEVEL)
24600 + irq_desc[idx].chip = &ioapic_level_type;
24602 + irq_desc[idx].chip = &ioapic_edge_type;
24603 + set_intr_gate(vector, interrupt[idx]);
24606 +#define ioapic_register_intr(irq, vector, trigger) evtchn_register_pirq(irq)
24607 +#endif /* !CONFIG_XEN */
24609 +static void __init setup_IO_APIC_irqs(void)
24611 + struct IO_APIC_route_entry entry;
24612 + int apic, pin, idx, irq, first_notcon = 1, vector;
24613 + unsigned long flags;
24615 + apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
24617 + for (apic = 0; apic < nr_ioapics; apic++) {
24618 + for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
24621 + * add it to the IO-APIC irq-routing table:
24623 + memset(&entry,0,sizeof(entry));
24625 + entry.delivery_mode = INT_DELIVERY_MODE;
24626 + entry.dest_mode = INT_DEST_MODE;
24627 + entry.mask = 0; /* enable IRQ */
24628 + entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
24630 + idx = find_irq_entry(apic,pin,mp_INT);
24632 + if (first_notcon) {
24633 + apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
24634 + first_notcon = 0;
24636 + apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
24640 + entry.trigger = irq_trigger(idx);
24641 + entry.polarity = irq_polarity(idx);
24643 + if (irq_trigger(idx)) {
24644 + entry.trigger = 1;
24646 + entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
24649 + irq = pin_2_irq(idx, apic, pin);
24650 + add_pin_to_irq(irq, apic, pin);
24652 + if (/* !apic && */ !IO_APIC_IRQ(irq))
24655 + if (IO_APIC_IRQ(irq)) {
24656 + vector = assign_irq_vector(irq);
24657 + entry.vector = vector;
24659 + ioapic_register_intr(irq, vector, IOAPIC_AUTO);
24660 + if (!apic && (irq < 16))
24661 + disable_8259A_irq(irq);
24663 + spin_lock_irqsave(&ioapic_lock, flags);
24664 + io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
24665 + io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
24666 + set_native_irq_info(irq, TARGET_CPUS);
24667 + spin_unlock_irqrestore(&ioapic_lock, flags);
24671 + if (!first_notcon)
24672 + apic_printk(APIC_VERBOSE," not connected.\n");
24675 +#ifndef CONFIG_XEN
24677 + * Set up the 8259A-master output pin as broadcast to all
24680 +static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
24682 + struct IO_APIC_route_entry entry;
24683 + unsigned long flags;
24685 + memset(&entry,0,sizeof(entry));
24687 + disable_8259A_irq(0);
24690 + apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
24693 + * We use logical delivery to get the timer IRQ
24694 + * to the first CPU.
24696 + entry.dest_mode = INT_DEST_MODE;
24697 + entry.mask = 0; /* unmask IRQ now */
24698 + entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
24699 + entry.delivery_mode = INT_DELIVERY_MODE;
24700 + entry.polarity = 0;
24701 + entry.trigger = 0;
24702 + entry.vector = vector;
24705 + * The timer IRQ doesn't have to know that behind the
24706 + * scene we have a 8259A-master in AEOI mode ...
24708 + irq_desc[0].chip = &ioapic_edge_type;
24711 + * Add it to the IO-APIC irq-routing table:
24713 + spin_lock_irqsave(&ioapic_lock, flags);
24714 + io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
24715 + io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
24716 + spin_unlock_irqrestore(&ioapic_lock, flags);
24718 + enable_8259A_irq(0);
24721 +void __init UNEXPECTED_IO_APIC(void)
24725 +void __apicdebuginit print_IO_APIC(void)
24728 + union IO_APIC_reg_00 reg_00;
24729 + union IO_APIC_reg_01 reg_01;
24730 + union IO_APIC_reg_02 reg_02;
24731 + unsigned long flags;
24733 + if (apic_verbosity == APIC_QUIET)
24736 + printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
24737 + for (i = 0; i < nr_ioapics; i++)
24738 + printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
24739 + mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
24742 + * We are a bit conservative about what we expect. We have to
24743 + * know about every hardware change ASAP.
24745 + printk(KERN_INFO "testing the IO APIC.......................\n");
24747 + for (apic = 0; apic < nr_ioapics; apic++) {
24749 + spin_lock_irqsave(&ioapic_lock, flags);
24750 + reg_00.raw = io_apic_read(apic, 0);
24751 + reg_01.raw = io_apic_read(apic, 1);
24752 + if (reg_01.bits.version >= 0x10)
24753 + reg_02.raw = io_apic_read(apic, 2);
24754 + spin_unlock_irqrestore(&ioapic_lock, flags);
24757 + printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
24758 + printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
24759 + printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
24760 + if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
24761 + UNEXPECTED_IO_APIC();
24763 + printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
24764 + printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
24765 + if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
24766 + (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
24767 + (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
24768 + (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
24769 + (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
24770 + (reg_01.bits.entries != 0x2E) &&
24771 + (reg_01.bits.entries != 0x3F) &&
24772 + (reg_01.bits.entries != 0x03)
24774 + UNEXPECTED_IO_APIC();
24776 + printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
24777 + printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
24778 + if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
24779 + (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
24780 + (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
24781 + (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
24782 + (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
24783 + (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
24785 + UNEXPECTED_IO_APIC();
24786 + if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
24787 + UNEXPECTED_IO_APIC();
24789 + if (reg_01.bits.version >= 0x10) {
24790 + printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
24791 + printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
24792 + if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
24793 + UNEXPECTED_IO_APIC();
24796 + printk(KERN_DEBUG ".... IRQ redirection table:\n");
24798 + printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
24799 + " Stat Dest Deli Vect: \n");
24801 + for (i = 0; i <= reg_01.bits.entries; i++) {
24802 + struct IO_APIC_route_entry entry;
24804 + spin_lock_irqsave(&ioapic_lock, flags);
24805 + *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
24806 + *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
24807 + spin_unlock_irqrestore(&ioapic_lock, flags);
24809 + printk(KERN_DEBUG " %02x %03X %02X ",
24811 + entry.dest.logical.logical_dest,
24812 + entry.dest.physical.physical_dest
24815 + printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
24820 + entry.delivery_status,
24822 + entry.delivery_mode,
24827 + if (use_pci_vector())
24828 + printk(KERN_INFO "Using vector-based indexing\n");
24829 + printk(KERN_DEBUG "IRQ to pin mappings:\n");
24830 + for (i = 0; i < NR_IRQS; i++) {
24831 + struct irq_pin_list *entry = irq_2_pin + i;
24832 + if (entry->pin < 0)
24834 + if (use_pci_vector() && !platform_legacy_irq(i))
24835 + printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
24837 + printk(KERN_DEBUG "IRQ%d ", i);
24839 + printk("-> %d:%d", entry->apic, entry->pin);
24840 + if (!entry->next)
24842 + entry = irq_2_pin + entry->next;
24847 + printk(KERN_INFO ".................................... done.\n");
24852 +static __apicdebuginit void print_APIC_bitfield (int base)
24857 + if (apic_verbosity == APIC_QUIET)
24860 + printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
24861 + for (i = 0; i < 8; i++) {
24862 + v = apic_read(base + i*0x10);
24863 + for (j = 0; j < 32; j++) {
24873 +void __apicdebuginit print_local_APIC(void * dummy)
24875 + unsigned int v, ver, maxlvt;
24877 + if (apic_verbosity == APIC_QUIET)
24880 + printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
24881 + smp_processor_id(), hard_smp_processor_id());
24882 + v = apic_read(APIC_ID);
24883 + printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
24884 + v = apic_read(APIC_LVR);
24885 + printk(KERN_INFO "... APIC VERSION: %08x\n", v);
24886 + ver = GET_APIC_VERSION(v);
24887 + maxlvt = get_maxlvt();
24889 + v = apic_read(APIC_TASKPRI);
24890 + printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
24892 + v = apic_read(APIC_ARBPRI);
24893 + printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
24894 + v & APIC_ARBPRI_MASK);
24895 + v = apic_read(APIC_PROCPRI);
24896 + printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
24898 + v = apic_read(APIC_EOI);
24899 + printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
24900 + v = apic_read(APIC_RRR);
24901 + printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
24902 + v = apic_read(APIC_LDR);
24903 + printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
24904 + v = apic_read(APIC_DFR);
24905 + printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
24906 + v = apic_read(APIC_SPIV);
24907 + printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
24909 + printk(KERN_DEBUG "... APIC ISR field:\n");
24910 + print_APIC_bitfield(APIC_ISR);
24911 + printk(KERN_DEBUG "... APIC TMR field:\n");
24912 + print_APIC_bitfield(APIC_TMR);
24913 + printk(KERN_DEBUG "... APIC IRR field:\n");
24914 + print_APIC_bitfield(APIC_IRR);
24916 + v = apic_read(APIC_ESR);
24917 + printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
24919 + v = apic_read(APIC_ICR);
24920 + printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
24921 + v = apic_read(APIC_ICR2);
24922 + printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
24924 + v = apic_read(APIC_LVTT);
24925 + printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
24927 + if (maxlvt > 3) { /* PC is LVT#4. */
24928 + v = apic_read(APIC_LVTPC);
24929 + printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
24931 + v = apic_read(APIC_LVT0);
24932 + printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
24933 + v = apic_read(APIC_LVT1);
24934 + printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
24936 + if (maxlvt > 2) { /* ERR is LVT#3. */
24937 + v = apic_read(APIC_LVTERR);
24938 + printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
24941 + v = apic_read(APIC_TMICT);
24942 + printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
24943 + v = apic_read(APIC_TMCCT);
24944 + printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
24945 + v = apic_read(APIC_TDCR);
24946 + printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
24950 +void print_all_local_APICs (void)
24952 + on_each_cpu(print_local_APIC, NULL, 1, 1);
24955 +void __apicdebuginit print_PIC(void)
24958 + unsigned long flags;
24960 + if (apic_verbosity == APIC_QUIET)
24963 + printk(KERN_DEBUG "\nprinting PIC contents\n");
24965 + spin_lock_irqsave(&i8259A_lock, flags);
24967 + v = inb(0xa1) << 8 | inb(0x21);
24968 + printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
24970 + v = inb(0xa0) << 8 | inb(0x20);
24971 + printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
24975 + v = inb(0xa0) << 8 | inb(0x20);
24979 + spin_unlock_irqrestore(&i8259A_lock, flags);
24981 + printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
24983 + v = inb(0x4d1) << 8 | inb(0x4d0);
24984 + printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
24986 +#endif /* !CONFIG_XEN */
24988 +static void __init enable_IO_APIC(void)
24990 + union IO_APIC_reg_01 reg_01;
24991 +#ifndef CONFIG_XEN
24992 + int i8259_apic, i8259_pin;
24995 + unsigned long flags;
24997 + for (i = 0; i < PIN_MAP_SIZE; i++) {
24998 + irq_2_pin[i].pin = -1;
24999 + irq_2_pin[i].next = 0;
25001 + if (!pirqs_enabled)
25002 + for (i = 0; i < MAX_PIRQS; i++)
25003 + pirq_entries[i] = -1;
25006 + * The number of IO-APIC IRQ registers (== #pins):
25008 + for (apic = 0; apic < nr_ioapics; apic++) {
25009 + spin_lock_irqsave(&ioapic_lock, flags);
25010 + reg_01.raw = io_apic_read(apic, 1);
25011 + spin_unlock_irqrestore(&ioapic_lock, flags);
25012 + nr_ioapic_registers[apic] = reg_01.bits.entries+1;
25014 +#ifndef CONFIG_XEN
25015 + for(apic = 0; apic < nr_ioapics; apic++) {
25017 + /* See if any of the pins is in ExtINT mode */
25018 + for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
25019 + struct IO_APIC_route_entry entry;
25020 + spin_lock_irqsave(&ioapic_lock, flags);
25021 + *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
25022 + *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
25023 + spin_unlock_irqrestore(&ioapic_lock, flags);
25026 + /* If the interrupt line is enabled and in ExtInt mode
25027 + * I have found the pin where the i8259 is connected.
25029 + if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
25030 + ioapic_i8259.apic = apic;
25031 + ioapic_i8259.pin = pin;
25032 + goto found_i8259;
25037 + /* Look to see what if the MP table has reported the ExtINT */
25038 + i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
25039 + i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
25040 + /* Trust the MP table if nothing is setup in the hardware */
25041 + if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
25042 + printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
25043 + ioapic_i8259.pin = i8259_pin;
25044 + ioapic_i8259.apic = i8259_apic;
25046 + /* Complain if the MP table and the hardware disagree */
25047 + if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
25048 + (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
25050 + printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
25055 + * Do not trust the IO-APIC being empty at bootup
25061 + * Not an __init, needed by the reboot code
25063 +void disable_IO_APIC(void)
25066 + * Clear the IO-APIC before rebooting:
25070 +#ifndef CONFIG_XEN
25072 + * If the i8259 is routed through an IOAPIC
25073 + * Put that IOAPIC in virtual wire mode
25074 + * so legacy interrupts can be delivered.
25076 + if (ioapic_i8259.pin != -1) {
25077 + struct IO_APIC_route_entry entry;
25078 + unsigned long flags;
25080 + memset(&entry, 0, sizeof(entry));
25081 + entry.mask = 0; /* Enabled */
25082 + entry.trigger = 0; /* Edge */
25084 + entry.polarity = 0; /* High */
25085 + entry.delivery_status = 0;
25086 + entry.dest_mode = 0; /* Physical */
25087 + entry.delivery_mode = dest_ExtINT; /* ExtInt */
25088 + entry.vector = 0;
25089 + entry.dest.physical.physical_dest =
25090 + GET_APIC_ID(apic_read(APIC_ID));
25093 + * Add it to the IO-APIC irq-routing table:
25095 + spin_lock_irqsave(&ioapic_lock, flags);
25096 + io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
25097 + *(((int *)&entry)+1));
25098 + io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
25099 + *(((int *)&entry)+0));
25100 + spin_unlock_irqrestore(&ioapic_lock, flags);
25103 + disconnect_bsp_APIC(ioapic_i8259.pin != -1);
25108 + * function to set the IO-APIC physical IDs based on the
25109 + * values stored in the MPC table.
25111 + * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
25114 +#ifndef CONFIG_XEN
25115 +static void __init setup_ioapic_ids_from_mpc (void)
25117 + union IO_APIC_reg_00 reg_00;
25120 + unsigned char old_id;
25121 + unsigned long flags;
25124 + * Set the IOAPIC ID to the value stored in the MPC table.
25126 + for (apic = 0; apic < nr_ioapics; apic++) {
25128 + /* Read the register 0 value */
25129 + spin_lock_irqsave(&ioapic_lock, flags);
25130 + reg_00.raw = io_apic_read(apic, 0);
25131 + spin_unlock_irqrestore(&ioapic_lock, flags);
25133 + old_id = mp_ioapics[apic].mpc_apicid;
25136 + printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
25140 + * We need to adjust the IRQ routing table
25141 + * if the ID changed.
25143 + if (old_id != mp_ioapics[apic].mpc_apicid)
25144 + for (i = 0; i < mp_irq_entries; i++)
25145 + if (mp_irqs[i].mpc_dstapic == old_id)
25146 + mp_irqs[i].mpc_dstapic
25147 + = mp_ioapics[apic].mpc_apicid;
25150 + * Read the right value from the MPC table and
25151 + * write it into the ID register.
25153 + apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
25154 + mp_ioapics[apic].mpc_apicid);
25156 + reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
25157 + spin_lock_irqsave(&ioapic_lock, flags);
25158 + io_apic_write(apic, 0, reg_00.raw);
25159 + spin_unlock_irqrestore(&ioapic_lock, flags);
25164 + spin_lock_irqsave(&ioapic_lock, flags);
25165 + reg_00.raw = io_apic_read(apic, 0);
25166 + spin_unlock_irqrestore(&ioapic_lock, flags);
25167 + if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
25168 + printk("could not set ID!\n");
25170 + apic_printk(APIC_VERBOSE," ok.\n");
25174 +static void __init setup_ioapic_ids_from_mpc(void) { }
25178 + * There is a nasty bug in some older SMP boards, their mptable lies
25179 + * about the timer IRQ. We do the following to work around the situation:
25181 + * - timer IRQ defaults to IO-APIC IRQ
25182 + * - if this function detects that timer IRQs are defunct, then we fall
25183 + * back to ISA timer IRQs
25185 +#ifndef CONFIG_XEN
25186 +static int __init timer_irq_works(void)
25188 + unsigned long t1 = jiffies;
25190 + local_irq_enable();
25191 + /* Let ten ticks pass... */
25192 + mdelay((10 * 1000) / HZ);
25195 + * Expect a few ticks at least, to be sure some possible
25196 + * glue logic does not lock up after one or two first
25197 + * ticks in a non-ExtINT mode. Also the local APIC
25198 + * might have cached one ExtINT interrupt. Finally, at
25199 + * least one tick may be lost due to delays.
25202 + /* jiffies wrap? */
25203 + if (jiffies - t1 > 4)
25209 + * In the SMP+IOAPIC case it might happen that there are an unspecified
25210 + * number of pending IRQ events unhandled. These cases are very rare,
25211 + * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
25212 + * better to do it this way as thus we do not have to be aware of
25213 + * 'pending' interrupts in the IRQ path, except at this point.
25216 + * Edge triggered needs to resend any interrupt
25217 + * that was delayed but this is now handled in the device
25218 + * independent code.
25222 + * Starting up a edge-triggered IO-APIC interrupt is
25223 + * nasty - we need to make sure that we get the edge.
25224 + * If it is already asserted for some reason, we need
25225 + * return 1 to indicate that is was pending.
25227 + * This is not complete - we should be able to fake
25228 + * an edge even if it isn't on the 8259A...
25231 +static unsigned int startup_edge_ioapic_irq(unsigned int irq)
25233 + int was_pending = 0;
25234 + unsigned long flags;
25236 + spin_lock_irqsave(&ioapic_lock, flags);
25238 + disable_8259A_irq(irq);
25239 + if (i8259A_irq_pending(irq))
25242 + __unmask_IO_APIC_irq(irq);
25243 + spin_unlock_irqrestore(&ioapic_lock, flags);
25245 + return was_pending;
25249 + * Once we have recorded IRQ_PENDING already, we can mask the
25250 + * interrupt for real. This prevents IRQ storms from unhandled
25253 +static void ack_edge_ioapic_irq(unsigned int irq)
25256 + if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
25257 + == (IRQ_PENDING | IRQ_DISABLED))
25258 + mask_IO_APIC_irq(irq);
25263 + * Level triggered interrupts can just be masked,
25264 + * and shutting down and starting up the interrupt
25265 + * is the same as enabling and disabling them -- except
25266 + * with a startup need to return a "was pending" value.
25268 + * Level triggered interrupts are special because we
25269 + * do not touch any IO-APIC register while handling
25270 + * them. We ack the APIC in the end-IRQ handler, not
25271 + * in the start-IRQ-handler. Protection against reentrance
25272 + * from the same interrupt is still provided, both by the
25273 + * generic IRQ layer and by the fact that an unacked local
25274 + * APIC does not accept IRQs.
25276 +static unsigned int startup_level_ioapic_irq (unsigned int irq)
25278 + unmask_IO_APIC_irq(irq);
25280 + return 0; /* don't check for pending */
25283 +static void end_level_ioapic_irq (unsigned int irq)
25289 +#ifdef CONFIG_PCI_MSI
25290 +static unsigned int startup_edge_ioapic_vector(unsigned int vector)
25292 + int irq = vector_to_irq(vector);
25294 + return startup_edge_ioapic_irq(irq);
25297 +static void ack_edge_ioapic_vector(unsigned int vector)
25299 + int irq = vector_to_irq(vector);
25301 + move_native_irq(vector);
25302 + ack_edge_ioapic_irq(irq);
25305 +static unsigned int startup_level_ioapic_vector (unsigned int vector)
25307 + int irq = vector_to_irq(vector);
25309 + return startup_level_ioapic_irq (irq);
25312 +static void end_level_ioapic_vector (unsigned int vector)
25314 + int irq = vector_to_irq(vector);
25316 + move_native_irq(vector);
25317 + end_level_ioapic_irq(irq);
25320 +static void mask_IO_APIC_vector (unsigned int vector)
25322 + int irq = vector_to_irq(vector);
25324 + mask_IO_APIC_irq(irq);
25327 +static void unmask_IO_APIC_vector (unsigned int vector)
25329 + int irq = vector_to_irq(vector);
25331 + unmask_IO_APIC_irq(irq);
25335 +static void set_ioapic_affinity_vector (unsigned int vector,
25336 + cpumask_t cpu_mask)
25338 + int irq = vector_to_irq(vector);
25340 + set_native_irq_info(vector, cpu_mask);
25341 + set_ioapic_affinity_irq(irq, cpu_mask);
25343 +#endif // CONFIG_SMP
25344 +#endif // CONFIG_PCI_MSI
25346 +static int ioapic_retrigger(unsigned int irq)
25348 + send_IPI_self(IO_APIC_VECTOR(irq));
25354 + * Level and edge triggered IO-APIC interrupts need different handling,
25355 + * so we use two separate IRQ descriptors. Edge triggered IRQs can be
25356 + * handled with the level-triggered descriptor, but that one has slightly
25357 + * more overhead. Level-triggered interrupts cannot be handled with the
25358 + * edge-triggered handler, without risking IRQ storms and other ugly
25362 +static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
25363 + .typename = "IO-APIC-edge",
25364 + .startup = startup_edge_ioapic,
25365 + .shutdown = shutdown_edge_ioapic,
25366 + .enable = enable_edge_ioapic,
25367 + .disable = disable_edge_ioapic,
25368 + .ack = ack_edge_ioapic,
25369 + .end = end_edge_ioapic,
25371 + .set_affinity = set_ioapic_affinity,
25373 + .retrigger = ioapic_retrigger,
25376 +static struct hw_interrupt_type ioapic_level_type __read_mostly = {
25377 + .typename = "IO-APIC-level",
25378 + .startup = startup_level_ioapic,
25379 + .shutdown = shutdown_level_ioapic,
25380 + .enable = enable_level_ioapic,
25381 + .disable = disable_level_ioapic,
25382 + .ack = mask_and_ack_level_ioapic,
25383 + .end = end_level_ioapic,
25385 + .set_affinity = set_ioapic_affinity,
25387 + .retrigger = ioapic_retrigger,
25389 +#endif /* !CONFIG_XEN */
25391 +static inline void init_IO_APIC_traps(void)
25396 + * NOTE! The local APIC isn't very good at handling
25397 + * multiple interrupts at the same interrupt level.
25398 + * As the interrupt level is determined by taking the
25399 + * vector number and shifting that right by 4, we
25400 + * want to spread these out a bit so that they don't
25401 + * all fall in the same interrupt level.
25403 + * Also, we've got to be careful not to trash gate
25404 + * 0x80, because int 0x80 is hm, kind of importantish. ;)
25406 + for (irq = 0; irq < NR_IRQS ; irq++) {
25408 + if (use_pci_vector()) {
25409 + if (!platform_legacy_irq(tmp))
25410 + if ((tmp = vector_to_irq(tmp)) == -1)
25413 + if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
25415 + * Hmm.. We don't have an entry for this,
25416 + * so default to an old-fashioned 8259
25417 + * interrupt if we can..
25420 + make_8259A_irq(irq);
25421 +#ifndef CONFIG_XEN
25423 + /* Strange. Oh, well.. */
25424 + irq_desc[irq].chip = &no_irq_type;
25430 +#ifndef CONFIG_XEN
25431 +static void enable_lapic_irq (unsigned int irq)
25435 + v = apic_read(APIC_LVT0);
25436 + apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
25439 +static void disable_lapic_irq (unsigned int irq)
25443 + v = apic_read(APIC_LVT0);
25444 + apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
25447 +static void ack_lapic_irq (unsigned int irq)
25452 +static void end_lapic_irq (unsigned int i) { /* nothing */ }
25454 +static struct hw_interrupt_type lapic_irq_type __read_mostly = {
25455 + .typename = "local-APIC-edge",
25456 + .startup = NULL, /* startup_irq() not used for IRQ0 */
25457 + .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
25458 + .enable = enable_lapic_irq,
25459 + .disable = disable_lapic_irq,
25460 + .ack = ack_lapic_irq,
25461 + .end = end_lapic_irq,
25464 +static void setup_nmi (void)
25467 + * Dirty trick to enable the NMI watchdog ...
25468 + * We put the 8259A master into AEOI mode and
25469 + * unmask on all local APICs LVT0 as NMI.
25471 + * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
25472 + * is from Maciej W. Rozycki - so we do not have to EOI from
25473 + * the NMI handler or the timer interrupt.
25475 + printk(KERN_INFO "activating NMI Watchdog ...");
25477 + enable_NMI_through_LVT0(NULL);
25479 + printk(" done.\n");
25483 + * This looks a bit hackish but it's about the only one way of sending
25484 + * a few INTA cycles to 8259As and any associated glue logic. ICR does
25485 + * not support the ExtINT mode, unfortunately. We need to send these
25486 + * cycles as some i82489DX-based boards have glue logic that keeps the
25487 + * 8259A interrupt line asserted until INTA. --macro
25489 +static inline void unlock_ExtINT_logic(void)
25491 + int apic, pin, i;
25492 + struct IO_APIC_route_entry entry0, entry1;
25493 + unsigned char save_control, save_freq_select;
25494 + unsigned long flags;
25496 + pin = find_isa_irq_pin(8, mp_INT);
25497 + apic = find_isa_irq_apic(8, mp_INT);
25501 + spin_lock_irqsave(&ioapic_lock, flags);
25502 + *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
25503 + *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
25504 + spin_unlock_irqrestore(&ioapic_lock, flags);
25505 + clear_IO_APIC_pin(apic, pin);
25507 + memset(&entry1, 0, sizeof(entry1));
25509 + entry1.dest_mode = 0; /* physical delivery */
25510 + entry1.mask = 0; /* unmask IRQ now */
25511 + entry1.dest.physical.physical_dest = hard_smp_processor_id();
25512 + entry1.delivery_mode = dest_ExtINT;
25513 + entry1.polarity = entry0.polarity;
25514 + entry1.trigger = 0;
25515 + entry1.vector = 0;
25517 + spin_lock_irqsave(&ioapic_lock, flags);
25518 + io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
25519 + io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
25520 + spin_unlock_irqrestore(&ioapic_lock, flags);
25522 + save_control = CMOS_READ(RTC_CONTROL);
25523 + save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
25524 + CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
25525 + RTC_FREQ_SELECT);
25526 + CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
25529 + while (i-- > 0) {
25531 + if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
25535 + CMOS_WRITE(save_control, RTC_CONTROL);
25536 + CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
25537 + clear_IO_APIC_pin(apic, pin);
25539 + spin_lock_irqsave(&ioapic_lock, flags);
25540 + io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
25541 + io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
25542 + spin_unlock_irqrestore(&ioapic_lock, flags);
25545 +int timer_uses_ioapic_pin_0;
25548 + * This code may look a bit paranoid, but it's supposed to cooperate with
25549 + * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
25550 + * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
25551 + * fanatically on his truly buggy board.
25553 + * FIXME: really need to revamp this for modern platforms only.
25555 +static inline void check_timer(void)
25557 + int apic1, pin1, apic2, pin2;
25561 + * get/set the timer IRQ vector:
25563 + disable_8259A_irq(0);
25564 + vector = assign_irq_vector(0);
25565 + set_intr_gate(vector, interrupt[0]);
25568 + * Subtle, code in do_timer_interrupt() expects an AEOI
25569 + * mode for the 8259A whenever interrupts are routed
25570 + * through I/O APICs. Also IRQ0 has to be enabled in
25571 + * the 8259A which implies the virtual wire has to be
25572 + * disabled in the local APIC.
25574 + apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
25576 + if (timer_over_8254 > 0)
25577 + enable_8259A_irq(0);
25579 + pin1 = find_isa_irq_pin(0, mp_INT);
25580 + apic1 = find_isa_irq_apic(0, mp_INT);
25581 + pin2 = ioapic_i8259.pin;
25582 + apic2 = ioapic_i8259.apic;
25585 + timer_uses_ioapic_pin_0 = 1;
25587 + apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
25588 + vector, apic1, pin1, apic2, pin2);
25590 + if (pin1 != -1) {
25592 + * Ok, does IRQ0 through the IOAPIC work?
25594 + unmask_IO_APIC_irq(0);
25595 + if (!no_timer_check && timer_irq_works()) {
25596 + nmi_watchdog_default();
25597 + if (nmi_watchdog == NMI_IO_APIC) {
25598 + disable_8259A_irq(0);
25600 + enable_8259A_irq(0);
25602 + if (disable_timer_pin_1 > 0)
25603 + clear_IO_APIC_pin(0, pin1);
25606 + clear_IO_APIC_pin(apic1, pin1);
25607 + apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
25608 + "connected to IO-APIC\n");
25611 + apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
25612 + "through the 8259A ... ");
25613 + if (pin2 != -1) {
25614 + apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
25617 + * legacy devices should be connected to IO APIC #0
25619 + setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
25620 + if (timer_irq_works()) {
25621 + apic_printk(APIC_VERBOSE," works.\n");
25622 + nmi_watchdog_default();
25623 + if (nmi_watchdog == NMI_IO_APIC) {
25629 + * Cleanup, just in case ...
25631 + clear_IO_APIC_pin(apic2, pin2);
25633 + apic_printk(APIC_VERBOSE," failed.\n");
25635 + if (nmi_watchdog == NMI_IO_APIC) {
25636 + printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
25637 + nmi_watchdog = 0;
25640 + apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
25642 + disable_8259A_irq(0);
25643 + irq_desc[0].chip = &lapic_irq_type;
25644 + apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
25645 + enable_8259A_irq(0);
25647 + if (timer_irq_works()) {
25648 + apic_printk(APIC_VERBOSE," works.\n");
25651 + apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
25652 + apic_printk(APIC_VERBOSE," failed.\n");
25654 + apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
25657 + make_8259A_irq(0);
25658 + apic_write(APIC_LVT0, APIC_DM_EXTINT);
25660 + unlock_ExtINT_logic();
25662 + if (timer_irq_works()) {
25663 + apic_printk(APIC_VERBOSE," works.\n");
25666 + apic_printk(APIC_VERBOSE," failed :(.\n");
25667 + panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
25670 +#define check_timer() ((void)0)
25671 +int timer_uses_ioapic_pin_0 = 0;
25672 +#endif /* !CONFIG_XEN */
25674 +static int __init notimercheck(char *s)
25676 + no_timer_check = 1;
25679 +__setup("no_timer_check", notimercheck);
25683 + * IRQ's that are handled by the PIC in the MPS IOAPIC case.
25684 + * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
25685 + * Linux doesn't really care, as it's not actually used
25686 + * for any interrupt handling anyway.
25688 +#define PIC_IRQS (1<<2)
25690 +void __init setup_IO_APIC(void)
25692 + enable_IO_APIC();
25695 + io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
25697 + io_apic_irqs = ~PIC_IRQS;
25699 + apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
25702 + * Set up the IO-APIC IRQ routing table.
25704 + if (!acpi_ioapic)
25705 + setup_ioapic_ids_from_mpc();
25706 +#ifndef CONFIG_XEN
25708 +#endif /* !CONFIG_XEN */
25709 + setup_IO_APIC_irqs();
25710 + init_IO_APIC_traps();
25712 + if (!acpi_ioapic)
25716 +struct sysfs_ioapic_data {
25717 + struct sys_device dev;
25718 + struct IO_APIC_route_entry entry[0];
25720 +static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
25722 +static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
25724 + struct IO_APIC_route_entry *entry;
25725 + struct sysfs_ioapic_data *data;
25726 + unsigned long flags;
25729 + data = container_of(dev, struct sysfs_ioapic_data, dev);
25730 + entry = data->entry;
25731 + spin_lock_irqsave(&ioapic_lock, flags);
25732 + for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
25733 + *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
25734 + *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
25736 + spin_unlock_irqrestore(&ioapic_lock, flags);
25741 +static int ioapic_resume(struct sys_device *dev)
25743 + struct IO_APIC_route_entry *entry;
25744 + struct sysfs_ioapic_data *data;
25745 + unsigned long flags;
25746 + union IO_APIC_reg_00 reg_00;
25749 + data = container_of(dev, struct sysfs_ioapic_data, dev);
25750 + entry = data->entry;
25752 + spin_lock_irqsave(&ioapic_lock, flags);
25753 + reg_00.raw = io_apic_read(dev->id, 0);
25754 + if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
25755 + reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
25756 + io_apic_write(dev->id, 0, reg_00.raw);
25758 + for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
25759 + io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
25760 + io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
25762 + spin_unlock_irqrestore(&ioapic_lock, flags);
25767 +static struct sysdev_class ioapic_sysdev_class = {
25768 + set_kset_name("ioapic"),
25769 +#ifndef CONFIG_XEN
25770 + .suspend = ioapic_suspend,
25771 + .resume = ioapic_resume,
25775 +static int __init ioapic_init_sysfs(void)
25777 + struct sys_device * dev;
25778 + int i, size, error = 0;
25780 + error = sysdev_class_register(&ioapic_sysdev_class);
25784 + for (i = 0; i < nr_ioapics; i++ ) {
25785 + size = sizeof(struct sys_device) + nr_ioapic_registers[i]
25786 + * sizeof(struct IO_APIC_route_entry);
25787 + mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
25788 + if (!mp_ioapic_data[i]) {
25789 + printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
25792 + memset(mp_ioapic_data[i], 0, size);
25793 + dev = &mp_ioapic_data[i]->dev;
25795 + dev->cls = &ioapic_sysdev_class;
25796 + error = sysdev_register(dev);
25798 + kfree(mp_ioapic_data[i]);
25799 + mp_ioapic_data[i] = NULL;
25800 + printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
25808 +device_initcall(ioapic_init_sysfs);
25810 +/* --------------------------------------------------------------------------
25811 + ACPI-based IOAPIC Configuration
25812 + -------------------------------------------------------------------------- */
25814 +#ifdef CONFIG_ACPI
25816 +#define IO_APIC_MAX_ID 0xFE
25818 +int __init io_apic_get_version (int ioapic)
25820 + union IO_APIC_reg_01 reg_01;
25821 + unsigned long flags;
25823 + spin_lock_irqsave(&ioapic_lock, flags);
25824 + reg_01.raw = io_apic_read(ioapic, 1);
25825 + spin_unlock_irqrestore(&ioapic_lock, flags);
25827 + return reg_01.bits.version;
25831 +int __init io_apic_get_redir_entries (int ioapic)
25833 + union IO_APIC_reg_01 reg_01;
25834 + unsigned long flags;
25836 + spin_lock_irqsave(&ioapic_lock, flags);
25837 + reg_01.raw = io_apic_read(ioapic, 1);
25838 + spin_unlock_irqrestore(&ioapic_lock, flags);
25840 + return reg_01.bits.entries;
25844 +int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
25846 + struct IO_APIC_route_entry entry;
25847 + unsigned long flags;
25849 + if (!IO_APIC_IRQ(irq)) {
25850 + apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
25856 + * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
25857 + * Note that we mask (disable) IRQs now -- these get enabled when the
25858 + * corresponding device driver registers for this IRQ.
25861 + memset(&entry,0,sizeof(entry));
25863 + entry.delivery_mode = INT_DELIVERY_MODE;
25864 + entry.dest_mode = INT_DEST_MODE;
25865 + entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
25866 + entry.trigger = edge_level;
25867 + entry.polarity = active_high_low;
25868 + entry.mask = 1; /* Disabled (masked) */
25870 + irq = gsi_irq_sharing(irq);
25872 + * IRQs < 16 are already in the irq_2_pin[] map
25875 + add_pin_to_irq(irq, ioapic, pin);
25877 + entry.vector = assign_irq_vector(irq);
25879 + apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
25880 + "IRQ %d Mode:%i Active:%i)\n", ioapic,
25881 + mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
25882 + edge_level, active_high_low);
25884 + ioapic_register_intr(irq, entry.vector, edge_level);
25886 + if (!ioapic && (irq < 16))
25887 + disable_8259A_irq(irq);
25889 + spin_lock_irqsave(&ioapic_lock, flags);
25890 + io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
25891 + io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
25892 + set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
25893 + spin_unlock_irqrestore(&ioapic_lock, flags);
25898 +#endif /* CONFIG_ACPI */
25901 +#ifndef CONFIG_XEN
25903 + * This function currently is only a helper for the i386 smp boot process where
25904 + * we need to reprogram the ioredtbls to cater for the cpus which have come online
25905 + * so mask in all cases should simply be TARGET_CPUS
25908 +void __init setup_ioapic_dest(void)
25910 + int pin, ioapic, irq, irq_entry;
25912 + if (skip_ioapic_setup == 1)
25915 + for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
25916 + for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
25917 + irq_entry = find_irq_entry(ioapic, pin, mp_INT);
25918 + if (irq_entry == -1)
25920 + irq = pin_2_irq(irq_entry, ioapic, pin);
25921 + set_ioapic_affinity_irq(irq, TARGET_CPUS);
25927 +#endif /* !CONFIG_XEN */
25928 Index: head-2008-11-25/arch/x86/kernel/ioport_64-xen.c
25929 ===================================================================
25930 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
25931 +++ head-2008-11-25/arch/x86/kernel/ioport_64-xen.c 2008-01-28 12:24:19.000000000 +0100
25934 + * linux/arch/x86_64/kernel/ioport.c
25936 + * This contains the io-permission bitmap code - written by obz, with changes
25940 +#include <linux/sched.h>
25941 +#include <linux/kernel.h>
25942 +#include <linux/capability.h>
25943 +#include <linux/errno.h>
25944 +#include <linux/types.h>
25945 +#include <linux/ioport.h>
25946 +#include <linux/mm.h>
25947 +#include <linux/smp.h>
25948 +#include <linux/smp_lock.h>
25949 +#include <linux/stddef.h>
25950 +#include <linux/slab.h>
25951 +#include <linux/thread_info.h>
25952 +#include <xen/interface/physdev.h>
25954 +/* Set EXTENT bits starting at BASE in BITMAP to value TURN_ON. */
25955 +static void set_bitmap(unsigned long *bitmap, unsigned int base, unsigned int extent, int new_value)
25960 + for (i = base; i < base + extent; i++)
25961 + __set_bit(i, bitmap);
25963 + for (i = base; i < base + extent; i++)
25964 + clear_bit(i, bitmap);
25968 + * this changes the io permissions bitmap in the current task.
25970 +asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on)
25972 + struct thread_struct * t = ¤t->thread;
25973 + unsigned long *bitmap;
25974 + struct physdev_set_iobitmap set_iobitmap;
25976 + if ((from + num <= from) || (from + num > IO_BITMAP_BITS))
25978 + if (turn_on && !capable(CAP_SYS_RAWIO))
25982 + * If it's the first ioperm() call in this thread's lifetime, set the
25983 + * IO bitmap up. ioperm() is much less timing critical than clone(),
25984 + * this is why we delay this operation until now:
25986 + if (!t->io_bitmap_ptr) {
25987 + bitmap = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
25991 + memset(bitmap, 0xff, IO_BITMAP_BYTES);
25992 + t->io_bitmap_ptr = bitmap;
25994 + set_xen_guest_handle(set_iobitmap.bitmap, (char *)bitmap);
25995 + set_iobitmap.nr_ports = IO_BITMAP_BITS;
25996 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap,
26000 + set_bitmap(t->io_bitmap_ptr, from, num, !turn_on);
26006 + * sys_iopl has to be used when you want to access the IO ports
26007 + * beyond the 0x3ff range: to get the full 65536 ports bitmapped
26008 + * you'd need 8kB of bitmaps/process, which is a bit excessive.
26012 +asmlinkage long sys_iopl(unsigned int new_iopl, struct pt_regs *regs)
26014 + unsigned int old_iopl = current->thread.iopl;
26015 + struct physdev_set_iopl set_iopl;
26017 + if (new_iopl > 3)
26020 + /* Need "raw I/O" privileges for direct port access. */
26021 + if ((new_iopl > old_iopl) && !capable(CAP_SYS_RAWIO))
26024 + /* Change our version of the privilege levels. */
26025 + current->thread.iopl = new_iopl;
26027 + /* Force the change at ring 0. */
26028 + set_iopl.iopl = (new_iopl == 0) ? 1 : new_iopl;
26029 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl));
26033 Index: head-2008-11-25/arch/x86/kernel/irq_64-xen.c
26034 ===================================================================
26035 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
26036 +++ head-2008-11-25/arch/x86/kernel/irq_64-xen.c 2008-10-29 09:55:56.000000000 +0100
26039 + * linux/arch/x86_64/kernel/irq.c
26041 + * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
26043 + * This file contains the lowest level x86_64-specific interrupt
26044 + * entry and irq statistics code. All the remaining irq logic is
26045 + * done by the generic kernel/irq/ code and in the
26046 + * x86_64-specific irq controller code. (e.g. i8259.c and
26050 +#include <linux/kernel_stat.h>
26051 +#include <linux/interrupt.h>
26052 +#include <linux/seq_file.h>
26053 +#include <linux/module.h>
26054 +#include <linux/delay.h>
26055 +#include <asm/uaccess.h>
26056 +#include <asm/io_apic.h>
26057 +#include <asm/idle.h>
26059 +atomic_t irq_err_count;
26060 +#ifdef CONFIG_X86_IO_APIC
26061 +#ifdef APIC_MISMATCH_DEBUG
26062 +atomic_t irq_mis_count;
26066 +#ifdef CONFIG_DEBUG_STACKOVERFLOW
26068 + * Probabilistic stack overflow check:
26070 + * Only check the stack in process context, because everything else
26071 + * runs on the big interrupt stacks. Checking reliably is too expensive,
26072 + * so we just check from interrupts.
26074 +static inline void stack_overflow_check(struct pt_regs *regs)
26076 + u64 curbase = (u64) current->thread_info;
26077 + static unsigned long warned = -60*HZ;
26079 + if (regs->rsp >= curbase && regs->rsp <= curbase + THREAD_SIZE &&
26080 + regs->rsp < curbase + sizeof(struct thread_info) + 128 &&
26081 + time_after(jiffies, warned + 60*HZ)) {
26082 + printk("do_IRQ: %s near stack overflow (cur:%Lx,rsp:%lx)\n",
26083 + current->comm, curbase, regs->rsp);
26084 + show_stack(NULL,NULL);
26085 + warned = jiffies;
26091 + * Generic, controller-independent functions:
26094 +int show_interrupts(struct seq_file *p, void *v)
26096 + int i = *(loff_t *) v, j;
26097 + struct irqaction * action;
26098 + unsigned long flags;
26101 + seq_printf(p, " ");
26102 + for_each_online_cpu(j)
26103 + seq_printf(p, "CPU%-8d",j);
26104 + seq_putc(p, '\n');
26107 + if (i < NR_IRQS) {
26108 + spin_lock_irqsave(&irq_desc[i].lock, flags);
26109 + action = irq_desc[i].action;
26112 + seq_printf(p, "%3d: ",i);
26113 +#ifndef CONFIG_SMP
26114 + seq_printf(p, "%10u ", kstat_irqs(i));
26116 + for_each_online_cpu(j)
26117 + seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
26119 + seq_printf(p, " %14s", irq_desc[i].chip->typename);
26121 + seq_printf(p, " %s", action->name);
26122 + for (action=action->next; action; action = action->next)
26123 + seq_printf(p, ", %s", action->name);
26124 + seq_putc(p, '\n');
26126 + spin_unlock_irqrestore(&irq_desc[i].lock, flags);
26127 + } else if (i == NR_IRQS) {
26128 + seq_printf(p, "NMI: ");
26129 + for_each_online_cpu(j)
26130 + seq_printf(p, "%10u ", cpu_pda(j)->__nmi_count);
26131 + seq_putc(p, '\n');
26132 +#ifdef CONFIG_X86_LOCAL_APIC
26133 + seq_printf(p, "LOC: ");
26134 + for_each_online_cpu(j)
26135 + seq_printf(p, "%10u ", cpu_pda(j)->apic_timer_irqs);
26136 + seq_putc(p, '\n');
26138 + seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
26139 +#ifdef CONFIG_X86_IO_APIC
26140 +#ifdef APIC_MISMATCH_DEBUG
26141 + seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
26149 + * do_IRQ handles all normal device IRQ's (the special
26150 + * SMP cross-CPU interrupts have their own specific
26153 +asmlinkage unsigned int do_IRQ(struct pt_regs *regs)
26155 + /* high bit used in ret_from_ code */
26156 + unsigned irq = ~regs->orig_rax;
26158 + if (unlikely(irq >= NR_IRQS)) {
26159 + printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
26160 + __FUNCTION__, irq);
26166 +#ifdef CONFIG_DEBUG_STACKOVERFLOW
26167 + stack_overflow_check(regs);
26169 + __do_IRQ(irq, regs);
26175 +#ifdef CONFIG_HOTPLUG_CPU
26176 +void fixup_irqs(cpumask_t map)
26178 + unsigned int irq;
26179 + static int warned;
26181 + for (irq = 0; irq < NR_IRQS; irq++) {
26186 + cpus_and(mask, irq_desc[irq].affinity, map);
26187 + if (any_online_cpu(mask) == NR_CPUS) {
26188 + /*printk("Breaking affinity for irq %i\n", irq);*/
26191 + if (irq_desc[irq].chip->set_affinity)
26192 + irq_desc[irq].chip->set_affinity(irq, mask);
26193 + else if (irq_desc[irq].action && !(warned++))
26194 + printk("Cannot set affinity for irq %i\n", irq);
26197 + /* That doesn't seem sufficient. Give it 1ms. */
26198 + local_irq_enable();
26200 + local_irq_disable();
26204 +extern void call_softirq(void);
26206 +asmlinkage void do_softirq(void)
26209 + unsigned long flags;
26211 + if (in_interrupt())
26214 + local_irq_save(flags);
26215 + pending = local_softirq_pending();
26216 + /* Switch to interrupt stack */
26219 + WARN_ON_ONCE(softirq_count());
26221 + local_irq_restore(flags);
26223 +EXPORT_SYMBOL(do_softirq);
26225 +#ifndef CONFIG_X86_LOCAL_APIC
26227 + * 'what should we do if we get a hw irq event on an illegal vector'.
26228 + * each architecture has to answer this themselves.
26230 +void ack_bad_irq(unsigned int irq)
26232 + printk("unexpected IRQ trap at vector %02x\n", irq);
26235 Index: head-2008-11-25/arch/x86/kernel/ldt_64-xen.c
26236 ===================================================================
26237 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
26238 +++ head-2008-11-25/arch/x86/kernel/ldt_64-xen.c 2007-06-12 13:13:01.000000000 +0200
26241 + * linux/arch/x86_64/kernel/ldt.c
26243 + * Copyright (C) 1992 Krishna Balasubramanian and Linus Torvalds
26244 + * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
26245 + * Copyright (C) 2002 Andi Kleen
26247 + * This handles calls from both 32bit and 64bit mode.
26250 +#include <linux/errno.h>
26251 +#include <linux/sched.h>
26252 +#include <linux/string.h>
26253 +#include <linux/mm.h>
26254 +#include <linux/smp.h>
26255 +#include <linux/smp_lock.h>
26256 +#include <linux/vmalloc.h>
26257 +#include <linux/slab.h>
26259 +#include <asm/uaccess.h>
26260 +#include <asm/system.h>
26261 +#include <asm/ldt.h>
26262 +#include <asm/desc.h>
26263 +#include <asm/proto.h>
26264 +#include <asm/pgalloc.h>
26266 +#ifdef CONFIG_SMP /* avoids "defined but not used" warnig */
26267 +static void flush_ldt(void *null)
26269 + if (current->active_mm)
26270 + load_LDT(¤t->active_mm->context);
26274 +static int alloc_ldt(mm_context_t *pc, unsigned mincount, int reload)
26278 + unsigned oldsize;
26280 + if (mincount <= (unsigned)pc->size)
26282 + oldsize = pc->size;
26283 + mincount = (mincount+511)&(~511);
26284 + if (mincount*LDT_ENTRY_SIZE > PAGE_SIZE)
26285 + newldt = vmalloc(mincount*LDT_ENTRY_SIZE);
26287 + newldt = kmalloc(mincount*LDT_ENTRY_SIZE, GFP_KERNEL);
26293 + memcpy(newldt, pc->ldt, oldsize*LDT_ENTRY_SIZE);
26294 + oldldt = pc->ldt;
26295 + memset(newldt+oldsize*LDT_ENTRY_SIZE, 0, (mincount-oldsize)*LDT_ENTRY_SIZE);
26297 + pc->ldt = newldt;
26299 + pc->size = mincount;
26305 + preempt_disable();
26307 + make_pages_readonly(
26309 + (pc->size * LDT_ENTRY_SIZE) / PAGE_SIZE,
26310 + XENFEAT_writable_descriptor_tables);
26313 + mask = cpumask_of_cpu(smp_processor_id());
26314 + if (!cpus_equal(current->mm->cpu_vm_mask, mask))
26315 + smp_call_function(flush_ldt, NULL, 1, 1);
26316 + preempt_enable();
26320 + make_pages_writable(
26322 + (oldsize * LDT_ENTRY_SIZE) / PAGE_SIZE,
26323 + XENFEAT_writable_descriptor_tables);
26324 + if (oldsize*LDT_ENTRY_SIZE > PAGE_SIZE)
26332 +static inline int copy_ldt(mm_context_t *new, mm_context_t *old)
26334 + int err = alloc_ldt(new, old->size, 0);
26337 + memcpy(new->ldt, old->ldt, old->size*LDT_ENTRY_SIZE);
26338 + make_pages_readonly(
26340 + (new->size * LDT_ENTRY_SIZE) / PAGE_SIZE,
26341 + XENFEAT_writable_descriptor_tables);
26346 + * we do not have to muck with descriptors here, that is
26347 + * done in switch_mm() as needed.
26349 +int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
26351 + struct mm_struct * old_mm;
26354 + memset(&mm->context, 0, sizeof(mm->context));
26355 + init_MUTEX(&mm->context.sem);
26356 + old_mm = current->mm;
26357 + if (old_mm && old_mm->context.size > 0) {
26358 + down(&old_mm->context.sem);
26359 + retval = copy_ldt(&mm->context, &old_mm->context);
26360 + up(&old_mm->context.sem);
26362 + if (retval == 0) {
26363 + spin_lock(&mm_unpinned_lock);
26364 + list_add(&mm->context.unpinned, &mm_unpinned);
26365 + spin_unlock(&mm_unpinned_lock);
26372 + * Don't touch the LDT register - we're already in the next thread.
26374 +void destroy_context(struct mm_struct *mm)
26376 + if (mm->context.size) {
26377 + if (mm == current->active_mm)
26379 + make_pages_writable(
26381 + (mm->context.size * LDT_ENTRY_SIZE) / PAGE_SIZE,
26382 + XENFEAT_writable_descriptor_tables);
26383 + if (mm->context.size*LDT_ENTRY_SIZE > PAGE_SIZE)
26384 + vfree(mm->context.ldt);
26386 + kfree(mm->context.ldt);
26387 + mm->context.size = 0;
26389 + if (!mm->context.pinned) {
26390 + spin_lock(&mm_unpinned_lock);
26391 + list_del(&mm->context.unpinned);
26392 + spin_unlock(&mm_unpinned_lock);
26396 +static int read_ldt(void __user * ptr, unsigned long bytecount)
26399 + unsigned long size;
26400 + struct mm_struct * mm = current->mm;
26402 + if (!mm->context.size)
26404 + if (bytecount > LDT_ENTRY_SIZE*LDT_ENTRIES)
26405 + bytecount = LDT_ENTRY_SIZE*LDT_ENTRIES;
26407 + down(&mm->context.sem);
26408 + size = mm->context.size*LDT_ENTRY_SIZE;
26409 + if (size > bytecount)
26410 + size = bytecount;
26413 + if (copy_to_user(ptr, mm->context.ldt, size))
26415 + up(&mm->context.sem);
26417 + goto error_return;
26418 + if (size != bytecount) {
26419 + /* zero-fill the rest */
26420 + if (clear_user(ptr+size, bytecount-size) != 0) {
26422 + goto error_return;
26425 + return bytecount;
26430 +static int read_default_ldt(void __user * ptr, unsigned long bytecount)
26432 + /* Arbitrary number */
26433 + /* x86-64 default LDT is all zeros */
26434 + if (bytecount > 128)
26436 + if (clear_user(ptr, bytecount))
26438 + return bytecount;
26441 +static int write_ldt(void __user * ptr, unsigned long bytecount, int oldmode)
26443 + struct task_struct *me = current;
26444 + struct mm_struct * mm = me->mm;
26445 + __u32 entry_1, entry_2, *lp;
26446 + unsigned long mach_lp;
26448 + struct user_desc ldt_info;
26452 + if (bytecount != sizeof(ldt_info))
26455 + if (copy_from_user(&ldt_info, ptr, bytecount))
26459 + if (ldt_info.entry_number >= LDT_ENTRIES)
26461 + if (ldt_info.contents == 3) {
26464 + if (ldt_info.seg_not_present == 0)
26468 + down(&mm->context.sem);
26469 + if (ldt_info.entry_number >= (unsigned)mm->context.size) {
26470 + error = alloc_ldt(¤t->mm->context, ldt_info.entry_number+1, 1);
26475 + lp = (__u32 *) ((ldt_info.entry_number << 3) + (char *) mm->context.ldt);
26476 + mach_lp = arbitrary_virt_to_machine(lp);
26478 + /* Allow LDTs to be cleared by the user. */
26479 + if (ldt_info.base_addr == 0 && ldt_info.limit == 0) {
26480 + if (oldmode || LDT_empty(&ldt_info)) {
26487 + entry_1 = LDT_entry_a(&ldt_info);
26488 + entry_2 = LDT_entry_b(&ldt_info);
26490 + entry_2 &= ~(1 << 20);
26492 + /* Install the new entry ... */
26494 + error = HYPERVISOR_update_descriptor(mach_lp, (unsigned long)((entry_1 | (unsigned long) entry_2 << 32)));
26497 + up(&mm->context.sem);
26502 +asmlinkage int sys_modify_ldt(int func, void __user *ptr, unsigned long bytecount)
26504 + int ret = -ENOSYS;
26508 + ret = read_ldt(ptr, bytecount);
26511 + ret = write_ldt(ptr, bytecount, 1);
26514 + ret = read_default_ldt(ptr, bytecount);
26517 + ret = write_ldt(ptr, bytecount, 0);
26522 Index: head-2008-11-25/arch/x86/kernel/mpparse_64-xen.c
26523 ===================================================================
26524 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
26525 +++ head-2008-11-25/arch/x86/kernel/mpparse_64-xen.c 2007-06-12 13:13:01.000000000 +0200
26528 + * Intel Multiprocessor Specification 1.1 and 1.4
26529 + * compliant MP-table parsing routines.
26531 + * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
26532 + * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
26535 + * Erich Boleyn : MP v1.4 and additional changes.
26536 + * Alan Cox : Added EBDA scanning
26537 + * Ingo Molnar : various cleanups and rewrites
26538 + * Maciej W. Rozycki: Bits for default MP configurations
26539 + * Paul Diefenbaugh: Added full ACPI support
26542 +#include <linux/mm.h>
26543 +#include <linux/init.h>
26544 +#include <linux/delay.h>
26545 +#include <linux/bootmem.h>
26546 +#include <linux/smp_lock.h>
26547 +#include <linux/kernel_stat.h>
26548 +#include <linux/mc146818rtc.h>
26549 +#include <linux/acpi.h>
26550 +#include <linux/module.h>
26552 +#include <asm/smp.h>
26553 +#include <asm/mtrr.h>
26554 +#include <asm/mpspec.h>
26555 +#include <asm/pgalloc.h>
26556 +#include <asm/io_apic.h>
26557 +#include <asm/proto.h>
26558 +#include <asm/acpi.h>
26560 +/* Have we found an MP table */
26561 +int smp_found_config;
26562 +unsigned int __initdata maxcpus = NR_CPUS;
26564 +int acpi_found_madt;
26567 + * Various Linux-internal data structures created from the
26570 +unsigned char apic_version [MAX_APICS];
26571 +unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
26572 +int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
26574 +static int mp_current_pci_id = 0;
26575 +/* I/O APIC entries */
26576 +struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
26578 +/* # of MP IRQ source entries */
26579 +struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
26581 +/* MP IRQ source entries */
26582 +int mp_irq_entries;
26586 +unsigned long mp_lapic_addr = 0;
26590 +/* Processor that is doing the boot up */
26591 +unsigned int boot_cpu_id = -1U;
26592 +/* Internal processor count */
26593 +unsigned int num_processors __initdata = 0;
26595 +unsigned disabled_cpus __initdata;
26597 +/* Bitmask of physically existing CPUs */
26598 +physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
26600 +/* ACPI MADT entry parsing functions */
26601 +#ifdef CONFIG_ACPI
26602 +extern struct acpi_boot_flags acpi_boot;
26603 +#ifdef CONFIG_X86_LOCAL_APIC
26604 +extern int acpi_parse_lapic (acpi_table_entry_header *header);
26605 +extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
26606 +extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
26607 +#endif /*CONFIG_X86_LOCAL_APIC*/
26608 +#ifdef CONFIG_X86_IO_APIC
26609 +extern int acpi_parse_ioapic (acpi_table_entry_header *header);
26610 +#endif /*CONFIG_X86_IO_APIC*/
26611 +#endif /*CONFIG_ACPI*/
26613 +u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
26617 + * Intel MP BIOS table parsing routines:
26621 + * Checksum an MP configuration block.
26624 +static int __init mpf_checksum(unsigned char *mp, int len)
26631 + return sum & 0xFF;
26634 +#ifndef CONFIG_XEN
26635 +static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
26638 + unsigned char ver;
26639 + cpumask_t tmp_map;
26641 + if (!(m->mpc_cpuflag & CPU_ENABLED)) {
26646 + printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
26648 + (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
26649 + (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
26652 + if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
26653 + Dprintk(" Bootup CPU\n");
26654 + boot_cpu_id = m->mpc_apicid;
26656 + if (num_processors >= NR_CPUS) {
26657 + printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
26658 + " Processor ignored.\n", NR_CPUS);
26662 + num_processors++;
26663 + cpus_complement(tmp_map, cpu_present_map);
26664 + cpu = first_cpu(tmp_map);
26666 +#if MAX_APICS < 255
26667 + if ((int)m->mpc_apicid > MAX_APICS) {
26668 + printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
26669 + m->mpc_apicid, MAX_APICS);
26673 + ver = m->mpc_apicver;
26675 + physid_set(m->mpc_apicid, phys_cpu_present_map);
26677 + * Validate version
26679 + if (ver == 0x0) {
26680 + printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
26683 + apic_version[m->mpc_apicid] = ver;
26684 + if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
26686 + * bios_cpu_apicid is required to have processors listed
26687 + * in same order as logical cpu numbers. Hence the first
26688 + * entry is BSP, and so on.
26692 + bios_cpu_apicid[cpu] = m->mpc_apicid;
26693 + x86_cpu_to_apicid[cpu] = m->mpc_apicid;
26695 + cpu_set(cpu, cpu_possible_map);
26696 + cpu_set(cpu, cpu_present_map);
26699 +static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
26701 + num_processors++;
26703 +#endif /* CONFIG_XEN */
26705 +static void __init MP_bus_info (struct mpc_config_bus *m)
26709 + memcpy(str, m->mpc_bustype, 6);
26711 + Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
26713 + if (strncmp(str, "ISA", 3) == 0) {
26714 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
26715 + } else if (strncmp(str, "EISA", 4) == 0) {
26716 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
26717 + } else if (strncmp(str, "PCI", 3) == 0) {
26718 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
26719 + mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
26720 + mp_current_pci_id++;
26721 + } else if (strncmp(str, "MCA", 3) == 0) {
26722 + mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
26724 + printk(KERN_ERR "Unknown bustype %s\n", str);
26728 +static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
26730 + if (!(m->mpc_flags & MPC_APIC_USABLE))
26733 + printk("I/O APIC #%d Version %d at 0x%X.\n",
26734 + m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
26735 + if (nr_ioapics >= MAX_IO_APICS) {
26736 + printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
26737 + MAX_IO_APICS, nr_ioapics);
26738 + panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
26740 + if (!m->mpc_apicaddr) {
26741 + printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
26742 + " found in MP table, skipping!\n");
26745 + mp_ioapics[nr_ioapics] = *m;
26749 +static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
26751 + mp_irqs [mp_irq_entries] = *m;
26752 + Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
26753 + " IRQ %02x, APIC ID %x, APIC INT %02x\n",
26754 + m->mpc_irqtype, m->mpc_irqflag & 3,
26755 + (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
26756 + m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
26757 + if (++mp_irq_entries >= MAX_IRQ_SOURCES)
26758 + panic("Max # of irq sources exceeded!!\n");
26761 +static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
26763 + Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
26764 + " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
26765 + m->mpc_irqtype, m->mpc_irqflag & 3,
26766 + (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
26767 + m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
26769 + * Well it seems all SMP boards in existence
26770 + * use ExtINT/LVT1 == LINT0 and
26771 + * NMI/LVT2 == LINT1 - the following check
26772 + * will show us if this assumptions is false.
26773 + * Until then we do not have to add baggage.
26775 + if ((m->mpc_irqtype == mp_ExtINT) &&
26776 + (m->mpc_destapiclint != 0))
26778 + if ((m->mpc_irqtype == mp_NMI) &&
26779 + (m->mpc_destapiclint != 1))
26784 + * Read/parse the MPC
26787 +static int __init smp_read_mpc(struct mp_config_table *mpc)
26790 + int count=sizeof(*mpc);
26791 + unsigned char *mpt=((unsigned char *)mpc)+count;
26793 + if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
26794 + printk("SMP mptable: bad signature [%c%c%c%c]!\n",
26795 + mpc->mpc_signature[0],
26796 + mpc->mpc_signature[1],
26797 + mpc->mpc_signature[2],
26798 + mpc->mpc_signature[3]);
26801 + if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
26802 + printk("SMP mptable: checksum error!\n");
26805 + if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
26806 + printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
26810 + if (!mpc->mpc_lapic) {
26811 + printk(KERN_ERR "SMP mptable: null local APIC address!\n");
26814 + memcpy(str,mpc->mpc_oem,8);
26816 + printk(KERN_INFO "OEM ID: %s ",str);
26818 + memcpy(str,mpc->mpc_productid,12);
26820 + printk("Product ID: %s ",str);
26822 + printk("APIC at: 0x%X\n",mpc->mpc_lapic);
26824 + /* save the local APIC address, it might be non-default */
26826 + mp_lapic_addr = mpc->mpc_lapic;
26829 + * Now process the configuration blocks.
26831 + while (count < mpc->mpc_length) {
26833 + case MP_PROCESSOR:
26835 + struct mpc_config_processor *m=
26836 + (struct mpc_config_processor *)mpt;
26838 + MP_processor_info(m);
26839 + mpt += sizeof(*m);
26840 + count += sizeof(*m);
26845 + struct mpc_config_bus *m=
26846 + (struct mpc_config_bus *)mpt;
26848 + mpt += sizeof(*m);
26849 + count += sizeof(*m);
26854 + struct mpc_config_ioapic *m=
26855 + (struct mpc_config_ioapic *)mpt;
26856 + MP_ioapic_info(m);
26858 + count+=sizeof(*m);
26863 + struct mpc_config_intsrc *m=
26864 + (struct mpc_config_intsrc *)mpt;
26866 + MP_intsrc_info(m);
26868 + count+=sizeof(*m);
26873 + struct mpc_config_lintsrc *m=
26874 + (struct mpc_config_lintsrc *)mpt;
26875 + MP_lintsrc_info(m);
26877 + count+=sizeof(*m);
26882 + clustered_apic_check();
26883 + if (!num_processors)
26884 + printk(KERN_ERR "SMP mptable: no processors registered!\n");
26885 + return num_processors;
26888 +static int __init ELCR_trigger(unsigned int irq)
26890 + unsigned int port;
26892 + port = 0x4d0 + (irq >> 3);
26893 + return (inb(port) >> (irq & 7)) & 1;
26896 +static void __init construct_default_ioirq_mptable(int mpc_default_type)
26898 + struct mpc_config_intsrc intsrc;
26900 + int ELCR_fallback = 0;
26902 + intsrc.mpc_type = MP_INTSRC;
26903 + intsrc.mpc_irqflag = 0; /* conforming */
26904 + intsrc.mpc_srcbus = 0;
26905 + intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
26907 + intsrc.mpc_irqtype = mp_INT;
26910 + * If true, we have an ISA/PCI system with no IRQ entries
26911 + * in the MP table. To prevent the PCI interrupts from being set up
26912 + * incorrectly, we try to use the ELCR. The sanity check to see if
26913 + * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
26914 + * never be level sensitive, so we simply see if the ELCR agrees.
26915 + * If it does, we assume it's valid.
26917 + if (mpc_default_type == 5) {
26918 + printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
26920 + if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
26921 + printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
26923 + printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
26924 + ELCR_fallback = 1;
26928 + for (i = 0; i < 16; i++) {
26929 + switch (mpc_default_type) {
26931 + if (i == 0 || i == 13)
26932 + continue; /* IRQ0 & IRQ13 not connected */
26933 + /* fall through */
26936 + continue; /* IRQ2 is never connected */
26939 + if (ELCR_fallback) {
26941 + * If the ELCR indicates a level-sensitive interrupt, we
26942 + * copy that information over to the MP table in the
26943 + * irqflag field (level sensitive, active high polarity).
26945 + if (ELCR_trigger(i))
26946 + intsrc.mpc_irqflag = 13;
26948 + intsrc.mpc_irqflag = 0;
26951 + intsrc.mpc_srcbusirq = i;
26952 + intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
26953 + MP_intsrc_info(&intsrc);
26956 + intsrc.mpc_irqtype = mp_ExtINT;
26957 + intsrc.mpc_srcbusirq = 0;
26958 + intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
26959 + MP_intsrc_info(&intsrc);
26962 +static inline void __init construct_default_ISA_mptable(int mpc_default_type)
26964 + struct mpc_config_processor processor;
26965 + struct mpc_config_bus bus;
26966 + struct mpc_config_ioapic ioapic;
26967 + struct mpc_config_lintsrc lintsrc;
26968 + int linttypes[2] = { mp_ExtINT, mp_NMI };
26972 + * local APIC has default address
26974 + mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
26977 + * 2 CPUs, numbered 0 & 1.
26979 + processor.mpc_type = MP_PROCESSOR;
26980 + /* Either an integrated APIC or a discrete 82489DX. */
26981 + processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
26982 + processor.mpc_cpuflag = CPU_ENABLED;
26983 + processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
26984 + (boot_cpu_data.x86_model << 4) |
26985 + boot_cpu_data.x86_mask;
26986 + processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
26987 + processor.mpc_reserved[0] = 0;
26988 + processor.mpc_reserved[1] = 0;
26989 + for (i = 0; i < 2; i++) {
26990 + processor.mpc_apicid = i;
26991 + MP_processor_info(&processor);
26994 + bus.mpc_type = MP_BUS;
26995 + bus.mpc_busid = 0;
26996 + switch (mpc_default_type) {
26998 + printk(KERN_ERR "???\nUnknown standard configuration %d\n",
26999 + mpc_default_type);
27000 + /* fall through */
27003 + memcpy(bus.mpc_bustype, "ISA ", 6);
27008 + memcpy(bus.mpc_bustype, "EISA ", 6);
27012 + memcpy(bus.mpc_bustype, "MCA ", 6);
27014 + MP_bus_info(&bus);
27015 + if (mpc_default_type > 4) {
27016 + bus.mpc_busid = 1;
27017 + memcpy(bus.mpc_bustype, "PCI ", 6);
27018 + MP_bus_info(&bus);
27021 + ioapic.mpc_type = MP_IOAPIC;
27022 + ioapic.mpc_apicid = 2;
27023 + ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
27024 + ioapic.mpc_flags = MPC_APIC_USABLE;
27025 + ioapic.mpc_apicaddr = 0xFEC00000;
27026 + MP_ioapic_info(&ioapic);
27029 + * We set up most of the low 16 IO-APIC pins according to MPS rules.
27031 + construct_default_ioirq_mptable(mpc_default_type);
27033 + lintsrc.mpc_type = MP_LINTSRC;
27034 + lintsrc.mpc_irqflag = 0; /* conforming */
27035 + lintsrc.mpc_srcbusid = 0;
27036 + lintsrc.mpc_srcbusirq = 0;
27037 + lintsrc.mpc_destapic = MP_APIC_ALL;
27038 + for (i = 0; i < 2; i++) {
27039 + lintsrc.mpc_irqtype = linttypes[i];
27040 + lintsrc.mpc_destapiclint = i;
27041 + MP_lintsrc_info(&lintsrc);
27045 +static struct intel_mp_floating *mpf_found;
27048 + * Scan the memory blocks for an SMP configuration block.
27050 +void __init get_smp_config (void)
27052 + struct intel_mp_floating *mpf = mpf_found;
27055 + * ACPI supports both logical (e.g. Hyper-Threading) and physical
27056 + * processors, where MPS only supports physical.
27058 + if (acpi_lapic && acpi_ioapic) {
27059 + printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
27062 + else if (acpi_lapic)
27063 + printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
27065 + printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
27066 + if (mpf->mpf_feature2 & (1<<7)) {
27067 + printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
27070 + printk(KERN_INFO " Virtual Wire compatibility mode.\n");
27075 + * Now see if we need to read further.
27077 + if (mpf->mpf_feature1 != 0) {
27079 + printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
27080 + construct_default_ISA_mptable(mpf->mpf_feature1);
27082 + } else if (mpf->mpf_physptr) {
27085 + * Read the physical hardware table. Anything here will
27086 + * override the defaults.
27088 + if (!smp_read_mpc(isa_bus_to_virt(mpf->mpf_physptr))) {
27089 + smp_found_config = 0;
27090 + printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
27091 + printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
27095 + * If there are no explicit MP IRQ entries, then we are
27096 + * broken. We set up most of the low 16 IO-APIC pins to
27097 + * ISA defaults and hope it will work.
27099 + if (!mp_irq_entries) {
27100 + struct mpc_config_bus bus;
27102 + printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
27104 + bus.mpc_type = MP_BUS;
27105 + bus.mpc_busid = 0;
27106 + memcpy(bus.mpc_bustype, "ISA ", 6);
27107 + MP_bus_info(&bus);
27109 + construct_default_ioirq_mptable(0);
27115 + printk(KERN_INFO "Processors: %d\n", num_processors);
27117 + * Only use the first configuration found.
27121 +static int __init smp_scan_config (unsigned long base, unsigned long length)
27123 + extern void __bad_mpf_size(void);
27124 + unsigned int *bp = isa_bus_to_virt(base);
27125 + struct intel_mp_floating *mpf;
27127 + Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
27128 + if (sizeof(*mpf) != 16)
27129 + __bad_mpf_size();
27131 + while (length > 0) {
27132 + mpf = (struct intel_mp_floating *)bp;
27133 + if ((*bp == SMP_MAGIC_IDENT) &&
27134 + (mpf->mpf_length == 1) &&
27135 + !mpf_checksum((unsigned char *)bp, 16) &&
27136 + ((mpf->mpf_specification == 1)
27137 + || (mpf->mpf_specification == 4)) ) {
27139 + smp_found_config = 1;
27149 +void __init find_intel_smp (void)
27151 + unsigned int address;
27154 + * FIXME: Linux assumes you have 640K of base ram..
27155 + * this continues the error...
27157 + * 1) Scan the bottom 1K for a signature
27158 + * 2) Scan the top 1K of base RAM
27159 + * 3) Scan the 64K of bios
27161 + if (smp_scan_config(0x0,0x400) ||
27162 + smp_scan_config(639*0x400,0x400) ||
27163 + smp_scan_config(0xF0000,0x10000))
27166 + * If it is an SMP machine we should know now, unless the
27167 + * configuration is in an EISA/MCA bus machine with an
27168 + * extended bios data area.
27170 + * there is a real-mode segmented pointer pointing to the
27171 + * 4K EBDA area at 0x40E, calculate and scan it here.
27173 + * NOTE! There are Linux loaders that will corrupt the EBDA
27174 + * area, and as such this kind of SMP config may be less
27175 + * trustworthy, simply because the SMP table may have been
27176 + * stomped on during early boot. These loaders are buggy and
27177 + * should be fixed.
27180 + address = *(unsigned short *)phys_to_virt(0x40E);
27182 + if (smp_scan_config(address, 0x1000))
27185 + /* If we have come this far, we did not find an MP table */
27186 + printk(KERN_INFO "No mptable found.\n");
27190 + * - Intel MP Configuration Table
27192 +void __init find_smp_config (void)
27194 +#ifdef CONFIG_X86_LOCAL_APIC
27195 + find_intel_smp();
27200 +/* --------------------------------------------------------------------------
27201 + ACPI-based MP Configuration
27202 + -------------------------------------------------------------------------- */
27204 +#ifdef CONFIG_ACPI
27206 +void __init mp_register_lapic_address (
27209 +#ifndef CONFIG_XEN
27210 + mp_lapic_addr = (unsigned long) address;
27212 + set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
27214 + if (boot_cpu_id == -1U)
27215 + boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
27217 + Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
27222 +void __cpuinit mp_register_lapic (
27226 + struct mpc_config_processor processor;
27227 + int boot_cpu = 0;
27229 + if (id >= MAX_APICS) {
27230 + printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
27235 + if (id == boot_cpu_physical_apicid)
27238 +#ifndef CONFIG_XEN
27239 + processor.mpc_type = MP_PROCESSOR;
27240 + processor.mpc_apicid = id;
27241 + processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
27242 + processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
27243 + processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
27244 + processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
27245 + (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
27246 + processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
27247 + processor.mpc_reserved[0] = 0;
27248 + processor.mpc_reserved[1] = 0;
27251 + MP_processor_info(&processor);
27254 +#ifdef CONFIG_X86_IO_APIC
27256 +#define MP_ISA_BUS 0
27257 +#define MP_MAX_IOAPIC_PIN 127
27259 +static struct mp_ioapic_routing {
27263 + u32 pin_programmed[4];
27264 +} mp_ioapic_routing[MAX_IO_APICS];
27267 +static int mp_find_ioapic (
27272 + /* Find the IOAPIC that manages this GSI. */
27273 + for (i = 0; i < nr_ioapics; i++) {
27274 + if ((gsi >= mp_ioapic_routing[i].gsi_start)
27275 + && (gsi <= mp_ioapic_routing[i].gsi_end))
27279 + printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
27285 +void __init mp_register_ioapic (
27292 + if (nr_ioapics >= MAX_IO_APICS) {
27293 + printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
27294 + "(found %d)\n", MAX_IO_APICS, nr_ioapics);
27295 + panic("Recompile kernel with bigger MAX_IO_APICS!\n");
27298 + printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
27299 + " found in MADT table, skipping!\n");
27303 + idx = nr_ioapics++;
27305 + mp_ioapics[idx].mpc_type = MP_IOAPIC;
27306 + mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
27307 + mp_ioapics[idx].mpc_apicaddr = address;
27309 +#ifndef CONFIG_XEN
27310 + set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
27312 + mp_ioapics[idx].mpc_apicid = id;
27313 + mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
27316 + * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
27317 + * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
27319 + mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
27320 + mp_ioapic_routing[idx].gsi_start = gsi_base;
27321 + mp_ioapic_routing[idx].gsi_end = gsi_base +
27322 + io_apic_get_redir_entries(idx);
27324 + printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
27325 + "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
27326 + mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
27327 + mp_ioapic_routing[idx].gsi_start,
27328 + mp_ioapic_routing[idx].gsi_end);
27334 +void __init mp_override_legacy_irq (
27340 + struct mpc_config_intsrc intsrc;
27345 + * Convert 'gsi' to 'ioapic.pin'.
27347 + ioapic = mp_find_ioapic(gsi);
27350 + pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
27353 + * TBD: This check is for faulty timer entries, where the override
27354 + * erroneously sets the trigger to level, resulting in a HUGE
27355 + * increase of timer interrupts!
27357 + if ((bus_irq == 0) && (trigger == 3))
27360 + intsrc.mpc_type = MP_INTSRC;
27361 + intsrc.mpc_irqtype = mp_INT;
27362 + intsrc.mpc_irqflag = (trigger << 2) | polarity;
27363 + intsrc.mpc_srcbus = MP_ISA_BUS;
27364 + intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
27365 + intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
27366 + intsrc.mpc_dstirq = pin; /* INTIN# */
27368 + Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
27369 + intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
27370 + (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
27371 + intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
27373 + mp_irqs[mp_irq_entries] = intsrc;
27374 + if (++mp_irq_entries == MAX_IRQ_SOURCES)
27375 + panic("Max # of irq sources exceeded!\n");
27381 +void __init mp_config_acpi_legacy_irqs (void)
27383 + struct mpc_config_intsrc intsrc;
27388 + * Fabricate the legacy ISA bus (bus #31).
27390 + mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
27391 + Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
27394 + * Locate the IOAPIC that manages the ISA IRQs (0-15).
27396 + ioapic = mp_find_ioapic(0);
27400 + intsrc.mpc_type = MP_INTSRC;
27401 + intsrc.mpc_irqflag = 0; /* Conforming */
27402 + intsrc.mpc_srcbus = MP_ISA_BUS;
27403 + intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
27406 + * Use the default configuration for the IRQs 0-15. Unless
27407 + * overridden by (MADT) interrupt source override entries.
27409 + for (i = 0; i < 16; i++) {
27412 + for (idx = 0; idx < mp_irq_entries; idx++) {
27413 + struct mpc_config_intsrc *irq = mp_irqs + idx;
27415 + /* Do we already have a mapping for this ISA IRQ? */
27416 + if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
27419 + /* Do we already have a mapping for this IOAPIC pin */
27420 + if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
27421 + (irq->mpc_dstirq == i))
27425 + if (idx != mp_irq_entries) {
27426 + printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
27427 + continue; /* IRQ already used */
27430 + intsrc.mpc_irqtype = mp_INT;
27431 + intsrc.mpc_srcbusirq = i; /* Identity mapped */
27432 + intsrc.mpc_dstirq = i;
27434 + Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
27435 + "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
27436 + (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
27437 + intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
27438 + intsrc.mpc_dstirq);
27440 + mp_irqs[mp_irq_entries] = intsrc;
27441 + if (++mp_irq_entries == MAX_IRQ_SOURCES)
27442 + panic("Max # of irq sources exceeded!\n");
27448 +#define MAX_GSI_NUM 4096
27450 +int mp_register_gsi(u32 gsi, int triggering, int polarity)
27453 + int ioapic_pin = 0;
27454 + int idx, bit = 0;
27455 + static int pci_irq = 16;
27457 + * Mapping between Global System Interrupts, which
27458 + * represent all possible interrupts, to the IRQs
27459 + * assigned to actual devices.
27461 + static int gsi_to_irq[MAX_GSI_NUM];
27463 + if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
27466 + /* Don't set up the ACPI SCI because it's already set up */
27467 + if (acpi_fadt.sci_int == gsi)
27470 + ioapic = mp_find_ioapic(gsi);
27471 + if (ioapic < 0) {
27472 + printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
27476 + ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
27479 + * Avoid pin reprogramming. PRTs typically include entries
27480 + * with redundant pin->gsi mappings (but unique PCI devices);
27481 + * we only program the IOAPIC on the first.
27483 + bit = ioapic_pin % 32;
27484 + idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
27486 + printk(KERN_ERR "Invalid reference to IOAPIC pin "
27487 + "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
27491 + if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
27492 + Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
27493 + mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
27494 + return gsi_to_irq[gsi];
27497 + mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
27499 + if (triggering == ACPI_LEVEL_SENSITIVE) {
27501 + * For PCI devices assign IRQs in order, avoiding gaps
27502 + * due to unused I/O APIC pins.
27505 + if (gsi < MAX_GSI_NUM) {
27507 + * Retain the VIA chipset work-around (gsi > 15), but
27508 + * avoid a problem where the 8254 timer (IRQ0) is setup
27509 + * via an override (so it's not on pin 0 of the ioapic),
27510 + * and at the same time, the pin 0 interrupt is a PCI
27511 + * type. The gsi > 15 test could cause these two pins
27512 + * to be shared as IRQ0, and they are not shareable.
27513 + * So test for this condition, and if necessary, avoid
27514 + * the pin collision.
27516 + if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
27519 + * Don't assign IRQ used by ACPI SCI
27521 + if (gsi == acpi_fadt.sci_int)
27523 + gsi_to_irq[irq] = gsi;
27525 + printk(KERN_ERR "GSI %u is too high\n", gsi);
27530 + io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
27531 + triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
27532 + polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
27536 +#endif /*CONFIG_X86_IO_APIC*/
27537 +#endif /*CONFIG_ACPI*/
27538 Index: head-2008-11-25/arch/x86/kernel/process_64-xen.c
27539 ===================================================================
27540 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
27541 +++ head-2008-11-25/arch/x86/kernel/process_64-xen.c 2008-08-07 12:44:36.000000000 +0200
27544 + * linux/arch/x86-64/kernel/process.c
27546 + * Copyright (C) 1995 Linus Torvalds
27548 + * Pentium III FXSR, SSE support
27549 + * Gareth Hughes <gareth@valinux.com>, May 2000
27554 + * CPU hotplug support - ashok.raj@intel.com
27556 + * Jun Nakajima <jun.nakajima@intel.com>
27557 + * Modified for Xen
27561 + * This file handles the architecture-dependent parts of process handling..
27564 +#include <stdarg.h>
27566 +#include <linux/cpu.h>
27567 +#include <linux/errno.h>
27568 +#include <linux/sched.h>
27569 +#include <linux/kernel.h>
27570 +#include <linux/mm.h>
27571 +#include <linux/elfcore.h>
27572 +#include <linux/smp.h>
27573 +#include <linux/slab.h>
27574 +#include <linux/user.h>
27575 +#include <linux/module.h>
27576 +#include <linux/a.out.h>
27577 +#include <linux/interrupt.h>
27578 +#include <linux/delay.h>
27579 +#include <linux/ptrace.h>
27580 +#include <linux/utsname.h>
27581 +#include <linux/random.h>
27582 +#include <linux/notifier.h>
27583 +#include <linux/kprobes.h>
27585 +#include <asm/uaccess.h>
27586 +#include <asm/pgtable.h>
27587 +#include <asm/system.h>
27588 +#include <asm/io.h>
27589 +#include <asm/processor.h>
27590 +#include <asm/i387.h>
27591 +#include <asm/mmu_context.h>
27592 +#include <asm/pda.h>
27593 +#include <asm/prctl.h>
27594 +#include <asm/kdebug.h>
27595 +#include <xen/interface/platform.h>
27596 +#include <xen/interface/physdev.h>
27597 +#include <xen/interface/vcpu.h>
27598 +#include <asm/desc.h>
27599 +#include <asm/proto.h>
27600 +#include <asm/hardirq.h>
27601 +#include <asm/ia32.h>
27602 +#include <asm/idle.h>
27604 +#include <xen/cpu_hotplug.h>
27606 +asmlinkage extern void ret_from_fork(void);
27608 +unsigned long kernel_thread_flags = CLONE_VM | CLONE_UNTRACED;
27610 +unsigned long boot_option_idle_override = 0;
27611 +EXPORT_SYMBOL(boot_option_idle_override);
27614 + * Powermanagement idle function, if any..
27616 +void (*pm_idle)(void);
27617 +EXPORT_SYMBOL(pm_idle);
27618 +static DEFINE_PER_CPU(unsigned int, cpu_idle_state);
27620 +static ATOMIC_NOTIFIER_HEAD(idle_notifier);
27622 +void idle_notifier_register(struct notifier_block *n)
27624 + atomic_notifier_chain_register(&idle_notifier, n);
27626 +EXPORT_SYMBOL_GPL(idle_notifier_register);
27628 +void idle_notifier_unregister(struct notifier_block *n)
27630 + atomic_notifier_chain_unregister(&idle_notifier, n);
27632 +EXPORT_SYMBOL(idle_notifier_unregister);
27634 +enum idle_state { CPU_IDLE, CPU_NOT_IDLE };
27635 +static DEFINE_PER_CPU(enum idle_state, idle_state) = CPU_NOT_IDLE;
27637 +void enter_idle(void)
27639 + __get_cpu_var(idle_state) = CPU_IDLE;
27640 + atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
27643 +static void __exit_idle(void)
27645 + __get_cpu_var(idle_state) = CPU_NOT_IDLE;
27646 + atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
27649 +/* Called from interrupts to signify idle end */
27650 +void exit_idle(void)
27652 + if (current->pid | read_pda(irqcount))
27658 + * On SMP it's slightly faster (but much more power-consuming!)
27659 + * to poll the ->need_resched flag instead of waiting for the
27660 + * cross-CPU IPI to arrive. Use this option with caution.
27662 +static void poll_idle (void)
27664 + local_irq_enable();
27672 + "i" (_TIF_NEED_RESCHED),
27673 + "m" (current_thread_info()->flags));
27676 +static void xen_idle(void)
27678 + local_irq_disable();
27680 + if (need_resched())
27681 + local_irq_enable();
27683 + current_thread_info()->status &= ~TS_POLLING;
27684 + smp_mb__after_clear_bit();
27686 + current_thread_info()->status |= TS_POLLING;
27690 +#ifdef CONFIG_HOTPLUG_CPU
27691 +static inline void play_dead(void)
27693 + idle_task_exit();
27694 + local_irq_disable();
27695 + cpu_clear(smp_processor_id(), cpu_initialized);
27696 + preempt_enable_no_resched();
27697 + VOID(HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL));
27701 +static inline void play_dead(void)
27705 +#endif /* CONFIG_HOTPLUG_CPU */
27708 + * The idle thread. There's no useful work to be
27709 + * done, so just try to conserve power and have a
27710 + * low exit latency (ie sit in a loop waiting for
27711 + * somebody to say that they'd like to reschedule)
27713 +void cpu_idle (void)
27715 + current_thread_info()->status |= TS_POLLING;
27716 + /* endless idle loop with no priority at all */
27718 + while (!need_resched()) {
27719 + void (*idle)(void);
27721 + if (__get_cpu_var(cpu_idle_state))
27722 + __get_cpu_var(cpu_idle_state) = 0;
27724 + idle = xen_idle; /* no alternatives */
27725 + if (cpu_is_offline(smp_processor_id()))
27732 + preempt_enable_no_resched();
27734 + preempt_disable();
27738 +void cpu_idle_wait(void)
27740 + unsigned int cpu, this_cpu = get_cpu();
27743 + set_cpus_allowed(current, cpumask_of_cpu(this_cpu));
27747 + for_each_online_cpu(cpu) {
27748 + per_cpu(cpu_idle_state, cpu) = 1;
27749 + cpu_set(cpu, map);
27752 + __get_cpu_var(cpu_idle_state) = 0;
27757 + for_each_online_cpu(cpu) {
27758 + if (cpu_isset(cpu, map) &&
27759 + !per_cpu(cpu_idle_state, cpu))
27760 + cpu_clear(cpu, map);
27762 + cpus_and(map, map, cpu_online_map);
27763 + } while (!cpus_empty(map));
27765 +EXPORT_SYMBOL_GPL(cpu_idle_wait);
27767 +void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
27771 +static int __init idle_setup (char *str)
27773 + if (!strncmp(str, "poll", 4)) {
27774 + printk("using polling idle threads.\n");
27775 + pm_idle = poll_idle;
27778 + boot_option_idle_override = 1;
27782 +__setup("idle=", idle_setup);
27784 +/* Prints also some state that isn't saved in the pt_regs */
27785 +void __show_regs(struct pt_regs * regs)
27787 + unsigned long fs, gs, shadowgs;
27788 + unsigned int fsindex,gsindex;
27789 + unsigned int ds,cs,es;
27793 + printk("Pid: %d, comm: %.20s %s %s %.*s\n",
27794 + current->pid, current->comm, print_tainted(),
27795 + system_utsname.release,
27796 + (int)strcspn(system_utsname.version, " "),
27797 + system_utsname.version);
27798 + printk("RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->rip);
27799 + printk_address(regs->rip);
27800 + printk("RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss, regs->rsp,
27802 + printk("RAX: %016lx RBX: %016lx RCX: %016lx\n",
27803 + regs->rax, regs->rbx, regs->rcx);
27804 + printk("RDX: %016lx RSI: %016lx RDI: %016lx\n",
27805 + regs->rdx, regs->rsi, regs->rdi);
27806 + printk("RBP: %016lx R08: %016lx R09: %016lx\n",
27807 + regs->rbp, regs->r8, regs->r9);
27808 + printk("R10: %016lx R11: %016lx R12: %016lx\n",
27809 + regs->r10, regs->r11, regs->r12);
27810 + printk("R13: %016lx R14: %016lx R15: %016lx\n",
27811 + regs->r13, regs->r14, regs->r15);
27813 + asm("mov %%ds,%0" : "=r" (ds));
27814 + asm("mov %%cs,%0" : "=r" (cs));
27815 + asm("mov %%es,%0" : "=r" (es));
27816 + asm("mov %%fs,%0" : "=r" (fsindex));
27817 + asm("mov %%gs,%0" : "=r" (gsindex));
27819 + rdmsrl(MSR_FS_BASE, fs);
27820 + rdmsrl(MSR_GS_BASE, gs);
27821 + rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
27823 + printk("FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
27824 + fs,fsindex,gs,gsindex,shadowgs);
27825 + printk("CS: %04x DS: %04x ES: %04x\n", cs, ds, es);
27829 +void show_regs(struct pt_regs *regs)
27831 + printk("CPU %d:", smp_processor_id());
27832 + __show_regs(regs);
27833 + show_trace(NULL, regs, (void *)(regs + 1));
27837 + * Free current thread data structures etc..
27839 +void exit_thread(void)
27841 + struct task_struct *me = current;
27842 + struct thread_struct *t = &me->thread;
27844 + if (me->thread.io_bitmap_ptr) {
27845 +#ifndef CONFIG_X86_NO_TSS
27846 + struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
27849 + struct physdev_set_iobitmap iobmp_op;
27850 + memset(&iobmp_op, 0, sizeof(iobmp_op));
27853 + kfree(t->io_bitmap_ptr);
27854 + t->io_bitmap_ptr = NULL;
27856 + * Careful, clear this in the TSS too:
27858 +#ifndef CONFIG_X86_NO_TSS
27859 + memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
27863 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap,
27866 + t->io_bitmap_max = 0;
27870 +void load_gs_index(unsigned gs)
27872 + WARN_ON(HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, gs));
27875 +void flush_thread(void)
27877 + struct task_struct *tsk = current;
27878 + struct thread_info *t = current_thread_info();
27880 + if (t->flags & _TIF_ABI_PENDING) {
27881 + t->flags ^= (_TIF_ABI_PENDING | _TIF_IA32);
27882 + if (t->flags & _TIF_IA32)
27883 + current_thread_info()->status |= TS_COMPAT;
27886 + tsk->thread.debugreg0 = 0;
27887 + tsk->thread.debugreg1 = 0;
27888 + tsk->thread.debugreg2 = 0;
27889 + tsk->thread.debugreg3 = 0;
27890 + tsk->thread.debugreg6 = 0;
27891 + tsk->thread.debugreg7 = 0;
27892 + memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
27894 + * Forget coprocessor state..
27897 + clear_used_math();
27900 +void release_thread(struct task_struct *dead_task)
27902 + if (dead_task->mm) {
27903 + if (dead_task->mm->context.size) {
27904 + printk("WARNING: dead process %8s still has LDT? <%p/%d>\n",
27906 + dead_task->mm->context.ldt,
27907 + dead_task->mm->context.size);
27913 +static inline void set_32bit_tls(struct task_struct *t, int tls, u32 addr)
27915 + struct user_desc ud = {
27916 + .base_addr = addr,
27917 + .limit = 0xfffff,
27919 + .limit_in_pages = 1,
27922 + struct n_desc_struct *desc = (void *)t->thread.tls_array;
27924 + desc->a = LDT_entry_a(&ud);
27925 + desc->b = LDT_entry_b(&ud);
27928 +static inline u32 read_32bit_tls(struct task_struct *t, int tls)
27930 + struct desc_struct *desc = (void *)t->thread.tls_array;
27932 + return desc->base0 |
27933 + (((u32)desc->base1) << 16) |
27934 + (((u32)desc->base2) << 24);
27938 + * This gets called before we allocate a new thread and copy
27939 + * the current task into it.
27941 +void prepare_to_copy(struct task_struct *tsk)
27946 +int copy_thread(int nr, unsigned long clone_flags, unsigned long rsp,
27947 + unsigned long unused,
27948 + struct task_struct * p, struct pt_regs * regs)
27951 + struct pt_regs * childregs;
27952 + struct task_struct *me = current;
27954 + childregs = ((struct pt_regs *)
27955 + (THREAD_SIZE + task_stack_page(p))) - 1;
27956 + *childregs = *regs;
27958 + childregs->rax = 0;
27959 + childregs->rsp = rsp;
27961 + childregs->rsp = (unsigned long)childregs;
27963 + p->thread.rsp = (unsigned long) childregs;
27964 + p->thread.rsp0 = (unsigned long) (childregs+1);
27965 + p->thread.userrsp = me->thread.userrsp;
27967 + set_tsk_thread_flag(p, TIF_FORK);
27969 + p->thread.fs = me->thread.fs;
27970 + p->thread.gs = me->thread.gs;
27972 + asm("mov %%gs,%0" : "=m" (p->thread.gsindex));
27973 + asm("mov %%fs,%0" : "=m" (p->thread.fsindex));
27974 + asm("mov %%es,%0" : "=m" (p->thread.es));
27975 + asm("mov %%ds,%0" : "=m" (p->thread.ds));
27977 + if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
27978 + p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
27979 + if (!p->thread.io_bitmap_ptr) {
27980 + p->thread.io_bitmap_max = 0;
27983 + memcpy(p->thread.io_bitmap_ptr, me->thread.io_bitmap_ptr,
27984 + IO_BITMAP_BYTES);
27988 + * Set a new TLS for the child thread?
27990 + if (clone_flags & CLONE_SETTLS) {
27991 +#ifdef CONFIG_IA32_EMULATION
27992 + if (test_thread_flag(TIF_IA32))
27993 + err = ia32_child_tls(p, childregs);
27996 + err = do_arch_prctl(p, ARCH_SET_FS, childregs->r8);
28000 + p->thread.iopl = current->thread.iopl;
28004 + if (err && p->thread.io_bitmap_ptr) {
28005 + kfree(p->thread.io_bitmap_ptr);
28006 + p->thread.io_bitmap_max = 0;
28011 +static inline void __save_init_fpu( struct task_struct *tsk )
28013 + asm volatile( "rex64 ; fxsave %0 ; fnclex"
28014 + : "=m" (tsk->thread.i387.fxsave));
28015 + tsk->thread_info->status &= ~TS_USEDFPU;
28019 + * switch_to(x,y) should switch tasks from x to y.
28021 + * This could still be optimized:
28022 + * - fold all the options into a flag word and test it with a single test.
28023 + * - could test fs/gs bitsliced
28025 + * Kprobes not supported here. Set the probe on schedule instead.
28027 +__kprobes struct task_struct *
28028 +__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
28030 + struct thread_struct *prev = &prev_p->thread,
28031 + *next = &next_p->thread;
28032 + int cpu = smp_processor_id();
28033 +#ifndef CONFIG_X86_NO_TSS
28034 + struct tss_struct *tss = &per_cpu(init_tss, cpu);
28036 +#if CONFIG_XEN_COMPAT > 0x030002
28037 + struct physdev_set_iopl iopl_op;
28038 + struct physdev_set_iobitmap iobmp_op;
28040 + struct physdev_op _pdo[2], *pdo = _pdo;
28041 +#define iopl_op pdo->u.set_iopl
28042 +#define iobmp_op pdo->u.set_iobitmap
28044 + multicall_entry_t _mcl[8], *mcl = _mcl;
28047 + * This is basically '__unlazy_fpu', except that we queue a
28048 + * multicall to indicate FPU task switch, rather than
28049 + * synchronously trapping to Xen.
28050 + * The AMD workaround requires it to be after DS reload, or
28051 + * after DS has been cleared, which we do in __prepare_arch_switch.
28053 + if (prev_p->thread_info->status & TS_USEDFPU) {
28054 + __save_init_fpu(prev_p); /* _not_ save_init_fpu() */
28055 + mcl->op = __HYPERVISOR_fpu_taskswitch;
28056 + mcl->args[0] = 1;
28061 + * Reload esp0, LDT and the page table pointer:
28063 + mcl->op = __HYPERVISOR_stack_switch;
28064 + mcl->args[0] = __KERNEL_DS;
28065 + mcl->args[1] = next->rsp0;
28069 + * Load the per-thread Thread-Local Storage descriptor.
28070 + * This is load_TLS(next, cpu) with multicalls.
28072 +#define C(i) do { \
28073 + if (unlikely(next->tls_array[i] != prev->tls_array[i])) { \
28074 + mcl->op = __HYPERVISOR_update_descriptor; \
28075 + mcl->args[0] = virt_to_machine( \
28076 + &cpu_gdt(cpu)[GDT_ENTRY_TLS_MIN + i]); \
28077 + mcl->args[1] = next->tls_array[i]; \
28081 + C(0); C(1); C(2);
28084 + if (unlikely(prev->iopl != next->iopl)) {
28085 + iopl_op.iopl = (next->iopl == 0) ? 1 : next->iopl;
28086 +#if CONFIG_XEN_COMPAT > 0x030002
28087 + mcl->op = __HYPERVISOR_physdev_op;
28088 + mcl->args[0] = PHYSDEVOP_set_iopl;
28089 + mcl->args[1] = (unsigned long)&iopl_op;
28091 + mcl->op = __HYPERVISOR_physdev_op_compat;
28092 + pdo->cmd = PHYSDEVOP_set_iopl;
28093 + mcl->args[0] = (unsigned long)pdo++;
28098 + if (unlikely(prev->io_bitmap_ptr || next->io_bitmap_ptr)) {
28099 + set_xen_guest_handle(iobmp_op.bitmap,
28100 + (char *)next->io_bitmap_ptr);
28101 + iobmp_op.nr_ports = next->io_bitmap_ptr ? IO_BITMAP_BITS : 0;
28102 +#if CONFIG_XEN_COMPAT > 0x030002
28103 + mcl->op = __HYPERVISOR_physdev_op;
28104 + mcl->args[0] = PHYSDEVOP_set_iobitmap;
28105 + mcl->args[1] = (unsigned long)&iobmp_op;
28107 + mcl->op = __HYPERVISOR_physdev_op_compat;
28108 + pdo->cmd = PHYSDEVOP_set_iobitmap;
28109 + mcl->args[0] = (unsigned long)pdo++;
28114 +#if CONFIG_XEN_COMPAT <= 0x030002
28115 + BUG_ON(pdo > _pdo + ARRAY_SIZE(_pdo));
28117 + BUG_ON(mcl > _mcl + ARRAY_SIZE(_mcl));
28118 + if (unlikely(HYPERVISOR_multicall_check(_mcl, mcl - _mcl, NULL)))
28122 + * Switch DS and ES.
28123 + * This won't pick up thread selector changes, but I guess that is ok.
28125 + if (unlikely(next->es))
28126 + loadsegment(es, next->es);
28128 + if (unlikely(next->ds))
28129 + loadsegment(ds, next->ds);
28132 + * Switch FS and GS.
28134 + if (unlikely(next->fsindex))
28135 + loadsegment(fs, next->fsindex);
28138 + WARN_ON(HYPERVISOR_set_segment_base(SEGBASE_FS, next->fs));
28140 + if (unlikely(next->gsindex))
28141 + load_gs_index(next->gsindex);
28144 + WARN_ON(HYPERVISOR_set_segment_base(SEGBASE_GS_USER, next->gs));
28147 + * Switch the PDA context.
28149 + prev->userrsp = read_pda(oldrsp);
28150 + write_pda(oldrsp, next->userrsp);
28151 + write_pda(pcurrent, next_p);
28152 + write_pda(kernelstack,
28153 + task_stack_page(next_p) + THREAD_SIZE - PDA_STACKOFFSET);
28156 + * Now maybe reload the debug registers
28158 + if (unlikely(next->debugreg7)) {
28159 + set_debugreg(next->debugreg0, 0);
28160 + set_debugreg(next->debugreg1, 1);
28161 + set_debugreg(next->debugreg2, 2);
28162 + set_debugreg(next->debugreg3, 3);
28164 + set_debugreg(next->debugreg6, 6);
28165 + set_debugreg(next->debugreg7, 7);
28172 + * sys_execve() executes a new program.
28175 +long sys_execve(char __user *name, char __user * __user *argv,
28176 + char __user * __user *envp, struct pt_regs regs)
28181 + filename = getname(name);
28182 + error = PTR_ERR(filename);
28183 + if (IS_ERR(filename))
28185 + error = do_execve(filename, argv, envp, ®s);
28186 + if (error == 0) {
28187 + task_lock(current);
28188 + current->ptrace &= ~PT_DTRACE;
28189 + task_unlock(current);
28191 + putname(filename);
28195 +void set_personality_64bit(void)
28197 + /* inherit personality from parent */
28199 + /* Make sure to be in 64bit mode */
28200 + clear_thread_flag(TIF_IA32);
28202 + /* TBD: overwrites user setup. Should have two bits.
28203 + But 64bit processes have always behaved this way,
28204 + so it's not too bad. The main problem is just that
28205 + 32bit childs are affected again. */
28206 + current->personality &= ~READ_IMPLIES_EXEC;
28209 +asmlinkage long sys_fork(struct pt_regs *regs)
28211 + return do_fork(SIGCHLD, regs->rsp, regs, 0, NULL, NULL);
28215 +sys_clone(unsigned long clone_flags, unsigned long newsp,
28216 + void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
28219 + newsp = regs->rsp;
28220 + return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
28224 + * This is trivial, and on the face of it looks like it
28225 + * could equally well be done in user mode.
28227 + * Not so, for quite unobvious reasons - register pressure.
28228 + * In user mode vfork() cannot have a stack frame, and if
28229 + * done by calling the "clone()" system call directly, you
28230 + * do not have enough call-clobbered registers to hold all
28231 + * the information you need.
28233 +asmlinkage long sys_vfork(struct pt_regs *regs)
28235 + return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->rsp, regs, 0,
28239 +unsigned long get_wchan(struct task_struct *p)
28241 + unsigned long stack;
28245 + if (!p || p == current || p->state==TASK_RUNNING)
28247 + stack = (unsigned long)task_stack_page(p);
28248 + if (p->thread.rsp < stack || p->thread.rsp > stack+THREAD_SIZE)
28250 + fp = *(u64 *)(p->thread.rsp);
28252 + if (fp < (unsigned long)stack ||
28253 + fp > (unsigned long)stack+THREAD_SIZE)
28255 + rip = *(u64 *)(fp+8);
28256 + if (!in_sched_functions(rip))
28259 + } while (count++ < 16);
28263 +long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
28266 + int doit = task == current;
28270 + case ARCH_SET_GS:
28271 + if (addr >= TASK_SIZE_OF(task))
28274 + /* handle small bases via the GDT because that's faster to
28276 + if (addr <= 0xffffffff) {
28277 + set_32bit_tls(task, GS_TLS, addr);
28279 + load_TLS(&task->thread, cpu);
28280 + load_gs_index(GS_TLS_SEL);
28282 + task->thread.gsindex = GS_TLS_SEL;
28283 + task->thread.gs = 0;
28285 + task->thread.gsindex = 0;
28286 + task->thread.gs = addr;
28288 + load_gs_index(0);
28289 + ret = HYPERVISOR_set_segment_base(
28290 + SEGBASE_GS_USER, addr);
28295 + case ARCH_SET_FS:
28296 + /* Not strictly needed for fs, but do it for symmetry
28298 + if (addr >= TASK_SIZE_OF(task))
28301 + /* handle small bases via the GDT because that's faster to
28303 + if (addr <= 0xffffffff) {
28304 + set_32bit_tls(task, FS_TLS, addr);
28306 + load_TLS(&task->thread, cpu);
28307 + asm volatile("movl %0,%%fs" :: "r"(FS_TLS_SEL));
28309 + task->thread.fsindex = FS_TLS_SEL;
28310 + task->thread.fs = 0;
28312 + task->thread.fsindex = 0;
28313 + task->thread.fs = addr;
28315 + /* set the selector to 0 to not confuse
28317 + asm volatile("movl %0,%%fs" :: "r" (0));
28318 + ret = HYPERVISOR_set_segment_base(SEGBASE_FS,
28324 + case ARCH_GET_FS: {
28325 + unsigned long base;
28326 + if (task->thread.fsindex == FS_TLS_SEL)
28327 + base = read_32bit_tls(task, FS_TLS);
28329 + rdmsrl(MSR_FS_BASE, base);
28331 + base = task->thread.fs;
28332 + ret = put_user(base, (unsigned long __user *)addr);
28335 + case ARCH_GET_GS: {
28336 + unsigned long base;
28337 + unsigned gsindex;
28338 + if (task->thread.gsindex == GS_TLS_SEL)
28339 + base = read_32bit_tls(task, GS_TLS);
28341 + asm("movl %%gs,%0" : "=r" (gsindex));
28343 + rdmsrl(MSR_KERNEL_GS_BASE, base);
28345 + base = task->thread.gs;
28348 + base = task->thread.gs;
28349 + ret = put_user(base, (unsigned long __user *)addr);
28361 +long sys_arch_prctl(int code, unsigned long addr)
28363 + return do_arch_prctl(current, code, addr);
28367 + * Capture the user space registers if the task is not running (in user space)
28369 +int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
28371 + struct pt_regs *pp, ptregs;
28373 + pp = task_pt_regs(tsk);
28376 + ptregs.cs &= 0xffff;
28377 + ptregs.ss &= 0xffff;
28379 + elf_core_copy_regs(regs, &ptregs);
28381 + boot_option_idle_override = 1;
28385 +unsigned long arch_align_stack(unsigned long sp)
28387 + if (randomize_va_space)
28388 + sp -= get_random_int() % 8192;
28389 + return sp & ~0xf;
28391 Index: head-2008-11-25/arch/x86/kernel/setup_64-xen.c
28392 ===================================================================
28393 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
28394 +++ head-2008-11-25/arch/x86/kernel/setup_64-xen.c 2008-04-22 15:41:51.000000000 +0200
28397 + * linux/arch/x86-64/kernel/setup.c
28399 + * Copyright (C) 1995 Linus Torvalds
28401 + * Nov 2001 Dave Jones <davej@suse.de>
28402 + * Forked from i386 setup code.
28406 + * This file handles the architecture-dependent parts of initialization
28409 +#include <linux/errno.h>
28410 +#include <linux/sched.h>
28411 +#include <linux/kernel.h>
28412 +#include <linux/mm.h>
28413 +#include <linux/stddef.h>
28414 +#include <linux/unistd.h>
28415 +#include <linux/ptrace.h>
28416 +#include <linux/slab.h>
28417 +#include <linux/user.h>
28418 +#include <linux/a.out.h>
28419 +#include <linux/screen_info.h>
28420 +#include <linux/ioport.h>
28421 +#include <linux/delay.h>
28422 +#include <linux/init.h>
28423 +#include <linux/initrd.h>
28424 +#include <linux/highmem.h>
28425 +#include <linux/bootmem.h>
28426 +#include <linux/module.h>
28427 +#include <asm/processor.h>
28428 +#include <linux/console.h>
28429 +#include <linux/seq_file.h>
28430 +#include <linux/crash_dump.h>
28431 +#include <linux/root_dev.h>
28432 +#include <linux/pci.h>
28433 +#include <linux/acpi.h>
28434 +#include <linux/kallsyms.h>
28435 +#include <linux/edd.h>
28436 +#include <linux/mmzone.h>
28437 +#include <linux/kexec.h>
28438 +#include <linux/cpufreq.h>
28439 +#include <linux/dmi.h>
28440 +#include <linux/dma-mapping.h>
28441 +#include <linux/ctype.h>
28443 +#include <asm/mtrr.h>
28444 +#include <asm/uaccess.h>
28445 +#include <asm/system.h>
28446 +#include <asm/io.h>
28447 +#include <asm/smp.h>
28448 +#include <asm/msr.h>
28449 +#include <asm/desc.h>
28450 +#include <video/edid.h>
28451 +#include <asm/e820.h>
28452 +#include <asm/dma.h>
28453 +#include <asm/mpspec.h>
28454 +#include <asm/mmu_context.h>
28455 +#include <asm/bootsetup.h>
28456 +#include <asm/proto.h>
28457 +#include <asm/setup.h>
28458 +#include <asm/mach_apic.h>
28459 +#include <asm/numa.h>
28460 +#include <asm/sections.h>
28461 +#include <asm/dmi.h>
28463 +#include <linux/percpu.h>
28464 +#include <xen/interface/physdev.h>
28465 +#include "setup_arch_pre.h"
28466 +#include <asm/hypervisor.h>
28467 +#include <xen/interface/nmi.h>
28468 +#include <xen/features.h>
28469 +#include <xen/firmware.h>
28470 +#include <xen/xencons.h>
28471 +#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
28472 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
28473 +#include <asm/mach-xen/setup_arch_post.h>
28474 +#include <xen/interface/memory.h>
28477 +#include <xen/interface/kexec.h>
28480 +extern unsigned long start_pfn;
28481 +extern struct edid_info edid_info;
28483 +shared_info_t *HYPERVISOR_shared_info = (shared_info_t *)empty_zero_page;
28484 +EXPORT_SYMBOL(HYPERVISOR_shared_info);
28486 +extern char hypercall_page[PAGE_SIZE];
28487 +EXPORT_SYMBOL(hypercall_page);
28489 +static int xen_panic_event(struct notifier_block *, unsigned long, void *);
28490 +static struct notifier_block xen_panic_block = {
28491 + xen_panic_event, NULL, 0 /* try to go last */
28494 +unsigned long *phys_to_machine_mapping;
28495 +unsigned long *pfn_to_mfn_frame_list_list, *pfn_to_mfn_frame_list[512];
28497 +EXPORT_SYMBOL(phys_to_machine_mapping);
28499 +DEFINE_PER_CPU(multicall_entry_t, multicall_list[8]);
28500 +DEFINE_PER_CPU(int, nr_multicall_ents);
28502 +/* Raw start-of-day parameters from the hypervisor. */
28503 +start_info_t *xen_start_info;
28504 +EXPORT_SYMBOL(xen_start_info);
28508 + * Machine setup..
28511 +struct cpuinfo_x86 boot_cpu_data __read_mostly;
28512 +EXPORT_SYMBOL(boot_cpu_data);
28514 +unsigned long mmu_cr4_features;
28516 +int acpi_disabled;
28517 +EXPORT_SYMBOL(acpi_disabled);
28518 +#ifdef CONFIG_ACPI
28519 +extern int __initdata acpi_ht;
28520 +extern acpi_interrupt_flags acpi_sci_flags;
28521 +int __initdata acpi_force = 0;
28524 +int acpi_numa __initdata;
28526 +/* Boot loader ID as an integer, for the benefit of proc_dointvec */
28527 +int bootloader_type;
28529 +unsigned long saved_video_mode;
28532 + * Early DMI memory
28534 +int dmi_alloc_index;
28535 +char dmi_alloc_data[DMI_MAX_DATA];
28540 +struct screen_info screen_info;
28541 +EXPORT_SYMBOL(screen_info);
28542 +struct sys_desc_table_struct {
28543 + unsigned short length;
28544 + unsigned char table[0];
28547 +struct edid_info edid_info;
28548 +EXPORT_SYMBOL_GPL(edid_info);
28549 +struct e820map e820;
28551 +struct e820map machine_e820;
28554 +extern int root_mountflags;
28556 +char command_line[COMMAND_LINE_SIZE];
28558 +struct resource standard_io_resources[] = {
28559 + { .name = "dma1", .start = 0x00, .end = 0x1f,
28560 + .flags = IORESOURCE_BUSY | IORESOURCE_IO },
28561 + { .name = "pic1", .start = 0x20, .end = 0x21,
28562 + .flags = IORESOURCE_BUSY | IORESOURCE_IO },
28563 + { .name = "timer0", .start = 0x40, .end = 0x43,
28564 + .flags = IORESOURCE_BUSY | IORESOURCE_IO },
28565 + { .name = "timer1", .start = 0x50, .end = 0x53,
28566 + .flags = IORESOURCE_BUSY | IORESOURCE_IO },
28567 + { .name = "keyboard", .start = 0x60, .end = 0x6f,
28568 + .flags = IORESOURCE_BUSY | IORESOURCE_IO },
28569 + { .name = "dma page reg", .start = 0x80, .end = 0x8f,
28570 + .flags = IORESOURCE_BUSY | IORESOURCE_IO },
28571 + { .name = "pic2", .start = 0xa0, .end = 0xa1,
28572 + .flags = IORESOURCE_BUSY | IORESOURCE_IO },
28573 + { .name = "dma2", .start = 0xc0, .end = 0xdf,
28574 + .flags = IORESOURCE_BUSY | IORESOURCE_IO },
28575 + { .name = "fpu", .start = 0xf0, .end = 0xff,
28576 + .flags = IORESOURCE_BUSY | IORESOURCE_IO }
28579 +#define STANDARD_IO_RESOURCES \
28580 + (sizeof standard_io_resources / sizeof standard_io_resources[0])
28582 +#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
28584 +struct resource data_resource = {
28585 + .name = "Kernel data",
28588 + .flags = IORESOURCE_RAM,
28590 +struct resource code_resource = {
28591 + .name = "Kernel code",
28594 + .flags = IORESOURCE_RAM,
28597 +#define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
28599 +static struct resource system_rom_resource = {
28600 + .name = "System ROM",
28601 + .start = 0xf0000,
28603 + .flags = IORESOURCE_ROM,
28606 +static struct resource extension_rom_resource = {
28607 + .name = "Extension ROM",
28608 + .start = 0xe0000,
28610 + .flags = IORESOURCE_ROM,
28613 +static struct resource adapter_rom_resources[] = {
28614 + { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
28615 + .flags = IORESOURCE_ROM },
28616 + { .name = "Adapter ROM", .start = 0, .end = 0,
28617 + .flags = IORESOURCE_ROM },
28618 + { .name = "Adapter ROM", .start = 0, .end = 0,
28619 + .flags = IORESOURCE_ROM },
28620 + { .name = "Adapter ROM", .start = 0, .end = 0,
28621 + .flags = IORESOURCE_ROM },
28622 + { .name = "Adapter ROM", .start = 0, .end = 0,
28623 + .flags = IORESOURCE_ROM },
28624 + { .name = "Adapter ROM", .start = 0, .end = 0,
28625 + .flags = IORESOURCE_ROM }
28628 +#define ADAPTER_ROM_RESOURCES \
28629 + (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
28631 +static struct resource video_rom_resource = {
28632 + .name = "Video ROM",
28633 + .start = 0xc0000,
28635 + .flags = IORESOURCE_ROM,
28638 +static struct resource video_ram_resource = {
28639 + .name = "Video RAM area",
28640 + .start = 0xa0000,
28642 + .flags = IORESOURCE_RAM,
28645 +#define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
28647 +static int __init romchecksum(unsigned char *rom, unsigned long length)
28649 + unsigned char *p, sum = 0;
28651 + for (p = rom; p < rom + length; p++)
28656 +static void __init probe_roms(void)
28658 + unsigned long start, length, upper;
28659 + unsigned char *rom;
28663 + /* Nothing to do if not running in dom0. */
28664 + if (!is_initial_xendomain())
28669 + upper = adapter_rom_resources[0].start;
28670 + for (start = video_rom_resource.start; start < upper; start += 2048) {
28671 + rom = isa_bus_to_virt(start);
28672 + if (!romsignature(rom))
28675 + video_rom_resource.start = start;
28677 + /* 0 < length <= 0x7f * 512, historically */
28678 + length = rom[2] * 512;
28680 + /* if checksum okay, trust length byte */
28681 + if (length && romchecksum(rom, length))
28682 + video_rom_resource.end = start + length - 1;
28684 + request_resource(&iomem_resource, &video_rom_resource);
28688 + start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
28689 + if (start < upper)
28693 + request_resource(&iomem_resource, &system_rom_resource);
28694 + upper = system_rom_resource.start;
28696 + /* check for extension rom (ignore length byte!) */
28697 + rom = isa_bus_to_virt(extension_rom_resource.start);
28698 + if (romsignature(rom)) {
28699 + length = extension_rom_resource.end - extension_rom_resource.start + 1;
28700 + if (romchecksum(rom, length)) {
28701 + request_resource(&iomem_resource, &extension_rom_resource);
28702 + upper = extension_rom_resource.start;
28706 + /* check for adapter roms on 2k boundaries */
28707 + for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
28708 + rom = isa_bus_to_virt(start);
28709 + if (!romsignature(rom))
28712 + /* 0 < length <= 0x7f * 512, historically */
28713 + length = rom[2] * 512;
28715 + /* but accept any length that fits if checksum okay */
28716 + if (!length || start + length > upper || !romchecksum(rom, length))
28719 + adapter_rom_resources[i].start = start;
28720 + adapter_rom_resources[i].end = start + length - 1;
28721 + request_resource(&iomem_resource, &adapter_rom_resources[i]);
28723 + start = adapter_rom_resources[i++].end & ~2047UL;
28727 +/* Check for full argument with no trailing characters */
28728 +static int fullarg(char *p, char *arg)
28730 + int l = strlen(arg);
28731 + return !memcmp(p, arg, l) && (p[l] == 0 || isspace(p[l]));
28734 +static __init void parse_cmdline_early (char ** cmdline_p)
28736 + char c = ' ', *to = command_line, *from = COMMAND_LINE;
28746 + * If the BIOS enumerates physical processors before logical,
28747 + * maxcpus=N at enumeration-time can be used to disable HT.
28749 + else if (!memcmp(from, "maxcpus=", 8)) {
28750 + extern unsigned int maxcpus;
28752 + maxcpus = simple_strtoul(from + 8, NULL, 0);
28755 +#ifdef CONFIG_ACPI
28756 + /* "acpi=off" disables both ACPI table parsing and interpreter init */
28757 + if (fullarg(from,"acpi=off"))
28760 + if (fullarg(from, "acpi=force")) {
28761 + /* add later when we do DMI horrors: */
28763 + acpi_disabled = 0;
28766 + /* acpi=ht just means: do ACPI MADT parsing
28767 + at bootup, but don't enable the full ACPI interpreter */
28768 + if (fullarg(from, "acpi=ht")) {
28773 + else if (fullarg(from, "pci=noacpi"))
28774 + acpi_disable_pci();
28775 + else if (fullarg(from, "acpi=noirq"))
28776 + acpi_noirq_set();
28778 + else if (fullarg(from, "acpi_sci=edge"))
28779 + acpi_sci_flags.trigger = 1;
28780 + else if (fullarg(from, "acpi_sci=level"))
28781 + acpi_sci_flags.trigger = 3;
28782 + else if (fullarg(from, "acpi_sci=high"))
28783 + acpi_sci_flags.polarity = 1;
28784 + else if (fullarg(from, "acpi_sci=low"))
28785 + acpi_sci_flags.polarity = 3;
28787 + /* acpi=strict disables out-of-spec workarounds */
28788 + else if (fullarg(from, "acpi=strict")) {
28791 +#ifdef CONFIG_X86_IO_APIC
28792 + else if (fullarg(from, "acpi_skip_timer_override"))
28793 + acpi_skip_timer_override = 1;
28797 +#ifndef CONFIG_XEN
28798 + if (fullarg(from, "nolapic") || fullarg(from, "disableapic")) {
28799 + clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
28800 + disable_apic = 1;
28803 + if (fullarg(from, "noapic"))
28804 + skip_ioapic_setup = 1;
28806 + if (fullarg(from,"apic")) {
28807 + skip_ioapic_setup = 0;
28808 + ioapic_force = 1;
28812 + if (!memcmp(from, "mem=", 4))
28813 + parse_memopt(from+4, &from);
28815 + if (!memcmp(from, "memmap=", 7)) {
28816 + /* exactmap option is for used defined memory */
28817 + if (!memcmp(from+7, "exactmap", 8)) {
28818 +#ifdef CONFIG_CRASH_DUMP
28819 + /* If we are doing a crash dump, we
28820 + * still need to know the real mem
28821 + * size before original memory map is
28824 + saved_max_pfn = e820_end_of_ram();
28832 + parse_memmapopt(from+7, &from);
28837 +#ifdef CONFIG_NUMA
28838 + if (!memcmp(from, "numa=", 5))
28839 + numa_setup(from+5);
28842 + if (!memcmp(from,"iommu=",6)) {
28843 + iommu_setup(from+6);
28846 + if (fullarg(from,"oops=panic"))
28847 + panic_on_oops = 1;
28849 + if (!memcmp(from, "noexec=", 7))
28850 + nonx_setup(from + 7);
28852 +#ifdef CONFIG_KEXEC
28853 + /* crashkernel=size@addr specifies the location to reserve for
28854 + * a crash kernel. By reserving this memory we guarantee
28855 + * that linux never set's it up as a DMA target.
28856 + * Useful for holding code to do something appropriate
28857 + * after a kernel panic.
28859 + else if (!memcmp(from, "crashkernel=", 12)) {
28860 +#ifndef CONFIG_XEN
28861 + unsigned long size, base;
28862 + size = memparse(from+12, &from);
28863 + if (*from == '@') {
28864 + base = memparse(from+1, &from);
28865 + /* FIXME: Do I want a sanity check
28866 + * to validate the memory range?
28868 + crashk_res.start = base;
28869 + crashk_res.end = base + size - 1;
28872 + printk("Ignoring crashkernel command line, "
28873 + "parameter will be supplied by xen\n");
28878 +#ifdef CONFIG_PROC_VMCORE
28879 + /* elfcorehdr= specifies the location of elf core header
28880 + * stored by the crashed kernel. This option will be passed
28881 + * by kexec loader to the capture kernel.
28883 + else if(!memcmp(from, "elfcorehdr=", 11))
28884 + elfcorehdr_addr = memparse(from+11, &from);
28887 +#if defined(CONFIG_HOTPLUG_CPU) && !defined(CONFIG_XEN)
28888 + else if (!memcmp(from, "additional_cpus=", 16))
28889 + setup_additional_cpus(from+16);
28896 + if (COMMAND_LINE_SIZE <= ++len)
28901 + printk(KERN_INFO "user-defined physical RAM map:\n");
28902 + e820_print_map("user");
28905 + *cmdline_p = command_line;
28908 +#ifndef CONFIG_NUMA
28909 +static void __init
28910 +contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
28912 + unsigned long bootmap_size, bootmap;
28914 + bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
28915 + bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
28916 + if (bootmap == -1L)
28917 + panic("Cannot find bootmem map of size %ld\n",bootmap_size);
28918 + bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
28920 + e820_bootmem_free(NODE_DATA(0), 0, xen_start_info->nr_pages<<PAGE_SHIFT);
28922 + e820_bootmem_free(NODE_DATA(0), 0, end_pfn << PAGE_SHIFT);
28924 + reserve_bootmem(bootmap, bootmap_size);
28928 +#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
28930 +#ifdef CONFIG_EDD_MODULE
28931 +EXPORT_SYMBOL(edd);
28933 +#ifndef CONFIG_XEN
28935 + * copy_edd() - Copy the BIOS EDD information
28936 + * from boot_params into a safe place.
28939 +static inline void copy_edd(void)
28941 + memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
28942 + memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
28943 + edd.mbr_signature_nr = EDD_MBR_SIG_NR;
28944 + edd.edd_info_nr = EDD_NR;
28948 +static inline void copy_edd(void)
28953 +#ifndef CONFIG_XEN
28954 +#define EBDA_ADDR_POINTER 0x40E
28956 +unsigned __initdata ebda_addr;
28957 +unsigned __initdata ebda_size;
28959 +static void discover_ebda(void)
28962 + * there is a real-mode segmented pointer pointing to the
28963 + * 4K EBDA area at 0x40E
28965 + ebda_addr = *(unsigned short *)EBDA_ADDR_POINTER;
28968 + ebda_size = *(unsigned short *)(unsigned long)ebda_addr;
28970 + /* Round EBDA up to pages */
28971 + if (ebda_size == 0)
28973 + ebda_size <<= 10;
28974 + ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
28975 + if (ebda_size > 64*1024)
28976 + ebda_size = 64*1024;
28979 +#define discover_ebda() ((void)0)
28982 +void __init setup_arch(char **cmdline_p)
28985 + /* Register a call for panic conditions. */
28986 + atomic_notifier_chain_register(&panic_notifier_list, &xen_panic_block);
28988 + ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
28989 + screen_info = SCREEN_INFO;
28991 + if (is_initial_xendomain()) {
28992 + const struct dom0_vga_console_info *info =
28993 + (void *)((char *)xen_start_info +
28994 + xen_start_info->console.dom0.info_off);
28996 + dom0_init_screen_info(info,
28997 + xen_start_info->console.dom0.info_size);
28998 + xen_start_info->console.domU.mfn = 0;
28999 + xen_start_info->console.domU.evtchn = 0;
29001 + screen_info.orig_video_isVGA = 0;
29005 + WARN_ON(HYPERVISOR_vm_assist(VMASST_CMD_enable,
29006 + VMASST_TYPE_writable_pagetables));
29010 + ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
29011 + screen_info = SCREEN_INFO;
29012 + edid_info = EDID_INFO;
29013 +#endif /* !CONFIG_XEN */
29014 + saved_video_mode = SAVED_VIDEO_MODE;
29015 + bootloader_type = LOADER_TYPE;
29017 +#ifdef CONFIG_BLK_DEV_RAM
29018 + rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
29019 + rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
29020 + rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
29022 + setup_memory_region();
29025 + if (!MOUNT_ROOT_RDONLY)
29026 + root_mountflags &= ~MS_RDONLY;
29027 + init_mm.start_code = (unsigned long) &_text;
29028 + init_mm.end_code = (unsigned long) &_etext;
29029 + init_mm.end_data = (unsigned long) &_edata;
29030 + init_mm.brk = (unsigned long) &_end;
29032 + code_resource.start = virt_to_phys(&_text);
29033 + code_resource.end = virt_to_phys(&_etext)-1;
29034 + data_resource.start = virt_to_phys(&_etext);
29035 + data_resource.end = virt_to_phys(&_edata)-1;
29037 + parse_cmdline_early(cmdline_p);
29039 + early_identify_cpu(&boot_cpu_data);
29042 + * partially used pages are not usable - thus
29043 + * we are rounding upwards:
29045 + end_pfn = e820_end_of_ram();
29046 + num_physpages = end_pfn; /* for pfn_valid */
29052 + init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
29054 + if (is_initial_xendomain())
29055 + dmi_scan_machine();
29057 +#ifdef CONFIG_ACPI_NUMA
29059 + * Parse SRAT to discover nodes.
29061 + acpi_numa_init();
29064 +#ifdef CONFIG_NUMA
29065 + numa_initmem_init(0, end_pfn);
29067 + contig_initmem_init(0, end_pfn);
29072 + * Reserve kernel, physmap, start info, initial page tables, and
29073 + * direct mapping.
29075 + reserve_bootmem_generic(__pa_symbol(&_text),
29076 + (table_end << PAGE_SHIFT) - __pa_symbol(&_text));
29078 + /* Reserve direct mapping */
29079 + reserve_bootmem_generic(table_start << PAGE_SHIFT,
29080 + (table_end - table_start) << PAGE_SHIFT);
29082 + /* reserve kernel */
29083 + reserve_bootmem_generic(__pa_symbol(&_text),
29084 + __pa_symbol(&_end) - __pa_symbol(&_text));
29087 + * reserve physical page 0 - it's a special BIOS page on many boxes,
29088 + * enabling clean reboots, SMP operation, laptop functions.
29090 + reserve_bootmem_generic(0, PAGE_SIZE);
29092 + /* reserve ebda region */
29094 + reserve_bootmem_generic(ebda_addr, ebda_size);
29098 + * But first pinch a few for the stack/trampoline stuff
29099 + * FIXME: Don't need the extra page at 4K, but need to fix
29100 + * trampoline before removing it. (see the GDT stuff)
29102 + reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
29104 + /* Reserve SMP trampoline */
29105 + reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
29109 +#ifdef CONFIG_ACPI_SLEEP
29111 + * Reserve low memory region for sleep support.
29113 + acpi_reserve_bootmem();
29116 +#ifdef CONFIG_BLK_DEV_INITRD
29117 + if (xen_start_info->mod_start) {
29118 + if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
29119 + /*reserve_bootmem_generic(INITRD_START, INITRD_SIZE);*/
29120 + initrd_start = INITRD_START + PAGE_OFFSET;
29121 + initrd_end = initrd_start+INITRD_SIZE;
29122 + initrd_below_start_ok = 1;
29124 + printk(KERN_ERR "initrd extends beyond end of memory "
29125 + "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
29126 + (unsigned long)(INITRD_START + INITRD_SIZE),
29127 + (unsigned long)(end_pfn << PAGE_SHIFT));
29128 + initrd_start = 0;
29132 +#else /* CONFIG_XEN */
29133 +#ifdef CONFIG_BLK_DEV_INITRD
29134 + if (LOADER_TYPE && INITRD_START) {
29135 + if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
29136 + reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
29138 + INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
29139 + initrd_end = initrd_start+INITRD_SIZE;
29142 + printk(KERN_ERR "initrd extends beyond end of memory "
29143 + "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
29144 + (unsigned long)(INITRD_START + INITRD_SIZE),
29145 + (unsigned long)(end_pfn << PAGE_SHIFT));
29146 + initrd_start = 0;
29150 +#endif /* !CONFIG_XEN */
29151 +#ifdef CONFIG_KEXEC
29153 + xen_machine_kexec_setup_resources();
29155 + if (crashk_res.start != crashk_res.end) {
29156 + reserve_bootmem_generic(crashk_res.start,
29157 + crashk_res.end - crashk_res.start + 1);
29163 +#ifdef CONFIG_X86_LOCAL_APIC
29165 + * Find and reserve possible boot-time SMP configuration:
29167 + find_smp_config();
29171 + int i, j, k, fpp;
29172 + unsigned long p2m_pages;
29174 + p2m_pages = end_pfn;
29175 + if (xen_start_info->nr_pages > end_pfn) {
29177 + * the end_pfn was shrunk (probably by mem= or highmem=
29178 + * kernel parameter); shrink reservation with the HV
29180 + struct xen_memory_reservation reservation = {
29181 + .address_bits = 0,
29182 + .extent_order = 0,
29183 + .domid = DOMID_SELF
29185 + unsigned int difference;
29188 + difference = xen_start_info->nr_pages - end_pfn;
29190 + set_xen_guest_handle(reservation.extent_start,
29191 + ((unsigned long *)xen_start_info->mfn_list) + end_pfn);
29192 + reservation.nr_extents = difference;
29193 + ret = HYPERVISOR_memory_op(XENMEM_decrease_reservation,
29195 + BUG_ON (ret != difference);
29197 + else if (end_pfn > xen_start_info->nr_pages)
29198 + p2m_pages = xen_start_info->nr_pages;
29200 + if (!xen_feature(XENFEAT_auto_translated_physmap)) {
29201 + /* Make sure we have a large enough P->M table. */
29202 + phys_to_machine_mapping = alloc_bootmem_pages(
29203 + end_pfn * sizeof(unsigned long));
29204 + memset(phys_to_machine_mapping, ~0,
29205 + end_pfn * sizeof(unsigned long));
29206 + memcpy(phys_to_machine_mapping,
29207 + (unsigned long *)xen_start_info->mfn_list,
29208 + p2m_pages * sizeof(unsigned long));
29210 + __pa(xen_start_info->mfn_list),
29211 + PFN_PHYS(PFN_UP(xen_start_info->nr_pages *
29212 + sizeof(unsigned long))));
29215 + * Initialise the list of the frames that specify the
29216 + * list of frames that make up the p2m table. Used by
29219 + pfn_to_mfn_frame_list_list = alloc_bootmem_pages(PAGE_SIZE);
29221 + fpp = PAGE_SIZE/sizeof(unsigned long);
29222 + for (i=0, j=0, k=-1; i< end_pfn; i+=fpp, j++) {
29223 + if ((j % fpp) == 0) {
29226 + pfn_to_mfn_frame_list[k] =
29227 + alloc_bootmem_pages(PAGE_SIZE);
29228 + pfn_to_mfn_frame_list_list[k] =
29229 + virt_to_mfn(pfn_to_mfn_frame_list[k]);
29232 + pfn_to_mfn_frame_list[k][j] =
29233 + virt_to_mfn(&phys_to_machine_mapping[i]);
29235 + HYPERVISOR_shared_info->arch.max_pfn = end_pfn;
29236 + HYPERVISOR_shared_info->arch.pfn_to_mfn_frame_list_list =
29237 + virt_to_mfn(pfn_to_mfn_frame_list_list);
29240 + /* Mark all ISA DMA channels in-use - using them wouldn't work. */
29241 + for (i = 0; i < MAX_DMA_CHANNELS; ++i)
29242 + if (i != 4 && request_dma(i, "xen") != 0)
29246 + if (!is_initial_xendomain()) {
29247 + acpi_disabled = 1;
29248 +#ifdef CONFIG_ACPI
29254 +#ifndef CONFIG_XEN
29258 + zap_low_mappings(0);
29261 + * set this early, so we dont allocate cpu0
29262 + * if MADT list doesnt list BSP first
29263 + * mpparse.c/MP_processor_info() allocates logical cpu numbers.
29265 + cpu_set(0, cpu_present_map);
29266 +#ifdef CONFIG_ACPI
29268 + * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
29269 + * Call this early for SRAT node setup.
29271 + acpi_boot_table_init();
29274 + * Read APIC and some other early information from ACPI tables.
29276 + acpi_boot_init();
29279 + init_cpu_to_node();
29281 +#ifdef CONFIG_X86_LOCAL_APIC
29283 + * get boot-time SMP configuration:
29285 + if (smp_found_config)
29286 + get_smp_config();
29287 +#ifndef CONFIG_XEN
29288 + init_apic_mappings();
29291 +#if defined(CONFIG_XEN) && defined(CONFIG_SMP) && !defined(CONFIG_HOTPLUG_CPU)
29292 + prefill_possible_map();
29296 + * Request address space for all standard RAM and ROM resources
29297 + * and also for regions reported as reserved by the e820.
29301 + if (is_initial_xendomain())
29302 + e820_reserve_resources(machine_e820.map, machine_e820.nr_map);
29304 + e820_reserve_resources(e820.map, e820.nr_map);
29307 + request_resource(&iomem_resource, &video_ram_resource);
29311 + /* request I/O space for devices used on all i[345]86 PCs */
29312 + for (i = 0; i < STANDARD_IO_RESOURCES; i++)
29313 + request_resource(&ioport_resource, &standard_io_resources[i]);
29317 + if (is_initial_xendomain())
29318 + e820_setup_gap(machine_e820.map, machine_e820.nr_map);
29320 + e820_setup_gap(e820.map, e820.nr_map);
29325 + struct physdev_set_iopl set_iopl;
29327 + set_iopl.iopl = 1;
29328 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl));
29330 + if (is_initial_xendomain()) {
29332 +#if defined(CONFIG_VGA_CONSOLE)
29333 + conswitchp = &vga_con;
29334 +#elif defined(CONFIG_DUMMY_CONSOLE)
29335 + conswitchp = &dummy_con;
29339 +#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
29340 + conswitchp = &dummy_con;
29344 +#else /* CONFIG_XEN */
29347 +#if defined(CONFIG_VGA_CONSOLE)
29348 + conswitchp = &vga_con;
29349 +#elif defined(CONFIG_DUMMY_CONSOLE)
29350 + conswitchp = &dummy_con;
29354 +#endif /* !CONFIG_XEN */
29359 +xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
29361 + HYPERVISOR_shutdown(SHUTDOWN_crash);
29362 + /* we're never actually going to get here... */
29363 + return NOTIFY_DONE;
29365 +#endif /* !CONFIG_XEN */
29368 +static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
29372 + if (c->extended_cpuid_level < 0x80000004)
29375 + v = (unsigned int *) c->x86_model_id;
29376 + cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
29377 + cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
29378 + cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
29379 + c->x86_model_id[48] = 0;
29384 +static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
29386 + unsigned int n, dummy, eax, ebx, ecx, edx;
29388 + n = c->extended_cpuid_level;
29390 + if (n >= 0x80000005) {
29391 + cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
29392 + printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
29393 + edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
29394 + c->x86_cache_size=(ecx>>24)+(edx>>24);
29395 + /* On K8 L1 TLB is inclusive, so don't count it */
29396 + c->x86_tlbsize = 0;
29399 + if (n >= 0x80000006) {
29400 + cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
29401 + ecx = cpuid_ecx(0x80000006);
29402 + c->x86_cache_size = ecx >> 16;
29403 + c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
29405 + printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
29406 + c->x86_cache_size, ecx & 0xFF);
29409 + if (n >= 0x80000007)
29410 + cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
29411 + if (n >= 0x80000008) {
29412 + cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
29413 + c->x86_virt_bits = (eax >> 8) & 0xff;
29414 + c->x86_phys_bits = eax & 0xff;
29418 +#ifdef CONFIG_NUMA
29419 +static int nearby_node(int apicid)
29422 + for (i = apicid - 1; i >= 0; i--) {
29423 + int node = apicid_to_node[i];
29424 + if (node != NUMA_NO_NODE && node_online(node))
29427 + for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
29428 + int node = apicid_to_node[i];
29429 + if (node != NUMA_NO_NODE && node_online(node))
29432 + return first_node(node_online_map); /* Shouldn't happen */
29437 + * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
29438 + * Assumes number of cores is a power of two.
29440 +static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
29444 +#ifdef CONFIG_NUMA
29445 + int cpu = smp_processor_id();
29447 + unsigned apicid = hard_smp_processor_id();
29449 + unsigned ecx = cpuid_ecx(0x80000008);
29451 + c->x86_max_cores = (ecx & 0xff) + 1;
29453 + /* CPU telling us the core id bits shift? */
29454 + bits = (ecx >> 12) & 0xF;
29456 + /* Otherwise recompute */
29458 + while ((1 << bits) < c->x86_max_cores)
29462 + /* Low order bits define the core id (index of core in socket) */
29463 + c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
29464 + /* Convert the APIC ID into the socket ID */
29465 + c->phys_proc_id = phys_pkg_id(bits);
29467 +#ifdef CONFIG_NUMA
29468 + node = c->phys_proc_id;
29469 + if (apicid_to_node[apicid] != NUMA_NO_NODE)
29470 + node = apicid_to_node[apicid];
29471 + if (!node_online(node)) {
29472 + /* Two possibilities here:
29473 + - The CPU is missing memory and no node was created.
29474 + In that case try picking one from a nearby CPU
29475 + - The APIC IDs differ from the HyperTransport node IDs
29476 + which the K8 northbridge parsing fills in.
29477 + Assume they are all increased by a constant offset,
29478 + but in the same order as the HT nodeids.
29479 + If that doesn't result in a usable node fall back to the
29480 + path for the previous case. */
29481 + int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
29482 + if (ht_nodeid >= 0 &&
29483 + apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
29484 + node = apicid_to_node[ht_nodeid];
29485 + /* Pick a nearby node */
29486 + if (!node_online(node))
29487 + node = nearby_node(apicid);
29489 + numa_set_node(cpu, node);
29491 + printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
29496 +static void __init init_amd(struct cpuinfo_x86 *c)
29501 + unsigned long value;
29504 + * Disable TLB flush filter by setting HWCR.FFDIS on K8
29505 + * bit 6 of msr C001_0015
29507 + * Errata 63 for SH-B3 steppings
29508 + * Errata 122 for all steppings (F+ have it disabled by default)
29510 + if (c->x86 == 15) {
29511 + rdmsrl(MSR_K8_HWCR, value);
29513 + wrmsrl(MSR_K8_HWCR, value);
29517 + /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
29518 + 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
29519 + clear_bit(0*32+31, &c->x86_capability);
29521 + /* On C+ stepping K8 rep microcode works well for copy/memset */
29522 + level = cpuid_eax(1);
29523 + if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
29524 + set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
29526 + /* Enable workaround for FXSAVE leak */
29528 + set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
29530 + level = get_model_name(c);
29532 + switch (c->x86) {
29534 + /* Should distinguish Models here, but this is only
29535 + a fallback anyways. */
29536 + strcpy(c->x86_model_id, "Hammer");
29540 + display_cacheinfo(c);
29542 + /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
29543 + if (c->x86_power & (1<<8))
29544 + set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
29546 + /* Multi core CPU? */
29547 + if (c->extended_cpuid_level >= 0x80000008)
29548 + amd_detect_cmp(c);
29550 + /* Fix cpuid4 emulation for more */
29551 + num_cache_leaves = 3;
29554 +static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
29557 + u32 eax, ebx, ecx, edx;
29558 + int index_msb, core_bits;
29560 + cpuid(1, &eax, &ebx, &ecx, &edx);
29563 + if (!cpu_has(c, X86_FEATURE_HT))
29565 + if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
29568 + smp_num_siblings = (ebx & 0xff0000) >> 16;
29570 + if (smp_num_siblings == 1) {
29571 + printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
29572 + } else if (smp_num_siblings > 1 ) {
29574 + if (smp_num_siblings > NR_CPUS) {
29575 + printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
29576 + smp_num_siblings = 1;
29580 + index_msb = get_count_order(smp_num_siblings);
29581 + c->phys_proc_id = phys_pkg_id(index_msb);
29583 + smp_num_siblings = smp_num_siblings / c->x86_max_cores;
29585 + index_msb = get_count_order(smp_num_siblings) ;
29587 + core_bits = get_count_order(c->x86_max_cores);
29589 + c->cpu_core_id = phys_pkg_id(index_msb) &
29590 + ((1 << core_bits) - 1);
29593 + if ((c->x86_max_cores * smp_num_siblings) > 1) {
29594 + printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
29595 + printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
29602 + * find out the number of processor cores on the die
29604 +static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
29606 + unsigned int eax, t;
29608 + if (c->cpuid_level < 4)
29611 + cpuid_count(4, 0, &eax, &t, &t, &t);
29614 + return ((eax >> 26) + 1);
29619 +static void srat_detect_node(void)
29621 +#ifdef CONFIG_NUMA
29623 + int cpu = smp_processor_id();
29624 + int apicid = hard_smp_processor_id();
29626 + /* Don't do the funky fallback heuristics the AMD version employs
29628 + node = apicid_to_node[apicid];
29629 + if (node == NUMA_NO_NODE)
29630 + node = first_node(node_online_map);
29631 + numa_set_node(cpu, node);
29633 + if (acpi_numa > 0)
29634 + printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
29638 +static void __cpuinit init_intel(struct cpuinfo_x86 *c)
29640 + /* Cache sizes */
29643 + init_intel_cacheinfo(c);
29644 + if (c->cpuid_level > 9 ) {
29645 + unsigned eax = cpuid_eax(10);
29646 + /* Check for version and the number of counters */
29647 + if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
29648 + set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
29651 + n = c->extended_cpuid_level;
29652 + if (n >= 0x80000008) {
29653 + unsigned eax = cpuid_eax(0x80000008);
29654 + c->x86_virt_bits = (eax >> 8) & 0xff;
29655 + c->x86_phys_bits = eax & 0xff;
29656 + /* CPUID workaround for Intel 0F34 CPU */
29657 + if (c->x86_vendor == X86_VENDOR_INTEL &&
29658 + c->x86 == 0xF && c->x86_model == 0x3 &&
29659 + c->x86_mask == 0x4)
29660 + c->x86_phys_bits = 36;
29663 + if (c->x86 == 15)
29664 + c->x86_cache_alignment = c->x86_clflush_size * 2;
29665 + if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
29666 + (c->x86 == 0x6 && c->x86_model >= 0x0e))
29667 + set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
29668 + set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
29669 + c->x86_max_cores = intel_num_cpu_cores(c);
29671 + srat_detect_node();
29674 +static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
29676 + char *v = c->x86_vendor_id;
29678 + if (!strcmp(v, "AuthenticAMD"))
29679 + c->x86_vendor = X86_VENDOR_AMD;
29680 + else if (!strcmp(v, "GenuineIntel"))
29681 + c->x86_vendor = X86_VENDOR_INTEL;
29683 + c->x86_vendor = X86_VENDOR_UNKNOWN;
29686 +struct cpu_model_info {
29689 + char *model_names[16];
29692 +/* Do some early cpuid on the boot CPU to get some parameter that are
29693 + needed before check_bugs. Everything advanced is in identify_cpu
29695 +void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
29699 + c->loops_per_jiffy = loops_per_jiffy;
29700 + c->x86_cache_size = -1;
29701 + c->x86_vendor = X86_VENDOR_UNKNOWN;
29702 + c->x86_model = c->x86_mask = 0; /* So far unknown... */
29703 + c->x86_vendor_id[0] = '\0'; /* Unset */
29704 + c->x86_model_id[0] = '\0'; /* Unset */
29705 + c->x86_clflush_size = 64;
29706 + c->x86_cache_alignment = c->x86_clflush_size;
29707 + c->x86_max_cores = 1;
29708 + c->extended_cpuid_level = 0;
29709 + memset(&c->x86_capability, 0, sizeof c->x86_capability);
29711 + /* Get vendor name */
29712 + cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
29713 + (unsigned int *)&c->x86_vendor_id[0],
29714 + (unsigned int *)&c->x86_vendor_id[8],
29715 + (unsigned int *)&c->x86_vendor_id[4]);
29717 + get_cpu_vendor(c);
29719 + /* Initialize the standard set of capabilities */
29720 + /* Note that the vendor-specific code below might override */
29722 + /* Intel-defined flags: level 0x00000001 */
29723 + if (c->cpuid_level >= 0x00000001) {
29725 + cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
29726 + &c->x86_capability[0]);
29727 + c->x86 = (tfms >> 8) & 0xf;
29728 + c->x86_model = (tfms >> 4) & 0xf;
29729 + c->x86_mask = tfms & 0xf;
29730 + if (c->x86 == 0xf)
29731 + c->x86 += (tfms >> 20) & 0xff;
29732 + if (c->x86 >= 0x6)
29733 + c->x86_model += ((tfms >> 16) & 0xF) << 4;
29734 + if (c->x86_capability[0] & (1<<19))
29735 + c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
29737 + /* Have CPUID level 0 only - unheard of */
29742 + c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
29747 + * This does the hard work of actually picking apart the CPU stuff...
29749 +void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
29754 + early_identify_cpu(c);
29756 + /* AMD-defined flags: level 0x80000001 */
29757 + xlvl = cpuid_eax(0x80000000);
29758 + c->extended_cpuid_level = xlvl;
29759 + if ((xlvl & 0xffff0000) == 0x80000000) {
29760 + if (xlvl >= 0x80000001) {
29761 + c->x86_capability[1] = cpuid_edx(0x80000001);
29762 + c->x86_capability[6] = cpuid_ecx(0x80000001);
29764 + if (xlvl >= 0x80000004)
29765 + get_model_name(c); /* Default name */
29768 + /* Transmeta-defined flags: level 0x80860001 */
29769 + xlvl = cpuid_eax(0x80860000);
29770 + if ((xlvl & 0xffff0000) == 0x80860000) {
29771 + /* Don't set x86_cpuid_level here for now to not confuse. */
29772 + if (xlvl >= 0x80860001)
29773 + c->x86_capability[2] = cpuid_edx(0x80860001);
29776 + c->apicid = phys_pkg_id(0);
29779 + * Vendor-specific initialization. In this section we
29780 + * canonicalize the feature flags, meaning if there are
29781 + * features a certain CPU supports which CPUID doesn't
29782 + * tell us, CPUID claiming incorrect flags, or other bugs,
29783 + * we handle them here.
29785 + * At the end of this section, c->x86_capability better
29786 + * indicate the features this CPU genuinely supports!
29788 + switch (c->x86_vendor) {
29789 + case X86_VENDOR_AMD:
29793 + case X86_VENDOR_INTEL:
29797 + case X86_VENDOR_UNKNOWN:
29799 + display_cacheinfo(c);
29803 + select_idle_routine(c);
29807 + * On SMP, boot_cpu_data holds the common feature set between
29808 + * all CPUs; so make sure that we indicate which features are
29809 + * common between the CPUs. The first time this routine gets
29810 + * executed, c == &boot_cpu_data.
29812 + if (c != &boot_cpu_data) {
29813 + /* AND the already accumulated flags with these */
29814 + for (i = 0 ; i < NCAPINTS ; i++)
29815 + boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
29818 +#ifdef CONFIG_X86_MCE
29821 + if (c == &boot_cpu_data)
29825 +#ifdef CONFIG_NUMA
29826 + numa_add_cpu(smp_processor_id());
29831 +void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
29833 + if (c->x86_model_id[0])
29834 + printk("%s", c->x86_model_id);
29836 + if (c->x86_mask || c->cpuid_level >= 0)
29837 + printk(" stepping %02x\n", c->x86_mask);
29843 + * Get CPU information for use by the procfs.
29846 +static int show_cpuinfo(struct seq_file *m, void *v)
29848 + struct cpuinfo_x86 *c = v;
29851 + * These flag bits must match the definitions in <asm/cpufeature.h>.
29852 + * NULL means this bit is undefined or reserved; either way it doesn't
29853 + * have meaning as far as Linux is concerned. Note that it's important
29854 + * to realize there is a difference between this table and CPUID -- if
29855 + * applications want to get the raw CPUID data, they should access
29856 + * /dev/cpu/<cpu_nr>/cpuid instead.
29858 + static char *x86_cap_flags[] = {
29859 + /* Intel-defined */
29860 + "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
29861 + "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
29862 + "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
29863 + "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
29865 + /* AMD-defined */
29866 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29867 + NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
29868 + NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
29869 + NULL, "fxsr_opt", NULL, "rdtscp", NULL, "lm", "3dnowext", "3dnow",
29871 + /* Transmeta-defined */
29872 + "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
29873 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29874 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29875 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29877 + /* Other (Linux-defined) */
29878 + "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
29879 + "constant_tsc", NULL, NULL,
29880 + "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29881 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29882 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29884 + /* Intel-defined (#2) */
29885 + "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
29886 + "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
29887 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29888 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29890 + /* VIA/Cyrix/Centaur-defined */
29891 + NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
29892 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29893 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29894 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29896 + /* AMD-defined (#2) */
29897 + "lahf_lm", "cmp_legacy", "svm", NULL, "cr8_legacy", NULL, NULL, NULL,
29898 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29899 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29900 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29902 + static char *x86_power_flags[] = {
29903 + "ts", /* temperature sensor */
29904 + "fid", /* frequency id control */
29905 + "vid", /* voltage id control */
29906 + "ttp", /* thermal trip */
29910 + /* nothing */ /* constant_tsc - moved to flags */
29915 + if (!cpu_online(c-cpu_data))
29919 + seq_printf(m,"processor\t: %u\n"
29920 + "vendor_id\t: %s\n"
29921 + "cpu family\t: %d\n"
29922 + "model\t\t: %d\n"
29923 + "model name\t: %s\n",
29924 + (unsigned)(c-cpu_data),
29925 + c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
29927 + (int)c->x86_model,
29928 + c->x86_model_id[0] ? c->x86_model_id : "unknown");
29930 + if (c->x86_mask || c->cpuid_level >= 0)
29931 + seq_printf(m, "stepping\t: %d\n", c->x86_mask);
29933 + seq_printf(m, "stepping\t: unknown\n");
29935 + if (cpu_has(c,X86_FEATURE_TSC)) {
29936 + unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
29939 + seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
29940 + freq / 1000, (freq % 1000));
29944 + if (c->x86_cache_size >= 0)
29945 + seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
29948 + if (smp_num_siblings * c->x86_max_cores > 1) {
29949 + int cpu = c - cpu_data;
29950 + seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
29951 + seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
29952 + seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
29953 + seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
29959 + "fpu_exception\t: yes\n"
29960 + "cpuid level\t: %d\n"
29967 + for ( i = 0 ; i < 32*NCAPINTS ; i++ )
29968 + if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
29969 + seq_printf(m, " %s", x86_cap_flags[i]);
29972 + seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
29973 + c->loops_per_jiffy/(500000/HZ),
29974 + (c->loops_per_jiffy/(5000/HZ)) % 100);
29976 + if (c->x86_tlbsize > 0)
29977 + seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
29978 + seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
29979 + seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
29981 + seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
29982 + c->x86_phys_bits, c->x86_virt_bits);
29984 + seq_printf(m, "power management:");
29987 + for (i = 0; i < 32; i++)
29988 + if (c->x86_power & (1 << i)) {
29989 + if (i < ARRAY_SIZE(x86_power_flags) &&
29990 + x86_power_flags[i])
29991 + seq_printf(m, "%s%s",
29992 + x86_power_flags[i][0]?" ":"",
29993 + x86_power_flags[i]);
29995 + seq_printf(m, " [%d]", i);
29999 + seq_printf(m, "\n\n");
30004 +static void *c_start(struct seq_file *m, loff_t *pos)
30006 + return *pos < NR_CPUS ? cpu_data + *pos : NULL;
30009 +static void *c_next(struct seq_file *m, void *v, loff_t *pos)
30012 + return c_start(m, pos);
30015 +static void c_stop(struct seq_file *m, void *v)
30019 +struct seq_operations cpuinfo_op = {
30023 + .show = show_cpuinfo,
30026 +#if defined(CONFIG_INPUT_PCSPKR) || defined(CONFIG_INPUT_PCSPKR_MODULE)
30027 +#include <linux/platform_device.h>
30028 +static __init int add_pcspkr(void)
30030 + struct platform_device *pd;
30033 + if (!is_initial_xendomain())
30036 + pd = platform_device_alloc("pcspkr", -1);
30040 + ret = platform_device_add(pd);
30042 + platform_device_put(pd);
30046 +device_initcall(add_pcspkr);
30048 Index: head-2008-11-25/arch/x86/kernel/setup64-xen.c
30049 ===================================================================
30050 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
30051 +++ head-2008-11-25/arch/x86/kernel/setup64-xen.c 2008-01-28 12:24:19.000000000 +0100
30054 + * X86-64 specific CPU setup.
30055 + * Copyright (C) 1995 Linus Torvalds
30056 + * Copyright 2001, 2002, 2003 SuSE Labs / Andi Kleen.
30057 + * See setup.c for older changelog.
30059 + * Jun Nakajima <jun.nakajima@intel.com>
30060 + * Modified for Xen
30063 +#include <linux/init.h>
30064 +#include <linux/kernel.h>
30065 +#include <linux/sched.h>
30066 +#include <linux/string.h>
30067 +#include <linux/bootmem.h>
30068 +#include <linux/bitops.h>
30069 +#include <linux/module.h>
30070 +#include <asm/bootsetup.h>
30071 +#include <asm/pda.h>
30072 +#include <asm/pgtable.h>
30073 +#include <asm/processor.h>
30074 +#include <asm/desc.h>
30075 +#include <asm/atomic.h>
30076 +#include <asm/mmu_context.h>
30077 +#include <asm/smp.h>
30078 +#include <asm/i387.h>
30079 +#include <asm/percpu.h>
30080 +#include <asm/proto.h>
30081 +#include <asm/sections.h>
30083 +#include <asm/hypervisor.h>
30086 +char x86_boot_params[BOOT_PARAM_SIZE] __initdata = {0,};
30088 +cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
30090 +struct x8664_pda *_cpu_pda[NR_CPUS] __read_mostly;
30091 +EXPORT_SYMBOL(_cpu_pda);
30092 +struct x8664_pda boot_cpu_pda[NR_CPUS] __cacheline_aligned;
30094 +#ifndef CONFIG_X86_NO_IDT
30095 +struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
30098 +char boot_cpu_stack[IRQSTACKSIZE] __attribute__((section(".bss.page_aligned")));
30100 +unsigned long __supported_pte_mask __read_mostly = ~0UL;
30101 +EXPORT_SYMBOL(__supported_pte_mask);
30102 +static int do_not_nx __cpuinitdata = 0;
30105 +Control non executable mappings for 64bit processes.
30107 +on Enable(default)
30110 +int __init nonx_setup(char *str)
30112 + if (!strncmp(str, "on", 2)) {
30113 + __supported_pte_mask |= _PAGE_NX;
30115 + } else if (!strncmp(str, "off", 3)) {
30117 + __supported_pte_mask &= ~_PAGE_NX;
30121 +__setup("noexec=", nonx_setup); /* parsed early actually */
30123 +int force_personality32 = 0;
30125 +/* noexec32=on|off
30126 +Control non executable heap for 32bit processes.
30127 +To control the stack too use noexec=off
30129 +on PROT_READ does not imply PROT_EXEC for 32bit processes
30130 +off PROT_READ implies PROT_EXEC (default)
30132 +static int __init nonx32_setup(char *str)
30134 + if (!strcmp(str, "on"))
30135 + force_personality32 &= ~READ_IMPLIES_EXEC;
30136 + else if (!strcmp(str, "off"))
30137 + force_personality32 |= READ_IMPLIES_EXEC;
30140 +__setup("noexec32=", nonx32_setup);
30143 + * Great future plan:
30144 + * Declare PDA itself and support (irqstack,tss,pgd) as per cpu data.
30145 + * Always point %gs to its beginning
30147 +void __init setup_per_cpu_areas(void)
30150 + unsigned long size;
30152 +#ifdef CONFIG_HOTPLUG_CPU
30153 + prefill_possible_map();
30156 + /* Copy section for each CPU (we discard the original) */
30157 + size = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
30158 +#ifdef CONFIG_MODULES
30159 + if (size < PERCPU_ENOUGH_ROOM)
30160 + size = PERCPU_ENOUGH_ROOM;
30163 + for_each_cpu_mask (i, cpu_possible_map) {
30166 + if (!NODE_DATA(cpu_to_node(i))) {
30167 + printk("cpu with no node %d, num_online_nodes %d\n",
30168 + i, num_online_nodes());
30169 + ptr = alloc_bootmem(size);
30171 + ptr = alloc_bootmem_node(NODE_DATA(cpu_to_node(i)), size);
30174 + panic("Cannot allocate cpu data for CPU %d\n", i);
30175 + cpu_pda(i)->data_offset = ptr - __per_cpu_start;
30176 + memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
30181 +static void switch_pt(void)
30183 + xen_pt_switch(__pa_symbol(init_level4_pgt));
30184 + xen_new_user_pt(__pa_symbol(__user_pgd(init_level4_pgt)));
30187 +static void __cpuinit cpu_gdt_init(const struct desc_ptr *gdt_descr)
30189 + unsigned long frames[16];
30190 + unsigned long va;
30193 + for (va = gdt_descr->address, f = 0;
30194 + va < gdt_descr->address + gdt_descr->size;
30195 + va += PAGE_SIZE, f++) {
30196 + frames[f] = virt_to_mfn(va);
30197 + make_page_readonly(
30198 + (void *)va, XENFEAT_writable_descriptor_tables);
30200 + if (HYPERVISOR_set_gdt(frames, (gdt_descr->size + 1) /
30201 + sizeof (struct desc_struct)))
30205 +static void switch_pt(void)
30207 + asm volatile("movq %0,%%cr3" :: "r" (__pa_symbol(&init_level4_pgt)));
30210 +static void __cpuinit cpu_gdt_init(const struct desc_ptr *gdt_descr)
30212 + asm volatile("lgdt %0" :: "m" (*gdt_descr));
30213 + asm volatile("lidt %0" :: "m" (idt_descr));
30217 +void pda_init(int cpu)
30219 + struct x8664_pda *pda = cpu_pda(cpu);
30221 + /* Setup up data that may be needed in __get_free_pages early */
30222 + asm volatile("movl %0,%%fs ; movl %0,%%gs" :: "r" (0));
30223 +#ifndef CONFIG_XEN
30224 + wrmsrl(MSR_GS_BASE, pda);
30226 + if (HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL,
30227 + (unsigned long)pda))
30230 + pda->cpunumber = cpu;
30231 + pda->irqcount = -1;
30232 + pda->kernelstack =
30233 + (unsigned long)stack_thread_info() - PDA_STACKOFFSET + THREAD_SIZE;
30234 + pda->active_mm = &init_mm;
30235 + pda->mmu_state = 0;
30241 + /* others are initialized in smpboot.c */
30242 + pda->pcurrent = &init_task;
30243 + pda->irqstackptr = boot_cpu_stack;
30245 + pda->irqstackptr = (char *)
30246 + __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
30247 + if (!pda->irqstackptr)
30248 + panic("cannot allocate irqstack for cpu %d", cpu);
30253 + pda->irqstackptr += IRQSTACKSIZE-64;
30256 +#ifndef CONFIG_X86_NO_TSS
30257 +char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]
30258 +__attribute__((section(".bss.page_aligned")));
30261 +/* May not be marked __init: used by software suspend */
30262 +void syscall_init(void)
30264 +#ifndef CONFIG_XEN
30266 + * LSTAR and STAR live in a bit strange symbiosis.
30267 + * They both write to the same internal register. STAR allows to set CS/DS
30268 + * but only a 32bit target. LSTAR sets the 64bit rip.
30270 + wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
30271 + wrmsrl(MSR_LSTAR, system_call);
30273 + /* Flags to clear on syscall */
30274 + wrmsrl(MSR_SYSCALL_MASK, EF_TF|EF_DF|EF_IE|0x3000);
30276 +#ifdef CONFIG_IA32_EMULATION
30277 + syscall32_cpu_init ();
30281 +void __cpuinit check_efer(void)
30283 + unsigned long efer;
30285 + rdmsrl(MSR_EFER, efer);
30286 + if (!(efer & EFER_NX) || do_not_nx) {
30287 + __supported_pte_mask &= ~_PAGE_NX;
30291 +unsigned long kernel_eflags;
30294 + * cpu_init() initializes state that is per-CPU. Some data is already
30295 + * initialized (naturally) in the bootstrap process, such as the GDT
30296 + * and IDT. We reload them nevertheless, this function acts as a
30297 + * 'CPU state barrier', nothing should get across.
30298 + * A lot of state is already set up in PDA init.
30300 +void __cpuinit cpu_init (void)
30302 + int cpu = stack_smp_processor_id();
30303 +#ifndef CONFIG_X86_NO_TSS
30304 + struct tss_struct *t = &per_cpu(init_tss, cpu);
30305 + struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
30307 + char *estacks = NULL;
30310 + struct task_struct *me;
30312 + /* CPU 0 is initialised in head64.c */
30315 + zap_low_mappings(cpu);
30317 +#ifndef CONFIG_X86_NO_TSS
30319 + estacks = boot_exception_stacks;
30324 + if (cpu_test_and_set(cpu, cpu_initialized))
30325 + panic("CPU#%d already initialized!\n", cpu);
30327 + printk("Initializing CPU#%d\n", cpu);
30329 + clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
30332 + * Initialize the per-CPU GDT with the boot GDT,
30333 + * and set up the GDT descriptor:
30335 +#ifndef CONFIG_XEN
30337 + memcpy(cpu_gdt(cpu), cpu_gdt_table, GDT_SIZE);
30340 + cpu_gdt_descr[cpu].size = GDT_SIZE;
30341 + cpu_gdt_init(&cpu_gdt_descr[cpu]);
30343 + memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
30346 + wrmsrl(MSR_FS_BASE, 0);
30347 + wrmsrl(MSR_KERNEL_GS_BASE, 0);
30352 +#ifndef CONFIG_X86_NO_TSS
30354 + * set up and load the per-CPU TSS
30356 + for (v = 0; v < N_EXCEPTION_STACKS; v++) {
30358 + static const unsigned int order[N_EXCEPTION_STACKS] = {
30359 + [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
30360 + [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
30363 + estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
30365 + panic("Cannot allocate exception stack %ld %d\n",
30369 +#if DEBUG_STKSZ > EXCEPTION_STKSZ
30370 + case DEBUG_STACK:
30371 + cpu_pda(cpu)->debugstack = (unsigned long)estacks;
30372 + estacks += DEBUG_STKSZ;
30376 + estacks += EXCEPTION_STKSZ;
30379 + orig_ist->ist[v] = t->ist[v] = (unsigned long)estacks;
30382 + t->io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
30384 + * <= is required because the CPU will access up to
30385 + * 8 bits beyond the end of the IO permission bitmap.
30387 + for (i = 0; i <= IO_BITMAP_LONGS; i++)
30388 + t->io_bitmap[i] = ~0UL;
30391 + atomic_inc(&init_mm.mm_count);
30392 + me->active_mm = &init_mm;
30395 + enter_lazy_tlb(&init_mm, me);
30397 +#ifndef CONFIG_X86_NO_TSS
30398 + set_tss_desc(cpu, t);
30400 +#ifndef CONFIG_XEN
30403 + load_LDT(&init_mm.context);
30406 + * Clear all 6 debug registers:
30409 + set_debugreg(0UL, 0);
30410 + set_debugreg(0UL, 1);
30411 + set_debugreg(0UL, 2);
30412 + set_debugreg(0UL, 3);
30413 + set_debugreg(0UL, 6);
30414 + set_debugreg(0UL, 7);
30418 + raw_local_save_flags(kernel_eflags);
30420 Index: head-2008-11-25/arch/x86/kernel/smp_64-xen.c
30421 ===================================================================
30422 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
30423 +++ head-2008-11-25/arch/x86/kernel/smp_64-xen.c 2008-04-02 12:34:02.000000000 +0200
30426 + * Intel SMP support routines.
30428 + * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
30429 + * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
30430 + * (c) 2002,2003 Andi Kleen, SuSE Labs.
30432 + * This code is released under the GNU General Public License version 2 or
30436 +#include <linux/init.h>
30438 +#include <linux/mm.h>
30439 +#include <linux/delay.h>
30440 +#include <linux/spinlock.h>
30441 +#include <linux/smp_lock.h>
30442 +#include <linux/smp.h>
30443 +#include <linux/kernel_stat.h>
30444 +#include <linux/mc146818rtc.h>
30445 +#include <linux/interrupt.h>
30447 +#include <asm/mtrr.h>
30448 +#include <asm/pgalloc.h>
30449 +#include <asm/tlbflush.h>
30450 +#include <asm/mach_apic.h>
30451 +#include <asm/mmu_context.h>
30452 +#include <asm/proto.h>
30453 +#include <asm/apicdef.h>
30454 +#include <asm/idle.h>
30456 +#include <xen/evtchn.h>
30459 +#ifndef CONFIG_XEN
30461 + * Smarter SMP flushing macros.
30462 + * c/o Linus Torvalds.
30464 + * These mean you can really definitely utterly forget about
30465 + * writing to user space from interrupts. (Its not allowed anyway).
30467 + * Optimizations Manfred Spraul <manfred@colorfullife.com>
30469 + * More scalable flush, from Andi Kleen
30471 + * To avoid global state use 8 different call vectors.
30472 + * Each CPU uses a specific vector to trigger flushes on other
30473 + * CPUs. Depending on the received vector the target CPUs look into
30474 + * the right per cpu variable for the flush data.
30476 + * With more than 8 CPUs they are hashed to the 8 available
30477 + * vectors. The limited global vector space forces us to this right now.
30478 + * In future when interrupts are split into per CPU domains this could be
30479 + * fixed, at the cost of triggering multiple IPIs in some cases.
30482 +union smp_flush_state {
30484 + cpumask_t flush_cpumask;
30485 + struct mm_struct *flush_mm;
30486 + unsigned long flush_va;
30487 +#define FLUSH_ALL -1ULL
30488 + spinlock_t tlbstate_lock;
30490 + char pad[SMP_CACHE_BYTES];
30491 +} ____cacheline_aligned;
30493 +/* State is put into the per CPU data section, but padded
30494 + to a full cache line because other CPUs can access it and we don't
30495 + want false sharing in the per cpu data segment. */
30496 +static DEFINE_PER_CPU(union smp_flush_state, flush_state);
30499 + * We cannot call mmdrop() because we are in interrupt context,
30500 + * instead update mm->cpu_vm_mask.
30502 +static inline void leave_mm(unsigned long cpu)
30504 + if (read_pda(mmu_state) == TLBSTATE_OK)
30506 + cpu_clear(cpu, read_pda(active_mm)->cpu_vm_mask);
30507 + load_cr3(swapper_pg_dir);
30512 + * The flush IPI assumes that a thread switch happens in this order:
30513 + * [cpu0: the cpu that switches]
30514 + * 1) switch_mm() either 1a) or 1b)
30515 + * 1a) thread switch to a different mm
30516 + * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
30517 + * Stop ipi delivery for the old mm. This is not synchronized with
30518 + * the other cpus, but smp_invalidate_interrupt ignore flush ipis
30519 + * for the wrong mm, and in the worst case we perform a superfluous
30521 + * 1a2) set cpu mmu_state to TLBSTATE_OK
30522 + * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
30523 + * was in lazy tlb mode.
30524 + * 1a3) update cpu active_mm
30525 + * Now cpu0 accepts tlb flushes for the new mm.
30526 + * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
30527 + * Now the other cpus will send tlb flush ipis.
30528 + * 1a4) change cr3.
30529 + * 1b) thread switch without mm change
30530 + * cpu active_mm is correct, cpu0 already handles
30532 + * 1b1) set cpu mmu_state to TLBSTATE_OK
30533 + * 1b2) test_and_set the cpu bit in cpu_vm_mask.
30534 + * Atomically set the bit [other cpus will start sending flush ipis],
30535 + * and test the bit.
30536 + * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
30537 + * 2) switch %%esp, ie current
30539 + * The interrupt must handle 2 special cases:
30540 + * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
30541 + * - the cpu performs speculative tlb reads, i.e. even if the cpu only
30542 + * runs in kernel space, the cpu could load tlb entries for user space
30545 + * The good news is that cpu mmu_state is local to each cpu, no
30546 + * write/read ordering problems.
30552 + * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
30553 + * 2) Leave the mm if we are in the lazy tlb mode.
30555 + * Interrupts are disabled.
30558 +asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs)
30562 + union smp_flush_state *f;
30564 + cpu = smp_processor_id();
30566 + * orig_rax contains the negated interrupt vector.
30567 + * Use that to determine where the sender put the data.
30569 + sender = ~regs->orig_rax - INVALIDATE_TLB_VECTOR_START;
30570 + f = &per_cpu(flush_state, sender);
30572 + if (!cpu_isset(cpu, f->flush_cpumask))
30575 + * This was a BUG() but until someone can quote me the
30576 + * line from the intel manual that guarantees an IPI to
30577 + * multiple CPUs is retried _only_ on the erroring CPUs
30578 + * its staying as a return
30583 + if (f->flush_mm == read_pda(active_mm)) {
30584 + if (read_pda(mmu_state) == TLBSTATE_OK) {
30585 + if (f->flush_va == FLUSH_ALL)
30586 + local_flush_tlb();
30588 + __flush_tlb_one(f->flush_va);
30594 + cpu_clear(cpu, f->flush_cpumask);
30597 +static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
30598 + unsigned long va)
30601 + union smp_flush_state *f;
30603 + /* Caller has disabled preemption */
30604 + sender = smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS;
30605 + f = &per_cpu(flush_state, sender);
30607 + /* Could avoid this lock when
30608 + num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
30609 + probably not worth checking this for a cache-hot lock. */
30610 + spin_lock(&f->tlbstate_lock);
30612 + f->flush_mm = mm;
30613 + f->flush_va = va;
30614 + cpus_or(f->flush_cpumask, cpumask, f->flush_cpumask);
30617 + * We have to send the IPI only to
30620 + send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR_START + sender);
30622 + while (!cpus_empty(f->flush_cpumask))
30625 + f->flush_mm = NULL;
30627 + spin_unlock(&f->tlbstate_lock);
30630 +int __cpuinit init_smp_flush(void)
30633 + for_each_cpu_mask(i, cpu_possible_map) {
30634 + spin_lock_init(&per_cpu(flush_state, i).tlbstate_lock);
30639 +core_initcall(init_smp_flush);
30641 +void flush_tlb_current_task(void)
30643 + struct mm_struct *mm = current->mm;
30644 + cpumask_t cpu_mask;
30646 + preempt_disable();
30647 + cpu_mask = mm->cpu_vm_mask;
30648 + cpu_clear(smp_processor_id(), cpu_mask);
30650 + local_flush_tlb();
30651 + if (!cpus_empty(cpu_mask))
30652 + flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
30653 + preempt_enable();
30655 +EXPORT_SYMBOL(flush_tlb_current_task);
30657 +void flush_tlb_mm (struct mm_struct * mm)
30659 + cpumask_t cpu_mask;
30661 + preempt_disable();
30662 + cpu_mask = mm->cpu_vm_mask;
30663 + cpu_clear(smp_processor_id(), cpu_mask);
30665 + if (current->active_mm == mm) {
30667 + local_flush_tlb();
30669 + leave_mm(smp_processor_id());
30671 + if (!cpus_empty(cpu_mask))
30672 + flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
30674 + preempt_enable();
30676 +EXPORT_SYMBOL(flush_tlb_mm);
30678 +void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
30680 + struct mm_struct *mm = vma->vm_mm;
30681 + cpumask_t cpu_mask;
30683 + preempt_disable();
30684 + cpu_mask = mm->cpu_vm_mask;
30685 + cpu_clear(smp_processor_id(), cpu_mask);
30687 + if (current->active_mm == mm) {
30689 + __flush_tlb_one(va);
30691 + leave_mm(smp_processor_id());
30694 + if (!cpus_empty(cpu_mask))
30695 + flush_tlb_others(cpu_mask, mm, va);
30697 + preempt_enable();
30699 +EXPORT_SYMBOL(flush_tlb_page);
30701 +static void do_flush_tlb_all(void* info)
30703 + unsigned long cpu = smp_processor_id();
30705 + __flush_tlb_all();
30706 + if (read_pda(mmu_state) == TLBSTATE_LAZY)
30710 +void flush_tlb_all(void)
30712 + on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
30717 + * this function sends a 'reschedule' IPI to another CPU.
30718 + * it goes straight through and wastes no time serializing
30719 + * anything. Worst case is that we lose a reschedule ...
30722 +void smp_send_reschedule(int cpu)
30724 + send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
30728 + * Structure and data for smp_call_function(). This is designed to minimise
30729 + * static memory requirements. It also looks cleaner.
30731 +static DEFINE_SPINLOCK(call_lock);
30733 +struct call_data_struct {
30734 + void (*func) (void *info);
30736 + atomic_t started;
30737 + atomic_t finished;
30741 +static struct call_data_struct * call_data;
30743 +void lock_ipi_call_lock(void)
30745 + spin_lock_irq(&call_lock);
30748 +void unlock_ipi_call_lock(void)
30750 + spin_unlock_irq(&call_lock);
30754 + * this function sends a 'generic call function' IPI to one other CPU
30757 + * cpu is a standard Linux logical CPU number.
30760 +__smp_call_function_single(int cpu, void (*func) (void *info), void *info,
30761 + int nonatomic, int wait)
30763 + struct call_data_struct data;
30766 + data.func = func;
30767 + data.info = info;
30768 + atomic_set(&data.started, 0);
30769 + data.wait = wait;
30771 + atomic_set(&data.finished, 0);
30773 + call_data = &data;
30775 + /* Send a message to all other CPUs and wait for them to respond */
30776 + send_IPI_mask(cpumask_of_cpu(cpu), CALL_FUNCTION_VECTOR);
30778 + /* Wait for response */
30779 + while (atomic_read(&data.started) != cpus)
30785 + while (atomic_read(&data.finished) != cpus)
30790 + * smp_call_function_single - Run a function on another CPU
30791 + * @func: The function to run. This must be fast and non-blocking.
30792 + * @info: An arbitrary pointer to pass to the function.
30793 + * @nonatomic: Currently unused.
30794 + * @wait: If true, wait until function has completed on other CPUs.
30796 + * Retrurns 0 on success, else a negative status code.
30798 + * Does not return until the remote CPU is nearly ready to execute <func>
30799 + * or is or has executed.
30802 +int smp_call_function_single (int cpu, void (*func) (void *info), void *info,
30803 + int nonatomic, int wait)
30805 + /* prevent preemption and reschedule on another processor */
30806 + int me = get_cpu();
30812 + spin_lock_bh(&call_lock);
30813 + __smp_call_function_single(cpu, func, info, nonatomic, wait);
30814 + spin_unlock_bh(&call_lock);
30820 + * this function sends a 'generic call function' IPI to all other CPUs
30823 +static void __smp_call_function (void (*func) (void *info), void *info,
30824 + int nonatomic, int wait)
30826 + struct call_data_struct data;
30827 + int cpus = num_online_cpus()-1;
30832 + data.func = func;
30833 + data.info = info;
30834 + atomic_set(&data.started, 0);
30835 + data.wait = wait;
30837 + atomic_set(&data.finished, 0);
30839 + call_data = &data;
30841 + /* Send a message to all other CPUs and wait for them to respond */
30842 + send_IPI_allbutself(CALL_FUNCTION_VECTOR);
30844 + /* Wait for response */
30845 + while (atomic_read(&data.started) != cpus)
30851 + while (atomic_read(&data.finished) != cpus)
30856 + * smp_call_function - run a function on all other CPUs.
30857 + * @func: The function to run. This must be fast and non-blocking.
30858 + * @info: An arbitrary pointer to pass to the function.
30859 + * @nonatomic: currently unused.
30860 + * @wait: If true, wait (atomically) until function has completed on other
30863 + * Returns 0 on success, else a negative status code. Does not return until
30864 + * remote CPUs are nearly ready to execute func or are or have executed.
30866 + * You must not call this function with disabled interrupts or from a
30867 + * hardware interrupt handler or from a bottom half handler.
30868 + * Actually there are a few legal cases, like panic.
30870 +int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
30873 + spin_lock(&call_lock);
30874 + __smp_call_function(func,info,nonatomic,wait);
30875 + spin_unlock(&call_lock);
30878 +EXPORT_SYMBOL(smp_call_function);
30880 +void smp_stop_cpu(void)
30882 + unsigned long flags;
30884 + * Remove this CPU:
30886 + cpu_clear(smp_processor_id(), cpu_online_map);
30887 + local_irq_save(flags);
30888 + disable_all_local_evtchn();
30889 + local_irq_restore(flags);
30892 +static void smp_really_stop_cpu(void *dummy)
30899 +void smp_send_stop(void)
30902 +#ifndef CONFIG_XEN
30903 + if (reboot_force)
30906 + /* Don't deadlock on the call lock in panic */
30907 + if (!spin_trylock(&call_lock)) {
30908 + /* ignore locking because we have panicked anyways */
30911 + __smp_call_function(smp_really_stop_cpu, NULL, 0, 0);
30913 + spin_unlock(&call_lock);
30915 + local_irq_disable();
30916 + disable_all_local_evtchn();
30917 + local_irq_enable();
30921 + * Reschedule call back. Nothing to do,
30922 + * all the work is done automatically when
30923 + * we return from the interrupt.
30925 +#ifndef CONFIG_XEN
30926 +asmlinkage void smp_reschedule_interrupt(void)
30928 +asmlinkage irqreturn_t smp_reschedule_interrupt(void)
30931 +#ifndef CONFIG_XEN
30934 + return IRQ_HANDLED;
30938 +#ifndef CONFIG_XEN
30939 +asmlinkage void smp_call_function_interrupt(void)
30941 +asmlinkage irqreturn_t smp_call_function_interrupt(void)
30944 + void (*func) (void *info) = call_data->func;
30945 + void *info = call_data->info;
30946 + int wait = call_data->wait;
30948 +#ifndef CONFIG_XEN
30952 + * Notify initiating CPU that I've grabbed the data and am
30953 + * about to execute the function
30956 + atomic_inc(&call_data->started);
30958 + * At this point the info structure may be out of scope unless wait==1
30966 + atomic_inc(&call_data->finished);
30969 + return IRQ_HANDLED;
30973 +int safe_smp_processor_id(void)
30976 + return smp_processor_id();
30978 + unsigned apicid, i;
30980 + if (disable_apic)
30983 + apicid = hard_smp_processor_id();
30984 + if (apicid < NR_CPUS && x86_cpu_to_apicid[apicid] == apicid)
30987 + for (i = 0; i < NR_CPUS; ++i) {
30988 + if (x86_cpu_to_apicid[i] == apicid)
30992 + /* No entries in x86_cpu_to_apicid? Either no MPS|ACPI,
30993 + * or called too early. Either way, we must be CPU 0. */
30994 + if (x86_cpu_to_apicid[0] == BAD_APICID)
30997 + return 0; /* Should not happen */
31000 Index: head-2008-11-25/arch/x86/kernel/traps_64-xen.c
31001 ===================================================================
31002 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
31003 +++ head-2008-11-25/arch/x86/kernel/traps_64-xen.c 2008-04-02 12:34:02.000000000 +0200
31006 + * linux/arch/x86-64/traps.c
31008 + * Copyright (C) 1991, 1992 Linus Torvalds
31009 + * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
31011 + * Pentium III FXSR, SSE support
31012 + * Gareth Hughes <gareth@valinux.com>, May 2000
31016 + * 'Traps.c' handles hardware traps and faults after we have saved some
31017 + * state in 'entry.S'.
31019 +#include <linux/sched.h>
31020 +#include <linux/kernel.h>
31021 +#include <linux/string.h>
31022 +#include <linux/errno.h>
31023 +#include <linux/ptrace.h>
31024 +#include <linux/timer.h>
31025 +#include <linux/mm.h>
31026 +#include <linux/init.h>
31027 +#include <linux/delay.h>
31028 +#include <linux/spinlock.h>
31029 +#include <linux/interrupt.h>
31030 +#include <linux/module.h>
31031 +#include <linux/moduleparam.h>
31032 +#include <linux/nmi.h>
31033 +#include <linux/kprobes.h>
31034 +#include <linux/kexec.h>
31035 +#include <linux/unwind.h>
31037 +#include <asm/system.h>
31038 +#include <asm/uaccess.h>
31039 +#include <asm/io.h>
31040 +#include <asm/atomic.h>
31041 +#include <asm/debugreg.h>
31042 +#include <asm/desc.h>
31043 +#include <asm/i387.h>
31044 +#include <asm/kdebug.h>
31045 +#include <asm/processor.h>
31046 +#include <asm/unwind.h>
31047 +#include <asm/smp.h>
31048 +#include <asm/pgalloc.h>
31049 +#include <asm/pda.h>
31050 +#include <asm/proto.h>
31051 +#include <asm/nmi.h>
31053 +asmlinkage void divide_error(void);
31054 +asmlinkage void debug(void);
31055 +asmlinkage void nmi(void);
31056 +asmlinkage void int3(void);
31057 +asmlinkage void overflow(void);
31058 +asmlinkage void bounds(void);
31059 +asmlinkage void invalid_op(void);
31060 +asmlinkage void device_not_available(void);
31061 +asmlinkage void double_fault(void);
31062 +asmlinkage void coprocessor_segment_overrun(void);
31063 +asmlinkage void invalid_TSS(void);
31064 +asmlinkage void segment_not_present(void);
31065 +asmlinkage void stack_segment(void);
31066 +asmlinkage void general_protection(void);
31067 +asmlinkage void page_fault(void);
31068 +asmlinkage void coprocessor_error(void);
31069 +asmlinkage void simd_coprocessor_error(void);
31070 +asmlinkage void reserved(void);
31071 +asmlinkage void alignment_check(void);
31072 +asmlinkage void machine_check(void);
31073 +asmlinkage void spurious_interrupt_bug(void);
31075 +ATOMIC_NOTIFIER_HEAD(die_chain);
31076 +EXPORT_SYMBOL(die_chain);
31078 +int register_die_notifier(struct notifier_block *nb)
31080 + vmalloc_sync_all();
31081 + return atomic_notifier_chain_register(&die_chain, nb);
31083 +EXPORT_SYMBOL(register_die_notifier); /* used modular by kdb */
31085 +int unregister_die_notifier(struct notifier_block *nb)
31087 + return atomic_notifier_chain_unregister(&die_chain, nb);
31089 +EXPORT_SYMBOL(unregister_die_notifier); /* used modular by kdb */
31091 +static inline void conditional_sti(struct pt_regs *regs)
31093 + if (regs->eflags & X86_EFLAGS_IF)
31094 + local_irq_enable();
31097 +static inline void preempt_conditional_sti(struct pt_regs *regs)
31099 + preempt_disable();
31100 + if (regs->eflags & X86_EFLAGS_IF)
31101 + local_irq_enable();
31104 +static inline void preempt_conditional_cli(struct pt_regs *regs)
31106 + if (regs->eflags & X86_EFLAGS_IF)
31107 + local_irq_disable();
31108 + /* Make sure to not schedule here because we could be running
31109 + on an exception stack. */
31110 + preempt_enable_no_resched();
31113 +static int kstack_depth_to_print = 12;
31114 +#ifdef CONFIG_STACK_UNWIND
31115 +static int call_trace = 1;
31117 +#define call_trace (-1)
31120 +#ifdef CONFIG_KALLSYMS
31121 +# include <linux/kallsyms.h>
31122 +void printk_address(unsigned long address)
31124 + unsigned long offset = 0, symsize;
31125 + const char *symname;
31127 + char *delim = ":";
31128 + char namebuf[128];
31130 + symname = kallsyms_lookup(address, &symsize, &offset,
31131 + &modname, namebuf);
31133 + printk(" [<%016lx>]\n", address);
31137 + modname = delim = "";
31138 + printk(" [<%016lx>] %s%s%s%s+0x%lx/0x%lx\n",
31139 + address, delim, modname, delim, symname, offset, symsize);
31142 +void printk_address(unsigned long address)
31144 + printk(" [<%016lx>]\n", address);
31148 +static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
31149 + unsigned *usedp, const char **idp)
31151 +#ifndef CONFIG_X86_NO_TSS
31152 + static char ids[][8] = {
31153 + [DEBUG_STACK - 1] = "#DB",
31154 + [NMI_STACK - 1] = "NMI",
31155 + [DOUBLEFAULT_STACK - 1] = "#DF",
31156 + [STACKFAULT_STACK - 1] = "#SS",
31157 + [MCE_STACK - 1] = "#MC",
31158 +#if DEBUG_STKSZ > EXCEPTION_STKSZ
31159 + [N_EXCEPTION_STACKS ... N_EXCEPTION_STACKS + DEBUG_STKSZ / EXCEPTION_STKSZ - 2] = "#DB[?]"
31165 + * Iterate over all exception stacks, and figure out whether
31166 + * 'stack' is in one of them:
31168 + for (k = 0; k < N_EXCEPTION_STACKS; k++) {
31169 + unsigned long end;
31172 + * set 'end' to the end of the exception stack.
31176 + * TODO: this block is not needed i think, because
31177 + * setup64.c:cpu_init() sets up t->ist[DEBUG_STACK]
31180 +#if DEBUG_STKSZ > EXCEPTION_STKSZ
31181 + case DEBUG_STACK:
31182 + end = cpu_pda(cpu)->debugstack + DEBUG_STKSZ;
31186 + end = per_cpu(orig_ist, cpu).ist[k];
31190 + * Is 'stack' above this exception frame's end?
31191 + * If yes then skip to the next frame.
31193 + if (stack >= end)
31196 + * Is 'stack' above this exception frame's start address?
31197 + * If yes then we found the right frame.
31199 + if (stack >= end - EXCEPTION_STKSZ) {
31201 + * Make sure we only iterate through an exception
31202 + * stack once. If it comes up for the second time
31203 + * then there's something wrong going on - just
31204 + * break out and return NULL:
31206 + if (*usedp & (1U << k))
31208 + *usedp |= 1U << k;
31210 + return (unsigned long *)end;
31213 + * If this is a debug stack, and if it has a larger size than
31214 + * the usual exception stacks, then 'stack' might still
31215 + * be within the lower portion of the debug stack:
31217 +#if DEBUG_STKSZ > EXCEPTION_STKSZ
31218 + if (k == DEBUG_STACK - 1 && stack >= end - DEBUG_STKSZ) {
31219 + unsigned j = N_EXCEPTION_STACKS - 1;
31222 + * Black magic. A large debug stack is composed of
31223 + * multiple exception stack entries, which we
31224 + * iterate through now. Dont look:
31228 + end -= EXCEPTION_STKSZ;
31229 + ids[j][4] = '1' + (j - N_EXCEPTION_STACKS);
31230 + } while (stack < end - EXCEPTION_STKSZ);
31231 + if (*usedp & (1U << j))
31233 + *usedp |= 1U << j;
31235 + return (unsigned long *)end;
31243 +static int show_trace_unwind(struct unwind_frame_info *info, void *context)
31247 + while (unwind(info) == 0 && UNW_PC(info)) {
31249 + printk_address(UNW_PC(info));
31250 + if (arch_unw_user_mode(info))
31257 + * x86-64 can have upto three kernel stacks:
31259 + * interrupt stack
31260 + * severe exception (double fault, nmi, stack fault, debug, mce) hardware stack
31263 +void show_trace(struct task_struct *tsk, struct pt_regs *regs, unsigned long * stack)
31265 + const unsigned cpu = safe_smp_processor_id();
31266 + unsigned long *irqstack_end = (unsigned long *)cpu_pda(cpu)->irqstackptr;
31267 + unsigned used = 0;
31269 + printk("\nCall Trace:\n");
31274 + if (call_trace >= 0) {
31276 + struct unwind_frame_info info;
31279 + if (unwind_init_frame_info(&info, tsk, regs) == 0)
31280 + unw_ret = show_trace_unwind(&info, NULL);
31281 + } else if (tsk == current)
31282 + unw_ret = unwind_init_running(&info, show_trace_unwind, NULL);
31284 + if (unwind_init_blocked(&info, tsk) == 0)
31285 + unw_ret = show_trace_unwind(&info, NULL);
31287 + if (unw_ret > 0) {
31288 + if (call_trace == 1 && !arch_unw_user_mode(&info)) {
31289 + print_symbol("DWARF2 unwinder stuck at %s\n",
31291 + if ((long)UNW_SP(&info) < 0) {
31292 + printk("Leftover inexact backtrace:\n");
31293 + stack = (unsigned long *)UNW_SP(&info);
31295 + printk("Full inexact backtrace again:\n");
31296 + } else if (call_trace >= 1)
31299 + printk("Full inexact backtrace again:\n");
31301 + printk("Inexact backtrace:\n");
31305 + * Print function call entries within a stack. 'cond' is the
31306 + * "end of stackframe" condition, that the 'stack++'
31307 + * iteration will eventually trigger.
31309 +#define HANDLE_STACK(cond) \
31310 + do while (cond) { \
31311 + unsigned long addr = *stack++; \
31312 + if (kernel_text_address(addr)) { \
31314 + * If the address is either in the text segment of the \
31315 + * kernel, or in the region which contains vmalloc'ed \
31316 + * memory, it *may* be the address of a calling \
31317 + * routine; if so, print it so that someone tracing \
31318 + * down the cause of the crash will be able to figure \
31319 + * out the call path that was taken. \
31321 + printk_address(addr); \
31326 + * Print function call entries in all stacks, starting at the
31327 + * current stack address. If the stacks consist of nested
31332 + unsigned long *estack_end;
31333 + estack_end = in_exception_stack(cpu, (unsigned long)stack,
31336 + if (estack_end) {
31337 + printk(" <%s>", id);
31338 + HANDLE_STACK (stack < estack_end);
31339 + printk(" <EOE>");
31341 + * We link to the next stack via the
31342 + * second-to-last pointer (index -2 to end) in the
31343 + * exception stack:
31345 + stack = (unsigned long *) estack_end[-2];
31348 + if (irqstack_end) {
31349 + unsigned long *irqstack;
31350 + irqstack = irqstack_end -
31351 + (IRQSTACKSIZE - 64) / sizeof(*irqstack);
31353 + if (stack >= irqstack && stack < irqstack_end) {
31354 + printk(" <IRQ>");
31355 + HANDLE_STACK (stack < irqstack_end);
31357 + * We link to the next stack (which would be
31358 + * the process stack normally) the last
31359 + * pointer (index -1 to end) in the IRQ stack:
31361 + stack = (unsigned long *) (irqstack_end[-1]);
31362 + irqstack_end = NULL;
31363 + printk(" <EOI>");
31371 + * This prints the process stack:
31373 + HANDLE_STACK (((long) stack & (THREAD_SIZE-1)) != 0);
31374 +#undef HANDLE_STACK
31379 +static void _show_stack(struct task_struct *tsk, struct pt_regs *regs, unsigned long * rsp)
31381 + unsigned long *stack;
31383 + const int cpu = safe_smp_processor_id();
31384 + unsigned long *irqstack_end = (unsigned long *) (cpu_pda(cpu)->irqstackptr);
31385 + unsigned long *irqstack = (unsigned long *) (cpu_pda(cpu)->irqstackptr - IRQSTACKSIZE);
31387 + // debugging aid: "show_stack(NULL, NULL);" prints the
31388 + // back trace for this cpu.
31390 + if (rsp == NULL) {
31392 + rsp = (unsigned long *)tsk->thread.rsp;
31394 + rsp = (unsigned long *)&rsp;
31398 + for(i=0; i < kstack_depth_to_print; i++) {
31399 + if (stack >= irqstack && stack <= irqstack_end) {
31400 + if (stack == irqstack_end) {
31401 + stack = (unsigned long *) (irqstack_end[-1]);
31402 + printk(" <EOI> ");
31405 + if (((long) stack & (THREAD_SIZE-1)) == 0)
31408 + if (i && ((i % 4) == 0))
31410 + printk(" %016lx", *stack++);
31411 + touch_nmi_watchdog();
31413 + show_trace(tsk, regs, rsp);
31416 +void show_stack(struct task_struct *tsk, unsigned long * rsp)
31418 + _show_stack(tsk, NULL, rsp);
31422 + * The architecture-independent dump_stack generator
31424 +void dump_stack(void)
31426 + unsigned long dummy;
31427 + show_trace(NULL, NULL, &dummy);
31430 +EXPORT_SYMBOL(dump_stack);
31432 +void show_registers(struct pt_regs *regs)
31435 + int in_kernel = !user_mode(regs);
31436 + unsigned long rsp;
31437 + const int cpu = safe_smp_processor_id();
31438 + struct task_struct *cur = cpu_pda(cpu)->pcurrent;
31442 + printk("CPU %d ", cpu);
31443 + __show_regs(regs);
31444 + printk("Process %s (pid: %d, threadinfo %p, task %p)\n",
31445 + cur->comm, cur->pid, task_thread_info(cur), cur);
31448 + * When in-kernel, we also print out the stack and code at the
31449 + * time of the fault..
31453 + printk("Stack: ");
31454 + _show_stack(NULL, regs, (unsigned long*)rsp);
31456 + printk("\nCode: ");
31457 + if (regs->rip < PAGE_OFFSET)
31460 + for (i=0; i<20; i++) {
31462 + if (__get_user(c, &((unsigned char*)regs->rip)[i])) {
31464 + printk(" Bad RIP value.");
31467 + printk("%02x ", c);
31473 +void handle_BUG(struct pt_regs *regs)
31475 + struct bug_frame f;
31477 + const char *prefix = "";
31479 + if (user_mode(regs))
31481 + if (__copy_from_user(&f, (const void __user *) regs->rip,
31482 + sizeof(struct bug_frame)))
31484 + if (f.filename >= 0 ||
31485 + f.ud2[0] != 0x0f || f.ud2[1] != 0x0b)
31487 + len = __strnlen_user((char *)(long)f.filename, PATH_MAX) - 1;
31488 + if (len < 0 || len >= PATH_MAX)
31489 + f.filename = (int)(long)"unmapped filename";
31490 + else if (len > 50) {
31491 + f.filename += len - 50;
31494 + printk("----------- [cut here ] --------- [please bite here ] ---------\n");
31495 + printk(KERN_ALERT "Kernel BUG at %s%.50s:%d\n", prefix, (char *)(long)f.filename, f.line);
31499 +void out_of_line_bug(void)
31503 +EXPORT_SYMBOL(out_of_line_bug);
31506 +static DEFINE_SPINLOCK(die_lock);
31507 +static int die_owner = -1;
31508 +static unsigned int die_nest_count;
31510 +unsigned __kprobes long oops_begin(void)
31512 + int cpu = safe_smp_processor_id();
31513 + unsigned long flags;
31515 + /* racy, but better than risking deadlock. */
31516 + local_irq_save(flags);
31517 + if (!spin_trylock(&die_lock)) {
31518 + if (cpu == die_owner)
31519 + /* nested oops. should stop eventually */;
31521 + spin_lock(&die_lock);
31523 + die_nest_count++;
31525 + console_verbose();
31526 + bust_spinlocks(1);
31530 +void __kprobes oops_end(unsigned long flags)
31533 + bust_spinlocks(0);
31534 + die_nest_count--;
31535 + if (die_nest_count)
31536 + /* We still own the lock */
31537 + local_irq_restore(flags);
31539 + /* Nest count reaches zero, release the lock. */
31540 + spin_unlock_irqrestore(&die_lock, flags);
31541 + if (panic_on_oops)
31542 + panic("Fatal exception");
31545 +void __kprobes __die(const char * str, struct pt_regs * regs, long err)
31547 + static int die_counter;
31548 + printk(KERN_EMERG "%s: %04lx [%u] ", str, err & 0xffff,++die_counter);
31549 +#ifdef CONFIG_PREEMPT
31550 + printk("PREEMPT ");
31555 +#ifdef CONFIG_DEBUG_PAGEALLOC
31556 + printk("DEBUG_PAGEALLOC");
31559 + notify_die(DIE_OOPS, str, regs, err, current->thread.trap_no, SIGSEGV);
31560 + show_registers(regs);
31561 + /* Executive summary in case the oops scrolled away */
31562 + printk(KERN_ALERT "RIP ");
31563 + printk_address(regs->rip);
31564 + printk(" RSP <%016lx>\n", regs->rsp);
31565 + if (kexec_should_crash(current))
31566 + crash_kexec(regs);
31569 +void die(const char * str, struct pt_regs * regs, long err)
31571 + unsigned long flags = oops_begin();
31573 + handle_BUG(regs);
31574 + __die(str, regs, err);
31576 + do_exit(SIGSEGV);
31579 +#ifdef CONFIG_X86_LOCAL_APIC
31580 +void __kprobes die_nmi(char *str, struct pt_regs *regs)
31582 + unsigned long flags = oops_begin();
31585 + * We are in trouble anyway, lets at least try
31586 + * to get a message out.
31588 + printk(str, safe_smp_processor_id());
31589 + show_registers(regs);
31590 + if (kexec_should_crash(current))
31591 + crash_kexec(regs);
31592 + if (panic_on_timeout || panic_on_oops)
31593 + panic("nmi watchdog");
31594 + printk("console shuts up ...\n");
31597 + local_irq_enable();
31598 + do_exit(SIGSEGV);
31602 +static void __kprobes do_trap(int trapnr, int signr, char *str,
31603 + struct pt_regs * regs, long error_code,
31606 + struct task_struct *tsk = current;
31608 + tsk->thread.error_code = error_code;
31609 + tsk->thread.trap_no = trapnr;
31611 + if (user_mode(regs)) {
31612 + if (exception_trace && unhandled_signal(tsk, signr))
31614 + "%s[%d] trap %s rip:%lx rsp:%lx error:%lx\n",
31615 + tsk->comm, tsk->pid, str,
31616 + regs->rip, regs->rsp, error_code);
31619 + force_sig_info(signr, info, tsk);
31621 + force_sig(signr, tsk);
31626 + /* kernel trap */
31628 + const struct exception_table_entry *fixup;
31629 + fixup = search_exception_tables(regs->rip);
31631 + regs->rip = fixup->fixup;
31633 + die(str, regs, error_code);
31638 +#define DO_ERROR(trapnr, signr, str, name) \
31639 +asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
31641 + if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
31642 + == NOTIFY_STOP) \
31644 + conditional_sti(regs); \
31645 + do_trap(trapnr, signr, str, regs, error_code, NULL); \
31648 +#define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
31649 +asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
31651 + siginfo_t info; \
31652 + info.si_signo = signr; \
31653 + info.si_errno = 0; \
31654 + info.si_code = sicode; \
31655 + info.si_addr = (void __user *)siaddr; \
31656 + if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
31657 + == NOTIFY_STOP) \
31659 + conditional_sti(regs); \
31660 + do_trap(trapnr, signr, str, regs, error_code, &info); \
31663 +DO_ERROR_INFO( 0, SIGFPE, "divide error", divide_error, FPE_INTDIV, regs->rip)
31664 +DO_ERROR( 4, SIGSEGV, "overflow", overflow)
31665 +DO_ERROR( 5, SIGSEGV, "bounds", bounds)
31666 +DO_ERROR_INFO( 6, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN, regs->rip)
31667 +DO_ERROR( 7, SIGSEGV, "device not available", device_not_available)
31668 +DO_ERROR( 9, SIGFPE, "coprocessor segment overrun", coprocessor_segment_overrun)
31669 +DO_ERROR(10, SIGSEGV, "invalid TSS", invalid_TSS)
31670 +DO_ERROR(11, SIGBUS, "segment not present", segment_not_present)
31671 +DO_ERROR_INFO(17, SIGBUS, "alignment check", alignment_check, BUS_ADRALN, 0)
31672 +DO_ERROR(18, SIGSEGV, "reserved", reserved)
31674 +/* Runs on IST stack */
31675 +asmlinkage void do_stack_segment(struct pt_regs *regs, long error_code)
31677 + if (notify_die(DIE_TRAP, "stack segment", regs, error_code,
31678 + 12, SIGBUS) == NOTIFY_STOP)
31680 + preempt_conditional_sti(regs);
31681 + do_trap(12, SIGBUS, "stack segment", regs, error_code, NULL);
31682 + preempt_conditional_cli(regs);
31685 +asmlinkage void do_double_fault(struct pt_regs * regs, long error_code)
31687 + static const char str[] = "double fault";
31688 + struct task_struct *tsk = current;
31690 + /* Return not checked because double check cannot be ignored */
31691 + notify_die(DIE_TRAP, str, regs, error_code, 8, SIGSEGV);
31693 + tsk->thread.error_code = error_code;
31694 + tsk->thread.trap_no = 8;
31696 + /* This is always a kernel trap and never fixable (and thus must
31697 + never return). */
31699 + die(str, regs, error_code);
31702 +asmlinkage void __kprobes do_general_protection(struct pt_regs * regs,
31705 + struct task_struct *tsk = current;
31707 + conditional_sti(regs);
31709 + tsk->thread.error_code = error_code;
31710 + tsk->thread.trap_no = 13;
31712 + if (user_mode(regs)) {
31713 + if (exception_trace && unhandled_signal(tsk, SIGSEGV))
31715 + "%s[%d] general protection rip:%lx rsp:%lx error:%lx\n",
31716 + tsk->comm, tsk->pid,
31717 + regs->rip, regs->rsp, error_code);
31719 + force_sig(SIGSEGV, tsk);
31725 + const struct exception_table_entry *fixup;
31726 + fixup = search_exception_tables(regs->rip);
31728 + regs->rip = fixup->fixup;
31731 + if (notify_die(DIE_GPF, "general protection fault", regs,
31732 + error_code, 13, SIGSEGV) == NOTIFY_STOP)
31734 + die("general protection fault", regs, error_code);
31738 +static __kprobes void
31739 +mem_parity_error(unsigned char reason, struct pt_regs * regs)
31741 + printk("Uhhuh. NMI received. Dazed and confused, but trying to continue\n");
31742 + printk("You probably have a hardware problem with your RAM chips\n");
31745 + /* Clear and disable the memory parity error line. */
31746 + reason = (reason & 0xf) | 4;
31747 + outb(reason, 0x61);
31751 +static __kprobes void
31752 +io_check_error(unsigned char reason, struct pt_regs * regs)
31754 + printk("NMI: IOCK error (debug interrupt?)\n");
31755 + show_registers(regs);
31758 + /* Re-enable the IOCK line, wait for a few seconds */
31759 + reason = (reason & 0xf) | 8;
31760 + outb(reason, 0x61);
31763 + outb(reason, 0x61);
31767 +static __kprobes void
31768 +unknown_nmi_error(unsigned char reason, struct pt_regs * regs)
31769 +{ printk("Uhhuh. NMI received for unknown reason %02x.\n", reason);
31770 + printk("Dazed and confused, but trying to continue\n");
31771 + printk("Do you have a strange power saving mode enabled?\n");
31774 +/* Runs on IST stack. This code must keep interrupts off all the time.
31775 + Nested NMIs are prevented by the CPU. */
31776 +asmlinkage __kprobes void default_do_nmi(struct pt_regs *regs)
31778 + unsigned char reason = 0;
31781 + cpu = smp_processor_id();
31783 + /* Only the BSP gets external NMIs from the system. */
31785 + reason = get_nmi_reason();
31787 + if (!(reason & 0xc0)) {
31788 + if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT)
31791 +#ifdef CONFIG_X86_LOCAL_APIC
31793 + * Ok, so this is none of the documented NMI sources,
31794 + * so it must be the NMI watchdog.
31796 + if (nmi_watchdog > 0) {
31797 + nmi_watchdog_tick(regs,reason);
31801 + unknown_nmi_error(reason, regs);
31804 + if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
31807 + /* AK: following checks seem to be broken on modern chipsets. FIXME */
31809 + if (reason & 0x80)
31810 + mem_parity_error(reason, regs);
31811 + if (reason & 0x40)
31812 + io_check_error(reason, regs);
31815 +/* runs on IST stack. */
31816 +asmlinkage void __kprobes do_int3(struct pt_regs * regs, long error_code)
31818 + if (notify_die(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP) == NOTIFY_STOP) {
31821 + preempt_conditional_sti(regs);
31822 + do_trap(3, SIGTRAP, "int3", regs, error_code, NULL);
31823 + preempt_conditional_cli(regs);
31826 +/* Help handler running on IST stack to switch back to user stack
31827 + for scheduling or signal handling. The actual stack switch is done in
31829 +asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
31831 + struct pt_regs *regs = eregs;
31832 + /* Did already sync */
31833 + if (eregs == (struct pt_regs *)eregs->rsp)
31835 + /* Exception from user space */
31836 + else if (user_mode(eregs))
31837 + regs = task_pt_regs(current);
31838 + /* Exception from kernel and interrupts are enabled. Move to
31839 + kernel process stack. */
31840 + else if (eregs->eflags & X86_EFLAGS_IF)
31841 + regs = (struct pt_regs *)(eregs->rsp -= sizeof(struct pt_regs));
31842 + if (eregs != regs)
31847 +/* runs on IST stack. */
31848 +asmlinkage void __kprobes do_debug(struct pt_regs * regs,
31849 + unsigned long error_code)
31851 + unsigned long condition;
31852 + struct task_struct *tsk = current;
31855 + get_debugreg(condition, 6);
31857 + if (notify_die(DIE_DEBUG, "debug", regs, condition, error_code,
31858 + SIGTRAP) == NOTIFY_STOP)
31861 + preempt_conditional_sti(regs);
31863 + /* Mask out spurious debug traps due to lazy DR7 setting */
31864 + if (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)) {
31865 + if (!tsk->thread.debugreg7) {
31870 + tsk->thread.debugreg6 = condition;
31872 + /* Mask out spurious TF errors due to lazy TF clearing */
31873 + if (condition & DR_STEP) {
31875 + * The TF error should be masked out only if the current
31876 + * process is not traced and if the TRAP flag has been set
31877 + * previously by a tracing process (condition detected by
31878 + * the PT_DTRACE flag); remember that the i386 TRAP flag
31879 + * can be modified by the process itself in user mode,
31880 + * allowing programs to debug themselves without the ptrace()
31883 + if (!user_mode(regs))
31884 + goto clear_TF_reenable;
31886 + * Was the TF flag set by a debugger? If so, clear it now,
31887 + * so that register information is correct.
31889 + if (tsk->ptrace & PT_DTRACE) {
31890 + regs->eflags &= ~TF_MASK;
31891 + tsk->ptrace &= ~PT_DTRACE;
31895 + /* Ok, finally something we can handle */
31896 + tsk->thread.trap_no = 1;
31897 + tsk->thread.error_code = error_code;
31898 + info.si_signo = SIGTRAP;
31899 + info.si_errno = 0;
31900 + info.si_code = TRAP_BRKPT;
31901 + info.si_addr = user_mode(regs) ? (void __user *)regs->rip : NULL;
31902 + force_sig_info(SIGTRAP, &info, tsk);
31905 + set_debugreg(0UL, 7);
31906 + preempt_conditional_cli(regs);
31909 +clear_TF_reenable:
31910 + set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
31911 + regs->eflags &= ~TF_MASK;
31912 + preempt_conditional_cli(regs);
31915 +static int kernel_math_error(struct pt_regs *regs, const char *str, int trapnr)
31917 + const struct exception_table_entry *fixup;
31918 + fixup = search_exception_tables(regs->rip);
31920 + regs->rip = fixup->fixup;
31923 + notify_die(DIE_GPF, str, regs, 0, trapnr, SIGFPE);
31924 + /* Illegal floating point operation in the kernel */
31925 + current->thread.trap_no = trapnr;
31926 + die(str, regs, 0);
31931 + * Note that we play around with the 'TS' bit in an attempt to get
31932 + * the correct behaviour even in the presence of the asynchronous
31933 + * IRQ13 behaviour
31935 +asmlinkage void do_coprocessor_error(struct pt_regs *regs)
31937 + void __user *rip = (void __user *)(regs->rip);
31938 + struct task_struct * task;
31940 + unsigned short cwd, swd;
31942 + conditional_sti(regs);
31943 + if (!user_mode(regs) &&
31944 + kernel_math_error(regs, "kernel x87 math error", 16))
31948 + * Save the info for the exception handler and clear the error.
31951 + save_init_fpu(task);
31952 + task->thread.trap_no = 16;
31953 + task->thread.error_code = 0;
31954 + info.si_signo = SIGFPE;
31955 + info.si_errno = 0;
31956 + info.si_code = __SI_FAULT;
31957 + info.si_addr = rip;
31959 + * (~cwd & swd) will mask out exceptions that are not set to unmasked
31960 + * status. 0x3f is the exception bits in these regs, 0x200 is the
31961 + * C1 reg you need in case of a stack fault, 0x040 is the stack
31962 + * fault bit. We should only be taking one exception at a time,
31963 + * so if this combination doesn't produce any single exception,
31964 + * then we have a bad program that isn't synchronizing its FPU usage
31965 + * and it will suffer the consequences since we won't be able to
31966 + * fully reproduce the context of the exception
31968 + cwd = get_fpu_cwd(task);
31969 + swd = get_fpu_swd(task);
31970 + switch (swd & ~cwd & 0x3f) {
31974 + case 0x001: /* Invalid Op */
31976 + * swd & 0x240 == 0x040: Stack Underflow
31977 + * swd & 0x240 == 0x240: Stack Overflow
31978 + * User must clear the SF bit (0x40) if set
31980 + info.si_code = FPE_FLTINV;
31982 + case 0x002: /* Denormalize */
31983 + case 0x010: /* Underflow */
31984 + info.si_code = FPE_FLTUND;
31986 + case 0x004: /* Zero Divide */
31987 + info.si_code = FPE_FLTDIV;
31989 + case 0x008: /* Overflow */
31990 + info.si_code = FPE_FLTOVF;
31992 + case 0x020: /* Precision */
31993 + info.si_code = FPE_FLTRES;
31996 + force_sig_info(SIGFPE, &info, task);
31999 +asmlinkage void bad_intr(void)
32001 + printk("bad interrupt");
32004 +asmlinkage void do_simd_coprocessor_error(struct pt_regs *regs)
32006 + void __user *rip = (void __user *)(regs->rip);
32007 + struct task_struct * task;
32009 + unsigned short mxcsr;
32011 + conditional_sti(regs);
32012 + if (!user_mode(regs) &&
32013 + kernel_math_error(regs, "kernel simd math error", 19))
32017 + * Save the info for the exception handler and clear the error.
32020 + save_init_fpu(task);
32021 + task->thread.trap_no = 19;
32022 + task->thread.error_code = 0;
32023 + info.si_signo = SIGFPE;
32024 + info.si_errno = 0;
32025 + info.si_code = __SI_FAULT;
32026 + info.si_addr = rip;
32028 + * The SIMD FPU exceptions are handled a little differently, as there
32029 + * is only a single status/control register. Thus, to determine which
32030 + * unmasked exception was caught we must mask the exception mask bits
32031 + * at 0x1f80, and then use these to mask the exception bits at 0x3f.
32033 + mxcsr = get_fpu_mxcsr(task);
32034 + switch (~((mxcsr & 0x1f80) >> 7) & (mxcsr & 0x3f)) {
32038 + case 0x001: /* Invalid Op */
32039 + info.si_code = FPE_FLTINV;
32041 + case 0x002: /* Denormalize */
32042 + case 0x010: /* Underflow */
32043 + info.si_code = FPE_FLTUND;
32045 + case 0x004: /* Zero Divide */
32046 + info.si_code = FPE_FLTDIV;
32048 + case 0x008: /* Overflow */
32049 + info.si_code = FPE_FLTOVF;
32051 + case 0x020: /* Precision */
32052 + info.si_code = FPE_FLTRES;
32055 + force_sig_info(SIGFPE, &info, task);
32058 +asmlinkage void do_spurious_interrupt_bug(struct pt_regs * regs)
32063 +asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void)
32068 +asmlinkage void __attribute__((weak)) mce_threshold_interrupt(void)
32073 + * 'math_state_restore()' saves the current math information in the
32074 + * old math state array, and gets the new ones from the current task
32076 + * Careful.. There are problems with IBM-designed IRQ13 behaviour.
32077 + * Don't touch unless you *really* know how it works.
32079 +asmlinkage void math_state_restore(void)
32081 + struct task_struct *me = current;
32082 + /* clts(); */ /* 'clts' is done for us by Xen during virtual trap. */
32084 + if (!used_math())
32086 + restore_fpu_checking(&me->thread.i387.fxsave);
32087 + task_thread_info(me)->status |= TS_USEDFPU;
32092 + * NB. All these are "interrupt gates" (i.e. events_mask is set) because we
32093 + * specify <dpl>|4 in the second field.
32095 +static trap_info_t __cpuinitdata trap_table[] = {
32096 + { 0, 0|4, __KERNEL_CS, (unsigned long)divide_error },
32097 + { 1, 0|4, __KERNEL_CS, (unsigned long)debug },
32098 + { 3, 3|4, __KERNEL_CS, (unsigned long)int3 },
32099 + { 4, 3|4, __KERNEL_CS, (unsigned long)overflow },
32100 + { 5, 0|4, __KERNEL_CS, (unsigned long)bounds },
32101 + { 6, 0|4, __KERNEL_CS, (unsigned long)invalid_op },
32102 + { 7, 0|4, __KERNEL_CS, (unsigned long)device_not_available },
32103 + { 9, 0|4, __KERNEL_CS, (unsigned long)coprocessor_segment_overrun},
32104 + { 10, 0|4, __KERNEL_CS, (unsigned long)invalid_TSS },
32105 + { 11, 0|4, __KERNEL_CS, (unsigned long)segment_not_present },
32106 + { 12, 0|4, __KERNEL_CS, (unsigned long)stack_segment },
32107 + { 13, 0|4, __KERNEL_CS, (unsigned long)general_protection },
32108 + { 14, 0|4, __KERNEL_CS, (unsigned long)page_fault },
32109 + { 15, 0|4, __KERNEL_CS, (unsigned long)spurious_interrupt_bug },
32110 + { 16, 0|4, __KERNEL_CS, (unsigned long)coprocessor_error },
32111 + { 17, 0|4, __KERNEL_CS, (unsigned long)alignment_check },
32112 +#ifdef CONFIG_X86_MCE
32113 + { 18, 0|4, __KERNEL_CS, (unsigned long)machine_check },
32115 + { 19, 0|4, __KERNEL_CS, (unsigned long)simd_coprocessor_error },
32116 +#ifdef CONFIG_IA32_EMULATION
32117 + { IA32_SYSCALL_VECTOR, 3, __KERNEL_CS, (unsigned long)ia32_syscall},
32122 +void __init trap_init(void)
32126 + ret = HYPERVISOR_set_trap_table(trap_table);
32128 + printk("HYPERVISOR_set_trap_table failed: error %d\n", ret);
32131 + * Should be a barrier for any external CPU state.
32136 +void __cpuinit smp_trap_init(trap_info_t *trap_ctxt)
32138 + const trap_info_t *t = trap_table;
32140 + for (t = trap_table; t->address; t++) {
32141 + trap_ctxt[t->vector].flags = t->flags;
32142 + trap_ctxt[t->vector].cs = t->cs;
32143 + trap_ctxt[t->vector].address = t->address;
32148 +/* Actual parsing is done early in setup.c. */
32149 +static int __init oops_dummy(char *s)
32151 + panic_on_oops = 1;
32154 +__setup("oops=", oops_dummy);
32156 +static int __init kstack_setup(char *s)
32158 + kstack_depth_to_print = simple_strtoul(s,NULL,0);
32161 +__setup("kstack=", kstack_setup);
32163 +#ifdef CONFIG_STACK_UNWIND
32164 +static int __init call_trace_setup(char *s)
32166 + if (strcmp(s, "old") == 0)
32168 + else if (strcmp(s, "both") == 0)
32170 + else if (strcmp(s, "newfallback") == 0)
32172 + else if (strcmp(s, "new") == 0)
32176 +__setup("call_trace=", call_trace_setup);
32178 Index: head-2008-11-25/arch/x86/kernel/vsyscall_64-xen.c
32179 ===================================================================
32180 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
32181 +++ head-2008-11-25/arch/x86/kernel/vsyscall_64-xen.c 2007-06-18 08:38:13.000000000 +0200
32184 + * linux/arch/x86_64/kernel/vsyscall.c
32186 + * Copyright (C) 2001 Andrea Arcangeli <andrea@suse.de> SuSE
32187 + * Copyright 2003 Andi Kleen, SuSE Labs.
32189 + * Thanks to hpa@transmeta.com for some useful hint.
32190 + * Special thanks to Ingo Molnar for his early experience with
32191 + * a different vsyscall implementation for Linux/IA32 and for the name.
32193 + * vsyscall 1 is located at -10Mbyte, vsyscall 2 is located
32194 + * at virtual address -10Mbyte+1024bytes etc... There are at max 4
32195 + * vsyscalls. One vsyscall can reserve more than 1 slot to avoid
32196 + * jumping out of line if necessary. We cannot add more with this
32197 + * mechanism because older kernels won't return -ENOSYS.
32198 + * If we want more than four we need a vDSO.
32200 + * Note: the concept clashes with user mode linux. If you use UML and
32201 + * want per guest time just set the kernel.vsyscall64 sysctl to 0.
32204 +#include <linux/time.h>
32205 +#include <linux/init.h>
32206 +#include <linux/kernel.h>
32207 +#include <linux/timer.h>
32208 +#include <linux/seqlock.h>
32209 +#include <linux/jiffies.h>
32210 +#include <linux/sysctl.h>
32212 +#include <asm/vsyscall.h>
32213 +#include <asm/pgtable.h>
32214 +#include <asm/page.h>
32215 +#include <asm/fixmap.h>
32216 +#include <asm/errno.h>
32217 +#include <asm/io.h>
32219 +#define __vsyscall(nr) __attribute__ ((unused,__section__(".vsyscall_" #nr)))
32221 +int __sysctl_vsyscall __section_sysctl_vsyscall = 1;
32222 +seqlock_t __xtime_lock __section_xtime_lock = SEQLOCK_UNLOCKED;
32224 +#include <asm/unistd.h>
32226 +static __always_inline void timeval_normalize(struct timeval * tv)
32230 + __sec = tv->tv_usec / 1000000;
32232 + tv->tv_usec %= 1000000;
32233 + tv->tv_sec += __sec;
32237 +static __always_inline void do_vgettimeofday(struct timeval * tv)
32239 + long sequence, t;
32240 + unsigned long sec, usec;
32243 + sequence = read_seqbegin(&__xtime_lock);
32245 + sec = __xtime.tv_sec;
32246 + usec = (__xtime.tv_nsec / 1000) +
32247 + (__jiffies - __wall_jiffies) * (1000000 / HZ);
32249 + if (__vxtime.mode != VXTIME_HPET) {
32250 + t = get_cycles_sync();
32251 + if (t < __vxtime.last_tsc)
32252 + t = __vxtime.last_tsc;
32253 + usec += ((t - __vxtime.last_tsc) *
32254 + __vxtime.tsc_quot) >> 32;
32255 + /* See comment in x86_64 do_gettimeofday. */
32257 + usec += ((readl((void *)fix_to_virt(VSYSCALL_HPET) + 0xf0) -
32258 + __vxtime.last) * __vxtime.quot) >> 32;
32260 + } while (read_seqretry(&__xtime_lock, sequence));
32262 + tv->tv_sec = sec + usec / 1000000;
32263 + tv->tv_usec = usec % 1000000;
32266 +/* RED-PEN may want to readd seq locking, but then the variable should be write-once. */
32267 +static __always_inline void do_get_tz(struct timezone * tz)
32272 +static __always_inline int gettimeofday(struct timeval *tv, struct timezone *tz)
32275 + asm volatile("vsysc2: syscall"
32277 + : "0" (__NR_gettimeofday),"D" (tv),"S" (tz) : __syscall_clobber );
32281 +static __always_inline long time_syscall(long *t)
32284 + asm volatile("vsysc1: syscall"
32286 + : "0" (__NR_time),"D" (t) : __syscall_clobber);
32290 +int __vsyscall(0) vgettimeofday(struct timeval * tv, struct timezone * tz)
32292 + if (!__sysctl_vsyscall)
32293 + return gettimeofday(tv,tz);
32295 + do_vgettimeofday(tv);
32301 +/* This will break when the xtime seconds get inaccurate, but that is
32303 +time_t __vsyscall(1) vtime(time_t *t)
32305 + if (!__sysctl_vsyscall)
32306 + return time_syscall(t);
32308 + *t = __xtime.tv_sec;
32309 + return __xtime.tv_sec;
32312 +long __vsyscall(2) venosys_0(void)
32317 +long __vsyscall(3) venosys_1(void)
32322 +#ifdef CONFIG_SYSCTL
32324 +#define SYSCALL 0x050f
32325 +#define NOP2 0x9090
32328 + * NOP out syscall in vsyscall page when not needed.
32330 +static int vsyscall_sysctl_change(ctl_table *ctl, int write, struct file * filp,
32331 + void __user *buffer, size_t *lenp, loff_t *ppos)
32333 + extern u16 vsysc1, vsysc2;
32334 + u16 *map1, *map2;
32335 + int ret = proc_dointvec(ctl, write, filp, buffer, lenp, ppos);
32338 + /* gcc has some trouble with __va(__pa()), so just do it this
32340 + map1 = ioremap(__pa_symbol(&vsysc1), 2);
32343 + map2 = ioremap(__pa_symbol(&vsysc2), 2);
32348 + if (!sysctl_vsyscall) {
32361 +static int vsyscall_sysctl_nostrat(ctl_table *t, int __user *name, int nlen,
32362 + void __user *oldval, size_t __user *oldlenp,
32363 + void __user *newval, size_t newlen,
32369 +static ctl_table kernel_table2[] = {
32370 + { .ctl_name = 99, .procname = "vsyscall64",
32371 + .data = &sysctl_vsyscall, .maxlen = sizeof(int), .mode = 0644,
32372 + .strategy = vsyscall_sysctl_nostrat,
32373 + .proc_handler = vsyscall_sysctl_change },
32377 +static ctl_table kernel_root_table2[] = {
32378 + { .ctl_name = CTL_KERN, .procname = "kernel", .mode = 0555,
32379 + .child = kernel_table2 },
32385 +static void __init map_vsyscall(void)
32387 + extern char __vsyscall_0;
32388 + unsigned long physaddr_page0 = __pa_symbol(&__vsyscall_0);
32390 + __set_fixmap(VSYSCALL_FIRST_PAGE, physaddr_page0, PAGE_KERNEL_VSYSCALL);
32393 +static int __init vsyscall_init(void)
32395 + BUG_ON(((unsigned long) &vgettimeofday !=
32396 + VSYSCALL_ADDR(__NR_vgettimeofday)));
32397 + BUG_ON((unsigned long) &vtime != VSYSCALL_ADDR(__NR_vtime));
32398 + BUG_ON((VSYSCALL_ADDR(0) != __fix_to_virt(VSYSCALL_FIRST_PAGE)));
32401 + sysctl_vsyscall = 0; /* disable vgettimeofay() */
32403 +#ifdef CONFIG_SYSCTL
32404 + register_sysctl_table(kernel_root_table2, 0);
32409 +__initcall(vsyscall_init);
32410 Index: head-2008-11-25/arch/x86/kernel/xen_entry_64.S
32411 ===================================================================
32412 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
32413 +++ head-2008-11-25/arch/x86/kernel/xen_entry_64.S 2008-04-02 12:34:02.000000000 +0200
32416 + * Copied from arch/xen/i386/kernel/entry.S
32418 +/* Offsets into shared_info_t. */
32419 +#define evtchn_upcall_pending /* 0 */
32420 +#define evtchn_upcall_mask 1
32422 +#define sizeof_vcpu_shift 6
32425 +//#define preempt_disable(reg) incl threadinfo_preempt_count(reg)
32426 +//#define preempt_enable(reg) decl threadinfo_preempt_count(reg)
32427 +#define preempt_disable(reg)
32428 +#define preempt_enable(reg)
32429 +#define XEN_GET_VCPU_INFO(reg) preempt_disable(%rbp) ; \
32430 + movq %gs:pda_cpunumber,reg ; \
32432 + shr $32-sizeof_vcpu_shift,reg ; \
32433 + addq HYPERVISOR_shared_info,reg
32434 +#define XEN_PUT_VCPU_INFO(reg) preempt_enable(%rbp) ; \
32435 +#define XEN_PUT_VCPU_INFO_fixup .byte 0xff,0xff,0xff
32437 +#define XEN_GET_VCPU_INFO(reg) movq HYPERVISOR_shared_info,reg
32438 +#define XEN_PUT_VCPU_INFO(reg)
32439 +#define XEN_PUT_VCPU_INFO_fixup
32442 +#define XEN_LOCKED_BLOCK_EVENTS(reg) movb $1,evtchn_upcall_mask(reg)
32443 +#define XEN_LOCKED_UNBLOCK_EVENTS(reg) movb $0,evtchn_upcall_mask(reg)
32444 +#define XEN_BLOCK_EVENTS(reg) XEN_GET_VCPU_INFO(reg) ; \
32445 + XEN_LOCKED_BLOCK_EVENTS(reg) ; \
32446 + XEN_PUT_VCPU_INFO(reg)
32447 +#define XEN_UNBLOCK_EVENTS(reg) XEN_GET_VCPU_INFO(reg) ; \
32448 + XEN_LOCKED_UNBLOCK_EVENTS(reg) ; \
32449 + XEN_PUT_VCPU_INFO(reg)
32450 +#define XEN_TEST_PENDING(reg) testb $0xFF,evtchn_upcall_pending(reg)
32451 Index: head-2008-11-25/arch/x86/mm/fault_64-xen.c
32452 ===================================================================
32453 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
32454 +++ head-2008-11-25/arch/x86/mm/fault_64-xen.c 2007-11-02 17:34:23.000000000 +0100
32457 + * linux/arch/x86-64/mm/fault.c
32459 + * Copyright (C) 1995 Linus Torvalds
32460 + * Copyright (C) 2001,2002 Andi Kleen, SuSE Labs.
32463 +#include <linux/signal.h>
32464 +#include <linux/sched.h>
32465 +#include <linux/kernel.h>
32466 +#include <linux/errno.h>
32467 +#include <linux/string.h>
32468 +#include <linux/types.h>
32469 +#include <linux/ptrace.h>
32470 +#include <linux/mman.h>
32471 +#include <linux/mm.h>
32472 +#include <linux/smp.h>
32473 +#include <linux/smp_lock.h>
32474 +#include <linux/interrupt.h>
32475 +#include <linux/init.h>
32476 +#include <linux/tty.h>
32477 +#include <linux/vt_kern.h> /* For unblank_screen() */
32478 +#include <linux/compiler.h>
32479 +#include <linux/module.h>
32480 +#include <linux/kprobes.h>
32482 +#include <asm/system.h>
32483 +#include <asm/uaccess.h>
32484 +#include <asm/pgalloc.h>
32485 +#include <asm/smp.h>
32486 +#include <asm/tlbflush.h>
32487 +#include <asm/proto.h>
32488 +#include <asm/kdebug.h>
32489 +#include <asm-generic/sections.h>
32491 +/* Page fault error code bits */
32492 +#define PF_PROT (1<<0) /* or no page found */
32493 +#define PF_WRITE (1<<1)
32494 +#define PF_USER (1<<2)
32495 +#define PF_RSVD (1<<3)
32496 +#define PF_INSTR (1<<4)
32498 +#ifdef CONFIG_KPROBES
32499 +ATOMIC_NOTIFIER_HEAD(notify_page_fault_chain);
32501 +/* Hook to register for page fault notifications */
32502 +int register_page_fault_notifier(struct notifier_block *nb)
32504 + vmalloc_sync_all();
32505 + return atomic_notifier_chain_register(¬ify_page_fault_chain, nb);
32508 +int unregister_page_fault_notifier(struct notifier_block *nb)
32510 + return atomic_notifier_chain_unregister(¬ify_page_fault_chain, nb);
32513 +static inline int notify_page_fault(enum die_val val, const char *str,
32514 + struct pt_regs *regs, long err, int trap, int sig)
32516 + struct die_args args = {
32523 + return atomic_notifier_call_chain(¬ify_page_fault_chain, val, &args);
32526 +static inline int notify_page_fault(enum die_val val, const char *str,
32527 + struct pt_regs *regs, long err, int trap, int sig)
32529 + return NOTIFY_DONE;
32533 +void bust_spinlocks(int yes)
32535 + int loglevel_save = console_loglevel;
32537 + oops_in_progress = 1;
32540 + unblank_screen();
32542 + oops_in_progress = 0;
32544 + * OK, the message is on the console. Now we call printk()
32545 + * without oops_in_progress set so that printk will give klogd
32546 + * a poke. Hold onto your hats...
32548 + console_loglevel = 15; /* NMI oopser may have shut the console up */
32550 + console_loglevel = loglevel_save;
32554 +/* Sometimes the CPU reports invalid exceptions on prefetch.
32555 + Check that here and ignore.
32556 + Opcode checker based on code by Richard Brunner */
32557 +static noinline int is_prefetch(struct pt_regs *regs, unsigned long addr,
32558 + unsigned long error_code)
32560 + unsigned char *instr;
32561 + int scan_more = 1;
32562 + int prefetch = 0;
32563 + unsigned char *max_instr;
32565 + /* If it was a exec fault ignore */
32566 + if (error_code & PF_INSTR)
32569 + instr = (unsigned char *)convert_rip_to_linear(current, regs);
32570 + max_instr = instr + 15;
32572 + if (user_mode(regs) && instr >= (unsigned char *)TASK_SIZE)
32575 + while (scan_more && instr < max_instr) {
32576 + unsigned char opcode;
32577 + unsigned char instr_hi;
32578 + unsigned char instr_lo;
32580 + if (__get_user(opcode, instr))
32583 + instr_hi = opcode & 0xf0;
32584 + instr_lo = opcode & 0x0f;
32587 + switch (instr_hi) {
32590 + /* Values 0x26,0x2E,0x36,0x3E are valid x86
32591 + prefixes. In long mode, the CPU will signal
32592 + invalid opcode if some of these prefixes are
32593 + present so we will never get here anyway */
32594 + scan_more = ((instr_lo & 7) == 0x6);
32598 + /* In AMD64 long mode, 0x40 to 0x4F are valid REX prefixes
32599 + Need to figure out under what instruction mode the
32600 + instruction was issued ... */
32601 + /* Could check the LDT for lm, but for now it's good
32602 + enough to assume that long mode only uses well known
32603 + segments or kernel. */
32604 + scan_more = (!user_mode(regs)) || (regs->cs == __USER_CS);
32608 + /* 0x64 thru 0x67 are valid prefixes in all modes. */
32609 + scan_more = (instr_lo & 0xC) == 0x4;
32612 + /* 0xF0, 0xF2, and 0xF3 are valid prefixes in all modes. */
32613 + scan_more = !instr_lo || (instr_lo>>1) == 1;
32616 + /* Prefetch instruction is 0x0F0D or 0x0F18 */
32618 + if (__get_user(opcode, instr))
32620 + prefetch = (instr_lo == 0xF) &&
32621 + (opcode == 0x0D || opcode == 0x18);
32631 +static int bad_address(void *p)
32633 + unsigned long dummy;
32634 + return __get_user(dummy, (unsigned long *)p);
32637 +void dump_pagetable(unsigned long address)
32644 + pgd = __va(read_cr3() & PHYSICAL_PAGE_MASK);
32645 + pgd += pgd_index(address);
32646 + if (bad_address(pgd)) goto bad;
32647 + printk("PGD %lx ", pgd_val(*pgd));
32648 + if (!pgd_present(*pgd)) goto ret;
32650 + pud = pud_offset(pgd, address);
32651 + if (bad_address(pud)) goto bad;
32652 + printk("PUD %lx ", pud_val(*pud));
32653 + if (!pud_present(*pud)) goto ret;
32655 + pmd = pmd_offset(pud, address);
32656 + if (bad_address(pmd)) goto bad;
32657 + printk("PMD %lx ", pmd_val(*pmd));
32658 + if (!pmd_present(*pmd)) goto ret;
32660 + pte = pte_offset_kernel(pmd, address);
32661 + if (bad_address(pte)) goto bad;
32662 + printk("PTE %lx", pte_val(*pte));
32670 +static const char errata93_warning[] =
32671 +KERN_ERR "******* Your BIOS seems to not contain a fix for K8 errata #93\n"
32672 +KERN_ERR "******* Working around it, but it may cause SEGVs or burn power.\n"
32673 +KERN_ERR "******* Please consider a BIOS update.\n"
32674 +KERN_ERR "******* Disabling USB legacy in the BIOS may also help.\n";
32676 +/* Workaround for K8 erratum #93 & buggy BIOS.
32677 + BIOS SMM functions are required to use a specific workaround
32678 + to avoid corruption of the 64bit RIP register on C stepping K8.
32679 + A lot of BIOS that didn't get tested properly miss this.
32680 + The OS sees this as a page fault with the upper 32bits of RIP cleared.
32681 + Try to work around it here.
32682 + Note we only handle faults in kernel here. */
32684 +static int is_errata93(struct pt_regs *regs, unsigned long address)
32686 + static int warned;
32687 + if (address != regs->rip)
32689 + if ((address >> 32) != 0)
32691 + address |= 0xffffffffUL << 32;
32692 + if ((address >= (u64)_stext && address <= (u64)_etext) ||
32693 + (address >= MODULES_VADDR && address <= MODULES_END)) {
32695 + printk(errata93_warning);
32698 + regs->rip = address;
32704 +int unhandled_signal(struct task_struct *tsk, int sig)
32706 + if (tsk->pid == 1)
32708 + if (tsk->ptrace & PT_PTRACED)
32710 + return (tsk->sighand->action[sig-1].sa.sa_handler == SIG_IGN) ||
32711 + (tsk->sighand->action[sig-1].sa.sa_handler == SIG_DFL);
32714 +static noinline void pgtable_bad(unsigned long address, struct pt_regs *regs,
32715 + unsigned long error_code)
32717 + unsigned long flags = oops_begin();
32718 + struct task_struct *tsk;
32720 + printk(KERN_ALERT "%s: Corrupted page table at address %lx\n",
32721 + current->comm, address);
32722 + dump_pagetable(address);
32724 + tsk->thread.cr2 = address;
32725 + tsk->thread.trap_no = 14;
32726 + tsk->thread.error_code = error_code;
32727 + __die("Bad pagetable", regs, error_code);
32729 + do_exit(SIGKILL);
32733 + * Handle a fault on the vmalloc area
32735 + * This assumes no large pages in there.
32737 +static int vmalloc_fault(unsigned long address)
32739 + pgd_t *pgd, *pgd_ref;
32740 + pud_t *pud, *pud_ref;
32741 + pmd_t *pmd, *pmd_ref;
32742 + pte_t *pte, *pte_ref;
32744 + /* Copy kernel mappings over when needed. This can also
32745 + happen within a race in page table update. In the later
32746 + case just flush. */
32748 + /* On Xen the line below does not always work. Needs investigating! */
32749 + /*pgd = pgd_offset(current->mm ?: &init_mm, address);*/
32750 + pgd = __va(read_cr3() & PHYSICAL_PAGE_MASK);
32751 + pgd += pgd_index(address);
32752 + pgd_ref = pgd_offset_k(address);
32753 + if (pgd_none(*pgd_ref))
32755 + if (pgd_none(*pgd))
32756 + set_pgd(pgd, *pgd_ref);
32758 + BUG_ON(pgd_page(*pgd) != pgd_page(*pgd_ref));
32760 + /* Below here mismatches are bugs because these lower tables
32763 + pud = pud_offset(pgd, address);
32764 + pud_ref = pud_offset(pgd_ref, address);
32765 + if (pud_none(*pud_ref))
32767 + if (pud_none(*pud) || pud_page(*pud) != pud_page(*pud_ref))
32769 + pmd = pmd_offset(pud, address);
32770 + pmd_ref = pmd_offset(pud_ref, address);
32771 + if (pmd_none(*pmd_ref))
32773 + if (pmd_none(*pmd) || pmd_page(*pmd) != pmd_page(*pmd_ref))
32775 + pte_ref = pte_offset_kernel(pmd_ref, address);
32776 + if (!pte_present(*pte_ref))
32778 + pte = pte_offset_kernel(pmd, address);
32779 + /* Don't use pte_page here, because the mappings can point
32780 + outside mem_map, and the NUMA hash lookup cannot handle
32782 + if (!pte_present(*pte) || pte_pfn(*pte) != pte_pfn(*pte_ref))
32787 +int page_fault_trace = 0;
32788 +int exception_trace = 1;
32791 +#define MEM_VERBOSE 1
32793 +#ifdef MEM_VERBOSE
32794 +#define MEM_LOG(_f, _a...) \
32795 + printk("fault.c:[%d]-> " _f "\n", \
32796 + __LINE__ , ## _a )
32798 +#define MEM_LOG(_f, _a...) ((void)0)
32801 +static int spurious_fault(struct pt_regs *regs,
32802 + unsigned long address,
32803 + unsigned long error_code)
32811 + /* Faults in hypervisor area are never spurious. */
32812 + if ((address >= HYPERVISOR_VIRT_START) &&
32813 + (address < HYPERVISOR_VIRT_END))
32817 + /* Reserved-bit violation or user access to kernel space? */
32818 + if (error_code & (PF_RSVD|PF_USER))
32821 + pgd = init_mm.pgd + pgd_index(address);
32822 + if (!pgd_present(*pgd))
32825 + pud = pud_offset(pgd, address);
32826 + if (!pud_present(*pud))
32829 + pmd = pmd_offset(pud, address);
32830 + if (!pmd_present(*pmd))
32833 + pte = pte_offset_kernel(pmd, address);
32834 + if (!pte_present(*pte))
32836 + if ((error_code & PF_WRITE) && !pte_write(*pte))
32838 + if ((error_code & PF_INSTR) && (__pte_val(*pte) & _PAGE_NX))
32845 + * This routine handles page faults. It determines the address,
32846 + * and the problem, and then passes it off to one of the appropriate
32849 +asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
32850 + unsigned long error_code)
32852 + struct task_struct *tsk;
32853 + struct mm_struct *mm;
32854 + struct vm_area_struct * vma;
32855 + unsigned long address;
32856 + const struct exception_table_entry *fixup;
32858 + unsigned long flags;
32861 + if (!user_mode(regs))
32862 + error_code &= ~PF_USER; /* means kernel */
32866 + prefetchw(&mm->mmap_sem);
32868 + /* get the address */
32869 + address = current_vcpu_info()->arch.cr2;
32871 + info.si_code = SEGV_MAPERR;
32875 + * We fault-in kernel-space virtual memory on-demand. The
32876 + * 'reference' page table is init_mm.pgd.
32878 + * NOTE! We MUST NOT take any locks for this case. We may
32879 + * be in an interrupt or a critical region, and should
32880 + * only copy the information from the master page table,
32883 + * This verifies that the fault happens in kernel space
32884 + * (error_code & 4) == 0, and that the fault was not a
32885 + * protection error (error_code & 9) == 0.
32887 + if (unlikely(address >= TASK_SIZE64)) {
32889 + * Don't check for the module range here: its PML4
32890 + * is always initialized because it's shared with the main
32891 + * kernel text. Only vmalloc may need PML4 syncups.
32893 + if (!(error_code & (PF_RSVD|PF_USER|PF_PROT)) &&
32894 + ((address >= VMALLOC_START && address < VMALLOC_END))) {
32895 + if (vmalloc_fault(address) >= 0)
32898 + /* Can take a spurious fault if mapping changes R/O -> R/W. */
32899 + if (spurious_fault(regs, address, error_code))
32901 + if (notify_page_fault(DIE_PAGE_FAULT, "page fault", regs, error_code, 14,
32902 + SIGSEGV) == NOTIFY_STOP)
32905 + * Don't take the mm semaphore here. If we fixup a prefetch
32906 + * fault we could otherwise deadlock.
32908 + goto bad_area_nosemaphore;
32911 + if (notify_page_fault(DIE_PAGE_FAULT, "page fault", regs, error_code, 14,
32912 + SIGSEGV) == NOTIFY_STOP)
32915 + if (likely(regs->eflags & X86_EFLAGS_IF))
32916 + local_irq_enable();
32918 + if (unlikely(page_fault_trace))
32919 + printk("pagefault rip:%lx rsp:%lx cs:%lu ss:%lu address %lx error %lx\n",
32920 + regs->rip,regs->rsp,regs->cs,regs->ss,address,error_code);
32922 + if (unlikely(error_code & PF_RSVD))
32923 + pgtable_bad(address, regs, error_code);
32926 + * If we're in an interrupt or have no user
32927 + * context, we must not take the fault..
32929 + if (unlikely(in_atomic() || !mm))
32930 + goto bad_area_nosemaphore;
32933 + /* When running in the kernel we expect faults to occur only to
32934 + * addresses in user space. All other faults represent errors in the
32935 + * kernel and should generate an OOPS. Unfortunatly, in the case of an
32936 + * erroneous fault occurring in a code path which already holds mmap_sem
32937 + * we will deadlock attempting to validate the fault against the
32938 + * address space. Luckily the kernel only validly references user
32939 + * space from well defined areas of code, which are listed in the
32940 + * exceptions table.
32942 + * As the vast majority of faults will be valid we will only perform
32943 + * the source reference check when there is a possibilty of a deadlock.
32944 + * Attempt to lock the address space, if we cannot we then validate the
32945 + * source. If this is invalid we can skip the address space check,
32946 + * thus avoiding the deadlock.
32948 + if (!down_read_trylock(&mm->mmap_sem)) {
32949 + if ((error_code & PF_USER) == 0 &&
32950 + !search_exception_tables(regs->rip))
32951 + goto bad_area_nosemaphore;
32952 + down_read(&mm->mmap_sem);
32955 + vma = find_vma(mm, address);
32958 + if (likely(vma->vm_start <= address))
32960 + if (!(vma->vm_flags & VM_GROWSDOWN))
32962 + if (error_code & 4) {
32963 + /* Allow userspace just enough access below the stack pointer
32964 + * to let the 'enter' instruction work.
32966 + if (address + 65536 + 32 * sizeof(unsigned long) < regs->rsp)
32969 + if (expand_stack(vma, address))
32972 + * Ok, we have a good vm_area for this memory access, so
32973 + * we can handle it..
32976 + info.si_code = SEGV_ACCERR;
32978 + switch (error_code & (PF_PROT|PF_WRITE)) {
32979 + default: /* 3: write, present */
32980 + /* fall through */
32981 + case PF_WRITE: /* write, not present */
32982 + if (!(vma->vm_flags & VM_WRITE))
32986 + case PF_PROT: /* read, present */
32988 + case 0: /* read, not present */
32989 + if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
32994 + * If for any reason at all we couldn't handle the fault,
32995 + * make sure we exit gracefully rather than endlessly redo
32998 + switch (handle_mm_fault(mm, vma, address, write)) {
32999 + case VM_FAULT_MINOR:
33002 + case VM_FAULT_MAJOR:
33005 + case VM_FAULT_SIGBUS:
33008 + goto out_of_memory;
33011 + up_read(&mm->mmap_sem);
33015 + * Something tried to access memory that isn't in our memory map..
33016 + * Fix it, but check if it's kernel or user first..
33019 + up_read(&mm->mmap_sem);
33021 +bad_area_nosemaphore:
33022 + /* User mode accesses just cause a SIGSEGV */
33023 + if (error_code & PF_USER) {
33024 + if (is_prefetch(regs, address, error_code))
33027 + /* Work around K8 erratum #100 K8 in compat mode
33028 + occasionally jumps to illegal addresses >4GB. We
33029 + catch this here in the page fault handler because
33030 + these addresses are not reachable. Just detect this
33031 + case and return. Any code segment in LDT is
33032 + compatibility mode. */
33033 + if ((regs->cs == __USER32_CS || (regs->cs & (1<<2))) &&
33037 + if (exception_trace && unhandled_signal(tsk, SIGSEGV)) {
33039 + "%s%s[%d]: segfault at %016lx rip %016lx rsp %016lx error %lx\n",
33040 + tsk->pid > 1 ? KERN_INFO : KERN_EMERG,
33041 + tsk->comm, tsk->pid, address, regs->rip,
33042 + regs->rsp, error_code);
33045 + tsk->thread.cr2 = address;
33046 + /* Kernel addresses are always protection faults */
33047 + tsk->thread.error_code = error_code | (address >= TASK_SIZE);
33048 + tsk->thread.trap_no = 14;
33049 + info.si_signo = SIGSEGV;
33050 + info.si_errno = 0;
33051 + /* info.si_code has been set above */
33052 + info.si_addr = (void __user *)address;
33053 + force_sig_info(SIGSEGV, &info, tsk);
33059 + /* Are we prepared to handle this kernel fault? */
33060 + fixup = search_exception_tables(regs->rip);
33062 + regs->rip = fixup->fixup;
33067 + * Hall of shame of CPU/BIOS bugs.
33070 + if (is_prefetch(regs, address, error_code))
33073 + if (is_errata93(regs, address))
33077 + * Oops. The kernel tried to access some bad page. We'll have to
33078 + * terminate things with extreme prejudice.
33081 + flags = oops_begin();
33083 + if (address < PAGE_SIZE)
33084 + printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
33086 + printk(KERN_ALERT "Unable to handle kernel paging request");
33087 + printk(" at %016lx RIP: \n" KERN_ALERT,address);
33088 + printk_address(regs->rip);
33089 + dump_pagetable(address);
33090 + tsk->thread.cr2 = address;
33091 + tsk->thread.trap_no = 14;
33092 + tsk->thread.error_code = error_code;
33093 + __die("Oops", regs, error_code);
33094 + /* Executive summary in case the body of the oops scrolled away */
33095 + printk(KERN_EMERG "CR2: %016lx\n", address);
33097 + do_exit(SIGKILL);
33100 + * We ran out of memory, or some other thing happened to us that made
33101 + * us unable to handle the page fault gracefully.
33104 + up_read(&mm->mmap_sem);
33105 + if (current->pid == 1) {
33109 + printk("VM: killing process %s\n", tsk->comm);
33110 + if (error_code & 4)
33111 + do_exit(SIGKILL);
33115 + up_read(&mm->mmap_sem);
33117 + /* Kernel mode? Handle exceptions or die */
33118 + if (!(error_code & PF_USER))
33121 + tsk->thread.cr2 = address;
33122 + tsk->thread.error_code = error_code;
33123 + tsk->thread.trap_no = 14;
33124 + info.si_signo = SIGBUS;
33125 + info.si_errno = 0;
33126 + info.si_code = BUS_ADRERR;
33127 + info.si_addr = (void __user *)address;
33128 + force_sig_info(SIGBUS, &info, tsk);
33132 +DEFINE_SPINLOCK(pgd_lock);
33133 +struct page *pgd_list;
33135 +void vmalloc_sync_all(void)
33137 + /* Note that races in the updates of insync and start aren't
33139 + insync can only get set bits added, and updates to start are only
33140 + improving performance (without affecting correctness if undone). */
33141 + static DECLARE_BITMAP(insync, PTRS_PER_PGD);
33142 + static unsigned long start = VMALLOC_START & PGDIR_MASK;
33143 + unsigned long address;
33145 + for (address = start; address <= VMALLOC_END; address += PGDIR_SIZE) {
33146 + if (!test_bit(pgd_index(address), insync)) {
33147 + const pgd_t *pgd_ref = pgd_offset_k(address);
33148 + struct page *page;
33150 + if (pgd_none(*pgd_ref))
33152 + spin_lock(&pgd_lock);
33153 + for (page = pgd_list; page;
33154 + page = (struct page *)page->index) {
33156 + pgd = (pgd_t *)page_address(page) + pgd_index(address);
33157 + if (pgd_none(*pgd))
33158 + set_pgd(pgd, *pgd_ref);
33160 + BUG_ON(pgd_page(*pgd) != pgd_page(*pgd_ref));
33162 + spin_unlock(&pgd_lock);
33163 + set_bit(pgd_index(address), insync);
33165 + if (address == start)
33166 + start = address + PGDIR_SIZE;
33168 + /* Check that there is no need to do the same for the modules area. */
33169 + BUILD_BUG_ON(!(MODULES_VADDR > __START_KERNEL));
33170 + BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) ==
33171 + (__START_KERNEL & PGDIR_MASK)));
33174 +static int __init enable_pagefaulttrace(char *str)
33176 + page_fault_trace = 1;
33179 +__setup("pagefaulttrace", enable_pagefaulttrace);
33180 Index: head-2008-11-25/arch/x86/mm/init_64-xen.c
33181 ===================================================================
33182 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
33183 +++ head-2008-11-25/arch/x86/mm/init_64-xen.c 2008-10-29 09:55:56.000000000 +0100
33186 + * linux/arch/x86_64/mm/init.c
33188 + * Copyright (C) 1995 Linus Torvalds
33189 + * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
33190 + * Copyright (C) 2002,2003 Andi Kleen <ak@suse.de>
33192 + * Jun Nakajima <jun.nakajima@intel.com>
33193 + * Modified for Xen.
33196 +#include <linux/signal.h>
33197 +#include <linux/sched.h>
33198 +#include <linux/kernel.h>
33199 +#include <linux/errno.h>
33200 +#include <linux/string.h>
33201 +#include <linux/types.h>
33202 +#include <linux/ptrace.h>
33203 +#include <linux/mman.h>
33204 +#include <linux/mm.h>
33205 +#include <linux/swap.h>
33206 +#include <linux/smp.h>
33207 +#include <linux/init.h>
33208 +#include <linux/pagemap.h>
33209 +#include <linux/bootmem.h>
33210 +#include <linux/proc_fs.h>
33211 +#include <linux/pci.h>
33212 +#include <linux/poison.h>
33213 +#include <linux/dma-mapping.h>
33214 +#include <linux/module.h>
33215 +#include <linux/memory_hotplug.h>
33217 +#include <asm/processor.h>
33218 +#include <asm/system.h>
33219 +#include <asm/uaccess.h>
33220 +#include <asm/pgtable.h>
33221 +#include <asm/pgalloc.h>
33222 +#include <asm/dma.h>
33223 +#include <asm/fixmap.h>
33224 +#include <asm/e820.h>
33225 +#include <asm/apic.h>
33226 +#include <asm/tlb.h>
33227 +#include <asm/mmu_context.h>
33228 +#include <asm/proto.h>
33229 +#include <asm/smp.h>
33230 +#include <asm/sections.h>
33232 +#include <xen/features.h>
33235 +#define Dprintk(x...)
33238 +struct dma_mapping_ops* dma_ops;
33239 +EXPORT_SYMBOL(dma_ops);
33241 +#if CONFIG_XEN_COMPAT <= 0x030002
33242 +unsigned int __kernel_page_user;
33243 +EXPORT_SYMBOL(__kernel_page_user);
33246 +int after_bootmem;
33248 +static unsigned long dma_reserve __initdata;
33250 +DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
33251 +extern unsigned long start_pfn;
33254 + * Use this until direct mapping is established, i.e. before __va() is
33255 + * available in init_memory_mapping().
33258 +#define addr_to_page(addr, page) \
33259 + (addr) &= PHYSICAL_PAGE_MASK; \
33260 + (page) = ((unsigned long *) ((unsigned long) \
33261 + (((mfn_to_pfn((addr) >> PAGE_SHIFT)) << PAGE_SHIFT) + \
33262 + __START_KERNEL_map)))
33264 +static void __meminit early_make_page_readonly(void *va, unsigned int feature)
33266 + unsigned long addr, _va = (unsigned long)va;
33267 + pte_t pte, *ptep;
33268 + unsigned long *page = (unsigned long *) init_level4_pgt;
33270 + BUG_ON(after_bootmem);
33272 + if (xen_feature(feature))
33275 + addr = (unsigned long) page[pgd_index(_va)];
33276 + addr_to_page(addr, page);
33278 + addr = page[pud_index(_va)];
33279 + addr_to_page(addr, page);
33281 + addr = page[pmd_index(_va)];
33282 + addr_to_page(addr, page);
33284 + ptep = (pte_t *) &page[pte_index(_va)];
33286 + pte.pte = ptep->pte & ~_PAGE_RW;
33287 + if (HYPERVISOR_update_va_mapping(_va, pte, 0))
33291 +static void __make_page_readonly(void *va)
33293 + pgd_t *pgd; pud_t *pud; pmd_t *pmd; pte_t pte, *ptep;
33294 + unsigned long addr = (unsigned long) va;
33296 + pgd = pgd_offset_k(addr);
33297 + pud = pud_offset(pgd, addr);
33298 + pmd = pmd_offset(pud, addr);
33299 + ptep = pte_offset_kernel(pmd, addr);
33301 + pte.pte = ptep->pte & ~_PAGE_RW;
33302 + if (HYPERVISOR_update_va_mapping(addr, pte, 0))
33303 + xen_l1_entry_update(ptep, pte); /* fallback */
33305 + if ((addr >= VMALLOC_START) && (addr < VMALLOC_END))
33306 + __make_page_readonly(__va(pte_pfn(pte) << PAGE_SHIFT));
33309 +static void __make_page_writable(void *va)
33311 + pgd_t *pgd; pud_t *pud; pmd_t *pmd; pte_t pte, *ptep;
33312 + unsigned long addr = (unsigned long) va;
33314 + pgd = pgd_offset_k(addr);
33315 + pud = pud_offset(pgd, addr);
33316 + pmd = pmd_offset(pud, addr);
33317 + ptep = pte_offset_kernel(pmd, addr);
33319 + pte.pte = ptep->pte | _PAGE_RW;
33320 + if (HYPERVISOR_update_va_mapping(addr, pte, 0))
33321 + xen_l1_entry_update(ptep, pte); /* fallback */
33323 + if ((addr >= VMALLOC_START) && (addr < VMALLOC_END))
33324 + __make_page_writable(__va(pte_pfn(pte) << PAGE_SHIFT));
33327 +void make_page_readonly(void *va, unsigned int feature)
33329 + if (!xen_feature(feature))
33330 + __make_page_readonly(va);
33333 +void make_page_writable(void *va, unsigned int feature)
33335 + if (!xen_feature(feature))
33336 + __make_page_writable(va);
33339 +void make_pages_readonly(void *va, unsigned nr, unsigned int feature)
33341 + if (xen_feature(feature))
33344 + while (nr-- != 0) {
33345 + __make_page_readonly(va);
33346 + va = (void*)((unsigned long)va + PAGE_SIZE);
33350 +void make_pages_writable(void *va, unsigned nr, unsigned int feature)
33352 + if (xen_feature(feature))
33355 + while (nr-- != 0) {
33356 + __make_page_writable(va);
33357 + va = (void*)((unsigned long)va + PAGE_SIZE);
33362 + * NOTE: pagetable_init alloc all the fixmap pagetables contiguous on the
33363 + * physical space so we can cache the place of the first one and move
33364 + * around without checking the pgd every time.
33367 +void show_mem(void)
33369 + long i, total = 0, reserved = 0;
33370 + long shared = 0, cached = 0;
33371 + pg_data_t *pgdat;
33372 + struct page *page;
33374 + printk(KERN_INFO "Mem-info:\n");
33375 + show_free_areas();
33376 + printk(KERN_INFO "Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
33378 + for_each_online_pgdat(pgdat) {
33379 + for (i = 0; i < pgdat->node_spanned_pages; ++i) {
33380 + page = pfn_to_page(pgdat->node_start_pfn + i);
33382 + if (PageReserved(page))
33384 + else if (PageSwapCache(page))
33386 + else if (page_count(page))
33387 + shared += page_count(page) - 1;
33390 + printk(KERN_INFO "%lu pages of RAM\n", total);
33391 + printk(KERN_INFO "%lu reserved pages\n",reserved);
33392 + printk(KERN_INFO "%lu pages shared\n",shared);
33393 + printk(KERN_INFO "%lu pages swap cached\n",cached);
33397 +static __init void *spp_getpage(void)
33400 + if (after_bootmem)
33401 + ptr = (void *) get_zeroed_page(GFP_ATOMIC);
33402 + else if (start_pfn < table_end) {
33403 + ptr = __va(start_pfn << PAGE_SHIFT);
33405 + memset(ptr, 0, PAGE_SIZE);
33407 + ptr = alloc_bootmem_pages(PAGE_SIZE);
33408 + if (!ptr || ((unsigned long)ptr & ~PAGE_MASK))
33409 + panic("set_pte_phys: cannot allocate page data %s\n", after_bootmem?"after bootmem":"");
33411 + Dprintk("spp_getpage %p\n", ptr);
33415 +#define pgd_offset_u(address) (__user_pgd(init_level4_pgt) + pgd_index(address))
33416 +#define pud_offset_u(address) (level3_user_pgt + pud_index(address))
33418 +static __init void set_pte_phys(unsigned long vaddr,
33419 + unsigned long phys, pgprot_t prot, int user_mode)
33424 + pte_t *pte, new_pte;
33426 + Dprintk("set_pte_phys %lx to %lx\n", vaddr, phys);
33428 + pgd = (user_mode ? pgd_offset_u(vaddr) : pgd_offset_k(vaddr));
33429 + if (pgd_none(*pgd)) {
33430 + printk("PGD FIXMAP MISSING, it should be setup in head.S!\n");
33433 + pud = (user_mode ? pud_offset_u(vaddr) : pud_offset(pgd, vaddr));
33434 + if (pud_none(*pud)) {
33435 + pmd = (pmd_t *) spp_getpage();
33436 + make_page_readonly(pmd, XENFEAT_writable_page_tables);
33437 + set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE | _PAGE_USER));
33438 + if (pmd != pmd_offset(pud, 0)) {
33439 + printk("PAGETABLE BUG #01! %p <-> %p\n", pmd, pmd_offset(pud,0));
33443 + pmd = pmd_offset(pud, vaddr);
33444 + if (pmd_none(*pmd)) {
33445 + pte = (pte_t *) spp_getpage();
33446 + make_page_readonly(pte, XENFEAT_writable_page_tables);
33447 + set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE | _PAGE_USER));
33448 + if (pte != pte_offset_kernel(pmd, 0)) {
33449 + printk("PAGETABLE BUG #02!\n");
33453 + if (pgprot_val(prot))
33454 + new_pte = pfn_pte(phys >> PAGE_SHIFT, prot);
33456 + new_pte = __pte(0);
33458 + pte = pte_offset_kernel(pmd, vaddr);
33459 + if (!pte_none(*pte) && __pte_val(new_pte) &&
33460 + __pte_val(*pte) != (__pte_val(new_pte) & __supported_pte_mask))
33462 + set_pte(pte, new_pte);
33465 + * It's enough to flush this one mapping.
33466 + * (PGE mappings get flushed as well)
33468 + __flush_tlb_one(vaddr);
33471 +static __init void set_pte_phys_ma(unsigned long vaddr,
33472 + unsigned long phys, pgprot_t prot)
33477 + pte_t *pte, new_pte;
33479 + Dprintk("set_pte_phys %lx to %lx\n", vaddr, phys);
33481 + pgd = pgd_offset_k(vaddr);
33482 + if (pgd_none(*pgd)) {
33483 + printk("PGD FIXMAP MISSING, it should be setup in head.S!\n");
33486 + pud = pud_offset(pgd, vaddr);
33487 + if (pud_none(*pud)) {
33489 + pmd = (pmd_t *) spp_getpage();
33490 + make_page_readonly(pmd, XENFEAT_writable_page_tables);
33491 + set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE | _PAGE_USER));
33492 + if (pmd != pmd_offset(pud, 0)) {
33493 + printk("PAGETABLE BUG #01! %p <-> %p\n", pmd, pmd_offset(pud,0));
33497 + pmd = pmd_offset(pud, vaddr);
33498 + if (pmd_none(*pmd)) {
33499 + pte = (pte_t *) spp_getpage();
33500 + make_page_readonly(pte, XENFEAT_writable_page_tables);
33501 + set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE | _PAGE_USER));
33502 + if (pte != pte_offset_kernel(pmd, 0)) {
33503 + printk("PAGETABLE BUG #02!\n");
33507 + new_pte = pfn_pte_ma(phys >> PAGE_SHIFT, prot);
33509 + pte = pte_offset_kernel(pmd, vaddr);
33510 + if (!pte_none(*pte) && __pte_val(new_pte) &&
33511 +#ifdef CONFIG_ACPI
33512 + /* __acpi_map_table() fails to properly call clear_fixmap() */
33513 + (vaddr < __fix_to_virt(FIX_ACPI_END) ||
33514 + vaddr > __fix_to_virt(FIX_ACPI_BEGIN)) &&
33516 + __pte_val(*pte) != (__pte_val(new_pte) & __supported_pte_mask))
33518 + set_pte(pte, new_pte);
33521 + * It's enough to flush this one mapping.
33522 + * (PGE mappings get flushed as well)
33524 + __flush_tlb_one(vaddr);
33527 +/* NOTE: this is meant to be run only at boot */
33529 +__set_fixmap (enum fixed_addresses idx, unsigned long phys, pgprot_t prot)
33531 + unsigned long address = __fix_to_virt(idx);
33533 + if (idx >= __end_of_fixed_addresses) {
33534 + printk("Invalid __set_fixmap\n");
33538 + case VSYSCALL_LAST_PAGE ... VSYSCALL_FIRST_PAGE:
33539 + set_pte_phys(address, phys, prot, 0);
33540 + set_pte_phys(address, phys, prot, 1);
33543 + set_pte_phys_ma(address, phys, prot);
33548 +unsigned long __initdata table_start, table_end;
33550 +static __meminit void *alloc_static_page(unsigned long *phys)
33552 + unsigned long va = (start_pfn << PAGE_SHIFT) + __START_KERNEL_map;
33554 + if (after_bootmem) {
33555 + void *adr = (void *)get_zeroed_page(GFP_ATOMIC);
33557 + *phys = __pa(adr);
33561 + *phys = start_pfn << PAGE_SHIFT;
33563 + memset((void *)va, 0, PAGE_SIZE);
33564 + return (void *)va;
33567 +#define PTE_SIZE PAGE_SIZE
33569 +static inline int make_readonly(unsigned long paddr)
33571 + extern char __vsyscall_0;
33572 + int readonly = 0;
33574 + /* Make new page tables read-only. */
33575 + if (!xen_feature(XENFEAT_writable_page_tables)
33576 + && (paddr >= (table_start << PAGE_SHIFT))
33577 + && (paddr < (table_end << PAGE_SHIFT)))
33579 + /* Make old page tables read-only. */
33580 + if (!xen_feature(XENFEAT_writable_page_tables)
33581 + && (paddr >= (xen_start_info->pt_base - __START_KERNEL_map))
33582 + && (paddr < (start_pfn << PAGE_SHIFT)))
33586 + * No need for writable mapping of kernel image. This also ensures that
33587 + * page and descriptor tables embedded inside don't have writable
33588 + * mappings. Exclude the vsyscall area here, allowing alternative
33589 + * instruction patching to work.
33591 + if ((paddr >= __pa_symbol(&_text)) && (paddr < __pa_symbol(&_end))
33592 + && !(paddr >= __pa_symbol(&__vsyscall_0)
33593 + && paddr < __pa_symbol(&__vsyscall_0) + PAGE_SIZE))
33599 +#ifndef CONFIG_XEN
33600 +/* Must run before zap_low_mappings */
33601 +__init void *early_ioremap(unsigned long addr, unsigned long size)
33603 + unsigned long map = round_down(addr, LARGE_PAGE_SIZE);
33605 + /* actually usually some more */
33606 + if (size >= LARGE_PAGE_SIZE) {
33607 + printk("SMBIOS area too long %lu\n", size);
33610 + set_pmd(temp_mappings[0].pmd, __pmd(map | _KERNPG_TABLE | _PAGE_PSE));
33611 + map += LARGE_PAGE_SIZE;
33612 + set_pmd(temp_mappings[1].pmd, __pmd(map | _KERNPG_TABLE | _PAGE_PSE));
33614 + return temp_mappings[0].address + (addr & (LARGE_PAGE_SIZE-1));
33617 +/* To avoid virtual aliases later */
33618 +__init void early_iounmap(void *addr, unsigned long size)
33620 + if ((void *)round_down((unsigned long)addr, LARGE_PAGE_SIZE) != temp_mappings[0].address)
33621 + printk("early_iounmap: bad address %p\n", addr);
33622 + set_pmd(temp_mappings[0].pmd, __pmd(0));
33623 + set_pmd(temp_mappings[1].pmd, __pmd(0));
33628 +static void __meminit
33629 +phys_pmd_init(pmd_t *pmd, unsigned long address, unsigned long end)
33633 + for (i = 0; i < PTRS_PER_PMD; pmd++, i++) {
33634 + unsigned long pte_phys;
33635 + pte_t *pte, *pte_save;
33637 + if (address >= end)
33639 + pte = alloc_static_page(&pte_phys);
33641 + for (k = 0; k < PTRS_PER_PTE; pte++, k++, address += PTE_SIZE) {
33642 + unsigned long pteval = address | _PAGE_NX | _KERNPG_TABLE;
33644 + if (address >= (after_bootmem
33646 + : xen_start_info->nr_pages << PAGE_SHIFT))
33648 + else if (make_readonly(address))
33649 + pteval &= ~_PAGE_RW;
33650 + set_pte(pte, __pte(pteval & __supported_pte_mask));
33652 + if (!after_bootmem) {
33653 + early_make_page_readonly(pte_save, XENFEAT_writable_page_tables);
33654 + *pmd = __pmd(pte_phys | _KERNPG_TABLE);
33656 + make_page_readonly(pte_save, XENFEAT_writable_page_tables);
33657 + set_pmd(pmd, __pmd(pte_phys | _KERNPG_TABLE));
33662 +static void __meminit
33663 +phys_pmd_update(pud_t *pud, unsigned long address, unsigned long end)
33665 + pmd_t *pmd = pmd_offset(pud, (unsigned long)__va(address));
33667 + if (pmd_none(*pmd)) {
33668 + spin_lock(&init_mm.page_table_lock);
33669 + phys_pmd_init(pmd, address, end);
33670 + spin_unlock(&init_mm.page_table_lock);
33671 + __flush_tlb_all();
33675 +static void __meminit phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
33677 + long i = pud_index(address);
33681 + if (after_bootmem && pud_val(*pud)) {
33682 + phys_pmd_update(pud, address, end);
33686 + for (; i < PTRS_PER_PUD; pud++, i++) {
33687 + unsigned long paddr, pmd_phys;
33690 + paddr = (address & PGDIR_MASK) + i*PUD_SIZE;
33691 + if (paddr >= end)
33694 + pmd = alloc_static_page(&pmd_phys);
33696 + spin_lock(&init_mm.page_table_lock);
33697 + *pud = __pud(pmd_phys | _KERNPG_TABLE);
33698 + phys_pmd_init(pmd, paddr, end);
33699 + spin_unlock(&init_mm.page_table_lock);
33701 + early_make_page_readonly(pmd, XENFEAT_writable_page_tables);
33706 +void __init xen_init_pt(void)
33708 + unsigned long addr, *page;
33710 + /* Find the initial pte page that was built for us. */
33711 + page = (unsigned long *)xen_start_info->pt_base;
33712 + addr = page[pgd_index(__START_KERNEL_map)];
33713 + addr_to_page(addr, page);
33714 + addr = page[pud_index(__START_KERNEL_map)];
33715 + addr_to_page(addr, page);
33717 +#if CONFIG_XEN_COMPAT <= 0x030002
33718 + /* On Xen 3.0.2 and older we may need to explicitly specify _PAGE_USER
33719 + in kernel PTEs. We check that here. */
33720 + if (HYPERVISOR_xen_version(XENVER_version, NULL) <= 0x30000) {
33721 + unsigned long *pg;
33724 + /* Mess with the initial mapping of page 0. It's not needed. */
33725 + BUILD_BUG_ON(__START_KERNEL <= __START_KERNEL_map);
33726 + addr = page[pmd_index(__START_KERNEL_map)];
33727 + addr_to_page(addr, pg);
33728 + pte.pte = pg[pte_index(__START_KERNEL_map)];
33729 + BUG_ON(!(pte.pte & _PAGE_PRESENT));
33731 + /* If _PAGE_USER isn't set, we obviously do not need it. */
33732 + if (pte.pte & _PAGE_USER) {
33733 + /* _PAGE_USER is needed, but is it set implicitly? */
33734 + pte.pte &= ~_PAGE_USER;
33735 + if ((HYPERVISOR_update_va_mapping(__START_KERNEL_map,
33737 + !(pg[pte_index(__START_KERNEL_map)] & _PAGE_USER))
33738 + /* We need to explicitly specify _PAGE_USER. */
33739 + __kernel_page_user = _PAGE_USER;
33744 + /* Construct mapping of initial pte page in our own directories. */
33745 + init_level4_pgt[pgd_index(__START_KERNEL_map)] =
33746 + __pgd(__pa_symbol(level3_kernel_pgt) | _PAGE_TABLE);
33747 + level3_kernel_pgt[pud_index(__START_KERNEL_map)] =
33748 + __pud(__pa_symbol(level2_kernel_pgt) | _PAGE_TABLE);
33749 + memcpy(level2_kernel_pgt, page, PAGE_SIZE);
33751 + __user_pgd(init_level4_pgt)[pgd_index(VSYSCALL_START)] =
33752 + __pgd(__pa_symbol(level3_user_pgt) | _PAGE_TABLE);
33754 + early_make_page_readonly(init_level4_pgt,
33755 + XENFEAT_writable_page_tables);
33756 + early_make_page_readonly(__user_pgd(init_level4_pgt),
33757 + XENFEAT_writable_page_tables);
33758 + early_make_page_readonly(level3_kernel_pgt,
33759 + XENFEAT_writable_page_tables);
33760 + early_make_page_readonly(level3_user_pgt,
33761 + XENFEAT_writable_page_tables);
33762 + early_make_page_readonly(level2_kernel_pgt,
33763 + XENFEAT_writable_page_tables);
33765 + if (!xen_feature(XENFEAT_writable_page_tables)) {
33766 + xen_pgd_pin(__pa_symbol(init_level4_pgt));
33767 + xen_pgd_pin(__pa_symbol(__user_pgd(init_level4_pgt)));
33771 +static void __init extend_init_mapping(unsigned long tables_space)
33773 + unsigned long va = __START_KERNEL_map;
33774 + unsigned long phys, addr, *pte_page;
33776 + pte_t *pte, new_pte;
33777 + unsigned long *page = (unsigned long *)init_level4_pgt;
33779 + addr = page[pgd_index(va)];
33780 + addr_to_page(addr, page);
33781 + addr = page[pud_index(va)];
33782 + addr_to_page(addr, page);
33784 + /* Kill mapping of low 1MB. */
33785 + while (va < (unsigned long)&_text) {
33786 + if (HYPERVISOR_update_va_mapping(va, __pte_ma(0), 0))
33791 + /* Ensure init mappings cover kernel text/data and initial tables. */
33792 + while (va < (__START_KERNEL_map
33793 + + (start_pfn << PAGE_SHIFT)
33794 + + tables_space)) {
33795 + pmd = (pmd_t *)&page[pmd_index(va)];
33796 + if (pmd_none(*pmd)) {
33797 + pte_page = alloc_static_page(&phys);
33798 + early_make_page_readonly(
33799 + pte_page, XENFEAT_writable_page_tables);
33800 + set_pmd(pmd, __pmd(phys | _KERNPG_TABLE));
33802 + addr = page[pmd_index(va)];
33803 + addr_to_page(addr, pte_page);
33805 + pte = (pte_t *)&pte_page[pte_index(va)];
33806 + if (pte_none(*pte)) {
33807 + new_pte = pfn_pte(
33808 + (va - __START_KERNEL_map) >> PAGE_SHIFT,
33809 + __pgprot(_KERNPG_TABLE));
33810 + xen_l1_entry_update(pte, new_pte);
33815 + /* Finally, blow away any spurious initial mappings. */
33817 + pmd = (pmd_t *)&page[pmd_index(va)];
33818 + if (pmd_none(*pmd))
33820 + if (HYPERVISOR_update_va_mapping(va, __pte_ma(0), 0))
33826 +static void __init find_early_table_space(unsigned long end)
33828 + unsigned long puds, pmds, ptes, tables;
33830 + puds = (end + PUD_SIZE - 1) >> PUD_SHIFT;
33831 + pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT;
33832 + ptes = (end + PTE_SIZE - 1) >> PAGE_SHIFT;
33834 + tables = round_up(puds * 8, PAGE_SIZE) +
33835 + round_up(pmds * 8, PAGE_SIZE) +
33836 + round_up(ptes * 8, PAGE_SIZE);
33838 + extend_init_mapping(tables);
33840 + table_start = start_pfn;
33841 + table_end = table_start + (tables>>PAGE_SHIFT);
33843 + early_printk("kernel direct mapping tables up to %lx @ %lx-%lx\n",
33844 + end, table_start << PAGE_SHIFT,
33845 + (table_start << PAGE_SHIFT) + tables);
33848 +static void xen_finish_init_mapping(void)
33850 + unsigned long i, start, end;
33852 + /* Re-vector virtual addresses pointing into the initial
33853 + mapping to the just-established permanent ones. */
33854 + xen_start_info = __va(__pa(xen_start_info));
33855 + xen_start_info->pt_base = (unsigned long)
33856 + __va(__pa(xen_start_info->pt_base));
33857 + if (!xen_feature(XENFEAT_auto_translated_physmap)) {
33858 + phys_to_machine_mapping =
33859 + __va(__pa(xen_start_info->mfn_list));
33860 + xen_start_info->mfn_list = (unsigned long)
33861 + phys_to_machine_mapping;
33863 + if (xen_start_info->mod_start)
33864 + xen_start_info->mod_start = (unsigned long)
33865 + __va(__pa(xen_start_info->mod_start));
33867 + /* Destroy the Xen-created mappings beyond the kernel image as
33868 + * well as the temporary mappings created above. Prevents
33869 + * overlap with modules area (if init mapping is very big).
33871 + start = PAGE_ALIGN((unsigned long)_end);
33872 + end = __START_KERNEL_map + (table_end << PAGE_SHIFT);
33873 + for (; start < end; start += PAGE_SIZE)
33874 + if (HYPERVISOR_update_va_mapping(start, __pte_ma(0), 0))
33877 + /* Allocate pte's for initial fixmaps from 'start_pfn' allocator. */
33878 + table_end = ~0UL;
33881 + * Prefetch pte's for the bt_ioremap() area. It gets used before the
33882 + * boot-time allocator is online, so allocate-on-demand would fail.
33884 + for (i = FIX_BTMAP_END; i <= FIX_BTMAP_BEGIN; i++)
33885 + __set_fixmap(i, 0, __pgprot(0));
33887 + /* Switch to the real shared_info page, and clear the dummy page. */
33888 + set_fixmap(FIX_SHARED_INFO, xen_start_info->shared_info);
33889 + HYPERVISOR_shared_info = (shared_info_t *)fix_to_virt(FIX_SHARED_INFO);
33890 + memset(empty_zero_page, 0, sizeof(empty_zero_page));
33892 + /* Set up mapping of lowest 1MB of physical memory. */
33893 + for (i = 0; i < NR_FIX_ISAMAPS; i++)
33894 + if (is_initial_xendomain())
33895 + set_fixmap(FIX_ISAMAP_BEGIN - i, i * PAGE_SIZE);
33897 + __set_fixmap(FIX_ISAMAP_BEGIN - i,
33898 + virt_to_mfn(empty_zero_page)
33902 + /* Disable the 'start_pfn' allocator. */
33903 + table_end = start_pfn;
33906 +/* Setup the direct mapping of the physical memory at PAGE_OFFSET.
33907 + This runs before bootmem is initialized and gets pages directly from the
33908 + physical memory. To access them they are temporarily mapped. */
33909 +void __meminit init_memory_mapping(unsigned long start, unsigned long end)
33911 + unsigned long next;
33913 + Dprintk("init_memory_mapping\n");
33916 + * Find space for the kernel direct mapping tables.
33917 + * Later we should allocate these tables in the local node of the memory
33918 + * mapped. Unfortunately this is done currently before the nodes are
33921 + if (!after_bootmem)
33922 + find_early_table_space(end);
33924 + start = (unsigned long)__va(start);
33925 + end = (unsigned long)__va(end);
33927 + for (; start < end; start = next) {
33928 + unsigned long pud_phys;
33929 + pgd_t *pgd = pgd_offset_k(start);
33932 + if (after_bootmem)
33933 + pud = pud_offset(pgd, start & PGDIR_MASK);
33935 + pud = alloc_static_page(&pud_phys);
33936 + next = start + PGDIR_SIZE;
33939 + phys_pud_init(pud, __pa(start), __pa(next));
33940 + if (!after_bootmem) {
33941 + early_make_page_readonly(pud, XENFEAT_writable_page_tables);
33942 + set_pgd(pgd_offset_k(start), mk_kernel_pgd(pud_phys));
33946 + if (!after_bootmem) {
33947 + BUG_ON(start_pfn != table_end);
33948 + xen_finish_init_mapping();
33951 + __flush_tlb_all();
33954 +void __cpuinit zap_low_mappings(int cpu)
33956 + /* this is not required for Xen */
33958 + swap_low_mappings();
33962 +/* Compute zone sizes for the DMA and DMA32 zones in a node. */
33964 +size_zones(unsigned long *z, unsigned long *h,
33965 + unsigned long start_pfn, unsigned long end_pfn)
33970 + for (i = 0; i < MAX_NR_ZONES; i++)
33973 + if (start_pfn < MAX_DMA_PFN)
33974 + z[ZONE_DMA] = MAX_DMA_PFN - start_pfn;
33975 + if (start_pfn < MAX_DMA32_PFN) {
33976 + unsigned long dma32_pfn = MAX_DMA32_PFN;
33977 + if (dma32_pfn > end_pfn)
33978 + dma32_pfn = end_pfn;
33979 + z[ZONE_DMA32] = dma32_pfn - start_pfn;
33981 + z[ZONE_NORMAL] = end_pfn - start_pfn;
33983 + /* Remove lower zones from higher ones. */
33985 + for (i = 0; i < MAX_NR_ZONES; i++) {
33991 + /* Compute holes */
33993 + for (i = 0; i < MAX_NR_ZONES; i++) {
33994 + unsigned long s = w;
33996 + h[i] = e820_hole_size(s, w);
33999 + /* Add the space pace needed for mem_map to the holes too. */
34000 + for (i = 0; i < MAX_NR_ZONES; i++)
34001 + h[i] += (z[i] * sizeof(struct page)) / PAGE_SIZE;
34003 + /* The 16MB DMA zone has the kernel and other misc mappings.
34004 + Account them too */
34005 + if (h[ZONE_DMA]) {
34006 + h[ZONE_DMA] += dma_reserve;
34007 + if (h[ZONE_DMA] >= z[ZONE_DMA]) {
34008 + printk(KERN_WARNING
34009 + "Kernel too large and filling up ZONE_DMA?\n");
34010 + h[ZONE_DMA] = z[ZONE_DMA];
34015 +#ifndef CONFIG_NUMA
34016 +void __init paging_init(void)
34018 + unsigned long zones[MAX_NR_ZONES], holes[MAX_NR_ZONES];
34020 + memory_present(0, 0, end_pfn);
34022 + size_zones(zones, holes, 0, end_pfn);
34023 + free_area_init_node(0, NODE_DATA(0), zones,
34024 + __pa(PAGE_OFFSET) >> PAGE_SHIFT, holes);
34026 + init_mm.context.pinned = 1;
34030 +/* Unmap a kernel mapping if it exists. This is useful to avoid prefetches
34031 + from the CPU leading to inconsistent cache lines. address and size
34032 + must be aligned to 2MB boundaries.
34033 + Does nothing when the mapping doesn't exist. */
34034 +void __init clear_kernel_mapping(unsigned long address, unsigned long size)
34036 + unsigned long end = address + size;
34038 + BUG_ON(address & ~LARGE_PAGE_MASK);
34039 + BUG_ON(size & ~LARGE_PAGE_MASK);
34041 + for (; address < end; address += LARGE_PAGE_SIZE) {
34042 + pgd_t *pgd = pgd_offset_k(address);
34045 + if (pgd_none(*pgd))
34047 + pud = pud_offset(pgd, address);
34048 + if (pud_none(*pud))
34050 + pmd = pmd_offset(pud, address);
34051 + if (!pmd || pmd_none(*pmd))
34053 + if (0 == (__pmd_val(*pmd) & _PAGE_PSE)) {
34054 + /* Could handle this, but it should not happen currently. */
34056 + "clear_kernel_mapping: mapping has been split. will leak memory\n");
34059 + set_pmd(pmd, __pmd(0));
34061 + __flush_tlb_all();
34065 + * Memory hotplug specific functions
34067 +void online_page(struct page *page)
34069 + ClearPageReserved(page);
34070 + init_page_count(page);
34071 + __free_page(page);
34072 + totalram_pages++;
34076 +#ifdef CONFIG_MEMORY_HOTPLUG
34078 + * XXX: memory_add_physaddr_to_nid() is to find node id from physical address
34079 + * via probe interface of sysfs. If acpi notifies hot-add event, then it
34080 + * can tell node id by searching dsdt. But, probe interface doesn't have
34081 + * node id. So, return 0 as node id at this time.
34083 +#ifdef CONFIG_NUMA
34084 +int memory_add_physaddr_to_nid(u64 start)
34091 + * Memory is added always to NORMAL zone. This means you will never get
34092 + * additional DMA/DMA32 memory.
34094 +int arch_add_memory(int nid, u64 start, u64 size)
34096 + struct pglist_data *pgdat = NODE_DATA(nid);
34097 + struct zone *zone = pgdat->node_zones + MAX_NR_ZONES-2;
34098 + unsigned long start_pfn = start >> PAGE_SHIFT;
34099 + unsigned long nr_pages = size >> PAGE_SHIFT;
34102 + ret = __add_pages(zone, start_pfn, nr_pages);
34106 + init_memory_mapping(start, (start + size -1));
34110 + printk("%s: Problem encountered in __add_pages!\n", __func__);
34113 +EXPORT_SYMBOL_GPL(arch_add_memory);
34115 +int remove_memory(u64 start, u64 size)
34119 +EXPORT_SYMBOL_GPL(remove_memory);
34121 +#else /* CONFIG_MEMORY_HOTPLUG */
34123 + * Memory Hotadd without sparsemem. The mem_maps have been allocated in advance,
34124 + * just online the pages.
34126 +int __add_pages(struct zone *z, unsigned long start_pfn, unsigned long nr_pages)
34129 + unsigned long pfn;
34130 + unsigned long total = 0, mem = 0;
34131 + for (pfn = start_pfn; pfn < start_pfn + nr_pages; pfn++) {
34132 + if (pfn_valid(pfn)) {
34133 + online_page(pfn_to_page(pfn));
34140 + z->spanned_pages += total;
34141 + z->present_pages += mem;
34142 + z->zone_pgdat->node_spanned_pages += total;
34143 + z->zone_pgdat->node_present_pages += mem;
34147 +#endif /* CONFIG_MEMORY_HOTPLUG */
34149 +static struct kcore_list kcore_mem, kcore_vmalloc, kcore_kernel, kcore_modules,
34152 +void __init mem_init(void)
34154 + long codesize, reservedpages, datasize, initsize;
34155 + unsigned long pfn;
34157 + pci_iommu_alloc();
34159 + /* How many end-of-memory variables you have, grandma! */
34160 + max_low_pfn = end_pfn;
34161 + max_pfn = end_pfn;
34162 + num_physpages = end_pfn;
34163 + high_memory = (void *) __va(end_pfn * PAGE_SIZE);
34165 + /* clear the zero-page */
34166 + memset(empty_zero_page, 0, PAGE_SIZE);
34168 + reservedpages = 0;
34170 + /* this will put all low memory onto the freelists */
34171 +#ifdef CONFIG_NUMA
34172 + totalram_pages = numa_free_all_bootmem();
34174 + totalram_pages = free_all_bootmem();
34176 + /* XEN: init and count pages outside initial allocation. */
34177 + for (pfn = xen_start_info->nr_pages; pfn < max_pfn; pfn++) {
34178 + ClearPageReserved(pfn_to_page(pfn));
34179 + init_page_count(pfn_to_page(pfn));
34180 + totalram_pages++;
34182 + reservedpages = end_pfn - totalram_pages - e820_hole_size(0, end_pfn);
34184 + after_bootmem = 1;
34186 + codesize = (unsigned long) &_etext - (unsigned long) &_text;
34187 + datasize = (unsigned long) &_edata - (unsigned long) &_etext;
34188 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
34190 + /* Register memory areas for /proc/kcore */
34191 + kclist_add(&kcore_mem, __va(0), max_low_pfn << PAGE_SHIFT);
34192 + kclist_add(&kcore_vmalloc, (void *)VMALLOC_START,
34193 + VMALLOC_END-VMALLOC_START);
34194 + kclist_add(&kcore_kernel, &_stext, _end - _stext);
34195 + kclist_add(&kcore_modules, (void *)MODULES_VADDR, MODULES_LEN);
34196 + kclist_add(&kcore_vsyscall, (void *)VSYSCALL_START,
34197 + VSYSCALL_END - VSYSCALL_START);
34199 + printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, %ldk data, %ldk init)\n",
34200 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
34201 + end_pfn << (PAGE_SHIFT-10),
34203 + reservedpages << (PAGE_SHIFT-10),
34207 +#ifndef CONFIG_XEN
34210 + * Sync boot_level4_pgt mappings with the init_level4_pgt
34211 + * except for the low identity mappings which are already zapped
34212 + * in init_level4_pgt. This sync-up is essential for AP's bringup
34214 + memcpy(boot_level4_pgt+1, init_level4_pgt+1, (PTRS_PER_PGD-1)*sizeof(pgd_t));
34219 +void free_init_pages(char *what, unsigned long begin, unsigned long end)
34221 + unsigned long addr;
34223 + if (begin >= end)
34226 + printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
34227 + for (addr = begin; addr < end; addr += PAGE_SIZE) {
34228 + ClearPageReserved(virt_to_page(addr));
34229 + init_page_count(virt_to_page(addr));
34230 + memset((void *)(addr & ~(PAGE_SIZE-1)),
34231 + POISON_FREE_INITMEM, PAGE_SIZE);
34232 + if (addr >= __START_KERNEL_map) {
34233 + /* make_readonly() reports all kernel addresses. */
34234 + __make_page_writable(__va(__pa(addr)));
34235 + if (HYPERVISOR_update_va_mapping(addr, __pte(0), 0)) {
34236 + pgd_t *pgd = pgd_offset_k(addr);
34237 + pud_t *pud = pud_offset(pgd, addr);
34238 + pmd_t *pmd = pmd_offset(pud, addr);
34239 + pte_t *pte = pte_offset_kernel(pmd, addr);
34241 + xen_l1_entry_update(pte, __pte(0)); /* fallback */
34245 + totalram_pages++;
34249 +void free_initmem(void)
34251 + memset(__initdata_begin, POISON_FREE_INITDATA,
34252 + __initdata_end - __initdata_begin);
34253 + free_init_pages("unused kernel memory",
34254 + (unsigned long)(&__init_begin),
34255 + (unsigned long)(&__init_end));
34258 +#ifdef CONFIG_DEBUG_RODATA
34260 +void mark_rodata_ro(void)
34262 + unsigned long addr = (unsigned long)__start_rodata;
34264 + for (; addr < (unsigned long)__end_rodata; addr += PAGE_SIZE)
34265 + change_page_attr_addr(addr, 1, PAGE_KERNEL_RO);
34267 + printk ("Write protecting the kernel read-only data: %luk\n",
34268 + (__end_rodata - __start_rodata) >> 10);
34271 + * change_page_attr_addr() requires a global_flush_tlb() call after it.
34272 + * We do this after the printk so that if something went wrong in the
34273 + * change, the printk gets out at least to give a better debug hint
34274 + * of who is the culprit.
34276 + global_flush_tlb();
34280 +#ifdef CONFIG_BLK_DEV_INITRD
34281 +void free_initrd_mem(unsigned long start, unsigned long end)
34283 + free_init_pages("initrd memory", start, end);
34287 +void __init reserve_bootmem_generic(unsigned long phys, unsigned len)
34289 + /* Should check here against the e820 map to avoid double free */
34290 +#ifdef CONFIG_NUMA
34291 + int nid = phys_to_nid(phys);
34292 + reserve_bootmem_node(NODE_DATA(nid), phys, len);
34294 + reserve_bootmem(phys, len);
34296 + if (phys+len <= MAX_DMA_PFN*PAGE_SIZE)
34297 + dma_reserve += len / PAGE_SIZE;
34300 +int kern_addr_valid(unsigned long addr)
34302 + unsigned long above = ((long)addr) >> __VIRTUAL_MASK_SHIFT;
34308 + if (above != 0 && above != -1UL)
34311 + pgd = pgd_offset_k(addr);
34312 + if (pgd_none(*pgd))
34315 + pud = pud_offset(pgd, addr);
34316 + if (pud_none(*pud))
34319 + pmd = pmd_offset(pud, addr);
34320 + if (pmd_none(*pmd))
34322 + if (pmd_large(*pmd))
34323 + return pfn_valid(pmd_pfn(*pmd));
34325 + pte = pte_offset_kernel(pmd, addr);
34326 + if (pte_none(*pte))
34328 + return pfn_valid(pte_pfn(*pte));
34331 +#ifdef CONFIG_SYSCTL
34332 +#include <linux/sysctl.h>
34334 +extern int exception_trace, page_fault_trace;
34336 +static ctl_table debug_table2[] = {
34337 + { 99, "exception-trace", &exception_trace, sizeof(int), 0644, NULL,
34342 +static ctl_table debug_root_table2[] = {
34343 + { .ctl_name = CTL_DEBUG, .procname = "debug", .mode = 0555,
34344 + .child = debug_table2 },
34348 +static __init int x8664_sysctl_init(void)
34350 + register_sysctl_table(debug_root_table2, 1);
34353 +__initcall(x8664_sysctl_init);
34356 +/* A pseudo VMAs to allow ptrace access for the vsyscall page. This only
34357 + covers the 64bit vsyscall page now. 32bit has a real VMA now and does
34358 + not need special handling anymore. */
34360 +static struct vm_area_struct gate_vma = {
34361 + .vm_start = VSYSCALL_START,
34362 + .vm_end = VSYSCALL_END,
34363 + .vm_page_prot = PAGE_READONLY
34366 +struct vm_area_struct *get_gate_vma(struct task_struct *tsk)
34368 +#ifdef CONFIG_IA32_EMULATION
34369 + if (test_tsk_thread_flag(tsk, TIF_IA32))
34372 + return &gate_vma;
34375 +int in_gate_area(struct task_struct *task, unsigned long addr)
34377 + struct vm_area_struct *vma = get_gate_vma(task);
34380 + return (addr >= vma->vm_start) && (addr < vma->vm_end);
34383 +/* Use this when you have no reliable task/vma, typically from interrupt
34384 + * context. It is less reliable than using the task's vma and may give
34385 + * false positives.
34387 +int in_gate_area_no_task(unsigned long addr)
34389 + return (addr >= VSYSCALL_START) && (addr < VSYSCALL_END);
34391 Index: head-2008-11-25/arch/x86/mm/pageattr_64-xen.c
34392 ===================================================================
34393 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
34394 +++ head-2008-11-25/arch/x86/mm/pageattr_64-xen.c 2008-07-21 11:00:32.000000000 +0200
34397 + * Copyright 2002 Andi Kleen, SuSE Labs.
34398 + * Thanks to Ben LaHaise for precious feedback.
34401 +#include <linux/mm.h>
34402 +#include <linux/sched.h>
34403 +#include <linux/highmem.h>
34404 +#include <linux/module.h>
34405 +#include <linux/slab.h>
34406 +#include <asm/uaccess.h>
34407 +#include <asm/processor.h>
34408 +#include <asm/tlbflush.h>
34409 +#include <asm/io.h>
34412 +#include <asm/pgalloc.h>
34413 +#include <asm/mmu_context.h>
34415 +LIST_HEAD(mm_unpinned);
34416 +DEFINE_SPINLOCK(mm_unpinned_lock);
34418 +static void _pin_lock(struct mm_struct *mm, int lock) {
34420 + spin_lock(&mm->page_table_lock);
34421 +#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
34422 + /* While mm->page_table_lock protects us against insertions and
34423 + * removals of higher level page table pages, it doesn't protect
34424 + * against updates of pte-s. Such updates, however, require the
34425 + * pte pages to be in consistent state (unpinned+writable or
34426 + * pinned+readonly). The pinning and attribute changes, however
34427 + * cannot be done atomically, which is why such updates must be
34428 + * prevented from happening concurrently.
34429 + * Note that no pte lock can ever elsewhere be acquired nesting
34430 + * with an already acquired one in the same mm, or with the mm's
34431 + * page_table_lock already acquired, as that would break in the
34432 + * non-split case (where all these are actually resolving to the
34433 + * one page_table_lock). Thus acquiring all of them here is not
34434 + * going to result in dead locks, and the order of acquires
34435 + * doesn't matter.
34438 + pgd_t *pgd = mm->pgd;
34441 + for (g = 0; g <= ((TASK_SIZE64-1) / PGDIR_SIZE); g++, pgd++) {
34445 + if (pgd_none(*pgd))
34447 + pud = pud_offset(pgd, 0);
34448 + for (u = 0; u < PTRS_PER_PUD; u++, pud++) {
34452 + if (pud_none(*pud))
34454 + pmd = pmd_offset(pud, 0);
34455 + for (m = 0; m < PTRS_PER_PMD; m++, pmd++) {
34458 + if (pmd_none(*pmd))
34460 + ptl = pte_lockptr(0, pmd);
34464 + spin_unlock(ptl);
34471 + spin_unlock(&mm->page_table_lock);
34473 +#define pin_lock(mm) _pin_lock(mm, 1)
34474 +#define pin_unlock(mm) _pin_lock(mm, 0)
34476 +#define PIN_BATCH 8
34477 +static DEFINE_PER_CPU(multicall_entry_t[PIN_BATCH], pb_mcl);
34479 +static inline unsigned int mm_walk_set_prot(void *pt, pgprot_t flags,
34480 + unsigned int cpu, unsigned int seq)
34482 + struct page *page = virt_to_page(pt);
34483 + unsigned long pfn = page_to_pfn(page);
34485 + MULTI_update_va_mapping(per_cpu(pb_mcl, cpu) + seq,
34486 + (unsigned long)__va(pfn << PAGE_SHIFT),
34487 + pfn_pte(pfn, flags), 0);
34488 + if (unlikely(++seq == PIN_BATCH)) {
34489 + if (unlikely(HYPERVISOR_multicall_check(per_cpu(pb_mcl, cpu),
34490 + PIN_BATCH, NULL)))
34498 +static void mm_walk(struct mm_struct *mm, pgprot_t flags)
34505 + unsigned int cpu, seq;
34506 + multicall_entry_t *mcl;
34512 + * Cannot iterate up to USER_PTRS_PER_PGD as these pagetables may not
34513 + * be the 'current' task's pagetables (e.g., current may be 32-bit,
34514 + * but the pagetables may be for a 64-bit task).
34515 + * Subtracting 1 from TASK_SIZE64 means the loop limit is correct
34516 + * regardless of whether TASK_SIZE64 is a multiple of PGDIR_SIZE.
34518 + for (g = 0, seq = 0; g <= ((TASK_SIZE64-1) / PGDIR_SIZE); g++, pgd++) {
34519 + if (pgd_none(*pgd))
34521 + pud = pud_offset(pgd, 0);
34522 + if (PTRS_PER_PUD > 1) /* not folded */
34523 + seq = mm_walk_set_prot(pud,flags,cpu,seq);
34524 + for (u = 0; u < PTRS_PER_PUD; u++, pud++) {
34525 + if (pud_none(*pud))
34527 + pmd = pmd_offset(pud, 0);
34528 + if (PTRS_PER_PMD > 1) /* not folded */
34529 + seq = mm_walk_set_prot(pmd,flags,cpu,seq);
34530 + for (m = 0; m < PTRS_PER_PMD; m++, pmd++) {
34531 + if (pmd_none(*pmd))
34533 + pte = pte_offset_kernel(pmd,0);
34534 + seq = mm_walk_set_prot(pte,flags,cpu,seq);
34539 + mcl = per_cpu(pb_mcl, cpu);
34540 + if (unlikely(seq > PIN_BATCH - 2)) {
34541 + if (unlikely(HYPERVISOR_multicall_check(mcl, seq, NULL)))
34545 + MULTI_update_va_mapping(mcl + seq,
34546 + (unsigned long)__user_pgd(mm->pgd),
34547 + pfn_pte(virt_to_phys(__user_pgd(mm->pgd))>>PAGE_SHIFT, flags),
34549 + MULTI_update_va_mapping(mcl + seq + 1,
34550 + (unsigned long)mm->pgd,
34551 + pfn_pte(virt_to_phys(mm->pgd)>>PAGE_SHIFT, flags),
34553 + if (unlikely(HYPERVISOR_multicall_check(mcl, seq + 2, NULL)))
34559 +void mm_pin(struct mm_struct *mm)
34561 + if (xen_feature(XENFEAT_writable_page_tables))
34566 + mm_walk(mm, PAGE_KERNEL_RO);
34567 + xen_pgd_pin(__pa(mm->pgd)); /* kernel */
34568 + xen_pgd_pin(__pa(__user_pgd(mm->pgd))); /* user */
34569 + mm->context.pinned = 1;
34570 + spin_lock(&mm_unpinned_lock);
34571 + list_del(&mm->context.unpinned);
34572 + spin_unlock(&mm_unpinned_lock);
34577 +void mm_unpin(struct mm_struct *mm)
34579 + if (xen_feature(XENFEAT_writable_page_tables))
34584 + xen_pgd_unpin(__pa(mm->pgd));
34585 + xen_pgd_unpin(__pa(__user_pgd(mm->pgd)));
34586 + mm_walk(mm, PAGE_KERNEL);
34587 + mm->context.pinned = 0;
34588 + spin_lock(&mm_unpinned_lock);
34589 + list_add(&mm->context.unpinned, &mm_unpinned);
34590 + spin_unlock(&mm_unpinned_lock);
34595 +void mm_pin_all(void)
34597 + if (xen_feature(XENFEAT_writable_page_tables))
34601 + * Allow uninterrupted access to the mm_unpinned list. We don't
34602 + * actually take the mm_unpinned_lock as it is taken inside mm_pin().
34603 + * All other CPUs must be at a safe point (e.g., in stop_machine
34604 + * or offlined entirely).
34606 + preempt_disable();
34607 + while (!list_empty(&mm_unpinned))
34608 + mm_pin(list_entry(mm_unpinned.next, struct mm_struct,
34609 + context.unpinned));
34610 + preempt_enable();
34613 +void _arch_dup_mmap(struct mm_struct *mm)
34615 + if (!mm->context.pinned)
34619 +void _arch_exit_mmap(struct mm_struct *mm)
34621 + struct task_struct *tsk = current;
34626 + * We aggressively remove defunct pgd from cr3. We execute unmap_vmas()
34627 + * *much* faster this way, as no tlb flushes means bigger wrpt batches.
34629 + if (tsk->active_mm == mm) {
34630 + tsk->active_mm = &init_mm;
34631 + atomic_inc(&init_mm.mm_count);
34633 + switch_mm(mm, &init_mm, tsk);
34635 + atomic_dec(&mm->mm_count);
34636 + BUG_ON(atomic_read(&mm->mm_count) == 0);
34639 + task_unlock(tsk);
34641 + if ( mm->context.pinned && (atomic_read(&mm->mm_count) == 1) &&
34642 + !mm->context.has_foreign_mappings )
34646 +struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
34648 + struct page *pte;
34650 + pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
34652 + SetPageForeign(pte, pte_free);
34653 + init_page_count(pte);
34658 +void pte_free(struct page *pte)
34660 + unsigned long va = (unsigned long)__va(page_to_pfn(pte)<<PAGE_SHIFT);
34662 + if (!pte_write(*virt_to_ptep(va)))
34663 + if (HYPERVISOR_update_va_mapping(
34664 + va, pfn_pte(page_to_pfn(pte), PAGE_KERNEL), 0))
34667 + ClearPageForeign(pte);
34668 + init_page_count(pte);
34670 + __free_page(pte);
34672 +#endif /* CONFIG_XEN */
34674 +pte_t *lookup_address(unsigned long address)
34676 + pgd_t *pgd = pgd_offset_k(address);
34680 + if (pgd_none(*pgd))
34682 + pud = pud_offset(pgd, address);
34683 + if (!pud_present(*pud))
34685 + pmd = pmd_offset(pud, address);
34686 + if (!pmd_present(*pmd))
34688 + if (pmd_large(*pmd))
34689 + return (pte_t *)pmd;
34690 + pte = pte_offset_kernel(pmd, address);
34691 + if (pte && !pte_present(*pte))
34696 +static struct page *split_large_page(unsigned long address, pgprot_t prot,
34697 + pgprot_t ref_prot)
34700 + unsigned long addr;
34701 + struct page *base = alloc_pages(GFP_KERNEL, 0);
34706 + * page_private is used to track the number of entries in
34707 + * the page table page have non standard attributes.
34709 + SetPagePrivate(base);
34710 + page_private(base) = 0;
34712 + address = __pa(address);
34713 + addr = address & LARGE_PAGE_MASK;
34714 + pbase = (pte_t *)page_address(base);
34715 + for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE) {
34716 + pbase[i] = pfn_pte(addr >> PAGE_SHIFT,
34717 + addr == address ? prot : ref_prot);
34723 +static void flush_kernel_map(void *address)
34725 + if (0 && address && cpu_has_clflush) {
34726 + /* is this worth it? */
34728 + for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
34729 + asm volatile("clflush (%0)" :: "r" (address + i));
34731 + asm volatile("wbinvd":::"memory");
34733 + __flush_tlb_one(address);
34735 + __flush_tlb_all();
34739 +static inline void flush_map(unsigned long address)
34741 + on_each_cpu(flush_kernel_map, (void *)address, 1, 1);
34744 +static struct page *deferred_pages; /* protected by init_mm.mmap_sem */
34746 +static inline void save_page(struct page *fpage)
34748 + fpage->lru.next = (struct list_head *)deferred_pages;
34749 + deferred_pages = fpage;
34753 + * No more special protections in this 2/4MB area - revert to a
34754 + * large page again.
34756 +static void revert_page(unsigned long address, pgprot_t ref_prot)
34763 + pgd = pgd_offset_k(address);
34764 + BUG_ON(pgd_none(*pgd));
34765 + pud = pud_offset(pgd,address);
34766 + BUG_ON(pud_none(*pud));
34767 + pmd = pmd_offset(pud, address);
34768 + BUG_ON(__pmd_val(*pmd) & _PAGE_PSE);
34769 + pgprot_val(ref_prot) |= _PAGE_PSE;
34770 + large_pte = mk_pte_phys(__pa(address) & LARGE_PAGE_MASK, ref_prot);
34771 + set_pte((pte_t *)pmd, large_pte);
34775 +__change_page_attr(unsigned long address, unsigned long pfn, pgprot_t prot,
34776 + pgprot_t ref_prot)
34779 + struct page *kpte_page;
34780 + unsigned kpte_flags;
34781 + pgprot_t ref_prot2;
34782 + kpte = lookup_address(address);
34783 + if (!kpte) return 0;
34784 + kpte_page = virt_to_page(((unsigned long)kpte) & PAGE_MASK);
34785 + kpte_flags = pte_val(*kpte);
34786 + if (pgprot_val(prot) != pgprot_val(ref_prot)) {
34787 + if ((kpte_flags & _PAGE_PSE) == 0) {
34788 + set_pte(kpte, pfn_pte(pfn, prot));
34791 + * split_large_page will take the reference for this
34792 + * change_page_attr on the split page.
34795 + struct page *split;
34796 + ref_prot2 = __pgprot(pgprot_val(pte_pgprot(*lookup_address(address))) & ~(1<<_PAGE_BIT_PSE));
34798 + split = split_large_page(address, prot, ref_prot2);
34801 + set_pte(kpte,mk_pte(split, ref_prot2));
34802 + kpte_page = split;
34804 + page_private(kpte_page)++;
34805 + } else if ((kpte_flags & _PAGE_PSE) == 0) {
34806 + set_pte(kpte, pfn_pte(pfn, ref_prot));
34807 + BUG_ON(page_private(kpte_page) == 0);
34808 + page_private(kpte_page)--;
34812 + /* on x86-64 the direct mapping set at boot is not using 4k pages */
34814 + * ..., but the XEN guest kernels (currently) do:
34815 + * If the pte was reserved, it means it was created at boot
34816 + * time (not via split_large_page) and in turn we must not
34817 + * replace it with a large page.
34819 +#ifndef CONFIG_XEN
34820 + BUG_ON(PageReserved(kpte_page));
34822 + if (PageReserved(kpte_page))
34826 + if (page_private(kpte_page) == 0) {
34827 + save_page(kpte_page);
34828 + revert_page(address, ref_prot);
34834 + * Change the page attributes of an page in the linear mapping.
34836 + * This should be used when a page is mapped with a different caching policy
34837 + * than write-back somewhere - some CPUs do not like it when mappings with
34838 + * different caching policies exist. This changes the page attributes of the
34839 + * in kernel linear mapping too.
34841 + * The caller needs to ensure that there are no conflicting mappings elsewhere.
34842 + * This function only deals with the kernel linear map.
34844 + * Caller must call global_flush_tlb() after this.
34846 +int change_page_attr_addr(unsigned long address, int numpages, pgprot_t prot)
34851 + down_write(&init_mm.mmap_sem);
34852 + for (i = 0; i < numpages; i++, address += PAGE_SIZE) {
34853 + unsigned long pfn = __pa(address) >> PAGE_SHIFT;
34855 + err = __change_page_attr(address, pfn, prot, PAGE_KERNEL);
34858 + /* Handle kernel mapping too which aliases part of the
34860 + if (__pa(address) < KERNEL_TEXT_SIZE) {
34861 + unsigned long addr2;
34862 + pgprot_t prot2 = prot;
34863 + addr2 = __START_KERNEL_map + __pa(address);
34864 + pgprot_val(prot2) &= ~_PAGE_NX;
34865 + err = __change_page_attr(addr2, pfn, prot2, PAGE_KERNEL_EXEC);
34868 + up_write(&init_mm.mmap_sem);
34872 +/* Don't call this for MMIO areas that may not have a mem_map entry */
34873 +int change_page_attr(struct page *page, int numpages, pgprot_t prot)
34875 + unsigned long addr = (unsigned long)page_address(page);
34876 + return change_page_attr_addr(addr, numpages, prot);
34879 +void global_flush_tlb(void)
34881 + struct page *dpage;
34883 + down_read(&init_mm.mmap_sem);
34884 + dpage = xchg(&deferred_pages, NULL);
34885 + up_read(&init_mm.mmap_sem);
34887 + flush_map((dpage && !dpage->lru.next) ? (unsigned long)page_address(dpage) : 0);
34889 + struct page *tmp = dpage;
34890 + dpage = (struct page *)dpage->lru.next;
34891 + ClearPagePrivate(tmp);
34892 + __free_page(tmp);
34896 +EXPORT_SYMBOL(change_page_attr);
34897 +EXPORT_SYMBOL(global_flush_tlb);
34898 Index: head-2008-11-25/drivers/pci/msi-xen.c
34899 ===================================================================
34900 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
34901 +++ head-2008-11-25/drivers/pci/msi-xen.c 2008-10-13 13:43:45.000000000 +0200
34905 + * Purpose: PCI Message Signaled Interrupt (MSI)
34907 + * Copyright (C) 2003-2004 Intel
34908 + * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
34911 +#include <linux/mm.h>
34912 +#include <linux/irq.h>
34913 +#include <linux/interrupt.h>
34914 +#include <linux/init.h>
34915 +#include <linux/ioport.h>
34916 +#include <linux/smp_lock.h>
34917 +#include <linux/pci.h>
34918 +#include <linux/proc_fs.h>
34920 +#include <xen/evtchn.h>
34922 +#include <asm/errno.h>
34923 +#include <asm/io.h>
34924 +#include <asm/smp.h>
34929 +static int pci_msi_enable = 1;
34931 +static struct msi_ops *msi_ops;
34933 +int msi_register(struct msi_ops *ops)
34939 +static LIST_HEAD(msi_dev_head);
34940 +DEFINE_SPINLOCK(msi_dev_lock);
34942 +struct msi_dev_list {
34943 + struct pci_dev *dev;
34944 + struct list_head list;
34945 + spinlock_t pirq_list_lock;
34946 + struct list_head pirq_list_head;
34949 +struct msi_pirq_entry {
34950 + struct list_head list;
34955 +static struct msi_dev_list *get_msi_dev_pirq_list(struct pci_dev *dev)
34957 + struct msi_dev_list *msi_dev_list, *ret = NULL;
34958 + unsigned long flags;
34960 + spin_lock_irqsave(&msi_dev_lock, flags);
34962 + list_for_each_entry(msi_dev_list, &msi_dev_head, list)
34963 + if ( msi_dev_list->dev == dev )
34964 + ret = msi_dev_list;
34967 + spin_unlock_irqrestore(&msi_dev_lock, flags);
34971 + /* Has not allocate msi_dev until now. */
34972 + ret = kzalloc(sizeof(struct msi_dev_list), GFP_ATOMIC);
34974 + /* Failed to allocate msi_dev structure */
34976 + spin_unlock_irqrestore(&msi_dev_lock, flags);
34981 + spin_lock_init(&ret->pirq_list_lock);
34982 + INIT_LIST_HEAD(&ret->pirq_list_head);
34983 + list_add_tail(&ret->list, &msi_dev_head);
34984 + spin_unlock_irqrestore(&msi_dev_lock, flags);
34988 +static int attach_pirq_entry(int pirq, int entry_nr,
34989 + struct msi_dev_list *msi_dev_entry)
34991 + struct msi_pirq_entry *entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
34992 + unsigned long flags;
34996 + entry->pirq = pirq;
34997 + entry->entry_nr = entry_nr;
34998 + spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
34999 + list_add_tail(&entry->list, &msi_dev_entry->pirq_list_head);
35000 + spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
35004 +static void detach_pirq_entry(int entry_nr,
35005 + struct msi_dev_list *msi_dev_entry)
35007 + unsigned long flags;
35008 + struct msi_pirq_entry *pirq_entry;
35010 + list_for_each_entry(pirq_entry, &msi_dev_entry->pirq_list_head, list) {
35011 + if (pirq_entry->entry_nr == entry_nr) {
35012 + spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
35013 + list_del(&pirq_entry->list);
35014 + spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
35015 + kfree(pirq_entry);
35022 + * pciback will provide device's owner
35024 +static int (*get_owner)(struct pci_dev *dev);
35026 +int register_msi_get_owner(int (*func)(struct pci_dev *dev))
35029 + printk(KERN_WARNING "register msi_get_owner again\n");
35032 + get_owner = func;
35036 +int unregister_msi_get_owner(int (*func)(struct pci_dev *dev))
35038 + if (get_owner != func)
35040 + get_owner = NULL;
35044 +static int msi_get_dev_owner(struct pci_dev *dev)
35048 + BUG_ON(!is_initial_xendomain());
35049 + if (get_owner && (owner = get_owner(dev)) >= 0) {
35050 + printk(KERN_INFO "get owner for dev %x get %x \n",
35051 + dev->devfn, owner);
35055 + return DOMID_SELF;
35058 +static int msi_unmap_pirq(struct pci_dev *dev, int pirq)
35060 + struct physdev_unmap_pirq unmap;
35063 + unmap.domid = msi_get_dev_owner(dev);
35064 + /* See comments in msi_map_pirq_to_vector, input parameter pirq
35065 + * mean irq number only if the device belongs to dom0 itself.
35067 + unmap.pirq = (unmap.domid != DOMID_SELF)
35068 + ? pirq : evtchn_get_xen_pirq(pirq);
35070 + if ((rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap)))
35071 + printk(KERN_WARNING "unmap irq %x failed\n", pirq);
35076 + if (unmap.domid == DOMID_SELF)
35077 + evtchn_map_pirq(pirq, 0);
35082 +static u64 find_table_base(struct pci_dev *dev, int pos)
35086 + unsigned long flags;
35088 + pci_read_config_dword(dev, msix_table_offset_reg(pos), ®);
35089 + bar = reg & PCI_MSIX_FLAGS_BIRMASK;
35091 + flags = pci_resource_flags(dev, bar);
35092 + if (flags & (IORESOURCE_DISABLED | IORESOURCE_UNSET | IORESOURCE_BUSY))
35095 + return pci_resource_start(dev, bar);
35099 + * Protected by msi_lock
35101 +static int msi_map_pirq_to_vector(struct pci_dev *dev, int pirq,
35102 + int entry_nr, u64 table_base)
35104 + struct physdev_map_pirq map_irq;
35106 + domid_t domid = DOMID_SELF;
35108 + domid = msi_get_dev_owner(dev);
35110 + map_irq.domid = domid;
35111 + map_irq.type = MAP_PIRQ_TYPE_MSI;
35112 + map_irq.index = -1;
35113 + map_irq.pirq = pirq < 0 ? -1 : evtchn_get_xen_pirq(pirq);
35114 + map_irq.bus = dev->bus->number;
35115 + map_irq.devfn = dev->devfn;
35116 + map_irq.entry_nr = entry_nr;
35117 + map_irq.table_base = table_base;
35119 + if ((rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq)))
35120 + printk(KERN_WARNING "map irq failed\n");
35124 + /* This happens when MSI support is not enabled in Xen. */
35125 + if (rc == 0 && map_irq.pirq < 0)
35128 + BUG_ON(map_irq.pirq <= 0);
35130 + /* If mapping of this particular MSI is on behalf of another domain,
35131 + * we do not need to get an irq in dom0. This also implies:
35132 + * dev->irq in dom0 will be 'Xen pirq' if this device belongs to
35133 + * to another domain, and will be 'Linux irq' if it belongs to dom0.
35135 + return ((domid != DOMID_SELF) ?
35136 + map_irq.pirq : evtchn_map_pirq(pirq, map_irq.pirq));
35139 +static int msi_map_vector(struct pci_dev *dev, int entry_nr, u64 table_base)
35141 + return msi_map_pirq_to_vector(dev, -1, entry_nr, table_base);
35144 +static int msi_init(void)
35146 + static int status = 0;
35148 + if (pci_msi_quirk) {
35149 + pci_msi_enable = 0;
35150 + printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
35151 + status = -EINVAL;
35157 +void pci_scan_msi_device(struct pci_dev *dev) { }
35159 +void disable_msi_mode(struct pci_dev *dev, int pos, int type)
35163 + pci_read_config_word(dev, msi_control_reg(pos), &control);
35164 + if (type == PCI_CAP_ID_MSI) {
35165 + /* Set enabled bits to single MSI & enable MSI_enable bit */
35166 + msi_disable(control);
35167 + pci_write_config_word(dev, msi_control_reg(pos), control);
35168 + dev->msi_enabled = 0;
35170 + msix_disable(control);
35171 + pci_write_config_word(dev, msi_control_reg(pos), control);
35172 + dev->msix_enabled = 0;
35174 + if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
35175 + /* PCI Express Endpoint device detected */
35176 + pci_intx(dev, 1); /* enable intx */
35180 +static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
35184 + pci_read_config_word(dev, msi_control_reg(pos), &control);
35185 + if (type == PCI_CAP_ID_MSI) {
35186 + /* Set enabled bits to single MSI & enable MSI_enable bit */
35187 + msi_enable(control, 1);
35188 + pci_write_config_word(dev, msi_control_reg(pos), control);
35189 + dev->msi_enabled = 1;
35191 + msix_enable(control);
35192 + pci_write_config_word(dev, msi_control_reg(pos), control);
35193 + dev->msix_enabled = 1;
35195 + if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
35196 + /* PCI Express Endpoint device detected */
35197 + pci_intx(dev, 0); /* disable intx */
35202 +int pci_save_msi_state(struct pci_dev *dev)
35206 + pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
35207 + if (pos <= 0 || dev->no_msi)
35210 + if (!dev->msi_enabled)
35213 + /* Restore dev->irq to its default pin-assertion vector */
35214 + msi_unmap_pirq(dev, dev->irq);
35215 + /* Disable MSI mode */
35216 + disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
35217 + /* Set the flags for use of restore */
35218 + dev->msi_enabled = 1;
35222 +void pci_restore_msi_state(struct pci_dev *dev)
35226 + pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
35230 + if (!dev->msi_enabled)
35233 + pirq = msi_map_pirq_to_vector(dev, dev->irq, 0, 0);
35236 + enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
35239 +int pci_save_msix_state(struct pci_dev *dev)
35242 + unsigned long flags;
35243 + struct msi_dev_list *msi_dev_entry;
35244 + struct msi_pirq_entry *pirq_entry, *tmp;
35246 + pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
35247 + if (pos <= 0 || dev->no_msi)
35250 + /* save the capability */
35251 + if (!dev->msix_enabled)
35254 + msi_dev_entry = get_msi_dev_pirq_list(dev);
35256 + spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
35257 + list_for_each_entry_safe(pirq_entry, tmp,
35258 + &msi_dev_entry->pirq_list_head, list)
35259 + msi_unmap_pirq(dev, pirq_entry->pirq);
35260 + spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
35262 + disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
35263 + /* Set the flags for use of restore */
35264 + dev->msix_enabled = 1;
35269 +void pci_restore_msix_state(struct pci_dev *dev)
35272 + unsigned long flags;
35274 + struct msi_dev_list *msi_dev_entry;
35275 + struct msi_pirq_entry *pirq_entry, *tmp;
35277 + pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
35281 + if (!dev->msix_enabled)
35284 + msi_dev_entry = get_msi_dev_pirq_list(dev);
35285 + table_base = find_table_base(dev, pos);
35289 + spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
35290 + list_for_each_entry_safe(pirq_entry, tmp,
35291 + &msi_dev_entry->pirq_list_head, list) {
35292 + int rc = msi_map_pirq_to_vector(dev, pirq_entry->pirq,
35293 + pirq_entry->entry_nr, table_base);
35295 + printk(KERN_WARNING
35296 + "%s: re-mapping irq #%d (pirq%d) failed: %d\n",
35297 + pci_name(dev), pirq_entry->entry_nr,
35298 + pirq_entry->pirq, rc);
35300 + spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
35302 + enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
35307 + * msi_capability_init - configure device's MSI capability structure
35308 + * @dev: pointer to the pci_dev data structure of MSI device function
35310 + * Setup the MSI capability structure of device function with a single
35311 + * MSI vector, regardless of device function is capable of handling
35312 + * multiple messages. A return of zero indicates the successful setup
35313 + * of an entry zero with the new MSI vector or non-zero for otherwise.
35315 +static int msi_capability_init(struct pci_dev *dev)
35320 + pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
35321 + pci_read_config_word(dev, msi_control_reg(pos), &control);
35323 + pirq = msi_map_vector(dev, 0, 0);
35328 + /* Set MSI enabled bits */
35329 + enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
35330 + dev->msi_enabled = 1;
35336 + * msix_capability_init - configure device's MSI-X capability
35337 + * @dev: pointer to the pci_dev data structure of MSI-X device function
35338 + * @entries: pointer to an array of struct msix_entry entries
35339 + * @nvec: number of @entries
35341 + * Setup the MSI-X capability structure of device function with a
35342 + * single MSI-X vector. A return of zero indicates the successful setup of
35343 + * requested MSI-X entries with allocated vectors or non-zero for otherwise.
35345 +static int msix_capability_init(struct pci_dev *dev,
35346 + struct msix_entry *entries, int nvec)
35349 + int pirq, i, j, mapped, pos;
35350 + struct msi_dev_list *msi_dev_entry = get_msi_dev_pirq_list(dev);
35351 + struct msi_pirq_entry *pirq_entry;
35353 + if (!msi_dev_entry)
35356 + pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
35357 + table_base = find_table_base(dev, pos);
35361 + /* MSI-X Table Initialization */
35362 + for (i = 0; i < nvec; i++) {
35364 + list_for_each_entry(pirq_entry, &msi_dev_entry->pirq_list_head, list) {
35365 + if (pirq_entry->entry_nr == entries[i].entry) {
35366 + printk(KERN_WARNING "msix entry %d for dev %02x:%02x:%01x are \
35367 + not freed before acquire again.\n", entries[i].entry,
35368 + dev->bus->number, PCI_SLOT(dev->devfn),
35369 + PCI_FUNC(dev->devfn));
35370 + (entries + i)->vector = pirq_entry->pirq;
35377 + pirq = msi_map_vector(dev, entries[i].entry, table_base);
35380 + attach_pirq_entry(pirq, entries[i].entry, msi_dev_entry);
35381 + (entries + i)->vector = pirq;
35385 + for (j = --i; j >= 0; j--) {
35386 + msi_unmap_pirq(dev, entries[j].vector);
35387 + detach_pirq_entry(entries[j].entry, msi_dev_entry);
35388 + entries[j].vector = 0;
35393 + enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
35394 + dev->msix_enabled = 1;
35400 + * pci_enable_msi - configure device's MSI capability structure
35401 + * @dev: pointer to the pci_dev data structure of MSI device function
35403 + * Setup the MSI capability structure of device function with
35404 + * a single MSI vector upon its software driver call to request for
35405 + * MSI mode enabled on its hardware device function. A return of zero
35406 + * indicates the successful setup of an entry zero with the new MSI
35407 + * vector or non-zero for otherwise.
35409 +extern int pci_frontend_enable_msi(struct pci_dev *dev);
35410 +int pci_enable_msi(struct pci_dev* dev)
35412 + struct pci_bus *bus;
35413 + int pos, temp, status = -EINVAL;
35415 + if (!pci_msi_enable || !dev)
35421 + for (bus = dev->bus; bus; bus = bus->parent)
35422 + if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
35425 + status = msi_init();
35429 +#ifdef CONFIG_XEN_PCIDEV_FRONTEND
35430 + if (!is_initial_xendomain())
35435 + ret = pci_frontend_enable_msi(dev);
35439 + dev->irq = evtchn_map_pirq(-1, dev->irq);
35440 + dev->irq_old = temp;
35448 + pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
35452 + /* Check whether driver already requested for MSI-X vectors */
35453 + if (dev->msix_enabled) {
35454 + printk(KERN_INFO "PCI: %s: Can't enable MSI. "
35455 + "Device already has MSI-X vectors assigned\n",
35461 + status = msi_capability_init(dev);
35463 + dev->irq_old = temp;
35470 +extern void pci_frontend_disable_msi(struct pci_dev* dev);
35471 +void pci_disable_msi(struct pci_dev* dev)
35476 + if (!pci_msi_enable)
35481 +#ifdef CONFIG_XEN_PCIDEV_FRONTEND
35482 + if (!is_initial_xendomain()) {
35483 + evtchn_map_pirq(dev->irq, 0);
35484 + pci_frontend_disable_msi(dev);
35485 + dev->irq = dev->irq_old;
35490 + pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
35495 + /* Restore dev->irq to its default pin-assertion vector */
35496 + dev->irq = dev->irq_old;
35497 + msi_unmap_pirq(dev, pirq);
35499 + /* Disable MSI mode */
35500 + disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
35504 + * pci_enable_msix - configure device's MSI-X capability structure
35505 + * @dev: pointer to the pci_dev data structure of MSI-X device function
35506 + * @entries: pointer to an array of MSI-X entries
35507 + * @nvec: number of MSI-X vectors requested for allocation by device driver
35509 + * Setup the MSI-X capability structure of device function with the number
35510 + * of requested vectors upon its software driver call to request for
35511 + * MSI-X mode enabled on its hardware device function. A return of zero
35512 + * indicates the successful configuration of MSI-X capability structure
35513 + * with new allocated MSI-X vectors. A return of < 0 indicates a failure.
35514 + * Or a return of > 0 indicates that driver request is exceeding the number
35515 + * of vectors available. Driver should use the returned value to re-send
35518 +extern int pci_frontend_enable_msix(struct pci_dev *dev,
35519 + struct msix_entry *entries, int nvec);
35520 +int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
35522 + struct pci_bus *bus;
35523 + int status, pos, nr_entries;
35527 + if (!pci_msi_enable || !dev || !entries)
35533 + for (bus = dev->bus; bus; bus = bus->parent)
35534 + if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
35537 +#ifdef CONFIG_XEN_PCIDEV_FRONTEND
35538 + if (!is_initial_xendomain()) {
35539 + struct msi_dev_list *msi_dev_entry;
35540 + struct msi_pirq_entry *pirq_entry;
35543 + ret = pci_frontend_enable_msix(dev, entries, nvec);
35545 + printk("get %x from pci_frontend_enable_msix\n", ret);
35549 + msi_dev_entry = get_msi_dev_pirq_list(dev);
35550 + for (i = 0; i < nvec; i++) {
35553 + list_for_each_entry(pirq_entry, &msi_dev_entry->pirq_list_head, list) {
35554 + if (pirq_entry->entry_nr == entries[i].entry) {
35555 + irq = pirq_entry->pirq;
35556 + BUG_ON(entries[i].vector != evtchn_get_xen_pirq(irq));
35557 + entries[i].vector = irq;
35564 + irq = evtchn_map_pirq(-1, entries[i].vector);
35565 + attach_pirq_entry(irq, entries[i].entry, msi_dev_entry);
35566 + entries[i].vector = irq;
35572 + status = msi_init();
35576 + pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
35580 + pci_read_config_word(dev, msi_control_reg(pos), &control);
35581 + nr_entries = multi_msix_capable(control);
35582 + if (nvec > nr_entries)
35585 + /* Check for any invalid entries */
35586 + for (i = 0; i < nvec; i++) {
35587 + if (entries[i].entry >= nr_entries)
35588 + return -EINVAL; /* invalid entry */
35589 + for (j = i + 1; j < nvec; j++) {
35590 + if (entries[i].entry == entries[j].entry)
35591 + return -EINVAL; /* duplicate entry */
35596 + /* Check whether driver already requested for MSI vector */
35597 + if (dev->msi_enabled) {
35598 + printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
35599 + "Device already has an MSI vector assigned\n",
35605 + status = msix_capability_init(dev, entries, nvec);
35608 + dev->irq_old = temp;
35615 +extern void pci_frontend_disable_msix(struct pci_dev* dev);
35616 +void pci_disable_msix(struct pci_dev* dev)
35622 + if (!pci_msi_enable)
35627 +#ifdef CONFIG_XEN_PCIDEV_FRONTEND
35628 + if (!is_initial_xendomain()) {
35629 + struct msi_dev_list *msi_dev_entry;
35630 + struct msi_pirq_entry *pirq_entry, *tmp;
35632 + pci_frontend_disable_msix(dev);
35634 + msi_dev_entry = get_msi_dev_pirq_list(dev);
35635 + list_for_each_entry_safe(pirq_entry, tmp,
35636 + &msi_dev_entry->pirq_list_head, list) {
35637 + evtchn_map_pirq(pirq_entry->pirq, 0);
35638 + list_del(&pirq_entry->list);
35639 + kfree(pirq_entry);
35642 + dev->irq = dev->irq_old;
35647 + pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
35651 + pci_read_config_word(dev, msi_control_reg(pos), &control);
35652 + if (!(control & PCI_MSIX_FLAGS_ENABLE))
35655 + msi_remove_pci_irq_vectors(dev);
35657 + /* Disable MSI mode */
35658 + disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
35662 + * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state
35663 + * @dev: pointer to the pci_dev data structure of MSI(X) device function
35665 + * Being called during hotplug remove, from which the device function
35666 + * is hot-removed. All previous assigned MSI/MSI-X vectors, if
35667 + * allocated for this device function, are reclaimed to unused state,
35668 + * which may be used later on.
35670 +void msi_remove_pci_irq_vectors(struct pci_dev* dev)
35672 + unsigned long flags;
35673 + struct msi_dev_list *msi_dev_entry;
35674 + struct msi_pirq_entry *pirq_entry, *tmp;
35676 + if (!pci_msi_enable || !dev)
35679 + msi_dev_entry = get_msi_dev_pirq_list(dev);
35681 + spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
35682 + if (!list_empty(&msi_dev_entry->pirq_list_head))
35684 + printk(KERN_WARNING "msix pirqs for dev %02x:%02x:%01x are not freed \
35685 + before acquire again.\n", dev->bus->number, PCI_SLOT(dev->devfn),
35686 + PCI_FUNC(dev->devfn));
35687 + list_for_each_entry_safe(pirq_entry, tmp,
35688 + &msi_dev_entry->pirq_list_head, list) {
35689 + msi_unmap_pirq(dev, pirq_entry->pirq);
35690 + list_del(&pirq_entry->list);
35691 + kfree(pirq_entry);
35694 + spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
35695 + dev->irq = dev->irq_old;
35698 +void pci_no_msi(void)
35700 + pci_msi_enable = 0;
35703 +EXPORT_SYMBOL(pci_enable_msi);
35704 +EXPORT_SYMBOL(pci_disable_msi);
35705 +EXPORT_SYMBOL(pci_enable_msix);
35706 +EXPORT_SYMBOL(pci_disable_msix);
35708 +EXPORT_SYMBOL(register_msi_get_owner);
35709 +EXPORT_SYMBOL(unregister_msi_get_owner);
35712 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/agp.h
35713 ===================================================================
35714 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
35715 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/agp.h 2007-06-22 09:08:06.000000000 +0200
35720 +#include <asm/pgtable.h>
35721 +#include <asm/cacheflush.h>
35722 +#include <asm/system.h>
35725 + * Functions to keep the agpgart mappings coherent with the MMU.
35726 + * The GART gives the CPU a physical alias of pages in memory. The alias region is
35727 + * mapped uncacheable. Make sure there are no conflicting mappings
35728 + * with different cachability attributes for the same page. This avoids
35729 + * data corruption on some CPUs.
35732 +/* Caller's responsibility to call global_flush_tlb() for
35733 + * performance reasons */
35734 +#define map_page_into_agp(page) ( \
35735 + xen_create_contiguous_region((unsigned long)page_address(page), 0, 32) \
35736 + ?: change_page_attr(page, 1, PAGE_KERNEL_NOCACHE))
35737 +#define unmap_page_from_agp(page) ( \
35738 + xen_destroy_contiguous_region((unsigned long)page_address(page), 0), \
35739 + /* only a fallback: xen_destroy_contiguous_region uses PAGE_KERNEL */ \
35740 + change_page_attr(page, 1, PAGE_KERNEL))
35741 +#define flush_agp_mappings() global_flush_tlb()
35743 +/* Could use CLFLUSH here if the cpu supports it. But then it would
35744 + need to be called for each cacheline of the whole page so it may not be
35745 + worth it. Would need a page for it. */
35746 +#define flush_agp_cache() wbinvd()
35748 +/* Convert a physical address to an address suitable for the GART. */
35749 +#define phys_to_gart(x) phys_to_machine(x)
35750 +#define gart_to_phys(x) machine_to_phys(x)
35752 +/* GATT allocation. Returns/accepts GATT kernel virtual address. */
35753 +#define alloc_gatt_pages(order) ({ \
35754 + char *_t; dma_addr_t _d; \
35755 + _t = dma_alloc_coherent(NULL,PAGE_SIZE<<(order),&_d,GFP_KERNEL); \
35757 +#define free_gatt_pages(table, order) \
35758 + dma_free_coherent(NULL,PAGE_SIZE<<(order),(table),virt_to_bus(table))
35761 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/desc_32.h
35762 ===================================================================
35763 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
35764 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/desc_32.h 2008-01-28 12:24:19.000000000 +0100
35766 +#ifndef __ARCH_DESC_H
35767 +#define __ARCH_DESC_H
35769 +#include <asm/ldt.h>
35770 +#include <asm/segment.h>
35772 +#define CPU_16BIT_STACK_SIZE 1024
35774 +#ifndef __ASSEMBLY__
35776 +#include <linux/preempt.h>
35777 +#include <linux/smp.h>
35779 +#include <asm/mmu.h>
35781 +extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
35783 +DECLARE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
35785 +struct Xgt_desc_struct {
35786 + unsigned short size;
35787 + unsigned long address __attribute__((packed));
35788 + unsigned short pad;
35789 +} __attribute__ ((packed));
35791 +extern struct Xgt_desc_struct idt_descr;
35792 +DECLARE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
35795 +static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
35797 + return (struct desc_struct *)per_cpu(cpu_gdt_descr, cpu).address;
35800 +#define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8))
35801 +#define load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8))
35803 +#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr))
35804 +#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr))
35805 +#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr))
35806 +#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt))
35808 +#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
35809 +#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
35810 +#define store_tr(tr) __asm__ ("str %0":"=mr" (tr))
35811 +#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt))
35814 + * This is the ldt that every process will get unless we need
35815 + * something other than this.
35817 +extern struct desc_struct default_ldt[];
35818 +extern void set_intr_gate(unsigned int irq, void * addr);
35820 +#define _set_tssldt_desc(n,addr,limit,type) \
35821 +__asm__ __volatile__ ("movw %w3,0(%2)\n\t" \
35822 + "movw %w1,2(%2)\n\t" \
35823 + "rorl $16,%1\n\t" \
35824 + "movb %b1,4(%2)\n\t" \
35825 + "movb %4,5(%2)\n\t" \
35826 + "movb $0,6(%2)\n\t" \
35827 + "movb %h1,7(%2)\n\t" \
35829 + : "=m"(*(n)) : "q" (addr), "r"(n), "ir"(limit), "i"(type))
35831 +#ifndef CONFIG_X86_NO_TSS
35832 +static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *addr)
35834 + _set_tssldt_desc(&get_cpu_gdt_table(cpu)[entry], (int)addr,
35835 + offsetof(struct tss_struct, __cacheline_filler) - 1, 0x89);
35838 +#define set_tss_desc(cpu,addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
35841 +static inline void set_ldt_desc(unsigned int cpu, void *addr, unsigned int size)
35843 + _set_tssldt_desc(&get_cpu_gdt_table(cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
35846 +#define LDT_entry_a(info) \
35847 + ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
35849 +#define LDT_entry_b(info) \
35850 + (((info)->base_addr & 0xff000000) | \
35851 + (((info)->base_addr & 0x00ff0000) >> 16) | \
35852 + ((info)->limit & 0xf0000) | \
35853 + (((info)->read_exec_only ^ 1) << 9) | \
35854 + ((info)->contents << 10) | \
35855 + (((info)->seg_not_present ^ 1) << 15) | \
35856 + ((info)->seg_32bit << 22) | \
35857 + ((info)->limit_in_pages << 23) | \
35858 + ((info)->useable << 20) | \
35861 +#define LDT_empty(info) (\
35862 + (info)->base_addr == 0 && \
35863 + (info)->limit == 0 && \
35864 + (info)->contents == 0 && \
35865 + (info)->read_exec_only == 1 && \
35866 + (info)->seg_32bit == 0 && \
35867 + (info)->limit_in_pages == 0 && \
35868 + (info)->seg_not_present == 1 && \
35869 + (info)->useable == 0 )
35871 +extern int write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 entry_b);
35873 +#if TLS_SIZE != 24
35874 +# error update this code.
35877 +static inline void load_TLS(struct thread_struct *t, unsigned int cpu)
35879 +#define C(i) if (HYPERVISOR_update_descriptor(virt_to_machine(&get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i]), \
35880 + *(u64 *)&t->tls_array[i])) \
35882 + C(0); C(1); C(2);
35886 +static inline void clear_LDT(void)
35888 + int cpu = get_cpu();
35891 + * NB. We load the default_ldt for lcall7/27 handling on demand, as
35892 + * it slows down context switching. Noone uses it anyway.
35894 + cpu = cpu; /* XXX avoid compiler warning */
35895 + xen_set_ldt(NULL, 0);
35900 + * load one particular LDT into the current CPU
35902 +static inline void load_LDT_nolock(mm_context_t *pc, int cpu)
35904 + void *segments = pc->ldt;
35905 + int count = pc->size;
35907 + if (likely(!count))
35910 + xen_set_ldt(segments, count);
35913 +static inline void load_LDT(mm_context_t *pc)
35915 + int cpu = get_cpu();
35916 + load_LDT_nolock(pc, cpu);
35920 +static inline unsigned long get_desc_base(unsigned long *desc)
35922 + unsigned long base;
35923 + base = ((desc[0] >> 16) & 0x0000ffff) |
35924 + ((desc[1] << 16) & 0x00ff0000) |
35925 + (desc[1] & 0xff000000);
35929 +#endif /* !__ASSEMBLY__ */
35932 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/dma-mapping_32.h
35933 ===================================================================
35934 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
35935 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/dma-mapping_32.h 2008-04-02 12:34:02.000000000 +0200
35937 +#ifndef _ASM_I386_DMA_MAPPING_H
35938 +#define _ASM_I386_DMA_MAPPING_H
35941 + * IOMMU interface. See Documentation/DMA-mapping.txt and DMA-API.txt for
35945 +#include <linux/mm.h>
35946 +#include <asm/cache.h>
35947 +#include <asm/io.h>
35948 +#include <asm/scatterlist.h>
35949 +#include <asm/swiotlb.h>
35952 +address_needs_mapping(struct device *hwdev, dma_addr_t addr)
35954 + dma_addr_t mask = 0xffffffff;
35955 + /* If the device has a mask, use it, otherwise default to 32 bits */
35956 + if (hwdev && hwdev->dma_mask)
35957 + mask = *hwdev->dma_mask;
35958 + return (addr & ~mask) != 0;
35961 +extern int range_straddles_page_boundary(paddr_t p, size_t size);
35963 +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
35964 +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
35966 +void *dma_alloc_coherent(struct device *dev, size_t size,
35967 + dma_addr_t *dma_handle, gfp_t flag);
35969 +void dma_free_coherent(struct device *dev, size_t size,
35970 + void *vaddr, dma_addr_t dma_handle);
35973 +dma_map_single(struct device *dev, void *ptr, size_t size,
35974 + enum dma_data_direction direction);
35977 +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
35978 + enum dma_data_direction direction);
35980 +extern int dma_map_sg(struct device *hwdev, struct scatterlist *sg,
35981 + int nents, enum dma_data_direction direction);
35982 +extern void dma_unmap_sg(struct device *hwdev, struct scatterlist *sg,
35983 + int nents, enum dma_data_direction direction);
35985 +#ifdef CONFIG_HIGHMEM
35987 +dma_map_page(struct device *dev, struct page *page, unsigned long offset,
35988 + size_t size, enum dma_data_direction direction);
35991 +dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
35992 + enum dma_data_direction direction);
35994 +#define dma_map_page(dev, page, offset, size, dir) \
35995 + dma_map_single(dev, page_address(page) + (offset), (size), (dir))
35996 +#define dma_unmap_page dma_unmap_single
36000 +dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
36001 + enum dma_data_direction direction);
36004 +dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
36005 + enum dma_data_direction direction);
36007 +static inline void
36008 +dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
36009 + unsigned long offset, size_t size,
36010 + enum dma_data_direction direction)
36012 + dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
36015 +static inline void
36016 +dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
36017 + unsigned long offset, size_t size,
36018 + enum dma_data_direction direction)
36020 + dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
36023 +static inline void
36024 +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
36025 + enum dma_data_direction direction)
36028 + swiotlb_sync_sg_for_cpu(dev,sg,nelems,direction);
36029 + flush_write_buffers();
36032 +static inline void
36033 +dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
36034 + enum dma_data_direction direction)
36037 + swiotlb_sync_sg_for_device(dev,sg,nelems,direction);
36038 + flush_write_buffers();
36042 +dma_mapping_error(dma_addr_t dma_addr);
36045 +dma_supported(struct device *dev, u64 mask);
36048 +dma_set_mask(struct device *dev, u64 mask)
36050 + if(!dev->dma_mask || !dma_supported(dev, mask))
36053 + *dev->dma_mask = mask;
36059 +dma_get_cache_alignment(void)
36061 + /* no easy way to get cache size on all x86, so return the
36062 + * maximum possible, to be safe */
36063 + return (1 << INTERNODE_CACHE_SHIFT);
36066 +#define dma_is_consistent(d) (1)
36068 +static inline void
36069 +dma_cache_sync(void *vaddr, size_t size,
36070 + enum dma_data_direction direction)
36072 + flush_write_buffers();
36075 +#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
36077 +dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
36078 + dma_addr_t device_addr, size_t size, int flags);
36081 +dma_release_declared_memory(struct device *dev);
36084 +dma_mark_declared_memory_occupied(struct device *dev,
36085 + dma_addr_t device_addr, size_t size);
36088 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/fixmap_32.h
36089 ===================================================================
36090 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
36091 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/fixmap_32.h 2007-06-12 13:14:02.000000000 +0200
36094 + * fixmap.h: compile-time virtual memory allocation
36096 + * This file is subject to the terms and conditions of the GNU General Public
36097 + * License. See the file "COPYING" in the main directory of this archive
36098 + * for more details.
36100 + * Copyright (C) 1998 Ingo Molnar
36102 + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
36105 +#ifndef _ASM_FIXMAP_H
36106 +#define _ASM_FIXMAP_H
36109 +/* used by vmalloc.c, vsyscall.lds.S.
36111 + * Leave one empty page between vmalloc'ed areas and
36112 + * the start of the fixmap.
36114 +extern unsigned long __FIXADDR_TOP;
36116 +#ifndef __ASSEMBLY__
36117 +#include <linux/kernel.h>
36118 +#include <asm/acpi.h>
36119 +#include <asm/apicdef.h>
36120 +#include <asm/page.h>
36121 +#ifdef CONFIG_HIGHMEM
36122 +#include <linux/threads.h>
36123 +#include <asm/kmap_types.h>
36127 + * Here we define all the compile-time 'special' virtual
36128 + * addresses. The point is to have a constant address at
36129 + * compile time, but to set the physical address only
36130 + * in the boot process. We allocate these special addresses
36131 + * from the end of virtual memory (0xfffff000) backwards.
36132 + * Also this lets us do fail-safe vmalloc(), we
36133 + * can guarantee that these special addresses and
36134 + * vmalloc()-ed addresses never overlap.
36136 + * these 'compile-time allocated' memory buffers are
36137 + * fixed-size 4k pages. (or larger if used with an increment
36138 + * highger than 1) use fixmap_set(idx,phys) to associate
36139 + * physical memory with fixmap indices.
36141 + * TLB entries of such buffers will not be flushed across
36144 +enum fixed_addresses {
36147 +#ifdef CONFIG_X86_LOCAL_APIC
36148 + FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */
36150 +#ifdef CONFIG_X86_IO_APIC
36151 + FIX_IO_APIC_BASE_0,
36152 + FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS-1,
36154 +#ifdef CONFIG_X86_VISWS_APIC
36155 + FIX_CO_CPU, /* Cobalt timer */
36156 + FIX_CO_APIC, /* Cobalt APIC Redirection Table */
36157 + FIX_LI_PCIA, /* Lithium PCI Bridge A */
36158 + FIX_LI_PCIB, /* Lithium PCI Bridge B */
36160 +#ifdef CONFIG_X86_F00F_BUG
36161 + FIX_F00F_IDT, /* Virtual mapping for IDT */
36163 +#ifdef CONFIG_X86_CYCLONE_TIMER
36164 + FIX_CYCLONE_TIMER, /*cyclone timer register*/
36166 +#ifdef CONFIG_HIGHMEM
36167 + FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
36168 + FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
36170 +#ifdef CONFIG_ACPI
36172 + FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
36174 +#ifdef CONFIG_PCI_MMCONFIG
36178 +#define NR_FIX_ISAMAPS 256
36180 + FIX_ISAMAP_BEGIN = FIX_ISAMAP_END + NR_FIX_ISAMAPS - 1,
36181 + __end_of_permanent_fixed_addresses,
36182 + /* temporary boot-time mappings, used before ioremap() is functional */
36183 +#define NR_FIX_BTMAPS 16
36184 + FIX_BTMAP_END = __end_of_permanent_fixed_addresses,
36185 + FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS - 1,
36187 + __end_of_fixed_addresses
36190 +extern void set_fixaddr_top(unsigned long top);
36192 +extern void __set_fixmap(enum fixed_addresses idx,
36193 + maddr_t phys, pgprot_t flags);
36195 +#define set_fixmap(idx, phys) \
36196 + __set_fixmap(idx, phys, PAGE_KERNEL)
36198 + * Some hardware wants to get fixmapped without caching.
36200 +#define set_fixmap_nocache(idx, phys) \
36201 + __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
36203 +#define clear_fixmap(idx) \
36204 + __set_fixmap(idx, 0, __pgprot(0))
36206 +#define FIXADDR_TOP ((unsigned long)__FIXADDR_TOP)
36208 +#define __FIXADDR_SIZE (__end_of_permanent_fixed_addresses << PAGE_SHIFT)
36209 +#define __FIXADDR_BOOT_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
36210 +#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE)
36211 +#define FIXADDR_BOOT_START (FIXADDR_TOP - __FIXADDR_BOOT_SIZE)
36213 +#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
36214 +#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
36216 +extern void __this_fixmap_does_not_exist(void);
36219 + * 'index to address' translation. If anyone tries to use the idx
36220 + * directly without tranlation, we catch the bug with a NULL-deference
36221 + * kernel oops. Illegal ranges of incoming indices are caught too.
36223 +static __always_inline unsigned long fix_to_virt(const unsigned int idx)
36226 + * this branch gets completely eliminated after inlining,
36227 + * except when someone tries to use fixaddr indices in an
36228 + * illegal way. (such as mixing up address types or using
36229 + * out-of-range indices).
36231 + * If it doesn't get removed, the linker will complain
36232 + * loudly with a reasonably clear error message..
36234 + if (idx >= __end_of_fixed_addresses)
36235 + __this_fixmap_does_not_exist();
36237 + return __fix_to_virt(idx);
36240 +static inline unsigned long virt_to_fix(const unsigned long vaddr)
36242 + BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
36243 + return __virt_to_fix(vaddr);
36246 +#endif /* !__ASSEMBLY__ */
36248 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/gnttab_dma.h
36249 ===================================================================
36250 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
36251 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/gnttab_dma.h 2007-08-06 15:10:49.000000000 +0200
36254 + * Copyright (c) 2007 Herbert Xu <herbert@gondor.apana.org.au>
36255 + * Copyright (c) 2007 Isaku Yamahata <yamahata at valinux co jp>
36256 + * VA Linux Systems Japan K.K.
36258 + * This program is free software; you can redistribute it and/or modify
36259 + * it under the terms of the GNU General Public License as published by
36260 + * the Free Software Foundation; either version 2 of the License, or
36261 + * (at your option) any later version.
36263 + * This program is distributed in the hope that it will be useful,
36264 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
36265 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36266 + * GNU General Public License for more details.
36268 + * You should have received a copy of the GNU General Public License
36269 + * along with this program; if not, write to the Free Software
36270 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36273 +#ifndef _ASM_I386_GNTTAB_DMA_H
36274 +#define _ASM_I386_GNTTAB_DMA_H
36276 +static inline int gnttab_dma_local_pfn(struct page *page)
36278 + /* Has it become a local MFN? */
36279 + return pfn_valid(mfn_to_local_pfn(pfn_to_mfn(page_to_pfn(page))));
36282 +static inline maddr_t gnttab_dma_map_page(struct page *page)
36284 + __gnttab_dma_map_page(page);
36285 + return ((maddr_t)pfn_to_mfn(page_to_pfn(page)) << PAGE_SHIFT);
36288 +static inline void gnttab_dma_unmap_page(maddr_t maddr)
36290 + __gnttab_dma_unmap_page(virt_to_page(bus_to_virt(maddr)));
36293 +#endif /* _ASM_I386_GNTTAB_DMA_H */
36294 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/highmem.h
36295 ===================================================================
36296 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
36297 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/highmem.h 2008-10-29 09:55:56.000000000 +0100
36300 + * highmem.h: virtual kernel memory mappings for high memory
36302 + * Used in CONFIG_HIGHMEM systems for memory pages which
36303 + * are not addressable by direct kernel virtual addresses.
36305 + * Copyright (C) 1999 Gerhard Wichert, Siemens AG
36306 + * Gerhard.Wichert@pdb.siemens.de
36309 + * Redesigned the x86 32-bit VM architecture to deal with
36310 + * up to 16 Terabyte physical memory. With current x86 CPUs
36311 + * we now support up to 64 Gigabytes physical RAM.
36313 + * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
36316 +#ifndef _ASM_HIGHMEM_H
36317 +#define _ASM_HIGHMEM_H
36321 +#include <linux/interrupt.h>
36322 +#include <linux/threads.h>
36323 +#include <asm/kmap_types.h>
36324 +#include <asm/tlbflush.h>
36326 +/* declarations for highmem.c */
36327 +extern unsigned long highstart_pfn, highend_pfn;
36329 +extern pte_t *kmap_pte;
36330 +extern pgprot_t kmap_prot;
36331 +extern pte_t *pkmap_page_table;
36334 + * Right now we initialize only a single pte table. It can be extended
36335 + * easily, subsequent pte tables have to be allocated in one physical
36338 +#ifdef CONFIG_X86_PAE
36339 +#define LAST_PKMAP 512
36341 +#define LAST_PKMAP 1024
36347 + * fixed_addresses
36349 + * temp fixed addresses
36350 + * FIXADDR_BOOT_START
36351 + * Persistent kmap area
36358 +#define PKMAP_BASE ( (FIXADDR_BOOT_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK )
36359 +#define LAST_PKMAP_MASK (LAST_PKMAP-1)
36360 +#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
36361 +#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
36363 +extern void * FASTCALL(kmap_high(struct page *page));
36364 +extern void FASTCALL(kunmap_high(struct page *page));
36366 +void *kmap(struct page *page);
36367 +void kunmap(struct page *page);
36368 +void *kmap_atomic(struct page *page, enum km_type type);
36369 +void *kmap_atomic_pte(struct page *page, enum km_type type);
36370 +void kunmap_atomic(void *kvaddr, enum km_type type);
36371 +void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
36372 +struct page *kmap_atomic_to_page(void *ptr);
36374 +#define flush_cache_kmaps() do { } while (0)
36376 +void clear_highpage(struct page *);
36377 +static inline void clear_user_highpage(struct page *page, unsigned long vaddr)
36379 + clear_highpage(page);
36381 +#define __HAVE_ARCH_CLEAR_HIGHPAGE
36382 +#define __HAVE_ARCH_CLEAR_USER_HIGHPAGE
36384 +void copy_highpage(struct page *to, struct page *from);
36385 +static inline void copy_user_highpage(struct page *to, struct page *from,
36386 + unsigned long vaddr)
36388 + copy_highpage(to, from);
36390 +#define __HAVE_ARCH_COPY_HIGHPAGE
36391 +#define __HAVE_ARCH_COPY_USER_HIGHPAGE
36393 +#endif /* __KERNEL__ */
36395 +#endif /* _ASM_HIGHMEM_H */
36396 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/hypercall_32.h
36397 ===================================================================
36398 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
36399 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/hypercall_32.h 2008-11-25 12:22:34.000000000 +0100
36401 +/******************************************************************************
36404 + * Linux-specific hypervisor handling.
36406 + * Copyright (c) 2002-2004, K A Fraser
36408 + * This program is free software; you can redistribute it and/or
36409 + * modify it under the terms of the GNU General Public License version 2
36410 + * as published by the Free Software Foundation; or, when distributed
36411 + * separately from the Linux kernel or incorporated into other
36412 + * software packages, subject to the following license:
36414 + * Permission is hereby granted, free of charge, to any person obtaining a copy
36415 + * of this source file (the "Software"), to deal in the Software without
36416 + * restriction, including without limitation the rights to use, copy, modify,
36417 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
36418 + * and to permit persons to whom the Software is furnished to do so, subject to
36419 + * the following conditions:
36421 + * The above copyright notice and this permission notice shall be included in
36422 + * all copies or substantial portions of the Software.
36424 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
36425 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36426 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
36427 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
36428 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
36429 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36430 + * IN THE SOFTWARE.
36433 +#ifndef __HYPERCALL_H__
36434 +#define __HYPERCALL_H__
36436 +#include <linux/string.h> /* memcpy() */
36437 +#include <linux/stringify.h>
36439 +#ifndef __HYPERVISOR_H__
36440 +# error "please don't include this file directly"
36444 +#define HYPERCALL_STR(name) \
36445 + "call hypercall_page + ("__stringify(__HYPERVISOR_##name)" * 32)"
36447 +#define HYPERCALL_STR(name) \
36448 + "mov hypercall_stubs,%%eax; " \
36449 + "add $("__stringify(__HYPERVISOR_##name)" * 32),%%eax; "\
36453 +#define _hypercall0(type, name) \
36457 + HYPERCALL_STR(name) \
36464 +#define _hypercall1(type, name, a1) \
36469 + HYPERCALL_STR(name) \
36470 + : "=a" (__res), "=b" (__ign1) \
36471 + : "1" ((long)(a1)) \
36476 +#define _hypercall2(type, name, a1, a2) \
36479 + long __ign1, __ign2; \
36481 + HYPERCALL_STR(name) \
36482 + : "=a" (__res), "=b" (__ign1), "=c" (__ign2) \
36483 + : "1" ((long)(a1)), "2" ((long)(a2)) \
36488 +#define _hypercall3(type, name, a1, a2, a3) \
36491 + long __ign1, __ign2, __ign3; \
36493 + HYPERCALL_STR(name) \
36494 + : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
36496 + : "1" ((long)(a1)), "2" ((long)(a2)), \
36497 + "3" ((long)(a3)) \
36502 +#define _hypercall4(type, name, a1, a2, a3, a4) \
36505 + long __ign1, __ign2, __ign3, __ign4; \
36507 + HYPERCALL_STR(name) \
36508 + : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
36509 + "=d" (__ign3), "=S" (__ign4) \
36510 + : "1" ((long)(a1)), "2" ((long)(a2)), \
36511 + "3" ((long)(a3)), "4" ((long)(a4)) \
36516 +#define _hypercall5(type, name, a1, a2, a3, a4, a5) \
36519 + long __ign1, __ign2, __ign3, __ign4, __ign5; \
36521 + HYPERCALL_STR(name) \
36522 + : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
36523 + "=d" (__ign3), "=S" (__ign4), "=D" (__ign5) \
36524 + : "1" ((long)(a1)), "2" ((long)(a2)), \
36525 + "3" ((long)(a3)), "4" ((long)(a4)), \
36526 + "5" ((long)(a5)) \
36531 +static inline int __must_check
36532 +HYPERVISOR_set_trap_table(
36533 + const trap_info_t *table)
36535 + return _hypercall1(int, set_trap_table, table);
36538 +static inline int __must_check
36539 +HYPERVISOR_mmu_update(
36540 + mmu_update_t *req, unsigned int count, unsigned int *success_count,
36543 + return _hypercall4(int, mmu_update, req, count, success_count, domid);
36546 +static inline int __must_check
36547 +HYPERVISOR_mmuext_op(
36548 + struct mmuext_op *op, unsigned int count, unsigned int *success_count,
36551 + return _hypercall4(int, mmuext_op, op, count, success_count, domid);
36554 +static inline int __must_check
36555 +HYPERVISOR_set_gdt(
36556 + unsigned long *frame_list, unsigned int entries)
36558 + return _hypercall2(int, set_gdt, frame_list, entries);
36561 +static inline int __must_check
36562 +HYPERVISOR_stack_switch(
36563 + unsigned long ss, unsigned long esp)
36565 + return _hypercall2(int, stack_switch, ss, esp);
36568 +static inline int __must_check
36569 +HYPERVISOR_set_callbacks(
36570 + unsigned long event_selector, unsigned long event_address,
36571 + unsigned long failsafe_selector, unsigned long failsafe_address)
36573 + return _hypercall4(int, set_callbacks,
36574 + event_selector, event_address,
36575 + failsafe_selector, failsafe_address);
36579 +HYPERVISOR_fpu_taskswitch(
36582 + return _hypercall1(int, fpu_taskswitch, set);
36585 +static inline int __must_check
36586 +HYPERVISOR_sched_op_compat(
36587 + int cmd, unsigned long arg)
36589 + return _hypercall2(int, sched_op_compat, cmd, arg);
36592 +static inline int __must_check
36593 +HYPERVISOR_sched_op(
36594 + int cmd, void *arg)
36596 + return _hypercall2(int, sched_op, cmd, arg);
36599 +static inline long __must_check
36600 +HYPERVISOR_set_timer_op(
36603 + unsigned long timeout_hi = (unsigned long)(timeout>>32);
36604 + unsigned long timeout_lo = (unsigned long)timeout;
36605 + return _hypercall2(long, set_timer_op, timeout_lo, timeout_hi);
36608 +static inline int __must_check
36609 +HYPERVISOR_platform_op(
36610 + struct xen_platform_op *platform_op)
36612 + platform_op->interface_version = XENPF_INTERFACE_VERSION;
36613 + return _hypercall1(int, platform_op, platform_op);
36616 +static inline int __must_check
36617 +HYPERVISOR_set_debugreg(
36618 + unsigned int reg, unsigned long value)
36620 + return _hypercall2(int, set_debugreg, reg, value);
36623 +static inline unsigned long __must_check
36624 +HYPERVISOR_get_debugreg(
36625 + unsigned int reg)
36627 + return _hypercall1(unsigned long, get_debugreg, reg);
36630 +static inline int __must_check
36631 +HYPERVISOR_update_descriptor(
36632 + u64 ma, u64 desc)
36634 + return _hypercall4(int, update_descriptor, ma, ma>>32, desc, desc>>32);
36637 +static inline int __must_check
36638 +HYPERVISOR_memory_op(
36639 + unsigned int cmd, void *arg)
36641 + return _hypercall2(int, memory_op, cmd, arg);
36644 +static inline int __must_check
36645 +HYPERVISOR_multicall(
36646 + multicall_entry_t *call_list, unsigned int nr_calls)
36648 + return _hypercall2(int, multicall, call_list, nr_calls);
36651 +static inline int __must_check
36652 +HYPERVISOR_update_va_mapping(
36653 + unsigned long va, pte_t new_val, unsigned long flags)
36655 + unsigned long pte_hi = 0;
36656 +#ifdef CONFIG_X86_PAE
36657 + pte_hi = new_val.pte_high;
36659 + return _hypercall4(int, update_va_mapping, va,
36660 + new_val.pte_low, pte_hi, flags);
36663 +static inline int __must_check
36664 +HYPERVISOR_event_channel_op(
36665 + int cmd, void *arg)
36667 + int rc = _hypercall2(int, event_channel_op, cmd, arg);
36669 +#if CONFIG_XEN_COMPAT <= 0x030002
36670 + if (unlikely(rc == -ENOSYS)) {
36671 + struct evtchn_op op;
36673 + memcpy(&op.u, arg, sizeof(op.u));
36674 + rc = _hypercall1(int, event_channel_op_compat, &op);
36675 + memcpy(arg, &op.u, sizeof(op.u));
36682 +static inline int __must_check
36683 +HYPERVISOR_xen_version(
36684 + int cmd, void *arg)
36686 + return _hypercall2(int, xen_version, cmd, arg);
36689 +static inline int __must_check
36690 +HYPERVISOR_console_io(
36691 + int cmd, unsigned int count, char *str)
36693 + return _hypercall3(int, console_io, cmd, count, str);
36696 +static inline int __must_check
36697 +HYPERVISOR_physdev_op(
36698 + int cmd, void *arg)
36700 + int rc = _hypercall2(int, physdev_op, cmd, arg);
36702 +#if CONFIG_XEN_COMPAT <= 0x030002
36703 + if (unlikely(rc == -ENOSYS)) {
36704 + struct physdev_op op;
36706 + memcpy(&op.u, arg, sizeof(op.u));
36707 + rc = _hypercall1(int, physdev_op_compat, &op);
36708 + memcpy(arg, &op.u, sizeof(op.u));
36715 +static inline int __must_check
36716 +HYPERVISOR_grant_table_op(
36717 + unsigned int cmd, void *uop, unsigned int count)
36719 + return _hypercall3(int, grant_table_op, cmd, uop, count);
36722 +static inline int __must_check
36723 +HYPERVISOR_update_va_mapping_otherdomain(
36724 + unsigned long va, pte_t new_val, unsigned long flags, domid_t domid)
36726 + unsigned long pte_hi = 0;
36727 +#ifdef CONFIG_X86_PAE
36728 + pte_hi = new_val.pte_high;
36730 + return _hypercall5(int, update_va_mapping_otherdomain, va,
36731 + new_val.pte_low, pte_hi, flags, domid);
36734 +static inline int __must_check
36735 +HYPERVISOR_vm_assist(
36736 + unsigned int cmd, unsigned int type)
36738 + return _hypercall2(int, vm_assist, cmd, type);
36741 +static inline int __must_check
36742 +HYPERVISOR_vcpu_op(
36743 + int cmd, unsigned int vcpuid, void *extra_args)
36745 + return _hypercall3(int, vcpu_op, cmd, vcpuid, extra_args);
36748 +static inline int __must_check
36749 +HYPERVISOR_suspend(
36750 + unsigned long srec)
36752 + struct sched_shutdown sched_shutdown = {
36753 + .reason = SHUTDOWN_suspend
36756 + int rc = _hypercall3(int, sched_op, SCHEDOP_shutdown,
36757 + &sched_shutdown, srec);
36759 +#if CONFIG_XEN_COMPAT <= 0x030002
36760 + if (rc == -ENOSYS)
36761 + rc = _hypercall3(int, sched_op_compat, SCHEDOP_shutdown,
36762 + SHUTDOWN_suspend, srec);
36768 +#if CONFIG_XEN_COMPAT <= 0x030002
36770 +HYPERVISOR_nmi_op(
36771 + unsigned long op, void *arg)
36773 + return _hypercall2(int, nmi_op, op, arg);
36777 +#ifndef CONFIG_XEN
36778 +static inline unsigned long __must_check
36779 +HYPERVISOR_hvm_op(
36780 + int op, void *arg)
36782 + return _hypercall2(unsigned long, hvm_op, op, arg);
36786 +static inline int __must_check
36787 +HYPERVISOR_callback_op(
36788 + int cmd, const void *arg)
36790 + return _hypercall2(int, callback_op, cmd, arg);
36793 +static inline int __must_check
36794 +HYPERVISOR_xenoprof_op(
36795 + int op, void *arg)
36797 + return _hypercall2(int, xenoprof_op, op, arg);
36800 +static inline int __must_check
36801 +HYPERVISOR_kexec_op(
36802 + unsigned long op, void *args)
36804 + return _hypercall2(int, kexec_op, op, args);
36809 +#endif /* __HYPERCALL_H__ */
36810 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/hypervisor.h
36811 ===================================================================
36812 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
36813 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/hypervisor.h 2008-02-20 09:32:49.000000000 +0100
36815 +/******************************************************************************
36818 + * Linux-specific hypervisor handling.
36820 + * Copyright (c) 2002-2004, K A Fraser
36822 + * This program is free software; you can redistribute it and/or
36823 + * modify it under the terms of the GNU General Public License version 2
36824 + * as published by the Free Software Foundation; or, when distributed
36825 + * separately from the Linux kernel or incorporated into other
36826 + * software packages, subject to the following license:
36828 + * Permission is hereby granted, free of charge, to any person obtaining a copy
36829 + * of this source file (the "Software"), to deal in the Software without
36830 + * restriction, including without limitation the rights to use, copy, modify,
36831 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
36832 + * and to permit persons to whom the Software is furnished to do so, subject to
36833 + * the following conditions:
36835 + * The above copyright notice and this permission notice shall be included in
36836 + * all copies or substantial portions of the Software.
36838 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
36839 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36840 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
36841 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
36842 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
36843 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36844 + * IN THE SOFTWARE.
36847 +#ifndef __HYPERVISOR_H__
36848 +#define __HYPERVISOR_H__
36850 +#include <linux/types.h>
36851 +#include <linux/kernel.h>
36852 +#include <linux/version.h>
36853 +#include <linux/errno.h>
36854 +#include <xen/interface/xen.h>
36855 +#include <xen/interface/platform.h>
36856 +#include <xen/interface/event_channel.h>
36857 +#include <xen/interface/physdev.h>
36858 +#include <xen/interface/sched.h>
36859 +#include <xen/interface/nmi.h>
36860 +#include <asm/ptrace.h>
36861 +#include <asm/page.h>
36862 +#if defined(__i386__)
36863 +# ifdef CONFIG_X86_PAE
36864 +# include <asm-generic/pgtable-nopud.h>
36866 +# include <asm-generic/pgtable-nopmd.h>
36868 +#elif defined(__x86_64__) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
36869 +# include <asm-generic/pgtable-nopud.h>
36872 +extern shared_info_t *HYPERVISOR_shared_info;
36874 +#define vcpu_info(cpu) (HYPERVISOR_shared_info->vcpu_info + (cpu))
36876 +#define current_vcpu_info() vcpu_info(smp_processor_id())
36878 +#define current_vcpu_info() vcpu_info(0)
36881 +#ifdef CONFIG_X86_32
36882 +extern unsigned long hypervisor_virt_start;
36885 +/* arch/xen/i386/kernel/setup.c */
36886 +extern start_info_t *xen_start_info;
36887 +#ifdef CONFIG_XEN_PRIVILEGED_GUEST
36888 +#define is_initial_xendomain() (xen_start_info->flags & SIF_INITDOMAIN)
36890 +#define is_initial_xendomain() 0
36893 +/* arch/xen/kernel/evtchn.c */
36894 +/* Force a proper event-channel callback from Xen. */
36895 +void force_evtchn_callback(void);
36897 +/* arch/xen/kernel/process.c */
36898 +void xen_cpu_idle (void);
36900 +/* arch/xen/i386/kernel/hypervisor.c */
36901 +void do_hypervisor_callback(struct pt_regs *regs);
36903 +/* arch/xen/i386/mm/hypervisor.c */
36905 + * NB. ptr values should be PHYSICAL, not MACHINE. 'vals' should be already
36906 + * be MACHINE addresses.
36909 +void xen_pt_switch(unsigned long ptr);
36910 +void xen_new_user_pt(unsigned long ptr); /* x86_64 only */
36911 +void xen_load_gs(unsigned int selector); /* x86_64 only */
36912 +void xen_tlb_flush(void);
36913 +void xen_invlpg(unsigned long ptr);
36915 +void xen_l1_entry_update(pte_t *ptr, pte_t val);
36916 +void xen_l2_entry_update(pmd_t *ptr, pmd_t val);
36917 +void xen_l3_entry_update(pud_t *ptr, pud_t val); /* x86_64/PAE */
36918 +void xen_l4_entry_update(pgd_t *ptr, pgd_t val); /* x86_64 only */
36919 +void xen_pgd_pin(unsigned long ptr);
36920 +void xen_pgd_unpin(unsigned long ptr);
36922 +void xen_set_ldt(const void *ptr, unsigned int ents);
36925 +#include <linux/cpumask.h>
36926 +void xen_tlb_flush_all(void);
36927 +void xen_invlpg_all(unsigned long ptr);
36928 +void xen_tlb_flush_mask(cpumask_t *mask);
36929 +void xen_invlpg_mask(cpumask_t *mask, unsigned long ptr);
36932 +/* Returns zero on success else negative errno. */
36933 +int xen_create_contiguous_region(
36934 + unsigned long vstart, unsigned int order, unsigned int address_bits);
36935 +void xen_destroy_contiguous_region(
36936 + unsigned long vstart, unsigned int order);
36940 +int xen_limit_pages_to_max_mfn(
36941 + struct page *pages, unsigned int order, unsigned int address_bits);
36943 +/* Turn jiffies into Xen system time. */
36944 +u64 jiffies_to_st(unsigned long jiffies);
36946 +#ifdef CONFIG_XEN_SCRUB_PAGES
36947 +void scrub_pages(void *, unsigned int);
36949 +#define scrub_pages(_p,_n) ((void)0)
36952 +#include <xen/hypercall.h>
36954 +#if defined(CONFIG_X86_64)
36955 +#define MULTI_UVMFLAGS_INDEX 2
36956 +#define MULTI_UVMDOMID_INDEX 3
36958 +#define MULTI_UVMFLAGS_INDEX 3
36959 +#define MULTI_UVMDOMID_INDEX 4
36963 +#define is_running_on_xen() 1
36965 +extern char *hypercall_stubs;
36966 +#define is_running_on_xen() (!!hypercall_stubs)
36973 + int rc = HYPERVISOR_sched_op(SCHEDOP_yield, NULL);
36975 +#if CONFIG_XEN_COMPAT <= 0x030002
36976 + if (rc == -ENOSYS)
36977 + rc = HYPERVISOR_sched_op_compat(SCHEDOP_yield, 0);
36987 + int rc = HYPERVISOR_sched_op(SCHEDOP_block, NULL);
36989 +#if CONFIG_XEN_COMPAT <= 0x030002
36990 + if (rc == -ENOSYS)
36991 + rc = HYPERVISOR_sched_op_compat(SCHEDOP_block, 0);
36997 +static inline void /*__noreturn*/
36998 +HYPERVISOR_shutdown(
36999 + unsigned int reason)
37001 + struct sched_shutdown sched_shutdown = {
37005 + VOID(HYPERVISOR_sched_op(SCHEDOP_shutdown, &sched_shutdown));
37006 +#if CONFIG_XEN_COMPAT <= 0x030002
37007 + VOID(HYPERVISOR_sched_op_compat(SCHEDOP_shutdown, reason));
37009 + /* Don't recurse needlessly. */
37010 + BUG_ON(reason != SHUTDOWN_crash);
37014 +static inline int __must_check
37016 + evtchn_port_t *ports, unsigned int nr_ports, u64 timeout)
37019 + struct sched_poll sched_poll = {
37020 + .nr_ports = nr_ports,
37021 + .timeout = jiffies_to_st(timeout)
37023 + set_xen_guest_handle(sched_poll.ports, ports);
37025 + rc = HYPERVISOR_sched_op(SCHEDOP_poll, &sched_poll);
37026 +#if CONFIG_XEN_COMPAT <= 0x030002
37027 + if (rc == -ENOSYS)
37028 + rc = HYPERVISOR_sched_op_compat(SCHEDOP_yield, 0);
37036 +static inline void
37037 +MULTI_update_va_mapping(
37038 + multicall_entry_t *mcl, unsigned long va,
37039 + pte_t new_val, unsigned long flags)
37041 + mcl->op = __HYPERVISOR_update_va_mapping;
37042 + mcl->args[0] = va;
37043 +#if defined(CONFIG_X86_64)
37044 + mcl->args[1] = new_val.pte;
37045 +#elif defined(CONFIG_X86_PAE)
37046 + mcl->args[1] = new_val.pte_low;
37047 + mcl->args[2] = new_val.pte_high;
37049 + mcl->args[1] = new_val.pte_low;
37050 + mcl->args[2] = 0;
37052 + mcl->args[MULTI_UVMFLAGS_INDEX] = flags;
37055 +static inline void
37056 +MULTI_grant_table_op(multicall_entry_t *mcl, unsigned int cmd,
37057 + void *uop, unsigned int count)
37059 + mcl->op = __HYPERVISOR_grant_table_op;
37060 + mcl->args[0] = cmd;
37061 + mcl->args[1] = (unsigned long)uop;
37062 + mcl->args[2] = count;
37065 +#else /* !defined(CONFIG_XEN) */
37067 +/* Multicalls not supported for HVM guests. */
37068 +#define MULTI_update_va_mapping(a,b,c,d) ((void)0)
37069 +#define MULTI_grant_table_op(a,b,c,d) ((void)0)
37073 +#endif /* __HYPERVISOR_H__ */
37074 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/irqflags_32.h
37075 ===================================================================
37076 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
37077 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/irqflags_32.h 2007-06-12 13:14:02.000000000 +0200
37080 + * include/asm-i386/irqflags.h
37082 + * IRQ flags handling
37084 + * This file gets included from lowlevel asm headers too, to provide
37085 + * wrapped versions of the local_irq_*() APIs, based on the
37086 + * raw_local_irq_*() functions from the lowlevel headers.
37088 +#ifndef _ASM_IRQFLAGS_H
37089 +#define _ASM_IRQFLAGS_H
37091 +#ifndef __ASSEMBLY__
37094 + * The use of 'barrier' in the following reflects their use as local-lock
37095 + * operations. Reentrancy must be prevented (e.g., __cli()) /before/ following
37096 + * critical operations are executed. All critical operations must complete
37097 + * /before/ reentrancy is permitted (e.g., __sti()). Alpha architecture also
37098 + * includes these barriers, for example.
37101 +#define __raw_local_save_flags() (current_vcpu_info()->evtchn_upcall_mask)
37103 +#define raw_local_save_flags(flags) \
37104 + do { (flags) = __raw_local_save_flags(); } while (0)
37106 +#define raw_local_irq_restore(x) \
37108 + vcpu_info_t *_vcpu; \
37110 + _vcpu = current_vcpu_info(); \
37111 + if ((_vcpu->evtchn_upcall_mask = (x)) == 0) { \
37112 + barrier(); /* unmask then check (avoid races) */ \
37113 + if (unlikely(_vcpu->evtchn_upcall_pending)) \
37114 + force_evtchn_callback(); \
37118 +#define raw_local_irq_disable() \
37120 + current_vcpu_info()->evtchn_upcall_mask = 1; \
37124 +#define raw_local_irq_enable() \
37126 + vcpu_info_t *_vcpu; \
37128 + _vcpu = current_vcpu_info(); \
37129 + _vcpu->evtchn_upcall_mask = 0; \
37130 + barrier(); /* unmask then check (avoid races) */ \
37131 + if (unlikely(_vcpu->evtchn_upcall_pending)) \
37132 + force_evtchn_callback(); \
37136 + * Used in the idle loop; sti takes one instruction cycle
37139 +void raw_safe_halt(void);
37142 + * Used when interrupts are already enabled or to
37143 + * shutdown the processor:
37147 +static inline int raw_irqs_disabled_flags(unsigned long flags)
37149 + return (flags != 0);
37152 +#define raw_irqs_disabled() \
37154 + unsigned long flags = __raw_local_save_flags(); \
37156 + raw_irqs_disabled_flags(flags); \
37160 + * For spinlocks, etc:
37162 +#define __raw_local_irq_save() \
37164 + unsigned long flags = __raw_local_save_flags(); \
37166 + raw_local_irq_disable(); \
37171 +#define raw_local_irq_save(flags) \
37172 + do { (flags) = __raw_local_irq_save(); } while (0)
37174 +#endif /* __ASSEMBLY__ */
37177 + * Do the CPU's IRQ-state tracing from assembly code. We call a
37178 + * C function, so save all the C-clobbered registers:
37180 +#ifdef CONFIG_TRACE_IRQFLAGS
37182 +# define TRACE_IRQS_ON \
37186 + call trace_hardirqs_on; \
37191 +# define TRACE_IRQS_OFF \
37195 + call trace_hardirqs_off; \
37201 +# define TRACE_IRQS_ON
37202 +# define TRACE_IRQS_OFF
37206 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/maddr_32.h
37207 ===================================================================
37208 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
37209 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/maddr_32.h 2008-04-02 12:34:02.000000000 +0200
37211 +#ifndef _I386_MADDR_H
37212 +#define _I386_MADDR_H
37214 +#include <xen/features.h>
37215 +#include <xen/interface/xen.h>
37217 +/**** MACHINE <-> PHYSICAL CONVERSION MACROS ****/
37218 +#define INVALID_P2M_ENTRY (~0UL)
37219 +#define FOREIGN_FRAME_BIT (1UL<<31)
37220 +#define FOREIGN_FRAME(m) ((m) | FOREIGN_FRAME_BIT)
37222 +/* Definitions for machine and pseudophysical addresses. */
37223 +#ifdef CONFIG_X86_PAE
37224 +typedef unsigned long long paddr_t;
37225 +typedef unsigned long long maddr_t;
37227 +typedef unsigned long paddr_t;
37228 +typedef unsigned long maddr_t;
37233 +extern unsigned long *phys_to_machine_mapping;
37234 +extern unsigned long max_mapnr;
37236 +#undef machine_to_phys_mapping
37237 +extern unsigned long *machine_to_phys_mapping;
37238 +extern unsigned int machine_to_phys_order;
37240 +static inline unsigned long pfn_to_mfn(unsigned long pfn)
37242 + if (xen_feature(XENFEAT_auto_translated_physmap))
37244 + BUG_ON(max_mapnr && pfn >= max_mapnr);
37245 + return phys_to_machine_mapping[pfn] & ~FOREIGN_FRAME_BIT;
37248 +static inline int phys_to_machine_mapping_valid(unsigned long pfn)
37250 + if (xen_feature(XENFEAT_auto_translated_physmap))
37252 + BUG_ON(max_mapnr && pfn >= max_mapnr);
37253 + return (phys_to_machine_mapping[pfn] != INVALID_P2M_ENTRY);
37256 +static inline unsigned long mfn_to_pfn(unsigned long mfn)
37258 + unsigned long pfn;
37260 + if (xen_feature(XENFEAT_auto_translated_physmap))
37263 + if (unlikely((mfn >> machine_to_phys_order) != 0))
37264 + return max_mapnr;
37266 + /* The array access can fail (e.g., device space beyond end of RAM). */
37268 + "1: movl %1,%0\n"
37270 + ".section .fixup,\"ax\"\n"
37271 + "3: movl %2,%0\n"
37274 + ".section __ex_table,\"a\"\n"
37279 + : "m" (machine_to_phys_mapping[mfn]), "m" (max_mapnr) );
37285 + * We detect special mappings in one of two ways:
37286 + * 1. If the MFN is an I/O page then Xen will set the m2p entry
37287 + * to be outside our maximum possible pseudophys range.
37288 + * 2. If the MFN belongs to a different domain then we will certainly
37289 + * not have MFN in our p2m table. Conversely, if the page is ours,
37290 + * then we'll have p2m(m2p(MFN))==MFN.
37291 + * If we detect a special mapping then it doesn't have a 'struct page'.
37292 + * We force !pfn_valid() by returning an out-of-range pointer.
37294 + * NB. These checks require that, for any MFN that is not in our reservation,
37295 + * there is no PFN such that p2m(PFN) == MFN. Otherwise we can get confused if
37296 + * we are foreign-mapping the MFN, and the other domain as m2p(MFN) == PFN.
37297 + * Yikes! Various places must poke in INVALID_P2M_ENTRY for safety.
37299 + * NB2. When deliberately mapping foreign pages into the p2m table, you *must*
37300 + * use FOREIGN_FRAME(). This will cause pte_pfn() to choke on it, as we
37301 + * require. In all the cases we care about, the FOREIGN_FRAME bit is
37302 + * masked (e.g., pfn_to_mfn()) so behaviour there is correct.
37304 +static inline unsigned long mfn_to_local_pfn(unsigned long mfn)
37306 + unsigned long pfn = mfn_to_pfn(mfn);
37307 + if ((pfn < max_mapnr)
37308 + && !xen_feature(XENFEAT_auto_translated_physmap)
37309 + && (phys_to_machine_mapping[pfn] != mfn))
37310 + return max_mapnr; /* force !pfn_valid() */
37314 +static inline void set_phys_to_machine(unsigned long pfn, unsigned long mfn)
37316 + BUG_ON(max_mapnr && pfn >= max_mapnr);
37317 + if (xen_feature(XENFEAT_auto_translated_physmap)) {
37318 + BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY);
37321 + phys_to_machine_mapping[pfn] = mfn;
37324 +static inline maddr_t phys_to_machine(paddr_t phys)
37326 + maddr_t machine = pfn_to_mfn(phys >> PAGE_SHIFT);
37327 + machine = (machine << PAGE_SHIFT) | (phys & ~PAGE_MASK);
37331 +static inline paddr_t machine_to_phys(maddr_t machine)
37333 + paddr_t phys = mfn_to_pfn(machine >> PAGE_SHIFT);
37334 + phys = (phys << PAGE_SHIFT) | (machine & ~PAGE_MASK);
37338 +#ifdef CONFIG_X86_PAE
37339 +static inline paddr_t pte_phys_to_machine(paddr_t phys)
37342 + * In PAE mode, the NX bit needs to be dealt with in the value
37343 + * passed to pfn_to_mfn(). On x86_64, we need to mask it off,
37344 + * but for i386 the conversion to ulong for the argument will
37347 + maddr_t machine = pfn_to_mfn(phys >> PAGE_SHIFT);
37348 + machine = (machine << PAGE_SHIFT) | (phys & ~PHYSICAL_PAGE_MASK);
37352 +static inline paddr_t pte_machine_to_phys(maddr_t machine)
37355 + * In PAE mode, the NX bit needs to be dealt with in the value
37356 + * passed to mfn_to_pfn(). On x86_64, we need to mask it off,
37357 + * but for i386 the conversion to ulong for the argument will
37360 + paddr_t phys = mfn_to_pfn(machine >> PAGE_SHIFT);
37361 + phys = (phys << PAGE_SHIFT) | (machine & ~PHYSICAL_PAGE_MASK);
37366 +#ifdef CONFIG_X86_PAE
37367 +#define __pte_ma(x) ((pte_t) { (x), (maddr_t)(x) >> 32 } )
37368 +static inline pte_t pfn_pte_ma(unsigned long page_nr, pgprot_t pgprot)
37372 + pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
37373 + (pgprot_val(pgprot) >> 32);
37374 + pte.pte_high &= (__supported_pte_mask >> 32);
37375 + pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
37376 + __supported_pte_mask;
37380 +#define __pte_ma(x) ((pte_t) { (x) } )
37381 +#define pfn_pte_ma(pfn, prot) __pte_ma(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
37384 +#else /* !CONFIG_XEN */
37386 +#define pfn_to_mfn(pfn) (pfn)
37387 +#define mfn_to_pfn(mfn) (mfn)
37388 +#define mfn_to_local_pfn(mfn) (mfn)
37389 +#define set_phys_to_machine(pfn, mfn) ((void)0)
37390 +#define phys_to_machine_mapping_valid(pfn) (1)
37391 +#define phys_to_machine(phys) ((maddr_t)(phys))
37392 +#define machine_to_phys(mach) ((paddr_t)(mach))
37393 +#define pfn_pte_ma(pfn, prot) pfn_pte(pfn, prot)
37394 +#define __pte_ma(x) __pte(x)
37396 +#endif /* !CONFIG_XEN */
37398 +/* VIRT <-> MACHINE conversion */
37399 +#define virt_to_machine(v) (phys_to_machine(__pa(v)))
37400 +#define virt_to_mfn(v) (pfn_to_mfn(__pa(v) >> PAGE_SHIFT))
37401 +#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT))
37403 +#endif /* _I386_MADDR_H */
37404 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/mmu_context_32.h
37405 ===================================================================
37406 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
37407 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/mmu_context_32.h 2007-06-12 13:14:02.000000000 +0200
37409 +#ifndef __I386_SCHED_H
37410 +#define __I386_SCHED_H
37412 +#include <asm/desc.h>
37413 +#include <asm/atomic.h>
37414 +#include <asm/pgalloc.h>
37415 +#include <asm/tlbflush.h>
37418 + * Used for LDT copy/destruction.
37420 +int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
37421 +void destroy_context(struct mm_struct *mm);
37424 +static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
37426 +#if 0 /* XEN: no lazy tlb */
37427 + unsigned cpu = smp_processor_id();
37428 + if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
37429 + per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_LAZY;
37433 +#define prepare_arch_switch(next) __prepare_arch_switch()
37435 +static inline void __prepare_arch_switch(void)
37438 + * Save away %fs and %gs. No need to save %es and %ds, as those
37439 + * are always kernel segments while inside the kernel. Must
37440 + * happen before reload of cr3/ldt (i.e., not in __switch_to).
37442 + asm volatile ( "mov %%fs,%0 ; mov %%gs,%1"
37443 + : "=m" (current->thread.fs),
37444 + "=m" (current->thread.gs));
37445 + asm volatile ( "movl %0,%%fs ; movl %0,%%gs"
37449 +extern void mm_pin(struct mm_struct *mm);
37450 +extern void mm_unpin(struct mm_struct *mm);
37451 +void mm_pin_all(void);
37453 +static inline void switch_mm(struct mm_struct *prev,
37454 + struct mm_struct *next,
37455 + struct task_struct *tsk)
37457 + int cpu = smp_processor_id();
37458 + struct mmuext_op _op[2], *op = _op;
37460 + if (likely(prev != next)) {
37461 + BUG_ON(!xen_feature(XENFEAT_writable_page_tables) &&
37462 + !test_bit(PG_pinned, &virt_to_page(next->pgd)->flags));
37464 + /* stop flush ipis for the previous mm */
37465 + cpu_clear(cpu, prev->cpu_vm_mask);
37466 +#if 0 /* XEN: no lazy tlb */
37467 + per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK;
37468 + per_cpu(cpu_tlbstate, cpu).active_mm = next;
37470 + cpu_set(cpu, next->cpu_vm_mask);
37472 + /* Re-load page tables: load_cr3(next->pgd) */
37473 + op->cmd = MMUEXT_NEW_BASEPTR;
37474 + op->arg1.mfn = pfn_to_mfn(__pa(next->pgd) >> PAGE_SHIFT);
37478 + * load the LDT, if the LDT is different:
37480 + if (unlikely(prev->context.ldt != next->context.ldt)) {
37481 + /* load_LDT_nolock(&next->context, cpu) */
37482 + op->cmd = MMUEXT_SET_LDT;
37483 + op->arg1.linear_addr = (unsigned long)next->context.ldt;
37484 + op->arg2.nr_ents = next->context.size;
37488 + BUG_ON(HYPERVISOR_mmuext_op(_op, op-_op, NULL, DOMID_SELF));
37490 +#if 0 /* XEN: no lazy tlb */
37492 + per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK;
37493 + BUG_ON(per_cpu(cpu_tlbstate, cpu).active_mm != next);
37495 + if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
37496 + /* We were in lazy tlb mode and leave_mm disabled
37497 + * tlb flush IPI delivery. We must reload %cr3.
37499 + load_cr3(next->pgd);
37500 + load_LDT_nolock(&next->context, cpu);
37506 +#define deactivate_mm(tsk, mm) \
37507 + asm("movl %0,%%fs ; movl %0,%%gs": :"r" (0))
37509 +static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
37511 + if (!test_bit(PG_pinned, &virt_to_page(next->pgd)->flags))
37513 + switch_mm(prev, next, NULL);
37517 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/pci_32.h
37518 ===================================================================
37519 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
37520 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/pci_32.h 2007-09-14 11:14:51.000000000 +0200
37522 +#ifndef __i386_PCI_H
37523 +#define __i386_PCI_H
37527 +#include <linux/mm.h> /* for struct page */
37529 +/* Can be used to override the logic in pci_scan_bus for skipping
37530 + already-configured bus numbers - to be used for buggy BIOSes
37531 + or architectures with incomplete PCI setup by the loader */
37534 +extern unsigned int pcibios_assign_all_busses(void);
37536 +#define pcibios_assign_all_busses() 0
37539 +#include <asm/hypervisor.h>
37540 +#define pcibios_scan_all_fns(a, b) (!is_initial_xendomain())
37542 +extern unsigned long pci_mem_start;
37543 +#define PCIBIOS_MIN_IO 0x1000
37544 +#define PCIBIOS_MIN_MEM (pci_mem_start)
37546 +#define PCIBIOS_MIN_CARDBUS_IO 0x4000
37548 +void pcibios_config_init(void);
37549 +struct pci_bus * pcibios_scan_root(int bus);
37551 +void pcibios_set_master(struct pci_dev *dev);
37552 +void pcibios_penalize_isa_irq(int irq, int active);
37553 +struct irq_routing_table *pcibios_get_irq_routing_table(void);
37554 +int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
37556 +/* Dynamic DMA mapping stuff.
37557 + * i386 has everything mapped statically.
37560 +#include <linux/types.h>
37561 +#include <linux/slab.h>
37562 +#include <asm/scatterlist.h>
37563 +#include <linux/string.h>
37564 +#include <asm/io.h>
37568 +#ifdef CONFIG_SWIOTLB
37571 +/* On Xen we use SWIOTLB instead of blk-specific bounce buffers. */
37572 +#define PCI_DMA_BUS_IS_PHYS (0)
37574 +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
37575 + dma_addr_t ADDR_NAME;
37576 +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
37578 +#define pci_unmap_addr(PTR, ADDR_NAME) \
37579 + ((PTR)->ADDR_NAME)
37580 +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
37581 + (((PTR)->ADDR_NAME) = (VAL))
37582 +#define pci_unmap_len(PTR, LEN_NAME) \
37583 + ((PTR)->LEN_NAME)
37584 +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
37585 + (((PTR)->LEN_NAME) = (VAL))
37589 +/* The PCI address space does equal the physical memory
37590 + * address space. The networking and block device layers use
37591 + * this boolean for bounce buffer decisions.
37593 +#define PCI_DMA_BUS_IS_PHYS (1)
37595 +/* pci_unmap_{page,single} is a nop so... */
37596 +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
37597 +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
37598 +#define pci_unmap_addr(PTR, ADDR_NAME) (0)
37599 +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
37600 +#define pci_unmap_len(PTR, LEN_NAME) (0)
37601 +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
37605 +/* This is always fine. */
37606 +#define pci_dac_dma_supported(pci_dev, mask) (1)
37608 +static inline dma64_addr_t
37609 +pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction)
37611 + return ((dma64_addr_t) page_to_phys(page) +
37612 + (dma64_addr_t) offset);
37615 +static inline struct page *
37616 +pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
37618 + return pfn_to_page(dma_addr >> PAGE_SHIFT);
37621 +static inline unsigned long
37622 +pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
37624 + return (dma_addr & ~PAGE_MASK);
37627 +static inline void
37628 +pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
37632 +static inline void
37633 +pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
37635 + flush_write_buffers();
37638 +#define HAVE_PCI_MMAP
37639 +extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
37640 + enum pci_mmap_state mmap_state, int write_combine);
37643 +static inline void pcibios_add_platform_entries(struct pci_dev *dev)
37648 +static inline void pci_dma_burst_advice(struct pci_dev *pdev,
37649 + enum pci_dma_burst_strategy *strat,
37650 + unsigned long *strategy_parameter)
37652 + *strat = PCI_DMA_BURST_INFINITY;
37653 + *strategy_parameter = ~0UL;
37657 +#endif /* __KERNEL__ */
37659 +#ifdef CONFIG_XEN_PCIDEV_FRONTEND
37660 +#include <xen/pcifront.h>
37661 +#endif /* CONFIG_XEN_PCIDEV_FRONTEND */
37663 +/* implement the pci_ DMA API in terms of the generic device dma_ one */
37664 +#include <asm-generic/pci-dma-compat.h>
37666 +/* generic pci stuff */
37667 +#include <asm-generic/pci.h>
37669 +#endif /* __i386_PCI_H */
37670 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/pgalloc_32.h
37671 ===================================================================
37672 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
37673 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/pgalloc_32.h 2008-07-21 11:00:33.000000000 +0200
37675 +#ifndef _I386_PGALLOC_H
37676 +#define _I386_PGALLOC_H
37678 +#include <asm/fixmap.h>
37679 +#include <linux/threads.h>
37680 +#include <linux/mm.h> /* for struct page */
37681 +#include <asm/io.h> /* for phys_to_virt and page_to_pseudophys */
37683 +#define pmd_populate_kernel(mm, pmd, pte) \
37684 + set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
37686 +#define pmd_populate(mm, pmd, pte) \
37688 + unsigned long pfn = page_to_pfn(pte); \
37689 + if (test_bit(PG_pinned, &virt_to_page((mm)->pgd)->flags)) { \
37690 + if (!PageHighMem(pte)) \
37691 + BUG_ON(HYPERVISOR_update_va_mapping( \
37692 + (unsigned long)__va(pfn << PAGE_SHIFT), \
37693 + pfn_pte(pfn, PAGE_KERNEL_RO), 0)); \
37694 + else if (!test_and_set_bit(PG_pinned, &pte->flags)) \
37695 + kmap_flush_unused(); \
37697 + __pmd(_PAGE_TABLE + ((paddr_t)pfn << PAGE_SHIFT))); \
37699 + *(pmd) = __pmd(_PAGE_TABLE + ((paddr_t)pfn << PAGE_SHIFT)); \
37703 + * Allocate and free page tables.
37705 +extern pgd_t *pgd_alloc(struct mm_struct *);
37706 +extern void pgd_free(pgd_t *pgd);
37708 +extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
37709 +extern struct page *pte_alloc_one(struct mm_struct *, unsigned long);
37711 +static inline void pte_free_kernel(pte_t *pte)
37713 + make_lowmem_page_writable(pte, XENFEAT_writable_page_tables);
37714 + free_page((unsigned long)pte);
37717 +extern void pte_free(struct page *pte);
37719 +#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
37721 +#ifdef CONFIG_X86_PAE
37723 + * In the PAE case we free the pmds as part of the pgd.
37725 +#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
37726 +#define pmd_free(x) do { } while (0)
37727 +#define __pmd_free_tlb(tlb,x) do { } while (0)
37728 +#define pud_populate(mm, pmd, pte) BUG()
37731 +#define check_pgt_cache() do { } while (0)
37733 +#endif /* _I386_PGALLOC_H */
37734 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/pgtable-3level-defs.h
37735 ===================================================================
37736 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
37737 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/pgtable-3level-defs.h 2007-06-12 13:14:02.000000000 +0200
37739 +#ifndef _I386_PGTABLE_3LEVEL_DEFS_H
37740 +#define _I386_PGTABLE_3LEVEL_DEFS_H
37742 +#define HAVE_SHARED_KERNEL_PMD 0
37745 + * PGDIR_SHIFT determines what a top-level page table entry can map
37747 +#define PGDIR_SHIFT 30
37748 +#define PTRS_PER_PGD 4
37751 + * PMD_SHIFT determines the size of the area a middle-level
37752 + * page table can map
37754 +#define PMD_SHIFT 21
37755 +#define PTRS_PER_PMD 512
37758 + * entries per page directory level
37760 +#define PTRS_PER_PTE 512
37762 +#endif /* _I386_PGTABLE_3LEVEL_DEFS_H */
37763 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/pgtable-3level.h
37764 ===================================================================
37765 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
37766 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/pgtable-3level.h 2008-04-02 12:34:02.000000000 +0200
37768 +#ifndef _I386_PGTABLE_3LEVEL_H
37769 +#define _I386_PGTABLE_3LEVEL_H
37771 +#include <asm-generic/pgtable-nopud.h>
37774 + * Intel Physical Address Extension (PAE) Mode - three-level page
37775 + * tables on PPro+ CPUs.
37777 + * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
37780 +#define pte_ERROR(e) \
37781 + printk("%s:%d: bad pte %p(%016Lx pfn %08lx).\n", __FILE__, __LINE__, \
37782 + &(e), __pte_val(e), pte_pfn(e))
37783 +#define pmd_ERROR(e) \
37784 + printk("%s:%d: bad pmd %p(%016Lx pfn %08Lx).\n", __FILE__, __LINE__, \
37785 + &(e), __pmd_val(e), (pmd_val(e) & PTE_MASK) >> PAGE_SHIFT)
37786 +#define pgd_ERROR(e) \
37787 + printk("%s:%d: bad pgd %p(%016Lx pfn %08Lx).\n", __FILE__, __LINE__, \
37788 + &(e), __pgd_val(e), (pgd_val(e) & PTE_MASK) >> PAGE_SHIFT)
37790 +#define pud_none(pud) 0
37791 +#define pud_bad(pud) 0
37792 +#define pud_present(pud) 1
37795 + * Is the pte executable?
37797 +static inline int pte_x(pte_t pte)
37799 + return !(__pte_val(pte) & _PAGE_NX);
37803 + * All present user-pages with !NX bit are user-executable:
37805 +static inline int pte_exec(pte_t pte)
37807 + return pte_user(pte) && pte_x(pte);
37810 + * All present pages with !NX bit are kernel-executable:
37812 +static inline int pte_exec_kernel(pte_t pte)
37814 + return pte_x(pte);
37817 +/* Rules for using set_pte: the pte being assigned *must* be
37818 + * either not present or in a state where the hardware will
37819 + * not attempt to update the pte. In places where this is
37820 + * not possible, use pte_get_and_clear to obtain the old pte
37821 + * value and then use set_pte to update it. -ben
37823 +#define __HAVE_ARCH_SET_PTE_ATOMIC
37825 +static inline void set_pte(pte_t *ptep, pte_t pte)
37827 + ptep->pte_high = pte.pte_high;
37829 + ptep->pte_low = pte.pte_low;
37831 +#define set_pte_atomic(pteptr,pteval) \
37832 + set_64bit((unsigned long long *)(pteptr),__pte_val(pteval))
37834 +#define set_pte_at(_mm,addr,ptep,pteval) do { \
37835 + if (((_mm) != current->mm && (_mm) != &init_mm) || \
37836 + HYPERVISOR_update_va_mapping((addr), (pteval), 0)) \
37837 + set_pte((ptep), (pteval)); \
37840 +#define set_pte_at_sync(_mm,addr,ptep,pteval) do { \
37841 + if (((_mm) != current->mm && (_mm) != &init_mm) || \
37842 + HYPERVISOR_update_va_mapping((addr), (pteval), UVMF_INVLPG)) { \
37843 + set_pte((ptep), (pteval)); \
37844 + xen_invlpg((addr)); \
37848 +#define set_pmd(pmdptr,pmdval) \
37849 + xen_l2_entry_update((pmdptr), (pmdval))
37850 +#define set_pud(pudptr,pudval) \
37851 + xen_l3_entry_update((pudptr), (pudval))
37854 + * Pentium-II erratum A13: in PAE mode we explicitly have to flush
37855 + * the TLB via cr3 if the top-level pgd is changed...
37856 + * We do not let the generic code free and clear pgd entries due to
37859 +static inline void pud_clear (pud_t * pud) { }
37861 +#define pud_page(pud) \
37862 +((struct page *) __va(pud_val(pud) & PAGE_MASK))
37864 +#define pud_page_kernel(pud) \
37865 +((unsigned long) __va(pud_val(pud) & PAGE_MASK))
37868 +/* Find an entry in the second-level page table.. */
37869 +#define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
37870 + pmd_index(address))
37872 +static inline int pte_none(pte_t pte)
37874 + return !(pte.pte_low | pte.pte_high);
37878 + * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
37879 + * entry, so clear the bottom half first and enforce ordering with a compiler
37882 +static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
37884 + if ((mm != current->mm && mm != &init_mm)
37885 + || HYPERVISOR_update_va_mapping(addr, __pte(0), 0)) {
37886 + ptep->pte_low = 0;
37888 + ptep->pte_high = 0;
37892 +#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
37894 +static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
37896 + pte_t pte = *ptep;
37897 + if (!pte_none(pte)) {
37898 + if ((mm != &init_mm) ||
37899 + HYPERVISOR_update_va_mapping(addr, __pte(0), 0)) {
37900 + uint64_t val = __pte_val(pte);
37901 + if (__cmpxchg64(ptep, val, 0) != val) {
37902 + /* xchg acts as a barrier before the setting of the high bits */
37903 + pte.pte_low = xchg(&ptep->pte_low, 0);
37904 + pte.pte_high = ptep->pte_high;
37905 + ptep->pte_high = 0;
37912 +#define ptep_clear_flush(vma, addr, ptep) \
37914 + pte_t *__ptep = (ptep); \
37915 + pte_t __res = *__ptep; \
37916 + if (!pte_none(__res) && \
37917 + ((vma)->vm_mm != current->mm || \
37918 + HYPERVISOR_update_va_mapping(addr, __pte(0), \
37919 + (unsigned long)(vma)->vm_mm->cpu_vm_mask.bits| \
37920 + UVMF_INVLPG|UVMF_MULTI))) { \
37921 + __ptep->pte_low = 0; \
37923 + __ptep->pte_high = 0; \
37924 + flush_tlb_page(vma, addr); \
37929 +static inline int pte_same(pte_t a, pte_t b)
37931 + return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
37934 +#define pte_page(x) pfn_to_page(pte_pfn(x))
37936 +#define __pte_mfn(_pte) (((_pte).pte_low >> PAGE_SHIFT) | \
37937 + ((_pte).pte_high << (32-PAGE_SHIFT)))
37938 +#define pte_mfn(_pte) ((_pte).pte_low & _PAGE_PRESENT ? \
37939 + __pte_mfn(_pte) : pfn_to_mfn(__pte_mfn(_pte)))
37940 +#define pte_pfn(_pte) ((_pte).pte_low & _PAGE_IO ? max_mapnr : \
37941 + (_pte).pte_low & _PAGE_PRESENT ? \
37942 + mfn_to_local_pfn(__pte_mfn(_pte)) : \
37945 +extern unsigned long long __supported_pte_mask;
37947 +static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
37949 + return __pte((((unsigned long long)page_nr << PAGE_SHIFT) |
37950 + pgprot_val(pgprot)) & __supported_pte_mask);
37953 +static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
37955 + return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) |
37956 + pgprot_val(pgprot)) & __supported_pte_mask);
37960 + * Bits 0, 6 and 7 are taken in the low part of the pte,
37961 + * put the 32 bits of offset into the high part.
37963 +#define pte_to_pgoff(pte) ((pte).pte_high)
37964 +#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
37965 +#define PTE_FILE_MAX_BITS 32
37967 +/* Encode and de-code a swap entry */
37968 +#define __swp_type(x) (((x).val) & 0x1f)
37969 +#define __swp_offset(x) ((x).val >> 5)
37970 +#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
37971 +#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
37972 +#define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
37974 +#define __pmd_free_tlb(tlb, x) do { } while (0)
37976 +void vmalloc_sync_all(void);
37978 +#endif /* _I386_PGTABLE_3LEVEL_H */
37979 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/pgtable_32.h
37980 ===================================================================
37981 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
37982 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/pgtable_32.h 2008-07-21 11:00:33.000000000 +0200
37984 +#ifndef _I386_PGTABLE_H
37985 +#define _I386_PGTABLE_H
37987 +#include <asm/hypervisor.h>
37990 + * The Linux memory management assumes a three-level page table setup. On
37991 + * the i386, we use that, but "fold" the mid level into the top-level page
37992 + * table, so that we physically have the same two-level page table as the
37993 + * i386 mmu expects.
37995 + * This file contains the functions and defines necessary to modify and use
37996 + * the i386 page table tree.
37998 +#ifndef __ASSEMBLY__
37999 +#include <asm/processor.h>
38000 +#include <asm/fixmap.h>
38001 +#include <linux/threads.h>
38003 +#ifndef _I386_BITOPS_H
38004 +#include <asm/bitops.h>
38007 +#include <linux/slab.h>
38008 +#include <linux/list.h>
38009 +#include <linux/spinlock.h>
38011 +/* Is this pagetable pinned? */
38012 +#define PG_pinned PG_arch_1
38015 +struct vm_area_struct;
38018 + * ZERO_PAGE is a global shared page that is always zero: used
38019 + * for zero-mapped memory areas etc..
38021 +#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
38022 +extern unsigned long empty_zero_page[1024];
38023 +extern pgd_t *swapper_pg_dir;
38024 +extern kmem_cache_t *pgd_cache;
38025 +extern kmem_cache_t *pmd_cache;
38026 +extern spinlock_t pgd_lock;
38027 +extern struct page *pgd_list;
38029 +void pmd_ctor(void *, kmem_cache_t *, unsigned long);
38030 +void pgd_ctor(void *, kmem_cache_t *, unsigned long);
38031 +void pgd_dtor(void *, kmem_cache_t *, unsigned long);
38032 +void pgtable_cache_init(void);
38033 +void paging_init(void);
38036 + * The Linux x86 paging architecture is 'compile-time dual-mode', it
38037 + * implements both the traditional 2-level x86 page tables and the
38038 + * newer 3-level PAE-mode page tables.
38040 +#ifdef CONFIG_X86_PAE
38041 +# include <asm/pgtable-3level-defs.h>
38042 +# define PMD_SIZE (1UL << PMD_SHIFT)
38043 +# define PMD_MASK (~(PMD_SIZE-1))
38045 +# include <asm/pgtable-2level-defs.h>
38048 +#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
38049 +#define PGDIR_MASK (~(PGDIR_SIZE-1))
38051 +#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
38052 +#define FIRST_USER_ADDRESS 0
38054 +#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
38055 +#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
38057 +#define TWOLEVEL_PGDIR_SHIFT 22
38058 +#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
38059 +#define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
38061 +/* Just any arbitrary offset to the start of the vmalloc VM area: the
38062 + * current 8MB value just means that there will be a 8MB "hole" after the
38063 + * physical memory until the kernel virtual memory starts. That means that
38064 + * any out-of-bounds memory accesses will hopefully be caught.
38065 + * The vmalloc() routines leaves a hole of 4kB between each vmalloced
38066 + * area for the same reason. ;)
38068 +#define VMALLOC_OFFSET (8*1024*1024)
38069 +#define VMALLOC_START (((unsigned long) high_memory + vmalloc_earlyreserve + \
38070 + 2*VMALLOC_OFFSET-1) & ~(VMALLOC_OFFSET-1))
38071 +#ifdef CONFIG_HIGHMEM
38072 +# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
38074 +# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
38078 + * _PAGE_PSE set in the page directory entry just means that
38079 + * the page directory entry points directly to a 4MB-aligned block of
38082 +#define _PAGE_BIT_PRESENT 0
38083 +#define _PAGE_BIT_RW 1
38084 +#define _PAGE_BIT_USER 2
38085 +#define _PAGE_BIT_PWT 3
38086 +#define _PAGE_BIT_PCD 4
38087 +#define _PAGE_BIT_ACCESSED 5
38088 +#define _PAGE_BIT_DIRTY 6
38089 +#define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */
38090 +#define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
38091 +/*#define _PAGE_BIT_UNUSED1 9*/ /* available for programmer */
38092 +#define _PAGE_BIT_UNUSED2 10
38093 +#define _PAGE_BIT_UNUSED3 11
38094 +#define _PAGE_BIT_NX 63
38096 +#define _PAGE_PRESENT 0x001
38097 +#define _PAGE_RW 0x002
38098 +#define _PAGE_USER 0x004
38099 +#define _PAGE_PWT 0x008
38100 +#define _PAGE_PCD 0x010
38101 +#define _PAGE_ACCESSED 0x020
38102 +#define _PAGE_DIRTY 0x040
38103 +#define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
38104 +#define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
38105 +/*#define _PAGE_UNUSED1 0x200*/ /* available for programmer */
38106 +#define _PAGE_UNUSED2 0x400
38107 +#define _PAGE_UNUSED3 0x800
38109 +/* If _PAGE_PRESENT is clear, we use these: */
38110 +#define _PAGE_FILE 0x040 /* nonlinear file mapping, saved PTE; unset:swap */
38111 +#define _PAGE_PROTNONE 0x080 /* if the user mapped it with PROT_NONE;
38112 + pte_present gives true */
38113 +#ifdef CONFIG_X86_PAE
38114 +#define _PAGE_NX (1ULL<<_PAGE_BIT_NX)
38116 +#define _PAGE_NX 0
38119 +/* Mapped page is I/O or foreign and has no associated page struct. */
38120 +#define _PAGE_IO 0x200
38122 +#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
38123 +#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
38124 +#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_IO)
38126 +#define PAGE_NONE \
38127 + __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
38128 +#define PAGE_SHARED \
38129 + __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
38131 +#define PAGE_SHARED_EXEC \
38132 + __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
38133 +#define PAGE_COPY_NOEXEC \
38134 + __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
38135 +#define PAGE_COPY_EXEC \
38136 + __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
38137 +#define PAGE_COPY \
38139 +#define PAGE_READONLY \
38140 + __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
38141 +#define PAGE_READONLY_EXEC \
38142 + __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
38144 +#define _PAGE_KERNEL \
38145 + (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX)
38146 +#define _PAGE_KERNEL_EXEC \
38147 + (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
38149 +extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
38150 +#define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
38151 +#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD)
38152 +#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
38153 +#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
38155 +#define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
38156 +#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
38157 +#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
38158 +#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
38159 +#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
38160 +#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
38163 + * The i386 can't do page protection for execute, and considers that
38164 + * the same are read. Also, write permissions imply read permissions.
38165 + * This is the closest we can get..
38167 +#define __P000 PAGE_NONE
38168 +#define __P001 PAGE_READONLY
38169 +#define __P010 PAGE_COPY
38170 +#define __P011 PAGE_COPY
38171 +#define __P100 PAGE_READONLY_EXEC
38172 +#define __P101 PAGE_READONLY_EXEC
38173 +#define __P110 PAGE_COPY_EXEC
38174 +#define __P111 PAGE_COPY_EXEC
38176 +#define __S000 PAGE_NONE
38177 +#define __S001 PAGE_READONLY
38178 +#define __S010 PAGE_SHARED
38179 +#define __S011 PAGE_SHARED
38180 +#define __S100 PAGE_READONLY_EXEC
38181 +#define __S101 PAGE_READONLY_EXEC
38182 +#define __S110 PAGE_SHARED_EXEC
38183 +#define __S111 PAGE_SHARED_EXEC
38186 + * Define this if things work differently on an i386 and an i486:
38187 + * it will (on an i486) warn about kernel memory accesses that are
38188 + * done without a 'access_ok(VERIFY_WRITE,..)'
38190 +#undef TEST_ACCESS_OK
38192 +/* The boot page tables (all created as a single array) */
38193 +extern unsigned long pg0[];
38195 +#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
38197 +/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
38198 +#define pmd_none(x) (!(unsigned long)__pmd_val(x))
38199 +#if CONFIG_XEN_COMPAT <= 0x030002
38200 +/* pmd_present doesn't just test the _PAGE_PRESENT bit since wr.p.t.
38201 + can temporarily clear it. */
38202 +#define pmd_present(x) (__pmd_val(x))
38203 +#define pmd_bad(x) ((__pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER & ~_PAGE_PRESENT)) != (_KERNPG_TABLE & ~_PAGE_PRESENT))
38205 +#define pmd_present(x) (__pmd_val(x) & _PAGE_PRESENT)
38206 +#define pmd_bad(x) ((__pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
38210 +#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
38213 + * The following only work if pte_present() is true.
38214 + * Undefined behaviour if not..
38216 +static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
38217 +static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
38218 +static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; }
38219 +static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
38220 +static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; }
38221 +static inline int pte_huge(pte_t pte) { return (pte).pte_low & _PAGE_PSE; }
38224 + * The following only works if pte_present() is not true.
38226 +static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; }
38228 +static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
38229 +static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
38230 +static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
38231 +static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
38232 +static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; }
38233 +static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
38234 +static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
38235 +static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
38236 +static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
38237 +static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
38238 +static inline pte_t pte_mkhuge(pte_t pte) { (pte).pte_low |= _PAGE_PSE; return pte; }
38240 +#ifdef CONFIG_X86_PAE
38241 +# include <asm/pgtable-3level.h>
38243 +# include <asm/pgtable-2level.h>
38246 +#define ptep_test_and_clear_dirty(vma, addr, ptep) \
38248 + pte_t __pte = *(ptep); \
38249 + int __ret = pte_dirty(__pte); \
38251 + __pte = pte_mkclean(__pte); \
38252 + if ((vma)->vm_mm != current->mm || \
38253 + HYPERVISOR_update_va_mapping(addr, __pte, 0)) \
38254 + (ptep)->pte_low = __pte.pte_low; \
38259 +#define ptep_test_and_clear_young(vma, addr, ptep) \
38261 + pte_t __pte = *(ptep); \
38262 + int __ret = pte_young(__pte); \
38264 + __pte = pte_mkold(__pte); \
38265 + if ((vma)->vm_mm != current->mm || \
38266 + HYPERVISOR_update_va_mapping(addr, __pte, 0)) \
38267 + (ptep)->pte_low = __pte.pte_low; \
38271 +#define ptep_get_and_clear_full(mm, addr, ptep, full) \
38273 + pte_t __res = *(ptep); \
38274 + if (test_bit(PG_pinned, &virt_to_page((mm)->pgd)->flags)) \
38275 + xen_l1_entry_update(ptep, __pte(0)); \
38277 + *(ptep) = __pte(0); \
38280 + ptep_get_and_clear(mm, addr, ptep))
38282 +static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
38284 + pte_t pte = *ptep;
38285 + if (pte_write(pte))
38286 + set_pte_at(mm, addr, ptep, pte_wrprotect(pte));
38290 + * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
38292 + * dst - pointer to pgd range anwhere on a pgd page
38294 + * count - the number of pgds to copy.
38296 + * dst and src can be on the same page, but the range must not overlap,
38297 + * and must not cross a page boundary.
38299 +static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
38301 + memcpy(dst, src, count * sizeof(pgd_t));
38305 + * Macro to mark a page protection value as "uncacheable". On processors which do not support
38306 + * it, this is a no-op.
38308 +#define pgprot_noncached(prot) ((boot_cpu_data.x86 > 3) \
38309 + ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
38312 + * Conversion functions: convert a page and protection to a page entry,
38313 + * and a page entry and page directory to the page they refer to.
38316 +#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
38318 +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
38321 + * Since this might change the present bit (which controls whether
38322 + * a pte_t object has undergone p2m translation), we must use
38323 + * pte_val() on the input pte and __pte() for the return value.
38325 + paddr_t pteval = pte_val(pte);
38327 + pteval &= _PAGE_CHG_MASK;
38328 + pteval |= pgprot_val(newprot);
38329 +#ifdef CONFIG_X86_PAE
38330 + pteval &= __supported_pte_mask;
38332 + return __pte(pteval);
38335 +#define pmd_large(pmd) \
38336 +((__pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
38339 + * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
38341 + * this macro returns the index of the entry in the pgd page which would
38342 + * control the given virtual address
38344 +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
38345 +#define pgd_index_k(addr) pgd_index(addr)
38348 + * pgd_offset() returns a (pgd_t *)
38349 + * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
38351 +#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
38354 + * a shortcut which implies the use of the kernel's pgd, instead
38357 +#define pgd_offset_k(address) pgd_offset(&init_mm, address)
38360 + * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
38362 + * this macro returns the index of the entry in the pmd page which would
38363 + * control the given virtual address
38365 +#define pmd_index(address) \
38366 + (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
38369 + * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
38371 + * this macro returns the index of the entry in the pte page which would
38372 + * control the given virtual address
38374 +#define pte_index(address) \
38375 + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
38376 +#define pte_offset_kernel(dir, address) \
38377 + ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
38379 +#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
38381 +#define pmd_page_kernel(pmd) \
38382 + ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
38385 + * Helper function that returns the kernel pagetable entry controlling
38386 + * the virtual address 'address'. NULL means no pagetable entry present.
38387 + * NOTE: the return type is pte_t but if the pmd is PSE then we return it
38390 +extern pte_t *lookup_address(unsigned long address);
38393 + * Make a given kernel text page executable/non-executable.
38394 + * Returns the previous executability setting of that page (which
38395 + * is used to restore the previous state). Used by the SMP bootup code.
38396 + * NOTE: this is an __init function for security reasons.
38398 +#ifdef CONFIG_X86_PAE
38399 + extern int set_kernel_exec(unsigned long vaddr, int enable);
38401 + static inline int set_kernel_exec(unsigned long vaddr, int enable) { return 0;}
38404 +extern void noexec_setup(const char *str);
38406 +#if defined(CONFIG_HIGHPTE)
38407 +#define pte_offset_map(dir, address) \
38408 + ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE0) + \
38409 + pte_index(address))
38410 +#define pte_offset_map_nested(dir, address) \
38411 + ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE1) + \
38412 + pte_index(address))
38413 +#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
38414 +#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
38416 +#define pte_offset_map(dir, address) \
38417 + ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
38418 +#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
38419 +#define pte_unmap(pte) do { } while (0)
38420 +#define pte_unmap_nested(pte) do { } while (0)
38423 +#define __HAVE_ARCH_PTEP_ESTABLISH
38424 +#define ptep_establish(vma, address, ptep, pteval) \
38426 + if ( likely((vma)->vm_mm == current->mm) ) { \
38427 + BUG_ON(HYPERVISOR_update_va_mapping(address, \
38429 + (unsigned long)(vma)->vm_mm->cpu_vm_mask.bits| \
38430 + UVMF_INVLPG|UVMF_MULTI)); \
38432 + xen_l1_entry_update(ptep, pteval); \
38433 + flush_tlb_page(vma, address); \
38438 + * The i386 doesn't have any external MMU info: the kernel page
38439 + * tables contain all the necessary information.
38441 + * Also, we only update the dirty/accessed state if we set
38442 + * the dirty bit by hand in the kernel, since the hardware
38443 + * will do the accessed bit for us, and we don't want to
38444 + * race with other CPU's that might be updating the dirty
38445 + * bit at the same time.
38447 +#define update_mmu_cache(vma,address,pte) do { } while (0)
38448 +#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
38449 +#define ptep_set_access_flags(vma, address, ptep, entry, dirty) \
38452 + ptep_establish(vma, address, ptep, entry); \
38455 +#include <xen/features.h>
38456 +void make_lowmem_page_readonly(void *va, unsigned int feature);
38457 +void make_lowmem_page_writable(void *va, unsigned int feature);
38458 +void make_page_readonly(void *va, unsigned int feature);
38459 +void make_page_writable(void *va, unsigned int feature);
38460 +void make_pages_readonly(void *va, unsigned int nr, unsigned int feature);
38461 +void make_pages_writable(void *va, unsigned int nr, unsigned int feature);
38463 +#define virt_to_ptep(va) \
38465 + pte_t *__ptep = lookup_address((unsigned long)(va)); \
38466 + BUG_ON(!__ptep || !pte_present(*__ptep)); \
38470 +#define arbitrary_virt_to_machine(va) \
38471 + (((maddr_t)pte_mfn(*virt_to_ptep(va)) << PAGE_SHIFT) \
38472 + | ((unsigned long)(va) & (PAGE_SIZE - 1)))
38474 +#endif /* !__ASSEMBLY__ */
38476 +#ifdef CONFIG_FLATMEM
38477 +#define kern_addr_valid(addr) (1)
38478 +#endif /* CONFIG_FLATMEM */
38480 +int direct_remap_pfn_range(struct vm_area_struct *vma,
38481 + unsigned long address,
38482 + unsigned long mfn,
38483 + unsigned long size,
38486 +int direct_kernel_remap_pfn_range(unsigned long address,
38487 + unsigned long mfn,
38488 + unsigned long size,
38491 +int create_lookup_pte_addr(struct mm_struct *mm,
38492 + unsigned long address,
38494 +int touch_pte_range(struct mm_struct *mm,
38495 + unsigned long address,
38496 + unsigned long size);
38498 +int xen_change_pte_range(struct mm_struct *mm, pmd_t *pmd,
38499 + unsigned long addr, unsigned long end, pgprot_t newprot);
38501 +#define arch_change_pte_range(mm, pmd, addr, end, newprot) \
38502 + xen_change_pte_range(mm, pmd, addr, end, newprot)
38504 +#define io_remap_pfn_range(vma,from,pfn,size,prot) \
38505 +direct_remap_pfn_range(vma,from,pfn,size,prot,DOMID_IO)
38507 +#define MK_IOSPACE_PFN(space, pfn) (pfn)
38508 +#define GET_IOSPACE(pfn) 0
38509 +#define GET_PFN(pfn) (pfn)
38511 +#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
38512 +#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
38513 +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
38514 +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
38515 +#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
38516 +#define __HAVE_ARCH_PTEP_SET_WRPROTECT
38517 +#define __HAVE_ARCH_PTE_SAME
38518 +#include <asm-generic/pgtable.h>
38520 +#endif /* _I386_PGTABLE_H */
38521 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/processor_32.h
38522 ===================================================================
38523 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
38524 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/processor_32.h 2008-01-28 12:24:19.000000000 +0100
38527 + * include/asm-i386/processor.h
38529 + * Copyright (C) 1994 Linus Torvalds
38532 +#ifndef __ASM_I386_PROCESSOR_H
38533 +#define __ASM_I386_PROCESSOR_H
38535 +#include <asm/vm86.h>
38536 +#include <asm/math_emu.h>
38537 +#include <asm/segment.h>
38538 +#include <asm/page.h>
38539 +#include <asm/types.h>
38540 +#include <asm/sigcontext.h>
38541 +#include <asm/cpufeature.h>
38542 +#include <asm/msr.h>
38543 +#include <asm/system.h>
38544 +#include <linux/cache.h>
38545 +#include <linux/threads.h>
38546 +#include <asm/percpu.h>
38547 +#include <linux/cpumask.h>
38548 +#include <xen/interface/physdev.h>
38550 +/* flag for disabling the tsc */
38551 +extern int tsc_disable;
38553 +struct desc_struct {
38554 + unsigned long a,b;
38557 +#define desc_empty(desc) \
38558 + (!((desc)->a | (desc)->b))
38560 +#define desc_equal(desc1, desc2) \
38561 + (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
38563 + * Default implementation of macro that returns current
38564 + * instruction pointer ("program counter").
38566 +#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
38569 + * CPU type and hardware bug flags. Kept separately for each CPU.
38570 + * Members of this structure are referenced in head.S, so think twice
38571 + * before touching them. [mj]
38574 +struct cpuinfo_x86 {
38575 + __u8 x86; /* CPU family */
38576 + __u8 x86_vendor; /* CPU vendor */
38579 + char wp_works_ok; /* It doesn't on 386's */
38580 + char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
38583 + int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
38584 + unsigned long x86_capability[NCAPINTS];
38585 + char x86_vendor_id[16];
38586 + char x86_model_id[64];
38587 + int x86_cache_size; /* in KB - valid for CPUS which support this
38589 + int x86_cache_alignment; /* In bytes */
38595 + unsigned long loops_per_jiffy;
38597 + cpumask_t llc_shared_map; /* cpus sharing the last level cache */
38599 + unsigned char x86_max_cores; /* cpuid returned max cores value */
38600 + unsigned char apicid;
38602 + unsigned char booted_cores; /* number of cores as seen by OS */
38603 + __u8 phys_proc_id; /* Physical processor id. */
38604 + __u8 cpu_core_id; /* Core id */
38606 +} __attribute__((__aligned__(SMP_CACHE_BYTES)));
38608 +#define X86_VENDOR_INTEL 0
38609 +#define X86_VENDOR_CYRIX 1
38610 +#define X86_VENDOR_AMD 2
38611 +#define X86_VENDOR_UMC 3
38612 +#define X86_VENDOR_NEXGEN 4
38613 +#define X86_VENDOR_CENTAUR 5
38614 +#define X86_VENDOR_RISE 6
38615 +#define X86_VENDOR_TRANSMETA 7
38616 +#define X86_VENDOR_NSC 8
38617 +#define X86_VENDOR_NUM 9
38618 +#define X86_VENDOR_UNKNOWN 0xff
38621 + * capabilities of CPUs
38624 +extern struct cpuinfo_x86 boot_cpu_data;
38625 +extern struct cpuinfo_x86 new_cpu_data;
38626 +#ifndef CONFIG_X86_NO_TSS
38627 +extern struct tss_struct doublefault_tss;
38628 +DECLARE_PER_CPU(struct tss_struct, init_tss);
38632 +extern struct cpuinfo_x86 cpu_data[];
38633 +#define current_cpu_data cpu_data[smp_processor_id()]
38635 +#define cpu_data (&boot_cpu_data)
38636 +#define current_cpu_data boot_cpu_data
38639 +extern int cpu_llc_id[NR_CPUS];
38640 +extern char ignore_fpu_irq;
38642 +extern void identify_cpu(struct cpuinfo_x86 *);
38643 +extern void print_cpu_info(struct cpuinfo_x86 *);
38644 +extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
38645 +extern unsigned short num_cache_leaves;
38647 +#ifdef CONFIG_X86_HT
38648 +extern void detect_ht(struct cpuinfo_x86 *c);
38650 +static inline void detect_ht(struct cpuinfo_x86 *c) {}
38656 +#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
38657 +#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
38658 +#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
38659 +#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
38660 +#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
38661 +#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
38662 +#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
38663 +#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
38664 +#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
38665 +#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
38666 +#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
38667 +#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
38668 +#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
38669 +#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
38670 +#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
38671 +#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
38672 +#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
38675 + * Generic CPUID function
38676 + * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
38677 + * resulting in stale register contents being returned.
38679 +static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
38681 + __asm__(XEN_CPUID
38686 + : "0" (op), "c"(0));
38689 +/* Some CPUID calls want 'count' to be placed in ecx */
38690 +static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
38693 + __asm__(XEN_CPUID
38698 + : "0" (op), "c" (count));
38702 + * CPUID functions returning a single datum
38704 +static inline unsigned int cpuid_eax(unsigned int op)
38706 + unsigned int eax;
38708 + __asm__(XEN_CPUID
38711 + : "bx", "cx", "dx");
38714 +static inline unsigned int cpuid_ebx(unsigned int op)
38716 + unsigned int eax, ebx;
38718 + __asm__(XEN_CPUID
38719 + : "=a" (eax), "=b" (ebx)
38724 +static inline unsigned int cpuid_ecx(unsigned int op)
38726 + unsigned int eax, ecx;
38728 + __asm__(XEN_CPUID
38729 + : "=a" (eax), "=c" (ecx)
38734 +static inline unsigned int cpuid_edx(unsigned int op)
38736 + unsigned int eax, edx;
38738 + __asm__(XEN_CPUID
38739 + : "=a" (eax), "=d" (edx)
38745 +#define load_cr3(pgdir) write_cr3(__pa(pgdir))
38748 + * Intel CPU features in CR4
38750 +#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
38751 +#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
38752 +#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
38753 +#define X86_CR4_DE 0x0008 /* enable debugging extensions */
38754 +#define X86_CR4_PSE 0x0010 /* enable page size extensions */
38755 +#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
38756 +#define X86_CR4_MCE 0x0040 /* Machine check enable */
38757 +#define X86_CR4_PGE 0x0080 /* enable global pages */
38758 +#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
38759 +#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
38760 +#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
38763 + * Save the cr4 feature set we're using (ie
38764 + * Pentium 4MB enable and PPro Global page
38765 + * enable), so that any CPU's that boot up
38766 + * after us can get the correct flags.
38768 +extern unsigned long mmu_cr4_features;
38770 +static inline void set_in_cr4 (unsigned long mask)
38773 + mmu_cr4_features |= mask;
38774 + cr4 = read_cr4();
38779 +static inline void clear_in_cr4 (unsigned long mask)
38782 + mmu_cr4_features &= ~mask;
38783 + cr4 = read_cr4();
38789 + * NSC/Cyrix CPU configuration register indexes
38792 +#define CX86_PCR0 0x20
38793 +#define CX86_GCR 0xb8
38794 +#define CX86_CCR0 0xc0
38795 +#define CX86_CCR1 0xc1
38796 +#define CX86_CCR2 0xc2
38797 +#define CX86_CCR3 0xc3
38798 +#define CX86_CCR4 0xe8
38799 +#define CX86_CCR5 0xe9
38800 +#define CX86_CCR6 0xea
38801 +#define CX86_CCR7 0xeb
38802 +#define CX86_PCR1 0xf0
38803 +#define CX86_DIR0 0xfe
38804 +#define CX86_DIR1 0xff
38805 +#define CX86_ARR_BASE 0xc4
38806 +#define CX86_RCR_BASE 0xdc
38809 + * NSC/Cyrix CPU indexed register access macros
38812 +#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
38814 +#define setCx86(reg, data) do { \
38815 + outb((reg), 0x22); \
38816 + outb((data), 0x23); \
38819 +/* Stop speculative execution */
38820 +static inline void sync_core(void)
38823 + asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
38826 +static inline void __monitor(const void *eax, unsigned long ecx,
38827 + unsigned long edx)
38829 + /* "monitor %eax,%ecx,%edx;" */
38831 + ".byte 0x0f,0x01,0xc8;"
38832 + : :"a" (eax), "c" (ecx), "d"(edx));
38835 +static inline void __mwait(unsigned long eax, unsigned long ecx)
38837 + /* "mwait %eax,%ecx;" */
38839 + ".byte 0x0f,0x01,0xc9;"
38840 + : :"a" (eax), "c" (ecx));
38843 +/* from system description table in BIOS. Mostly for MCA use, but
38844 +others may find it useful. */
38845 +extern unsigned int machine_id;
38846 +extern unsigned int machine_submodel_id;
38847 +extern unsigned int BIOS_revision;
38848 +extern unsigned int mca_pentium_flag;
38850 +/* Boot loader type from the setup header */
38851 +extern int bootloader_type;
38854 + * User space process size: 3GB (default).
38856 +#define TASK_SIZE (PAGE_OFFSET)
38858 +/* This decides where the kernel will search for a free chunk of vm
38859 + * space during mmap's.
38861 +#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
38863 +#define HAVE_ARCH_PICK_MMAP_LAYOUT
38866 + * Size of io_bitmap.
38868 +#define IO_BITMAP_BITS 65536
38869 +#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
38870 +#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
38871 +#ifndef CONFIG_X86_NO_TSS
38872 +#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
38874 +#define INVALID_IO_BITMAP_OFFSET 0x8000
38875 +#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
38877 +struct i387_fsave_struct {
38885 + long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
38886 + long status; /* software status information */
38889 +struct i387_fxsave_struct {
38890 + unsigned short cwd;
38891 + unsigned short swd;
38892 + unsigned short twd;
38893 + unsigned short fop;
38900 + long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
38901 + long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
38902 + long padding[56];
38903 +} __attribute__ ((aligned (16)));
38905 +struct i387_soft_struct {
38913 + long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
38914 + unsigned char ftop, changed, lookahead, no_update, rm, alimit;
38915 + struct info *info;
38916 + unsigned long entry_eip;
38919 +union i387_union {
38920 + struct i387_fsave_struct fsave;
38921 + struct i387_fxsave_struct fxsave;
38922 + struct i387_soft_struct soft;
38926 + unsigned long seg;
38929 +struct thread_struct;
38931 +#ifndef CONFIG_X86_NO_TSS
38932 +struct tss_struct {
38933 + unsigned short back_link,__blh;
38934 + unsigned long esp0;
38935 + unsigned short ss0,__ss0h;
38936 + unsigned long esp1;
38937 + unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
38938 + unsigned long esp2;
38939 + unsigned short ss2,__ss2h;
38940 + unsigned long __cr3;
38941 + unsigned long eip;
38942 + unsigned long eflags;
38943 + unsigned long eax,ecx,edx,ebx;
38944 + unsigned long esp;
38945 + unsigned long ebp;
38946 + unsigned long esi;
38947 + unsigned long edi;
38948 + unsigned short es, __esh;
38949 + unsigned short cs, __csh;
38950 + unsigned short ss, __ssh;
38951 + unsigned short ds, __dsh;
38952 + unsigned short fs, __fsh;
38953 + unsigned short gs, __gsh;
38954 + unsigned short ldt, __ldth;
38955 + unsigned short trace, io_bitmap_base;
38957 + * The extra 1 is there because the CPU will access an
38958 + * additional byte beyond the end of the IO permission
38959 + * bitmap. The extra byte must be all 1 bits, and must
38960 + * be within the limit.
38962 + unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
38964 + * Cache the current maximum and the last task that used the bitmap:
38966 + unsigned long io_bitmap_max;
38967 + struct thread_struct *io_bitmap_owner;
38969 + * pads the TSS to be cacheline-aligned (size is 0x100)
38971 + unsigned long __cacheline_filler[35];
38973 + * .. and then another 0x100 bytes for emergency kernel stack
38975 + unsigned long stack[64];
38976 +} __attribute__((packed));
38979 +#define ARCH_MIN_TASKALIGN 16
38981 +struct thread_struct {
38982 +/* cached TLS descriptors. */
38983 + struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
38984 + unsigned long esp0;
38985 + unsigned long sysenter_cs;
38986 + unsigned long eip;
38987 + unsigned long esp;
38988 + unsigned long fs;
38989 + unsigned long gs;
38990 +/* Hardware debugging registers */
38991 + unsigned long debugreg[8]; /* %%db0-7 debug registers */
38993 + unsigned long cr2, trap_no, error_code;
38994 +/* floating point info */
38995 + union i387_union i387;
38996 +/* virtual 86 mode info */
38997 + struct vm86_struct __user * vm86_info;
38998 + unsigned long screen_bitmap;
38999 + unsigned long v86flags, v86mask, saved_esp0;
39000 + unsigned int saved_fs, saved_gs;
39001 +/* IO permissions */
39002 + unsigned long *io_bitmap_ptr;
39003 + unsigned long iopl;
39004 +/* max allowed port in the bitmap, in bytes: */
39005 + unsigned long io_bitmap_max;
39008 +#define INIT_THREAD { \
39009 + .vm86_info = NULL, \
39010 + .sysenter_cs = __KERNEL_CS, \
39011 + .io_bitmap_ptr = NULL, \
39014 +#ifndef CONFIG_X86_NO_TSS
39016 + * Note that the .io_bitmap member must be extra-big. This is because
39017 + * the CPU will access an additional byte beyond the end of the IO
39018 + * permission bitmap. The extra byte must be all 1 bits, and must
39019 + * be within the limit.
39021 +#define INIT_TSS { \
39022 + .esp0 = sizeof(init_stack) + (long)&init_stack, \
39023 + .ss0 = __KERNEL_DS, \
39024 + .ss1 = __KERNEL_CS, \
39025 + .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
39026 + .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
39029 +static inline void __load_esp0(struct tss_struct *tss, struct thread_struct *thread)
39031 + tss->esp0 = thread->esp0;
39032 + /* This can only happen when SEP is enabled, no need to test "SEP"arately */
39033 + if (unlikely(tss->ss1 != thread->sysenter_cs)) {
39034 + tss->ss1 = thread->sysenter_cs;
39035 + wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
39038 +#define load_esp0(tss, thread) \
39039 + __load_esp0(tss, thread)
39041 +#define load_esp0(tss, thread) do { \
39042 + if (HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->esp0)) \
39047 +#define start_thread(regs, new_eip, new_esp) do { \
39048 + __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
39049 + set_fs(USER_DS); \
39050 + regs->xds = __USER_DS; \
39051 + regs->xes = __USER_DS; \
39052 + regs->xss = __USER_DS; \
39053 + regs->xcs = __USER_CS; \
39054 + regs->eip = new_eip; \
39055 + regs->esp = new_esp; \
39059 + * These special macros can be used to get or set a debugging register
39061 +#define get_debugreg(var, register) \
39062 + (var) = HYPERVISOR_get_debugreg((register))
39063 +#define set_debugreg(value, register) \
39064 + WARN_ON(HYPERVISOR_set_debugreg((register), (value)))
39067 + * Set IOPL bits in EFLAGS from given mask
39069 +static inline void set_iopl_mask(unsigned mask)
39071 + struct physdev_set_iopl set_iopl;
39073 + /* Force the change at ring 0. */
39074 + set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
39075 + WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl));
39078 +/* Forward declaration, a strange C thing */
39079 +struct task_struct;
39082 +/* Free all resources held by a thread. */
39083 +extern void release_thread(struct task_struct *);
39085 +/* Prepare to copy thread state - unlazy all lazy status */
39086 +extern void prepare_to_copy(struct task_struct *tsk);
39089 + * create a kernel thread without removing it from tasklists
39091 +extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
39093 +extern unsigned long thread_saved_pc(struct task_struct *tsk);
39094 +void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
39096 +unsigned long get_wchan(struct task_struct *p);
39098 +#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
39099 +#define KSTK_TOP(info) \
39101 + unsigned long *__ptr = (unsigned long *)(info); \
39102 + (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
39106 + * The below -8 is to reserve 8 bytes on top of the ring0 stack.
39107 + * This is necessary to guarantee that the entire "struct pt_regs"
39108 + * is accessable even if the CPU haven't stored the SS/ESP registers
39109 + * on the stack (interrupt gate does not save these registers
39110 + * when switching to the same priv ring).
39111 + * Therefore beware: accessing the xss/esp fields of the
39112 + * "struct pt_regs" is possible, but they may contain the
39113 + * completely wrong values.
39115 +#define task_pt_regs(task) \
39117 + struct pt_regs *__regs__; \
39118 + __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
39122 +#define KSTK_EIP(task) (task_pt_regs(task)->eip)
39123 +#define KSTK_ESP(task) (task_pt_regs(task)->esp)
39126 +struct microcode_header {
39127 + unsigned int hdrver;
39128 + unsigned int rev;
39129 + unsigned int date;
39130 + unsigned int sig;
39131 + unsigned int cksum;
39132 + unsigned int ldrver;
39134 + unsigned int datasize;
39135 + unsigned int totalsize;
39136 + unsigned int reserved[3];
39139 +struct microcode {
39140 + struct microcode_header hdr;
39141 + unsigned int bits[0];
39144 +typedef struct microcode microcode_t;
39145 +typedef struct microcode_header microcode_header_t;
39147 +/* microcode format is extended from prescott processors */
39148 +struct extended_signature {
39149 + unsigned int sig;
39151 + unsigned int cksum;
39154 +struct extended_sigtable {
39155 + unsigned int count;
39156 + unsigned int cksum;
39157 + unsigned int reserved[3];
39158 + struct extended_signature sigs[0];
39161 +/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
39162 +static inline void rep_nop(void)
39164 + __asm__ __volatile__("rep;nop": : :"memory");
39167 +#define cpu_relax() rep_nop()
39169 +/* generic versions from gas */
39170 +#define GENERIC_NOP1 ".byte 0x90\n"
39171 +#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
39172 +#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
39173 +#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
39174 +#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
39175 +#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
39176 +#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
39177 +#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
39179 +/* Opteron nops */
39180 +#define K8_NOP1 GENERIC_NOP1
39181 +#define K8_NOP2 ".byte 0x66,0x90\n"
39182 +#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
39183 +#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
39184 +#define K8_NOP5 K8_NOP3 K8_NOP2
39185 +#define K8_NOP6 K8_NOP3 K8_NOP3
39186 +#define K8_NOP7 K8_NOP4 K8_NOP3
39187 +#define K8_NOP8 K8_NOP4 K8_NOP4
39190 +/* uses eax dependencies (arbitary choice) */
39191 +#define K7_NOP1 GENERIC_NOP1
39192 +#define K7_NOP2 ".byte 0x8b,0xc0\n"
39193 +#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
39194 +#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
39195 +#define K7_NOP5 K7_NOP4 ASM_NOP1
39196 +#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
39197 +#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
39198 +#define K7_NOP8 K7_NOP7 ASM_NOP1
39201 +#define ASM_NOP1 K8_NOP1
39202 +#define ASM_NOP2 K8_NOP2
39203 +#define ASM_NOP3 K8_NOP3
39204 +#define ASM_NOP4 K8_NOP4
39205 +#define ASM_NOP5 K8_NOP5
39206 +#define ASM_NOP6 K8_NOP6
39207 +#define ASM_NOP7 K8_NOP7
39208 +#define ASM_NOP8 K8_NOP8
39209 +#elif defined(CONFIG_MK7)
39210 +#define ASM_NOP1 K7_NOP1
39211 +#define ASM_NOP2 K7_NOP2
39212 +#define ASM_NOP3 K7_NOP3
39213 +#define ASM_NOP4 K7_NOP4
39214 +#define ASM_NOP5 K7_NOP5
39215 +#define ASM_NOP6 K7_NOP6
39216 +#define ASM_NOP7 K7_NOP7
39217 +#define ASM_NOP8 K7_NOP8
39219 +#define ASM_NOP1 GENERIC_NOP1
39220 +#define ASM_NOP2 GENERIC_NOP2
39221 +#define ASM_NOP3 GENERIC_NOP3
39222 +#define ASM_NOP4 GENERIC_NOP4
39223 +#define ASM_NOP5 GENERIC_NOP5
39224 +#define ASM_NOP6 GENERIC_NOP6
39225 +#define ASM_NOP7 GENERIC_NOP7
39226 +#define ASM_NOP8 GENERIC_NOP8
39229 +#define ASM_NOP_MAX 8
39231 +/* Prefetch instructions for Pentium III and AMD Athlon */
39232 +/* It's not worth to care about 3dnow! prefetches for the K6
39233 + because they are microcoded there and very slow.
39234 + However we don't do prefetches for pre XP Athlons currently
39235 + That should be fixed. */
39236 +#define ARCH_HAS_PREFETCH
39237 +static inline void prefetch(const void *x)
39239 + alternative_input(ASM_NOP4,
39240 + "prefetchnta (%1)",
39245 +#define ARCH_HAS_PREFETCH
39246 +#define ARCH_HAS_PREFETCHW
39247 +#define ARCH_HAS_SPINLOCK_PREFETCH
39249 +/* 3dnow! prefetch to get an exclusive cache line. Useful for
39250 + spinlocks to avoid one state transition in the cache coherency protocol. */
39251 +static inline void prefetchw(const void *x)
39253 + alternative_input(ASM_NOP4,
39254 + "prefetchw (%1)",
39255 + X86_FEATURE_3DNOW,
39258 +#define spin_lock_prefetch(x) prefetchw(x)
39260 +extern void select_idle_routine(const struct cpuinfo_x86 *c);
39262 +#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
39264 +extern unsigned long boot_option_idle_override;
39265 +extern void enable_sep_cpu(void);
39266 +extern int sysenter_setup(void);
39268 +#endif /* __ASM_I386_PROCESSOR_H */
39269 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/segment_32.h
39270 ===================================================================
39271 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
39272 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/segment_32.h 2007-06-12 13:14:02.000000000 +0200
39274 +#ifndef _ASM_SEGMENT_H
39275 +#define _ASM_SEGMENT_H
39278 + * The layout of the per-CPU GDT under Linux:
39285 + * 4 - unused <==== new cacheline
39288 + * ------- start of TLS (Thread-Local Storage) segments:
39290 + * 6 - TLS segment #1 [ glibc's TLS segment ]
39291 + * 7 - TLS segment #2 [ Wine's %fs Win32 segment ]
39292 + * 8 - TLS segment #3
39297 + * ------- start of kernel segments:
39299 + * 12 - kernel code segment <==== new cacheline
39300 + * 13 - kernel data segment
39301 + * 14 - default user CS
39302 + * 15 - default user DS
39305 + * 18 - PNPBIOS support (16->32 gate)
39306 + * 19 - PNPBIOS support
39307 + * 20 - PNPBIOS support
39308 + * 21 - PNPBIOS support
39309 + * 22 - PNPBIOS support
39310 + * 23 - APM BIOS support
39311 + * 24 - APM BIOS support
39312 + * 25 - APM BIOS support
39314 + * 26 - ESPFIX small SS
39319 + * 31 - TSS for double fault handler
39321 +#define GDT_ENTRY_TLS_ENTRIES 3
39322 +#define GDT_ENTRY_TLS_MIN 6
39323 +#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
39325 +#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
39327 +#define GDT_ENTRY_DEFAULT_USER_CS 14
39328 +#define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS * 8 + 3)
39330 +#define GDT_ENTRY_DEFAULT_USER_DS 15
39331 +#define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS * 8 + 3)
39333 +#define GDT_ENTRY_KERNEL_BASE 12
39335 +#define GDT_ENTRY_KERNEL_CS (GDT_ENTRY_KERNEL_BASE + 0)
39336 +#define __KERNEL_CS (GDT_ENTRY_KERNEL_CS * 8)
39337 +#define GET_KERNEL_CS() (__KERNEL_CS | (xen_feature(XENFEAT_supervisor_mode_kernel)?0:1) )
39339 +#define GDT_ENTRY_KERNEL_DS (GDT_ENTRY_KERNEL_BASE + 1)
39340 +#define __KERNEL_DS (GDT_ENTRY_KERNEL_DS * 8)
39341 +#define GET_KERNEL_DS() (__KERNEL_DS | (xen_feature(XENFEAT_supervisor_mode_kernel)?0:1) )
39343 +#define GDT_ENTRY_TSS (GDT_ENTRY_KERNEL_BASE + 4)
39344 +#define GDT_ENTRY_LDT (GDT_ENTRY_KERNEL_BASE + 5)
39346 +#define GDT_ENTRY_PNPBIOS_BASE (GDT_ENTRY_KERNEL_BASE + 6)
39347 +#define GDT_ENTRY_APMBIOS_BASE (GDT_ENTRY_KERNEL_BASE + 11)
39349 +#define GDT_ENTRY_ESPFIX_SS (GDT_ENTRY_KERNEL_BASE + 14)
39350 +#define __ESPFIX_SS (GDT_ENTRY_ESPFIX_SS * 8)
39352 +#define GDT_ENTRY_DOUBLEFAULT_TSS 31
39355 + * The GDT has 32 entries
39357 +#define GDT_ENTRIES 32
39359 +#define GDT_SIZE (GDT_ENTRIES * 8)
39361 +/* Simple and small GDT entries for booting only */
39363 +#define GDT_ENTRY_BOOT_CS 2
39364 +#define __BOOT_CS (GDT_ENTRY_BOOT_CS * 8)
39366 +#define GDT_ENTRY_BOOT_DS (GDT_ENTRY_BOOT_CS + 1)
39367 +#define __BOOT_DS (GDT_ENTRY_BOOT_DS * 8)
39369 +/* The PnP BIOS entries in the GDT */
39370 +#define GDT_ENTRY_PNPBIOS_CS32 (GDT_ENTRY_PNPBIOS_BASE + 0)
39371 +#define GDT_ENTRY_PNPBIOS_CS16 (GDT_ENTRY_PNPBIOS_BASE + 1)
39372 +#define GDT_ENTRY_PNPBIOS_DS (GDT_ENTRY_PNPBIOS_BASE + 2)
39373 +#define GDT_ENTRY_PNPBIOS_TS1 (GDT_ENTRY_PNPBIOS_BASE + 3)
39374 +#define GDT_ENTRY_PNPBIOS_TS2 (GDT_ENTRY_PNPBIOS_BASE + 4)
39376 +/* The PnP BIOS selectors */
39377 +#define PNP_CS32 (GDT_ENTRY_PNPBIOS_CS32 * 8) /* segment for calling fn */
39378 +#define PNP_CS16 (GDT_ENTRY_PNPBIOS_CS16 * 8) /* code segment for BIOS */
39379 +#define PNP_DS (GDT_ENTRY_PNPBIOS_DS * 8) /* data segment for BIOS */
39380 +#define PNP_TS1 (GDT_ENTRY_PNPBIOS_TS1 * 8) /* transfer data segment */
39381 +#define PNP_TS2 (GDT_ENTRY_PNPBIOS_TS2 * 8) /* another data segment */
39384 + * The interrupt descriptor table has room for 256 idt's,
39385 + * the global descriptor table is dependent on the number
39386 + * of tasks we can have..
39388 +#define IDT_ENTRIES 256
39391 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/smp_32.h
39392 ===================================================================
39393 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
39394 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/smp_32.h 2007-06-12 13:14:02.000000000 +0200
39396 +#ifndef __ASM_SMP_H
39397 +#define __ASM_SMP_H
39400 + * We need the APIC definitions automatically as part of 'smp.h'
39402 +#ifndef __ASSEMBLY__
39403 +#include <linux/kernel.h>
39404 +#include <linux/threads.h>
39405 +#include <linux/cpumask.h>
39408 +#ifdef CONFIG_X86_LOCAL_APIC
39409 +#ifndef __ASSEMBLY__
39410 +#include <asm/fixmap.h>
39411 +#include <asm/bitops.h>
39412 +#include <asm/mpspec.h>
39413 +#ifdef CONFIG_X86_IO_APIC
39414 +#include <asm/io_apic.h>
39416 +#include <asm/apic.h>
39420 +#define BAD_APICID 0xFFu
39422 +#ifndef __ASSEMBLY__
39425 + * Private routines/data
39428 +extern void smp_alloc_memory(void);
39429 +extern int pic_mode;
39430 +extern int smp_num_siblings;
39431 +extern cpumask_t cpu_sibling_map[];
39432 +extern cpumask_t cpu_core_map[];
39434 +extern void (*mtrr_hook) (void);
39435 +extern void zap_low_mappings (void);
39436 +extern void lock_ipi_call_lock(void);
39437 +extern void unlock_ipi_call_lock(void);
39439 +#define MAX_APICID 256
39440 +extern u8 x86_cpu_to_apicid[];
39442 +#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu]
39444 +#ifdef CONFIG_HOTPLUG_CPU
39445 +extern void cpu_exit_clear(void);
39446 +extern void cpu_uninit(void);
39450 + * This function is needed by all SMP systems. It must _always_ be valid
39451 + * from the initial startup. We map APIC_BASE very early in page_setup(),
39452 + * so this is correct in the x86 case.
39454 +#define raw_smp_processor_id() (current_thread_info()->cpu)
39456 +extern cpumask_t cpu_possible_map;
39457 +#define cpu_callin_map cpu_possible_map
39459 +/* We don't mark CPUs online until __cpu_up(), so we need another measure */
39460 +static inline int num_booting_cpus(void)
39462 + return cpus_weight(cpu_possible_map);
39465 +#ifdef CONFIG_X86_LOCAL_APIC
39467 +#ifdef APIC_DEFINITION
39468 +extern int hard_smp_processor_id(void);
39470 +#include <mach_apicdef.h>
39471 +static inline int hard_smp_processor_id(void)
39473 + /* we don't want to mark this access volatile - bad code generation */
39474 + return GET_APIC_ID(*(unsigned long *)(APIC_BASE+APIC_ID));
39478 +static __inline int logical_smp_processor_id(void)
39480 + /* we don't want to mark this access volatile - bad code generation */
39481 + return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
39486 +extern int __cpu_disable(void);
39487 +extern void __cpu_die(unsigned int cpu);
39488 +extern void prefill_possible_map(void);
39489 +#endif /* !__ASSEMBLY__ */
39491 +#else /* CONFIG_SMP */
39493 +#define cpu_physical_id(cpu) boot_cpu_physical_apicid
39495 +#define NO_PROC_ID 0xFF /* No processor magic marker */
39499 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/swiotlb_32.h
39500 ===================================================================
39501 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
39502 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/swiotlb_32.h 2007-06-12 13:14:02.000000000 +0200
39504 +#ifndef _ASM_SWIOTLB_H
39505 +#define _ASM_SWIOTLB_H 1
39507 +/* SWIOTLB interface */
39509 +extern dma_addr_t swiotlb_map_single(struct device *hwdev, void *ptr, size_t size,
39511 +extern void swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr,
39512 + size_t size, int dir);
39513 +extern void swiotlb_sync_single_for_cpu(struct device *hwdev,
39514 + dma_addr_t dev_addr,
39515 + size_t size, int dir);
39516 +extern void swiotlb_sync_single_for_device(struct device *hwdev,
39517 + dma_addr_t dev_addr,
39518 + size_t size, int dir);
39519 +extern void swiotlb_sync_sg_for_cpu(struct device *hwdev,
39520 + struct scatterlist *sg, int nelems,
39522 +extern void swiotlb_sync_sg_for_device(struct device *hwdev,
39523 + struct scatterlist *sg, int nelems,
39525 +extern int swiotlb_map_sg(struct device *hwdev, struct scatterlist *sg,
39526 + int nents, int direction);
39527 +extern void swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg,
39528 + int nents, int direction);
39529 +extern int swiotlb_dma_mapping_error(dma_addr_t dma_addr);
39530 +#ifdef CONFIG_HIGHMEM
39531 +extern dma_addr_t swiotlb_map_page(struct device *hwdev, struct page *page,
39532 + unsigned long offset, size_t size,
39533 + enum dma_data_direction direction);
39534 +extern void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dma_address,
39535 + size_t size, enum dma_data_direction direction);
39537 +extern int swiotlb_dma_supported(struct device *hwdev, u64 mask);
39538 +extern void swiotlb_init(void);
39540 +#ifdef CONFIG_SWIOTLB
39541 +extern int swiotlb;
39547 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/synch_bitops.h
39548 ===================================================================
39549 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
39550 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/synch_bitops.h 2008-04-02 12:34:02.000000000 +0200
39552 +#ifndef __XEN_SYNCH_BITOPS_H__
39553 +#define __XEN_SYNCH_BITOPS_H__
39556 + * Copyright 1992, Linus Torvalds.
39557 + * Heavily modified to provide guaranteed strong synchronisation
39558 + * when communicating with Xen or other guest OSes running on other CPUs.
39561 +#ifdef HAVE_XEN_PLATFORM_COMPAT_H
39562 +#include <xen/platform-compat.h>
39565 +#define ADDR (*(volatile long *) addr)
39567 +static __inline__ void synch_set_bit(int nr, volatile void * addr)
39569 + __asm__ __volatile__ (
39570 + "lock btsl %1,%0"
39571 + : "+m" (ADDR) : "Ir" (nr) : "memory" );
39574 +static __inline__ void synch_clear_bit(int nr, volatile void * addr)
39576 + __asm__ __volatile__ (
39577 + "lock btrl %1,%0"
39578 + : "+m" (ADDR) : "Ir" (nr) : "memory" );
39581 +static __inline__ void synch_change_bit(int nr, volatile void * addr)
39583 + __asm__ __volatile__ (
39584 + "lock btcl %1,%0"
39585 + : "+m" (ADDR) : "Ir" (nr) : "memory" );
39588 +static __inline__ int synch_test_and_set_bit(int nr, volatile void * addr)
39591 + __asm__ __volatile__ (
39592 + "lock btsl %2,%1\n\tsbbl %0,%0"
39593 + : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory");
39597 +static __inline__ int synch_test_and_clear_bit(int nr, volatile void * addr)
39600 + __asm__ __volatile__ (
39601 + "lock btrl %2,%1\n\tsbbl %0,%0"
39602 + : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory");
39606 +static __inline__ int synch_test_and_change_bit(int nr, volatile void * addr)
39610 + __asm__ __volatile__ (
39611 + "lock btcl %2,%1\n\tsbbl %0,%0"
39612 + : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory");
39616 +struct __synch_xchg_dummy { unsigned long a[100]; };
39617 +#define __synch_xg(x) ((struct __synch_xchg_dummy *)(x))
39619 +#define synch_cmpxchg(ptr, old, new) \
39620 +((__typeof__(*(ptr)))__synch_cmpxchg((ptr),\
39621 + (unsigned long)(old), \
39622 + (unsigned long)(new), \
39625 +static inline unsigned long __synch_cmpxchg(volatile void *ptr,
39626 + unsigned long old,
39627 + unsigned long new, int size)
39629 + unsigned long prev;
39632 + __asm__ __volatile__("lock; cmpxchgb %b1,%2"
39634 + : "q"(new), "m"(*__synch_xg(ptr)),
39639 + __asm__ __volatile__("lock; cmpxchgw %w1,%2"
39641 + : "r"(new), "m"(*__synch_xg(ptr)),
39645 +#ifdef CONFIG_X86_64
39647 + __asm__ __volatile__("lock; cmpxchgl %k1,%2"
39649 + : "r"(new), "m"(*__synch_xg(ptr)),
39654 + __asm__ __volatile__("lock; cmpxchgq %1,%2"
39656 + : "r"(new), "m"(*__synch_xg(ptr)),
39662 + __asm__ __volatile__("lock; cmpxchgl %1,%2"
39664 + : "r"(new), "m"(*__synch_xg(ptr)),
39673 +#define synch_test_bit test_bit
39675 +#define synch_cmpxchg_subword synch_cmpxchg
39677 +#endif /* __XEN_SYNCH_BITOPS_H__ */
39678 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/system_32.h
39679 ===================================================================
39680 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
39681 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/system_32.h 2007-06-12 13:14:02.000000000 +0200
39683 +#ifndef __ASM_SYSTEM_H
39684 +#define __ASM_SYSTEM_H
39686 +#include <linux/kernel.h>
39687 +#include <asm/segment.h>
39688 +#include <asm/cpufeature.h>
39689 +#include <linux/bitops.h> /* for LOCK_PREFIX */
39690 +#include <asm/synch_bitops.h>
39691 +#include <asm/hypervisor.h>
39695 +struct task_struct; /* one of the stranger aspects of C forward declarations.. */
39696 +extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
39699 + * Saving eflags is important. It switches not only IOPL between tasks,
39700 + * it also protects other tasks from NT leaking through sysenter etc.
39702 +#define switch_to(prev,next,last) do { \
39703 + unsigned long esi,edi; \
39704 + asm volatile("pushfl\n\t" /* Save flags */ \
39705 + "pushl %%ebp\n\t" \
39706 + "movl %%esp,%0\n\t" /* save ESP */ \
39707 + "movl %5,%%esp\n\t" /* restore ESP */ \
39708 + "movl $1f,%1\n\t" /* save EIP */ \
39709 + "pushl %6\n\t" /* restore EIP */ \
39710 + "jmp __switch_to\n" \
39712 + "popl %%ebp\n\t" \
39714 + :"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
39715 + "=a" (last),"=S" (esi),"=D" (edi) \
39716 + :"m" (next->thread.esp),"m" (next->thread.eip), \
39717 + "2" (prev), "d" (next)); \
39720 +#define _set_base(addr,base) do { unsigned long __pr; \
39721 +__asm__ __volatile__ ("movw %%dx,%1\n\t" \
39722 + "rorl $16,%%edx\n\t" \
39723 + "movb %%dl,%2\n\t" \
39726 + :"m" (*((addr)+2)), \
39727 + "m" (*((addr)+4)), \
39728 + "m" (*((addr)+7)), \
39732 +#define _set_limit(addr,limit) do { unsigned long __lr; \
39733 +__asm__ __volatile__ ("movw %%dx,%1\n\t" \
39734 + "rorl $16,%%edx\n\t" \
39735 + "movb %2,%%dh\n\t" \
39736 + "andb $0xf0,%%dh\n\t" \
39737 + "orb %%dh,%%dl\n\t" \
39740 + :"m" (*(addr)), \
39741 + "m" (*((addr)+6)), \
39745 +#define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
39746 +#define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
39749 + * Load a segment. Fall back on loading the zero
39750 + * segment if something goes wrong..
39752 +#define loadsegment(seg,value) \
39753 + asm volatile("\n" \
39755 + "mov %0,%%" #seg "\n" \
39757 + ".section .fixup,\"ax\"\n" \
39760 + "popl %%" #seg "\n\t" \
39763 + ".section __ex_table,\"a\"\n\t" \
39765 + ".long 1b,3b\n" \
39770 + * Save a segment register away
39772 +#define savesegment(seg, value) \
39773 + asm volatile("mov %%" #seg ",%0":"=rm" (value))
39775 +#define read_cr0() ({ \
39776 + unsigned int __dummy; \
39777 + __asm__ __volatile__( \
39778 + "movl %%cr0,%0\n\t" \
39779 + :"=r" (__dummy)); \
39782 +#define write_cr0(x) \
39783 + __asm__ __volatile__("movl %0,%%cr0": :"r" (x))
39785 +#define read_cr2() (current_vcpu_info()->arch.cr2)
39786 +#define write_cr2(x) \
39787 + __asm__ __volatile__("movl %0,%%cr2": :"r" (x))
39789 +#define read_cr3() ({ \
39790 + unsigned int __dummy; \
39792 + "movl %%cr3,%0\n\t" \
39793 + :"=r" (__dummy)); \
39794 + __dummy = xen_cr3_to_pfn(__dummy); \
39795 + mfn_to_pfn(__dummy) << PAGE_SHIFT; \
39797 +#define write_cr3(x) ({ \
39798 + unsigned int __dummy = pfn_to_mfn((x) >> PAGE_SHIFT); \
39799 + __dummy = xen_pfn_to_cr3(__dummy); \
39800 + __asm__ __volatile__("movl %0,%%cr3": :"r" (__dummy)); \
39802 +#define read_cr4() ({ \
39803 + unsigned int __dummy; \
39805 + "movl %%cr4,%0\n\t" \
39806 + :"=r" (__dummy)); \
39809 +#define read_cr4_safe() ({ \
39810 + unsigned int __dummy; \
39811 + /* This could fault if %cr4 does not exist */ \
39812 + __asm__("1: movl %%cr4, %0 \n" \
39814 + ".section __ex_table,\"a\" \n" \
39815 + ".long 1b,2b \n" \
39817 + : "=r" (__dummy): "0" (0)); \
39821 +#define write_cr4(x) \
39822 + __asm__ __volatile__("movl %0,%%cr4": :"r" (x))
39825 + * Clear and set 'TS' bit respectively
39827 +#define clts() (HYPERVISOR_fpu_taskswitch(0))
39828 +#define stts() (HYPERVISOR_fpu_taskswitch(1))
39830 +#endif /* __KERNEL__ */
39832 +#define wbinvd() \
39833 + __asm__ __volatile__ ("wbinvd": : :"memory")
39835 +static inline unsigned long get_limit(unsigned long segment)
39837 + unsigned long __limit;
39838 + __asm__("lsll %1,%0"
39839 + :"=r" (__limit):"r" (segment));
39840 + return __limit+1;
39843 +#define nop() __asm__ __volatile__ ("nop")
39845 +#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
39847 +#define tas(ptr) (xchg((ptr),1))
39849 +struct __xchg_dummy { unsigned long a[100]; };
39850 +#define __xg(x) ((struct __xchg_dummy *)(x))
39853 +#ifdef CONFIG_X86_CMPXCHG64
39856 + * The semantics of XCHGCMP8B are a bit strange, this is why
39857 + * there is a loop and the loading of %%eax and %%edx has to
39858 + * be inside. This inlines well in most cases, the cached
39859 + * cost is around ~38 cycles. (in the future we might want
39860 + * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
39861 + * might have an implicit FPU-save as a cost, so it's not
39862 + * clear which path to go.)
39864 + * cmpxchg8b must be used with the lock prefix here to allow
39865 + * the instruction to be executed atomically, see page 3-102
39866 + * of the instruction set reference 24319102.pdf. We need
39867 + * the reader side to see the coherent 64bit value.
39869 +static inline void __set_64bit (unsigned long long * ptr,
39870 + unsigned int low, unsigned int high)
39872 + __asm__ __volatile__ (
39874 + "movl (%0), %%eax\n\t"
39875 + "movl 4(%0), %%edx\n\t"
39876 + "lock cmpxchg8b (%0)\n\t"
39878 + : /* no outputs */
39882 + : "ax","dx","memory");
39885 +static inline void __set_64bit_constant (unsigned long long *ptr,
39886 + unsigned long long value)
39888 + __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
39890 +#define ll_low(x) *(((unsigned int*)&(x))+0)
39891 +#define ll_high(x) *(((unsigned int*)&(x))+1)
39893 +static inline void __set_64bit_var (unsigned long long *ptr,
39894 + unsigned long long value)
39896 + __set_64bit(ptr,ll_low(value), ll_high(value));
39899 +#define set_64bit(ptr,value) \
39900 +(__builtin_constant_p(value) ? \
39901 + __set_64bit_constant(ptr, value) : \
39902 + __set_64bit_var(ptr, value) )
39904 +#define _set_64bit(ptr,value) \
39905 +(__builtin_constant_p(value) ? \
39906 + __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
39907 + __set_64bit(ptr, ll_low(value), ll_high(value)) )
39912 + * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
39913 + * Note 2: xchg has side effect, so that attribute volatile is necessary,
39914 + * but generally the primitive is invalid, *ptr is output argument. --ANK
39916 +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
39920 + __asm__ __volatile__("xchgb %b0,%1"
39922 + :"m" (*__xg(ptr)), "0" (x)
39926 + __asm__ __volatile__("xchgw %w0,%1"
39928 + :"m" (*__xg(ptr)), "0" (x)
39932 + __asm__ __volatile__("xchgl %0,%1"
39934 + :"m" (*__xg(ptr)), "0" (x)
39942 + * Atomic compare and exchange. Compare OLD with MEM, if identical,
39943 + * store NEW in MEM. Return the initial value in MEM. Success is
39944 + * indicated by comparing RETURN with OLD.
39947 +#ifdef CONFIG_X86_CMPXCHG
39948 +#define __HAVE_ARCH_CMPXCHG 1
39949 +#define cmpxchg(ptr,o,n)\
39950 + ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
39951 + (unsigned long)(n),sizeof(*(ptr))))
39954 +static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
39955 + unsigned long new, int size)
39957 + unsigned long prev;
39960 + __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
39962 + : "q"(new), "m"(*__xg(ptr)), "0"(old)
39966 + __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
39968 + : "r"(new), "m"(*__xg(ptr)), "0"(old)
39972 + __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
39974 + : "r"(new), "m"(*__xg(ptr)), "0"(old)
39981 +#ifndef CONFIG_X86_CMPXCHG
39983 + * Building a kernel capable running on 80386. It may be necessary to
39984 + * simulate the cmpxchg on the 80386 CPU. For that purpose we define
39985 + * a function for each of the sizes we support.
39988 +extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
39989 +extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
39990 +extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
39992 +static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
39993 + unsigned long new, int size)
39997 + return cmpxchg_386_u8(ptr, old, new);
39999 + return cmpxchg_386_u16(ptr, old, new);
40001 + return cmpxchg_386_u32(ptr, old, new);
40006 +#define cmpxchg(ptr,o,n) \
40008 + __typeof__(*(ptr)) __ret; \
40009 + if (likely(boot_cpu_data.x86 > 3)) \
40010 + __ret = __cmpxchg((ptr), (unsigned long)(o), \
40011 + (unsigned long)(n), sizeof(*(ptr))); \
40013 + __ret = cmpxchg_386((ptr), (unsigned long)(o), \
40014 + (unsigned long)(n), sizeof(*(ptr))); \
40019 +#ifdef CONFIG_X86_CMPXCHG64
40021 +static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
40022 + unsigned long long new)
40024 + unsigned long long prev;
40025 + __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
40027 + : "b"((unsigned long)new),
40028 + "c"((unsigned long)(new >> 32)),
40035 +#define cmpxchg64(ptr,o,n)\
40036 + ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
40037 + (unsigned long long)(n)))
40042 + * Force strict CPU ordering.
40043 + * And yes, this is required on UP too when we're talking
40046 + * For now, "wmb()" doesn't actually do anything, as all
40047 + * Intel CPU's follow what Intel calls a *Processor Order*,
40048 + * in which all writes are seen in the program order even
40049 + * outside the CPU.
40051 + * I expect future Intel CPU's to have a weaker ordering,
40052 + * but I'd also expect them to finally get their act together
40053 + * and add some real memory barriers if so.
40055 + * Some non intel clones support out of order store. wmb() ceases to be a
40061 + * Actually only lfence would be needed for mb() because all stores done
40062 + * by the kernel should be already ordered. But keep a full barrier for now.
40065 +#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
40066 +#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
40069 + * read_barrier_depends - Flush all pending reads that subsequents reads
40072 + * No data-dependent reads from memory-like regions are ever reordered
40073 + * over this barrier. All reads preceding this primitive are guaranteed
40074 + * to access memory (but not necessarily other CPUs' caches) before any
40075 + * reads following this primitive that depend on the data return by
40076 + * any of the preceding reads. This primitive is much lighter weight than
40077 + * rmb() on most CPUs, and is never heavier weight than is
40080 + * These ordering constraints are respected by both the local CPU
40081 + * and the compiler.
40083 + * Ordering is not guaranteed by anything other than these primitives,
40084 + * not even by data dependencies. See the documentation for
40085 + * memory_barrier() for examples and URLs to more information.
40087 + * For example, the following code would force ordering (the initial
40088 + * value of "a" is zero, "b" is one, and "p" is "&a"):
40090 + * <programlisting>
40094 + * memory_barrier();
40096 + * read_barrier_depends();
40098 + * </programlisting>
40100 + * because the read of "*q" depends on the read of "p" and these
40101 + * two reads are separated by a read_barrier_depends(). However,
40102 + * the following code, with the same initial values for "a" and "b":
40104 + * <programlisting>
40108 + * memory_barrier();
40110 + * read_barrier_depends();
40112 + * </programlisting>
40114 + * does not enforce ordering, since there is no data dependency between
40115 + * the read of "a" and the read of "b". Therefore, on some CPUs, such
40116 + * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
40117 + * in cases like this where there are no data dependencies.
40120 +#define read_barrier_depends() do { } while(0)
40122 +#ifdef CONFIG_X86_OOSTORE
40123 +/* Actually there are no OOO store capable CPUs for now that do SSE,
40124 + but make it already an possibility. */
40125 +#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
40127 +#define wmb() __asm__ __volatile__ ("": : :"memory")
40131 +#define smp_mb() mb()
40132 +#define smp_rmb() rmb()
40133 +#define smp_wmb() wmb()
40134 +#define smp_read_barrier_depends() read_barrier_depends()
40135 +#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
40137 +#define smp_mb() barrier()
40138 +#define smp_rmb() barrier()
40139 +#define smp_wmb() barrier()
40140 +#define smp_read_barrier_depends() do { } while(0)
40141 +#define set_mb(var, value) do { var = value; barrier(); } while (0)
40144 +#include <linux/irqflags.h>
40147 + * disable hlt during certain critical i/o operations
40149 +#define HAVE_DISABLE_HLT
40150 +void disable_hlt(void);
40151 +void enable_hlt(void);
40153 +extern int es7000_plat;
40154 +void cpu_idle_wait(void);
40157 + * On SMP systems, when the scheduler does migration-cost autodetection,
40158 + * it needs a way to flush as much of the CPU's caches as possible:
40160 +static inline void sched_cacheflush(void)
40165 +extern unsigned long arch_align_stack(unsigned long sp);
40166 +extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
40168 +void default_idle(void);
40171 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/tlbflush_32.h
40172 ===================================================================
40173 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
40174 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/tlbflush_32.h 2007-11-26 16:59:25.000000000 +0100
40176 +#ifndef _I386_TLBFLUSH_H
40177 +#define _I386_TLBFLUSH_H
40179 +#include <linux/mm.h>
40180 +#include <asm/processor.h>
40182 +#define __flush_tlb() xen_tlb_flush()
40183 +#define __flush_tlb_global() xen_tlb_flush()
40184 +#define __flush_tlb_all() xen_tlb_flush()
40186 +extern unsigned long pgkern_mask;
40188 +#define cpu_has_invlpg (boot_cpu_data.x86 > 3)
40190 +#define __flush_tlb_single(addr) xen_invlpg(addr)
40192 +#define __flush_tlb_one(addr) __flush_tlb_single(addr)
40197 + * - flush_tlb() flushes the current mm struct TLBs
40198 + * - flush_tlb_all() flushes all processes TLBs
40199 + * - flush_tlb_mm(mm) flushes the specified mm context TLB's
40200 + * - flush_tlb_page(vma, vmaddr) flushes one page
40201 + * - flush_tlb_range(vma, start, end) flushes a range of pages
40202 + * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
40203 + * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
40205 + * ..but the i386 has somewhat limited tlb flushing capabilities,
40206 + * and page-granular flushes are available only on i486 and up.
40209 +#ifndef CONFIG_SMP
40211 +#define flush_tlb() __flush_tlb()
40212 +#define flush_tlb_all() __flush_tlb_all()
40213 +#define local_flush_tlb() __flush_tlb()
40215 +static inline void flush_tlb_mm(struct mm_struct *mm)
40217 + if (mm == current->active_mm)
40221 +static inline void flush_tlb_page(struct vm_area_struct *vma,
40222 + unsigned long addr)
40224 + if (vma->vm_mm == current->active_mm)
40225 + __flush_tlb_one(addr);
40228 +static inline void flush_tlb_range(struct vm_area_struct *vma,
40229 + unsigned long start, unsigned long end)
40231 + if (vma->vm_mm == current->active_mm)
40237 +#include <asm/smp.h>
40239 +#define local_flush_tlb() \
40242 +#define flush_tlb_all xen_tlb_flush_all
40243 +#define flush_tlb_current_task() xen_tlb_flush_mask(¤t->mm->cpu_vm_mask)
40244 +#define flush_tlb_mm(mm) xen_tlb_flush_mask(&(mm)->cpu_vm_mask)
40245 +#define flush_tlb_page(vma, va) xen_invlpg_mask(&(vma)->vm_mm->cpu_vm_mask, va)
40247 +#define flush_tlb() flush_tlb_current_task()
40249 +static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
40251 + flush_tlb_mm(vma->vm_mm);
40254 +#define TLBSTATE_OK 1
40255 +#define TLBSTATE_LAZY 2
40259 + struct mm_struct *active_mm;
40261 + char __cacheline_padding[L1_CACHE_BYTES-8];
40263 +DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate);
40268 +#define flush_tlb_kernel_range(start, end) flush_tlb_all()
40270 +static inline void flush_tlb_pgtables(struct mm_struct *mm,
40271 + unsigned long start, unsigned long end)
40273 + /* i386 does not keep any page table caches in TLB */
40276 +#endif /* _I386_TLBFLUSH_H */
40277 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/vga.h
40278 ===================================================================
40279 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
40280 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/vga.h 2007-06-12 13:14:02.000000000 +0200
40283 + * Access to VGA videoram
40285 + * (c) 1998 Martin Mares <mj@ucw.cz>
40288 +#ifndef _LINUX_ASM_VGA_H_
40289 +#define _LINUX_ASM_VGA_H_
40292 + * On the PC, we can just recalculate addresses and then
40293 + * access the videoram directly without any black magic.
40296 +#define VGA_MAP_MEM(x,s) (unsigned long)isa_bus_to_virt(x)
40298 +#define vga_readb(x) (*(x))
40299 +#define vga_writeb(x,y) (*(y) = (x))
40302 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/xenoprof.h
40303 ===================================================================
40304 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
40305 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/xenoprof.h 2007-06-12 13:14:02.000000000 +0200
40307 +/******************************************************************************
40308 + * asm-i386/mach-xen/asm/xenoprof.h
40310 + * Copyright (c) 2006 Isaku Yamahata <yamahata at valinux co jp>
40311 + * VA Linux Systems Japan K.K.
40313 + * This program is free software; you can redistribute it and/or modify
40314 + * it under the terms of the GNU General Public License as published by
40315 + * the Free Software Foundation; either version 2 of the License, or
40316 + * (at your option) any later version.
40318 + * This program is distributed in the hope that it will be useful,
40319 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
40320 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40321 + * GNU General Public License for more details.
40323 + * You should have received a copy of the GNU General Public License
40324 + * along with this program; if not, write to the Free Software
40325 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
40328 +#ifndef __ASM_XENOPROF_H__
40329 +#define __ASM_XENOPROF_H__
40332 +struct super_block;
40334 +int xenoprof_create_files(struct super_block * sb, struct dentry * root);
40335 +#define HAVE_XENOPROF_CREATE_FILES
40337 +struct xenoprof_init;
40338 +void xenoprof_arch_init_counter(struct xenoprof_init *init);
40339 +void xenoprof_arch_counter(void);
40340 +void xenoprof_arch_start(void);
40341 +void xenoprof_arch_stop(void);
40343 +struct xenoprof_arch_shared_buffer {
40346 +struct xenoprof_shared_buffer;
40347 +void xenoprof_arch_unmap_shared_buffer(struct xenoprof_shared_buffer* sbuf);
40348 +struct xenoprof_get_buffer;
40349 +int xenoprof_arch_map_shared_buffer(struct xenoprof_get_buffer* get_buffer, struct xenoprof_shared_buffer* sbuf);
40350 +struct xenoprof_passive;
40351 +int xenoprof_arch_set_passive(struct xenoprof_passive* pdomain, struct xenoprof_shared_buffer* sbuf);
40353 +#endif /* CONFIG_XEN */
40354 +#endif /* __ASM_XENOPROF_H__ */
40355 Index: head-2008-11-25/include/asm-x86/mach-xen/irq_vectors.h
40356 ===================================================================
40357 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
40358 +++ head-2008-11-25/include/asm-x86/mach-xen/irq_vectors.h 2008-09-25 13:55:32.000000000 +0200
40361 + * This file should contain #defines for all of the interrupt vector
40362 + * numbers used by this architecture.
40364 + * In addition, there are some standard defines:
40366 + * FIRST_EXTERNAL_VECTOR:
40367 + * The first free place for external interrupts
40369 + * SYSCALL_VECTOR:
40370 + * The IRQ vector a syscall makes the user to kernel transition
40374 + * The IRQ number the timer interrupt comes in at.
40377 + * The total number of interrupt vectors (including all the
40378 + * architecture specific interrupts) needed.
40381 +#ifndef _ASM_IRQ_VECTORS_H
40382 +#define _ASM_IRQ_VECTORS_H
40385 + * IDT vectors usable for external interrupt sources start
40388 +#define FIRST_EXTERNAL_VECTOR 0x20
40390 +#define SYSCALL_VECTOR 0x80
40393 + * Vectors 0x20-0x2f are used for ISA interrupts.
40398 + * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
40400 + * some of the following vectors are 'rare', they are merged
40401 + * into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
40402 + * TLB, reschedule and local APIC vectors are performance-critical.
40404 + * Vectors 0xf0-0xfa are free (reserved for future Linux use).
40406 +#define SPURIOUS_APIC_VECTOR 0xff
40407 +#define ERROR_APIC_VECTOR 0xfe
40408 +#define INVALIDATE_TLB_VECTOR 0xfd
40409 +#define RESCHEDULE_VECTOR 0xfc
40410 +#define CALL_FUNCTION_VECTOR 0xfb
40412 +#define THERMAL_APIC_VECTOR 0xf0
40414 + * Local APIC timer IRQ vector is on a different priority level,
40415 + * to work around the 'lost local interrupt if more than 2 IRQ
40416 + * sources per level' errata.
40418 +#define LOCAL_TIMER_VECTOR 0xef
40421 +#define SPURIOUS_APIC_VECTOR 0xff
40422 +#define ERROR_APIC_VECTOR 0xfe
40425 + * First APIC vector available to drivers: (vectors 0x30-0xee)
40426 + * we start at 0x31 to spread out vectors evenly between priority
40427 + * levels. (0x80 is the syscall vector)
40429 +#define FIRST_DEVICE_VECTOR 0x31
40430 +#define FIRST_SYSTEM_VECTOR 0xef
40433 + * 16 8259A IRQ's, 208 potential APIC interrupt sources.
40434 + * Right now the APIC is mostly only used for SMP.
40435 + * 256 vectors is an architectural limit. (we can have
40436 + * more than 256 devices theoretically, but they will
40437 + * have to use shared interrupts)
40438 + * Since vectors 0x00-0x1f are used/reserved for the CPU,
40439 + * the usable vector space is 0x20-0xff (224 vectors)
40442 +#define RESCHEDULE_VECTOR 0
40443 +#define CALL_FUNCTION_VECTOR 1
40447 + * The maximum number of vectors supported by i386 processors
40448 + * is limited to 256. For processors other than i386, NR_VECTORS
40449 + * should be changed accordingly.
40451 +#define NR_VECTORS 256
40453 +#define FPU_IRQ 13
40455 +#define FIRST_VM86_IRQ 3
40456 +#define LAST_VM86_IRQ 15
40457 +#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15)
40460 + * The flat IRQ space is divided into two regions:
40461 + * 1. A one-to-one mapping of real physical IRQs. This space is only used
40462 + * if we have physical device-access privilege. This region is at the
40463 + * start of the IRQ space so that existing device drivers do not need
40464 + * to be modified to translate physical IRQ numbers into our IRQ space.
40465 + * 3. A dynamic mapping of inter-domain and Xen-sourced virtual IRQs. These
40466 + * are bound using the provided bind/unbind functions.
40469 +#define PIRQ_BASE 0
40470 +#if !defined(MAX_IO_APICS)
40471 +# define NR_PIRQS (NR_VECTORS + 32 * NR_CPUS)
40472 +#elif NR_CPUS < MAX_IO_APICS
40473 +# define NR_PIRQS (NR_VECTORS + 32 * NR_CPUS)
40475 +# define NR_PIRQS (NR_VECTORS + 32 * MAX_IO_APICS)
40478 +#define DYNIRQ_BASE (PIRQ_BASE + NR_PIRQS)
40479 +#define NR_DYNIRQS 256
40481 +#define NR_IRQS (NR_PIRQS + NR_DYNIRQS)
40482 +#define NR_IRQ_VECTORS NR_IRQS
40484 +#endif /* _ASM_IRQ_VECTORS_H */
40485 Index: head-2008-11-25/include/asm-x86/mach-xen/mach_traps.h
40486 ===================================================================
40487 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
40488 +++ head-2008-11-25/include/asm-x86/mach-xen/mach_traps.h 2007-06-12 13:14:02.000000000 +0200
40491 + * include/asm-xen/asm-i386/mach-xen/mach_traps.h
40493 + * Machine specific NMI handling for Xen
40495 +#ifndef _MACH_TRAPS_H
40496 +#define _MACH_TRAPS_H
40498 +#include <linux/bitops.h>
40499 +#include <xen/interface/nmi.h>
40501 +static inline void clear_mem_error(unsigned char reason) {}
40502 +static inline void clear_io_check_error(unsigned char reason) {}
40504 +static inline unsigned char get_nmi_reason(void)
40506 + shared_info_t *s = HYPERVISOR_shared_info;
40507 + unsigned char reason = 0;
40509 + /* construct a value which looks like it came from
40512 + if (test_bit(_XEN_NMIREASON_io_error, &s->arch.nmi_reason))
40514 + if (test_bit(_XEN_NMIREASON_parity_error, &s->arch.nmi_reason))
40520 +static inline void reassert_nmi(void) {}
40522 +#endif /* !_MACH_TRAPS_H */
40523 Index: head-2008-11-25/include/asm-x86/mach-xen/setup_arch.h
40524 ===================================================================
40525 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
40526 +++ head-2008-11-25/include/asm-x86/mach-xen/setup_arch.h 2007-06-12 13:14:02.000000000 +0200
40528 +/* Hook to call BIOS initialisation function */
40530 +#define ARCH_SETUP machine_specific_arch_setup();
40532 +void __init machine_specific_arch_setup(void);
40533 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/desc_64.h
40534 ===================================================================
40535 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
40536 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/desc_64.h 2008-01-28 12:24:19.000000000 +0100
40538 +/* Written 2000 by Andi Kleen */
40539 +#ifndef __ARCH_DESC_H
40540 +#define __ARCH_DESC_H
40542 +#include <linux/threads.h>
40543 +#include <asm/ldt.h>
40545 +#ifndef __ASSEMBLY__
40547 +#include <linux/string.h>
40548 +#include <linux/smp.h>
40550 +#include <asm/segment.h>
40551 +#include <asm/mmu.h>
40553 +// 8 byte segment descriptor
40554 +struct desc_struct {
40557 + unsigned base1 : 8, type : 4, s : 1, dpl : 2, p : 1;
40558 + unsigned limit : 4, avl : 1, l : 1, d : 1, g : 1, base2 : 8;
40559 +} __attribute__((packed));
40561 +struct n_desc_struct {
40562 + unsigned int a,b;
40566 + GATE_INTERRUPT = 0xE,
40572 +struct gate_struct {
40575 + unsigned ist : 3, zero0 : 5, type : 5, dpl : 2, p : 1;
40576 + u16 offset_middle;
40579 +} __attribute__((packed));
40581 +#define PTR_LOW(x) ((unsigned long)(x) & 0xFFFF)
40582 +#define PTR_MIDDLE(x) (((unsigned long)(x) >> 16) & 0xFFFF)
40583 +#define PTR_HIGH(x) ((unsigned long)(x) >> 32)
40590 +// LDT or TSS descriptor in the GDT. 16 bytes.
40591 +struct ldttss_desc {
40594 + unsigned base1 : 8, type : 5, dpl : 2, p : 1;
40595 + unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
40598 +} __attribute__((packed));
40601 + unsigned short size;
40602 + unsigned long address;
40603 +} __attribute__((packed)) ;
40605 +extern struct desc_ptr idt_descr, cpu_gdt_descr[NR_CPUS];
40607 +extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
40609 +#define load_TR_desc() asm volatile("ltr %w0"::"r" (GDT_ENTRY_TSS*8))
40610 +#define load_LDT_desc() asm volatile("lldt %w0"::"r" (GDT_ENTRY_LDT*8))
40612 +static inline void clear_LDT(void)
40614 + int cpu = get_cpu();
40617 + * NB. We load the default_ldt for lcall7/27 handling on demand, as
40618 + * it slows down context switching. Noone uses it anyway.
40620 + cpu = cpu; /* XXX avoid compiler warning */
40621 + xen_set_ldt(NULL, 0);
40626 + * This is the ldt that every process will get unless we need
40627 + * something other than this.
40629 +extern struct desc_struct default_ldt[];
40630 +#ifndef CONFIG_X86_NO_IDT
40631 +extern struct gate_struct idt_table[];
40633 +extern struct desc_ptr cpu_gdt_descr[];
40635 +/* the cpu gdt accessor */
40636 +#define cpu_gdt(_cpu) ((struct desc_struct *)cpu_gdt_descr[_cpu].address)
40638 +static inline void _set_gate(void *adr, unsigned type, unsigned long func, unsigned dpl, unsigned ist)
40640 + struct gate_struct s;
40641 + s.offset_low = PTR_LOW(func);
40642 + s.segment = __KERNEL_CS;
40649 + s.offset_middle = PTR_MIDDLE(func);
40650 + s.offset_high = PTR_HIGH(func);
40651 + /* does not need to be atomic because it is only done once at setup time */
40652 + memcpy(adr, &s, 16);
40655 +#ifndef CONFIG_X86_NO_IDT
40656 +static inline void set_intr_gate(int nr, void *func)
40658 + BUG_ON((unsigned)nr > 0xFF);
40659 + _set_gate(&idt_table[nr], GATE_INTERRUPT, (unsigned long) func, 0, 0);
40662 +static inline void set_intr_gate_ist(int nr, void *func, unsigned ist)
40664 + BUG_ON((unsigned)nr > 0xFF);
40665 + _set_gate(&idt_table[nr], GATE_INTERRUPT, (unsigned long) func, 0, ist);
40668 +static inline void set_system_gate(int nr, void *func)
40670 + BUG_ON((unsigned)nr > 0xFF);
40671 + _set_gate(&idt_table[nr], GATE_INTERRUPT, (unsigned long) func, 3, 0);
40674 +static inline void set_system_gate_ist(int nr, void *func, unsigned ist)
40676 + _set_gate(&idt_table[nr], GATE_INTERRUPT, (unsigned long) func, 3, ist);
40680 +static inline void set_tssldt_descriptor(void *ptr, unsigned long tss, unsigned type,
40683 + struct ldttss_desc d;
40684 + memset(&d,0,sizeof(d));
40685 + d.limit0 = size & 0xFFFF;
40686 + d.base0 = PTR_LOW(tss);
40687 + d.base1 = PTR_MIDDLE(tss) & 0xFF;
40690 + d.limit1 = (size >> 16) & 0xF;
40691 + d.base2 = (PTR_MIDDLE(tss) >> 8) & 0xFF;
40692 + d.base3 = PTR_HIGH(tss);
40693 + memcpy(ptr, &d, 16);
40696 +#ifndef CONFIG_X86_NO_TSS
40697 +static inline void set_tss_desc(unsigned cpu, void *addr)
40700 + * sizeof(unsigned long) coming from an extra "long" at the end
40701 + * of the iobitmap. See tss_struct definition in processor.h
40703 + * -1? seg base+limit should be pointing to the address of the
40704 + * last valid byte
40706 + set_tssldt_descriptor(&cpu_gdt(cpu)[GDT_ENTRY_TSS],
40707 + (unsigned long)addr, DESC_TSS,
40708 + IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1);
40712 +static inline void set_ldt_desc(unsigned cpu, void *addr, int size)
40714 + set_tssldt_descriptor(&cpu_gdt(cpu)[GDT_ENTRY_LDT], (unsigned long)addr,
40715 + DESC_LDT, size * 8 - 1);
40718 +static inline void set_seg_base(unsigned cpu, int entry, void *base)
40720 + struct desc_struct *d = &cpu_gdt(cpu)[entry];
40721 + u32 addr = (u32)(u64)base;
40722 + BUG_ON((u64)base >> 32);
40723 + d->base0 = addr & 0xffff;
40724 + d->base1 = (addr >> 16) & 0xff;
40725 + d->base2 = (addr >> 24) & 0xff;
40728 +#define LDT_entry_a(info) \
40729 + ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
40730 +/* Don't allow setting of the lm bit. It is useless anyways because
40731 + 64bit system calls require __USER_CS. */
40732 +#define LDT_entry_b(info) \
40733 + (((info)->base_addr & 0xff000000) | \
40734 + (((info)->base_addr & 0x00ff0000) >> 16) | \
40735 + ((info)->limit & 0xf0000) | \
40736 + (((info)->read_exec_only ^ 1) << 9) | \
40737 + ((info)->contents << 10) | \
40738 + (((info)->seg_not_present ^ 1) << 15) | \
40739 + ((info)->seg_32bit << 22) | \
40740 + ((info)->limit_in_pages << 23) | \
40741 + ((info)->useable << 20) | \
40742 + /* ((info)->lm << 21) | */ \
40745 +#define LDT_empty(info) (\
40746 + (info)->base_addr == 0 && \
40747 + (info)->limit == 0 && \
40748 + (info)->contents == 0 && \
40749 + (info)->read_exec_only == 1 && \
40750 + (info)->seg_32bit == 0 && \
40751 + (info)->limit_in_pages == 0 && \
40752 + (info)->seg_not_present == 1 && \
40753 + (info)->useable == 0 && \
40756 +#if TLS_SIZE != 24
40757 +# error update this code.
40760 +static inline void load_TLS(struct thread_struct *t, unsigned int cpu)
40763 + u64 *gdt = (u64 *)(cpu_gdt(cpu) + GDT_ENTRY_TLS_MIN);
40764 + gdt[0] = t->tls_array[0];
40765 + gdt[1] = t->tls_array[1];
40766 + gdt[2] = t->tls_array[2];
40769 + if (HYPERVISOR_update_descriptor(virt_to_machine(&cpu_gdt(cpu)[GDT_ENTRY_TLS_MIN + i]), \
40770 + t->tls_array[i])) \
40773 + C(0); C(1); C(2);
40778 + * load one particular LDT into the current CPU
40780 +static inline void load_LDT_nolock (mm_context_t *pc, int cpu)
40782 + void *segments = pc->ldt;
40783 + int count = pc->size;
40785 + if (likely(!count))
40788 + xen_set_ldt(segments, count);
40791 +static inline void load_LDT(mm_context_t *pc)
40793 + int cpu = get_cpu();
40794 + load_LDT_nolock(pc, cpu);
40798 +extern struct desc_ptr idt_descr;
40800 +#endif /* !__ASSEMBLY__ */
40803 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/dma-mapping_64.h
40804 ===================================================================
40805 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
40806 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/dma-mapping_64.h 2007-06-12 13:14:13.000000000 +0200
40808 +#ifndef _X8664_DMA_MAPPING_H
40809 +#define _X8664_DMA_MAPPING_H 1
40812 + * IOMMU interface. See Documentation/DMA-mapping.txt and DMA-API.txt for
40817 +#include <asm/scatterlist.h>
40818 +#include <asm/io.h>
40819 +#include <asm/swiotlb.h>
40821 +struct dma_mapping_ops {
40822 + int (*mapping_error)(dma_addr_t dma_addr);
40823 + void* (*alloc_coherent)(struct device *dev, size_t size,
40824 + dma_addr_t *dma_handle, gfp_t gfp);
40825 + void (*free_coherent)(struct device *dev, size_t size,
40826 + void *vaddr, dma_addr_t dma_handle);
40827 + dma_addr_t (*map_single)(struct device *hwdev, void *ptr,
40828 + size_t size, int direction);
40829 + /* like map_single, but doesn't check the device mask */
40830 + dma_addr_t (*map_simple)(struct device *hwdev, char *ptr,
40831 + size_t size, int direction);
40832 + void (*unmap_single)(struct device *dev, dma_addr_t addr,
40833 + size_t size, int direction);
40834 + void (*sync_single_for_cpu)(struct device *hwdev,
40835 + dma_addr_t dma_handle, size_t size,
40837 + void (*sync_single_for_device)(struct device *hwdev,
40838 + dma_addr_t dma_handle, size_t size,
40840 + void (*sync_single_range_for_cpu)(struct device *hwdev,
40841 + dma_addr_t dma_handle, unsigned long offset,
40842 + size_t size, int direction);
40843 + void (*sync_single_range_for_device)(struct device *hwdev,
40844 + dma_addr_t dma_handle, unsigned long offset,
40845 + size_t size, int direction);
40846 + void (*sync_sg_for_cpu)(struct device *hwdev,
40847 + struct scatterlist *sg, int nelems,
40849 + void (*sync_sg_for_device)(struct device *hwdev,
40850 + struct scatterlist *sg, int nelems,
40852 + int (*map_sg)(struct device *hwdev, struct scatterlist *sg,
40853 + int nents, int direction);
40854 + void (*unmap_sg)(struct device *hwdev,
40855 + struct scatterlist *sg, int nents,
40857 + int (*dma_supported)(struct device *hwdev, u64 mask);
40861 +extern dma_addr_t bad_dma_address;
40862 +extern struct dma_mapping_ops* dma_ops;
40863 +extern int iommu_merge;
40865 +static inline int valid_dma_direction(int dma_direction)
40867 + return ((dma_direction == DMA_BIDIRECTIONAL) ||
40868 + (dma_direction == DMA_TO_DEVICE) ||
40869 + (dma_direction == DMA_FROM_DEVICE));
40873 +static inline int dma_mapping_error(dma_addr_t dma_addr)
40875 + if (dma_ops->mapping_error)
40876 + return dma_ops->mapping_error(dma_addr);
40878 + return (dma_addr == bad_dma_address);
40881 +extern void *dma_alloc_coherent(struct device *dev, size_t size,
40882 + dma_addr_t *dma_handle, gfp_t gfp);
40883 +extern void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
40884 + dma_addr_t dma_handle);
40886 +static inline dma_addr_t
40887 +dma_map_single(struct device *hwdev, void *ptr, size_t size,
40890 + BUG_ON(!valid_dma_direction(direction));
40891 + return dma_ops->map_single(hwdev, ptr, size, direction);
40894 +static inline void
40895 +dma_unmap_single(struct device *dev, dma_addr_t addr,size_t size,
40898 + BUG_ON(!valid_dma_direction(direction));
40899 + dma_ops->unmap_single(dev, addr, size, direction);
40902 +#define dma_map_page(dev,page,offset,size,dir) \
40903 + dma_map_single((dev), page_address(page)+(offset), (size), (dir))
40905 +#define dma_unmap_page dma_unmap_single
40907 +static inline void
40908 +dma_sync_single_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
40909 + size_t size, int direction)
40911 + BUG_ON(!valid_dma_direction(direction));
40912 + if (dma_ops->sync_single_for_cpu)
40913 + dma_ops->sync_single_for_cpu(hwdev, dma_handle, size,
40915 + flush_write_buffers();
40918 +static inline void
40919 +dma_sync_single_for_device(struct device *hwdev, dma_addr_t dma_handle,
40920 + size_t size, int direction)
40922 + BUG_ON(!valid_dma_direction(direction));
40923 + if (dma_ops->sync_single_for_device)
40924 + dma_ops->sync_single_for_device(hwdev, dma_handle, size,
40926 + flush_write_buffers();
40929 +static inline void
40930 +dma_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
40931 + unsigned long offset, size_t size, int direction)
40933 + BUG_ON(!valid_dma_direction(direction));
40934 + if (dma_ops->sync_single_range_for_cpu) {
40935 + dma_ops->sync_single_range_for_cpu(hwdev, dma_handle, offset, size, direction);
40938 + flush_write_buffers();
40941 +static inline void
40942 +dma_sync_single_range_for_device(struct device *hwdev, dma_addr_t dma_handle,
40943 + unsigned long offset, size_t size, int direction)
40945 + BUG_ON(!valid_dma_direction(direction));
40946 + if (dma_ops->sync_single_range_for_device)
40947 + dma_ops->sync_single_range_for_device(hwdev, dma_handle,
40948 + offset, size, direction);
40950 + flush_write_buffers();
40953 +static inline void
40954 +dma_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
40955 + int nelems, int direction)
40957 + BUG_ON(!valid_dma_direction(direction));
40958 + if (dma_ops->sync_sg_for_cpu)
40959 + dma_ops->sync_sg_for_cpu(hwdev, sg, nelems, direction);
40960 + flush_write_buffers();
40963 +static inline void
40964 +dma_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
40965 + int nelems, int direction)
40967 + BUG_ON(!valid_dma_direction(direction));
40968 + if (dma_ops->sync_sg_for_device) {
40969 + dma_ops->sync_sg_for_device(hwdev, sg, nelems, direction);
40972 + flush_write_buffers();
40976 +dma_map_sg(struct device *hwdev, struct scatterlist *sg, int nents, int direction)
40978 + BUG_ON(!valid_dma_direction(direction));
40979 + return dma_ops->map_sg(hwdev, sg, nents, direction);
40982 +static inline void
40983 +dma_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
40986 + BUG_ON(!valid_dma_direction(direction));
40987 + dma_ops->unmap_sg(hwdev, sg, nents, direction);
40990 +extern int dma_supported(struct device *hwdev, u64 mask);
40992 +/* same for gart, swiotlb, and nommu */
40993 +static inline int dma_get_cache_alignment(void)
40995 + return boot_cpu_data.x86_clflush_size;
40998 +#define dma_is_consistent(h) 1
41000 +extern int dma_set_mask(struct device *dev, u64 mask);
41002 +static inline void
41003 +dma_cache_sync(void *vaddr, size_t size, enum dma_data_direction dir)
41005 + flush_write_buffers();
41008 +extern struct device fallback_dev;
41009 +extern int panic_on_overflow;
41012 +#endif /* _X8664_DMA_MAPPING_H */
41014 +#include <asm-i386/mach-xen/asm/dma-mapping.h>
41015 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/fixmap_64.h
41016 ===================================================================
41017 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
41018 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/fixmap_64.h 2007-06-12 13:14:13.000000000 +0200
41021 + * fixmap.h: compile-time virtual memory allocation
41023 + * This file is subject to the terms and conditions of the GNU General Public
41024 + * License. See the file "COPYING" in the main directory of this archive
41025 + * for more details.
41027 + * Copyright (C) 1998 Ingo Molnar
41030 +#ifndef _ASM_FIXMAP_H
41031 +#define _ASM_FIXMAP_H
41033 +#include <linux/kernel.h>
41034 +#include <asm/apicdef.h>
41035 +#include <asm/page.h>
41036 +#include <asm/vsyscall.h>
41037 +#include <asm/vsyscall32.h>
41038 +#include <asm/acpi.h>
41041 + * Here we define all the compile-time 'special' virtual
41042 + * addresses. The point is to have a constant address at
41043 + * compile time, but to set the physical address only
41044 + * in the boot process.
41046 + * these 'compile-time allocated' memory buffers are
41047 + * fixed-size 4k pages. (or larger if used with an increment
41048 + * highger than 1) use fixmap_set(idx,phys) to associate
41049 + * physical memory with fixmap indices.
41051 + * TLB entries of such buffers will not be flushed across
41055 +enum fixed_addresses {
41056 + VSYSCALL_LAST_PAGE,
41057 + VSYSCALL_FIRST_PAGE = VSYSCALL_LAST_PAGE + ((VSYSCALL_END-VSYSCALL_START) >> PAGE_SHIFT) - 1,
41060 +#ifdef CONFIG_X86_LOCAL_APIC
41061 + FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */
41063 +#ifdef CONFIG_X86_IO_APIC
41064 + FIX_IO_APIC_BASE_0,
41065 + FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS-1,
41067 +#ifdef CONFIG_ACPI
41069 + FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
41072 +#define NR_FIX_ISAMAPS 256
41074 + FIX_ISAMAP_BEGIN = FIX_ISAMAP_END + NR_FIX_ISAMAPS - 1,
41075 + __end_of_permanent_fixed_addresses,
41076 + /* temporary boot-time mappings, used before ioremap() is functional */
41077 +#define NR_FIX_BTMAPS 16
41078 + FIX_BTMAP_END = __end_of_permanent_fixed_addresses,
41079 + FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS - 1,
41080 + __end_of_fixed_addresses
41083 +extern void __set_fixmap (enum fixed_addresses idx,
41084 + unsigned long phys, pgprot_t flags);
41086 +#define set_fixmap(idx, phys) \
41087 + __set_fixmap(idx, phys, PAGE_KERNEL)
41089 + * Some hardware wants to get fixmapped without caching.
41091 +#define set_fixmap_nocache(idx, phys) \
41092 + __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
41094 +#define clear_fixmap(idx) \
41095 + __set_fixmap(idx, 0, __pgprot(0))
41097 +#define FIXADDR_TOP (VSYSCALL_END-PAGE_SIZE)
41098 +#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
41099 +#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
41101 +/* Only covers 32bit vsyscalls currently. Need another set for 64bit. */
41102 +#define FIXADDR_USER_START ((unsigned long)VSYSCALL32_VSYSCALL)
41103 +#define FIXADDR_USER_END (FIXADDR_USER_START + PAGE_SIZE)
41105 +#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
41107 +extern void __this_fixmap_does_not_exist(void);
41110 + * 'index to address' translation. If anyone tries to use the idx
41111 + * directly without translation, we catch the bug with a NULL-deference
41112 + * kernel oops. Illegal ranges of incoming indices are caught too.
41114 +static __always_inline unsigned long fix_to_virt(const unsigned int idx)
41117 + * this branch gets completely eliminated after inlining,
41118 + * except when someone tries to use fixaddr indices in an
41119 + * illegal way. (such as mixing up address types or using
41120 + * out-of-range indices).
41122 + * If it doesn't get removed, the linker will complain
41123 + * loudly with a reasonably clear error message..
41125 + if (idx >= __end_of_fixed_addresses)
41126 + __this_fixmap_does_not_exist();
41128 + return __fix_to_virt(idx);
41132 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/hypercall_64.h
41133 ===================================================================
41134 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
41135 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/hypercall_64.h 2008-11-25 12:22:34.000000000 +0100
41137 +/******************************************************************************
41140 + * Linux-specific hypervisor handling.
41142 + * Copyright (c) 2002-2004, K A Fraser
41144 + * 64-bit updates:
41145 + * Benjamin Liu <benjamin.liu@intel.com>
41146 + * Jun Nakajima <jun.nakajima@intel.com>
41148 + * This program is free software; you can redistribute it and/or
41149 + * modify it under the terms of the GNU General Public License version 2
41150 + * as published by the Free Software Foundation; or, when distributed
41151 + * separately from the Linux kernel or incorporated into other
41152 + * software packages, subject to the following license:
41154 + * Permission is hereby granted, free of charge, to any person obtaining a copy
41155 + * of this source file (the "Software"), to deal in the Software without
41156 + * restriction, including without limitation the rights to use, copy, modify,
41157 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
41158 + * and to permit persons to whom the Software is furnished to do so, subject to
41159 + * the following conditions:
41161 + * The above copyright notice and this permission notice shall be included in
41162 + * all copies or substantial portions of the Software.
41164 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41165 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
41166 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
41167 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
41168 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41169 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
41170 + * IN THE SOFTWARE.
41173 +#ifndef __HYPERCALL_H__
41174 +#define __HYPERCALL_H__
41176 +#include <linux/string.h> /* memcpy() */
41177 +#include <linux/stringify.h>
41179 +#ifndef __HYPERVISOR_H__
41180 +# error "please don't include this file directly"
41184 +#define HYPERCALL_STR(name) \
41185 + "call hypercall_page + ("__stringify(__HYPERVISOR_##name)" * 32)"
41187 +#define HYPERCALL_STR(name) \
41188 + "mov $("__stringify(__HYPERVISOR_##name)" * 32),%%eax; "\
41189 + "add hypercall_stubs(%%rip),%%rax; " \
41193 +#define _hypercall0(type, name) \
41197 + HYPERCALL_STR(name) \
41204 +#define _hypercall1(type, name, a1) \
41209 + HYPERCALL_STR(name) \
41210 + : "=a" (__res), "=D" (__ign1) \
41211 + : "1" ((long)(a1)) \
41216 +#define _hypercall2(type, name, a1, a2) \
41219 + long __ign1, __ign2; \
41221 + HYPERCALL_STR(name) \
41222 + : "=a" (__res), "=D" (__ign1), "=S" (__ign2) \
41223 + : "1" ((long)(a1)), "2" ((long)(a2)) \
41228 +#define _hypercall3(type, name, a1, a2, a3) \
41231 + long __ign1, __ign2, __ign3; \
41233 + HYPERCALL_STR(name) \
41234 + : "=a" (__res), "=D" (__ign1), "=S" (__ign2), \
41236 + : "1" ((long)(a1)), "2" ((long)(a2)), \
41237 + "3" ((long)(a3)) \
41242 +#define _hypercall4(type, name, a1, a2, a3, a4) \
41245 + long __ign1, __ign2, __ign3; \
41246 + register long __arg4 asm("r10") = (long)(a4); \
41248 + HYPERCALL_STR(name) \
41249 + : "=a" (__res), "=D" (__ign1), "=S" (__ign2), \
41250 + "=d" (__ign3), "+r" (__arg4) \
41251 + : "1" ((long)(a1)), "2" ((long)(a2)), \
41252 + "3" ((long)(a3)) \
41257 +#define _hypercall5(type, name, a1, a2, a3, a4, a5) \
41260 + long __ign1, __ign2, __ign3; \
41261 + register long __arg4 asm("r10") = (long)(a4); \
41262 + register long __arg5 asm("r8") = (long)(a5); \
41264 + HYPERCALL_STR(name) \
41265 + : "=a" (__res), "=D" (__ign1), "=S" (__ign2), \
41266 + "=d" (__ign3), "+r" (__arg4), "+r" (__arg5) \
41267 + : "1" ((long)(a1)), "2" ((long)(a2)), \
41268 + "3" ((long)(a3)) \
41273 +static inline int __must_check
41274 +HYPERVISOR_set_trap_table(
41275 + const trap_info_t *table)
41277 + return _hypercall1(int, set_trap_table, table);
41280 +static inline int __must_check
41281 +HYPERVISOR_mmu_update(
41282 + mmu_update_t *req, unsigned int count, unsigned int *success_count,
41285 + return _hypercall4(int, mmu_update, req, count, success_count, domid);
41288 +static inline int __must_check
41289 +HYPERVISOR_mmuext_op(
41290 + struct mmuext_op *op, unsigned int count, unsigned int *success_count,
41293 + return _hypercall4(int, mmuext_op, op, count, success_count, domid);
41296 +static inline int __must_check
41297 +HYPERVISOR_set_gdt(
41298 + unsigned long *frame_list, unsigned int entries)
41300 + return _hypercall2(int, set_gdt, frame_list, entries);
41303 +static inline int __must_check
41304 +HYPERVISOR_stack_switch(
41305 + unsigned long ss, unsigned long esp)
41307 + return _hypercall2(int, stack_switch, ss, esp);
41310 +static inline int __must_check
41311 +HYPERVISOR_set_callbacks(
41312 + unsigned long event_address, unsigned long failsafe_address,
41313 + unsigned long syscall_address)
41315 + return _hypercall3(int, set_callbacks,
41316 + event_address, failsafe_address, syscall_address);
41320 +HYPERVISOR_fpu_taskswitch(
41323 + return _hypercall1(int, fpu_taskswitch, set);
41326 +static inline int __must_check
41327 +HYPERVISOR_sched_op_compat(
41328 + int cmd, unsigned long arg)
41330 + return _hypercall2(int, sched_op_compat, cmd, arg);
41333 +static inline int __must_check
41334 +HYPERVISOR_sched_op(
41335 + int cmd, void *arg)
41337 + return _hypercall2(int, sched_op, cmd, arg);
41340 +static inline long __must_check
41341 +HYPERVISOR_set_timer_op(
41344 + return _hypercall1(long, set_timer_op, timeout);
41347 +static inline int __must_check
41348 +HYPERVISOR_platform_op(
41349 + struct xen_platform_op *platform_op)
41351 + platform_op->interface_version = XENPF_INTERFACE_VERSION;
41352 + return _hypercall1(int, platform_op, platform_op);
41355 +static inline int __must_check
41356 +HYPERVISOR_set_debugreg(
41357 + unsigned int reg, unsigned long value)
41359 + return _hypercall2(int, set_debugreg, reg, value);
41362 +static inline unsigned long __must_check
41363 +HYPERVISOR_get_debugreg(
41364 + unsigned int reg)
41366 + return _hypercall1(unsigned long, get_debugreg, reg);
41369 +static inline int __must_check
41370 +HYPERVISOR_update_descriptor(
41371 + unsigned long ma, unsigned long word)
41373 + return _hypercall2(int, update_descriptor, ma, word);
41376 +static inline int __must_check
41377 +HYPERVISOR_memory_op(
41378 + unsigned int cmd, void *arg)
41380 + return _hypercall2(int, memory_op, cmd, arg);
41383 +static inline int __must_check
41384 +HYPERVISOR_multicall(
41385 + multicall_entry_t *call_list, unsigned int nr_calls)
41387 + return _hypercall2(int, multicall, call_list, nr_calls);
41390 +static inline int __must_check
41391 +HYPERVISOR_update_va_mapping(
41392 + unsigned long va, pte_t new_val, unsigned long flags)
41394 + return _hypercall3(int, update_va_mapping, va, new_val.pte, flags);
41397 +static inline int __must_check
41398 +HYPERVISOR_event_channel_op(
41399 + int cmd, void *arg)
41401 + int rc = _hypercall2(int, event_channel_op, cmd, arg);
41403 +#if CONFIG_XEN_COMPAT <= 0x030002
41404 + if (unlikely(rc == -ENOSYS)) {
41405 + struct evtchn_op op;
41407 + memcpy(&op.u, arg, sizeof(op.u));
41408 + rc = _hypercall1(int, event_channel_op_compat, &op);
41409 + memcpy(arg, &op.u, sizeof(op.u));
41416 +static inline int __must_check
41417 +HYPERVISOR_xen_version(
41418 + int cmd, void *arg)
41420 + return _hypercall2(int, xen_version, cmd, arg);
41423 +static inline int __must_check
41424 +HYPERVISOR_console_io(
41425 + int cmd, unsigned int count, char *str)
41427 + return _hypercall3(int, console_io, cmd, count, str);
41430 +static inline int __must_check
41431 +HYPERVISOR_physdev_op(
41432 + int cmd, void *arg)
41434 + int rc = _hypercall2(int, physdev_op, cmd, arg);
41436 +#if CONFIG_XEN_COMPAT <= 0x030002
41437 + if (unlikely(rc == -ENOSYS)) {
41438 + struct physdev_op op;
41440 + memcpy(&op.u, arg, sizeof(op.u));
41441 + rc = _hypercall1(int, physdev_op_compat, &op);
41442 + memcpy(arg, &op.u, sizeof(op.u));
41449 +static inline int __must_check
41450 +HYPERVISOR_grant_table_op(
41451 + unsigned int cmd, void *uop, unsigned int count)
41453 + return _hypercall3(int, grant_table_op, cmd, uop, count);
41456 +static inline int __must_check
41457 +HYPERVISOR_update_va_mapping_otherdomain(
41458 + unsigned long va, pte_t new_val, unsigned long flags, domid_t domid)
41460 + return _hypercall4(int, update_va_mapping_otherdomain, va,
41461 + new_val.pte, flags, domid);
41464 +static inline int __must_check
41465 +HYPERVISOR_vm_assist(
41466 + unsigned int cmd, unsigned int type)
41468 + return _hypercall2(int, vm_assist, cmd, type);
41471 +static inline int __must_check
41472 +HYPERVISOR_vcpu_op(
41473 + int cmd, unsigned int vcpuid, void *extra_args)
41475 + return _hypercall3(int, vcpu_op, cmd, vcpuid, extra_args);
41478 +static inline int __must_check
41479 +HYPERVISOR_set_segment_base(
41480 + int reg, unsigned long value)
41482 + return _hypercall2(int, set_segment_base, reg, value);
41485 +static inline int __must_check
41486 +HYPERVISOR_suspend(
41487 + unsigned long srec)
41489 + struct sched_shutdown sched_shutdown = {
41490 + .reason = SHUTDOWN_suspend
41493 + int rc = _hypercall3(int, sched_op, SCHEDOP_shutdown,
41494 + &sched_shutdown, srec);
41496 +#if CONFIG_XEN_COMPAT <= 0x030002
41497 + if (rc == -ENOSYS)
41498 + rc = _hypercall3(int, sched_op_compat, SCHEDOP_shutdown,
41499 + SHUTDOWN_suspend, srec);
41505 +#if CONFIG_XEN_COMPAT <= 0x030002
41507 +HYPERVISOR_nmi_op(
41508 + unsigned long op, void *arg)
41510 + return _hypercall2(int, nmi_op, op, arg);
41514 +#ifndef CONFIG_XEN
41515 +static inline unsigned long __must_check
41516 +HYPERVISOR_hvm_op(
41517 + int op, void *arg)
41519 + return _hypercall2(unsigned long, hvm_op, op, arg);
41523 +static inline int __must_check
41524 +HYPERVISOR_callback_op(
41525 + int cmd, const void *arg)
41527 + return _hypercall2(int, callback_op, cmd, arg);
41530 +static inline int __must_check
41531 +HYPERVISOR_xenoprof_op(
41532 + int op, void *arg)
41534 + return _hypercall2(int, xenoprof_op, op, arg);
41537 +static inline int __must_check
41538 +HYPERVISOR_kexec_op(
41539 + unsigned long op, void *args)
41541 + return _hypercall2(int, kexec_op, op, args);
41544 +#endif /* __HYPERCALL_H__ */
41545 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/irqflags_64.h
41546 ===================================================================
41547 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
41548 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/irqflags_64.h 2007-06-12 13:14:13.000000000 +0200
41551 + * include/asm-x86_64/irqflags.h
41553 + * IRQ flags handling
41555 + * This file gets included from lowlevel asm headers too, to provide
41556 + * wrapped versions of the local_irq_*() APIs, based on the
41557 + * raw_local_irq_*() functions from the lowlevel headers.
41559 +#ifndef _ASM_IRQFLAGS_H
41560 +#define _ASM_IRQFLAGS_H
41562 +#ifndef __ASSEMBLY__
41564 + * Interrupt control:
41568 + * The use of 'barrier' in the following reflects their use as local-lock
41569 + * operations. Reentrancy must be prevented (e.g., __cli()) /before/ following
41570 + * critical operations are executed. All critical operations must complete
41571 + * /before/ reentrancy is permitted (e.g., __sti()). Alpha architecture also
41572 + * includes these barriers, for example.
41575 +#define __raw_local_save_flags() (current_vcpu_info()->evtchn_upcall_mask)
41577 +#define raw_local_save_flags(flags) \
41578 + do { (flags) = __raw_local_save_flags(); } while (0)
41580 +#define raw_local_irq_restore(x) \
41582 + vcpu_info_t *_vcpu; \
41584 + _vcpu = current_vcpu_info(); \
41585 + if ((_vcpu->evtchn_upcall_mask = (x)) == 0) { \
41586 + barrier(); /* unmask then check (avoid races) */ \
41587 + if ( unlikely(_vcpu->evtchn_upcall_pending) ) \
41588 + force_evtchn_callback(); \
41592 +#ifdef CONFIG_X86_VSMP
41595 + * Interrupt control for the VSMP architecture:
41598 +static inline void raw_local_irq_disable(void)
41600 + unsigned long flags = __raw_local_save_flags();
41602 + raw_local_irq_restore((flags & ~(1 << 9)) | (1 << 18));
41605 +static inline void raw_local_irq_enable(void)
41607 + unsigned long flags = __raw_local_save_flags();
41609 + raw_local_irq_restore((flags | (1 << 9)) & ~(1 << 18));
41612 +static inline int raw_irqs_disabled_flags(unsigned long flags)
41614 + return !(flags & (1<<9)) || (flags & (1 << 18));
41617 +#else /* CONFIG_X86_VSMP */
41619 +#define raw_local_irq_disable() \
41621 + current_vcpu_info()->evtchn_upcall_mask = 1; \
41625 +#define raw_local_irq_enable() \
41627 + vcpu_info_t *_vcpu; \
41629 + _vcpu = current_vcpu_info(); \
41630 + _vcpu->evtchn_upcall_mask = 0; \
41631 + barrier(); /* unmask then check (avoid races) */ \
41632 + if ( unlikely(_vcpu->evtchn_upcall_pending) ) \
41633 + force_evtchn_callback(); \
41636 +static inline int raw_irqs_disabled_flags(unsigned long flags)
41638 + return (flags != 0);
41644 + * For spinlocks, etc.:
41647 +#define __raw_local_irq_save() \
41649 + unsigned long flags = __raw_local_save_flags(); \
41651 + raw_local_irq_disable(); \
41656 +#define raw_local_irq_save(flags) \
41657 + do { (flags) = __raw_local_irq_save(); } while (0)
41659 +#define raw_irqs_disabled() \
41661 + unsigned long flags = __raw_local_save_flags(); \
41663 + raw_irqs_disabled_flags(flags); \
41667 + * Used in the idle loop; sti takes one instruction cycle
41670 +void raw_safe_halt(void);
41673 + * Used when interrupts are already enabled or to
41674 + * shutdown the processor:
41678 +#else /* __ASSEMBLY__: */
41679 +# ifdef CONFIG_TRACE_IRQFLAGS
41680 +# define TRACE_IRQS_ON call trace_hardirqs_on_thunk
41681 +# define TRACE_IRQS_OFF call trace_hardirqs_off_thunk
41683 +# define TRACE_IRQS_ON
41684 +# define TRACE_IRQS_OFF
41689 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/maddr_64.h
41690 ===================================================================
41691 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
41692 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/maddr_64.h 2007-06-12 13:14:13.000000000 +0200
41694 +#ifndef _X86_64_MADDR_H
41695 +#define _X86_64_MADDR_H
41697 +#include <xen/features.h>
41698 +#include <xen/interface/xen.h>
41700 +/**** MACHINE <-> PHYSICAL CONVERSION MACROS ****/
41701 +#define INVALID_P2M_ENTRY (~0UL)
41702 +#define FOREIGN_FRAME_BIT (1UL<<63)
41703 +#define FOREIGN_FRAME(m) ((m) | FOREIGN_FRAME_BIT)
41705 +/* Definitions for machine and pseudophysical addresses. */
41706 +typedef unsigned long paddr_t;
41707 +typedef unsigned long maddr_t;
41711 +extern unsigned long *phys_to_machine_mapping;
41713 +#undef machine_to_phys_mapping
41714 +extern unsigned long *machine_to_phys_mapping;
41715 +extern unsigned int machine_to_phys_order;
41717 +static inline unsigned long pfn_to_mfn(unsigned long pfn)
41719 + if (xen_feature(XENFEAT_auto_translated_physmap))
41721 + BUG_ON(end_pfn && pfn >= end_pfn);
41722 + return phys_to_machine_mapping[pfn] & ~FOREIGN_FRAME_BIT;
41725 +static inline int phys_to_machine_mapping_valid(unsigned long pfn)
41727 + if (xen_feature(XENFEAT_auto_translated_physmap))
41729 + BUG_ON(end_pfn && pfn >= end_pfn);
41730 + return (phys_to_machine_mapping[pfn] != INVALID_P2M_ENTRY);
41733 +static inline unsigned long mfn_to_pfn(unsigned long mfn)
41735 + unsigned long pfn;
41737 + if (xen_feature(XENFEAT_auto_translated_physmap))
41740 + if (unlikely((mfn >> machine_to_phys_order) != 0))
41743 + /* The array access can fail (e.g., device space beyond end of RAM). */
41745 + "1: movq %1,%0\n"
41747 + ".section .fixup,\"ax\"\n"
41748 + "3: movq %2,%0\n"
41751 + ".section __ex_table,\"a\"\n"
41756 + : "m" (machine_to_phys_mapping[mfn]), "m" (end_pfn) );
41762 + * We detect special mappings in one of two ways:
41763 + * 1. If the MFN is an I/O page then Xen will set the m2p entry
41764 + * to be outside our maximum possible pseudophys range.
41765 + * 2. If the MFN belongs to a different domain then we will certainly
41766 + * not have MFN in our p2m table. Conversely, if the page is ours,
41767 + * then we'll have p2m(m2p(MFN))==MFN.
41768 + * If we detect a special mapping then it doesn't have a 'struct page'.
41769 + * We force !pfn_valid() by returning an out-of-range pointer.
41771 + * NB. These checks require that, for any MFN that is not in our reservation,
41772 + * there is no PFN such that p2m(PFN) == MFN. Otherwise we can get confused if
41773 + * we are foreign-mapping the MFN, and the other domain as m2p(MFN) == PFN.
41774 + * Yikes! Various places must poke in INVALID_P2M_ENTRY for safety.
41776 + * NB2. When deliberately mapping foreign pages into the p2m table, you *must*
41777 + * use FOREIGN_FRAME(). This will cause pte_pfn() to choke on it, as we
41778 + * require. In all the cases we care about, the FOREIGN_FRAME bit is
41779 + * masked (e.g., pfn_to_mfn()) so behaviour there is correct.
41781 +static inline unsigned long mfn_to_local_pfn(unsigned long mfn)
41783 + unsigned long pfn = mfn_to_pfn(mfn);
41784 + if ((pfn < end_pfn)
41785 + && !xen_feature(XENFEAT_auto_translated_physmap)
41786 + && (phys_to_machine_mapping[pfn] != mfn))
41787 + return end_pfn; /* force !pfn_valid() */
41791 +static inline void set_phys_to_machine(unsigned long pfn, unsigned long mfn)
41793 + BUG_ON(end_pfn && pfn >= end_pfn);
41794 + if (xen_feature(XENFEAT_auto_translated_physmap)) {
41795 + BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY);
41798 + phys_to_machine_mapping[pfn] = mfn;
41801 +static inline maddr_t phys_to_machine(paddr_t phys)
41803 + maddr_t machine = pfn_to_mfn(phys >> PAGE_SHIFT);
41804 + machine = (machine << PAGE_SHIFT) | (phys & ~PAGE_MASK);
41808 +static inline paddr_t machine_to_phys(maddr_t machine)
41810 + paddr_t phys = mfn_to_pfn(machine >> PAGE_SHIFT);
41811 + phys = (phys << PAGE_SHIFT) | (machine & ~PAGE_MASK);
41815 +static inline paddr_t pte_phys_to_machine(paddr_t phys)
41818 + machine = pfn_to_mfn((phys & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT);
41819 + machine = (machine << PAGE_SHIFT) | (phys & ~PHYSICAL_PAGE_MASK);
41823 +static inline paddr_t pte_machine_to_phys(maddr_t machine)
41826 + phys = mfn_to_pfn((machine & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT);
41827 + phys = (phys << PAGE_SHIFT) | (machine & ~PHYSICAL_PAGE_MASK);
41831 +#define __pte_ma(x) ((pte_t) { (x) } )
41832 +#define pfn_pte_ma(pfn, prot) __pte_ma((((pfn) << PAGE_SHIFT) | pgprot_val(prot)) & __supported_pte_mask)
41834 +#else /* !CONFIG_XEN */
41836 +#define pfn_to_mfn(pfn) (pfn)
41837 +#define mfn_to_pfn(mfn) (mfn)
41838 +#define mfn_to_local_pfn(mfn) (mfn)
41839 +#define set_phys_to_machine(pfn, mfn) ((void)0)
41840 +#define phys_to_machine_mapping_valid(pfn) (1)
41841 +#define phys_to_machine(phys) ((maddr_t)(phys))
41842 +#define machine_to_phys(mach) ((paddr_t)(mach))
41843 +#define pfn_pte_ma(pfn, prot) pfn_pte(pfn, prot)
41844 +#define __pte_ma(x) __pte(x)
41846 +#endif /* !CONFIG_XEN */
41848 +/* VIRT <-> MACHINE conversion */
41849 +#define virt_to_machine(v) (phys_to_machine(__pa(v)))
41850 +#define virt_to_mfn(v) (pfn_to_mfn(__pa(v) >> PAGE_SHIFT))
41851 +#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT))
41853 +#endif /* _X86_64_MADDR_H */
41855 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/mmu_context_64.h
41856 ===================================================================
41857 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
41858 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/mmu_context_64.h 2007-06-12 13:14:13.000000000 +0200
41860 +#ifndef __X86_64_MMU_CONTEXT_H
41861 +#define __X86_64_MMU_CONTEXT_H
41863 +#include <asm/desc.h>
41864 +#include <asm/atomic.h>
41865 +#include <asm/pgalloc.h>
41866 +#include <asm/page.h>
41867 +#include <asm/pda.h>
41868 +#include <asm/pgtable.h>
41869 +#include <asm/tlbflush.h>
41872 + * possibly do the LDT unload here?
41874 +int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
41875 +void destroy_context(struct mm_struct *mm);
41877 +static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
41879 +#if defined(CONFIG_SMP) && !defined(CONFIG_XEN)
41880 + if (read_pda(mmu_state) == TLBSTATE_OK)
41881 + write_pda(mmu_state, TLBSTATE_LAZY);
41885 +#define prepare_arch_switch(next) __prepare_arch_switch()
41887 +static inline void __prepare_arch_switch(void)
41890 + * Save away %es, %ds, %fs and %gs. Must happen before reload
41891 + * of cr3/ldt (i.e., not in __switch_to).
41893 + __asm__ __volatile__ (
41894 + "mov %%es,%0 ; mov %%ds,%1 ; mov %%fs,%2 ; mov %%gs,%3"
41895 + : "=m" (current->thread.es),
41896 + "=m" (current->thread.ds),
41897 + "=m" (current->thread.fsindex),
41898 + "=m" (current->thread.gsindex) );
41900 + if (current->thread.ds)
41901 + __asm__ __volatile__ ( "movl %0,%%ds" : : "r" (0) );
41903 + if (current->thread.es)
41904 + __asm__ __volatile__ ( "movl %0,%%es" : : "r" (0) );
41906 + if (current->thread.fsindex) {
41907 + __asm__ __volatile__ ( "movl %0,%%fs" : : "r" (0) );
41908 + current->thread.fs = 0;
41911 + if (current->thread.gsindex) {
41912 + load_gs_index(0);
41913 + current->thread.gs = 0;
41917 +extern void mm_pin(struct mm_struct *mm);
41918 +extern void mm_unpin(struct mm_struct *mm);
41919 +void mm_pin_all(void);
41921 +static inline void load_cr3(pgd_t *pgd)
41923 + asm volatile("movq %0,%%cr3" :: "r" (phys_to_machine(__pa(pgd))) :
41927 +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
41928 + struct task_struct *tsk)
41930 + unsigned cpu = smp_processor_id();
41931 + struct mmuext_op _op[3], *op = _op;
41933 + if (likely(prev != next)) {
41934 + BUG_ON(!xen_feature(XENFEAT_writable_page_tables) &&
41935 + !next->context.pinned);
41937 + /* stop flush ipis for the previous mm */
41938 + cpu_clear(cpu, prev->cpu_vm_mask);
41939 +#if defined(CONFIG_SMP) && !defined(CONFIG_XEN)
41940 + write_pda(mmu_state, TLBSTATE_OK);
41941 + write_pda(active_mm, next);
41943 + cpu_set(cpu, next->cpu_vm_mask);
41945 + /* load_cr3(next->pgd) */
41946 + op->cmd = MMUEXT_NEW_BASEPTR;
41947 + op->arg1.mfn = pfn_to_mfn(__pa(next->pgd) >> PAGE_SHIFT);
41950 + /* xen_new_user_pt(__pa(__user_pgd(next->pgd))) */
41951 + op->cmd = MMUEXT_NEW_USER_BASEPTR;
41952 + op->arg1.mfn = pfn_to_mfn(__pa(__user_pgd(next->pgd)) >> PAGE_SHIFT);
41955 + if (unlikely(next->context.ldt != prev->context.ldt)) {
41956 + /* load_LDT_nolock(&next->context, cpu) */
41957 + op->cmd = MMUEXT_SET_LDT;
41958 + op->arg1.linear_addr = (unsigned long)next->context.ldt;
41959 + op->arg2.nr_ents = next->context.size;
41963 + BUG_ON(HYPERVISOR_mmuext_op(_op, op-_op, NULL, DOMID_SELF));
41965 +#if defined(CONFIG_SMP) && !defined(CONFIG_XEN)
41967 + write_pda(mmu_state, TLBSTATE_OK);
41968 + if (read_pda(active_mm) != next)
41969 + out_of_line_bug();
41970 + if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
41971 + /* We were in lazy tlb mode and leave_mm disabled
41972 + * tlb flush IPI delivery. We must reload CR3
41973 + * to make sure to use no freed page tables.
41975 + load_cr3(next->pgd);
41976 + xen_new_user_pt(__pa(__user_pgd(next->pgd)));
41977 + load_LDT_nolock(&next->context, cpu);
41983 +#define deactivate_mm(tsk,mm) do { \
41984 + load_gs_index(0); \
41985 + asm volatile("movl %0,%%fs"::"r"(0)); \
41988 +static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
41990 + if (!next->context.pinned)
41992 + switch_mm(prev, next, NULL);
41996 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/page_64.h
41997 ===================================================================
41998 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
41999 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/page_64.h 2008-04-02 12:34:02.000000000 +0200
42001 +#ifndef _X86_64_PAGE_H
42002 +#define _X86_64_PAGE_H
42004 +/* #include <linux/string.h> */
42005 +#ifndef __ASSEMBLY__
42006 +#include <linux/kernel.h>
42007 +#include <linux/types.h>
42008 +#include <asm/bug.h>
42010 +#include <xen/interface/xen.h>
42013 + * Need to repeat this here in order to not include pgtable.h (which in turn
42014 + * depends on definitions made here), but to be able to use the symbolic
42015 + * below. The preprocessor will warn if the two definitions aren't identical.
42017 +#define _PAGE_PRESENT 0x001
42018 +#define _PAGE_IO 0x200
42020 +/* PAGE_SHIFT determines the page size */
42021 +#define PAGE_SHIFT 12
42022 +#ifdef __ASSEMBLY__
42023 +#define PAGE_SIZE (0x1 << PAGE_SHIFT)
42025 +#define PAGE_SIZE (1UL << PAGE_SHIFT)
42027 +#define PAGE_MASK (~(PAGE_SIZE-1))
42029 +/* See Documentation/x86_64/mm.txt for a description of the memory map. */
42030 +#define __PHYSICAL_MASK_SHIFT 46
42031 +#define __PHYSICAL_MASK ((1UL << __PHYSICAL_MASK_SHIFT) - 1)
42032 +#define __VIRTUAL_MASK_SHIFT 48
42033 +#define __VIRTUAL_MASK ((1UL << __VIRTUAL_MASK_SHIFT) - 1)
42035 +#define PHYSICAL_PAGE_MASK (~(PAGE_SIZE-1) & __PHYSICAL_MASK)
42037 +#define THREAD_ORDER 1
42038 +#define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER)
42039 +#define CURRENT_MASK (~(THREAD_SIZE-1))
42041 +#define EXCEPTION_STACK_ORDER 0
42042 +#define EXCEPTION_STKSZ (PAGE_SIZE << EXCEPTION_STACK_ORDER)
42044 +#define DEBUG_STACK_ORDER (EXCEPTION_STACK_ORDER + 1)
42045 +#define DEBUG_STKSZ (PAGE_SIZE << DEBUG_STACK_ORDER)
42047 +#define IRQSTACK_ORDER 2
42048 +#define IRQSTACKSIZE (PAGE_SIZE << IRQSTACK_ORDER)
42050 +#define STACKFAULT_STACK 1
42051 +#define DOUBLEFAULT_STACK 2
42052 +#define NMI_STACK 3
42053 +#define DEBUG_STACK 4
42054 +#define MCE_STACK 5
42055 +#define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
42057 +#define LARGE_PAGE_MASK (~(LARGE_PAGE_SIZE-1))
42058 +#define LARGE_PAGE_SIZE (1UL << PMD_SHIFT)
42060 +#define HPAGE_SHIFT PMD_SHIFT
42061 +#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
42062 +#define HPAGE_MASK (~(HPAGE_SIZE - 1))
42063 +#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
42066 +#ifndef __ASSEMBLY__
42068 +extern unsigned long end_pfn;
42070 +#include <asm/maddr.h>
42072 +void clear_page(void *);
42073 +void copy_page(void *, void *);
42075 +#define clear_user_page(page, vaddr, pg) clear_page(page)
42076 +#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
42078 +#define alloc_zeroed_user_highpage(vma, vaddr) alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO, vma, vaddr)
42079 +#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
42082 + * These are used to make use of C type-checking..
42084 +typedef struct { unsigned long pte; } pte_t;
42085 +typedef struct { unsigned long pmd; } pmd_t;
42086 +typedef struct { unsigned long pud; } pud_t;
42087 +typedef struct { unsigned long pgd; } pgd_t;
42088 +#define PTE_MASK PHYSICAL_PAGE_MASK
42090 +typedef struct { unsigned long pgprot; } pgprot_t;
42092 +#define __pte_val(x) ((x).pte)
42093 +#define pte_val(x) ((__pte_val(x) & (_PAGE_PRESENT|_PAGE_IO)) \
42094 + == _PAGE_PRESENT ? \
42095 + pte_machine_to_phys(__pte_val(x)) : \
42098 +#define __pmd_val(x) ((x).pmd)
42099 +static inline unsigned long pmd_val(pmd_t x)
42101 + unsigned long ret = __pmd_val(x);
42102 +#if CONFIG_XEN_COMPAT <= 0x030002
42103 + if (ret) ret = pte_machine_to_phys(ret) | _PAGE_PRESENT;
42105 + if (ret & _PAGE_PRESENT) ret = pte_machine_to_phys(ret);
42110 +#define __pud_val(x) ((x).pud)
42111 +static inline unsigned long pud_val(pud_t x)
42113 + unsigned long ret = __pud_val(x);
42114 + if (ret & _PAGE_PRESENT) ret = pte_machine_to_phys(ret);
42118 +#define __pgd_val(x) ((x).pgd)
42119 +static inline unsigned long pgd_val(pgd_t x)
42121 + unsigned long ret = __pgd_val(x);
42122 + if (ret & _PAGE_PRESENT) ret = pte_machine_to_phys(ret);
42126 +#define pgprot_val(x) ((x).pgprot)
42128 +static inline pte_t __pte(unsigned long x)
42130 + if ((x & (_PAGE_PRESENT|_PAGE_IO)) == _PAGE_PRESENT)
42131 + x = pte_phys_to_machine(x);
42132 + return ((pte_t) { (x) });
42135 +static inline pmd_t __pmd(unsigned long x)
42137 + if (x & _PAGE_PRESENT) x = pte_phys_to_machine(x);
42138 + return ((pmd_t) { (x) });
42141 +static inline pud_t __pud(unsigned long x)
42143 + if (x & _PAGE_PRESENT) x = pte_phys_to_machine(x);
42144 + return ((pud_t) { (x) });
42147 +static inline pgd_t __pgd(unsigned long x)
42149 + if (x & _PAGE_PRESENT) x = pte_phys_to_machine(x);
42150 + return ((pgd_t) { (x) });
42153 +#define __pgprot(x) ((pgprot_t) { (x) } )
42155 +#define __PHYSICAL_START ((unsigned long)CONFIG_PHYSICAL_START)
42156 +#define __START_KERNEL (__START_KERNEL_map + __PHYSICAL_START)
42157 +#define __START_KERNEL_map 0xffffffff80000000UL
42158 +#define __PAGE_OFFSET 0xffff880000000000UL
42161 +#define __PHYSICAL_START CONFIG_PHYSICAL_START
42162 +#define __START_KERNEL (__START_KERNEL_map + __PHYSICAL_START)
42163 +#define __START_KERNEL_map 0xffffffff80000000
42164 +#define __PAGE_OFFSET 0xffff880000000000
42165 +#endif /* !__ASSEMBLY__ */
42167 +#if CONFIG_XEN_COMPAT <= 0x030002
42168 +#undef LOAD_OFFSET
42169 +#define LOAD_OFFSET 0
42172 +/* to align the pointer to the (next) page boundary */
42173 +#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
42175 +#define KERNEL_TEXT_SIZE (40UL*1024*1024)
42176 +#define KERNEL_TEXT_START 0xffffffff80000000UL
42178 +#define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET)
42180 +/* Note: __pa(&symbol_visible_to_c) should be always replaced with __pa_symbol.
42181 + Otherwise you risk miscompilation. */
42182 +#define __pa(x) (((unsigned long)(x)>=__START_KERNEL_map)?(unsigned long)(x) - (unsigned long)__START_KERNEL_map:(unsigned long)(x) - PAGE_OFFSET)
42183 +/* __pa_symbol should be used for C visible symbols.
42184 + This seems to be the official gcc blessed way to do such arithmetic. */
42185 +#define __pa_symbol(x) \
42186 + ({unsigned long v; \
42187 + asm("" : "=r" (v) : "0" (x)); \
42190 +#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
42191 +#define __boot_va(x) __va(x)
42192 +#define __boot_pa(x) __pa(x)
42193 +#ifdef CONFIG_FLATMEM
42194 +#define pfn_valid(pfn) ((pfn) < end_pfn)
42197 +#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
42198 +#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
42199 +#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
42201 +#define VM_DATA_DEFAULT_FLAGS \
42202 + (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
42203 + VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
42205 +#define __HAVE_ARCH_GATE_AREA 1
42207 +#include <asm-generic/memory_model.h>
42208 +#include <asm-generic/page.h>
42210 +#endif /* __KERNEL__ */
42212 +#endif /* _X86_64_PAGE_H */
42213 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/pgalloc_64.h
42214 ===================================================================
42215 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
42216 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/pgalloc_64.h 2007-06-18 08:38:13.000000000 +0200
42218 +#ifndef _X86_64_PGALLOC_H
42219 +#define _X86_64_PGALLOC_H
42221 +#include <asm/fixmap.h>
42222 +#include <asm/pda.h>
42223 +#include <linux/threads.h>
42224 +#include <linux/mm.h>
42225 +#include <asm/io.h> /* for phys_to_virt and page_to_pseudophys */
42227 +#include <xen/features.h>
42228 +void make_page_readonly(void *va, unsigned int feature);
42229 +void make_page_writable(void *va, unsigned int feature);
42230 +void make_pages_readonly(void *va, unsigned int nr, unsigned int feature);
42231 +void make_pages_writable(void *va, unsigned int nr, unsigned int feature);
42233 +#define __user_pgd(pgd) ((pgd) + PTRS_PER_PGD)
42235 +static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
42237 + set_pmd(pmd, __pmd(_PAGE_TABLE | __pa(pte)));
42240 +static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte)
42242 + if (unlikely((mm)->context.pinned)) {
42243 + BUG_ON(HYPERVISOR_update_va_mapping(
42244 + (unsigned long)__va(page_to_pfn(pte) << PAGE_SHIFT),
42245 + pfn_pte(page_to_pfn(pte), PAGE_KERNEL_RO), 0));
42246 + set_pmd(pmd, __pmd(_PAGE_TABLE | (page_to_pfn(pte) << PAGE_SHIFT)));
42248 + *(pmd) = __pmd(_PAGE_TABLE | (page_to_pfn(pte) << PAGE_SHIFT));
42252 +static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
42254 + if (unlikely((mm)->context.pinned)) {
42255 + BUG_ON(HYPERVISOR_update_va_mapping(
42256 + (unsigned long)pmd,
42257 + pfn_pte(virt_to_phys(pmd)>>PAGE_SHIFT,
42258 + PAGE_KERNEL_RO), 0));
42259 + set_pud(pud, __pud(_PAGE_TABLE | __pa(pmd)));
42261 + *(pud) = __pud(_PAGE_TABLE | __pa(pmd));
42266 + * We need to use the batch mode here, but pgd_pupulate() won't be
42267 + * be called frequently.
42269 +static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
42271 + if (unlikely((mm)->context.pinned)) {
42272 + BUG_ON(HYPERVISOR_update_va_mapping(
42273 + (unsigned long)pud,
42274 + pfn_pte(virt_to_phys(pud)>>PAGE_SHIFT,
42275 + PAGE_KERNEL_RO), 0));
42276 + set_pgd(pgd, __pgd(_PAGE_TABLE | __pa(pud)));
42277 + set_pgd(__user_pgd(pgd), __pgd(_PAGE_TABLE | __pa(pud)));
42279 + *(pgd) = __pgd(_PAGE_TABLE | __pa(pud));
42280 + *(__user_pgd(pgd)) = *(pgd);
42284 +extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr);
42285 +extern void pte_free(struct page *pte);
42287 +static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
42291 + pg = pte_alloc_one(mm, addr);
42292 + return pg ? page_address(pg) : NULL;
42295 +static inline void pmd_free(pmd_t *pmd)
42297 + BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
42298 + pte_free(virt_to_page(pmd));
42301 +static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
42305 + pg = pte_alloc_one(mm, addr);
42306 + return pg ? page_address(pg) : NULL;
42309 +static inline void pud_free(pud_t *pud)
42311 + BUG_ON((unsigned long)pud & (PAGE_SIZE-1));
42312 + pte_free(virt_to_page(pud));
42315 +static inline void pgd_list_add(pgd_t *pgd)
42317 + struct page *page = virt_to_page(pgd);
42319 + spin_lock(&pgd_lock);
42320 + page->index = (pgoff_t)pgd_list;
42322 + pgd_list->private = (unsigned long)&page->index;
42324 + page->private = (unsigned long)&pgd_list;
42325 + spin_unlock(&pgd_lock);
42328 +static inline void pgd_list_del(pgd_t *pgd)
42330 + struct page *next, **pprev, *page = virt_to_page(pgd);
42332 + spin_lock(&pgd_lock);
42333 + next = (struct page *)page->index;
42334 + pprev = (struct page **)page->private;
42337 + next->private = (unsigned long)pprev;
42338 + spin_unlock(&pgd_lock);
42341 +static inline pgd_t *pgd_alloc(struct mm_struct *mm)
42344 + * We allocate two contiguous pages for kernel and user.
42346 + unsigned boundary;
42347 + pgd_t *pgd = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_REPEAT, 1);
42350 + pgd_list_add(pgd);
42352 + * Copy kernel pointers in from init.
42353 + * Could keep a freelist or slab cache of those because the kernel
42354 + * part never changes.
42356 + boundary = pgd_index(__PAGE_OFFSET);
42357 + memset(pgd, 0, boundary * sizeof(pgd_t));
42358 + memcpy(pgd + boundary,
42359 + init_level4_pgt + boundary,
42360 + (PTRS_PER_PGD - boundary) * sizeof(pgd_t));
42362 + memset(__user_pgd(pgd), 0, PAGE_SIZE); /* clean up user pgd */
42364 + * Set level3_user_pgt for vsyscall area
42366 + __user_pgd(pgd)[pgd_index(VSYSCALL_START)] =
42367 + __pgd(__pa_symbol(level3_user_pgt) | _PAGE_TABLE);
42371 +static inline void pgd_free(pgd_t *pgd)
42373 + pte_t *ptep = virt_to_ptep(pgd);
42375 + if (!pte_write(*ptep)) {
42376 + xen_pgd_unpin(__pa(pgd));
42377 + BUG_ON(HYPERVISOR_update_va_mapping(
42378 + (unsigned long)pgd,
42379 + pfn_pte(virt_to_phys(pgd)>>PAGE_SHIFT, PAGE_KERNEL),
42383 + ptep = virt_to_ptep(__user_pgd(pgd));
42385 + if (!pte_write(*ptep)) {
42386 + xen_pgd_unpin(__pa(__user_pgd(pgd)));
42387 + BUG_ON(HYPERVISOR_update_va_mapping(
42388 + (unsigned long)__user_pgd(pgd),
42389 + pfn_pte(virt_to_phys(__user_pgd(pgd))>>PAGE_SHIFT,
42394 + pgd_list_del(pgd);
42395 + free_pages((unsigned long)pgd, 1);
42398 +static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
42400 + pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
42402 + make_page_readonly(pte, XENFEAT_writable_page_tables);
42407 +/* Should really implement gc for free page table pages. This could be
42408 + done with a reference count in struct page. */
42410 +static inline void pte_free_kernel(pte_t *pte)
42412 + BUG_ON((unsigned long)pte & (PAGE_SIZE-1));
42413 + make_page_writable(pte, XENFEAT_writable_page_tables);
42414 + free_page((unsigned long)pte);
42417 +#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
42418 +#define __pmd_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x))
42419 +#define __pud_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x))
42421 +#endif /* _X86_64_PGALLOC_H */
42422 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/pgtable_64.h
42423 ===================================================================
42424 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
42425 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/pgtable_64.h 2008-07-21 11:00:33.000000000 +0200
42427 +#ifndef _X86_64_PGTABLE_H
42428 +#define _X86_64_PGTABLE_H
42431 + * This file contains the functions and defines necessary to modify and use
42432 + * the x86-64 page table tree.
42434 +#include <asm/processor.h>
42435 +#include <asm/fixmap.h>
42436 +#include <asm/bitops.h>
42437 +#include <linux/threads.h>
42438 +#include <linux/sched.h>
42439 +#include <asm/pda.h>
42441 +#include <asm/hypervisor.h>
42443 +extern pud_t level3_user_pgt[512];
42445 +extern void xen_init_pt(void);
42447 +extern pte_t *lookup_address(unsigned long address);
42449 +#define virt_to_ptep(va) \
42451 + pte_t *__ptep = lookup_address((unsigned long)(va)); \
42452 + BUG_ON(!__ptep || !pte_present(*__ptep)); \
42456 +#define arbitrary_virt_to_machine(va) \
42457 + (((maddr_t)pte_mfn(*virt_to_ptep(va)) << PAGE_SHIFT) \
42458 + | ((unsigned long)(va) & (PAGE_SIZE - 1)))
42461 +extern pud_t level3_kernel_pgt[512];
42462 +extern pud_t level3_physmem_pgt[512];
42463 +extern pud_t level3_ident_pgt[512];
42464 +extern pmd_t level2_kernel_pgt[512];
42465 +extern pgd_t init_level4_pgt[];
42466 +extern pgd_t boot_level4_pgt[];
42467 +extern unsigned long __supported_pte_mask;
42469 +#define swapper_pg_dir init_level4_pgt
42471 +extern int nonx_setup(char *str);
42472 +extern void paging_init(void);
42473 +extern void clear_kernel_mapping(unsigned long addr, unsigned long size);
42475 +extern unsigned long pgkern_mask;
42478 + * ZERO_PAGE is a global shared page that is always zero: used
42479 + * for zero-mapped memory areas etc..
42481 +extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
42482 +#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
42485 + * PGDIR_SHIFT determines what a top-level page table entry can map
42487 +#define PGDIR_SHIFT 39
42488 +#define PTRS_PER_PGD 512
42493 +#define PUD_SHIFT 30
42494 +#define PTRS_PER_PUD 512
42497 + * PMD_SHIFT determines the size of the area a middle-level
42498 + * page table can map
42500 +#define PMD_SHIFT 21
42501 +#define PTRS_PER_PMD 512
42504 + * entries per page directory level
42506 +#define PTRS_PER_PTE 512
42508 +#define pte_ERROR(e) \
42509 + printk("%s:%d: bad pte %p(%016lx pfn %010lx).\n", __FILE__, __LINE__, \
42510 + &(e), __pte_val(e), pte_pfn(e))
42511 +#define pmd_ERROR(e) \
42512 + printk("%s:%d: bad pmd %p(%016lx pfn %010lx).\n", __FILE__, __LINE__, \
42513 + &(e), __pmd_val(e), pmd_pfn(e))
42514 +#define pud_ERROR(e) \
42515 + printk("%s:%d: bad pud %p(%016lx pfn %010lx).\n", __FILE__, __LINE__, \
42516 + &(e), __pud_val(e), (pud_val(e) & __PHYSICAL_MASK) >> PAGE_SHIFT)
42517 +#define pgd_ERROR(e) \
42518 + printk("%s:%d: bad pgd %p(%016lx pfn %010lx).\n", __FILE__, __LINE__, \
42519 + &(e), __pgd_val(e), (pgd_val(e) & __PHYSICAL_MASK) >> PAGE_SHIFT)
42521 +#define pgd_none(x) (!__pgd_val(x))
42522 +#define pud_none(x) (!__pud_val(x))
42524 +static inline void set_pte(pte_t *dst, pte_t val)
42529 +#define set_pmd(pmdptr, pmdval) xen_l2_entry_update(pmdptr, (pmdval))
42530 +#define set_pud(pudptr, pudval) xen_l3_entry_update(pudptr, (pudval))
42531 +#define set_pgd(pgdptr, pgdval) xen_l4_entry_update(pgdptr, (pgdval))
42533 +static inline void pud_clear (pud_t * pud)
42535 + set_pud(pud, __pud(0));
42538 +#define __user_pgd(pgd) ((pgd) + PTRS_PER_PGD)
42540 +static inline void pgd_clear (pgd_t * pgd)
42542 + set_pgd(pgd, __pgd(0));
42543 + set_pgd(__user_pgd(pgd), __pgd(0));
42546 +#define pud_page(pud) \
42547 + ((unsigned long) __va(pud_val(pud) & PHYSICAL_PAGE_MASK))
42549 +#define pte_same(a, b) ((a).pte == (b).pte)
42551 +#define pte_pgprot(a) (__pgprot((a).pte & ~PHYSICAL_PAGE_MASK))
42553 +#define PMD_SIZE (1UL << PMD_SHIFT)
42554 +#define PMD_MASK (~(PMD_SIZE-1))
42555 +#define PUD_SIZE (1UL << PUD_SHIFT)
42556 +#define PUD_MASK (~(PUD_SIZE-1))
42557 +#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
42558 +#define PGDIR_MASK (~(PGDIR_SIZE-1))
42560 +#define USER_PTRS_PER_PGD ((TASK_SIZE-1)/PGDIR_SIZE+1)
42561 +#define FIRST_USER_ADDRESS 0
42563 +#ifndef __ASSEMBLY__
42564 +#define MAXMEM 0x3fffffffffffUL
42565 +#define VMALLOC_START 0xffffc20000000000UL
42566 +#define VMALLOC_END 0xffffe1ffffffffffUL
42567 +#define MODULES_VADDR 0xffffffff88000000UL
42568 +#define MODULES_END 0xfffffffffff00000UL
42569 +#define MODULES_LEN (MODULES_END - MODULES_VADDR)
42571 +#define _PAGE_BIT_PRESENT 0
42572 +#define _PAGE_BIT_RW 1
42573 +#define _PAGE_BIT_USER 2
42574 +#define _PAGE_BIT_PWT 3
42575 +#define _PAGE_BIT_PCD 4
42576 +#define _PAGE_BIT_ACCESSED 5
42577 +#define _PAGE_BIT_DIRTY 6
42578 +#define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */
42579 +#define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
42580 +#define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */
42582 +#define _PAGE_PRESENT 0x001
42583 +#define _PAGE_RW 0x002
42584 +#define _PAGE_USER 0x004
42585 +#define _PAGE_PWT 0x008
42586 +#define _PAGE_PCD 0x010
42587 +#define _PAGE_ACCESSED 0x020
42588 +#define _PAGE_DIRTY 0x040
42589 +#define _PAGE_PSE 0x080 /* 2MB page */
42590 +#define _PAGE_FILE 0x040 /* nonlinear file mapping, saved PTE; unset:swap */
42591 +#define _PAGE_GLOBAL 0x100 /* Global TLB entry */
42593 +#define _PAGE_PROTNONE 0x080 /* If not present */
42594 +#define _PAGE_NX (1UL<<_PAGE_BIT_NX)
42596 +/* Mapped page is I/O or foreign and has no associated page struct. */
42597 +#define _PAGE_IO 0x200
42599 +#if CONFIG_XEN_COMPAT <= 0x030002
42600 +extern unsigned int __kernel_page_user;
42602 +#define __kernel_page_user 0
42605 +#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
42606 +#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY | __kernel_page_user)
42608 +#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_IO)
42610 +#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
42611 +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
42612 +#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
42613 +#define PAGE_COPY_NOEXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
42614 +#define PAGE_COPY PAGE_COPY_NOEXEC
42615 +#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
42616 +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
42617 +#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
42618 +#define __PAGE_KERNEL \
42619 + (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX | __kernel_page_user)
42620 +#define __PAGE_KERNEL_EXEC \
42621 + (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | __kernel_page_user)
42622 +#define __PAGE_KERNEL_NOCACHE \
42623 + (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED | _PAGE_NX | __kernel_page_user)
42624 +#define __PAGE_KERNEL_RO \
42625 + (_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX | __kernel_page_user)
42626 +#define __PAGE_KERNEL_VSYSCALL \
42627 + (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
42628 +#define __PAGE_KERNEL_VSYSCALL_NOCACHE \
42629 + (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PCD)
42630 +#define __PAGE_KERNEL_LARGE \
42631 + (__PAGE_KERNEL | _PAGE_PSE)
42632 +#define __PAGE_KERNEL_LARGE_EXEC \
42633 + (__PAGE_KERNEL_EXEC | _PAGE_PSE)
42636 + * We don't support GLOBAL page in xenolinux64
42638 +#define MAKE_GLOBAL(x) __pgprot((x))
42640 +#define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
42641 +#define PAGE_KERNEL_EXEC MAKE_GLOBAL(__PAGE_KERNEL_EXEC)
42642 +#define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
42643 +#define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
42644 +#define PAGE_KERNEL_VSYSCALL32 __pgprot(__PAGE_KERNEL_VSYSCALL)
42645 +#define PAGE_KERNEL_VSYSCALL MAKE_GLOBAL(__PAGE_KERNEL_VSYSCALL)
42646 +#define PAGE_KERNEL_LARGE MAKE_GLOBAL(__PAGE_KERNEL_LARGE)
42647 +#define PAGE_KERNEL_VSYSCALL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_VSYSCALL_NOCACHE)
42650 +#define __P000 PAGE_NONE
42651 +#define __P001 PAGE_READONLY
42652 +#define __P010 PAGE_COPY
42653 +#define __P011 PAGE_COPY
42654 +#define __P100 PAGE_READONLY_EXEC
42655 +#define __P101 PAGE_READONLY_EXEC
42656 +#define __P110 PAGE_COPY_EXEC
42657 +#define __P111 PAGE_COPY_EXEC
42659 +#define __S000 PAGE_NONE
42660 +#define __S001 PAGE_READONLY
42661 +#define __S010 PAGE_SHARED
42662 +#define __S011 PAGE_SHARED
42663 +#define __S100 PAGE_READONLY_EXEC
42664 +#define __S101 PAGE_READONLY_EXEC
42665 +#define __S110 PAGE_SHARED_EXEC
42666 +#define __S111 PAGE_SHARED_EXEC
42668 +static inline unsigned long pgd_bad(pgd_t pgd)
42670 + unsigned long val = __pgd_val(pgd);
42671 + val &= ~PTE_MASK;
42672 + val &= ~(_PAGE_USER | _PAGE_DIRTY);
42673 + return val & ~(_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED);
42676 +static inline unsigned long pud_bad(pud_t pud)
42678 + unsigned long val = __pud_val(pud);
42679 + val &= ~PTE_MASK;
42680 + val &= ~(_PAGE_USER | _PAGE_DIRTY);
42681 + return val & ~(_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED);
42684 +#define set_pte_at(_mm,addr,ptep,pteval) do { \
42685 + if (((_mm) != current->mm && (_mm) != &init_mm) || \
42686 + HYPERVISOR_update_va_mapping((addr), (pteval), 0)) \
42687 + set_pte((ptep), (pteval)); \
42690 +#define pte_none(x) (!(x).pte)
42691 +#define pte_present(x) ((x).pte & (_PAGE_PRESENT | _PAGE_PROTNONE))
42692 +#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
42694 +#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
42696 +#define __pte_mfn(_pte) (((_pte).pte & PTE_MASK) >> PAGE_SHIFT)
42697 +#define pte_mfn(_pte) ((_pte).pte & _PAGE_PRESENT ? \
42698 + __pte_mfn(_pte) : pfn_to_mfn(__pte_mfn(_pte)))
42699 +#define pte_pfn(_pte) ((_pte).pte & _PAGE_IO ? end_pfn : \
42700 + (_pte).pte & _PAGE_PRESENT ? \
42701 + mfn_to_local_pfn(__pte_mfn(_pte)) : \
42704 +#define pte_page(x) pfn_to_page(pte_pfn(x))
42706 +static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
42708 + unsigned long pte = page_nr << PAGE_SHIFT;
42709 + pte |= pgprot_val(pgprot);
42710 + pte &= __supported_pte_mask;
42711 + return __pte(pte);
42714 +static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
42716 + pte_t pte = *ptep;
42717 + if (!pte_none(pte)) {
42718 + if ((mm != &init_mm) ||
42719 + HYPERVISOR_update_va_mapping(addr, __pte(0), 0))
42720 + pte = __pte_ma(xchg(&ptep->pte, 0));
42725 +static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full)
42728 + pte_t pte = *ptep;
42729 + if (mm->context.pinned)
42730 + xen_l1_entry_update(ptep, __pte(0));
42732 + *ptep = __pte(0);
42735 + return ptep_get_and_clear(mm, addr, ptep);
42738 +#define ptep_clear_flush(vma, addr, ptep) \
42740 + pte_t *__ptep = (ptep); \
42741 + pte_t __res = *__ptep; \
42742 + if (!pte_none(__res) && \
42743 + ((vma)->vm_mm != current->mm || \
42744 + HYPERVISOR_update_va_mapping(addr, __pte(0), \
42745 + (unsigned long)(vma)->vm_mm->cpu_vm_mask.bits| \
42746 + UVMF_INVLPG|UVMF_MULTI))) { \
42747 + __ptep->pte = 0; \
42748 + flush_tlb_page(vma, addr); \
42754 + * The following only work if pte_present() is true.
42755 + * Undefined behaviour if not..
42757 +#define __LARGE_PTE (_PAGE_PSE|_PAGE_PRESENT)
42758 +static inline int pte_user(pte_t pte) { return __pte_val(pte) & _PAGE_USER; }
42759 +static inline int pte_read(pte_t pte) { return __pte_val(pte) & _PAGE_USER; }
42760 +static inline int pte_exec(pte_t pte) { return __pte_val(pte) & _PAGE_USER; }
42761 +static inline int pte_dirty(pte_t pte) { return __pte_val(pte) & _PAGE_DIRTY; }
42762 +static inline int pte_young(pte_t pte) { return __pte_val(pte) & _PAGE_ACCESSED; }
42763 +static inline int pte_write(pte_t pte) { return __pte_val(pte) & _PAGE_RW; }
42764 +static inline int pte_file(pte_t pte) { return __pte_val(pte) & _PAGE_FILE; }
42765 +static inline int pte_huge(pte_t pte) { return __pte_val(pte) & _PAGE_PSE; }
42767 +static inline pte_t pte_rdprotect(pte_t pte) { __pte_val(pte) &= ~_PAGE_USER; return pte; }
42768 +static inline pte_t pte_exprotect(pte_t pte) { __pte_val(pte) &= ~_PAGE_USER; return pte; }
42769 +static inline pte_t pte_mkclean(pte_t pte) { __pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
42770 +static inline pte_t pte_mkold(pte_t pte) { __pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
42771 +static inline pte_t pte_wrprotect(pte_t pte) { __pte_val(pte) &= ~_PAGE_RW; return pte; }
42772 +static inline pte_t pte_mkread(pte_t pte) { __pte_val(pte) |= _PAGE_USER; return pte; }
42773 +static inline pte_t pte_mkexec(pte_t pte) { __pte_val(pte) |= _PAGE_USER; return pte; }
42774 +static inline pte_t pte_mkdirty(pte_t pte) { __pte_val(pte) |= _PAGE_DIRTY; return pte; }
42775 +static inline pte_t pte_mkyoung(pte_t pte) { __pte_val(pte) |= _PAGE_ACCESSED; return pte; }
42776 +static inline pte_t pte_mkwrite(pte_t pte) { __pte_val(pte) |= _PAGE_RW; return pte; }
42777 +static inline pte_t pte_mkhuge(pte_t pte) { __pte_val(pte) |= _PAGE_PSE; return pte; }
42779 +#define ptep_test_and_clear_dirty(vma, addr, ptep) \
42781 + pte_t __pte = *(ptep); \
42782 + int __ret = pte_dirty(__pte); \
42784 + set_pte_at((vma)->vm_mm, addr, ptep, pte_mkclean(__pte)); \
42788 +#define ptep_test_and_clear_young(vma, addr, ptep) \
42790 + pte_t __pte = *(ptep); \
42791 + int __ret = pte_young(__pte); \
42793 + set_pte_at((vma)->vm_mm, addr, ptep, pte_mkold(__pte)); \
42797 +static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
42799 + pte_t pte = *ptep;
42800 + if (pte_write(pte))
42801 + set_pte_at(mm, addr, ptep, pte_wrprotect(pte));
42805 + * Macro to mark a page protection value as "uncacheable".
42807 +#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT))
42809 +static inline int pmd_large(pmd_t pte) {
42810 + return (__pmd_val(pte) & __LARGE_PTE) == __LARGE_PTE;
42815 + * Conversion functions: convert a page and protection to a page entry,
42816 + * and a page entry and page directory to the page they refer to.
42820 + * Level 4 access.
42821 + * Never use these in the common code.
42823 +#define pgd_page(pgd) ((unsigned long) __va(pgd_val(pgd) & PTE_MASK))
42824 +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
42825 +#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
42826 +#define pgd_offset_k(address) (init_level4_pgt + pgd_index(address))
42827 +#define pgd_present(pgd) (__pgd_val(pgd) & _PAGE_PRESENT)
42828 +#define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE)
42830 +/* PUD - Level3 access */
42831 +/* to find an entry in a page-table-directory. */
42832 +#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
42833 +#define pud_offset(pgd, address) ((pud_t *) pgd_page(*(pgd)) + pud_index(address))
42834 +#define pud_present(pud) (__pud_val(pud) & _PAGE_PRESENT)
42836 +/* PMD - Level 2 access */
42837 +#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PTE_MASK))
42838 +#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
42840 +#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
42841 +#define pmd_offset(dir, address) ((pmd_t *) pud_page(*(dir)) + \
42842 + pmd_index(address))
42843 +#define pmd_none(x) (!__pmd_val(x))
42844 +#if CONFIG_XEN_COMPAT <= 0x030002
42845 +/* pmd_present doesn't just test the _PAGE_PRESENT bit since wr.p.t.
42846 + can temporarily clear it. */
42847 +#define pmd_present(x) (__pmd_val(x))
42849 +#define pmd_present(x) (__pmd_val(x) & _PAGE_PRESENT)
42851 +#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
42852 +#define pmd_bad(x) ((__pmd_val(x) & ~(PTE_MASK | _PAGE_USER | _PAGE_PRESENT)) \
42853 + != (_KERNPG_TABLE & ~(_PAGE_USER | _PAGE_PRESENT)))
42854 +#define pfn_pmd(nr,prot) (__pmd(((nr) << PAGE_SHIFT) | pgprot_val(prot)))
42855 +#define pmd_pfn(x) ((pmd_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT)
42857 +#define pte_to_pgoff(pte) ((__pte_val(pte) & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT)
42858 +#define pgoff_to_pte(off) ((pte_t) { ((off) << PAGE_SHIFT) | _PAGE_FILE })
42859 +#define PTE_FILE_MAX_BITS __PHYSICAL_MASK_SHIFT
42861 +/* PTE - Level 1 access. */
42863 +/* page, protection -> pte */
42864 +#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
42865 +#define mk_pte_huge(entry) (__pte_val(entry) |= _PAGE_PRESENT | _PAGE_PSE)
42867 +/* physical address -> PTE */
42868 +static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
42870 + unsigned long pteval;
42871 + pteval = physpage | pgprot_val(pgprot);
42872 + return __pte(pteval);
42875 +/* Change flags of a PTE */
42876 +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
42879 + * Since this might change the present bit (which controls whether
42880 + * a pte_t object has undergone p2m translation), we must use
42881 + * pte_val() on the input pte and __pte() for the return value.
42883 + unsigned long pteval = pte_val(pte);
42885 + pteval &= _PAGE_CHG_MASK;
42886 + pteval |= pgprot_val(newprot);
42887 + pteval &= __supported_pte_mask;
42888 + return __pte(pteval);
42891 +#define pte_index(address) \
42892 + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
42893 +#define pte_offset_kernel(dir, address) ((pte_t *) pmd_page_kernel(*(dir)) + \
42894 + pte_index(address))
42896 +/* x86-64 always has all page tables mapped. */
42897 +#define pte_offset_map(dir,address) pte_offset_kernel(dir,address)
42898 +#define pte_offset_map_nested(dir,address) pte_offset_kernel(dir,address)
42899 +#define pte_unmap(pte) /* NOP */
42900 +#define pte_unmap_nested(pte) /* NOP */
42902 +#define update_mmu_cache(vma,address,pte) do { } while (0)
42905 + * Rules for using ptep_establish: the pte MUST be a user pte, and
42906 + * must be a present->present transition.
42908 +#define __HAVE_ARCH_PTEP_ESTABLISH
42909 +#define ptep_establish(vma, address, ptep, pteval) \
42911 + if ( likely((vma)->vm_mm == current->mm) ) { \
42912 + BUG_ON(HYPERVISOR_update_va_mapping(address, \
42914 + (unsigned long)(vma)->vm_mm->cpu_vm_mask.bits| \
42915 + UVMF_INVLPG|UVMF_MULTI)); \
42917 + xen_l1_entry_update(ptep, pteval); \
42918 + flush_tlb_page(vma, address); \
42922 +/* We only update the dirty/accessed state if we set
42923 + * the dirty bit by hand in the kernel, since the hardware
42924 + * will do the accessed bit for us, and we don't want to
42925 + * race with other CPU's that might be updating the dirty
42926 + * bit at the same time. */
42927 +#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
42928 +#define ptep_set_access_flags(vma, address, ptep, entry, dirty) \
42931 + ptep_establish(vma, address, ptep, entry); \
42934 +/* Encode and de-code a swap entry */
42935 +#define __swp_type(x) (((x).val >> 1) & 0x3f)
42936 +#define __swp_offset(x) ((x).val >> 8)
42937 +#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
42938 +#define __pte_to_swp_entry(pte) ((swp_entry_t) { __pte_val(pte) })
42939 +#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
42941 +extern spinlock_t pgd_lock;
42942 +extern struct page *pgd_list;
42943 +void vmalloc_sync_all(void);
42945 +#endif /* !__ASSEMBLY__ */
42947 +extern int kern_addr_valid(unsigned long addr);
42949 +#define DOMID_LOCAL (0xFFFFU)
42951 +struct vm_area_struct;
42953 +int direct_remap_pfn_range(struct vm_area_struct *vma,
42954 + unsigned long address,
42955 + unsigned long mfn,
42956 + unsigned long size,
42960 +int direct_kernel_remap_pfn_range(unsigned long address,
42961 + unsigned long mfn,
42962 + unsigned long size,
42966 +int create_lookup_pte_addr(struct mm_struct *mm,
42967 + unsigned long address,
42970 +int touch_pte_range(struct mm_struct *mm,
42971 + unsigned long address,
42972 + unsigned long size);
42974 +int xen_change_pte_range(struct mm_struct *mm, pmd_t *pmd,
42975 + unsigned long addr, unsigned long end, pgprot_t newprot);
42977 +#define arch_change_pte_range(mm, pmd, addr, end, newprot) \
42978 + xen_change_pte_range(mm, pmd, addr, end, newprot)
42980 +#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
42981 + direct_remap_pfn_range(vma,vaddr,pfn,size,prot,DOMID_IO)
42983 +#define MK_IOSPACE_PFN(space, pfn) (pfn)
42984 +#define GET_IOSPACE(pfn) 0
42985 +#define GET_PFN(pfn) (pfn)
42987 +#define HAVE_ARCH_UNMAPPED_AREA
42989 +#define pgtable_cache_init() do { } while (0)
42990 +#define check_pgt_cache() do { } while (0)
42992 +#define PAGE_AGP PAGE_KERNEL_NOCACHE
42993 +#define HAVE_PAGE_AGP 1
42995 +/* fs/proc/kcore.c */
42996 +#define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
42997 +#define kc_offset_to_vaddr(o) \
42998 + (((o) & (1UL << (__VIRTUAL_MASK_SHIFT-1))) ? ((o) | (~__VIRTUAL_MASK)) : (o))
43000 +#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
43001 +#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
43002 +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
43003 +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
43004 +#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
43005 +#define __HAVE_ARCH_PTEP_SET_WRPROTECT
43006 +#define __HAVE_ARCH_PTE_SAME
43007 +#include <asm-generic/pgtable.h>
43009 +#endif /* _X86_64_PGTABLE_H */
43010 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/processor_64.h
43011 ===================================================================
43012 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
43013 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/processor_64.h 2008-03-06 08:54:32.000000000 +0100
43016 + * include/asm-x86_64/processor.h
43018 + * Copyright (C) 1994 Linus Torvalds
43021 +#ifndef __ASM_X86_64_PROCESSOR_H
43022 +#define __ASM_X86_64_PROCESSOR_H
43024 +#include <asm/segment.h>
43025 +#include <asm/page.h>
43026 +#include <asm/types.h>
43027 +#include <asm/sigcontext.h>
43028 +#include <asm/cpufeature.h>
43029 +#include <linux/threads.h>
43030 +#include <asm/msr.h>
43031 +#include <asm/current.h>
43032 +#include <asm/system.h>
43033 +#include <asm/mmsegment.h>
43034 +#include <asm/percpu.h>
43035 +#include <linux/personality.h>
43036 +#include <linux/cpumask.h>
43038 +#define TF_MASK 0x00000100
43039 +#define IF_MASK 0x00000200
43040 +#define IOPL_MASK 0x00003000
43041 +#define NT_MASK 0x00004000
43042 +#define VM_MASK 0x00020000
43043 +#define AC_MASK 0x00040000
43044 +#define VIF_MASK 0x00080000 /* virtual interrupt flag */
43045 +#define VIP_MASK 0x00100000 /* virtual interrupt pending */
43046 +#define ID_MASK 0x00200000
43048 +#define desc_empty(desc) \
43049 + (!((desc)->a | (desc)->b))
43051 +#define desc_equal(desc1, desc2) \
43052 + (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
43055 + * Default implementation of macro that returns current
43056 + * instruction pointer ("program counter").
43058 +#define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
43061 + * CPU type and hardware bug flags. Kept separately for each CPU.
43064 +struct cpuinfo_x86 {
43065 + __u8 x86; /* CPU family */
43066 + __u8 x86_vendor; /* CPU vendor */
43069 + int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
43070 + __u32 x86_capability[NCAPINTS];
43071 + char x86_vendor_id[16];
43072 + char x86_model_id[64];
43073 + int x86_cache_size; /* in KB */
43074 + int x86_clflush_size;
43075 + int x86_cache_alignment;
43076 + int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
43077 + __u8 x86_virt_bits, x86_phys_bits;
43078 + __u8 x86_max_cores; /* cpuid returned max cores value */
43080 + __u32 extended_cpuid_level; /* Max extended CPUID function supported */
43081 + unsigned long loops_per_jiffy;
43083 + cpumask_t llc_shared_map; /* cpus sharing the last level cache */
43087 + __u8 booted_cores; /* number of cores as seen by OS */
43088 + __u8 phys_proc_id; /* Physical Processor id. */
43089 + __u8 cpu_core_id; /* Core id. */
43091 +} ____cacheline_aligned;
43093 +#define X86_VENDOR_INTEL 0
43094 +#define X86_VENDOR_CYRIX 1
43095 +#define X86_VENDOR_AMD 2
43096 +#define X86_VENDOR_UMC 3
43097 +#define X86_VENDOR_NEXGEN 4
43098 +#define X86_VENDOR_CENTAUR 5
43099 +#define X86_VENDOR_RISE 6
43100 +#define X86_VENDOR_TRANSMETA 7
43101 +#define X86_VENDOR_NUM 8
43102 +#define X86_VENDOR_UNKNOWN 0xff
43105 +extern struct cpuinfo_x86 cpu_data[];
43106 +#define current_cpu_data cpu_data[smp_processor_id()]
43108 +#define cpu_data (&boot_cpu_data)
43109 +#define current_cpu_data boot_cpu_data
43112 +extern char ignore_irq13;
43114 +extern void identify_cpu(struct cpuinfo_x86 *);
43115 +extern void print_cpu_info(struct cpuinfo_x86 *);
43116 +extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
43117 +extern unsigned short num_cache_leaves;
43122 +#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
43123 +#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
43124 +#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
43125 +#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
43126 +#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
43127 +#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
43128 +#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
43129 +#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
43130 +#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
43131 +#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
43132 +#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
43133 +#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
43134 +#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
43135 +#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
43136 +#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
43137 +#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
43138 +#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
43141 + * Intel CPU features in CR4
43143 +#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
43144 +#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
43145 +#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
43146 +#define X86_CR4_DE 0x0008 /* enable debugging extensions */
43147 +#define X86_CR4_PSE 0x0010 /* enable page size extensions */
43148 +#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
43149 +#define X86_CR4_MCE 0x0040 /* Machine check enable */
43150 +#define X86_CR4_PGE 0x0080 /* enable global pages */
43151 +#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
43152 +#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
43153 +#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
43156 + * Save the cr4 feature set we're using (ie
43157 + * Pentium 4MB enable and PPro Global page
43158 + * enable), so that any CPU's that boot up
43159 + * after us can get the correct flags.
43161 +extern unsigned long mmu_cr4_features;
43163 +static inline void set_in_cr4 (unsigned long mask)
43165 + mmu_cr4_features |= mask;
43166 + __asm__("movq %%cr4,%%rax\n\t"
43167 + "orq %0,%%rax\n\t"
43168 + "movq %%rax,%%cr4\n"
43173 +static inline void clear_in_cr4 (unsigned long mask)
43175 + mmu_cr4_features &= ~mask;
43176 + __asm__("movq %%cr4,%%rax\n\t"
43177 + "andq %0,%%rax\n\t"
43178 + "movq %%rax,%%cr4\n"
43179 + : : "irg" (~mask)
43185 + * User space process size. 47bits minus one guard page.
43187 +#define TASK_SIZE64 (0x800000000000UL - 4096)
43189 +/* This decides where the kernel will search for a free chunk of vm
43190 + * space during mmap's.
43192 +#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
43194 +#define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
43195 +#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
43197 +#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
43200 + * Size of io_bitmap.
43202 +#define IO_BITMAP_BITS 65536
43203 +#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
43204 +#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
43205 +#ifndef CONFIG_X86_NO_TSS
43206 +#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
43208 +#define INVALID_IO_BITMAP_OFFSET 0x8000
43210 +struct i387_fxsave_struct {
43219 + u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
43220 + u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 128 bytes */
43222 +} __attribute__ ((aligned (16)));
43224 +union i387_union {
43225 + struct i387_fxsave_struct fxsave;
43228 +#ifndef CONFIG_X86_NO_TSS
43229 +struct tss_struct {
43239 + u16 io_bitmap_base;
43241 + * The extra 1 is there because the CPU will access an
43242 + * additional byte beyond the end of the IO permission
43243 + * bitmap. The extra byte must be all 1 bits, and must
43244 + * be within the limit. Thus we have:
43246 + * 128 bytes, the bitmap itself, for ports 0..0x3ff
43247 + * 8 bytes, for an extra "long" of ~0UL
43249 + unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
43250 +} __attribute__((packed)) ____cacheline_aligned;
43252 +DECLARE_PER_CPU(struct tss_struct,init_tss);
43256 +extern struct cpuinfo_x86 boot_cpu_data;
43257 +#ifndef CONFIG_X86_NO_TSS
43258 +/* Save the original ist values for checking stack pointers during debugging */
43260 + unsigned long ist[7];
43262 +DECLARE_PER_CPU(struct orig_ist, orig_ist);
43265 +#ifdef CONFIG_X86_VSMP
43266 +#define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
43267 +#define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
43269 +#define ARCH_MIN_TASKALIGN 16
43270 +#define ARCH_MIN_MMSTRUCT_ALIGN 0
43273 +struct thread_struct {
43274 + unsigned long rsp0;
43275 + unsigned long rsp;
43276 + unsigned long userrsp; /* Copy from PDA */
43277 + unsigned long fs;
43278 + unsigned long gs;
43279 + unsigned short es, ds, fsindex, gsindex;
43280 +/* Hardware debugging registers */
43281 + unsigned long debugreg0;
43282 + unsigned long debugreg1;
43283 + unsigned long debugreg2;
43284 + unsigned long debugreg3;
43285 + unsigned long debugreg6;
43286 + unsigned long debugreg7;
43288 + unsigned long cr2, trap_no, error_code;
43289 +/* floating point info */
43290 + union i387_union i387 __attribute__((aligned(16)));
43291 +/* IO permissions. the bitmap could be moved into the GDT, that would make
43292 + switch faster for a limited number of ioperm using tasks. -AK */
43294 + unsigned long *io_bitmap_ptr;
43295 + unsigned io_bitmap_max;
43296 +/* cached TLS descriptors. */
43297 + u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
43298 + unsigned int iopl;
43299 +} __attribute__((aligned(16)));
43301 +#define INIT_THREAD { \
43302 + .rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
43305 +#ifndef CONFIG_X86_NO_TSS
43306 +#define INIT_TSS { \
43307 + .rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
43311 +#define INIT_MMAP \
43312 +{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
43314 +#define start_thread(regs,new_rip,new_rsp) do { \
43315 + asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
43316 + load_gs_index(0); \
43317 + (regs)->rip = (new_rip); \
43318 + (regs)->rsp = (new_rsp); \
43319 + write_pda(oldrsp, (new_rsp)); \
43320 + (regs)->cs = __USER_CS; \
43321 + (regs)->ss = __USER_DS; \
43322 + (regs)->eflags = 0x200; \
43323 + set_fs(USER_DS); \
43326 +#define get_debugreg(var, register) \
43327 + var = HYPERVISOR_get_debugreg(register)
43328 +#define set_debugreg(value, register) do { \
43329 + if (HYPERVISOR_set_debugreg(register, value)) \
43333 +struct task_struct;
43336 +/* Free all resources held by a thread. */
43337 +extern void release_thread(struct task_struct *);
43339 +/* Prepare to copy thread state - unlazy all lazy status */
43340 +extern void prepare_to_copy(struct task_struct *tsk);
43343 + * create a kernel thread without removing it from tasklists
43345 +extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
43348 + * Return saved PC of a blocked thread.
43349 + * What is this good for? it will be always the scheduler or ret_from_fork.
43351 +#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.rsp - 8))
43353 +extern unsigned long get_wchan(struct task_struct *p);
43354 +#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.rsp0 - 1)
43355 +#define KSTK_EIP(tsk) (task_pt_regs(tsk)->rip)
43356 +#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
43359 +struct microcode_header {
43360 + unsigned int hdrver;
43361 + unsigned int rev;
43362 + unsigned int date;
43363 + unsigned int sig;
43364 + unsigned int cksum;
43365 + unsigned int ldrver;
43367 + unsigned int datasize;
43368 + unsigned int totalsize;
43369 + unsigned int reserved[3];
43372 +struct microcode {
43373 + struct microcode_header hdr;
43374 + unsigned int bits[0];
43377 +typedef struct microcode microcode_t;
43378 +typedef struct microcode_header microcode_header_t;
43380 +/* microcode format is extended from prescott processors */
43381 +struct extended_signature {
43382 + unsigned int sig;
43384 + unsigned int cksum;
43387 +struct extended_sigtable {
43388 + unsigned int count;
43389 + unsigned int cksum;
43390 + unsigned int reserved[3];
43391 + struct extended_signature sigs[0];
43395 +#define ASM_NOP1 K8_NOP1
43396 +#define ASM_NOP2 K8_NOP2
43397 +#define ASM_NOP3 K8_NOP3
43398 +#define ASM_NOP4 K8_NOP4
43399 +#define ASM_NOP5 K8_NOP5
43400 +#define ASM_NOP6 K8_NOP6
43401 +#define ASM_NOP7 K8_NOP7
43402 +#define ASM_NOP8 K8_NOP8
43404 +/* Opteron nops */
43405 +#define K8_NOP1 ".byte 0x90\n"
43406 +#define K8_NOP2 ".byte 0x66,0x90\n"
43407 +#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
43408 +#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
43409 +#define K8_NOP5 K8_NOP3 K8_NOP2
43410 +#define K8_NOP6 K8_NOP3 K8_NOP3
43411 +#define K8_NOP7 K8_NOP4 K8_NOP3
43412 +#define K8_NOP8 K8_NOP4 K8_NOP4
43414 +#define ASM_NOP_MAX 8
43416 +/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
43417 +static inline void rep_nop(void)
43419 + __asm__ __volatile__("rep;nop": : :"memory");
43422 +/* Stop speculative execution */
43423 +static inline void sync_core(void)
43426 + asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
43429 +#define cpu_has_fpu 1
43431 +#define ARCH_HAS_PREFETCH
43432 +static inline void prefetch(void *x)
43434 + asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
43437 +#define ARCH_HAS_PREFETCHW 1
43438 +static inline void prefetchw(void *x)
43440 + alternative_input("prefetcht0 (%1)",
43441 + "prefetchw (%1)",
43442 + X86_FEATURE_3DNOW,
43446 +#define ARCH_HAS_SPINLOCK_PREFETCH 1
43448 +#define spin_lock_prefetch(x) prefetchw(x)
43450 +#define cpu_relax() rep_nop()
43453 + * NSC/Cyrix CPU configuration register indexes
43455 +#define CX86_CCR0 0xc0
43456 +#define CX86_CCR1 0xc1
43457 +#define CX86_CCR2 0xc2
43458 +#define CX86_CCR3 0xc3
43459 +#define CX86_CCR4 0xe8
43460 +#define CX86_CCR5 0xe9
43461 +#define CX86_CCR6 0xea
43462 +#define CX86_CCR7 0xeb
43463 +#define CX86_DIR0 0xfe
43464 +#define CX86_DIR1 0xff
43465 +#define CX86_ARR_BASE 0xc4
43466 +#define CX86_RCR_BASE 0xdc
43469 + * NSC/Cyrix CPU indexed register access macros
43472 +#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
43474 +#define setCx86(reg, data) do { \
43475 + outb((reg), 0x22); \
43476 + outb((data), 0x23); \
43479 +static inline void serialize_cpu(void)
43481 + __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
43484 +static inline void __monitor(const void *eax, unsigned long ecx,
43485 + unsigned long edx)
43487 + /* "monitor %eax,%ecx,%edx;" */
43489 + ".byte 0x0f,0x01,0xc8;"
43490 + : :"a" (eax), "c" (ecx), "d"(edx));
43493 +static inline void __mwait(unsigned long eax, unsigned long ecx)
43495 + /* "mwait %eax,%ecx;" */
43497 + ".byte 0x0f,0x01,0xc9;"
43498 + : :"a" (eax), "c" (ecx));
43501 +#define stack_current() \
43503 + struct thread_info *ti; \
43504 + asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
43508 +#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
43510 +extern unsigned long boot_option_idle_override;
43511 +/* Boot loader type from the setup header */
43512 +extern int bootloader_type;
43514 +#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
43516 +#endif /* __ASM_X86_64_PROCESSOR_H */
43517 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/smp_64.h
43518 ===================================================================
43519 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
43520 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/smp_64.h 2007-06-12 13:14:13.000000000 +0200
43522 +#ifndef __ASM_SMP_H
43523 +#define __ASM_SMP_H
43526 + * We need the APIC definitions automatically as part of 'smp.h'
43528 +#ifndef __ASSEMBLY__
43529 +#include <linux/threads.h>
43530 +#include <linux/cpumask.h>
43531 +#include <linux/bitops.h>
43532 +extern int disable_apic;
43535 +#ifdef CONFIG_X86_LOCAL_APIC
43536 +#ifndef __ASSEMBLY__
43537 +#include <asm/fixmap.h>
43538 +#include <asm/mpspec.h>
43539 +#ifdef CONFIG_X86_IO_APIC
43540 +#include <asm/io_apic.h>
43542 +#include <asm/apic.h>
43543 +#include <asm/thread_info.h>
43550 +#include <asm/pda.h>
43554 +extern cpumask_t cpu_present_mask;
43555 +extern cpumask_t cpu_possible_map;
43556 +extern cpumask_t cpu_online_map;
43557 +extern cpumask_t cpu_initialized;
43560 + * Private routines/data
43563 +extern void smp_alloc_memory(void);
43564 +extern volatile unsigned long smp_invalidate_needed;
43565 +extern int pic_mode;
43566 +extern void lock_ipi_call_lock(void);
43567 +extern void unlock_ipi_call_lock(void);
43568 +extern int smp_num_siblings;
43569 +extern void smp_send_reschedule(int cpu);
43570 +void smp_stop_cpu(void);
43571 +extern int smp_call_function_single(int cpuid, void (*func) (void *info),
43572 + void *info, int retry, int wait);
43574 +extern cpumask_t cpu_sibling_map[NR_CPUS];
43575 +extern cpumask_t cpu_core_map[NR_CPUS];
43576 +extern u8 cpu_llc_id[NR_CPUS];
43578 +#define SMP_TRAMPOLINE_BASE 0x6000
43581 + * On x86 all CPUs are mapped 1:1 to the APIC space.
43582 + * This simplifies scheduling and IPI sending and
43583 + * compresses data structures.
43586 +static inline int num_booting_cpus(void)
43588 + return cpus_weight(cpu_possible_map);
43591 +#define raw_smp_processor_id() read_pda(cpunumber)
43593 +#ifdef CONFIG_X86_LOCAL_APIC
43594 +static inline int hard_smp_processor_id(void)
43596 + /* we don't want to mark this access volatile - bad code generation */
43597 + return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID));
43601 +extern int safe_smp_processor_id(void);
43602 +extern int __cpu_disable(void);
43603 +extern void __cpu_die(unsigned int cpu);
43604 +extern void prefill_possible_map(void);
43605 +extern unsigned num_processors;
43606 +extern unsigned disabled_cpus;
43608 +#endif /* !ASSEMBLY */
43610 +#define NO_PROC_ID 0xFF /* No processor magic marker */
43616 + * Some lowlevel functions might want to know about
43617 + * the real APIC ID <-> CPU # mapping.
43619 +extern u8 x86_cpu_to_apicid[NR_CPUS]; /* physical ID */
43620 +extern u8 x86_cpu_to_log_apicid[NR_CPUS];
43621 +extern u8 bios_cpu_apicid[];
43623 +#ifdef CONFIG_X86_LOCAL_APIC
43624 +static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
43626 + return cpus_addr(cpumask)[0];
43629 +static inline int cpu_present_to_apicid(int mps_cpu)
43631 + if (mps_cpu < NR_CPUS)
43632 + return (int)bios_cpu_apicid[mps_cpu];
43634 + return BAD_APICID;
43638 +#endif /* !ASSEMBLY */
43640 +#ifndef CONFIG_SMP
43641 +#define stack_smp_processor_id() 0
43642 +#define safe_smp_processor_id() 0
43643 +#define cpu_logical_map(x) (x)
43645 +#include <asm/thread_info.h>
43646 +#define stack_smp_processor_id() \
43648 + struct thread_info *ti; \
43649 + __asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
43654 +#ifndef __ASSEMBLY__
43655 +#ifdef CONFIG_X86_LOCAL_APIC
43656 +static __inline int logical_smp_processor_id(void)
43658 + /* we don't want to mark this access volatile - bad code generation */
43659 + return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
43665 +#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu]
43667 +#define cpu_physical_id(cpu) boot_cpu_id
43672 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/system_64.h
43673 ===================================================================
43674 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
43675 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/system_64.h 2007-11-26 16:59:25.000000000 +0100
43677 +#ifndef __ASM_SYSTEM_H
43678 +#define __ASM_SYSTEM_H
43680 +#include <linux/kernel.h>
43681 +#include <asm/segment.h>
43682 +#include <asm/alternative.h>
43684 +#include <asm/synch_bitops.h>
43685 +#include <asm/hypervisor.h>
43686 +#include <xen/interface/arch-x86_64.h>
43690 +#define __STR(x) #x
43691 +#define STR(x) __STR(x)
43693 +#define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
43694 +#define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
43696 +/* frame pointer must be last for get_wchan */
43697 +#define SAVE_CONTEXT "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
43698 +#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\n\t"
43700 +#define __EXTRA_CLOBBER \
43701 + ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
43703 +#define switch_to(prev,next,last) \
43704 + asm volatile(SAVE_CONTEXT \
43705 + "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
43706 + "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
43707 + "call __switch_to\n\t" \
43708 + ".globl thread_return\n" \
43709 + "thread_return:\n\t" \
43710 + "movq %%gs:%P[pda_pcurrent],%%rsi\n\t" \
43711 + "movq %P[thread_info](%%rsi),%%r8\n\t" \
43712 + LOCK_PREFIX "btr %[tif_fork],%P[ti_flags](%%r8)\n\t" \
43713 + "movq %%rax,%%rdi\n\t" \
43714 + "jc ret_from_fork\n\t" \
43715 + RESTORE_CONTEXT \
43717 + : [next] "S" (next), [prev] "D" (prev), \
43718 + [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
43719 + [ti_flags] "i" (offsetof(struct thread_info, flags)),\
43720 + [tif_fork] "i" (TIF_FORK), \
43721 + [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
43722 + [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
43723 + : "memory", "cc" __EXTRA_CLOBBER)
43725 +extern void load_gs_index(unsigned);
43728 + * Load a segment. Fall back on loading the zero
43729 + * segment if something goes wrong..
43731 +#define loadsegment(seg,value) \
43732 + asm volatile("\n" \
43734 + "movl %k0,%%" #seg "\n" \
43736 + ".section .fixup,\"ax\"\n" \
43738 + "movl %1,%%" #seg "\n\t" \
43741 + ".section __ex_table,\"a\"\n\t" \
43743 + ".quad 1b,3b\n" \
43745 + : :"r" (value), "r" (0))
43748 + * Clear and set 'TS' bit respectively
43750 +#define clts() (HYPERVISOR_fpu_taskswitch(0))
43752 +static inline unsigned long read_cr0(void)
43754 + unsigned long cr0;
43755 + asm volatile("movq %%cr0,%0" : "=r" (cr0));
43759 +static inline void write_cr0(unsigned long val)
43761 + asm volatile("movq %0,%%cr0" :: "r" (val));
43764 +#define read_cr3() ({ \
43765 + unsigned long __dummy; \
43766 + asm("movq %%cr3,%0" : "=r" (__dummy)); \
43767 + machine_to_phys(__dummy); \
43770 +static inline unsigned long read_cr4(void)
43772 + unsigned long cr4;
43773 + asm("movq %%cr4,%0" : "=r" (cr4));
43777 +static inline void write_cr4(unsigned long val)
43779 + asm volatile("movq %0,%%cr4" :: "r" (val));
43782 +#define stts() (HYPERVISOR_fpu_taskswitch(1))
43784 +#define wbinvd() \
43785 + __asm__ __volatile__ ("wbinvd": : :"memory");
43788 + * On SMP systems, when the scheduler does migration-cost autodetection,
43789 + * it needs a way to flush as much of the CPU's caches as possible.
43791 +static inline void sched_cacheflush(void)
43796 +#endif /* __KERNEL__ */
43798 +#define nop() __asm__ __volatile__ ("nop")
43800 +#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
43802 +#define tas(ptr) (xchg((ptr),1))
43804 +#define __xg(x) ((volatile long *)(x))
43806 +static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
43811 +#define _set_64bit set_64bit
43814 + * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
43815 + * Note 2: xchg has side effect, so that attribute volatile is necessary,
43816 + * but generally the primitive is invalid, *ptr is output argument. --ANK
43818 +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
43822 + __asm__ __volatile__("xchgb %b0,%1"
43824 + :"m" (*__xg(ptr)), "0" (x)
43828 + __asm__ __volatile__("xchgw %w0,%1"
43830 + :"m" (*__xg(ptr)), "0" (x)
43834 + __asm__ __volatile__("xchgl %k0,%1"
43836 + :"m" (*__xg(ptr)), "0" (x)
43840 + __asm__ __volatile__("xchgq %0,%1"
43842 + :"m" (*__xg(ptr)), "0" (x)
43850 + * Atomic compare and exchange. Compare OLD with MEM, if identical,
43851 + * store NEW in MEM. Return the initial value in MEM. Success is
43852 + * indicated by comparing RETURN with OLD.
43855 +#define __HAVE_ARCH_CMPXCHG 1
43857 +static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
43858 + unsigned long new, int size)
43860 + unsigned long prev;
43863 + __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
43865 + : "q"(new), "m"(*__xg(ptr)), "0"(old)
43869 + __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
43871 + : "r"(new), "m"(*__xg(ptr)), "0"(old)
43875 + __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
43877 + : "r"(new), "m"(*__xg(ptr)), "0"(old)
43881 + __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
43883 + : "r"(new), "m"(*__xg(ptr)), "0"(old)
43890 +#define cmpxchg(ptr,o,n)\
43891 + ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
43892 + (unsigned long)(n),sizeof(*(ptr))))
43895 +#define smp_mb() mb()
43896 +#define smp_rmb() rmb()
43897 +#define smp_wmb() wmb()
43898 +#define smp_read_barrier_depends() do {} while(0)
43900 +#define smp_mb() barrier()
43901 +#define smp_rmb() barrier()
43902 +#define smp_wmb() barrier()
43903 +#define smp_read_barrier_depends() do {} while(0)
43908 + * Force strict CPU ordering.
43909 + * And yes, this is required on UP too when we're talking
43912 +#define mb() asm volatile("mfence":::"memory")
43913 +#define rmb() asm volatile("lfence":::"memory")
43915 +#ifdef CONFIG_UNORDERED_IO
43916 +#define wmb() asm volatile("sfence" ::: "memory")
43918 +#define wmb() asm volatile("" ::: "memory")
43920 +#define read_barrier_depends() do {} while(0)
43921 +#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
43923 +#define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
43925 +#include <linux/irqflags.h>
43927 +void cpu_idle_wait(void);
43929 +extern unsigned long arch_align_stack(unsigned long sp);
43930 +extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
43933 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/tlbflush_64.h
43934 ===================================================================
43935 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
43936 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/tlbflush_64.h 2007-11-26 16:59:25.000000000 +0100
43938 +#ifndef _X8664_TLBFLUSH_H
43939 +#define _X8664_TLBFLUSH_H
43941 +#include <linux/mm.h>
43942 +#include <asm/processor.h>
43944 +#define __flush_tlb() xen_tlb_flush()
43947 + * Global pages have to be flushed a bit differently. Not a real
43948 + * performance problem because this does not happen often.
43950 +#define __flush_tlb_global() xen_tlb_flush()
43953 +extern unsigned long pgkern_mask;
43955 +#define __flush_tlb_all() __flush_tlb_global()
43957 +#define __flush_tlb_one(addr) xen_invlpg((unsigned long)addr)
43963 + * - flush_tlb() flushes the current mm struct TLBs
43964 + * - flush_tlb_all() flushes all processes TLBs
43965 + * - flush_tlb_mm(mm) flushes the specified mm context TLB's
43966 + * - flush_tlb_page(vma, vmaddr) flushes one page
43967 + * - flush_tlb_range(vma, start, end) flushes a range of pages
43968 + * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
43969 + * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
43971 + * x86-64 can only flush individual pages or full VMs. For a range flush
43972 + * we always do the full VM. Might be worth trying if for a small
43973 + * range a few INVLPGs in a row are a win.
43976 +#ifndef CONFIG_SMP
43978 +#define flush_tlb() __flush_tlb()
43979 +#define flush_tlb_all() __flush_tlb_all()
43980 +#define local_flush_tlb() __flush_tlb()
43982 +static inline void flush_tlb_mm(struct mm_struct *mm)
43984 + if (mm == current->active_mm)
43988 +static inline void flush_tlb_page(struct vm_area_struct *vma,
43989 + unsigned long addr)
43991 + if (vma->vm_mm == current->active_mm)
43992 + __flush_tlb_one(addr);
43995 +static inline void flush_tlb_range(struct vm_area_struct *vma,
43996 + unsigned long start, unsigned long end)
43998 + if (vma->vm_mm == current->active_mm)
44004 +#include <asm/smp.h>
44006 +#define local_flush_tlb() \
44009 +#define flush_tlb_all xen_tlb_flush_all
44010 +#define flush_tlb_current_task() xen_tlb_flush_mask(¤t->mm->cpu_vm_mask)
44011 +#define flush_tlb_mm(mm) xen_tlb_flush_mask(&(mm)->cpu_vm_mask)
44012 +#define flush_tlb_page(vma, va) xen_invlpg_mask(&(vma)->vm_mm->cpu_vm_mask, va)
44014 +#define flush_tlb() flush_tlb_current_task()
44016 +static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
44018 + flush_tlb_mm(vma->vm_mm);
44021 +#define TLBSTATE_OK 1
44022 +#define TLBSTATE_LAZY 2
44024 +/* Roughly an IPI every 20MB with 4k pages for freeing page table
44025 + ranges. Cost is about 42k of memory for each CPU. */
44026 +#define ARCH_FREE_PTE_NR 5350
44030 +#define flush_tlb_kernel_range(start, end) flush_tlb_all()
44032 +static inline void flush_tlb_pgtables(struct mm_struct *mm,
44033 + unsigned long start, unsigned long end)
44035 + /* x86_64 does not keep any page table caches in a software TLB.
44036 + The CPUs do in their hardware TLBs, but they are handled
44037 + by the normal TLB flushing algorithms. */
44040 +#endif /* _X8664_TLBFLUSH_H */
44041 Index: head-2008-11-25/include/asm-x86/mach-xen/asm/xor_64.h
44042 ===================================================================
44043 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44044 +++ head-2008-11-25/include/asm-x86/mach-xen/asm/xor_64.h 2007-06-12 13:14:13.000000000 +0200
44047 + * x86-64 changes / gcc fixes from Andi Kleen.
44048 + * Copyright 2002 Andi Kleen, SuSE Labs.
44050 + * This hasn't been optimized for the hammer yet, but there are likely
44051 + * no advantages to be gotten from x86-64 here anyways.
44054 +typedef struct { unsigned long a,b; } __attribute__((aligned(16))) xmm_store_t;
44056 +/* Doesn't use gcc to save the XMM registers, because there is no easy way to
44057 + tell it to do a clts before the register saving. */
44058 +#define XMMS_SAVE do { \
44059 + preempt_disable(); \
44060 + if (!(current_thread_info()->status & TS_USEDFPU)) \
44062 + __asm__ __volatile__ ( \
44063 + "movups %%xmm0,(%1) ;\n\t" \
44064 + "movups %%xmm1,0x10(%1) ;\n\t" \
44065 + "movups %%xmm2,0x20(%1) ;\n\t" \
44066 + "movups %%xmm3,0x30(%1) ;\n\t" \
44068 + : "r" (xmm_save) \
44072 +#define XMMS_RESTORE do { \
44075 + "movups (%1),%%xmm0 ;\n\t" \
44076 + "movups 0x10(%1),%%xmm1 ;\n\t" \
44077 + "movups 0x20(%1),%%xmm2 ;\n\t" \
44078 + "movups 0x30(%1),%%xmm3 ;\n\t" \
44080 + : "r" (cr0), "r" (xmm_save) \
44082 + if (!(current_thread_info()->status & TS_USEDFPU)) \
44084 + preempt_enable(); \
44087 +#define OFFS(x) "16*("#x")"
44088 +#define PF_OFFS(x) "256+16*("#x")"
44089 +#define PF0(x) " prefetchnta "PF_OFFS(x)"(%[p1]) ;\n"
44090 +#define LD(x,y) " movaps "OFFS(x)"(%[p1]), %%xmm"#y" ;\n"
44091 +#define ST(x,y) " movaps %%xmm"#y", "OFFS(x)"(%[p1]) ;\n"
44092 +#define PF1(x) " prefetchnta "PF_OFFS(x)"(%[p2]) ;\n"
44093 +#define PF2(x) " prefetchnta "PF_OFFS(x)"(%[p3]) ;\n"
44094 +#define PF3(x) " prefetchnta "PF_OFFS(x)"(%[p4]) ;\n"
44095 +#define PF4(x) " prefetchnta "PF_OFFS(x)"(%[p5]) ;\n"
44096 +#define PF5(x) " prefetchnta "PF_OFFS(x)"(%[p6]) ;\n"
44097 +#define XO1(x,y) " xorps "OFFS(x)"(%[p2]), %%xmm"#y" ;\n"
44098 +#define XO2(x,y) " xorps "OFFS(x)"(%[p3]), %%xmm"#y" ;\n"
44099 +#define XO3(x,y) " xorps "OFFS(x)"(%[p4]), %%xmm"#y" ;\n"
44100 +#define XO4(x,y) " xorps "OFFS(x)"(%[p5]), %%xmm"#y" ;\n"
44101 +#define XO5(x,y) " xorps "OFFS(x)"(%[p6]), %%xmm"#y" ;\n"
44105 +xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
44107 + unsigned int lines = bytes >> 8;
44108 + unsigned long cr0;
44109 + xmm_store_t xmm_save[4];
44115 +#define BLOCK(i) \
44145 + " addq %[inc], %[p1] ;\n"
44146 + " addq %[inc], %[p2] ;\n"
44147 + " decl %[cnt] ; jnz 1b"
44148 + : [p1] "+r" (p1), [p2] "+r" (p2), [cnt] "+r" (lines)
44149 + : [inc] "r" (256UL)
44156 +xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
44157 + unsigned long *p3)
44159 + unsigned int lines = bytes >> 8;
44160 + xmm_store_t xmm_save[4];
44161 + unsigned long cr0;
44165 + __asm__ __volatile__ (
44167 +#define BLOCK(i) \
44203 + " addq %[inc], %[p1] ;\n"
44204 + " addq %[inc], %[p2] ;\n"
44205 + " addq %[inc], %[p3] ;\n"
44206 + " decl %[cnt] ; jnz 1b"
44207 + : [cnt] "+r" (lines),
44208 + [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
44209 + : [inc] "r" (256UL)
44215 +xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
44216 + unsigned long *p3, unsigned long *p4)
44218 + unsigned int lines = bytes >> 8;
44219 + xmm_store_t xmm_save[4];
44220 + unsigned long cr0;
44224 + __asm__ __volatile__ (
44226 +#define BLOCK(i) \
44268 + " addq %[inc], %[p1] ;\n"
44269 + " addq %[inc], %[p2] ;\n"
44270 + " addq %[inc], %[p3] ;\n"
44271 + " addq %[inc], %[p4] ;\n"
44272 + " decl %[cnt] ; jnz 1b"
44273 + : [cnt] "+c" (lines),
44274 + [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
44275 + : [inc] "r" (256UL)
44282 +xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
44283 + unsigned long *p3, unsigned long *p4, unsigned long *p5)
44285 + unsigned int lines = bytes >> 8;
44286 + xmm_store_t xmm_save[4];
44287 + unsigned long cr0;
44291 + __asm__ __volatile__ (
44293 +#define BLOCK(i) \
44341 + " addq %[inc], %[p1] ;\n"
44342 + " addq %[inc], %[p2] ;\n"
44343 + " addq %[inc], %[p3] ;\n"
44344 + " addq %[inc], %[p4] ;\n"
44345 + " addq %[inc], %[p5] ;\n"
44346 + " decl %[cnt] ; jnz 1b"
44347 + : [cnt] "+c" (lines),
44348 + [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4),
44350 + : [inc] "r" (256UL)
44356 +static struct xor_block_template xor_block_sse = {
44357 + .name = "generic_sse",
44358 + .do_2 = xor_sse_2,
44359 + .do_3 = xor_sse_3,
44360 + .do_4 = xor_sse_4,
44361 + .do_5 = xor_sse_5,
44364 +#undef XOR_TRY_TEMPLATES
44365 +#define XOR_TRY_TEMPLATES \
44367 + xor_speed(&xor_block_sse); \
44370 +/* We force the use of the SSE xor block because it can write around L2.
44371 + We may also be able to load into the L1 only depending on how the cpu
44372 + deals with a load to a line that is being prefetched. */
44373 +#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse)
44374 Index: head-2008-11-25/include/asm-x86/mach-xen/mach_time.h
44375 ===================================================================
44376 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44377 +++ head-2008-11-25/include/asm-x86/mach-xen/mach_time.h 2007-06-12 13:14:13.000000000 +0200
44380 + * include/asm-i386/mach-default/mach_time.h
44382 + * Machine specific set RTC function for generic.
44383 + * Split out from time.c by Osamu Tomita <tomita@cinet.co.jp>
44385 +#ifndef _MACH_TIME_H
44386 +#define _MACH_TIME_H
44388 +#include <asm-i386/mc146818rtc.h>
44390 +/* for check timing call set_rtc_mmss() 500ms */
44391 +/* used in arch/i386/time.c::do_timer_interrupt() */
44392 +#define USEC_AFTER 500000
44393 +#define USEC_BEFORE 500000
44396 + * In order to set the CMOS clock precisely, set_rtc_mmss has to be
44397 + * called 500 ms after the second nowtime has started, because when
44398 + * nowtime is written into the registers of the CMOS clock, it will
44399 + * jump to the next second precisely 500 ms later. Check the Motorola
44400 + * MC146818A or Dallas DS12887 data sheet for details.
44402 + * BUG: This routine does not handle hour overflow properly; it just
44403 + * sets the minutes. Usually you'll only notice that after reboot!
44405 +static inline int mach_set_rtc_mmss(unsigned long nowtime)
44408 + int real_seconds, real_minutes, cmos_minutes;
44409 + unsigned char save_control, save_freq_select;
44411 + save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
44412 + CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
44414 + save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
44415 + CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
44417 + cmos_minutes = CMOS_READ(RTC_MINUTES);
44418 + if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
44419 + BCD_TO_BIN(cmos_minutes);
44422 + * since we're only adjusting minutes and seconds,
44423 + * don't interfere with hour overflow. This avoids
44424 + * messing with unknown time zones but requires your
44425 + * RTC not to be off by more than 15 minutes
44427 + real_seconds = nowtime % 60;
44428 + real_minutes = nowtime / 60;
44429 + if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
44430 + real_minutes += 30; /* correct for half hour time zone */
44431 + real_minutes %= 60;
44433 + if (abs(real_minutes - cmos_minutes) < 30) {
44434 + if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
44435 + BIN_TO_BCD(real_seconds);
44436 + BIN_TO_BCD(real_minutes);
44438 + CMOS_WRITE(real_seconds,RTC_SECONDS);
44439 + CMOS_WRITE(real_minutes,RTC_MINUTES);
44441 + printk(KERN_WARNING
44442 + "set_rtc_mmss: can't update from %d to %d\n",
44443 + cmos_minutes, real_minutes);
44447 + /* The following flags have to be released exactly in this order,
44448 + * otherwise the DS12887 (popular MC146818A clone with integrated
44449 + * battery and quartz) will not reset the oscillator and will not
44450 + * update precisely 500 ms later. You won't find this mentioned in
44451 + * the Dallas Semiconductor data sheets, but who believes data
44452 + * sheets anyway ... -- Markus Kuhn
44454 + CMOS_WRITE(save_control, RTC_CONTROL);
44455 + CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
44460 +static inline unsigned long mach_get_cmos_time(void)
44462 + unsigned int year, mon, day, hour, min, sec;
44465 + sec = CMOS_READ(RTC_SECONDS);
44466 + min = CMOS_READ(RTC_MINUTES);
44467 + hour = CMOS_READ(RTC_HOURS);
44468 + day = CMOS_READ(RTC_DAY_OF_MONTH);
44469 + mon = CMOS_READ(RTC_MONTH);
44470 + year = CMOS_READ(RTC_YEAR);
44471 + } while (sec != CMOS_READ(RTC_SECONDS));
44473 + if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
44476 + BCD_TO_BIN(hour);
44479 + BCD_TO_BIN(year);
44486 + return mktime(year, mon, day, hour, min, sec);
44489 +#endif /* !_MACH_TIME_H */
44490 Index: head-2008-11-25/include/asm-x86/mach-xen/setup_arch_post.h
44491 ===================================================================
44492 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44493 +++ head-2008-11-25/include/asm-x86/mach-xen/setup_arch_post.h 2007-06-12 13:14:13.000000000 +0200
44496 + * machine_specific_* - Hooks for machine specific setup.
44499 + * This is included late in kernel/setup.c so that it can make
44500 + * use of all of the static functions.
44503 +#include <xen/interface/callback.h>
44505 +extern void hypervisor_callback(void);
44506 +extern void failsafe_callback(void);
44507 +extern void nmi(void);
44509 +static void __init machine_specific_arch_setup(void)
44512 + static struct callback_register __initdata event = {
44513 + .type = CALLBACKTYPE_event,
44514 + .address = (unsigned long) hypervisor_callback,
44516 + static struct callback_register __initdata failsafe = {
44517 + .type = CALLBACKTYPE_failsafe,
44518 + .address = (unsigned long)failsafe_callback,
44520 + static struct callback_register __initdata syscall = {
44521 + .type = CALLBACKTYPE_syscall,
44522 + .address = (unsigned long)system_call,
44524 +#ifdef CONFIG_X86_LOCAL_APIC
44525 + static struct callback_register __initdata nmi_cb = {
44526 + .type = CALLBACKTYPE_nmi,
44527 + .address = (unsigned long)nmi,
44531 + ret = HYPERVISOR_callback_op(CALLBACKOP_register, &event);
44533 + ret = HYPERVISOR_callback_op(CALLBACKOP_register, &failsafe);
44535 + ret = HYPERVISOR_callback_op(CALLBACKOP_register, &syscall);
44536 +#if CONFIG_XEN_COMPAT <= 0x030002
44537 + if (ret == -ENOSYS)
44538 + ret = HYPERVISOR_set_callbacks(
44540 + failsafe.address,
44541 + syscall.address);
44545 +#ifdef CONFIG_X86_LOCAL_APIC
44546 + ret = HYPERVISOR_callback_op(CALLBACKOP_register, &nmi_cb);
44547 +#if CONFIG_XEN_COMPAT <= 0x030002
44548 + if (ret == -ENOSYS) {
44549 + static struct xennmi_callback __initdata cb = {
44550 + .handler_address = (unsigned long)nmi
44553 + HYPERVISOR_nmi_op(XENNMI_register_callback, &cb);
44558 Index: head-2008-11-25/include/asm-x86/mach-xen/setup_arch_pre.h
44559 ===================================================================
44560 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44561 +++ head-2008-11-25/include/asm-x86/mach-xen/setup_arch_pre.h 2007-06-12 13:14:13.000000000 +0200
44563 +/* Hook to call BIOS initialisation function */
44565 +#define ARCH_SETUP machine_specific_arch_setup();
44567 +static void __init machine_specific_arch_setup(void);
44568 Index: head-2008-11-25/include/xen/blkif.h
44569 ===================================================================
44570 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44571 +++ head-2008-11-25/include/xen/blkif.h 2008-07-21 11:00:33.000000000 +0200
44574 + * Permission is hereby granted, free of charge, to any person obtaining a copy
44575 + * of this software and associated documentation files (the "Software"), to
44576 + * deal in the Software without restriction, including without limitation the
44577 + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
44578 + * sell copies of the Software, and to permit persons to whom the Software is
44579 + * furnished to do so, subject to the following conditions:
44581 + * The above copyright notice and this permission notice shall be included in
44582 + * all copies or substantial portions of the Software.
44584 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
44585 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
44586 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
44587 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44588 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44589 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
44590 + * DEALINGS IN THE SOFTWARE.
44593 +#ifndef __XEN_BLKIF_H__
44594 +#define __XEN_BLKIF_H__
44596 +#include <xen/interface/io/ring.h>
44597 +#include <xen/interface/io/blkif.h>
44598 +#include <xen/interface/io/protocols.h>
44600 +/* Not a real protocol. Used to generate ring structs which contain
44601 + * the elements common to all protocols only. This way we get a
44602 + * compiler-checkable way to use common struct elements, so we can
44603 + * avoid using switch(protocol) in a number of places. */
44604 +struct blkif_common_request {
44607 +struct blkif_common_response {
44611 +/* i386 protocol version */
44612 +#pragma pack(push, 4)
44613 +struct blkif_x86_32_request {
44614 + uint8_t operation; /* BLKIF_OP_??? */
44615 + uint8_t nr_segments; /* number of segments */
44616 + blkif_vdev_t handle; /* only for read/write requests */
44617 + uint64_t id; /* private guest value, echoed in resp */
44618 + blkif_sector_t sector_number;/* start sector idx on disk (r/w only) */
44619 + struct blkif_request_segment seg[BLKIF_MAX_SEGMENTS_PER_REQUEST];
44621 +struct blkif_x86_32_response {
44622 + uint64_t id; /* copied from request */
44623 + uint8_t operation; /* copied from request */
44624 + int16_t status; /* BLKIF_RSP_??? */
44626 +typedef struct blkif_x86_32_request blkif_x86_32_request_t;
44627 +typedef struct blkif_x86_32_response blkif_x86_32_response_t;
44630 +/* x86_64 protocol version */
44631 +struct blkif_x86_64_request {
44632 + uint8_t operation; /* BLKIF_OP_??? */
44633 + uint8_t nr_segments; /* number of segments */
44634 + blkif_vdev_t handle; /* only for read/write requests */
44635 + uint64_t __attribute__((__aligned__(8))) id;
44636 + blkif_sector_t sector_number;/* start sector idx on disk (r/w only) */
44637 + struct blkif_request_segment seg[BLKIF_MAX_SEGMENTS_PER_REQUEST];
44639 +struct blkif_x86_64_response {
44640 + uint64_t __attribute__((__aligned__(8))) id;
44641 + uint8_t operation; /* copied from request */
44642 + int16_t status; /* BLKIF_RSP_??? */
44644 +typedef struct blkif_x86_64_request blkif_x86_64_request_t;
44645 +typedef struct blkif_x86_64_response blkif_x86_64_response_t;
44647 +DEFINE_RING_TYPES(blkif_common, struct blkif_common_request, struct blkif_common_response);
44648 +DEFINE_RING_TYPES(blkif_x86_32, struct blkif_x86_32_request, struct blkif_x86_32_response);
44649 +DEFINE_RING_TYPES(blkif_x86_64, struct blkif_x86_64_request, struct blkif_x86_64_response);
44651 +union blkif_back_rings {
44652 + blkif_back_ring_t native;
44653 + blkif_common_back_ring_t common;
44654 + blkif_x86_32_back_ring_t x86_32;
44655 + blkif_x86_64_back_ring_t x86_64;
44657 +typedef union blkif_back_rings blkif_back_rings_t;
44659 +enum blkif_protocol {
44660 + BLKIF_PROTOCOL_NATIVE = 1,
44661 + BLKIF_PROTOCOL_X86_32 = 2,
44662 + BLKIF_PROTOCOL_X86_64 = 3,
44665 +static void inline blkif_get_x86_32_req(blkif_request_t *dst, blkif_x86_32_request_t *src)
44667 + int i, n = BLKIF_MAX_SEGMENTS_PER_REQUEST;
44668 + dst->operation = src->operation;
44669 + dst->nr_segments = src->nr_segments;
44670 + dst->handle = src->handle;
44671 + dst->id = src->id;
44672 + dst->sector_number = src->sector_number;
44674 + if (n > dst->nr_segments)
44675 + n = dst->nr_segments;
44676 + for (i = 0; i < n; i++)
44677 + dst->seg[i] = src->seg[i];
44680 +static void inline blkif_get_x86_64_req(blkif_request_t *dst, blkif_x86_64_request_t *src)
44682 + int i, n = BLKIF_MAX_SEGMENTS_PER_REQUEST;
44683 + dst->operation = src->operation;
44684 + dst->nr_segments = src->nr_segments;
44685 + dst->handle = src->handle;
44686 + dst->id = src->id;
44687 + dst->sector_number = src->sector_number;
44689 + if (n > dst->nr_segments)
44690 + n = dst->nr_segments;
44691 + for (i = 0; i < n; i++)
44692 + dst->seg[i] = src->seg[i];
44695 +#endif /* __XEN_BLKIF_H__ */
44696 Index: head-2008-11-25/include/xen/compat_ioctl.h
44697 ===================================================================
44698 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44699 +++ head-2008-11-25/include/xen/compat_ioctl.h 2007-07-10 09:42:30.000000000 +0200
44702 + * This program is free software; you can redistribute it and/or
44703 + * modify it under the terms of the GNU General Public License as
44704 + * published by the Free Software Foundation; either version 2 of the
44705 + * License, or (at your option) any later version.
44707 + * This program is distributed in the hope that it will be useful,
44708 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
44709 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
44710 + * GNU General Public License for more details.
44712 + * You should have received a copy of the GNU General Public License
44713 + * along with this program; if not, write to the Free Software
44714 + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
44716 + * Copyright IBM Corp. 2007
44718 + * Authors: Jimi Xenidis <jimix@watson.ibm.com>
44719 + * Hollis Blanchard <hollisb@us.ibm.com>
44722 +#ifndef __LINUX_XEN_COMPAT_H__
44723 +#define __LINUX_XEN_COMPAT_H__
44725 +#include <linux/compat.h>
44727 +extern int privcmd_ioctl_32(int fd, unsigned int cmd, unsigned long arg);
44728 +struct privcmd_mmap_32 {
44731 + compat_uptr_t entry;
44734 +struct privcmd_mmapbatch_32 {
44735 + int num; /* number of pages to populate */
44736 + domid_t dom; /* target domain */
44737 + __u64 addr; /* virtual address */
44738 + compat_uptr_t arr; /* array of mfns - top nibble set on err */
44740 +#define IOCTL_PRIVCMD_MMAP_32 \
44741 + _IOC(_IOC_NONE, 'P', 2, sizeof(struct privcmd_mmap_32))
44742 +#define IOCTL_PRIVCMD_MMAPBATCH_32 \
44743 + _IOC(_IOC_NONE, 'P', 3, sizeof(struct privcmd_mmapbatch_32))
44745 +#endif /* __LINUX_XEN_COMPAT_H__ */
44746 Index: head-2008-11-25/include/xen/cpu_hotplug.h
44747 ===================================================================
44748 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44749 +++ head-2008-11-25/include/xen/cpu_hotplug.h 2007-08-16 18:07:01.000000000 +0200
44751 +#ifndef __XEN_CPU_HOTPLUG_H__
44752 +#define __XEN_CPU_HOTPLUG_H__
44754 +#include <linux/kernel.h>
44755 +#include <linux/cpumask.h>
44757 +#if defined(CONFIG_X86) && defined(CONFIG_SMP)
44758 +extern cpumask_t cpu_initialized_map;
44761 +#if defined(CONFIG_HOTPLUG_CPU)
44763 +int cpu_up_check(unsigned int cpu);
44764 +void init_xenbus_allowed_cpumask(void);
44765 +int smp_suspend(void);
44766 +void smp_resume(void);
44768 +void cpu_bringup(void);
44770 +#else /* !defined(CONFIG_HOTPLUG_CPU) */
44772 +#define cpu_up_check(cpu) (0)
44773 +#define init_xenbus_allowed_cpumask() ((void)0)
44775 +static inline int smp_suspend(void)
44777 + if (num_online_cpus() > 1) {
44778 + printk(KERN_WARNING "Can't suspend SMP guests "
44779 + "without CONFIG_HOTPLUG_CPU\n");
44780 + return -EOPNOTSUPP;
44785 +static inline void smp_resume(void)
44789 +#endif /* !defined(CONFIG_HOTPLUG_CPU) */
44791 +#endif /* __XEN_CPU_HOTPLUG_H__ */
44792 Index: head-2008-11-25/include/xen/driver_util.h
44793 ===================================================================
44794 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44795 +++ head-2008-11-25/include/xen/driver_util.h 2007-06-12 13:14:19.000000000 +0200
44798 +#ifndef __ASM_XEN_DRIVER_UTIL_H__
44799 +#define __ASM_XEN_DRIVER_UTIL_H__
44801 +#include <linux/vmalloc.h>
44802 +#include <linux/device.h>
44804 +/* Allocate/destroy a 'vmalloc' VM area. */
44805 +extern struct vm_struct *alloc_vm_area(unsigned long size);
44806 +extern void free_vm_area(struct vm_struct *area);
44808 +extern struct class *get_xen_class(void);
44810 +#endif /* __ASM_XEN_DRIVER_UTIL_H__ */
44811 Index: head-2008-11-25/include/xen/evtchn.h
44812 ===================================================================
44813 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44814 +++ head-2008-11-25/include/xen/evtchn.h 2008-09-15 13:40:15.000000000 +0200
44816 +/******************************************************************************
44819 + * Communication via Xen event channels.
44820 + * Also definitions for the device that demuxes notifications to userspace.
44822 + * Copyright (c) 2004-2005, K A Fraser
44824 + * This program is free software; you can redistribute it and/or
44825 + * modify it under the terms of the GNU General Public License version 2
44826 + * as published by the Free Software Foundation; or, when distributed
44827 + * separately from the Linux kernel or incorporated into other
44828 + * software packages, subject to the following license:
44830 + * Permission is hereby granted, free of charge, to any person obtaining a copy
44831 + * of this source file (the "Software"), to deal in the Software without
44832 + * restriction, including without limitation the rights to use, copy, modify,
44833 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
44834 + * and to permit persons to whom the Software is furnished to do so, subject to
44835 + * the following conditions:
44837 + * The above copyright notice and this permission notice shall be included in
44838 + * all copies or substantial portions of the Software.
44840 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
44841 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
44842 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
44843 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44844 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44845 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
44846 + * IN THE SOFTWARE.
44849 +#ifndef __ASM_EVTCHN_H__
44850 +#define __ASM_EVTCHN_H__
44852 +#include <linux/interrupt.h>
44853 +#include <asm/hypervisor.h>
44854 +#include <asm/ptrace.h>
44855 +#include <asm/synch_bitops.h>
44856 +#include <xen/interface/event_channel.h>
44857 +#include <linux/smp.h>
44860 + * LOW-LEVEL DEFINITIONS
44864 + * Dynamically bind an event source to an IRQ-like callback handler.
44865 + * On some platforms this may not be implemented via the Linux IRQ subsystem.
44866 + * The IRQ argument passed to the callback handler is the same as returned
44867 + * from the bind call. It may not correspond to a Linux IRQ number.
44868 + * Returns IRQ or negative errno.
44870 +int bind_caller_port_to_irqhandler(
44871 + unsigned int caller_port,
44872 + irqreturn_t (*handler)(int, void *, struct pt_regs *),
44873 + unsigned long irqflags,
44874 + const char *devname,
44876 +int bind_listening_port_to_irqhandler(
44877 + unsigned int remote_domain,
44878 + irqreturn_t (*handler)(int, void *, struct pt_regs *),
44879 + unsigned long irqflags,
44880 + const char *devname,
44882 +int bind_interdomain_evtchn_to_irqhandler(
44883 + unsigned int remote_domain,
44884 + unsigned int remote_port,
44885 + irqreturn_t (*handler)(int, void *, struct pt_regs *),
44886 + unsigned long irqflags,
44887 + const char *devname,
44889 +int bind_virq_to_irqhandler(
44890 + unsigned int virq,
44891 + unsigned int cpu,
44892 + irqreturn_t (*handler)(int, void *, struct pt_regs *),
44893 + unsigned long irqflags,
44894 + const char *devname,
44896 +int bind_ipi_to_irqhandler(
44897 + unsigned int ipi,
44898 + unsigned int cpu,
44899 + irqreturn_t (*handler)(int, void *, struct pt_regs *),
44900 + unsigned long irqflags,
44901 + const char *devname,
44905 + * Common unbind function for all event sources. Takes IRQ to unbind from.
44906 + * Automatically closes the underlying event channel (except for bindings
44907 + * made with bind_caller_port_to_irqhandler()).
44909 +void unbind_from_irqhandler(unsigned int irq, void *dev_id);
44911 +void irq_resume(void);
44913 +/* Entry point for notifications into Linux subsystems. */
44914 +asmlinkage void evtchn_do_upcall(struct pt_regs *regs);
44916 +/* Entry point for notifications into the userland character device. */
44917 +void evtchn_device_upcall(int port);
44919 +/* Mark a PIRQ as unavailable for dynamic allocation. */
44920 +void evtchn_register_pirq(int irq);
44921 +/* Map a Xen-supplied PIRQ to a dynamically allocated one. */
44922 +int evtchn_map_pirq(int irq, int xen_pirq);
44923 +/* Look up a Xen-supplied PIRQ for a dynamically allocated one. */
44924 +int evtchn_get_xen_pirq(int irq);
44926 +void mask_evtchn(int port);
44927 +void disable_all_local_evtchn(void);
44928 +void unmask_evtchn(int port);
44931 +void rebind_evtchn_to_cpu(int port, unsigned int cpu);
44933 +#define rebind_evtchn_to_cpu(port, cpu) ((void)0)
44936 +static inline int test_and_set_evtchn_mask(int port)
44938 + shared_info_t *s = HYPERVISOR_shared_info;
44939 + return synch_test_and_set_bit(port, s->evtchn_mask);
44942 +static inline void clear_evtchn(int port)
44944 + shared_info_t *s = HYPERVISOR_shared_info;
44945 + synch_clear_bit(port, s->evtchn_pending);
44948 +static inline void notify_remote_via_evtchn(int port)
44950 + struct evtchn_send send = { .port = port };
44951 + VOID(HYPERVISOR_event_channel_op(EVTCHNOP_send, &send));
44955 + * Use these to access the event channel underlying the IRQ handle returned
44956 + * by bind_*_to_irqhandler().
44958 +void notify_remote_via_irq(int irq);
44959 +int irq_to_evtchn_port(int irq);
44961 +#define PIRQ_SET_MAPPING 0x0
44962 +#define PIRQ_CLEAR_MAPPING 0x1
44963 +#define PIRQ_GET_MAPPING 0x3
44964 +int pirq_mapstatus(int pirq, int action);
44965 +int set_pirq_hw_action(int pirq, int (*action)(int pirq, int action));
44966 +int clear_pirq_hw_action(int pirq);
44968 +#define PIRQ_STARTUP 1
44969 +#define PIRQ_SHUTDOWN 2
44970 +#define PIRQ_ENABLE 3
44971 +#define PIRQ_DISABLE 4
44972 +#define PIRQ_END 5
44973 +#define PIRQ_ACK 6
44975 +#endif /* __ASM_EVTCHN_H__ */
44976 Index: head-2008-11-25/include/xen/firmware.h
44977 ===================================================================
44978 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44979 +++ head-2008-11-25/include/xen/firmware.h 2007-07-02 08:16:19.000000000 +0200
44981 +#ifndef __XEN_FIRMWARE_H__
44982 +#define __XEN_FIRMWARE_H__
44984 +#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
44985 +void copy_edd(void);
44988 +void copy_edid(void);
44990 +#endif /* __XEN_FIRMWARE_H__ */
44991 Index: head-2008-11-25/include/xen/gnttab.h
44992 ===================================================================
44993 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44994 +++ head-2008-11-25/include/xen/gnttab.h 2008-11-04 11:13:10.000000000 +0100
44996 +/******************************************************************************
44999 + * Two sets of functionality:
45000 + * 1. Granting foreign access to our memory reservation.
45001 + * 2. Accessing others' memory reservations via grant references.
45002 + * (i.e., mechanisms for both sender and recipient of grant references)
45004 + * Copyright (c) 2004-2005, K A Fraser
45005 + * Copyright (c) 2005, Christopher Clark
45007 + * This program is free software; you can redistribute it and/or
45008 + * modify it under the terms of the GNU General Public License version 2
45009 + * as published by the Free Software Foundation; or, when distributed
45010 + * separately from the Linux kernel or incorporated into other
45011 + * software packages, subject to the following license:
45013 + * Permission is hereby granted, free of charge, to any person obtaining a copy
45014 + * of this source file (the "Software"), to deal in the Software without
45015 + * restriction, including without limitation the rights to use, copy, modify,
45016 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
45017 + * and to permit persons to whom the Software is furnished to do so, subject to
45018 + * the following conditions:
45020 + * The above copyright notice and this permission notice shall be included in
45021 + * all copies or substantial portions of the Software.
45023 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45024 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
45025 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
45026 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
45027 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45028 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
45029 + * IN THE SOFTWARE.
45032 +#ifndef __ASM_GNTTAB_H__
45033 +#define __ASM_GNTTAB_H__
45035 +#include <asm/hypervisor.h>
45036 +#include <asm/maddr.h> /* maddr_t */
45037 +#include <linux/mm.h>
45038 +#include <xen/interface/grant_table.h>
45039 +#include <xen/features.h>
45041 +struct gnttab_free_callback {
45042 + struct gnttab_free_callback *next;
45043 + void (*fn)(void *);
45049 +int gnttab_grant_foreign_access(domid_t domid, unsigned long frame,
45053 + * End access through the given grant reference, iff the grant entry is no
45054 + * longer in use. Return 1 if the grant entry was freed, 0 if it is still in
45057 +int gnttab_end_foreign_access_ref(grant_ref_t ref);
45060 + * Eventually end access through the given grant reference, and once that
45061 + * access has been ended, free the given page too. Access will be ended
45062 + * immediately iff the grant entry is not in use, otherwise it will happen
45063 + * some time later. page may be 0, in which case no freeing will occur.
45065 +void gnttab_end_foreign_access(grant_ref_t ref, unsigned long page);
45067 +int gnttab_grant_foreign_transfer(domid_t domid, unsigned long pfn);
45069 +unsigned long gnttab_end_foreign_transfer_ref(grant_ref_t ref);
45070 +unsigned long gnttab_end_foreign_transfer(grant_ref_t ref);
45072 +int gnttab_query_foreign_access(grant_ref_t ref);
45075 + * operations on reserved batches of grant references
45077 +int gnttab_alloc_grant_references(u16 count, grant_ref_t *pprivate_head);
45079 +void gnttab_free_grant_reference(grant_ref_t ref);
45081 +void gnttab_free_grant_references(grant_ref_t head);
45083 +int gnttab_empty_grant_references(const grant_ref_t *pprivate_head);
45085 +int gnttab_claim_grant_reference(grant_ref_t *pprivate_head);
45087 +void gnttab_release_grant_reference(grant_ref_t *private_head,
45088 + grant_ref_t release);
45090 +void gnttab_request_free_callback(struct gnttab_free_callback *callback,
45091 + void (*fn)(void *), void *arg, u16 count);
45092 +void gnttab_cancel_free_callback(struct gnttab_free_callback *callback);
45094 +void gnttab_grant_foreign_access_ref(grant_ref_t ref, domid_t domid,
45095 + unsigned long frame, int flags);
45097 +void gnttab_grant_foreign_transfer_ref(grant_ref_t, domid_t domid,
45098 + unsigned long pfn);
45100 +int gnttab_copy_grant_page(grant_ref_t ref, struct page **pagep);
45101 +void __gnttab_dma_map_page(struct page *page);
45102 +static inline void __gnttab_dma_unmap_page(struct page *page)
45106 +void gnttab_reset_grant_page(struct page *page);
45108 +int gnttab_suspend(void);
45109 +int gnttab_resume(void);
45111 +void *arch_gnttab_alloc_shared(unsigned long *frames);
45113 +static inline void
45114 +gnttab_set_map_op(struct gnttab_map_grant_ref *map, maddr_t addr,
45115 + uint32_t flags, grant_ref_t ref, domid_t domid)
45117 + if (flags & GNTMAP_contains_pte)
45118 + map->host_addr = addr;
45119 + else if (xen_feature(XENFEAT_auto_translated_physmap))
45120 + map->host_addr = __pa(addr);
45122 + map->host_addr = addr;
45124 + map->flags = flags;
45126 + map->dom = domid;
45129 +static inline void
45130 +gnttab_set_unmap_op(struct gnttab_unmap_grant_ref *unmap, maddr_t addr,
45131 + uint32_t flags, grant_handle_t handle)
45133 + if (flags & GNTMAP_contains_pte)
45134 + unmap->host_addr = addr;
45135 + else if (xen_feature(XENFEAT_auto_translated_physmap))
45136 + unmap->host_addr = __pa(addr);
45138 + unmap->host_addr = addr;
45140 + unmap->handle = handle;
45141 + unmap->dev_bus_addr = 0;
45144 +static inline void
45145 +gnttab_set_replace_op(struct gnttab_unmap_and_replace *unmap, maddr_t addr,
45146 + maddr_t new_addr, grant_handle_t handle)
45148 + if (xen_feature(XENFEAT_auto_translated_physmap)) {
45149 + unmap->host_addr = __pa(addr);
45150 + unmap->new_addr = __pa(new_addr);
45152 + unmap->host_addr = addr;
45153 + unmap->new_addr = new_addr;
45156 + unmap->handle = handle;
45159 +#endif /* __ASM_GNTTAB_H__ */
45160 Index: head-2008-11-25/include/xen/hvm.h
45161 ===================================================================
45162 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45163 +++ head-2008-11-25/include/xen/hvm.h 2007-06-12 13:14:19.000000000 +0200
45165 +/* Simple wrappers around HVM functions */
45166 +#ifndef XEN_HVM_H__
45167 +#define XEN_HVM_H__
45169 +#include <xen/interface/hvm/params.h>
45171 +static inline unsigned long hvm_get_parameter(int idx)
45173 + struct xen_hvm_param xhv;
45176 + xhv.domid = DOMID_SELF;
45178 + r = HYPERVISOR_hvm_op(HVMOP_get_param, &xhv);
45180 + printk(KERN_ERR "cannot get hvm parameter %d: %d.\n",
45184 + return xhv.value;
45187 +#endif /* XEN_HVM_H__ */
45188 Index: head-2008-11-25/include/xen/hypercall.h
45189 ===================================================================
45190 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45191 +++ head-2008-11-25/include/xen/hypercall.h 2008-01-28 12:24:19.000000000 +0100
45193 +#ifndef __XEN_HYPERCALL_H__
45194 +#define __XEN_HYPERCALL_H__
45196 +#include <asm/hypercall.h>
45198 +static inline int __must_check
45199 +HYPERVISOR_multicall_check(
45200 + multicall_entry_t *call_list, unsigned int nr_calls,
45201 + const unsigned long *rc_list)
45203 + int rc = HYPERVISOR_multicall(call_list, nr_calls);
45205 + if (unlikely(rc < 0))
45208 + BUG_ON((int)nr_calls < 0);
45210 + for ( ; nr_calls > 0; --nr_calls, ++call_list)
45211 + if (unlikely(call_list->result != (rc_list ? *rc_list++ : 0)))
45217 +/* A construct to ignore the return value of hypercall wrappers in a few
45218 + * exceptional cases (simply casting the function result to void doesn't
45219 + * avoid the compiler warning): */
45220 +#define VOID(expr) ((void)((expr)?:0))
45222 +#endif /* __XEN_HYPERCALL_H__ */
45223 Index: head-2008-11-25/include/xen/hypervisor_sysfs.h
45224 ===================================================================
45225 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45226 +++ head-2008-11-25/include/xen/hypervisor_sysfs.h 2007-06-22 09:08:06.000000000 +0200
45229 + * copyright (c) 2006 IBM Corporation
45230 + * Authored by: Mike D. Day <ncmike@us.ibm.com>
45232 + * This program is free software; you can redistribute it and/or modify
45233 + * it under the terms of the GNU General Public License version 2 as
45234 + * published by the Free Software Foundation.
45237 +#ifndef _HYP_SYSFS_H_
45238 +#define _HYP_SYSFS_H_
45240 +#include <linux/kobject.h>
45241 +#include <linux/sysfs.h>
45243 +#define HYPERVISOR_ATTR_RO(_name) \
45244 +static struct hyp_sysfs_attr _name##_attr = __ATTR_RO(_name)
45246 +#define HYPERVISOR_ATTR_RW(_name) \
45247 +static struct hyp_sysfs_attr _name##_attr = \
45248 + __ATTR(_name, 0644, _name##_show, _name##_store)
45250 +struct hyp_sysfs_attr {
45251 + struct attribute attr;
45252 + ssize_t (*show)(struct hyp_sysfs_attr *, char *);
45253 + ssize_t (*store)(struct hyp_sysfs_attr *, const char *, size_t);
45254 + void *hyp_attr_data;
45257 +#endif /* _HYP_SYSFS_H_ */
45258 Index: head-2008-11-25/include/xen/pcifront.h
45259 ===================================================================
45260 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45261 +++ head-2008-11-25/include/xen/pcifront.h 2007-06-18 08:38:13.000000000 +0200
45264 + * PCI Frontend - arch-dependendent declarations
45266 + * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
45268 +#ifndef __XEN_ASM_PCIFRONT_H__
45269 +#define __XEN_ASM_PCIFRONT_H__
45271 +#include <linux/spinlock.h>
45277 +struct pcifront_device;
45280 +struct pcifront_sd {
45282 + struct pcifront_device *pdev;
45285 +static inline struct pcifront_device *
45286 +pcifront_get_pdev(struct pcifront_sd *sd)
45291 +static inline void pcifront_init_sd(struct pcifront_sd *sd,
45292 + unsigned int domain, unsigned int bus,
45293 + struct pcifront_device *pdev)
45295 + sd->domain = domain;
45299 +#if defined(CONFIG_PCI_DOMAINS)
45300 +static inline int pci_domain_nr(struct pci_bus *bus)
45302 + struct pcifront_sd *sd = bus->sysdata;
45303 + return sd->domain;
45305 +static inline int pci_proc_domain(struct pci_bus *bus)
45307 + return pci_domain_nr(bus);
45309 +#endif /* CONFIG_PCI_DOMAINS */
45311 +static inline void pcifront_setup_root_resources(struct pci_bus *bus,
45312 + struct pcifront_sd *sd)
45316 +#else /* __ia64__ */
45318 +#include <linux/acpi.h>
45319 +#include <asm/pci.h>
45320 +#define pcifront_sd pci_controller
45322 +extern void xen_add_resource(struct pci_controller *, unsigned int,
45323 + unsigned int, struct acpi_resource *);
45324 +extern void xen_pcibios_setup_root_windows(struct pci_bus *,
45325 + struct pci_controller *);
45327 +static inline struct pcifront_device *
45328 +pcifront_get_pdev(struct pcifront_sd *sd)
45330 + return (struct pcifront_device *)sd->platform_data;
45333 +static inline void pcifront_setup_root_resources(struct pci_bus *bus,
45334 + struct pcifront_sd *sd)
45336 + xen_pcibios_setup_root_windows(bus, sd);
45339 +#endif /* __ia64__ */
45341 +extern struct rw_semaphore pci_bus_sem;
45343 +#endif /* __KERNEL__ */
45345 +#endif /* __XEN_ASM_PCIFRONT_H__ */
45346 Index: head-2008-11-25/include/xen/public/evtchn.h
45347 ===================================================================
45348 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45349 +++ head-2008-11-25/include/xen/public/evtchn.h 2007-06-12 13:14:19.000000000 +0200
45351 +/******************************************************************************
45354 + * Interface to /dev/xen/evtchn.
45356 + * Copyright (c) 2003-2005, K A Fraser
45358 + * This program is free software; you can redistribute it and/or
45359 + * modify it under the terms of the GNU General Public License version 2
45360 + * as published by the Free Software Foundation; or, when distributed
45361 + * separately from the Linux kernel or incorporated into other
45362 + * software packages, subject to the following license:
45364 + * Permission is hereby granted, free of charge, to any person obtaining a copy
45365 + * of this source file (the "Software"), to deal in the Software without
45366 + * restriction, including without limitation the rights to use, copy, modify,
45367 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
45368 + * and to permit persons to whom the Software is furnished to do so, subject to
45369 + * the following conditions:
45371 + * The above copyright notice and this permission notice shall be included in
45372 + * all copies or substantial portions of the Software.
45374 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45375 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
45376 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
45377 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
45378 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45379 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
45380 + * IN THE SOFTWARE.
45383 +#ifndef __LINUX_PUBLIC_EVTCHN_H__
45384 +#define __LINUX_PUBLIC_EVTCHN_H__
45387 + * Bind a fresh port to VIRQ @virq.
45388 + * Return allocated port.
45390 +#define IOCTL_EVTCHN_BIND_VIRQ \
45391 + _IOC(_IOC_NONE, 'E', 0, sizeof(struct ioctl_evtchn_bind_virq))
45392 +struct ioctl_evtchn_bind_virq {
45393 + unsigned int virq;
45397 + * Bind a fresh port to remote <@remote_domain, @remote_port>.
45398 + * Return allocated port.
45400 +#define IOCTL_EVTCHN_BIND_INTERDOMAIN \
45401 + _IOC(_IOC_NONE, 'E', 1, sizeof(struct ioctl_evtchn_bind_interdomain))
45402 +struct ioctl_evtchn_bind_interdomain {
45403 + unsigned int remote_domain, remote_port;
45407 + * Allocate a fresh port for binding to @remote_domain.
45408 + * Return allocated port.
45410 +#define IOCTL_EVTCHN_BIND_UNBOUND_PORT \
45411 + _IOC(_IOC_NONE, 'E', 2, sizeof(struct ioctl_evtchn_bind_unbound_port))
45412 +struct ioctl_evtchn_bind_unbound_port {
45413 + unsigned int remote_domain;
45417 + * Unbind previously allocated @port.
45419 +#define IOCTL_EVTCHN_UNBIND \
45420 + _IOC(_IOC_NONE, 'E', 3, sizeof(struct ioctl_evtchn_unbind))
45421 +struct ioctl_evtchn_unbind {
45422 + unsigned int port;
45426 + * Unbind previously allocated @port.
45428 +#define IOCTL_EVTCHN_NOTIFY \
45429 + _IOC(_IOC_NONE, 'E', 4, sizeof(struct ioctl_evtchn_notify))
45430 +struct ioctl_evtchn_notify {
45431 + unsigned int port;
45434 +/* Clear and reinitialise the event buffer. Clear error condition. */
45435 +#define IOCTL_EVTCHN_RESET \
45436 + _IOC(_IOC_NONE, 'E', 5, 0)
45438 +#endif /* __LINUX_PUBLIC_EVTCHN_H__ */
45439 Index: head-2008-11-25/include/xen/public/gntdev.h
45440 ===================================================================
45441 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45442 +++ head-2008-11-25/include/xen/public/gntdev.h 2008-04-02 12:34:02.000000000 +0200
45444 +/******************************************************************************
45447 + * Interface to /dev/xen/gntdev.
45449 + * Copyright (c) 2007, D G Murray
45451 + * This program is free software; you can redistribute it and/or
45452 + * modify it under the terms of the GNU General Public License version 2
45453 + * as published by the Free Software Foundation; or, when distributed
45454 + * separately from the Linux kernel or incorporated into other
45455 + * software packages, subject to the following license:
45457 + * Permission is hereby granted, free of charge, to any person obtaining a copy
45458 + * of this source file (the "Software"), to deal in the Software without
45459 + * restriction, including without limitation the rights to use, copy, modify,
45460 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
45461 + * and to permit persons to whom the Software is furnished to do so, subject to
45462 + * the following conditions:
45464 + * The above copyright notice and this permission notice shall be included in
45465 + * all copies or substantial portions of the Software.
45467 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45468 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
45469 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
45470 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
45471 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45472 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
45473 + * IN THE SOFTWARE.
45476 +#ifndef __LINUX_PUBLIC_GNTDEV_H__
45477 +#define __LINUX_PUBLIC_GNTDEV_H__
45479 +struct ioctl_gntdev_grant_ref {
45480 + /* The domain ID of the grant to be mapped. */
45482 + /* The grant reference of the grant to be mapped. */
45487 + * Inserts the grant references into the mapping table of an instance
45488 + * of gntdev. N.B. This does not perform the mapping, which is deferred
45489 + * until mmap() is called with @index as the offset.
45491 +#define IOCTL_GNTDEV_MAP_GRANT_REF \
45492 +_IOC(_IOC_NONE, 'G', 0, sizeof(struct ioctl_gntdev_map_grant_ref))
45493 +struct ioctl_gntdev_map_grant_ref {
45494 + /* IN parameters */
45495 + /* The number of grants to be mapped. */
45498 + /* OUT parameters */
45499 + /* The offset to be used on a subsequent call to mmap(). */
45501 + /* Variable IN parameter. */
45502 + /* Array of grant references, of size @count. */
45503 + struct ioctl_gntdev_grant_ref refs[1];
45507 + * Removes the grant references from the mapping table of an instance of
45508 + * of gntdev. N.B. munmap() must be called on the relevant virtual address(es)
45509 + * before this ioctl is called, or an error will result.
45511 +#define IOCTL_GNTDEV_UNMAP_GRANT_REF \
45512 +_IOC(_IOC_NONE, 'G', 1, sizeof(struct ioctl_gntdev_unmap_grant_ref))
45513 +struct ioctl_gntdev_unmap_grant_ref {
45514 + /* IN parameters */
45515 + /* The offset was returned by the corresponding map operation. */
45517 + /* The number of pages to be unmapped. */
45523 + * Returns the offset in the driver's address space that corresponds
45524 + * to @vaddr. This can be used to perform a munmap(), followed by an
45525 + * UNMAP_GRANT_REF ioctl, where no state about the offset is retained by
45526 + * the caller. The number of pages that were allocated at the same time as
45527 + * @vaddr is returned in @count.
45529 + * N.B. Where more than one page has been mapped into a contiguous range, the
45530 + * supplied @vaddr must correspond to the start of the range; otherwise
45531 + * an error will result. It is only possible to munmap() the entire
45532 + * contiguously-allocated range at once, and not any subrange thereof.
45534 +#define IOCTL_GNTDEV_GET_OFFSET_FOR_VADDR \
45535 +_IOC(_IOC_NONE, 'G', 2, sizeof(struct ioctl_gntdev_get_offset_for_vaddr))
45536 +struct ioctl_gntdev_get_offset_for_vaddr {
45537 + /* IN parameters */
45538 + /* The virtual address of the first mapped page in a range. */
45540 + /* OUT parameters */
45541 + /* The offset that was used in the initial mmap() operation. */
45543 + /* The number of pages mapped in the VM area that begins at @vaddr. */
45549 + * Sets the maximum number of grants that may mapped at once by this gntdev
45552 + * N.B. This must be called before any other ioctl is performed on the device.
45554 +#define IOCTL_GNTDEV_SET_MAX_GRANTS \
45555 +_IOC(_IOC_NONE, 'G', 3, sizeof(struct ioctl_gntdev_set_max_grants))
45556 +struct ioctl_gntdev_set_max_grants {
45557 + /* IN parameter */
45558 + /* The maximum number of grants that may be mapped at once. */
45562 +#endif /* __LINUX_PUBLIC_GNTDEV_H__ */
45563 Index: head-2008-11-25/include/xen/public/privcmd.h
45564 ===================================================================
45565 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45566 +++ head-2008-11-25/include/xen/public/privcmd.h 2007-06-12 13:14:19.000000000 +0200
45568 +/******************************************************************************
45571 + * Interface to /proc/xen/privcmd.
45573 + * Copyright (c) 2003-2005, K A Fraser
45575 + * This program is free software; you can redistribute it and/or
45576 + * modify it under the terms of the GNU General Public License version 2
45577 + * as published by the Free Software Foundation; or, when distributed
45578 + * separately from the Linux kernel or incorporated into other
45579 + * software packages, subject to the following license:
45581 + * Permission is hereby granted, free of charge, to any person obtaining a copy
45582 + * of this source file (the "Software"), to deal in the Software without
45583 + * restriction, including without limitation the rights to use, copy, modify,
45584 + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
45585 + * and to permit persons to whom the Software is furnished to do so, subject to
45586 + * the following conditions:
45588 + * The above copyright notice and this permission notice shall be included in
45589 + * all copies or substantial portions of the Software.
45591 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45592 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
45593 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
45594 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
45595 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45596 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
45597 + * IN THE SOFTWARE.
45600 +#ifndef __LINUX_PUBLIC_PRIVCMD_H__
45601 +#define __LINUX_PUBLIC_PRIVCMD_H__
45603 +#include <linux/types.h>
45609 +typedef struct privcmd_hypercall
45613 +} privcmd_hypercall_t;
45615 +typedef struct privcmd_mmap_entry {
45619 +} privcmd_mmap_entry_t;
45621 +typedef struct privcmd_mmap {
45623 + domid_t dom; /* target domain */
45624 + privcmd_mmap_entry_t __user *entry;
45627 +typedef struct privcmd_mmapbatch {
45628 + int num; /* number of pages to populate */
45629 + domid_t dom; /* target domain */
45630 + __u64 addr; /* virtual address */
45631 + xen_pfn_t __user *arr; /* array of mfns - top nibble set on err */
45632 +} privcmd_mmapbatch_t;
45635 + * @cmd: IOCTL_PRIVCMD_HYPERCALL
45636 + * @arg: &privcmd_hypercall_t
45637 + * Return: Value returned from execution of the specified hypercall.
45639 +#define IOCTL_PRIVCMD_HYPERCALL \
45640 + _IOC(_IOC_NONE, 'P', 0, sizeof(privcmd_hypercall_t))
45641 +#define IOCTL_PRIVCMD_MMAP \
45642 + _IOC(_IOC_NONE, 'P', 2, sizeof(privcmd_mmap_t))
45643 +#define IOCTL_PRIVCMD_MMAPBATCH \
45644 + _IOC(_IOC_NONE, 'P', 3, sizeof(privcmd_mmapbatch_t))
45646 +#endif /* __LINUX_PUBLIC_PRIVCMD_H__ */
45647 Index: head-2008-11-25/include/xen/xen_proc.h
45648 ===================================================================
45649 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45650 +++ head-2008-11-25/include/xen/xen_proc.h 2007-06-12 13:14:19.000000000 +0200
45653 +#ifndef __ASM_XEN_PROC_H__
45654 +#define __ASM_XEN_PROC_H__
45656 +#include <linux/proc_fs.h>
45658 +extern struct proc_dir_entry *create_xen_proc_entry(
45659 + const char *name, mode_t mode);
45660 +extern void remove_xen_proc_entry(
45661 + const char *name);
45663 +#endif /* __ASM_XEN_PROC_H__ */
45664 Index: head-2008-11-25/include/xen/xencons.h
45665 ===================================================================
45666 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45667 +++ head-2008-11-25/include/xen/xencons.h 2007-10-15 09:39:38.000000000 +0200
45669 +#ifndef __ASM_XENCONS_H__
45670 +#define __ASM_XENCONS_H__
45672 +struct dom0_vga_console_info;
45673 +void dom0_init_screen_info(const struct dom0_vga_console_info *, size_t);
45675 +void xencons_force_flush(void);
45676 +void xencons_resume(void);
45678 +/* Interrupt work hooks. Receive data, or kick data out. */
45679 +void xencons_rx(char *buf, unsigned len, struct pt_regs *regs);
45680 +void xencons_tx(void);
45682 +int xencons_ring_init(void);
45683 +int xencons_ring_send(const char *data, unsigned len);
45685 +#endif /* __ASM_XENCONS_H__ */
45686 Index: head-2008-11-25/include/xen/xenoprof.h
45687 ===================================================================
45688 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45689 +++ head-2008-11-25/include/xen/xenoprof.h 2007-06-12 13:14:19.000000000 +0200
45691 +/******************************************************************************
45694 + * Copyright (c) 2006 Isaku Yamahata <yamahata at valinux co jp>
45695 + * VA Linux Systems Japan K.K.
45697 + * This program is free software; you can redistribute it and/or modify
45698 + * it under the terms of the GNU General Public License as published by
45699 + * the Free Software Foundation; either version 2 of the License, or
45700 + * (at your option) any later version.
45702 + * This program is distributed in the hope that it will be useful,
45703 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
45704 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45705 + * GNU General Public License for more details.
45707 + * You should have received a copy of the GNU General Public License
45708 + * along with this program; if not, write to the Free Software
45709 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45713 +#ifndef __XEN_XENOPROF_H__
45714 +#define __XEN_XENOPROF_H__
45717 +#include <asm/xenoprof.h>
45719 +struct oprofile_operations;
45720 +int xenoprofile_init(struct oprofile_operations * ops);
45721 +void xenoprofile_exit(void);
45723 +struct xenoprof_shared_buffer {
45725 + struct xenoprof_arch_shared_buffer arch;
45728 +#define xenoprofile_init(ops) (-ENOSYS)
45729 +#define xenoprofile_exit() do { } while (0)
45731 +#endif /* CONFIG_XEN */
45732 +#endif /* __XEN_XENOPROF_H__ */
45733 Index: head-2008-11-25/lib/swiotlb-xen.c
45734 ===================================================================
45735 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45736 +++ head-2008-11-25/lib/swiotlb-xen.c 2008-09-15 13:40:15.000000000 +0200
45739 + * Dynamic DMA mapping support.
45741 + * This implementation is a fallback for platforms that do not support
45742 + * I/O TLBs (aka DMA address translation hardware).
45743 + * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com>
45744 + * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com>
45745 + * Copyright (C) 2000, 2003 Hewlett-Packard Co
45746 + * David Mosberger-Tang <davidm@hpl.hp.com>
45747 + * Copyright (C) 2005 Keir Fraser <keir@xensource.com>
45750 +#include <linux/cache.h>
45751 +#include <linux/mm.h>
45752 +#include <linux/module.h>
45753 +#include <linux/pci.h>
45754 +#include <linux/spinlock.h>
45755 +#include <linux/string.h>
45756 +#include <linux/types.h>
45757 +#include <linux/ctype.h>
45758 +#include <linux/init.h>
45759 +#include <linux/bootmem.h>
45760 +#include <linux/highmem.h>
45761 +#include <asm/io.h>
45762 +#include <asm/pci.h>
45763 +#include <asm/dma.h>
45764 +#include <asm/uaccess.h>
45765 +#include <xen/gnttab.h>
45766 +#include <xen/interface/memory.h>
45767 +#include <asm-i386/mach-xen/asm/gnttab_dma.h>
45770 +EXPORT_SYMBOL(swiotlb);
45772 +#define OFFSET(val,align) ((unsigned long)((val) & ( (align) - 1)))
45775 + * Maximum allowable number of contiguous slabs to map,
45776 + * must be a power of 2. What is the appropriate value ?
45777 + * The complexity of {map,unmap}_single is linearly dependent on this value.
45779 +#define IO_TLB_SEGSIZE 128
45782 + * log of the size of each IO TLB slab. The number of slabs is command line
45785 +#define IO_TLB_SHIFT 11
45787 +int swiotlb_force;
45789 +static char *iotlb_virt_start;
45790 +static unsigned long iotlb_nslabs;
45793 + * Used to do a quick range check in swiotlb_unmap_single and
45794 + * swiotlb_sync_single_*, to see if the memory was in fact allocated by this
45797 +static unsigned long iotlb_pfn_start, iotlb_pfn_end;
45799 +/* Does the given dma address reside within the swiotlb aperture? */
45800 +static inline int in_swiotlb_aperture(dma_addr_t dev_addr)
45802 + unsigned long pfn = mfn_to_local_pfn(dev_addr >> PAGE_SHIFT);
45803 + return (pfn_valid(pfn)
45804 + && (pfn >= iotlb_pfn_start)
45805 + && (pfn < iotlb_pfn_end));
45809 + * When the IOMMU overflows we return a fallback buffer. This sets the size.
45811 +static unsigned long io_tlb_overflow = 32*1024;
45813 +void *io_tlb_overflow_buffer;
45816 + * This is a free list describing the number of free entries available from
45819 +static unsigned int *io_tlb_list;
45820 +static unsigned int io_tlb_index;
45823 + * We need to save away the original address corresponding to a mapped entry
45824 + * for the sync operations.
45826 +static struct phys_addr {
45827 + struct page *page;
45828 + unsigned int offset;
45829 +} *io_tlb_orig_addr;
45832 + * Protect the above data structures in the map and unmap calls
45834 +static DEFINE_SPINLOCK(io_tlb_lock);
45836 +static unsigned int dma_bits;
45837 +static unsigned int __initdata max_dma_bits = 32;
45839 +setup_dma_bits(char *str)
45841 + max_dma_bits = simple_strtoul(str, NULL, 0);
45844 +__setup("dma_bits=", setup_dma_bits);
45847 +setup_io_tlb_npages(char *str)
45849 + /* Unlike ia64, the size is aperture in megabytes, not 'slabs'! */
45850 + if (isdigit(*str)) {
45851 + iotlb_nslabs = simple_strtoul(str, &str, 0) <<
45852 + (20 - IO_TLB_SHIFT);
45853 + iotlb_nslabs = ALIGN(iotlb_nslabs, IO_TLB_SEGSIZE);
45858 + * NB. 'force' enables the swiotlb, but doesn't force its use for
45859 + * every DMA like it does on native Linux. 'off' forcibly disables
45860 + * use of the swiotlb.
45862 + if (!strcmp(str, "force"))
45863 + swiotlb_force = 1;
45864 + else if (!strcmp(str, "off"))
45865 + swiotlb_force = -1;
45868 +__setup("swiotlb=", setup_io_tlb_npages);
45869 +/* make io_tlb_overflow tunable too? */
45872 + * Statically reserve bounce buffer space and initialize bounce buffer data
45873 + * structures for the software IO TLB used to implement the PCI DMA API.
45876 +swiotlb_init_with_default_size (size_t default_size)
45878 + unsigned long i, bytes;
45881 + if (!iotlb_nslabs) {
45882 + iotlb_nslabs = (default_size >> IO_TLB_SHIFT);
45883 + iotlb_nslabs = ALIGN(iotlb_nslabs, IO_TLB_SEGSIZE);
45886 + bytes = iotlb_nslabs * (1UL << IO_TLB_SHIFT);
45889 + * Get IO TLB memory from the low pages
45891 + iotlb_virt_start = alloc_bootmem_low_pages(bytes);
45892 + if (!iotlb_virt_start)
45893 + panic("Cannot allocate SWIOTLB buffer!\n");
45895 + dma_bits = get_order(IO_TLB_SEGSIZE << IO_TLB_SHIFT) + PAGE_SHIFT;
45896 + for (i = 0; i < iotlb_nslabs; i += IO_TLB_SEGSIZE) {
45898 + rc = xen_create_contiguous_region(
45899 + (unsigned long)iotlb_virt_start + (i << IO_TLB_SHIFT),
45900 + get_order(IO_TLB_SEGSIZE << IO_TLB_SHIFT),
45902 + } while (rc && dma_bits++ < max_dma_bits);
45905 + panic("No suitable physical memory available for SWIOTLB buffer!\n"
45906 + "Use dom0_mem Xen boot parameter to reserve\n"
45907 + "some DMA memory (e.g., dom0_mem=-128M).\n");
45908 + iotlb_nslabs = i;
45909 + i <<= IO_TLB_SHIFT;
45910 + free_bootmem(__pa(iotlb_virt_start + i), bytes - i);
45912 + for (dma_bits = 0; i > 0; i -= IO_TLB_SEGSIZE << IO_TLB_SHIFT) {
45913 + unsigned int bits = fls64(virt_to_bus(iotlb_virt_start + i - 1));
45915 + if (bits > dma_bits)
45923 + * Allocate and initialize the free list array. This array is used
45924 + * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE.
45926 + io_tlb_list = alloc_bootmem(iotlb_nslabs * sizeof(int));
45927 + for (i = 0; i < iotlb_nslabs; i++)
45928 + io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
45929 + io_tlb_index = 0;
45930 + io_tlb_orig_addr = alloc_bootmem(
45931 + iotlb_nslabs * sizeof(*io_tlb_orig_addr));
45934 + * Get the overflow emergency buffer
45936 + io_tlb_overflow_buffer = alloc_bootmem_low(io_tlb_overflow);
45937 + if (!io_tlb_overflow_buffer)
45938 + panic("Cannot allocate SWIOTLB overflow buffer!\n");
45941 + rc = xen_create_contiguous_region(
45942 + (unsigned long)io_tlb_overflow_buffer,
45943 + get_order(io_tlb_overflow),
45945 + } while (rc && dma_bits++ < max_dma_bits);
45947 + panic("No suitable physical memory available for SWIOTLB overflow buffer!\n");
45949 + iotlb_pfn_start = __pa(iotlb_virt_start) >> PAGE_SHIFT;
45950 + iotlb_pfn_end = iotlb_pfn_start + (bytes >> PAGE_SHIFT);
45952 + printk(KERN_INFO "Software IO TLB enabled: \n"
45953 + " Aperture: %lu megabytes\n"
45954 + " Kernel range: %p - %p\n"
45955 + " Address size: %u bits\n",
45957 + iotlb_virt_start, iotlb_virt_start + bytes,
45962 +swiotlb_init(void)
45965 + size_t defsz = 64 * (1 << 20); /* 64MB default size */
45967 + if (swiotlb_force == 1) {
45969 + } else if ((swiotlb_force != -1) &&
45970 + is_running_on_xen() &&
45971 + is_initial_xendomain()) {
45972 + /* Domain 0 always has a swiotlb. */
45973 + ram_end = HYPERVISOR_memory_op(XENMEM_maximum_ram_page, NULL);
45974 + if (ram_end <= 0x7ffff)
45975 + defsz = 2 * (1 << 20); /* 2MB on <2GB on systems. */
45980 + swiotlb_init_with_default_size(defsz);
45982 + printk(KERN_INFO "Software IO TLB disabled\n");
45986 + * We use __copy_to_user_inatomic to transfer to the host buffer because the
45987 + * buffer may be mapped read-only (e.g, in blkback driver) but lower-level
45988 + * drivers map the buffer for DMA_BIDIRECTIONAL access. This causes an
45989 + * unnecessary copy from the aperture to the host buffer, and a page fault.
45992 +__sync_single(struct phys_addr buffer, char *dma_addr, size_t size, int dir)
45994 + if (PageHighMem(buffer.page)) {
45995 + size_t len, bytes;
45996 + char *dev, *host, *kmp;
45998 + while (len != 0) {
45999 + unsigned long flags;
46001 + if (((bytes = len) + buffer.offset) > PAGE_SIZE)
46002 + bytes = PAGE_SIZE - buffer.offset;
46003 + local_irq_save(flags); /* protects KM_BOUNCE_READ */
46004 + kmp = kmap_atomic(buffer.page, KM_BOUNCE_READ);
46005 + dev = dma_addr + size - len;
46006 + host = kmp + buffer.offset;
46007 + if (dir == DMA_FROM_DEVICE) {
46008 + if (__copy_to_user_inatomic(host, dev, bytes))
46009 + /* inaccessible */;
46011 + memcpy(dev, host, bytes);
46012 + kunmap_atomic(kmp, KM_BOUNCE_READ);
46013 + local_irq_restore(flags);
46016 + buffer.offset = 0;
46019 + char *host = (char *)phys_to_virt(
46020 + page_to_pseudophys(buffer.page)) + buffer.offset;
46021 + if (dir == DMA_FROM_DEVICE) {
46022 + if (__copy_to_user_inatomic(host, dma_addr, size))
46023 + /* inaccessible */;
46024 + } else if (dir == DMA_TO_DEVICE)
46025 + memcpy(dma_addr, host, size);
46030 + * Allocates bounce buffer and returns its kernel virtual address.
46033 +map_single(struct device *hwdev, struct phys_addr buffer, size_t size, int dir)
46035 + unsigned long flags;
46037 + unsigned int nslots, stride, index, wrap;
46038 + struct phys_addr slot_buf;
46042 + * For mappings greater than a page, we limit the stride (and
46043 + * hence alignment) to a page size.
46045 + nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
46046 + if (size > PAGE_SIZE)
46047 + stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT));
46054 + * Find suitable number of IO TLB entries size that will fit this
46055 + * request and allocate a buffer from that IO TLB pool.
46057 + spin_lock_irqsave(&io_tlb_lock, flags);
46059 + wrap = index = ALIGN(io_tlb_index, stride);
46061 + if (index >= iotlb_nslabs)
46062 + wrap = index = 0;
46066 + * If we find a slot that indicates we have 'nslots'
46067 + * number of contiguous buffers, we allocate the
46068 + * buffers from that slot and mark the entries as '0'
46069 + * indicating unavailable.
46071 + if (io_tlb_list[index] >= nslots) {
46074 + for (i = index; i < (int)(index + nslots); i++)
46075 + io_tlb_list[i] = 0;
46076 + for (i = index - 1;
46077 + (OFFSET(i, IO_TLB_SEGSIZE) !=
46078 + IO_TLB_SEGSIZE -1) && io_tlb_list[i];
46080 + io_tlb_list[i] = ++count;
46081 + dma_addr = iotlb_virt_start +
46082 + (index << IO_TLB_SHIFT);
46085 + * Update the indices to avoid searching in
46086 + * the next round.
46089 + ((index + nslots) < iotlb_nslabs
46090 + ? (index + nslots) : 0);
46095 + if (index >= iotlb_nslabs)
46097 + } while (index != wrap);
46099 + spin_unlock_irqrestore(&io_tlb_lock, flags);
46103 + spin_unlock_irqrestore(&io_tlb_lock, flags);
46106 + * Save away the mapping from the original address to the DMA address.
46107 + * This is needed when we sync the memory. Then we sync the buffer if
46110 + slot_buf = buffer;
46111 + for (i = 0; i < nslots; i++) {
46112 + slot_buf.page += slot_buf.offset >> PAGE_SHIFT;
46113 + slot_buf.offset &= PAGE_SIZE - 1;
46114 + io_tlb_orig_addr[index+i] = slot_buf;
46115 + slot_buf.offset += 1 << IO_TLB_SHIFT;
46117 + if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL))
46118 + __sync_single(buffer, dma_addr, size, DMA_TO_DEVICE);
46123 +static struct phys_addr dma_addr_to_phys_addr(char *dma_addr)
46125 + int index = (dma_addr - iotlb_virt_start) >> IO_TLB_SHIFT;
46126 + struct phys_addr buffer = io_tlb_orig_addr[index];
46127 + buffer.offset += (long)dma_addr & ((1 << IO_TLB_SHIFT) - 1);
46128 + buffer.page += buffer.offset >> PAGE_SHIFT;
46129 + buffer.offset &= PAGE_SIZE - 1;
46134 + * dma_addr is the kernel virtual address of the bounce buffer to unmap.
46137 +unmap_single(struct device *hwdev, char *dma_addr, size_t size, int dir)
46139 + unsigned long flags;
46140 + int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
46141 + int index = (dma_addr - iotlb_virt_start) >> IO_TLB_SHIFT;
46142 + struct phys_addr buffer = dma_addr_to_phys_addr(dma_addr);
46145 + * First, sync the memory before unmapping the entry
46147 + if ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))
46148 + __sync_single(buffer, dma_addr, size, DMA_FROM_DEVICE);
46151 + * Return the buffer to the free list by setting the corresponding
46152 + * entries to indicate the number of contigous entries available.
46153 + * While returning the entries to the free list, we merge the entries
46154 + * with slots below and above the pool being returned.
46156 + spin_lock_irqsave(&io_tlb_lock, flags);
46158 + count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ?
46159 + io_tlb_list[index + nslots] : 0);
46161 + * Step 1: return the slots to the free list, merging the
46162 + * slots with superceeding slots
46164 + for (i = index + nslots - 1; i >= index; i--)
46165 + io_tlb_list[i] = ++count;
46167 + * Step 2: merge the returned slots with the preceding slots,
46168 + * if available (non zero)
46170 + for (i = index - 1;
46171 + (OFFSET(i, IO_TLB_SEGSIZE) !=
46172 + IO_TLB_SEGSIZE -1) && io_tlb_list[i];
46174 + io_tlb_list[i] = ++count;
46176 + spin_unlock_irqrestore(&io_tlb_lock, flags);
46180 +sync_single(struct device *hwdev, char *dma_addr, size_t size, int dir)
46182 + struct phys_addr buffer = dma_addr_to_phys_addr(dma_addr);
46183 + BUG_ON((dir != DMA_FROM_DEVICE) && (dir != DMA_TO_DEVICE));
46184 + __sync_single(buffer, dma_addr, size, dir);
46188 +swiotlb_full(struct device *dev, size_t size, int dir, int do_panic)
46191 + * Ran out of IOMMU space for this operation. This is very bad.
46192 + * Unfortunately the drivers cannot handle this operation properly.
46193 + * unless they check for pci_dma_mapping_error (most don't)
46194 + * When the mapping is small enough return a static buffer to limit
46195 + * the damage, or panic when the transfer is too big.
46197 + printk(KERN_ERR "PCI-DMA: Out of SW-IOMMU space for %lu bytes at "
46198 + "device %s\n", (unsigned long)size, dev ? dev->bus_id : "?");
46200 + if (size > io_tlb_overflow && do_panic) {
46201 + if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
46202 + panic("PCI-DMA: Memory would be corrupted\n");
46203 + if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
46204 + panic("PCI-DMA: Random memory would be DMAed\n");
46209 + * Map a single buffer of the indicated size for DMA in streaming mode. The
46210 + * PCI address to use is returned.
46212 + * Once the device is given the dma address, the device owns this memory until
46213 + * either swiotlb_unmap_single or swiotlb_dma_sync_single is performed.
46216 +swiotlb_map_single(struct device *hwdev, void *ptr, size_t size, int dir)
46218 + dma_addr_t dev_addr = gnttab_dma_map_page(virt_to_page(ptr)) +
46219 + offset_in_page(ptr);
46221 + struct phys_addr buffer;
46223 + BUG_ON(dir == DMA_NONE);
46226 + * If the pointer passed in happens to be in the device's DMA window,
46227 + * we can safely return the device addr and not worry about bounce
46230 + if (!range_straddles_page_boundary(__pa(ptr), size) &&
46231 + !address_needs_mapping(hwdev, dev_addr))
46235 + * Oh well, have to allocate and map a bounce buffer.
46237 + gnttab_dma_unmap_page(dev_addr);
46238 + buffer.page = virt_to_page(ptr);
46239 + buffer.offset = (unsigned long)ptr & ~PAGE_MASK;
46240 + map = map_single(hwdev, buffer, size, dir);
46242 + swiotlb_full(hwdev, size, dir, 1);
46243 + map = io_tlb_overflow_buffer;
46246 + dev_addr = virt_to_bus(map);
46251 + * Unmap a single streaming mode DMA translation. The dma_addr and size must
46252 + * match what was provided for in a previous swiotlb_map_single call. All
46253 + * other usages are undefined.
46255 + * After this call, reads by the cpu to the buffer are guaranteed to see
46256 + * whatever the device wrote there.
46259 +swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr, size_t size,
46262 + BUG_ON(dir == DMA_NONE);
46263 + if (in_swiotlb_aperture(dev_addr))
46264 + unmap_single(hwdev, bus_to_virt(dev_addr), size, dir);
46266 + gnttab_dma_unmap_page(dev_addr);
46270 + * Make physical memory consistent for a single streaming mode DMA translation
46271 + * after a transfer.
46273 + * If you perform a swiotlb_map_single() but wish to interrogate the buffer
46274 + * using the cpu, yet do not wish to teardown the PCI dma mapping, you must
46275 + * call this function before doing so. At the next point you give the PCI dma
46276 + * address back to the card, you must first perform a
46277 + * swiotlb_dma_sync_for_device, and then the device again owns the buffer
46280 +swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
46281 + size_t size, int dir)
46283 + BUG_ON(dir == DMA_NONE);
46284 + if (in_swiotlb_aperture(dev_addr))
46285 + sync_single(hwdev, bus_to_virt(dev_addr), size, dir);
46289 +swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr,
46290 + size_t size, int dir)
46292 + BUG_ON(dir == DMA_NONE);
46293 + if (in_swiotlb_aperture(dev_addr))
46294 + sync_single(hwdev, bus_to_virt(dev_addr), size, dir);
46298 + * Map a set of buffers described by scatterlist in streaming mode for DMA.
46299 + * This is the scatter-gather version of the above swiotlb_map_single
46300 + * interface. Here the scatter gather list elements are each tagged with the
46301 + * appropriate dma address and length. They are obtained via
46302 + * sg_dma_{address,length}(SG).
46304 + * NOTE: An implementation may be able to use a smaller number of
46305 + * DMA address/length pairs than there are SG table elements.
46306 + * (for example via virtual mapping capabilities)
46307 + * The routine returns the number of addr/length pairs actually
46308 + * used, at most nents.
46310 + * Device ownership issues as mentioned above for swiotlb_map_single are the
46314 +swiotlb_map_sg(struct device *hwdev, struct scatterlist *sg, int nelems,
46317 + struct phys_addr buffer;
46318 + dma_addr_t dev_addr;
46322 + BUG_ON(dir == DMA_NONE);
46324 + for (i = 0; i < nelems; i++, sg++) {
46325 + dev_addr = gnttab_dma_map_page(sg->page) + sg->offset;
46327 + if (range_straddles_page_boundary(page_to_pseudophys(sg->page)
46328 + + sg->offset, sg->length)
46329 + || address_needs_mapping(hwdev, dev_addr)) {
46330 + gnttab_dma_unmap_page(dev_addr);
46331 + buffer.page = sg->page;
46332 + buffer.offset = sg->offset;
46333 + map = map_single(hwdev, buffer, sg->length, dir);
46335 + /* Don't panic here, we expect map_sg users
46336 + to do proper error handling. */
46337 + swiotlb_full(hwdev, sg->length, dir, 0);
46338 + swiotlb_unmap_sg(hwdev, sg - i, i, dir);
46339 + sg[0].dma_length = 0;
46342 + sg->dma_address = (dma_addr_t)virt_to_bus(map);
46344 + sg->dma_address = dev_addr;
46345 + sg->dma_length = sg->length;
46351 + * Unmap a set of streaming mode DMA translations. Again, cpu read rules
46352 + * concerning calls here are the same as for swiotlb_unmap_single() above.
46355 +swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nelems,
46360 + BUG_ON(dir == DMA_NONE);
46362 + for (i = 0; i < nelems; i++, sg++)
46363 + if (in_swiotlb_aperture(sg->dma_address))
46364 + unmap_single(hwdev,
46365 + (void *)bus_to_virt(sg->dma_address),
46366 + sg->dma_length, dir);
46368 + gnttab_dma_unmap_page(sg->dma_address);
46372 + * Make physical memory consistent for a set of streaming mode DMA translations
46373 + * after a transfer.
46375 + * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules
46379 +swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
46380 + int nelems, int dir)
46384 + BUG_ON(dir == DMA_NONE);
46386 + for (i = 0; i < nelems; i++, sg++)
46387 + if (in_swiotlb_aperture(sg->dma_address))
46388 + sync_single(hwdev,
46389 + (void *)bus_to_virt(sg->dma_address),
46390 + sg->dma_length, dir);
46394 +swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
46395 + int nelems, int dir)
46399 + BUG_ON(dir == DMA_NONE);
46401 + for (i = 0; i < nelems; i++, sg++)
46402 + if (in_swiotlb_aperture(sg->dma_address))
46403 + sync_single(hwdev,
46404 + (void *)bus_to_virt(sg->dma_address),
46405 + sg->dma_length, dir);
46408 +#ifdef CONFIG_HIGHMEM
46411 +swiotlb_map_page(struct device *hwdev, struct page *page,
46412 + unsigned long offset, size_t size,
46413 + enum dma_data_direction direction)
46415 + struct phys_addr buffer;
46416 + dma_addr_t dev_addr;
46419 + dev_addr = gnttab_dma_map_page(page) + offset;
46420 + if (address_needs_mapping(hwdev, dev_addr)) {
46421 + gnttab_dma_unmap_page(dev_addr);
46422 + buffer.page = page;
46423 + buffer.offset = offset;
46424 + map = map_single(hwdev, buffer, size, direction);
46426 + swiotlb_full(hwdev, size, direction, 1);
46427 + map = io_tlb_overflow_buffer;
46429 + dev_addr = (dma_addr_t)virt_to_bus(map);
46436 +swiotlb_unmap_page(struct device *hwdev, dma_addr_t dma_address,
46437 + size_t size, enum dma_data_direction direction)
46439 + BUG_ON(direction == DMA_NONE);
46440 + if (in_swiotlb_aperture(dma_address))
46441 + unmap_single(hwdev, bus_to_virt(dma_address), size, direction);
46443 + gnttab_dma_unmap_page(dma_address);
46449 +swiotlb_dma_mapping_error(dma_addr_t dma_addr)
46451 + return (dma_addr == virt_to_bus(io_tlb_overflow_buffer));
46455 + * Return whether the given PCI device DMA address mask can be supported
46456 + * properly. For example, if your device can only drive the low 24-bits
46457 + * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
46461 +swiotlb_dma_supported (struct device *hwdev, u64 mask)
46463 + return (mask >= ((1UL << dma_bits) - 1));
46466 +EXPORT_SYMBOL(swiotlb_init);
46467 +EXPORT_SYMBOL(swiotlb_map_single);
46468 +EXPORT_SYMBOL(swiotlb_unmap_single);
46469 +EXPORT_SYMBOL(swiotlb_map_sg);
46470 +EXPORT_SYMBOL(swiotlb_unmap_sg);
46471 +EXPORT_SYMBOL(swiotlb_sync_single_for_cpu);
46472 +EXPORT_SYMBOL(swiotlb_sync_single_for_device);
46473 +EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu);
46474 +EXPORT_SYMBOL(swiotlb_sync_sg_for_device);
46475 +EXPORT_SYMBOL(swiotlb_dma_mapping_error);
46476 +EXPORT_SYMBOL(swiotlb_dma_supported);
46477 Index: head-2008-11-25/scripts/Makefile.xen.awk
46478 ===================================================================
46479 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
46480 +++ head-2008-11-25/scripts/Makefile.xen.awk 2007-08-06 15:10:49.000000000 +0200
46486 +/^[[:space:]]*#/ {
46490 +/^[[:space:]]*$/ {
46497 +/:[[:space:]]*%\.[cS][[:space:]]/ {
46498 + line = gensub(/%.([cS])/, "%-xen.\\1", "g", $0)
46499 + line = gensub(/(single-used-m)/, "xen-\\1", "g", line)