1 From: Jim Paris <jim@jtan.com>
2 Subject: Add ps3vram driver, which exposes unused video RAM on the PS3 as a MTD
4 Add ps3vram driver, which exposes unused video RAM on the PS3 as a MTD
5 device suitable for storage or swap. Fast data transfer is achieved
6 using a local cache in system RAM and DMA transfers via the GPU.
8 Signed-off-by: Vivien Chappelier <vivien.chappelier@free.fr>
9 CC: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
10 CC: Geoff Levand <geoffrey.levand@am.sony.com>
11 Signed-off-by: Jim Paris <jim@jtan.com>
12 Signed-off-by: Stefan Assmann <sassmann@suse.de>
14 This version has been updated to work with PS3 firmware 2.50, and
17 Please consider for 2.6.29.
20 arch/powerpc/include/asm/ps3.h | 1
21 arch/powerpc/platforms/ps3/device-init.c | 37 +
22 drivers/mtd/devices/Kconfig | 7
23 drivers/mtd/devices/Makefile | 1
25 arch/powerpc/include/asm/ps3.h | 1
26 arch/powerpc/platforms/ps3/device-init.c | 37 +
27 drivers/mtd/devices/Kconfig | 7
28 drivers/mtd/devices/Makefile | 1
29 drivers/mtd/devices/ps3vram.c | 776 +++++++++++++++++++++++++++++++
30 6 files changed, 828 insertions(+)
31 create mode 100644 drivers/mtd/devices/ps3vram.c
33 --- a/arch/powerpc/include/asm/ps3.h
34 +++ b/arch/powerpc/include/asm/ps3.h
35 @@ -340,6 +340,7 @@ enum ps3_system_bus_device_type {
36 enum ps3_match_sub_id {
37 /* for PS3_MATCH_ID_GRAPHICS */
38 PS3_MATCH_SUB_ID_FB = 1,
39 + PS3_MATCH_SUB_ID_RAMDISK = 2,
43 --- a/arch/powerpc/platforms/ps3/device-init.c
44 +++ b/arch/powerpc/platforms/ps3/device-init.c
45 @@ -499,6 +499,41 @@ static int __init ps3_register_graphics_
49 +static int __init ps3_register_ramdisk_device(void)
53 + struct ps3_system_bus_device dev;
56 + pr_debug(" -> %s:%d\n", __func__, __LINE__);
58 + p = kzalloc(sizeof(struct layout), GFP_KERNEL);
63 + p->dev.match_id = PS3_MATCH_ID_GRAPHICS;
64 + p->dev.match_sub_id = PS3_MATCH_SUB_ID_RAMDISK;
65 + p->dev.dev_type = PS3_DEVICE_TYPE_IOC0;
67 + result = ps3_system_bus_device_register(&p->dev);
70 + pr_debug("%s:%d ps3_system_bus_device_register failed\n",
71 + __func__, __LINE__);
72 + goto fail_device_register;
75 + pr_debug(" <- %s:%d\n", __func__, __LINE__);
78 +fail_device_register:
80 + pr_debug(" <- %s:%d failed\n", __func__, __LINE__);
85 * ps3_setup_dynamic_device - Setup a dynamic device from the repository
87 @@ -927,6 +962,8 @@ static int __init ps3_register_devices(v
89 ps3_register_lpm_devices();
91 + ps3_register_ramdisk_device();
93 pr_debug(" <- %s:%d\n", __func__, __LINE__);
96 --- a/drivers/mtd/devices/Kconfig
97 +++ b/drivers/mtd/devices/Kconfig
98 @@ -99,6 +99,13 @@ config MTD_PHRAM
99 doesn't have access to, memory beyond the mem=xxx limit, nvram,
100 memory on the video card, etc...
103 + tristate "PS3 video RAM"
106 + This driver allows you to use excess PS3 video RAM as volatile
107 + storage or system swap.
110 tristate "28F160xx flash driver for LART"
111 depends on SA1100_LART
112 --- a/drivers/mtd/devices/Makefile
113 +++ b/drivers/mtd/devices/Makefile
114 @@ -16,3 +16,4 @@ obj-$(CONFIG_MTD_LART) += lart.o
115 obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
116 obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
117 obj-$(CONFIG_MTD_M25P80) += m25p80.o
118 +obj-$(CONFIG_MTD_PS3VRAM) += ps3vram.o
120 +++ b/drivers/mtd/devices/ps3vram.c
123 + * ps3vram - Use extra PS3 video ram as MTD block device.
125 + * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
126 + * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
129 +#include <linux/io.h>
130 +#include <linux/init.h>
131 +#include <linux/kernel.h>
132 +#include <linux/list.h>
133 +#include <linux/module.h>
134 +#include <linux/moduleparam.h>
135 +#include <linux/slab.h>
136 +#include <linux/version.h>
137 +#include <linux/gfp.h>
138 +#include <linux/delay.h>
139 +#include <linux/mtd/mtd.h>
141 +#include <asm/lv1call.h>
142 +#include <asm/ps3.h>
144 +#define DEVICE_NAME "ps3vram"
146 +#define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MB aligned) */
147 +#define XDR_IOIF 0x0c000000
149 +#define FIFO_BASE XDR_IOIF
150 +#define FIFO_SIZE (64 * 1024)
152 +#define DMA_PAGE_SIZE (4 * 1024)
154 +#define CACHE_PAGE_SIZE (256 * 1024)
155 +#define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
157 +#define CACHE_OFFSET CACHE_PAGE_SIZE
158 +#define FIFO_OFFSET 0
160 +#define CTRL_PUT 0x10
161 +#define CTRL_GET 0x11
162 +#define CTRL_TOP 0x15
164 +#define UPLOAD_SUBCH 1
165 +#define DOWNLOAD_SUBCH 2
167 +#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
168 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
170 +#define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
172 +struct mtd_info ps3vram_mtd;
174 +#define CACHE_PAGE_PRESENT 1
175 +#define CACHE_PAGE_DIRTY 2
177 +#define dbg(fmt, args...) \
178 + pr_debug("%s:%d " fmt "\n", __func__, __LINE__, ## args)
180 +struct ps3vram_tag {
181 + unsigned int address;
182 + unsigned int flags;
185 +struct ps3vram_cache {
186 + unsigned int page_count;
187 + unsigned int page_size;
188 + struct ps3vram_tag *tags;
191 +struct ps3vram_priv {
192 + uint64_t memory_handle;
193 + uint64_t context_handle;
199 + uint32_t *fifo_base;
200 + uint32_t *fifo_ptr;
202 + struct ps3vram_cache cache;
204 + /* Used to serialize cache/DMA operations */
208 +#define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
209 +#define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
210 +#define DMA_NOTIFIER_SIZE 0x40
212 +#define NUM_NOTIFIERS 16
214 +#define NOTIFIER 7 /* notifier used for completion report */
216 +/* A trailing '-' means to subtract off ps3fb_videomemory.size */
217 +char *size = "256M-";
218 +module_param(size, charp, 0);
219 +MODULE_PARM_DESC(size, "memory size");
221 +static inline uint32_t *ps3vram_get_notifier(uint32_t *reports, int notifier)
223 + return (void *) reports +
224 + DMA_NOTIFIER_OFFSET_BASE +
225 + DMA_NOTIFIER_SIZE * notifier;
228 +static void ps3vram_notifier_reset(struct mtd_info *mtd)
231 + struct ps3vram_priv *priv = mtd->priv;
232 + uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
233 + for (i = 0; i < 4; i++)
234 + notify[i] = 0xffffffff;
237 +static int ps3vram_notifier_wait(struct mtd_info *mtd, int timeout_ms)
239 + struct ps3vram_priv *priv = mtd->priv;
240 + uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
242 + timeout_ms *= 1000;
245 + if (notify[3] == 0)
250 + } while (timeout_ms--);
255 +static void ps3vram_dump_ring(struct mtd_info *mtd)
257 + struct ps3vram_priv *priv = mtd->priv;
260 + pr_info("PUT = %08x GET = %08x\n", priv->ctrl[CTRL_PUT],
261 + priv->ctrl[CTRL_GET]);
262 + for (fifo = priv->fifo_base; fifo < priv->fifo_ptr; fifo++)
263 + pr_info("%p: %08x\n", fifo, *fifo);
266 +static void ps3vram_dump_reports(struct mtd_info *mtd)
268 + struct ps3vram_priv *priv = mtd->priv;
271 + for (i = 0; i < NUM_NOTIFIERS; i++) {
272 + uint32_t *n = ps3vram_get_notifier(priv->reports, i);
273 + pr_info("%p: %08x\n", n, *n);
277 +static void ps3vram_init_ring(struct mtd_info *mtd)
279 + struct ps3vram_priv *priv = mtd->priv;
281 + priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
282 + priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
285 +static int ps3vram_wait_ring(struct mtd_info *mtd, int timeout)
287 + struct ps3vram_priv *priv = mtd->priv;
289 + /* wait until setup commands are processed */
291 + while (--timeout) {
292 + if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
296 + if (timeout == 0) {
297 + pr_err("FIFO timeout (%08x/%08x/%08x)\n", priv->ctrl[CTRL_PUT],
298 + priv->ctrl[CTRL_GET], priv->ctrl[CTRL_TOP]);
305 +static inline void ps3vram_out_ring(struct ps3vram_priv *priv, uint32_t data)
307 + *(priv->fifo_ptr)++ = data;
310 +static inline void ps3vram_begin_ring(struct ps3vram_priv *priv, uint32_t chan,
311 + uint32_t tag, uint32_t size)
313 + ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
316 +static void ps3vram_rewind_ring(struct mtd_info *mtd)
318 + struct ps3vram_priv *priv = mtd->priv;
321 + ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
323 + priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
325 + /* asking the HV for a blit will kick the fifo */
326 + status = lv1_gpu_context_attribute(priv->context_handle,
327 + L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
330 + pr_err("ps3vram: lv1_gpu_context_attribute FB_BLIT failed\n");
332 + priv->fifo_ptr = priv->fifo_base;
335 +static void ps3vram_fire_ring(struct mtd_info *mtd)
337 + struct ps3vram_priv *priv = mtd->priv;
340 + mutex_lock(&ps3_gpu_mutex);
342 + priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
343 + (priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t);
345 + /* asking the HV for a blit will kick the fifo */
346 + status = lv1_gpu_context_attribute(priv->context_handle,
347 + L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
350 + pr_err("ps3vram: lv1_gpu_context_attribute FB_BLIT failed\n");
352 + if ((priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t) >
353 + FIFO_SIZE - 1024) {
354 + dbg("fifo full, rewinding");
355 + ps3vram_wait_ring(mtd, 200);
356 + ps3vram_rewind_ring(mtd);
359 + mutex_unlock(&ps3_gpu_mutex);
362 +static void ps3vram_bind(struct mtd_info *mtd)
364 + struct ps3vram_priv *priv = mtd->priv;
366 + ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
367 + ps3vram_out_ring(priv, 0x31337303);
368 + ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
369 + ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
370 + ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
371 + ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
373 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
374 + ps3vram_out_ring(priv, 0x3137c0de);
375 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
376 + ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
377 + ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
378 + ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
380 + ps3vram_fire_ring(mtd);
383 +static int ps3vram_upload(struct mtd_info *mtd, unsigned int src_offset,
384 + unsigned int dst_offset, int len, int count)
386 + struct ps3vram_priv *priv = mtd->priv;
388 + ps3vram_begin_ring(priv, UPLOAD_SUBCH,
389 + NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
390 + ps3vram_out_ring(priv, XDR_IOIF + src_offset);
391 + ps3vram_out_ring(priv, dst_offset);
392 + ps3vram_out_ring(priv, len);
393 + ps3vram_out_ring(priv, len);
394 + ps3vram_out_ring(priv, len);
395 + ps3vram_out_ring(priv, count);
396 + ps3vram_out_ring(priv, (1 << 8) | 1);
397 + ps3vram_out_ring(priv, 0);
399 + ps3vram_notifier_reset(mtd);
400 + ps3vram_begin_ring(priv, UPLOAD_SUBCH,
401 + NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
402 + ps3vram_out_ring(priv, 0);
403 + ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
404 + ps3vram_out_ring(priv, 0);
405 + ps3vram_fire_ring(mtd);
406 + if (ps3vram_notifier_wait(mtd, 200) < 0) {
407 + pr_err("notifier timeout\n");
408 + ps3vram_dump_ring(mtd);
409 + ps3vram_dump_reports(mtd);
416 +static int ps3vram_download(struct mtd_info *mtd, unsigned int src_offset,
417 + unsigned int dst_offset, int len, int count)
419 + struct ps3vram_priv *priv = mtd->priv;
421 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
422 + NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
423 + ps3vram_out_ring(priv, src_offset);
424 + ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
425 + ps3vram_out_ring(priv, len);
426 + ps3vram_out_ring(priv, len);
427 + ps3vram_out_ring(priv, len);
428 + ps3vram_out_ring(priv, count);
429 + ps3vram_out_ring(priv, (1 << 8) | 1);
430 + ps3vram_out_ring(priv, 0);
432 + ps3vram_notifier_reset(mtd);
433 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
434 + NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
435 + ps3vram_out_ring(priv, 0);
436 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
437 + ps3vram_out_ring(priv, 0);
438 + ps3vram_fire_ring(mtd);
439 + if (ps3vram_notifier_wait(mtd, 200) < 0) {
440 + pr_err("notifier timeout\n");
441 + ps3vram_dump_ring(mtd);
442 + ps3vram_dump_reports(mtd);
449 +static void ps3vram_cache_evict(struct mtd_info *mtd, int entry)
451 + struct ps3vram_priv *priv = mtd->priv;
452 + struct ps3vram_cache *cache = &priv->cache;
454 + if (cache->tags[entry].flags & CACHE_PAGE_DIRTY) {
455 + dbg("flushing %d : 0x%08x", entry, cache->tags[entry].address);
456 + if (ps3vram_upload(mtd,
457 + CACHE_OFFSET + entry * cache->page_size,
458 + cache->tags[entry].address,
460 + cache->page_size / DMA_PAGE_SIZE) < 0) {
461 + pr_err("failed to upload from 0x%x to 0x%x size 0x%x\n",
462 + entry * cache->page_size,
463 + cache->tags[entry].address,
466 + cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
470 +static void ps3vram_cache_load(struct mtd_info *mtd, int entry,
471 + unsigned int address)
473 + struct ps3vram_priv *priv = mtd->priv;
474 + struct ps3vram_cache *cache = &priv->cache;
476 + dbg("fetching %d : 0x%08x", entry, address);
477 + if (ps3vram_download(mtd,
479 + CACHE_OFFSET + entry * cache->page_size,
481 + cache->page_size / DMA_PAGE_SIZE) < 0) {
482 + pr_err("failed to download from 0x%x to 0x%x size 0x%x\n",
484 + entry * cache->page_size,
488 + cache->tags[entry].address = address;
489 + cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
493 +static void ps3vram_cache_flush(struct mtd_info *mtd)
495 + struct ps3vram_priv *priv = mtd->priv;
496 + struct ps3vram_cache *cache = &priv->cache;
500 + for (i = 0; i < cache->page_count; i++) {
501 + ps3vram_cache_evict(mtd, i);
502 + cache->tags[i].flags = 0;
506 +static unsigned int ps3vram_cache_match(struct mtd_info *mtd, loff_t address)
508 + struct ps3vram_priv *priv = mtd->priv;
509 + struct ps3vram_cache *cache = &priv->cache;
511 + unsigned int offset;
513 + static int counter;
515 + offset = (unsigned int) (address & (cache->page_size - 1));
516 + base = (unsigned int) (address - offset);
518 + /* fully associative check */
519 + for (i = 0; i < cache->page_count; i++) {
520 + if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
521 + cache->tags[i].address == base) {
522 + dbg("found entry %d : 0x%08x",
523 + i, cache->tags[i].address);
528 + /* choose a random entry */
529 + i = (jiffies + (counter++)) % cache->page_count;
530 + dbg("using cache entry %d", i);
532 + ps3vram_cache_evict(mtd, i);
533 + ps3vram_cache_load(mtd, i, base);
538 +static int ps3vram_cache_init(struct mtd_info *mtd)
540 + struct ps3vram_priv *priv = mtd->priv;
542 + pr_info("creating cache: %d entries, %d bytes pages\n",
543 + CACHE_PAGE_COUNT, CACHE_PAGE_SIZE);
545 + priv->cache.page_count = CACHE_PAGE_COUNT;
546 + priv->cache.page_size = CACHE_PAGE_SIZE;
547 + priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
548 + CACHE_PAGE_COUNT, GFP_KERNEL);
549 + if (priv->cache.tags == NULL) {
550 + pr_err("could not allocate cache tags\n");
557 +static void ps3vram_cache_cleanup(struct mtd_info *mtd)
559 + struct ps3vram_priv *priv = mtd->priv;
561 + ps3vram_cache_flush(mtd);
562 + kfree(priv->cache.tags);
565 +static int ps3vram_erase(struct mtd_info *mtd, struct erase_info *instr)
567 + struct ps3vram_priv *priv = mtd->priv;
569 + if (instr->addr + instr->len > mtd->size)
572 + mutex_lock(&priv->lock);
574 + ps3vram_cache_flush(mtd);
576 + /* Set bytes to 0xFF */
577 + memset(priv->base + instr->addr, 0xFF, instr->len);
579 + mutex_unlock(&priv->lock);
581 + instr->state = MTD_ERASE_DONE;
582 + mtd_erase_callback(instr);
588 +static int ps3vram_read(struct mtd_info *mtd, loff_t from, size_t len,
589 + size_t *retlen, u_char *buf)
591 + struct ps3vram_priv *priv = mtd->priv;
592 + unsigned int cached, count;
594 + dbg("from = 0x%08x len = 0x%zx", (unsigned int) from, len);
596 + if (from >= mtd->size)
599 + if (len > mtd->size - from)
600 + len = mtd->size - from;
602 + /* Copy from vram to buf */
605 + unsigned int offset, avail;
606 + unsigned int entry;
608 + offset = (unsigned int) (from & (priv->cache.page_size - 1));
609 + avail = priv->cache.page_size - offset;
611 + mutex_lock(&priv->lock);
613 + entry = ps3vram_cache_match(mtd, from);
614 + cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
616 + dbg("from=%08x cached=%08x offset=%08x avail=%08x count=%08x",
617 + (unsigned)from, cached, offset, avail, count);
621 + memcpy(buf, priv->xdr_buf + cached, avail);
623 + mutex_unlock(&priv->lock);
634 +static int ps3vram_write(struct mtd_info *mtd, loff_t to, size_t len,
635 + size_t *retlen, const u_char *buf)
637 + struct ps3vram_priv *priv = mtd->priv;
638 + unsigned int cached, count;
640 + if (to >= mtd->size)
643 + if (len > mtd->size - to)
644 + len = mtd->size - to;
646 + /* Copy from buf to vram */
649 + unsigned int offset, avail;
650 + unsigned int entry;
652 + offset = (unsigned int) (to & (priv->cache.page_size - 1));
653 + avail = priv->cache.page_size - offset;
655 + mutex_lock(&priv->lock);
657 + entry = ps3vram_cache_match(mtd, to);
658 + cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
660 + dbg("to=%08x cached=%08x offset=%08x avail=%08x count=%08x",
661 + (unsigned) to, cached, offset, avail, count);
665 + memcpy(priv->xdr_buf + cached, buf, avail);
667 + priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
669 + mutex_unlock(&priv->lock);
680 +static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
682 + struct ps3vram_priv *priv;
684 + uint64_t ddr_lpar, ctrl_lpar, info_lpar, reports_lpar;
686 + uint64_t reports_size;
691 + ps3vram_mtd.priv = kzalloc(sizeof(struct ps3vram_priv), GFP_KERNEL);
692 + if (!ps3vram_mtd.priv)
694 + priv = ps3vram_mtd.priv;
696 + mutex_init(&priv->lock);
698 + /* Allocate XDR buffer (1MB aligned) */
699 + priv->xdr_buf = (uint8_t *) __get_free_pages(GFP_KERNEL,
700 + get_order(XDR_BUF_SIZE));
701 + if (priv->xdr_buf == NULL) {
702 + pr_err("ps3vram: could not allocate XDR buffer\n");
704 + goto out_free_priv;
707 + /* Put FIFO at begginning of XDR buffer */
708 + priv->fifo_base = (uint32_t *) (priv->xdr_buf + FIFO_OFFSET);
709 + priv->fifo_ptr = priv->fifo_base;
711 + /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
712 + if (ps3_open_hv_device(dev)) {
713 + pr_err("ps3vram: ps3_open_hv_device failed\n");
715 + goto out_close_gpu;
718 + /* Request memory */
720 + ddr_size = memparse(size, &rest);
722 + ddr_size -= ps3fb_videomemory.size;
723 + ddr_size = ALIGN(ddr_size, 1024*1024);
724 + if (ddr_size <= 0) {
725 + printk(KERN_ERR "ps3vram: specified size is too small\n");
727 + goto out_close_gpu;
730 + while (ddr_size > 0) {
731 + status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
732 + &priv->memory_handle,
736 + ddr_size -= 1024*1024;
738 + if (status != 0 || ddr_size <= 0) {
739 + pr_err("ps3vram: lv1_gpu_memory_allocate failed\n");
741 + goto out_free_xdr_buf;
743 + pr_info("ps3vram: allocated %u MiB of DDR memory\n",
744 + (unsigned int) (ddr_size / 1024 / 1024));
746 + /* Request context */
747 + status = lv1_gpu_context_allocate(priv->memory_handle,
749 + &priv->context_handle,
755 + pr_err("ps3vram: lv1_gpu_context_allocate failed\n");
757 + goto out_free_memory;
760 + /* Map XDR buffer to RSX */
761 + status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
762 + ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
765 + pr_err("ps3vram: lv1_gpu_context_iomap failed\n");
767 + goto out_free_context;
770 + priv->base = ioremap(ddr_lpar, ddr_size);
772 + pr_err("ps3vram: ioremap failed\n");
774 + goto out_free_context;
777 + priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
779 + pr_err("ps3vram: ioremap failed\n");
781 + goto out_unmap_vram;
784 + priv->reports = ioremap(reports_lpar, reports_size);
785 + if (!priv->reports) {
786 + pr_err("ps3vram: ioremap failed\n");
788 + goto out_unmap_ctrl;
791 + mutex_lock(&ps3_gpu_mutex);
792 + ps3vram_init_ring(&ps3vram_mtd);
793 + mutex_unlock(&ps3_gpu_mutex);
795 + ps3vram_mtd.name = "ps3vram";
796 + ps3vram_mtd.size = ddr_size;
797 + ps3vram_mtd.flags = MTD_CAP_RAM;
798 + ps3vram_mtd.erase = ps3vram_erase;
799 + ps3vram_mtd.point = NULL;
800 + ps3vram_mtd.unpoint = NULL;
801 + ps3vram_mtd.read = ps3vram_read;
802 + ps3vram_mtd.write = ps3vram_write;
803 + ps3vram_mtd.owner = THIS_MODULE;
804 + ps3vram_mtd.type = MTD_RAM;
805 + ps3vram_mtd.erasesize = CACHE_PAGE_SIZE;
806 + ps3vram_mtd.writesize = 1;
808 + ps3vram_bind(&ps3vram_mtd);
810 + mutex_lock(&ps3_gpu_mutex);
811 + ret = ps3vram_wait_ring(&ps3vram_mtd, 100);
812 + mutex_unlock(&ps3_gpu_mutex);
814 + pr_err("failed to initialize channels\n");
816 + goto out_unmap_reports;
819 + ps3vram_cache_init(&ps3vram_mtd);
821 + if (add_mtd_device(&ps3vram_mtd)) {
822 + pr_err("ps3vram: failed to register device\n");
824 + goto out_cache_cleanup;
827 + pr_info("ps3vram mtd device registered, %lu bytes\n", ddr_size);
831 + ps3vram_cache_cleanup(&ps3vram_mtd);
833 + iounmap(priv->reports);
835 + iounmap(priv->ctrl);
837 + iounmap(priv->base);
839 + lv1_gpu_context_free(priv->context_handle);
841 + lv1_gpu_memory_free(priv->memory_handle);
843 + ps3_close_hv_device(dev);
845 + free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
847 + kfree(ps3vram_mtd.priv);
848 + ps3vram_mtd.priv = NULL;
853 +static int ps3vram_shutdown(struct ps3_system_bus_device *dev)
855 + struct ps3vram_priv *priv;
857 + priv = ps3vram_mtd.priv;
859 + del_mtd_device(&ps3vram_mtd);
860 + ps3vram_cache_cleanup(&ps3vram_mtd);
861 + iounmap(priv->reports);
862 + iounmap(priv->ctrl);
863 + iounmap(priv->base);
864 + lv1_gpu_context_free(priv->context_handle);
865 + lv1_gpu_memory_free(priv->memory_handle);
866 + ps3_close_hv_device(dev);
867 + free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
872 +static struct ps3_system_bus_driver ps3vram_driver = {
873 + .match_id = PS3_MATCH_ID_GRAPHICS,
874 + .match_sub_id = PS3_MATCH_SUB_ID_RAMDISK,
875 + .core.name = DEVICE_NAME,
876 + .core.owner = THIS_MODULE,
877 + .probe = ps3vram_probe,
878 + .remove = ps3vram_shutdown,
879 + .shutdown = ps3vram_shutdown,
882 +static int __init ps3vram_init(void)
884 + return ps3_system_bus_driver_register(&ps3vram_driver);
887 +static void __exit ps3vram_exit(void)
889 + ps3_system_bus_driver_unregister(&ps3vram_driver);
892 +module_init(ps3vram_init);
893 +module_exit(ps3vram_exit);
895 +MODULE_LICENSE("GPL");
896 +MODULE_AUTHOR("Jim Paris <jim@jtan.com>");
897 +MODULE_DESCRIPTION("MTD driver for PS3 video RAM");
900 @@ -3353,6 +3353,12 @@ L: linuxppc-dev@ozlabs.org
901 L: cbe-oss-dev@ozlabs.org
907 +L: cbe-oss-dev@ozlabs.org
910 PVRUSB2 VIDEO4LINUX DRIVER