1 From: Suresh Siddha <suresh.b.siddha@intel.com>
2 Subject: x64, x2apic/intr-remap: add x2apic support, including enabling interrupt-remapping
3 References: fate #303948 and fate #303984
4 Patch-Mainline: queued for .28
5 Commit-ID: 6e1cb38a2aef7680975e71f23de187859ee8b158
7 Signed-off-by: Thomas Renninger <trenn@suse.de>
9 x2apic support. Interrupt-remapping must be enabled before enabling x2apic,
10 this is needed to ensure that IO interrupts continue to work properly after the
11 cpu mode is changed to x2apic(which uses 32bit extended physical/cluster
14 On systems where apicid's are > 255, BIOS can handover the control to OS in
15 x2apic mode. Or if the OS handover was in legacy xapic mode, check
16 if it is capable of x2apic mode. And if we succeed in enabling
17 Interrupt-remapping, then we can enable x2apic mode in the CPU.
19 Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
20 Cc: akpm@linux-foundation.org
21 Cc: arjan@linux.intel.com
22 Cc: andi@firstfloor.org
23 Cc: ebiederm@xmission.com
24 Cc: jbarnes@virtuousgeek.org
26 Signed-off-by: Ingo Molnar <mingo@elte.hu>
29 Documentation/kernel-parameters.txt | 2
30 arch/x86/kernel/acpi/boot.c | 2
31 arch/x86/kernel/apic_64.c | 154 +++++++++++++++++++++++++++++++++++-
32 arch/x86/kernel/cpu/common_64.c | 2
33 arch/x86/kernel/mpparse.c | 2
34 arch/x86/kernel/setup.c | 2
35 arch/x86/kernel/smpboot.c | 5 +
36 include/asm-x86/apic.h | 14 +--
37 8 files changed, 172 insertions(+), 11 deletions(-)
39 --- a/Documentation/kernel-parameters.txt
40 +++ b/Documentation/kernel-parameters.txt
41 @@ -1428,6 +1428,8 @@ and is between 256 and 4096 characters.
43 nolapic_timer [X86-32,APIC] Do not use the local APIC timer.
45 + nox2apic [X86-64,APIC] Do not enable x2APIC mode.
47 noltlbs [PPC] Do not use large page/tlb entries for kernel
48 lowmem mapping on PPC40x.
50 --- a/arch/x86/kernel/acpi/boot.c
51 +++ b/arch/x86/kernel/acpi/boot.c
52 @@ -1351,7 +1351,9 @@ static void __init acpi_process_madt(voi
61 if (error == -EINVAL) {
62 --- a/arch/x86/kernel/apic_64.c
63 +++ b/arch/x86/kernel/apic_64.c
65 #include <linux/clockchips.h>
66 #include <linux/acpi_pmtmr.h>
67 #include <linux/module.h>
68 +#include <linux/dmar.h>
70 #include <asm/atomic.h>
73 #include <asm/proto.h>
74 #include <asm/timex.h>
76 +#include <asm/i8259.h>
79 #include <mach_apic.h>
81 static int disable_apic_timer __cpuinitdata;
82 static int apic_calibrate_pmtmr __initdata;
87 +/* x2apic enabled before OS handover */
88 +int x2apic_preenabled;
90 /* Local APIC timer works in C2 */
91 int local_apic_timer_c2_ok;
92 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
93 @@ -925,6 +931,125 @@ void __cpuinit end_local_APIC_setup(void
97 +void check_x2apic(void)
101 + rdmsr(MSR_IA32_APICBASE, msr, msr2);
103 + if (msr & X2APIC_ENABLE) {
104 + printk("x2apic enabled by BIOS, switching to x2apic ops\n");
105 + x2apic_preenabled = x2apic = 1;
106 + apic_ops = &x2apic_ops;
110 +void enable_x2apic(void)
114 + rdmsr(MSR_IA32_APICBASE, msr, msr2);
115 + if (!(msr & X2APIC_ENABLE)) {
116 + printk("Enabling x2apic\n");
117 + wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
121 +void enable_IR_x2apic(void)
123 +#ifdef CONFIG_INTR_REMAP
125 + unsigned long flags;
127 + if (!cpu_has_x2apic)
130 + if (!x2apic_preenabled && disable_x2apic) {
132 + "Skipped enabling x2apic and Interrupt-remapping "
133 + "because of nox2apic\n");
137 + if (x2apic_preenabled && disable_x2apic)
138 + panic("Bios already enabled x2apic, can't enforce nox2apic");
140 + if (!x2apic_preenabled && skip_ioapic_setup) {
142 + "Skipped enabling x2apic and Interrupt-remapping "
143 + "because of skipping io-apic setup\n");
147 + ret = dmar_table_init();
150 + "dmar_table_init() failed with %d:\n", ret);
152 + if (x2apic_preenabled)
153 + panic("x2apic enabled by bios. But IR enabling failed");
156 + "Not enabling x2apic,Intr-remapping\n");
160 + local_irq_save(flags);
162 + save_mask_IO_APIC_setup();
164 + ret = enable_intr_remapping(1);
166 + if (ret && x2apic_preenabled) {
167 + local_irq_restore(flags);
168 + panic("x2apic enabled by bios. But IR enabling failed");
176 + apic_ops = &x2apic_ops;
182 + * IR enabling failed
184 + restore_IO_APIC_setup();
186 + reinit_intr_remapped_IO_APIC(x2apic_preenabled);
189 + local_irq_restore(flags);
192 + if (!x2apic_preenabled)
194 + "Enabled x2apic and interrupt-remapping\n");
197 + "Enabled Interrupt-remapping\n");
200 + "Failed to enable Interrupt-remapping and x2apic\n");
202 + if (!cpu_has_x2apic)
205 + if (x2apic_preenabled)
206 + panic("x2apic enabled prior OS handover,"
207 + " enable CONFIG_INTR_REMAP");
209 + printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
217 * Detect and enable local APICs on non-SMP boards.
218 * Original code written by Keir Fraser.
219 @@ -972,6 +1097,11 @@ void __init early_init_lapic_mapping(voi
221 void __init init_apic_mappings(void)
224 + boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
229 * If no local APIC can be found then set up a fake all
230 * zeroes page to simulate the local APIC and another
231 @@ -1010,6 +1140,9 @@ int __init APIC_init_uniprocessor(void)
235 + enable_IR_x2apic();
236 + setup_apic_routing();
241 @@ -1263,10 +1396,14 @@ static int lapic_resume(struct sys_devic
242 maxlvt = lapic_get_maxlvt();
244 local_irq_save(flags);
245 - rdmsr(MSR_IA32_APICBASE, l, h);
246 - l &= ~MSR_IA32_APICBASE_BASE;
247 - l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
248 - wrmsr(MSR_IA32_APICBASE, l, h);
250 + rdmsr(MSR_IA32_APICBASE, l, h);
251 + l &= ~MSR_IA32_APICBASE_BASE;
252 + l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
253 + wrmsr(MSR_IA32_APICBASE, l, h);
257 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
258 apic_write(APIC_ID, apic_pm_state.apic_id);
259 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
260 @@ -1406,6 +1543,15 @@ __cpuinit int apic_is_clustered_box(void
261 return (clusters > 2);
264 +static __init int setup_nox2apic(char *str)
266 + disable_x2apic = 1;
267 + clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
270 +early_param("nox2apic", setup_nox2apic);
274 * APIC command line parameters
276 --- a/arch/x86/kernel/cpu/common_64.c
277 +++ b/arch/x86/kernel/cpu/common_64.c
278 @@ -636,6 +636,8 @@ void __cpuinit cpu_init(void)
282 + if (cpu != 0 && x2apic)
286 * set up and load the per-CPU TSS
287 --- a/arch/x86/kernel/mpparse.c
288 +++ b/arch/x86/kernel/mpparse.c
289 @@ -397,7 +397,9 @@ static int __init smp_read_mpc(struct mp
290 generic_bigsmp_probe();
293 +#ifdef CONFIG_X86_32
294 setup_apic_routing();
297 printk(KERN_ERR "MPTABLE: no processors registered!\n");
298 return num_processors;
299 --- a/arch/x86/kernel/setup.c
300 +++ b/arch/x86/kernel/setup.c
301 @@ -769,6 +769,8 @@ void __init setup_arch(char **cmdline_p)
303 num_physpages = max_pfn;
305 + if (cpu_has_x2apic)
308 /* How many end-of-memory variables you have, grandma! */
309 /* need this before calling reserve_initrd */
310 --- a/arch/x86/kernel/smpboot.c
311 +++ b/arch/x86/kernel/smpboot.c
312 @@ -1169,6 +1169,11 @@ void __init native_smp_prepare_cpus(unsi
313 current_thread_info()->cpu = 0; /* needed? */
314 set_cpu_sibling_map(0);
316 +#ifdef CONFIG_X86_64
317 + enable_IR_x2apic();
318 + setup_apic_routing();
321 if (smp_sanity_check(max_cpus) < 0) {
322 printk(KERN_INFO "SMP disabled\n");
324 --- a/include/asm-x86/apic.h
325 +++ b/include/asm-x86/apic.h
326 @@ -93,12 +93,13 @@ static inline u32 native_apic_msr_read(u
330 -#ifdef CONFIG_X86_32
331 -extern void apic_wait_icr_idle(void);
332 -extern u32 safe_apic_wait_icr_idle(void);
333 -extern void apic_icr_write(u32 low, u32 id);
335 -extern void x2apic_icr_write(u32 low, u32 id);
336 +#ifndef CONFIG_X86_32
337 + extern int x2apic, x2apic_preenabled;
338 + extern void check_x2apic(void);
339 + extern void enable_x2apic(void);
340 + extern void enable_IR_x2apic(void);
341 + extern void x2apic_icr_write(u32 low, u32 id);
345 u32 (*read)(u32 reg);
346 @@ -119,7 +120,6 @@ extern struct apic_ops *apic_ops;
347 #define apic_icr_write (apic_ops->icr_write)
348 #define apic_wait_icr_idle (apic_ops->wait_icr_idle)
349 #define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
352 extern int get_physical_broadcast(void);