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1 /* Copyright (C) 2003-2017 Free Software Foundation, Inc.
2
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library. If not, see
17 <http://www.gnu.org/licenses/>. */
18
19 #include <stdint.h>
20 #include <sysdep.h>
21
22
23 typedef int8_t atomic8_t;
24 typedef uint8_t uatomic8_t;
25 typedef int_fast8_t atomic_fast8_t;
26 typedef uint_fast8_t uatomic_fast8_t;
27
28 typedef int32_t atomic32_t;
29 typedef uint32_t uatomic32_t;
30 typedef int_fast32_t atomic_fast32_t;
31 typedef uint_fast32_t uatomic_fast32_t;
32
33 typedef intptr_t atomicptr_t;
34 typedef uintptr_t uatomicptr_t;
35 typedef intmax_t atomic_max_t;
36 typedef uintmax_t uatomic_max_t;
37
38 #define __HAVE_64B_ATOMICS 0
39 #define USE_ATOMIC_COMPILER_BUILTINS 0
40
41
42 /* Microblaze does not have byte and halfword forms of load and reserve and
43 store conditional. So for microblaze we stub out the 8- and 16-bit forms. */
44 #define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
45 (abort (), 0)
46
47 #define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
48 (abort (), 0)
49
50 #define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
51 ({ \
52 __typeof (*(mem)) __tmp; \
53 __typeof (mem) __memp = (mem); \
54 int test; \
55 __asm __volatile ( \
56 " addc r0, r0, r0;" \
57 "1: lwx %0, %3, r0;" \
58 " addic %1, r0, 0;" \
59 " bnei %1, 1b;" \
60 " cmp %1, %0, %4;" \
61 " bnei %1, 2f;" \
62 " swx %5, %3, r0;" \
63 " addic %1, r0, 0;" \
64 " bnei %1, 1b;" \
65 "2:" \
66 : "=&r" (__tmp), \
67 "=&r" (test), \
68 "=m" (*__memp) \
69 : "r" (__memp), \
70 "r" (oldval), \
71 "r" (newval) \
72 : "cc", "memory"); \
73 __tmp; \
74 })
75
76 #define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
77 (abort (), (__typeof (*mem)) 0)
78
79 #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
80 ({ \
81 __typeof (*(mem)) __result; \
82 if (sizeof (*mem) == 4) \
83 __result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
84 else if (sizeof (*mem) == 8) \
85 __result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
86 else \
87 abort (); \
88 __result; \
89 })
90
91 #define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
92 ({ \
93 __typeof (*(mem)) __result; \
94 if (sizeof (*mem) == 4) \
95 __result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
96 else if (sizeof (*mem) == 8) \
97 __result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
98 else \
99 abort (); \
100 __result; \
101 })
102
103 #define __arch_atomic_exchange_32_acq(mem, value) \
104 ({ \
105 __typeof (*(mem)) __tmp; \
106 __typeof (mem) __memp = (mem); \
107 int test; \
108 __asm __volatile ( \
109 " addc r0, r0, r0;" \
110 "1: lwx %0, %4, r0;" \
111 " addic %1, r0, 0;" \
112 " bnei %1, 1b;" \
113 " swx %3, %4, r0;" \
114 " addic %1, r0, 0;" \
115 " bnei %1, 1b;" \
116 : "=&r" (__tmp), \
117 "=&r" (test), \
118 "=m" (*__memp) \
119 : "r" (value), \
120 "r" (__memp) \
121 : "cc", "memory"); \
122 __tmp; \
123 })
124
125 #define __arch_atomic_exchange_64_acq(mem, newval) \
126 (abort (), (__typeof (*mem)) 0)
127
128 #define atomic_exchange_acq(mem, value) \
129 ({ \
130 __typeof (*(mem)) __result; \
131 if (sizeof (*mem) == 4) \
132 __result = __arch_atomic_exchange_32_acq (mem, value); \
133 else if (sizeof (*mem) == 8) \
134 __result = __arch_atomic_exchange_64_acq (mem, value); \
135 else \
136 abort (); \
137 __result; \
138 })
139
140 #define atomic_exchange_rel(mem, value) \
141 ({ \
142 __typeof (*(mem)) __result; \
143 if (sizeof (*mem) == 4) \
144 __result = __arch_atomic_exchange_32_acq (mem, value); \
145 else if (sizeof (*mem) == 8) \
146 __result = __arch_atomic_exchange_64_acq (mem, value); \
147 else \
148 abort (); \
149 __result; \
150 })
151
152 #define __arch_atomic_exchange_and_add_32(mem, value) \
153 ({ \
154 __typeof (*(mem)) __tmp; \
155 __typeof (mem) __memp = (mem); \
156 int test; \
157 __asm __volatile ( \
158 " addc r0, r0, r0;" \
159 "1: lwx %0, %4, r0;" \
160 " addic %1, r0, 0;" \
161 " bnei %1, 1b;" \
162 " add %1, %3, %0;" \
163 " swx %1, %4, r0;" \
164 " addic %1, r0, 0;" \
165 " bnei %1, 1b;" \
166 : "=&r" (__tmp), \
167 "=&r" (test), \
168 "=m" (*__memp) \
169 : "r" (value), \
170 "r" (__memp) \
171 : "cc", "memory"); \
172 __tmp; \
173 })
174
175 #define __arch_atomic_exchange_and_add_64(mem, value) \
176 (abort (), (__typeof (*mem)) 0)
177
178 #define atomic_exchange_and_add(mem, value) \
179 ({ \
180 __typeof (*(mem)) __result; \
181 if (sizeof (*mem) == 4) \
182 __result = __arch_atomic_exchange_and_add_32 (mem, value); \
183 else if (sizeof (*mem) == 8) \
184 __result = __arch_atomic_exchange_and_add_64 (mem, value); \
185 else \
186 abort (); \
187 __result; \
188 })
189
190 #define __arch_atomic_increment_val_32(mem) \
191 ({ \
192 __typeof (*(mem)) __val; \
193 int test; \
194 __asm __volatile ( \
195 " addc r0, r0, r0;" \
196 "1: lwx %0, %3, r0;" \
197 " addic %1, r0, 0;" \
198 " bnei %1, 1b;" \
199 " addi %0, %0, 1;" \
200 " swx %0, %3, r0;" \
201 " addic %1, r0, 0;" \
202 " bnei %1, 1b;" \
203 : "=&r" (__val), \
204 "=&r" (test), \
205 "=m" (*mem) \
206 : "r" (mem), \
207 "m" (*mem) \
208 : "cc", "memory"); \
209 __val; \
210 })
211
212 #define __arch_atomic_increment_val_64(mem) \
213 (abort (), (__typeof (*mem)) 0)
214
215 #define atomic_increment_val(mem) \
216 ({ \
217 __typeof (*(mem)) __result; \
218 if (sizeof (*(mem)) == 4) \
219 __result = __arch_atomic_increment_val_32 (mem); \
220 else if (sizeof (*(mem)) == 8) \
221 __result = __arch_atomic_increment_val_64 (mem); \
222 else \
223 abort (); \
224 __result; \
225 })
226
227 #define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; })
228
229 #define __arch_atomic_decrement_val_32(mem) \
230 ({ \
231 __typeof (*(mem)) __val; \
232 int test; \
233 __asm __volatile ( \
234 " addc r0, r0, r0;" \
235 "1: lwx %0, %3, r0;" \
236 " addic %1, r0, 0;" \
237 " bnei %1, 1b;" \
238 " rsubi %0, %0, 1;" \
239 " swx %0, %3, r0;" \
240 " addic %1, r0, 0;" \
241 " bnei %1, 1b;" \
242 : "=&r" (__val), \
243 "=&r" (test), \
244 "=m" (*mem) \
245 : "r" (mem), \
246 "m" (*mem) \
247 : "cc", "memory"); \
248 __val; \
249 })
250
251 #define __arch_atomic_decrement_val_64(mem) \
252 (abort (), (__typeof (*mem)) 0)
253
254 #define atomic_decrement_val(mem) \
255 ({ \
256 __typeof (*(mem)) __result; \
257 if (sizeof (*(mem)) == 4) \
258 __result = __arch_atomic_decrement_val_32 (mem); \
259 else if (sizeof (*(mem)) == 8) \
260 __result = __arch_atomic_decrement_val_64 (mem); \
261 else \
262 abort (); \
263 __result; \
264 })
265
266 #define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; })