1 /* Optimized 32-bit memset implementation for POWER6.
2 Copyright (C) 1997-2015 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
21 /* __ptr_t [r3] memset (__ptr_t s [r3], int c [r4], size_t n [r5]));
24 The memset is done in three sizes: byte (8 bits), word (32 bits),
25 cache line (1024 bits). There is a special case for setting cache lines
26 to 0, to take advantage of the dcbz instruction. */
33 #define rRTN r3 /* Initial value of 1st argument. */
34 #define rMEMP0 r3 /* Original value of 1st arg. */
35 #define rCHR r4 /* Char to set in each byte. */
36 #define rLEN r5 /* Length of region to set. */
37 #define rMEMP r6 /* Address at which we are storing. */
38 #define rALIGN r7 /* Number of bytes we are setting now (when aligning). */
41 #define rNEG64 r8 /* Constant -64 for clearing with dcbz. */
42 #define rMEMP3 r9 /* Alt mem pointer. */
44 /* Take care of case for size <= 4. */
46 andi. rALIGN, rMEMP0, 3
49 /* Align to word boundary. */
51 insrwi rCHR, rCHR, 8, 16 /* Replicate byte to halfword. */
54 subfic rALIGN, rALIGN, 4
55 add rMEMP, rMEMP, rALIGN
56 sub rLEN, rLEN, rALIGN
64 /* Handle the case of size < 31. */
67 insrwi rCHR, rCHR, 16, 0 /* Replicate halfword to word. */
69 /* Align to 32-byte boundary. */
70 andi. rALIGN, rMEMP, 0x1C
71 subfic rALIGN, rALIGN, 0x20
74 add rMEMP, rMEMP, rALIGN
75 sub rLEN, rLEN, rALIGN
76 cmplwi cr1, rALIGN, 0x10
86 stwu rCHR, -16(rMEMP2)
87 L(a2): bf 29, L(caligned)
91 /* Now aligned to a 32 byte boundary. */
94 clrrwi. rALIGN, rLEN, 5
96 beq cr1, L(zloopstart) /* Special case for clearing memory using dcbz. */
98 beq L(medium) /* We may not actually get to do a full line. */
100 /* Storing a non-zero "c" value. We are aligned at a sector (32-byte)
101 boundary may not be at cache line (128-byte) boundary. */
103 /* memset in 32-byte chunks until we get to a cache line boundary.
104 If rLEN is less than the distance to the next cache-line boundary use
105 cacheAligned1 code to finish the tail. */
109 blt cr1,L(cacheAligned1)
111 beq L(nzCacheAligned)
120 andi. rTMP,rMEMP3,127
124 beq L(nzCacheAligned)
137 beq L(nzCacheAligned)
139 /* At this point we can overrun the store queue (pipe reject) so it is
140 time to slow things down. The store queue can merge two adjacent
141 stores into a single L1/L2 op, but the L2 is clocked at 1/2 the CPU.
142 So we add "group ending nops" to guarantee that we dispatch only two
143 stores every other cycle. */
162 blt cr1,L(cacheAligned1)
165 /* Now we are aligned to the cache line and can use dcbtst. */
170 blt cr1,L(cacheAligned1)
171 blt cr6,L(nzCacheAligned128)
173 L(nzCacheAligned128):
194 /* At this point we can overrun the store queue (pipe reject) so it is
195 time to slow things down. The store queue can merge two adjacent
196 stores into a single L1/L2 op, but the L2 is clocked at 1/2 the CPU.
197 So we add "group ending nops" to guarantee that we dispatch only one
230 blt cr6,L(cacheAligned1)
234 b L(nzCacheAligned256)
236 L(nzCacheAligned256):
240 /* When we are not in libc we should use only GPRs to avoid the FPU lock
277 /* We are in libc and this is a long memset so we can use FPRs and can afford
278 occasional FPU locked interrupts. */
298 bge cr1,L(nzCacheAligned256)
303 /* Storing a zero "c" value. We are aligned at a sector (32-byte)
304 boundary but may not be at cache line (128-byte) boundary. If the
305 remaining length spans a full cache line we can use the Data cache
306 block zero instruction. */
308 /* memset in 32-byte chunks until we get to a cache line boundary.
309 If rLEN is less than the distance to the next cache-line boundary use
310 cacheAligned1 code to finish the tail. */
315 blt cr1,L(cacheAligned1)
326 andi. rTMP,rMEMP3,127
345 /* At this point we can overrun the store queue (pipe reject) so it is
346 time to slow things down. The store queue can merge two adjacent
347 stores into a single L1/L2 op, but the L2 is clocked at 1/2 the CPU.
348 So we add "group ending nops" to guarantee that we dispatch only two
349 stores every other cycle. */
369 blt cr1,L(cacheAligned1)
370 blt cr6,L(cacheAligned128)
373 /* Now we are aligned to the cache line and can use dcbz. */
378 blt cr1,L(cacheAligned1)
382 blt cr6,L(cacheAligned128)
383 bgt cr5,L(cacheAligned512)
390 blt cr1,L(cacheAligned1)
391 blt cr6,L(cacheAligned128)
394 /* A simple loop for the longer (>640 bytes) lengths. This form limits
395 the branch miss-predicted to exactly 1 at loop exit.*/
398 blt cr1,L(cacheAligned1)
411 bge cr6,L(cacheAligned256)
412 blt cr1,L(cacheAligned1)
421 blt cr1,L(handletail32)
435 blt cr1,L(handletail32)
449 blt cr1,L(handletail32)
450 /* At this point we can overrun the store queue (pipe reject) so it is
451 time to slow things down. The store queue can merge two adjacent
452 stores into a single L1/L2 op, but the L2 is clocked at 1/2 the CPU.
453 So we add "group ending nops" to guarantee that we dispatch only two
454 stores every other cycle. */
476 /* We are here because the length or remainder (rLEN) is less than the
477 cache line/sector size and does not justify aggressive loop unrolling.
478 So set up the preconditions for L(medium) and go there. */
487 /* Memset of 4 bytes or less. */
500 /* Memset of 0-31 bytes. */
505 add rMEMP, rMEMP, rLEN
507 bt- 31, L(medium_31t)
508 bt- 30, L(medium_30t)
512 bge cr1, L(medium_27t)
520 bf- 30, L(medium_30f)
523 bf- 29, L(medium_29f)
526 blt cr1, L(medium_27f)
531 stwu rCHR, -16(rMEMP)
539 libc_hidden_builtin_def (memset)