1 /* Optimized memcpy implementation for PowerPC64.
2 Copyright (C) 2003-2019 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <https://www.gnu.org/licenses/>. */
21 /* void * [r3] memcpy (void *dst [r3], void *src [r4], size_t len [r5]);
24 Memcpy handles short copies (< 32-bytes) using a binary move blocks
25 (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled
26 with the appropriate combination of byte and halfword load/stores.
27 There is minimal effort to optimize the alignment of short moves.
28 The 64-bit implementations of POWER3 and POWER4 do a reasonable job
29 of handling unaligned load/stores that do not cross 32-byte boundaries.
31 Longer moves (>= 32-bytes) justify the effort to get at least the
32 destination doubleword (8-byte) aligned. Further optimization is
33 possible when both source and destination are doubleword aligned.
34 Each case has a optimized unrolled loop. */
37 # define MEMCPY memcpy
40 ENTRY_TOCLESS (MEMCPY, 5)
48 andi. 11,3,7 /* check alignment of dst. */
49 clrldi 0,0,61 /* Number of bytes until the 1st doubleword of dst. */
50 clrldi 10,4,61 /* check alignment of src. */
52 ble- cr1,.L2 /* If move < 32 bytes use short move code. */
55 srdi 9,5,3 /* Number of full double words remaining. */
61 /* Move 0-7 bytes as needed to get the destination doubleword aligned. */
78 clrldi 10,12,61 /* check alignment of src again. */
79 srdi 9,31,3 /* Number of full double words remaining. */
81 /* Copy doublewords from source to destination, assuming the
82 destination is aligned on a doubleword boundary.
84 At this point we know there are at least 25 bytes left (32-7) to copy.
85 The next step is to determine if the source is also doubleword aligned.
86 If not branch to the unaligned move code at .L6. which uses
87 a load, shift, store strategy.
89 Otherwise source and destination are doubleword aligned, and we can
90 the optimized doubleword copy loop. */
94 bne- cr6,.L6 /* If source is not DW aligned. */
96 /* Move doublewords where destination and source are DW aligned.
97 Use a unrolled loop to copy 4 doubleword (32-bytes) per iteration.
98 If the copy is not an exact multiple of 32 bytes, 1-3
99 doublewords are copied as needed to set up the main loop. After
100 the main loop exits there may be a tail of 1-7 bytes. These byte are
101 copied a word/halfword/byte at a time as needed to preserve alignment. */
156 /* At this point we have a tail of 0-7 bytes and we know that the
157 destination is double word aligned. */
172 /* Return original dst pointer. */
177 /* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31
178 bytes. Each case is handled without loops, using binary (1,2,4,8)
181 In the short (0-8 byte) case no attempt is made to force alignment
182 of either source or destination. The hardware will handle the
183 unaligned load/stores with small delays for crossing 32- 64-byte, and
184 4096-byte boundaries. Since these short moves are unlikely to be
185 unaligned or cross these boundaries, the overhead to force
186 alignment is not justified.
188 The longer (9-31 byte) move is more likely to cross 32- or 64-byte
189 boundaries. Since only loads are sensitive to the 32-/64-byte
190 boundaries it is more important to align the source then the
191 destination. If the source is not already word aligned, we first
192 move 1-3 bytes as needed. Since we are only word aligned we don't
193 use double word load/stores to insure that all loads are aligned.
194 While the destination and stores may still be unaligned, this
195 is only an issue for page (4096 byte boundary) crossing, which
196 should be rare for these short moves. The hardware handles this
197 case automatically with a small delay. */
205 ble cr6,.LE8 /* Handle moves of 0-8 bytes. */
206 /* At least 9 bytes left. Get the source word aligned. */
211 beq .L3 /* If the source is already word aligned skip this. */
212 /* Copy 1-3 bytes to get source address word aligned. */
219 #ifdef __LITTLE_ENDIAN__
227 #ifdef __LITTLE_ENDIAN__
238 #ifdef __LITTLE_ENDIAN__
248 /* At least 6 bytes left and the source is word aligned. */
250 16: /* Move 16 bytes. */
261 8: /* Move 8 bytes. */
269 4: /* Move 4 bytes. */
275 2: /* Move 2-3 bytes. */
284 1: /* Move 1 byte. */
289 /* Return original dst pointer. */
293 /* Special case to copy 0-8 bytes. */
298 /* Would have liked to use use ld/std here but the 630 processors are
299 slow for load/store doubles that are not at least word aligned.
300 Unaligned Load/Store word execute with only a 1 cycle penalty. */
305 /* Return original dst pointer. */
328 /* Return original dst pointer. */
335 /* Copy doublewords where the destination is aligned but the source is
336 not. Use aligned doubleword loads from the source, shifted to realign
337 the data, to allow aligned destination stores. */
348 #ifdef __LITTLE_ENDIAN__
360 #ifdef __LITTLE_ENDIAN__
372 #ifdef __LITTLE_ENDIAN__
391 bne cr6,.L9 /* If the tail is 0 bytes we are done! */
392 /* Return original dst pointer. */
396 END_GEN_TB (MEMCPY,TB_TOCLESS)
397 libc_hidden_builtin_def (memcpy)