1 /* Optimized memcpy implementation for PowerPC64.
2 Copyright (C) 2003-2019 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <https://www.gnu.org/licenses/>. */
21 /* void * [r3] memcpy (void *dst [r3], void *src [r4], size_t len [r5]);
24 Memcpy handles short copies (< 32-bytes) using a binary move blocks
25 (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled
26 with the appropriate combination of byte and halfword load/stores.
27 There is minimal effort to optimize the alignment of short moves.
28 The 64-bit implementations of POWER3 and POWER4 do a reasonable job
29 of handling unaligned load/stores that do not cross 32-byte boundaries.
31 Longer moves (>= 32-bytes) justify the effort to get at least the
32 destination doubleword (8-byte) aligned. Further optimization is
33 possible when both source and destination are doubleword aligned.
34 Each case has a optimized unrolled loop.
36 For POWER6 unaligned loads will take a 20+ cycle hiccup for any
37 L1 cache miss that crosses a 32- or 128-byte boundary. Store
38 is more forgiving and does not take a hiccup until page or
39 segment boundaries. So we require doubleword alignment for
40 the source but may take a risk and only require word alignment
41 for the destination. */
44 # define MEMCPY memcpy
47 ENTRY_TOCLESS (MEMCPY, 7)
54 andi. 11,3,7 /* check alignment of dst. */
55 clrldi 0,0,61 /* Number of bytes until the 1st doubleword of dst. */
56 clrldi 10,4,61 /* check alignment of src. */
58 ble- cr1,.L2 /* If move < 32 bytes use short move code. */
61 srdi 9,5,3 /* Number of full double words remaining. */
65 /* Move 0-7 bytes as needed to get the destination doubleword aligned.
66 Duplicate some code to maximize fall-through and minimize agen delays. */
95 /* Add the number of bytes until the 1st doubleword of dst to src and dst. */
99 clrldi 10,4,61 /* check alignment of src again. */
100 srdi 9,5,3 /* Number of full double words remaining. */
102 /* Copy doublewords from source to destination, assuming the
103 destination is aligned on a doubleword boundary.
105 At this point we know there are at least 25 bytes left (32-7) to copy.
106 The next step is to determine if the source is also doubleword aligned.
107 If not branch to the unaligned move code at .L6. which uses
108 a load, shift, store strategy.
110 Otherwise source and destination are doubleword aligned, and we can
111 the optimized doubleword copy loop. */
116 srdi 12,5,7 /* Number of 128-byte blocks to move. */
117 cmpldi cr1,11,0 /* If the tail is 0 bytes */
118 bne- cr6,.L6 /* If source is not DW aligned. */
120 /* Move doublewords where destination and source are DW aligned.
121 Use a unrolled loop to copy 16 doublewords (128-bytes) per iteration.
122 If the copy is not an exact multiple of 128 bytes, 1-15
123 doublewords are copied as needed to set up the main loop. After
124 the main loop exits there may be a tail of 1-7 bytes. These byte
125 are copied a word/halfword/byte at a time as needed to preserve
128 For POWER6 the L1 is store-through and the L2 is store-in. The
129 L2 is clocked at half CPU clock so we can store 16 bytes every
130 other cycle. POWER6 also has a load/store bypass so we can do
131 load, load, store, store every 2 cycles.
133 The following code is sensitive to cache line alignment. Do not
134 make any change with out first making sure they don't result in
135 splitting ld/std pairs across a cache line. */
276 ble cr5,L(das_loop_e)
322 /* Check of a 1-7 byte tail, return if none. */
324 /* Return original dst pointer. */
332 /* At this point we have a tail of 0-7 bytes and we know that the
333 destination is double word aligned. */
361 /* Return original dst pointer. */
365 /* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31
366 bytes. Each case is handled without loops, using binary (1,2,4,8)
369 In the short (0-8 byte) case no attempt is made to force alignment
370 of either source or destination. The hardware will handle the
371 unaligned load/stores with small delays for crossing 32- 128-byte,
372 and 4096-byte boundaries. Since these short moves are unlikely to be
373 unaligned or cross these boundaries, the overhead to force
374 alignment is not justified.
376 The longer (9-31 byte) move is more likely to cross 32- or 128-byte
377 boundaries. Since only loads are sensitive to the 32-/128-byte
378 boundaries it is more important to align the source then the
379 destination. If the source is not already word aligned, we first
380 move 1-3 bytes as needed. Since we are only word aligned we don't
381 use double word load/stores to insure that all loads are aligned.
382 While the destination and stores may still be unaligned, this
383 is only an issue for page (4096 byte boundary) crossing, which
384 should be rare for these short moves. The hardware handles this
385 case automatically with a small (~20 cycle) delay. */
392 ble cr6,.LE8 /* Handle moves of 0-8 bytes. */
393 /* At least 9 bytes left. Get the source word aligned. */
398 beq L(dus_tail) /* If the source is already word aligned skip this. */
399 /* Copy 1-3 bytes to get source address word aligned. */
406 #ifdef __LITTLE_ENDIAN__
414 #ifdef __LITTLE_ENDIAN__
425 #ifdef __LITTLE_ENDIAN__
435 /* At least 6 bytes left and the source is word aligned. This allows
436 some speculative loads up front. */
437 /* We need to special case the fall-through because the biggest delays
438 are due to address computation not being ready in time for the
444 L(dus_tail16): /* Move 16 bytes. */
451 /* Move 8 bytes more. */
452 bf 28,L(dus_tail16p8)
458 /* Move 4 bytes more. */
459 bf 29,L(dus_tail16p4)
465 /* exactly 28 bytes. Return original dst pointer and exit. */
469 L(dus_tail16p8): /* less than 8 bytes left. */
470 beq cr1,L(dus_tailX) /* exactly 16 bytes, early exit. */
472 bf 29,L(dus_tail16p2)
473 /* Move 4 bytes more. */
479 /* exactly 20 bytes. Return original dst pointer and exit. */
483 L(dus_tail16p4): /* less than 4 bytes left. */
487 /* exactly 24 bytes. Return original dst pointer and exit. */
491 L(dus_tail16p2): /* 16 bytes moved, less than 4 bytes left. */
497 L(dus_tail8): /* Move 8 bytes. */
498 /* r6, r7 already loaded speculatively. */
505 /* Move 4 bytes more. */
512 /* exactly 12 bytes. Return original dst pointer and exit. */
516 L(dus_tail8p4): /* less than 4 bytes left. */
520 /* exactly 8 bytes. Return original dst pointer and exit. */
525 L(dus_tail4): /* Move 4 bytes. */
526 /* r6 already loaded speculatively. If we are here we know there is
527 more than 4 bytes left. So there is no need to test. */
531 L(dus_tail2): /* Move 2-3 bytes. */
540 L(dus_tail1): /* Move 1 byte. */
545 /* Return original dst pointer. */
549 /* Special case to copy 0-8 bytes. */
554 /* Exactly 8 bytes. We may cross a 32-/128-byte boundary and take a ~20
555 cycle delay. This case should be rare and any attempt to avoid this
556 would take most of 20 cycles any way. */
559 /* Return original dst pointer. */
581 /* Return original dst pointer. */
590 /* Copy doublewords where the destination is aligned but the source is
591 not. Use aligned doubleword loads from the source, shifted to realign
592 the data, to allow aligned destination stores. */
593 addi 11,9,-1 /* loop DW count is one less than total */
594 subf 5,10,12 /* Move source addr to previous full double word. */
598 srdi 8,11,2 /* calculate the 32 byte loop count */
599 ld 6,0(5) /* pre load 1st full doubleword. */
603 ld 7,8(5) /* pre load 2nd full doubleword. */
613 /* there are at least two DWs to copy */
614 /* FIXME: can combine last shift and "or" into "rldimi" */
615 #ifdef __LITTLE_ENDIAN__
625 #ifdef __LITTLE_ENDIAN__
637 blt cr6,L(du1_fini) /* if total DWs = 3, then bypass loop */
639 /* there is a third DW to copy */
640 #ifdef __LITTLE_ENDIAN__
653 beq cr6,L(du1_fini) /* if total DWs = 4, then bypass loop */
657 #ifdef __LITTLE_ENDIAN__
673 /* copy 32 bytes at a time */
675 #ifdef __LITTLE_ENDIAN__
685 #ifdef __LITTLE_ENDIAN__
695 #ifdef __LITTLE_ENDIAN__
705 #ifdef __LITTLE_ENDIAN__
720 /* calculate and store the final DW */
721 #ifdef __LITTLE_ENDIAN__
736 /* there are at least two DWs to copy */
737 #ifdef __LITTLE_ENDIAN__
747 #ifdef __LITTLE_ENDIAN__
759 blt cr6,L(du2_fini) /* if total DWs = 3, then bypass loop */
761 /* there is a third DW to copy */
762 #ifdef __LITTLE_ENDIAN__
775 beq cr6,L(du2_fini) /* if total DWs = 4, then bypass loop */
779 #ifdef __LITTLE_ENDIAN__
795 /* copy 32 bytes at a time */
797 #ifdef __LITTLE_ENDIAN__
807 #ifdef __LITTLE_ENDIAN__
817 #ifdef __LITTLE_ENDIAN__
827 #ifdef __LITTLE_ENDIAN__
842 /* calculate and store the final DW */
843 #ifdef __LITTLE_ENDIAN__
858 /* there are at least two DWs to copy */
859 #ifdef __LITTLE_ENDIAN__
869 #ifdef __LITTLE_ENDIAN__
881 blt cr6,L(du3_fini) /* if total DWs = 3, then bypass loop */
883 /* there is a third DW to copy */
884 #ifdef __LITTLE_ENDIAN__
897 beq cr6,L(du3_fini) /* if total DWs = 4, then bypass loop */
901 #ifdef __LITTLE_ENDIAN__
917 /* copy 32 bytes at a time */
919 #ifdef __LITTLE_ENDIAN__
929 #ifdef __LITTLE_ENDIAN__
939 #ifdef __LITTLE_ENDIAN__
949 #ifdef __LITTLE_ENDIAN__
964 /* calculate and store the final DW */
965 #ifdef __LITTLE_ENDIAN__
986 /* there are at least two DWs to copy */
987 #ifdef __LITTLE_ENDIAN__
997 #ifdef __LITTLE_ENDIAN__
1009 blt cr6,L(du4_fini) /* if total DWs = 3, then bypass loop */
1011 /* there is a third DW to copy */
1012 #ifdef __LITTLE_ENDIAN__
1025 beq cr6,L(du4_fini) /* if total DWs = 4, then bypass loop */
1029 #ifdef __LITTLE_ENDIAN__
1045 /* copy 32 bytes at a time */
1047 #ifdef __LITTLE_ENDIAN__
1057 #ifdef __LITTLE_ENDIAN__
1067 #ifdef __LITTLE_ENDIAN__
1077 #ifdef __LITTLE_ENDIAN__
1092 /* calculate and store the final DW */
1093 #ifdef __LITTLE_ENDIAN__
1108 /* there are at least two DWs to copy */
1109 #ifdef __LITTLE_ENDIAN__
1119 #ifdef __LITTLE_ENDIAN__
1131 blt cr6,L(du5_fini) /* if total DWs = 3, then bypass loop */
1133 /* there is a third DW to copy */
1134 #ifdef __LITTLE_ENDIAN__
1147 beq cr6,L(du5_fini) /* if total DWs = 4, then bypass loop */
1151 #ifdef __LITTLE_ENDIAN__
1167 /* copy 32 bytes at a time */
1169 #ifdef __LITTLE_ENDIAN__
1179 #ifdef __LITTLE_ENDIAN__
1189 #ifdef __LITTLE_ENDIAN__
1199 #ifdef __LITTLE_ENDIAN__
1214 /* calculate and store the final DW */
1215 #ifdef __LITTLE_ENDIAN__
1230 /* there are at least two DWs to copy */
1231 #ifdef __LITTLE_ENDIAN__
1241 #ifdef __LITTLE_ENDIAN__
1253 blt cr6,L(du6_fini) /* if total DWs = 3, then bypass loop */
1255 /* there is a third DW to copy */
1256 #ifdef __LITTLE_ENDIAN__
1269 beq cr6,L(du6_fini) /* if total DWs = 4, then bypass loop */
1273 #ifdef __LITTLE_ENDIAN__
1289 /* copy 32 bytes at a time */
1291 #ifdef __LITTLE_ENDIAN__
1301 #ifdef __LITTLE_ENDIAN__
1311 #ifdef __LITTLE_ENDIAN__
1321 #ifdef __LITTLE_ENDIAN__
1336 /* calculate and store the final DW */
1337 #ifdef __LITTLE_ENDIAN__
1352 /* there are at least two DWs to copy */
1353 #ifdef __LITTLE_ENDIAN__
1363 #ifdef __LITTLE_ENDIAN__
1375 blt cr6,L(du7_fini) /* if total DWs = 3, then bypass loop */
1377 /* there is a third DW to copy */
1378 #ifdef __LITTLE_ENDIAN__
1391 beq cr6,L(du7_fini) /* if total DWs = 4, then bypass loop */
1395 #ifdef __LITTLE_ENDIAN__
1411 /* copy 32 bytes at a time */
1413 #ifdef __LITTLE_ENDIAN__
1423 #ifdef __LITTLE_ENDIAN__
1433 #ifdef __LITTLE_ENDIAN__
1443 #ifdef __LITTLE_ENDIAN__
1458 /* calculate and store the final DW */
1459 #ifdef __LITTLE_ENDIAN__
1474 beq cr1,0f /* If the tail is 0 bytes we are done! */
1478 /* At this point we have a tail of 0-7 bytes and we know that the
1479 destination is double word aligned. */
1494 /* Return original dst pointer. */
1498 END_GEN_TB (MEMCPY,TB_TOCLESS)
1499 libc_hidden_builtin_def (memcpy)