sysdeps/standalone/i960/nindy960/brdinit.c

   1 /* Copyright (C) 1994 Free Software Foundation, Inc.
   2    Contributed by Joel Sherrill (jsherril@redstone-emh2.army.mil),
   3      On-Line Applications Research Corporation.
   4
   5 This file is part of the GNU C Library.
   6
   7 The GNU C Library is free software; you can redistribute it and/or
   8 modify it under the terms of the GNU Library General Public License as
   9 published by the Free Software Foundation; either version 2 of the
  10 License, or (at your option) any later version.
  11
  12 The GNU C Library is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 Library General Public License for more details.
  16
  17 You should have received a copy of the GNU Library General Public
  18 License along with the GNU C Library; see the file COPYING.LIB.  If
  19 not, write to the Free Software Foundation, Inc., 675 Mass Ave,
  20 Cambridge, MA 02139, USA.  */
  21
  22 #include <ansidecl.h>
  23 #include <standalone.h>
  24 #include "i960ca.h"
  25
  26 /*  _Board_Initialize()
  27
  28 This routine initializes the board.
  29
  30 NOTE: Only tested on a Cyclone CVME961 but should be OK on any i960ca board. */
  31
  32 void
  33 DEFUN_VOID(_Board_Initialize)
  34 {
  35   struct i80960ca_prcb   *prcb;     /* ptr to processor control block */
  36   struct i80960ca_ctltbl *ctl_tbl;  /* ptr to control table */
  37
  38   static inline struct i80960ca_prcb *get_prcb()
  39   { register struct i80960ca_prcb *_prcb = 0;
  40     asm volatile( "calls 5; \
  41                    mov   g0,%0" \
  42                    : "=d" (_prcb) \
  43                    : "0" (_prcb) );
  44     return ( _prcb );
  45   }
  46
  47   prcb    = get_prcb();
  48   ctl_tbl = prcb->control_tbl;
  49
  50   /*   The following configures the data breakpoint (which must be set
  51    *   before this is executed) to break on writes only.
  52    */
  53
  54   ctl_tbl->bpcon &= ~0x00cc0000;
  55   reload_ctl_group( 6 );
  56
  57    /*  bit 31 of the Register Cache Control can be set to
  58     *  enable an alternative caching algorithm.  It does
  59     *  not appear to help our applications.
  60     */
  61
  62    /* Configure Number of Register Caches */
  63
  64   prcb->reg_cache_cfg = 8;
  65   soft_reset( prcb );
  66 }