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git.ipfire.org Git - thirdparty/glibc.git/blob - sysdeps/x86/fpu/sfp-machine.h
1 /* Configure soft-fp for building sqrtf128. Based on sfp-machine.h in
2 libgcc, with soft-float and other irrelevant parts removed. */
4 /* The type of the result of a floating point comparison. This must
5 match `__libgcc_cmp_return__' in GCC for the target. */
6 typedef int __gcc_CMPtype
__attribute__ ((mode (__libgcc_cmp_return__
)));
7 #define CMPtype __gcc_CMPtype
10 # define _FP_W_TYPE_SIZE 64
11 # define _FP_W_TYPE unsigned long long
12 # define _FP_WS_TYPE signed long long
13 # define _FP_I_TYPE long long
15 typedef int TItype
__attribute__ ((mode (TI
)));
16 typedef unsigned int UTItype
__attribute__ ((mode (TI
)));
18 # define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype))
20 # define _FP_MUL_MEAT_Q(R,X,Y) \
21 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
23 # define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
25 # define _FP_NANFRAC_S _FP_QNANBIT_S
26 # define _FP_NANFRAC_D _FP_QNANBIT_D
27 # define _FP_NANFRAC_E _FP_QNANBIT_E, 0
28 # define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0
30 # define FP_EX_SHIFT 7
32 # define _FP_DECL_EX \
33 unsigned int _fcw __attribute__ ((unused)) = FP_RND_NEAREST;
35 # define FP_RND_NEAREST 0
36 # define FP_RND_ZERO 0x6000
37 # define FP_RND_PINF 0x4000
38 # define FP_RND_MINF 0x2000
40 # define FP_RND_MASK 0x6000
42 # define FP_INIT_ROUNDMODE \
44 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (_fcw)); \
47 # define _FP_W_TYPE_SIZE 32
48 # define _FP_W_TYPE unsigned int
49 # define _FP_WS_TYPE signed int
50 # define _FP_I_TYPE int
52 # define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
53 __asm__ ("add{l} {%11,%3|%3,%11}\n\t" \
54 "adc{l} {%9,%2|%2,%9}\n\t" \
55 "adc{l} {%7,%1|%1,%7}\n\t" \
56 "adc{l} {%5,%0|%0,%5}" \
57 : "=r" ((USItype) (r3)), \
58 "=&r" ((USItype) (r2)), \
59 "=&r" ((USItype) (r1)), \
60 "=&r" ((USItype) (r0)) \
61 : "%0" ((USItype) (x3)), \
62 "g" ((USItype) (y3)), \
63 "%1" ((USItype) (x2)), \
64 "g" ((USItype) (y2)), \
65 "%2" ((USItype) (x1)), \
66 "g" ((USItype) (y1)), \
67 "%3" ((USItype) (x0)), \
69 # define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
70 __asm__ ("add{l} {%8,%2|%2,%8}\n\t" \
71 "adc{l} {%6,%1|%1,%6}\n\t" \
72 "adc{l} {%4,%0|%0,%4}" \
73 : "=r" ((USItype) (r2)), \
74 "=&r" ((USItype) (r1)), \
75 "=&r" ((USItype) (r0)) \
76 : "%0" ((USItype) (x2)), \
77 "g" ((USItype) (y2)), \
78 "%1" ((USItype) (x1)), \
79 "g" ((USItype) (y1)), \
80 "%2" ((USItype) (x0)), \
82 # define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
83 __asm__ ("sub{l} {%11,%3|%3,%11}\n\t" \
84 "sbb{l} {%9,%2|%2,%9}\n\t" \
85 "sbb{l} {%7,%1|%1,%7}\n\t" \
86 "sbb{l} {%5,%0|%0,%5}" \
87 : "=r" ((USItype) (r3)), \
88 "=&r" ((USItype) (r2)), \
89 "=&r" ((USItype) (r1)), \
90 "=&r" ((USItype) (r0)) \
91 : "0" ((USItype) (x3)), \
92 "g" ((USItype) (y3)), \
93 "1" ((USItype) (x2)), \
94 "g" ((USItype) (y2)), \
95 "2" ((USItype) (x1)), \
96 "g" ((USItype) (y1)), \
97 "3" ((USItype) (x0)), \
99 # define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
100 __asm__ ("sub{l} {%8,%2|%2,%8}\n\t" \
101 "sbb{l} {%6,%1|%1,%6}\n\t" \
102 "sbb{l} {%4,%0|%0,%4}" \
103 : "=r" ((USItype) (r2)), \
104 "=&r" ((USItype) (r1)), \
105 "=&r" ((USItype) (r0)) \
106 : "0" ((USItype) (x2)), \
107 "g" ((USItype) (y2)), \
108 "1" ((USItype) (x1)), \
109 "g" ((USItype) (y1)), \
110 "2" ((USItype) (x0)), \
111 "g" ((USItype) (y0)))
112 # define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \
113 __asm__ ("add{l} {%4,%3|%3,%4}\n\t" \
114 "adc{l} {$0,%2|%2,0}\n\t" \
115 "adc{l} {$0,%1|%1,0}\n\t" \
116 "adc{l} {$0,%0|%0,0}" \
117 : "+r" ((USItype) (x3)), \
118 "+&r" ((USItype) (x2)), \
119 "+&r" ((USItype) (x1)), \
120 "+&r" ((USItype) (x0)) \
121 : "g" ((USItype) (i)))
124 # define _FP_MUL_MEAT_S(R,X,Y) \
125 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
126 # define _FP_MUL_MEAT_D(R,X,Y) \
127 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
128 # define _FP_MUL_MEAT_Q(R,X,Y) \
129 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
131 # define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y)
132 # define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
133 # define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
135 # define _FP_NANFRAC_S _FP_QNANBIT_S
136 # define _FP_NANFRAC_D _FP_QNANBIT_D, 0
137 /* Even if XFmode is 12byte, we have to pad it to
138 16byte since soft-fp emulation is done in 16byte. */
139 # define _FP_NANFRAC_E _FP_QNANBIT_E, 0, 0, 0
140 # define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
142 # define FP_EX_SHIFT 0
144 # define _FP_DECL_EX \
145 unsigned short _fcw __attribute__ ((unused)) = FP_RND_NEAREST;
147 # define FP_RND_NEAREST 0
148 # define FP_RND_ZERO 0xc00
149 # define FP_RND_PINF 0x800
150 # define FP_RND_MINF 0x400
152 # define FP_RND_MASK 0xc00
154 # define FP_INIT_ROUNDMODE \
156 __asm__ __volatile__ ("fnstcw\t%0" : "=m" (_fcw)); \
160 #define _FP_KEEPNANFRACP 1
161 #define _FP_QNANNEGATEDP 0
163 #define _FP_NANSIGN_S 1
164 #define _FP_NANSIGN_D 1
165 #define _FP_NANSIGN_E 1
166 #define _FP_NANSIGN_Q 1
168 /* Here is something Intel misdesigned: the specs don't define
169 the case where we have two NaNs with same mantissas, but
170 different sign. Different operations pick up different NaNs. */
171 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
173 if (_FP_FRAC_GT_##wc(X, Y) \
174 || (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
177 _FP_FRAC_COPY_##wc(R,X); \
182 _FP_FRAC_COPY_##wc(R,Y); \
184 R##_c = FP_CLS_NAN; \
187 #define FP_EX_INVALID 0x01
188 #define FP_EX_DENORM 0x02
189 #define FP_EX_DIVZERO 0x04
190 #define FP_EX_OVERFLOW 0x08
191 #define FP_EX_UNDERFLOW 0x10
192 #define FP_EX_INEXACT 0x20
194 (FP_EX_INVALID | FP_EX_DENORM | FP_EX_DIVZERO | FP_EX_OVERFLOW \
195 | FP_EX_UNDERFLOW | FP_EX_INEXACT)
197 void __sfp_handle_exceptions (int);
199 #define FP_HANDLE_EXCEPTIONS \
201 if (__builtin_expect (_fex, 0)) \
202 __sfp_handle_exceptions (_fex); \
205 #define FP_TRAPPING_EXCEPTIONS ((~_fcw >> FP_EX_SHIFT) & FP_EX_ALL)
207 #define FP_ROUNDMODE (_fcw & FP_RND_MASK)
209 #define _FP_TININESS_AFTER_ROUNDING 1