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git.ipfire.org Git - thirdparty/glibc.git/blob - sysdeps/x86_64/fpu/feenablxcpt.c
1 /* Enable floating-point exceptions.
2 Copyright (C) 2001-2021 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <https://www.gnu.org/licenses/>. */
22 feenableexcept (int excepts
)
24 unsigned short int new_exc
, old_exc
;
27 excepts
&= FE_ALL_EXCEPT
;
29 /* Get the current control word of the x87 FPU. */
30 __asm__ ("fstcw %0" : "=m" (*&new_exc
));
32 old_exc
= (~new_exc
) & FE_ALL_EXCEPT
;
35 __asm__ ("fldcw %0" : : "m" (*&new_exc
));
37 /* And now the same for the SSE MXCSR register. */
38 __asm__ ("stmxcsr %0" : "=m" (*&new));
40 /* The SSE exception masks are shifted by 7 bits. */
41 new &= ~(excepts
<< 7);
42 __asm__ ("ldmxcsr %0" : : "m" (*&new));