RC4 tune-up for Intel P4 core, both 32- and 64-bit ones. As it's

[thirdparty/openssl.git] / doc / crypto / OPENSSL_ia32cap.pod

diff --git a/doc/crypto/OPENSSL_ia32cap.pod b/doc/crypto/OPENSSL_ia32cap.pod
index 790e8e9b1ef2d120c6a55a2f5546274547be42f4..ec6b655c17b3459260ab7ff91e7aeb026658b616 100644 (file)
--- a/doc/crypto/OPENSSL_ia32cap.pod
+++ b/doc/crypto/OPENSSL_ia32cap.pod
@@ -14,11 +14,12 @@ OPENSSL_ia32cap
 Value returned by OPENSSL_ia32cap_loc() is address of a variable
 containing IA-32 processor capabilities bit vector as it appears in EDX
 register after executing CPUID instruction with EAX=1 input value (see
-Intel Application Note #241618). Naturally it's meaningful on IA-32
+Intel Application Note #241618). Naturally it's meaningful on IA-32[E]
 platforms only. The variable is normally set up automatically upon
 toolkit initialization, but can be manipulated afterwards to modify
-crypto library behaviour. For the moment of this writing only two bits
-are significant, namely bit #26 denoting SSE2 support, and bit #4
+crypto library behaviour. For the moment of this writing three bits are
+significant, namely bit #28 denoting Hyperthreading, which is used to
+distinguish Intel P4 core, bit #26 denoting SSE2 support, and bit #4
 denoting presence of Time-Stamp Counter. Clearing bit #26 at run-time
 for example disables high-performance SSE2 code present in the crypto
 library. You might have to do this if target OpenSSL application is