rockchip: clk: Add rk3399 SARADC clock support

[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3399.c

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 10db46e400b85c623ba41587aa35feb1b4a4a580..50faf5d193563a05a693cd866e80e6f50f75dc91 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -12,6 +12,7 @@
 #include <errno.h>
 #include <mapmem.h>
 #include <syscon.h>
+#include <bitfield.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3399.h>
@@ -181,7 +182,8 @@ enum {
 
        /* CLKSEL_CON26 */
        CLK_SARADC_DIV_CON_SHIFT        = 8,
-       CLK_SARADC_DIV_CON_MASK         = 0xff << CLK_SARADC_DIV_CON_SHIFT,
+       CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
+       CLK_SARADC_DIV_CON_WIDTH        = 8,
 
        /* CLKSEL_CON27 */
        CLK_TSADC_SEL_X24M              = 0x0,
@@ -676,8 +678,8 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
        const struct spi_clkreg *spiclk = NULL;
        int src_clk_div;
 
-       src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
-       assert(src_clk_div < 127);
+       src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
+       assert(src_clk_div < 128);
 
        switch (clk_id) {
        case SCLK_SPI1 ... SCLK_SPI5:
@@ -750,18 +752,21 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
        case HCLK_SDMMC:
        case SCLK_SDMMC:
                con = readl(&cru->clksel_con[16]);
+               /* dwmmc controller have internal div 2 */
+               div = 2;
                break;
        case SCLK_EMMC:
                con = readl(&cru->clksel_con[21]);
+               div = 1;
                break;
        default:
                return -EINVAL;
        }
-       div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 
+       div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
        if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
                        == CLK_EMMC_PLL_SEL_24M)
-               return DIV_TO_RATE(24*1000*1000, div);
+               return DIV_TO_RATE(OSC_HZ, div);
        else
                return DIV_TO_RATE(GPLL_HZ, div);
 }
@@ -776,11 +781,13 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
        case HCLK_SDMMC:
        case SCLK_SDMMC:
                /* Select clk_sdmmc source from GPLL by default */
-               src_clk_div = GPLL_HZ / set_rate;
+               /* mmc clock defaulg div 2 internal, provide double in cru */
+               src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 
-               if (src_clk_div > 127) {
+               if (src_clk_div > 128) {
                        /* use 24MHz source for 400KHz clock */
-                       src_clk_div = 24*1000*1000 / set_rate;
+                       src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
+                       assert(src_clk_div - 1 < 128);
                        rk_clrsetreg(&cru->clksel_con[16],
                                     CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
                                     CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
@@ -794,8 +801,8 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
                break;
        case SCLK_EMMC:
                /* Select aclk_emmc source from GPLL */
-               src_clk_div = GPLL_HZ / aclk_emmc;
-               assert(src_clk_div - 1 < 31);
+               src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);
+               assert(src_clk_div - 1 < 32);
 
                rk_clrsetreg(&cru->clksel_con[21],
                             ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
@@ -803,8 +810,8 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
                             (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 
                /* Select clk_emmc source from GPLL too */
-               src_clk_div = GPLL_HZ / set_rate;
-               assert(src_clk_div - 1 < 127);
+               src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
+               assert(src_clk_div - 1 < 128);
 
                rk_clrsetreg(&cru->clksel_con[22],
                             CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
@@ -855,6 +862,32 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 
        return set_rate;
 }
+
+static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
+{
+       u32 div, val;
+
+       val = readl(&cru->clksel_con[26]);
+       div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+                              CLK_SARADC_DIV_CON_WIDTH);
+
+       return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
+{
+       int src_clk_div;
+
+       src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+       assert(src_clk_div < 128);
+
+       rk_clrsetreg(&cru->clksel_con[26],
+                    CLK_SARADC_DIV_CON_MASK,
+                    src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+       return rk3399_saradc_get_clk(cru);
+}
+
 static ulong rk3399_clk_get_rate(struct clk *clk)
 {
        struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
@@ -882,11 +915,17 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
        case SCLK_UART0:
        case SCLK_UART2:
                return 24000000;
+               break;
+       case PCLK_HDMI_CTRL:
+               break;
        case DCLK_VOP0:
        case DCLK_VOP1:
                break;
        case PCLK_EFUSE1024NS:
                break;
+       case SCLK_SARADC:
+               rate = rk3399_saradc_get_clk(priv->cru);
+               break;
        default:
                return -ENOENT;
        }
@@ -922,6 +961,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
        case SCLK_SPI0...SCLK_SPI5:
                ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
                break;
+       case PCLK_HDMI_CTRL:
+       case PCLK_VIO_GRF:
+               /* the PCLK gates for video are enabled by default */
+               break;
        case DCLK_VOP0:
        case DCLK_VOP1:
                ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
@@ -931,6 +974,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
                break;
        case PCLK_EFUSE1024NS:
                break;
+       case SCLK_SARADC:
+               ret = rk3399_saradc_set_clk(priv->cru, rate);
+               break;
        default:
                return -ENOENT;
        }
@@ -938,9 +984,24 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
        return ret;
 }
 
+static int rk3399_clk_enable(struct clk *clk)
+{
+       switch (clk->id) {
+       case HCLK_HOST0:
+       case HCLK_HOST0_ARB:
+       case HCLK_HOST1:
+       case HCLK_HOST1_ARB:
+               return 0;
+       }
+
+       debug("%s: unsupported clk %ld\n", __func__, clk->id);
+       return -ENOENT;
+}
+
 static struct clk_ops rk3399_clk_ops = {
        .get_rate = rk3399_clk_get_rate,
        .set_rate = rk3399_clk_set_rate,
+       .enable = rk3399_clk_enable,
 };
 
 static int rk3399_clk_probe(struct udevice *dev)
@@ -951,7 +1012,7 @@ static int rk3399_clk_probe(struct udevice *dev)
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3399_clk_plat *plat = dev_get_platdata(dev);
 
-       priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+       priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 #endif
        rkclk_init(priv->cru);
 #endif
@@ -963,7 +1024,7 @@ static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3399_clk_priv *priv = dev_get_priv(dev);
 
-       priv->cru = (struct rk3399_cru *)dev_get_addr(dev);
+       priv->cru = dev_read_addr_ptr(dev);
 #endif
        return 0;
 }
@@ -1133,7 +1194,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev)
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
 
-       priv->pmucru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+       priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 #endif
 
 #ifndef CONFIG_SPL_BUILD
@@ -1147,7 +1208,7 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
 
-       priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev);
+       priv->pmucru = dev_read_addr_ptr(dev);
 #endif
        return 0;
 }