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(parent: 615514c) | patch
rockchip: clk: Add rk3399 SARADC clock support
authorDavid Wu <david.wu@rock-chips.com>
Wed, 20 Sep 2017 06:38:58 +0000 (14:38 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sat, 30 Sep 2017 22:33:30 +0000 (00:33 +0200)
commit364fc7315aa0e6e20f604bb8b369b4bdc0dd8e8a
tree6bfd8955bddacb21b9769d900a3c7b9d061ad387tree | snapshot
parent615514c16dee4d43bd584ea326a5a56ebcb89c85commit | diff
rockchip: clk: Add rk3399 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
drivers/clk/rockchip/clk_rk3399.c diff | blob | blame | history
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