treewide: Remove clk_free

[thirdparty/u-boot.git] / drivers / i2c / designware_i2c.c

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index d95f77649e4aad9b1b6f59e6010b5c120d795028..29cf63375c7f173e71c8265f69ddd041c8fbc4f2 100644 (file)
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  */
 
 #include <common.h>
@@ -24,6 +24,17 @@
  */
 #define DW_I2C_COMP_TYPE       0x44570140
 
+/*
+ * This constant is used to calculate when during the clock high phase the data
+ * bit shall be read. The value was copied from the Linux v6.5 function
+ * i2c_dw_scl_hcnt() which provides the following explanation:
+ *
+ * "This is just an experimental rule: the tHD;STA period turned out to be
+ * proportinal to (_HCNT + 3). With this setting, we could meet both tHIGH and
+ * tHD;STA timing specs."
+ */
+#define T_HD_STA_OFFSET 3
+
 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
        u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -57,7 +68,7 @@ enum {
  *
  * @ic_clk: Input clock in Hz
  * @period_ns: Period to represent, in ns
- * @return calculated count
+ * Return: calculated count
  */
 static uint calc_counts(uint ic_clk, uint period_ns)
 {
@@ -123,7 +134,7 @@ static const struct i2c_mode_info info_for_mode[] = {
  * @ic_clk: IC clock speed in Hz
  * @spk_cnt: Spike-suppression count
  * @config: Returns value to use
- * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
+ * Return: 0 if OK, -EINVAL if the calculation failed due to invalid data
  */
 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
                              int ic_clk, int spk_cnt,
@@ -155,10 +166,10 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 
        /*
         * Back-solve for hcnt and lcnt according to the following equations:
-        * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
+        * SCL_High_time = [(HCNT + IC_*_SPKLEN + T_HD_STA_OFFSET) * ic_clk] + SCL_Fall_time
         * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
         */
-       hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
+       hcnt = min_thigh_cnt - fall_cnt - T_HD_STA_OFFSET - spk_cnt;
        lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 
        if (hcnt < 0 || lcnt < 0) {
@@ -170,13 +181,13 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
         * Now add things back up to ensure the period is hit. If it is off,
         * split the difference and bias to lcnt for remainder
         */
-       tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
+       tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1;
 
        if (tot < period_cnt) {
                diff = (period_cnt - tot) / 2;
                hcnt += diff;
                lcnt += diff;
-               tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
+               tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1;
                lcnt += period_cnt - tot;
        }
 
@@ -202,7 +213,7 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
  * @speed: Required i2c speed in Hz
  * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
  * @config: Returns the config to use for this speed
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
  */
 static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed,
                          ulong bus_clk, struct dw_i2c_speed_config *config)
@@ -271,7 +282,7 @@ static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed,
  * @i2c_base: Registers for the I2C controller
  * @speed: Required i2c speed in Hz
  * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
  */
 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
                                 unsigned int speed, unsigned int bus_clk)
@@ -759,7 +770,6 @@ int designware_i2c_of_to_plat(struct udevice *bus)
 
        ret = clk_enable(&priv->clk);
        if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
-               clk_free(&priv->clk);
                dev_err(bus, "failed to enable clock\n");
                return ret;
        }
@@ -792,7 +802,6 @@ int designware_i2c_remove(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(CLK)
        clk_disable(&priv->clk);
-       clk_free(&priv->clk);
 #endif
 
        return reset_release_bulk(&priv->resets);