rate = clk_get_rate(&clk);
printf("%s: %lu\n", clks[i].name, rate);
-
- clk_free(&clk);
}
return 0;
rate = clk_get_rate(&clk);
- clk_free(&clk);
-
if ((rate == (unsigned long)-ENOSYS) ||
(rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
struct uclass *uc;
struct udevice *dev = NULL;
struct clk clk = { 0 };
- ulong rate;
int ret;
/* Device addresses start at 1 */
if (ret)
return 0;
- rate = clk_get_rate(&clk);
-
- clk_free(&clk);
-
- return rate;
+ return clk_get_rate(&clk);
}
static u32 cm_get_rate_dm_khz(char *name)
rate = clk_get_rate(&clk);
- clk_free(&clk);
-
if ((rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
debug("%s id %u: clk_get_rate err: %ld\n",
gd->bd->bi_arm_freq = rate;
gd->cpu_clk = clk_get_rate(&clk);
}
-
- clk_free(&clk);
}
gd->bd->bi_dsp_freq = 0;
int ret;
struct udevice *dev;
struct clk clk;
- ulong rate;
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
if (ret < 0)
return ret;
- rate = clk_get_rate(&clk);
-
- clk_free(&clk);
-
- return rate;
+ return clk_get_rate(&clk);
}
static ulong clk_get_cpu_rate(void)
rate = clk_get_rate(&clk);
printf("CPU Speed: %lu MHz\n", rate / 1000000);
- clk_free(&clk);
-
return 0;
}
#endif
continue;
ret = clk_enable(&clk);
- clk_free(&clk);
if (ret)
return ret;
}
priv_rate = clk_get_rate(&clk);
- clk_free(&clk);
-
mhz_rate = ceil(priv_rate, HZ_IN_MHZ);
if (ctl & CLK_MHZ)
ret = clk_get_rate(&clk);
rate = ret;
- clk_free(&clk);
-
if (ret == -EINVAL) {
printf("clk ID %lu not supported yet\n",
aspeed_clk_names[i].id);
{
struct udevice *dev;
struct clk clk_dev;
- ulong clk_rate;
int ret;
dev = dev_get_parent(clk->dev);
if (ret)
return ret;
- clk_rate = clk_get_rate(&clk_dev);
-
- clk_free(&clk_dev);
-
- return clk_rate;
+ return clk_get_rate(&clk_dev);
}
static struct clk_ops periph_clk_ops = {
struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk parent;
- ulong clk_rate;
u32 tmp, gckdiv;
u8 clock_source, parent_index;
int ret;
if (ret)
return 0;
- clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
-
- clk_free(&parent);
-
- return clk_rate;
+ return clk_get_rate(&parent) / (gckdiv + 1);
}
static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
ret = clk_disable(&clk[i]);
if (ret && ret != -ENOSYS)
return ret;
-
- clk_free(&clk[i]);
}
return 0;
return false;
}
-static void devm_clk_release(struct udevice *dev, void *res)
-{
- clk_free(res);
-}
-
-static int devm_clk_match(struct udevice *dev, void *res, void *data)
-{
- return res == data;
-}
-
struct clk *devm_clk_get(struct udevice *dev, const char *id)
{
int rc;
struct clk *clk;
- clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
+ clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
if (unlikely(!clk))
return ERR_PTR(-ENOMEM);
if (rc)
return ERR_PTR(rc);
- devres_add(dev, clk);
return clk;
}
-void devm_clk_put(struct udevice *dev, struct clk *clk)
-{
- int rc;
-
- if (!clk)
- return;
-
- rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
- WARN_ON(rc);
-}
-
int clk_uclass_post_probe(struct udevice *dev)
{
/*
ret = clk_enable(&clk_in1);
if (ret) {
dev_err(dev, "failed to enable clock\n");
- clk_free(&clk_in1);
return ret;
}
return 0;
free_out:
- for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
- clk_free(&vc5->clk_out[n].hw);
+ for (n = 1; n < vc5->chip_info->clk_out_cnt; n++)
free(out_name[n]);
- }
free_selb:
- clk_free(&vc5->clk_out[0].hw);
free(outsel_name);
free_fod:
- for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
- clk_free(&vc5->clk_fod[n].hw);
+ for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++)
free(fod_name[n]);
- }
free_pll:
- clk_free(&vc5->clk_pll.hw);
free(pll_name);
free_pfd:
- clk_free(&vc5->clk_pfd);
free(pfd_name);
free_mux:
- clk_free(&vc5->clk_mux);
free(mux_name);
return ret;
rate = clk_get_rate(&clk);
- clk_free(&clk);
-
if ((rate == (unsigned long)-ENOSYS) ||
(rate == (unsigned long)-ENXIO))
printf("%10s%20s\n", name, "unknown");
rate = clk_get_rate(&clk);
- clk_free(&clk);
-
if ((rate == (unsigned long)-ENOSYS) ||
(rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO))
ret = clk_get_rate(&clk);
rate = ret;
- clk_free(&clk);
-
if (ret == -EINVAL) {
printf("clk ID %lu not supported yet\n",
imx8_clk_names[i].id);
if (parent->dev != check_parent.dev)
ret = -EINVAL;
- clk_free(&check_parent);
if (ret < 0)
return ret;
}
priv->parents[i] = clk_get_rate(&clk);
- clk_free(&clk);
}
return 0;
ret = clk_get_rate(&clk);
if (!IS_ERR_VALUE(ret))
info->cpu_freq = ret;
- clk_free(&clk);
}
if (!info->cpu_freq)
return 0;
ret = clk_enable(&clk);
- clk_free(&clk);
if (ret == -ENOSYS || ret == -ENOTSUPP)
return 0;
else
pr_err("error enabling clock %d\n", i);
return ret;
}
-
- clk_free(&clk);
}
/* try to perform resets */
if (ret)
return ret;
- clk_free(&clk);
-
#if CONFIG_IS_ENABLED(OF_CONTROL)
plat->base_addr = dev_read_addr(dev);
#endif
if (ret)
return ret;
- clk_free(&clk);
-
addr_base = dev_read_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
}
ret = clk_enable(&clk);
- clk_free(&clk);
if (ret) {
dev_err(dev, "Failed to enable GPIO bank clock\n");
return ret;
if (ret)
return ret;
- ret = clk_enable(&clk);
- if (ret)
- clk_free(&clk);
-
- return ret;
+ return clk_enable(&clk);
}
static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = {
bus->bus_clk_rate = clk_rate;
- clk_free(&clk);
-
return 0;
}
ret = clk_enable(&priv->clk);
if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
- clk_free(&priv->clk);
dev_err(bus, "failed to enable clock\n");
return ret;
}
#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk);
- clk_free(&priv->clk);
#endif
return reset_release_bulk(&priv->resets);
if (!clk_rate)
return -EINVAL;
- clk_free(&bus->i2c_clk);
-
divisor = clk_rate / bus->clk_rate;
ctrl = readl(bus->base + MPFS_I2C_CTRL);
printf("%s: fail to get rate\n", __func__);
return -EINVAL;
}
- clk_free(&clk);
bus->num = dev->seq_;
bus->reg = dev_read_addr_ptr(dev);
bus->ip_clk_khz = clk_rate / 1000;
- clk_free(&bus->clk);
-
return 0;
}
ret = clk_enable(&i2c_priv->clk);
if (ret)
- goto clk_free;
+ return ret;
ret = reset_get_by_index(dev, 0, &reset_ctl);
if (ret)
clk_disable:
clk_disable(&i2c_priv->clk);
-clk_free:
- clk_free(&i2c_priv->clk);
return ret;
}
ret = clk_enable(&clk);
if (ret)
- goto clk_free;
+ return ret;
/* get channel number */
ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
ipcc->n_chans &= IPCFGR_CHAN_MASK;
return 0;
-
-clk_free:
- clk_free(&clk);
-
- return ret;
}
static const struct udevice_id stm32_ipcc_ids[] = {
}
rate = clk_get_rate(&clk);
- clk_free(&clk);
if (!rate || IS_ERR_VALUE(rate)) {
ret = rate ? rate : -ENOENT;
dev_dbg(dev, "could not get clock rate (err %d)\n",
ret = clk_enable(&clk);
if (ret) {
- clk_free(&clk);
dev_err(dev, "failed to enable clock\n");
return ret;
}
ret = clk_enable(&clk);
if (ret) {
debug("%s: clock enable failed %d\n", __func__, ret);
- goto free;
+ return ret;
}
host->name = dev->name;
err:
clk_disable(&clk);
-free:
- clk_free(&clk);
return ret;
}
host->ops = &atmel_sdhci_ops;
upriv->mmc = host->mmc;
- clk_free(&clk);
-
ret = sdhci_probe(dev);
if (ret)
return ret;
int ret = 0;
ret = clk_get_by_index(dev, 0, &clk);
- if (ret) {
- ret = -EINVAL;
- goto failed;
- }
+ if (ret)
+ return -EINVAL;
ret = clk_enable(&clk);
if (ret)
- goto failed;
+ return ret;
clk_rate = clk_get_rate(&clk);
- if (!clk_rate) {
- ret = -EINVAL;
- goto failed;
- }
+ if (!clk_rate)
+ return -EINVAL;
priv->bus_clk_rate = clk_rate;
-failed:
- clk_free(&clk);
-
- return ret;
+ return 0;
}
static int atmel_mci_probe(struct udevice *dev)
return ret;
ret = clk_set_rate(&clk, clk_rate);
- clk_free(&clk);
if (ret < 0)
return ret;
return ret;
clk_rate = clk_get_rate(&clk);
- clk_free(&clk);
if (IS_ERR_VALUE(clk_rate))
return clk_rate;
ret = clk_get_by_name(dev, "cd", &imclk2);
if (ret < 0) {
dev_err(dev, "failed to get imclk2 (chip detect clk)\n");
- goto err_get_imclk2;
+ return ret;
}
ret = clk_get_by_name(dev, "aclk", &aclk);
if (ret < 0) {
dev_err(dev, "failed to get aclk\n");
- goto err_get_aclk;
+ return ret;
}
ret = clk_enable(&imclk2);
if (ret < 0) {
dev_err(dev, "failed to enable imclk2 (chip detect clk)\n");
- goto err_imclk2;
+ return ret;
}
ret = clk_enable(&aclk);
clk_disable(&aclk);
err_aclk:
clk_disable(&imclk2);
-err_imclk2:
- clk_free(&aclk);
-err_get_aclk:
- clk_free(&imclk2);
-err_get_imclk2:
return ret;
}
ret = clk_set_rate(&priv->clkh, 800000000);
if (ret < 0) {
dev_err(dev, "failed to set rate for SDnH clock (%d)\n", ret);
- goto err_clk;
+ return ret;
}
}
ret = clk_set_rate(&priv->clk, 200000000);
if (ret < 0) {
dev_err(dev, "failed to set rate for SDn clock (%d)\n", ret);
- goto err_clkh;
+ return ret;
}
ret = clk_enable(&priv->clk);
if (ret) {
dev_err(dev, "failed to enable SDn clock (%d)\n", ret);
- goto err_clkh;
+ return ret;
}
if (device_is_compatible(dev, "renesas,sdhi-r9a07g044"))
err_tmio_probe:
clk_disable(&priv->clk);
-err_clkh:
- clk_free(&priv->clkh);
-err_clk:
- clk_free(&priv->clk);
return ret;
}
ret = clk_enable(&clk_ciu);
if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
- goto clk_err_ciu;
+ goto clk_err;
host->bus_hz = clk_get_rate(&clk_ciu);
if (host->bus_hz < CLOCK_MIN) {
ret = clk_enable(&clk_biu);
if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
- goto clk_err_biu;
+ goto clk_err_ciu_dis;
return 0;
-clk_err_biu:
- clk_free(&clk_biu);
clk_err_ciu_dis:
clk_disable(&clk_ciu);
-clk_err_ciu:
- clk_free(&clk_ciu);
clk_err:
dev_err(dev, "failed to setup clocks, ret %d\n", ret);
host->bus_hz = clk_get_rate(&clk);
- clk_free(&clk);
#else
/* Fixed clock divide by 4 which due to the SDMMC wrapper */
host->bus_hz = cm_get_mmc_controller_clk_hz();
int ret;
ret = clk_enable(&plat->clk);
- if (ret) {
- clk_free(&plat->clk);
+ if (ret)
return ret;
- }
upriv->mmc = &plat->mmc;
ret = clk_set_rate(&priv->clk, ULONG_MAX);
if (ret < 0) {
dev_err(dev, "failed to set rate for host clock\n");
- clk_free(&priv->clk);
return ret;
}
hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
- if (hsmc_nc->clk) {
+ if (hsmc_nc->clk)
clk_disable_unprepare(hsmc_nc->clk);
- devm_clk_put(nc->dev, hsmc_nc->clk);
- }
return 0;
}
}
ret = clk_enable(&clk);
- clk_free(&clk);
if (ret) {
dev_err(dev, "Failed to enable RPC clock\n");
return ret;
pr_err("%s: error enabling clock %d\n", __func__, i);
return ret;
}
-
- clk_free(&clk);
}
/* try to perform resets */
pr_err("%s: error enabling clock %d\n", __func__, i);
return ret;
}
-
- clk_free(&clk);
}
/* try to perform resets */
err = clk_enable(&priv->clocks[i]);
if (err && err != -ENOSYS && err != -ENOTSUPP) {
pr_err("failed to enable clock %d\n", i);
- clk_free(&priv->clocks[i]);
goto clk_err;
}
priv->clock_count++;
ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
if (ret) {
pr_err("clk_get_by_name(master_bus) failed: %d", ret);
- goto err_free_clk_slave_bus;
+ goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
if (ret) {
pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
+ goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
if (ret) {
pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
- goto err_free_clk_rx;
+ goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
if (ret) {
pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_ptp_ref;
+ goto err_free_gpio_phy_reset;
}
debug("%s: OK\n", __func__);
return 0;
-err_free_clk_ptp_ref:
- clk_free(&eqos->clk_ptp_ref);
-err_free_clk_rx:
- clk_free(&eqos->clk_rx);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
-err_free_clk_slave_bus:
- clk_free(&eqos->clk_slave_bus);
err_free_gpio_phy_reset:
dm_gpio_free(dev, &eqos->phy_reset_gpio);
err_free_reset_eqos:
ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
if (ret) {
pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
+ goto err_probe;
}
ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
if (ret) {
pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_rx;
+ goto err_probe;
}
/* Get ETH_CLK clocks (optional) */
debug("%s: OK\n", __func__);
return 0;
-err_free_clk_rx:
- clk_free(&eqos->clk_rx);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
err_probe:
debug("%s: returns %d\n", __func__, ret);
debug("%s(dev=%p):\n", __func__, dev);
-#ifdef CONFIG_CLK
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_ptp_ref);
- clk_free(&eqos->clk_rx);
- clk_free(&eqos->clk_slave_bus);
- clk_free(&eqos->clk_master_bus);
-#endif
dm_gpio_free(dev, &eqos->phy_reset_gpio);
reset_free(&eqos->reset_ctl);
static int eqos_remove_resources_stm32(struct udevice *dev)
{
- struct eqos_priv * __maybe_unused eqos = dev_get_priv(dev);
-
debug("%s(dev=%p):\n", __func__, dev);
-
-#ifdef CONFIG_CLK
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_rx);
- clk_free(&eqos->clk_master_bus);
- if (clk_valid(&eqos->clk_ck))
- clk_free(&eqos->clk_ck);
-#endif
-
- debug("%s: OK\n", __func__);
return 0;
}
ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
if (ret) {
dev_dbg(dev, "clk_get_by_name(ptp_ref) failed: %d", ret);
- goto err_free_clk_master_bus;
+ goto err_probe;
}
ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
if (ret) {
dev_dbg(dev, "clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_ptp_ref;
+ goto err_probe;
}
ret = clk_get_by_name(dev, "pclk", &eqos->clk_ck);
if (ret) {
dev_dbg(dev, "clk_get_by_name(pclk) failed: %d", ret);
- goto err_free_clk_tx;
+ goto err_probe;
}
debug("%s: OK\n", __func__);
return 0;
-err_free_clk_tx:
- clk_free(&eqos->clk_tx);
-err_free_clk_ptp_ref:
- clk_free(&eqos->clk_ptp_ref);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
err_probe:
debug("%s: returns %d\n", __func__, ret);
static int eqos_remove_resources_imx(struct udevice *dev)
{
- struct eqos_priv *eqos = dev_get_priv(dev);
-
debug("%s(dev=%p):\n", __func__, dev);
-
- clk_free(&eqos->clk_ck);
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_ptp_ref);
- clk_free(&eqos->clk_master_bus);
-
- debug("%s: OK\n", __func__);
return 0;
}
debug("%s(dev=%p):\n", __func__, dev);
- clk_free(&eqos->clk_tx);
dm_gpio_free(dev, &eqos->phy_reset_gpio);
reset_free(&eqos->reset_ctl);
ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
if (ret) {
dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
- goto err_free_clk_master_bus;
+ goto err_release_resets;
}
}
return 0;
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
err_release_resets:
reset_release_bulk(&data->resets);
err_free:
if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
dm_gpio_free(dev, &eqos->phy_reset_gpio);
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_master_bus);
reset_release_bulk(&data->resets);
free(data);
if (ret) {
dev_err(dev, "Failed to get clocks property: %d\n",
ret);
- goto out_clk_free;
+ return ret;
}
priv->nclks++;
}
out_reset_free:
while (--nr >= 0)
reset_free(&priv->rst[nr]);
-out_clk_free:
- while (--nc >= 0)
- clk_free(&priv->clk[nc]);
return ret;
}
cpsw_common->bus_freq);
out:
- clk_free(&cpsw_common->fclk);
power_domain_free(&cpsw_common->pwrdmn);
return ret;
}
if (ret < 0)
return ret;
- clk_free(&clk);
-
/* enable power domain */
ret = power_domain_get(dev, &pwr_dom);
if (ret < 0)
if (ret < 0)
return ret;
- clk_free(&clk);
-
/* perform reset */
ret = reset_get_by_index(dev, 0, &rst_ctl);
if (ret < 0)
if (ret < 0)
return ret;
- clk_free(&clk);
-
#if defined(CONFIG_POWER_DOMAIN)
/* enable power domain */
ret = power_domain_get(dev, &pwr_dom);
ret = clk_enable(&clk);
if (ret < 0)
return ret;
-
- clk_free(&clk);
}
mdelay(100);
ret = clk_enable(&priv->clk);
if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
pr_err("failed to enable PHY clock\n");
- clk_free(&priv->clk);
return ret;
}
#endif
ret = clk_enable(&priv->clk);
if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
pr_err("failed to enable PHY clock\n");
- clk_free(&priv->clk);
return ret;
}
#endif
ret = clk_enable(&priv->clk);
if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
pr_err("failed to enable PHY clock\n");
- clk_free(&priv->clk);
return ret;
}
#endif
struct rcar_gen2_phy *priv = dev_get_priv(dev);
clk_disable(&priv->clk);
- clk_free(&priv->clk);
return 0;
}
struct rcar_gen3_phy *priv = dev_get_priv(dev);
clk_disable(&priv->clk);
- clk_free(&priv->clk);
return 0;
}
ret = clk_enable(&priv->clk);
if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
- goto err;
+ return ret;
ret = dev_read_phandle_with_args(dev, "canaan,k210-sysctl-power",
NULL, 1, 0, &args);
if (ret)
- goto err;
+ return ret;
- if (args.args_count != 1) {
- ret = -EINVAL;
- goto err;
- }
+ if (args.args_count != 1)
+ return -EINVAL;
priv->sysctl = syscon_node_to_regmap(args.node);
- if (IS_ERR(priv->sysctl)) {
- ret = PTR_ERR(priv->sysctl);
- goto err;
- }
+ if (IS_ERR(priv->sysctl))
+ return PTR_ERR(priv->sysctl);
priv->power_offset = args.args[0];
}
return 0;
-
-err:
- clk_free(&priv->clk);
- return ret;
}
static const struct udevice_id k210_pc_ids[] = {
ret = power_domain_get_by_name(dev, &priv->pd_bus, "bus");
if (ret < 0)
- goto err_pd_bus;
+ return ret;
ret = power_domain_get_by_name(dev, &priv->pd_usb, "usb");
if (ret < 0)
power_domain_free(&priv->pd_usb);
err_pd_usb:
power_domain_free(&priv->pd_bus);
-err_pd_bus:
- clk_free(&priv->clk_usb);
return ret;
}
return ret;
ret = clk_enable(&clk);
- if (ret) {
- clk_free(&clk);
+ if (ret)
return ret;
- }
rate = clk_get_rate(&clk);
unlock:
stm32_rtc_lock(dev);
- if (ret) {
+ if (ret)
clk_disable(&clk);
- clk_free(&clk);
- }
return ret;
}
return ret;
ret = clk_enable(&clk);
- if (ret) {
- clk_free(&clk);
+ if (ret)
return ret;
- }
ret = stm32_rtc_init(dev);
- if (ret) {
+ if (ret)
clk_disable(&clk);
- clk_free(&clk);
- }
return ret;
}
priv->usart_clk_rate = clk_rate;
- clk_free(&clk);
-
return 0;
}
#endif
if (ret < 0)
return ret;
priv->uartclk = clk_get_rate(&clk);
- clk_free(&clk);
/* initialize serial */
return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
return ret;
ret = clk_set_rate(&clk, clk_rate);
- clk_free(&clk);
if (ret < 0)
return ret;
if (ret < 0)
return ret;
priv->uartclk = clk_get_rate(&clk);
- clk_free(&clk);
/* initialize serial */
return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
return -EINVAL;
ns->clock = clk_rate;
- clk_free(&clk);
return 0;
}
ret = clk_enable(&gclk);
if (ret)
dev_err(bus, "Failed to enable QSPI generic clock\n");
- clk_free(&gclk);
return ret;
}
ret = clk_enable(&pclk);
if (ret) {
dev_err(dev, "Failed to enable QSPI peripheral clock\n");
- goto free_pclk;
+ return ret;
}
if (aq->caps->has_qspick) {
ret = clk_get_by_name(dev, "qspick", &qspick);
if (ret) {
dev_err(dev, "Missing QSPI peripheral clock\n");
- goto free_pclk;
+ return ret;
}
ret = clk_enable(&qspick);
if (ret)
dev_err(dev, "Failed to enable QSPI system clock\n");
- clk_free(&qspick);
} else if (aq->caps->has_gclk) {
ret = clk_get_by_name(dev, "gclk", &gclk);
if (ret) {
dev_err(dev, "Missing QSPI generic clock\n");
- goto free_pclk;
+ return ret;
}
ret = clk_enable(&gclk);
if (ret)
dev_err(dev, "Failed to enable QSPI system clock\n");
- clk_free(&gclk);
}
aq->bus_clk_rate = clk_get_rate(&pclk);
if (!aq->bus_clk_rate)
- ret = -EINVAL;
-
-free_pclk:
- clk_free(&pclk);
+ return -EINVAL;
return ret;
}
priv->bus_clk_rate = clk_rate;
- clk_free(&clk);
-
return 0;
}
if (ret < 0 && ret != -ENOSYS)
return ret;
- clk_free(&clk);
-
/* get clock rate */
ret = clk_get_by_name(dev, "pll", &clk);
if (ret < 0 && ret != -ENOSYS)
priv->clk_rate = clk_get_rate(&clk);
- clk_free(&clk);
-
/* perform reset */
ret = reset_get_by_index(dev, 0, &rst_ctl);
if (ret >= 0) {
if (ret < 0)
return ret;
- clk_free(&clk);
-
/* perform reset */
ret = reset_get_by_index(dev, 0, &rst_ctl);
if (ret < 0)
if (ret < 0 && ret != -ENOSYS)
return ret;
- clk_free(&clk);
-
/* get clock rate */
ret = clk_get_by_name(dev, "pll", &clk);
if (ret < 0 && ret != -ENOSYS)
priv->clk_rate = clk_get_rate(&clk);
- clk_free(&clk);
-
/* initialize hardware */
writel(0, priv->regs + SPI_IR_MASK_REG);
#endif
} else {
priv->ref_clk_hz = clk_get_rate(&clk);
- clk_free(&clk);
if (IS_ERR_VALUE(priv->ref_clk_hz))
return priv->ref_clk_hz;
}
err_rate:
clk_disable(&priv->clk);
- clk_free(&priv->clk);
return -EINVAL;
}
ret = clk_disable(&priv->clk);
if (ret)
return ret;
-
- clk_free(&priv->clk);
- if (ret)
- return ret;
#endif
return 0;
}
return 0;
}
-static int amlogic_spifc_a1_remove(struct udevice *dev)
-{
- struct amlogic_spifc_a1 *spifc = dev_get_priv(dev);
-
- clk_free(&spifc->clk);
-
- return 0;
-}
-
static const struct udevice_id meson_spifc_ids[] = {
{ .compatible = "amlogic,a1-spifc", },
{ }
.of_match = meson_spifc_ids,
.ops = &amlogic_spifc_a1_ops,
.probe = amlogic_spifc_a1_probe,
- .remove = amlogic_spifc_a1_remove,
.priv_auto = sizeof(struct amlogic_spifc_a1),
};
return 0;
}
-static int mvebu_spi_remove(struct udevice *bus)
-{
- struct mvebu_spi_plat *plat = dev_get_plat(bus);
-
- clk_free(&plat->clk);
-
- return 0;
-}
-
static const struct dm_spi_ops mvebu_spi_ops = {
.xfer = mvebu_spi_xfer,
.set_speed = mvebu_spi_set_speed,
.of_to_plat = mvebu_spi_of_to_plat,
.plat_auto = sizeof(struct mvebu_spi_plat),
.probe = mvebu_spi_probe,
- .remove = mvebu_spi_remove,
};
}
plat->hclk_rate = clk_get_rate(&hclk);
- clk_free(&hclk);
dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n",
(u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz);
ret = reset_get_by_index(dev, 0, &plat->rst_ctl);
if (ret < 0)
- goto clk_err;
+ return ret;
ret = gpio_request_list_by_name(dev, "cs-gpios", plat->cs_gpios,
ARRAY_SIZE(plat->cs_gpios), 0);
if (ret < 0) {
dev_err(dev, "Can't get %s cs gpios: %d", dev->name, ret);
- ret = -ENOENT;
- goto clk_err;
+ return -ENOENT;
}
return 0;
-
-clk_err:
- clk_free(&plat->clk);
-
- return ret;
}
static int stm32_spi_probe(struct udevice *dev)
clk_err:
clk_disable(&plat->clk);
- clk_free(&plat->clk);
return ret;
};
reset_free(&plat->rst_ctl);
- ret = clk_disable(&plat->clk);
- if (ret < 0)
- return ret;
-
- clk_free(&plat->clk);
-
- return ret;
+ return clk_disable(&plat->clk);
};
static const struct dm_spi_ops stm32_spi_ops = {
return ret;
uc_priv->clock_rate = clk_get_rate(&clk);
-
- clk_free(&clk);
}
/* init timer */
return ret;
uc_priv->clock_rate = clk_get_rate(&clk);
-
- clk_free(&clk);
#else
uc_priv->clock_rate = get_board_sys_clk() / 2;
#endif
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&priv->clk);
- if (ret) {
- clk_free(&priv->clk);
+ if (ret)
return ret;
- }
#endif
return 0;
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&priv->clk);
- if (ret) {
- clk_free(&priv->clk);
+ if (ret)
return ret;
- }
#endif
return 0;
if (ret)
return -EINVAL;
- ret = clk_enable(&clk);
- if (ret)
- return ret;
-
- clk_free(&clk);
-
- return 0;
+ return clk_enable(&clk);
}
static int ehci_atmel_probe(struct udevice *dev)
err = clk_enable(&priv->clocks[i]);
if (err) {
dev_err(dev, "failed to enable clock %d\n", i);
- clk_free(&priv->clocks[i]);
goto clk_err;
}
priv->clock_count++;
ret = clk_enable(&plat->clk);
if (ret) {
dev_err(dev, "Failed to enable USB3 clock\n");
- goto err_clk;
+ return ret;
}
ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
err_fw:
clk_disable(&plat->clk);
-err_clk:
- clk_free(&plat->clk);
return ret;
}
ret = xhci_deregister(dev);
clk_disable(&plat->clk);
- clk_free(&plat->clk);
return ret;
}
priv->clk_rate = clk_rate;
- clk_free(&clk);
-
return 0;
}
err = malidp_setup_mode(priv, &timings);
if (err)
- goto fail_timings;
+ return err;
malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1,
(phys_addr_t)uc_plat->base);
err = malidp_leave_config(priv);
if (err)
- goto fail_timings;
+ return err;
malidp_set_configvalid(priv);
return 0;
-
-fail_timings:
- clk_free(&priv->aclk);
-fail_aclk:
- clk_free(&priv->pxlclk);
-
- return err;
}
static int malidp_bind(struct udevice *dev)
* monitor wants
*/
ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
- if (ret >= 0) {
+ if (ret >= 0)
ret = clk_set_rate(&clk, 384000000);
- clk_free(&clk);
- }
if (ret < 0) {
debug("%s: Failed to set clock in source device '%s': ret=%d\n",
__func__, uc_plat->src_dev->name, ret);
if (edp_data->chip_type == RK3288_DP) {
ret = clk_get_by_index(dev, 1, &clk);
- if (ret >= 0) {
+ if (ret >= 0)
ret = clk_set_rate(&clk, 0);
- clk_free(&clk);
- }
if (ret) {
debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
return ret;
}
}
ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
- if (ret >= 0) {
+ if (ret >= 0)
ret = clk_set_rate(&clk, 192000000);
- clk_free(&clk);
- }
if (ret < 0) {
debug("%s: Failed to set clock in source device '%s': ret=%d\n",
__func__, uc_plat->src_dev->name, ret);
ret = clk_enable(&clk);
if (ret)
- goto err;
+ return ret;
priv->clk_khz = clk_get_rate(&clk) / 1000;
- if (!priv->clk_khz) {
- ret = -EINVAL;
- goto err;
- }
+ if (!priv->clk_khz)
+ return -EINVAL;
#else
priv->clk_khz = CFG_DW_WDT_CLOCK_KHZ;
#endif
ofnode_read_prop(dev_ofnode(dev), "resets", &ret)) {
ret = reset_get_bulk(dev, &priv->resets);
if (ret)
- goto err;
+ return ret;
ret = reset_deassert_bulk(&priv->resets);
if (ret)
- goto err;
+ return ret;
}
/* reset to disable the watchdog */
return designware_wdt_stop(dev);
-
-err:
-#if CONFIG_IS_ENABLED(CLK)
- clk_free(&clk);
-#endif
- return ret;
}
static const struct wdt_ops designware_wdt_ops = {
return ret;
ret = clk_enable(&clk);
- if (ret) {
- clk_free(&clk);
+ if (ret)
return ret;
- }
/* Setup with 1ms timebase */
writel(((clk_get_rate(&clk) / 1000) & GXBB_WDT_CTRL_DIV_MASK) |
*/
int clk_release_all(struct clk *clk, unsigned int count);
-/**
- * devm_clk_put - "free" a managed clock source
- * @dev: device used to acquire the clock
- * @clk: clock source acquired with devm_clk_get()
- *
- * Note: drivers must ensure that all clk_enable calls made on this
- * clock source are balanced by clk_disable calls prior to calling
- * this function.
- *
- * clk_put should not be called from within interrupt context.
- */
-void devm_clk_put(struct udevice *dev, struct clk *clk);
-
#else
static inline int clk_get_by_phandle(struct udevice *dev, const
{
return -ENOSYS;
}
-
-static inline void devm_clk_put(struct udevice *dev, struct clk *clk)
-{
-}
#endif
/**
return clk_release_all(bulk->clks, bulk->count);
}
-static inline void clk_free(struct clk *clk)
-{
-}
-
#if CONFIG_IS_ENABLED(CLK)
/**
* clk_request() - Request a clock by provider-specific ID.
projects / thirdparty / u-boot.git / commitdiff
