+2020-05-17 Jeff Law <law@redhat.com>
+
+ * config/h8300/predicates.md (pc_or_label_operand): New predicate.
+ * config/h8300/jumpcall.md (branch_true, branch_false): Consolidate
+ into a single pattern using pc_or_label_operand.
+ * config/h8300/combiner.md (bit branch patterns): Likewise.
+ * config/h8300/peepholes.md (HImode and SImode branches): Likewise.
+
+2020-05-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/95021
+ * config/i386/i386-features.c (has_non_address_hard_reg):
+ Renamed to ...
+ (pseudo_reg_set): This. Return the SET expression. Ignore
+ pseudo register push.
+ (general_scalar_to_vector_candidate_p): Combine single_set and
+ has_non_address_hard_reg calls to pseudo_reg_set.
+ (timode_scalar_to_vector_candidate_p): Likewise.
+ * config/i386/i386.md (*pushv1ti2): New pattern.
+
+2020-05-17 Aldy Hernandez <aldyh@redhat.com>
+
+ Revert:
+ 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (operand_less_p): Move to...
+ * vr-values.c (operand_less_p): ...here.
+ * tree-vrp.h (operand_less_p): Remove.
+
+2020-05-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (operand_less_p): Move to...
+ * vr-values.c (operand_less_p): ...here.
+ * tree-vrp.h (operand_less_p): Remove.
+
+2020-05-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (class vrp_insert): Remove prototype for
+ live_on_edge.
+
+2020-05-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (class live_names): New.
+ (live_on_edge): Move into live_names.
+ (build_assert_expr_for): Move into vrp_insert.
+ (find_assert_locations_in_bb): Rename from
+ find_assert_locations_1.
+ (process_assert_insertions_for): Move into vrp_insert.
+ (compare_assert_loc): Same.
+ (remove_range_assertions): Same.
+ (dump_asserts_for): Rename to vrp_insert::dump.
+ (debug_asserts_for): Rename to vrp_insert::debug.
+ (dump_all_asserts): Rename to vrp_insert::dump.
+ (debug_all_asserts): Rename to vrp_insert::debug.
+
+2020-05-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (class vrp_prop): Move check_all_array_refs,
+ check_array_ref, check_mem_ref, and search_for_addr_array
+ into new class...
+ (class array_bounds_checker): ...here.
+ (class check_array_bounds_dom_walker): Adjust to use
+ array_bounds_checker.
+ (check_all_array_refs): Move into array_bounds_checker and rename
+ to check.
+ (class vrp_folder): Make fold_predicate_in private.
+
+2020-05-15 Jeff Law <law@redhat.com>
+
+ * config/h8300/h8300.md (SFI iterator): New iterator for
+ SFmode and SImode.
+ * config/h8300/peepholes.md (memory comparison): Use mode
+ iterator to consolidate 3 patterns into one.
+ (stack allocation and stack store): Handle SFmode. Handle
+ 8 byte allocations.
+
+2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_2): Also require
+ RS6000_BTM_POWERPC64.
+
+2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (SWI48DWI): New mode iterator.
+ (*push<mode>2): Allow XMM registers.
+ (*pushdi2_rex64): Ditto.
+ (*pushsi2_rex64): Ditto.
+ (*pushsi2): Ditto.
+ (push XMM reg splitter): New splitter
+
+ (*pushdf) Change "x" operand constraint to "v".
+ (*pushsf_rex64): Ditto.
+ (*pushsf): Ditto.
+
+2020-05-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92260
+ * tree-vect-slp.c (vect_get_constant_vectors): Compute
+ the number of vector stmts in a canonical way.
+
+2020-05-15 Martin Liska <mliska@suse.cz>
+
+ * hsa-gen.c (get_symbol_for_decl): Fix misleading indentation
+ warning.
+
+2020-05-15 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
+
+2020-05-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/95133
+ * gimple-ssa-split-paths.c
+ (find_block_to_duplicate_for_splitting_paths): Check for
+ normal edges.
+
+2020-05-15 Christophe Lyon <christophe.lyon@linaro.org>
+
+ * config/arm/arm.c (reg_needs_saving_p): Add support for interrupt
+ routines.
+ (arm_compute_save_reg0_reg12_mask): Use reg_needs_saving_p.
+
+2020-05-15 Tobias Burnus <tobias@codesourcery.com>
+
+ PR middle-end/94635
+ * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with
+ OMP_TARGET_EXIT_DATA, use 'release:' unless the associated
+ item is 'delete:'.
+
+2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/i386.md (isa): Add sse3_noavx.
+ (enabled): Handle sse3_noavx.
+
+ * config/i386/mmx.md (mmx_haddv2sf3): New expander.
+ (*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX
+ alternatives. Match commutative vec_select selector operands.
+ (*mmx_haddv2sf3_low): New insn pattern.
+
+ (*mmx_hsubv2sf3): Add SSE/AVX alternatives.
+ (*mmx_hsubv2sf3_low): New insn pattern.
+
+2020-05-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/33315
+ * tree-ssa-sink.c: Include tree-eh.h.
+ (sink_stats): Add commoned member.
+ (sink_common_stores_to_bb): New function implementing store
+ commoning by sinking to the successor.
+ (sink_code_in_bb): Call it, pass down TODO_cleanup_cfg returned.
+ (pass_sink_code::execute): Likewise. Record commoned stores
+ in statistics.
+
+2020-05-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
+
+ PR rtl-optimization/37451, part of PR target/61837
+ * loop-doloop.c (doloop_simplify_count): New function. Simplify
+ (add -1; zero_ext; add +1) to zero_ext when not wrapping.
+ (doloop_modify): Call doloop_simplify_count.
+
+2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR jit/94778
+ * doc/sourcebuild.texi: Document effective target lgccjit.
+
+2020-05-14 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a
+ define_expand, and rename the original to ...
+ (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand.
+ (add<mode>3_zext_dup_exec): Likewise, with ...
+ (add<mode>3_vcc_zext_dup_exec): ... this.
+ (add<mode>3_zext_dup2): Likewise, with ...
+ (add<mode>3_zext_dup_exec): ... this.
+ (add<mode>3_zext_dup2_exec): Likewise, with ...
+ (add<mode>3_zext_dup2): ... this.
+ * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch
+ addv64di3_zext* calls to use addv64di3_vcc_zext*.
+
+2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/sse.md (truncv2dfv2df2): New insn pattern.
+ (extendv2sfv2df2): Ditto.
+
+2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
+
+ * config/arm/arm.c (reg_needs_saving_p): New function.
+ (use_return_insn): Use reg_needs_saving_p.
+ (arm_get_vfp_saved_size): Likewise.
+ (arm_compute_frame_layout): Likewise.
+ (arm_save_coproc_regs): Likewise.
+ (thumb1_expand_epilogue): Likewise.
+ (arm_expand_epilogue_apcs_frame): Likewise.
+ (arm_expand_epilogue): Likewise.
+
+2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
+
+ * config/arm/arm.c (thumb1_expand_prologue): Update error message.
+
+2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.
+
+ (floatv2siv2df2): New expander.
+ (floatunsv2siv2df2): New insn pattern.
+
+ (fix_truncv2dfv2si2): New expander.
+ (fixuns_truncv2dfv2si2): New insn pattern.
+
+2020-05-14 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/95105
+ * config/aarch64/aarch64-sve-builtins.cc
+ (handle_arm_sve_vector_bits_attribute): Create a copy of the
+ original type's TYPE_MAIN_VARIANT, then reapply all the differences
+ between the original type and its main variant.
+
+2020-05-14 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/95118
+ * real.c (real_to_decimal_for_mode): Make sure we handle
+ a zero with nonzero exponent.
+
+2020-05-14 Jakub Jelinek <jakub@redhat.com>
+
+ * Makefile.in (GTFILES): Add omp-general.c.
+ * cgraph.h (struct cgraph_node): Add declare_variant_alt and
+ calls_declare_variant_alt members and initialize them in the
+ ctor.
+ * ipa.c (symbol_table::remove_unreachable_nodes): Handle direct
+ calls to declare_variant_alt nodes.
+ * lto-cgraph.c (lto_output_node): Write declare_variant_alt
+ and calls_declare_variant_alt.
+ (input_overwrite_node): Read them back.
+ * omp-simd-clone.c (simd_clone_create): Copy calls_declare_variant_alt
+ bit.
+ * tree-inline.c (expand_call_inline): Or in calls_declare_variant_alt
+ bit.
+ (tree_function_versioning): Copy calls_declare_variant_alt bit.
+ * omp-offload.c (execute_omp_device_lower): Call
+ omp_resolve_declare_variant on direct function calls.
+ (pass_omp_device_lower::gate): Also enable for
+ calls_declare_variant_alt functions.
+ * omp-general.c (omp_maybe_offloaded): Return false after inlining.
+ (omp_context_selector_matches): Handle the case when
+ cfun->curr_properties has PROP_gimple_any bit set.
+ (struct omp_declare_variant_entry): New type.
+ (struct omp_declare_variant_base_entry): New type.
+ (struct omp_declare_variant_hasher): New type.
+ (omp_declare_variant_hasher::hash, omp_declare_variant_hasher::equal):
+ New methods.
+ (omp_declare_variants): New variable.
+ (struct omp_declare_variant_alt_hasher): New type.
+ (omp_declare_variant_alt_hasher::hash,
+ omp_declare_variant_alt_hasher::equal): New methods.
+ (omp_declare_variant_alt): New variables.
+ (omp_resolve_late_declare_variant): New function.
+ (omp_resolve_declare_variant): Call omp_resolve_late_declare_variant
+ when called late. Create a magic declare_variant_alt fndecl and
+ cgraph node and return that if decision needs to be deferred until
+ after gimplification.
+ * cgraph.c (symbol_table::create_edge): Or in calls_declare_variant_alt
+ bit.
+
+ PR middle-end/95108
+ * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member.
+ (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in
+ entry block if info->after_stmt is NULL, otherwise add after that stmt
+ and update it after adding each stmt.
+ (ipa_simd_modify_function_body): Initialize info.after_stmt.
+
+ * function.h (struct function): Add has_omp_target bit.
+ * omp-offload.c (omp_discover_declare_target_fn_r): New function,
+ old renamed to ...
+ (omp_discover_declare_target_tgt_fn_r): ... this.
+ (omp_discover_declare_target_var_r): Call
+ omp_discover_declare_target_tgt_fn_r instead of
+ omp_discover_declare_target_fn_r.
+ (omp_discover_implicit_declare_target): Also queue functions with
+ has_omp_target bit set, for those walk with
+ omp_discover_declare_target_fn_r, for declare target to functions
+ walk with omp_discover_declare_target_tgt_fn_r.
+
+2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): Rename from mmx_pf2id.
+ Add SSE/AVX alternative. Change operand predicates from
+ nonimmediate_operand to register_mmxmem_operand.
+ Enable instruction pattern for TARGET_MMX_WITH_SSE.
+ (fix_truncv2sfv2si2): New expander.
+ (fixuns_truncv2sfv2si2): New insn pattern.
+
+ (mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
+ Add SSE/AVX alternative. Change operand predicates from
+ nonimmediate_operand to register_mmxmem_operand.
+ Enable instruction pattern for TARGET_MMX_WITH_SSE.
+ (floatv2siv2sf2): New expander.
+ (floatunsv2siv2sf2): New insn pattern.
+
+ * config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
+ Update for rename.
+ (IX86_BUILTIN_PI2FD): Ditto.
+
+2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/s390/s390.c (s390_emit_stack_probe): Call the probe_stack
+ expander.
+ * config/s390/s390.md ("@probe_stack2<mode>", "probe_stack"): New
+ expanders.
+
+2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/s390/s390.c (allocate_stack_space): Add missing updates
+ of last_probe_offset.
+
+2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/s390/s390.md ("allocate_stack"): Call
+ anti_adjust_stack_and_probe_stack_clash when stack clash
+ protection is enabled.
+ * explow.c (anti_adjust_stack_and_probe_stack_clash): Remove
+ prototype. Remove static.
+ * explow.h (anti_adjust_stack_and_probe_stack_clash): Add
+ prototype.
+
+2020-05-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.h (vec_extractl): New #define.
+ (vec_extracth): Likewise.
+ * config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
+ (UNSPEC_EXTRACTR): Likewise.
+ (vextractl<mode>): New expansion.
+ (vextractl<mode>_internal): New insn.
+ (vextractr<mode>): New expansion.
+ (vextractr<mode>_internal): New insn.
+ * config/rs6000/rs6000-builtin.def (__builtin_altivec_vextdubvlx):
+ New built-in function.
+ (__builtin_altivec_vextduhvlx): Likewise.
+ (__builtin_altivec_vextduwvlx): Likewise.
+ (__builtin_altivec_vextddvlx): Likewise.
+ (__builtin_altivec_vextdubvhx): Likewise.
+ (__builtin_altivec_vextduhvhx): Likewise.
+ (__builtin_altivec_vextduwvhx): Likewise.
+ (__builtin_altivec_vextddvhx): Likewise.
+ (__builtin_vec_extractl): New overloaded built-in function.
+ (__builtin_vec_extracth): Likewise.
+ * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
+ Define overloaded forms of __builtin_vec_extractl and
+ __builtin_vec_extracth.
+ (builtin_function_type): Add cases to mark arguments of new
+ built-in functions as unsigned.
+ (rs6000_common_init_builtins): Add
+ opaque_ftype_opaque_opaque_opaque_opaque.
+ * config/rs6000/rs6000.md (du_or_d): New mode attribute.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
+ for a Future Architecture): Add description of vec_extractl and
+ vec_extractr built-in functions.
+
+2020-05-13 Richard Biener <rguenther@suse.de>
+
+ * target.def (add_stmt_cost): Add new vectype parameter.
+ * targhooks.c (default_add_stmt_cost): Adjust.
+ * targhooks.h (default_add_stmt_cost): Likewise.
+ * config/aarch64/aarch64.c (aarch64_add_stmt_cost): Take new
+ vectype parameter.
+ * config/arm/arm.c (arm_add_stmt_cost): Likewise.
+ * config/i386/i386.c (ix86_add_stmt_cost): Likewise.
+ * config/rs6000/rs6000.c (rs6000_add_stmt_cost): Likewise.
+
+ * tree-vectorizer.h (stmt_info_for_cost::vectype): Add.
+ (dump_stmt_cost): Add new vectype parameter.
+ (add_stmt_cost): Likewise.
+ (record_stmt_cost): Likewise.
+ (record_stmt_cost): Add overload with old signature.
+ * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost):
+ Adjust.
+ (vect_get_known_peeling_cost): Likewise.
+ (vect_estimate_min_profitable_iters): Likewise.
+ * tree-vectorizer.c (dump_stmt_cost): Add new vectype parameter.
+ * tree-vect-stmts.c (record_stmt_cost): Likewise.
+ (vect_prologue_cost_for_slp_op): Remove stmt_vec_info parameter
+ and pass down correct vectype and NULL stmt_info.
+ (vect_model_simple_cost): Adjust.
+ (vect_model_store_cost): Likewise.
+
+2020-05-13 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (SLP_INSTANCE_GROUP_SIZE): Remove.
+ (_slp_instance::group_size): Likewise.
+ * tree-vect-loop.c (vectorizable_reduction): The group size
+ is the number of lanes in the node.
+ * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Likewise.
+ (vect_analyze_slp_instance): Do not set SLP_INSTANCE_GROUP_SIZE,
+ verify it matches the instance trees number of lanes.
+ (vect_slp_analyze_node_operations_1): Use the numer of lanes
+ in the node as group size.
+ (vect_bb_vectorization_profitable_p): Use the instance root
+ number of lanes for the size of life.
+ (vect_schedule_slp_instance): Use the number of lanes as
+ group_size.
+ * tree-vect-stmts.c (vectorizable_load): Remove SLP instance
+ parameter. Use the number of lanes of the load for the group
+ size in the gap adjustment code.
+ (vect_analyze_stmt): Adjust.
+ (vect_transform_stmt): Likewise.
+
+2020-05-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/95080
+ * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even
+ if the last insn is a note.
+
+ PR tree-optimization/95060
+ * tree-ssa-math-opts.c (convert_mult_to_fma_1): Fold a NEGATE_EXPR
+ if it is the single use of the FMA internal builtin.
+
+2020-05-13 Bin Cheng <bin.cheng@linux.alibaba.com>
+
+ PR tree-optimization/94969
+ * tree-data-dependence.c (constant_access_functions): Rename to...
+ (invariant_access_functions): ...this. Add parameter. Check for
+ invariant access function, rather than constant.
+ (build_classic_dist_vector): Call above function.
+ * tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
+
+2020-05-13 Hongtao Liu <hongtao.liu@intel.com>
+
+ PR target/94118
+ * doc/extend.texi (x86Operandmodifiers): Document more x86
+ operand modifier.
+ * gcc/config/i386/i386.c: Add comment for operand modifier N and I.
+
+2020-05-12 Giuliano Belinassi <giuliano.belinassi@usp.br>
+
+ * tree-vrp.c (class vrp_insert): New.
+ (insert_range_assertions): Move to class vrp_insert.
+ (dump_all_asserts): Same as above.
+ (dump_asserts_for): Same as above.
+ (live): Same as above.
+ (need_assert_for): Same as above.
+ (live_on_edge): Same as above.
+ (finish_register_edge_assert_for): Same as above.
+ (find_switch_asserts): Same as above.
+ (find_assert_locations): Same as above.
+ (find_assert_locations_1): Same as above.
+ (find_conditional_asserts): Same as above.
+ (process_assert_insertions): Same as above.
+ (register_new_assert_for): Same as above.
+ (vrp_prop): New variable fun.
+ (vrp_initialize): New parameter.
+ (identify_jump_threads): Same as above.
+ (execute_vrp): Same as above.
+
+
+2020-05-12 Keith Packard <keith.packard@sifive.com>
+
+ * config/riscv/riscv.c (riscv_unique_section): New.
+ (TARGET_ASM_UNIQUE_SECTION): New.
+
+2020-05-12 Craig Blackmore <craig.blackmore@embecosm.com>
+
+ * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv.
+ * config/riscv/riscv-passes.def: New file.
+ * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
+ * config/riscv/riscv-shorten-memrefs.c: New file.
+ * config/riscv/riscv.c (tree-pass.h): New include.
+ (riscv_compressed_reg_p): New Function
+ (riscv_compressed_lw_offset_p): Likewise.
+ (riscv_compressed_lw_address_p): Likewise.
+ (riscv_shorten_lw_offset): Likewise.
+ (riscv_legitimize_address): Attempt to convert base + large_offset
+ to compressible new_base + small_offset.
+ (riscv_address_cost): Make anticipated compressed load/stores
+ cheaper for code size than uncompressed load/stores.
+ (riscv_register_priority): Move compressed register check to
+ riscv_compressed_reg_p.
+ * config/riscv/riscv.h (C_S_BITS): Define.
+ (CSW_MAX_OFFSET): Define.
+ * config/riscv/riscv.opt (mshorten-memefs): New option.
+ * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
+ (PASSES_EXTRA): Add riscv-passes.def.
+ * doc/invoke.texi: Document -mshorten-memrefs.
+
+ * config/riscv/riscv.c (riscv_new_address_profitable_p): New function.
+ (TARGET_NEW_ADDRESS_PROFITABLE_P): Define.
+ * doc/tm.texi: Regenerate.
+ * doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook.
+ * sched-deps.c (attempt_change): Use old address if it is cheaper than
+ new address.
+ * target.def (new_address_profitable_p): New hook.
+ * targhooks.c (default_new_address_profitable_p): New function.
+ * targhooks.h (default_new_address_profitable_p): Declare.
+
+2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/mmx.md (copysignv2sf3): New expander.
+ (xorsignv2sf3): Ditto.
+ (signbitv2sf3): Ditto.
+
+2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/mmx.md (fmav2sf4): New insn pattern.
+ (fmsv2sf4): Ditto.
+ (fnmav2sf4): Ditto.
+ (fnmsv2sf4): Ditto.
+
+2020-05-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * Makefile.in (CET_HOST_FLAGS): New.
+ (COMPILER): Add $(CET_HOST_FLAGS).
+ * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and
+ AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't
+ enabled.
+ * aclocal.m4: Regenerated.
+ * configure: Likewise.
+
+2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/mmx.md (<code>v2sf2): New insn pattern.
+ (*mmx_<code>v2sf2): New insn_and_split pattern.
+ (*mmx_nabsv2sf2): Ditto.
+ (*mmx_andnotv2sf3): New insn pattern.
+ (*mmx_<code>v2sf3): Ditto.
+ * config/i386/i386.md (absneg_op): New code attribute.
+ * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
+ (ix86_build_signbit_mask): Ditto.
+
+2020-05-12 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-live.c (remove_unused_locals): Remove dead debug
+ bind resets.
+
+2020-05-12 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
+ Update prototype to include "local" argument.
+ * config/msp430/msp430.c (msp430_output_aligned_decl_common): Add
+ "local" argument. Handle local common decls.
+ * config/msp430/msp430.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Adjust
+ msp430_output_aligned_decl_common call with 0 for "local" argument.
+ (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Define.
+
+2020-05-12 Richard Biener <rguenther@suse.de>
+
+ * cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
+
+2020-05-12 Martin Liska <mliska@suse.cz>
+
+ PR sanitizer/95033
+ PR sanitizer/95051
+ * sanopt.c (sanitize_rewrite_addressable_params):
+ Clear DECL_NOT_GIMPLE_REG_P for argument.
+
+2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/94980
+ * tree-vect-generic.c (expand_vector_comparison): Use
+ vector_element_bits_tree to get the element size in bits,
+ rather than using TYPE_SIZE.
+ (expand_vector_condition, vector_element): Likewise.
+
+2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/94980
+ * tree-vect-generic.c (build_replicated_const): Take the number
+ of bits as a parameter, instead of the type of the elements.
+ (do_plus_minus): Update accordingly, using vector_element_bits
+ to calculate the correct number of bits.
+ (do_negate): Likewise.
+
+2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/94980
+ * tree.h (vector_element_bits, vector_element_bits_tree): Declare.
+ * tree.c (vector_element_bits, vector_element_bits_tree): New.
+ * match.pd: Use the new functions instead of determining the
+ vector element size directly from TYPE_SIZE(_UNIT).
+ * tree-vect-data-refs.c (vect_gather_scatter_fn_p): Likewise.
+ * tree-vect-patterns.c (vect_recog_mask_conversion_pattern): Likewise.
+ * tree-vect-stmts.c (vect_is_simple_cond): Likewise.
+ * tree-vect-generic.c (expand_vector_piecewise): Likewise.
+ (expand_vector_conversion): Likewise.
+ (expand_vector_addition): Likewise for a TYPE_SIZE_UNIT used as
+ a divisor. Convert the dividend to bits to compensate.
+ * tree-vect-loop.c (vectorizable_live_operation): Call
+ vector_element_bits instead of open-coding it.
+
+2020-05-12 Jakub Jelinek <jakub@redhat.com>
+
+ * omp-offload.h (omp_discover_implicit_declare_target): Declare.
+ * omp-offload.c: Include context.h.
+ (omp_declare_target_fn_p, omp_declare_target_var_p,
+ omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
+ omp_discover_implicit_declare_target): New functions.
+ * cgraphunit.c (analyze_functions): Call
+ omp_discover_implicit_declare_target.
+
+2020-05-12 Richard Biener <rguenther@suse.de>
+
+ * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Canonicalize
+ literal constant &MEM[..] to a constant literal.
+
+2020-05-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/95045
+ * dbgcnt.def (lim): Add debug-counter.
+ * tree-ssa-loop-im.c: Include dbgcnt.h.
+ (find_refs_for_sm): Use lim debug counter for store motion
+ candidates.
+ (do_store_motion): Rename form store_motion. Commit edge
+ insertions...
+ (store_motion_loop): ... here.
+ (tree_ssa_lim): Adjust.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
+ (vec_ctzm): Rename to vec_cnttzm.
+ * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
+ Change fourth operand for vec_ternarylogic to require
+ compatibility with unsigned SImode rather than unsigned QImode.
+ * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
+ Remove overloaded forms of vec_gnb that are no longer needed.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
+ for a Future Architecture): Replace vec_clzm with vec_cntlzm;
+ replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
+ vec_gnb; move vec_ternarylogic documentation into this section
+ and replace const unsigned char with const unsigned int as its
+ fourth argument.
+
+2020-05-11 Carl Love <cel@us.ibm.com>
+
+ * config/rs6000/altivec.h (vec_genpcvm): New #define.
+ * config/rs6000/rs6000-builtin.def (XXGENPCVM_V16QI): New built-in
+ instantiation.
+ (XXGENPCVM_V8HI): Likewise.
+ (XXGENPCVM_V4SI): Likewise.
+ (XXGENPCVM_V2DI): Likewise.
+ (XXGENPCVM): New overloaded built-in instantiation.
+ * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add
+ entries for FUTURE_BUILTIN_VEC_XXGENPCVM.
+ (altivec_expand_builtin): Add special handling for
+ FUTURE_BUILTIN_VEC_XXGENPCVM.
+ (builtin_function_type): Add handling for
+ FUTURE_BUILTIN_XXGENPCVM_{V16QI,V8HI,V4SI,V2DI}.
+ * config/rs6000/vsx.md (VSX_EXTRACT_I4): New mode iterator.
+ (UNSPEC_XXGENPCV): New constant.
+ (xxgenpcvm_<mode>_internal): New insn.
+ (xxgenpcvm_<mode>): New expansion.
+ * doc/extend.texi: Add documentation for vec_genpcvm built-ins.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.h (vec_strir): New #define.
+ (vec_stril): Likewise.
+ (vec_strir_p): Likewise.
+ (vec_stril_p): Likewise.
+ * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
+ (UNSPEC_VSTRIL): Likewise.
+ (vstrir_<mode>): New expansion.
+ (vstrir_code_<mode>): New insn.
+ (vstrir_p_<mode>): New expansion.
+ (vstrir_p_code_<mode>): New insn.
+ (vstril_<mode>): New expansion.
+ (vstril_code_<mode>): New insn.
+ (vstril_p_<mode>): New expansion.
+ (vstril_p_code_<mode>): New insn.
+ * config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
+ New built-in function.
+ (__builtin_altivec_vstrihr): Likewise.
+ (__builtin_altivec_vstribl): Likewise.
+ (__builtin_altivec_vstrihl): Likewise.
+ (__builtin_altivec_vstribr_p): Likewise.
+ (__builtin_altivec_vstrihr_p): Likewise.
+ (__builtin_altivec_vstribl_p): Likewise.
+ (__builtin_altivec_vstrihl_p): Likewise.
+ (__builtin_vec_strir): New overloaded built-in function.
+ (__builtin_vec_stril): Likewise.
+ (__builtin_vec_strir_p): Likewise.
+ (__builtin_vec_stril_p): Likewise.
+ * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
+ Define overloaded forms of __builtin_vec_strir,
+ __builtin_vec_stril, __builtin_vec_strir_p, and
+ __builtin_vec_stril_p.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
+ for a Future Architecture): Add description of vec_stril,
+ vec_stril_p, vec_strir, and vec_strir_p built-in functions.
+
+2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
+
+ * config/rs6000/altivec.h (vec_ternarylogic): New #define.
+ * config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
+ (xxeval): New insn.
+ * config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
+ * config/rs6000/rs6000-builtin.def: Add handling of new macro
+ RS6000_BUILTIN_4.
+ (BU_FUTURE_V_4): New macro. Use it.
+ (BU_FUTURE_OVERLOAD_4): Likewise.
+ * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
+ handling for quaternary built-in functions.
+ (altivec_resolve_overloaded_builtin): Add special-case handling
+ for __builtin_vec_xxeval.
+ * config/rs6000/rs6000-call.c: Add handling of new macro
+ RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
+ bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
+ bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
+ (altivec_overloaded_builtins): Add definitions for
+ FUTURE_BUILTIN_VEC_XXEVAL.
+ (bdesc_4arg): New array.
+ (htm_expand_builtin): Add handling for quaternary built-in
+ functions.
+ (rs6000_expand_quaternop_builtin): New function.
+ (rs6000_expand_builtin): Add handling for quaternary built-in
+ functions.
+ (rs6000_init_builtins): Initialize builtin_mode_to_type entries
+ for unsigned QImode and unsigned HImode.
+ (builtin_quaternary_function_type): New function.
+ (rs6000_common_init_builtins): Add handling of quaternary
+ operations.
+ * config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
+ constant.
+ (RS6000_BTC_PREDICATE): Change value of constant.
+ (RS6000_BTC_ABS): Likewise.
+ (rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
+ * doc/extend.texi (PowerPC AltiVec Built-In Functions Available
+ for a Future Architecture): Add description of vec_ternarylogic
+ built-in function.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
+ function.
+ (__builtin_pextd): Likewise.
+ * config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
+ (UNSPEC_PEXTD): Likewise.
+ (pdepd): New insn.
+ (pextd): Likewise.
+ * doc/extend.texi (Basic PowerPC Built-in Functions Available for
+ a Future Architecture): Add descriptions of __builtin_pdepd and
+ __builtin_pextd functions.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.h (vec_clrl): New #define.
+ (vec_clrr): Likewise.
+ * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
+ (UNSPEC_VCLRRB): Likewise.
+ (vclrlb): New insn.
+ (vclrrb): Likewise.
+ * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
+ built-in function.
+ (__builtin_altivec_vclrrb): Likewise.
+ (__builtin_vec_clrl): New overloaded built-in function.
+ (__builtin_vec_clrr): Likewise.
+ * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
+ Define overloaded forms of __builtin_vec_clrl and
+ __builtin_vec_clrr.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
+ for a Future Architecture): Add descriptions of vec_clrl and
+ vec_clrr.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
+ built-in function definition.
+ (__builtin_cnttzdm): Likewise.
+ * config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
+ (UNSPEC_CNTTZDM): Likewise.
+ (cntlzdm): New insn.
+ (cnttzdm): Likewise.
+ * doc/extend.texi (Basic PowerPC Built-in Functions available for
+ a Future Architecture): Add descriptions of __builtin_cntlzdm and
+ __builtin_cnttzdm functions.
+
+2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/mmx.md (sqrtv2sf2): New insn pattern.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.h (vec_cfuge): New #define.
+ * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant.
+ (vcfuged): New insn.
+ * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged):
+ New built-in function.
+ * config/rs6000/rs6000-call.c (builtin_function_type): Add
+ handling for FUTURE_BUILTIN_VCFUGED case.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
+ for a Future Architecture): Add description of vec_cfuge built-in
+ function.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
+ #define.
+ (BU_FUTURE_MISC_1): Likewise.
+ (BU_FUTURE_MISC_2): Likewise.
+ (BU_FUTURE_MISC_3): Likewise.
+ (__builtin_cfuged): New built-in function definition.
+ * config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
+ (cfuged): New insn.
+ * doc/extend.texi (Basic PowerPC Built-in Functions Available for
+ a Future Architecture): New subsubsection.
+
+2020-05-11 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/95049
+ * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
+ between different constants.
+
+2020-05-11 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+ Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/altivec.h (vec_gnb): New #define.
+ * config/rs6000/altivec.md (UNSPEC_VGNB): New constant.
+ (vgnb): New insn.
+ * config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New
+ #define.
+ (BU_FUTURE_OVERLOAD_2): Likewise.
+ (BU_FUTURE_OVERLOAD_3): Likewise.
+ (__builtin_altivec_gnb): New built-in function.
+ (__buiiltin_vec_gnb): New overloaded built-in function.
+ * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
+ Define overloaded forms of __builtin_vec_gnb.
+ (rs6000_expand_binop_builtin): Add error checking for 2nd argument
+ of __builtin_vec_gnb.
+ (builtin_function_type): Mark return value and arguments unsigned
+ for FUTURE_BUILTIN_VGNB.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
+ for a Future Architecture): Add description of vec_gnb built-in
+ function.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+ Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/altivec.h (vec_pdep): New macro implementing new
+ built-in function.
+ (vec_pext): Likewise.
+ * config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
+ (UNSPEC_VPEXTD): Likewise.
+ (vpdepd): New insn.
+ (vpextd): Likewise.
+ * config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New
+ built-in function.
+ (__builtin_altivec_vpextd): Likewise.
+ * config/rs6000/rs6000-call.c (builtin_function_type): Add
+ handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD
+ cases.
+ * doc/extend.texi (PowerPC Altivec Built-in Functions Available
+ for a Future Architecture): Add description of vec_pdep and
+ vec_pext built-in functions.
+
+2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
+ Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/altivec.h (vec_clzm): New macro.
+ (vec_ctzm): Likewise.
+ * config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
+ (UNSPEC_VCTZDM): Likewise.
+ (vclzdm): New insn.
+ (vctzdm): Likewise.
+ * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro.
+ (BU_FUTURE_V_1): Likewise.
+ (BU_FUTURE_V_2): Likewise.
+ (BU_FUTURE_V_3): Likewise.
+ (__builtin_altivec_vclzdm): New builtin definition.
+ (__builtin_altivec_vctzdm): Likewise.
+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause
+ _ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is
+ set.
+ * config/rs6000/rs6000-call.c (builtin_function_type): Set return
+ value and parameter types to be unsigned for VCLZDM and VCTZDM.
+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
+ support for TARGET_FUTURE flag.
+ * config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant.
+ * doc/extend.texi (PowerPC Altivec Built-in Functions Available
+ for a Future Architecture): New subsubsection.
+
+2020-05-11 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/94988
+ PR tree-optimization/95025
+ * tree-ssa-loop-im.c (seq_entry): Make a struct, add from.
+ (sm_seq_push_down): Take extra parameter denoting where we
+ moved the ref to.
+ (execute_sm_exit): Re-issue sm_other stores in the correct
+ order.
+ (sm_seq_valid_bb): When always executed, allow sm_other to
+ prevail inbetween sm_ord and record their stored value.
+ (hoist_memory_references): Adjust refs_not_supported propagation
+ and prune sm_other from the end of the ordered sequences.
+
+2020-05-11 Felix Yang <felix.yang@huawei.com>
+
+ PR target/94991
+ * config/aarch64/aarch64.md (mov<mode>):
+ Bitcasts to the equivalent integer mode using gen_lowpart
+ instead of doing FAIL for scalar floating point move.
+
+2020-05-11 Alex Coplan <alex.coplan@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
+ to correctly calculate cost for new pattern (*csinv3_uxtw_insn3).
+ * config/aarch64/aarch64.md (*csinv3_utxw_insn1): New.
+ (*csinv3_uxtw_insn2): New.
+ (*csinv3_uxtw_insn3): New.
+ * config/aarch64/iterators.md (neg_not_cs): New.
+
+2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
+ instead of "Yv" for AVX alternatives. Add "prefix" attribute.
+ (*mmx_addv2sf3): Ditto.
+ (*mmx_subv2sf3): Ditto.
+ (*mmx_mulv2sf3): Ditto.
+ (*mmx_<code>v2sf3): Ditto.
+ (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
+
+2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/i386.c (ix86_vector_mode_supported_p):
+ Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
+ * config/i386/mmx.md (*mov<mode>_internal): Do not set
+ mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
+
+ (mmx_addv2sf3): Change operand predicates from
+ nonimmediate_operand to register_mmxmem_operand.
+ (addv2sf3): New expander.
+ (*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
+ predicates from nonimmediate_operand to register_mmxmem_operand.
+ Enable instruction pattern for TARGET_MMX_WITH_SSE.
+
+ (mmx_subv2sf3): Change operand predicate from
+ nonimmediate_operand to register_mmxmem_operand.
+ (mmx_subrv2sf3): Ditto.
+ (subv2sf3): New expander.
+ (*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
+ predicates from nonimmediate_operand to register_mmxmem_operand.
+ Enable instruction pattern for TARGET_MMX_WITH_SSE.
+
+ (mmx_mulv2sf3): Change operand predicates from
+ nonimmediate_operand to register_mmxmem_operand.
+ (mulv2sf3): New expander.
+ (*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
+ predicates from nonimmediate_operand to register_mmxmem_operand.
+ Enable instruction pattern for TARGET_MMX_WITH_SSE.
+
+ (mmx_<code>v2sf3): Change operand predicates from
+ nonimmediate_operand to register_mmxmem_operand.
+ (<code>v2sf3): New expander.
+ (*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
+ predicates from nonimmediate_operand to register_mmxmem_operand.
+ Enable instruction pattern for TARGET_MMX_WITH_SSE.
+ (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
+
+2020-05-11 Martin Liska <mliska@suse.cz>
+
+ PR c/95040
+ * common.opt: Fix typo in option description.
+
+2020-05-11 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/94928
+ * gcov-io.h: Add caveat about coverage format parsing and
+ possible outdated documentation.
+
2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
PR tree-optimization/83403
projects / thirdparty / gcc.git / blobdiff