Riscv patterns to optimize away some redundant zero/sign extends.

[thirdparty/gcc.git] / gcc / ChangeLog

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 96f27abc3f0987be13cf6920d0884bcd182afe5a..877a4e8e248b3debd162597baf3279172e54416f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2017-11-29  Jim Wilson  <jimw@sifive.com>
+           Andrew Waterman  <andrew@sifive.com>
+
+       * config/riscv/riscv.c (SINGLE_SHIFT_COST): New.
+       (riscv_rtx_costs): Case ZERO_EXTRACT, match new pattern, and return
+       SINGLE_SHIFT_COST.  Case LT and ZERO_EXTEND, likewise.  Case ASHIFT,
+       use SINGLE_SHIFT_COST.
+       * config/riscv/riscv.md (lshrsi3_zero_extend_1): New.
+       (lshrsi3_zero_extend_2, lshrsi3_zero_extend_3): New.
+
 2017-11-29  Julia Koval  <julia.koval@intel.com>
 
        * config/i386/avx512vbmi2intrin.h (_mm512_shldv_epi16,