+2021-04-23 YiFei Zhu <zhuyifei1999@gmail.com>
+
+ * config/bpf/bpf.h (ASM_OUTPUT_ALIGNED_BSS): Use .type and .lcomm.
+
+2021-04-23 YiFei Zhu <zhuyifei1999@gmail.com>
+
+ * config/bpf/bpf.h (FUNCTION_BOUNDARY): Set to 64.
+
+2021-04-23 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/100041
+ * config/i386/i386-options.c (ix86_option_override_internal):
+ Error out when -m96bit-long-double is used with 64bit targets.
+ * config/i386/i386.md (*pushxf_rounded): Remove pattern.
+
+2021-04-23 Martin Liska <mliska@suse.cz>
+
+ * lto-wrapper.c: Remove FIXME about usage of
+ hardware_concurrency. The function is not on par with
+ what we have now.
+
+2021-04-23 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/100182
+ * config/i386/sync.md (FILD_ATOMIC/FIST_ATOMIC FP load peephole2):
+ Copy operand 3 to operand 4. Use sse_reg_operand
+ as operand 3 predicate.
+ (FILD_ATOMIC/FIST_ATOMIC FP load peephole2 with mem blockage): Ditto.
+ (LDX_ATOMIC/STX_ATOMIC FP load peephole2): Ditto.
+ (LDX_ATOMIC/LDX_ATOMIC FP load peephole2 with mem blockage): Ditto.
+ (FILD_ATOMIC/FIST_ATOMIC FP store peephole2):
+ Copy operand 1 to operand 0.
+ (FILD_ATOMIC/FIST_ATOMIC FP store peephole2 with mem blockage): Ditto.
+ (LDX_ATOMIC/STX_ATOMIC FP store peephole2): Ditto.
+ (LDX_ATOMIC/LDX_ATOMIC FP store peephole2 with mem blockage): Ditto.
+
+2021-04-23 Alex Coplan <alex.coplan@arm.com>
+
+ PR rtl-optimization/100230
+ * early-remat.c (early_remat::sort_candidates): Use delete[]
+ instead of delete for array allocated with new[].
+
+2021-04-23 Richard Biener <rguenther@suse.de>
+
+ * genmatch.c (lower_cond): Remove VEC_COND_EXPR special-casing.
+ (capture_info::capture_info): Likewise.
+ (capture_info::walk_match): Likewise.
+ (expr::gen_transform): Likewise.
+ (dt_simplify::gen_1): Likewise.
+ * gimple-match-head.c (maybe_resimplify_conditional_op):
+ Remove VEC_COND_EXPR special-casing.
+ (gimple_simplify): Likewise.
+ * gimple.c (gimple_could_trap_p_1): Adjust.
+ * tree-ssa-pre.c (compute_avail): Allow VEC_COND_EXPR
+ to participate in PRE.
+
+2021-04-23 Richard Biener <rguenther@suse.de>
+
+ * cfganal.c (connect_infinite_loops_to_exit): First call
+ add_noreturn_fake_exit_edges.
+ * ipa-sra.c (process_scan_results): Do not call the now redundant
+ add_noreturn_fake_exit_edges.
+ * predict.c (tree_estimate_probability): Likewise.
+ (rebuild_frequencies): Likewise.
+ * store-motion.c (one_store_motion_pass): Likewise.
+
+2021-04-23 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/100222
+ * predict.c (pass_profile::execute): Remove redundant call to
+ mark_irreducible_loops.
+ (report_predictor_hitrates): Likewise.
+
+2021-04-23 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-loop-ivopts.c (rewrite_use_nonlinear_expr): Avoid
+ valid_gimple_rhs_p by instead gimplifying to one.
+
+2021-04-23 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99971
+ * tree-vect-data-refs.c (vect_slp_analyze_node_dependences):
+ Always use TBAA for loads.
+
+2021-04-23 liuhongt <hongtao.liu@intel.com>
+
+ PR target/100093
+ * config/i386/i386-options.c (ix86_option_override_internal):
+ Clear MASK_AVX256_SPLIT_UNALIGNED_LOAD/STORE in x_target_flags
+ when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL is enabled
+ by target attribute.
+
+2021-04-23 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/aix71.h (PREFERRED_DEBUGGING_TYPE): Change to
+ DWARF2_DEBUG.
+ * config/rs6000/aix72.h (PREFERRED_DEBUGGING_TYPE): Same.
+
+2021-04-22 David Edelsohn <dje.gcc@gmail.com>
+
+ * config.gcc (powerpc-ibm-aix6.*): Remove.
+ * config/rs6000/aix61.h: Delete.
+
+2021-04-22 Martin Liska <mliska@suse.cz>
+
+ PR testsuite/100159
+ PR testsuite/100192
+ * builtins.c (expand_builtin): Fix typos and missing comments.
+ * dwarf2out.c (gen_subprogram_die): Likewise.
+ (gen_struct_or_union_type_die): Likewise.
+
+2021-04-22 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/100119
+ * config/i386/i386-expand.c (ix86_expand_convert_uns_sidf_sse):
+ Remove the sign with FE_DOWNWARD, where x - x = -0.0.
+
+2021-04-21 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/i386/darwin.h (TARGET_64BIT): Remove definition
+ based on TARGET_ISA_64BIT.
+ (TARGET_64BIT_P): Remove definition based on
+ TARGET_ISA_64BIT_P().
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ Revert:
+ 2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * lto-wrapper.c (cpuset_popcount): Remove.
+ (init_num_threads): Remove and use hardware_concurrency.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ PR jit/98615
+ * main.c (main): Call toplev::finalize in CHECKING_P mode.
+ * ipa-modref.c (ipa_modref_c_finalize): summaries are NULL
+ when incremental LTO linking happens.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * lto-wrapper.c (run_gcc): When -flto=jobserver is used, but the
+ makeserver cannot be detected, then use -flto=N fallback.
+
+2021-04-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * acinclude.m4 (gcc_AC_INITFINI_ARRAY): When cross-compiling,
+ default to yes for aarch64-linux-gnu.
+ * configure: Regenerate.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * lto-wrapper.c (cpuset_popcount): Remove.
+ (init_num_threads): Remove and use hardware_concurrency.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * config/i386/i386.c: Remove superfluous || TARGET_MACHO
+ which remains to be '(... || 0)' and clang complains about it.
+ * dwarf2out.c (AT_vms_delta): Declare conditionally.
+ (add_AT_vms_delta): Likewise.
+ * tree.c (fld_simplified_type): Use rather more common pattern
+ for disabling of something (#if 0).
+ (get_tree_code_name): Likewise.
+ (verify_type_variant): Likewise.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * config/i386/i386-expand.c (decide_alignment): Use newly named
+ macro TARGET_CPU_P.
+ * config/i386/i386.c (ix86_decompose_address): Likewise.
+ (ix86_address_cost): Likewise.
+ (ix86_lea_outperforms): Likewise.
+ (ix86_avoid_lea_for_addr): Likewise.
+ (ix86_add_stmt_cost): Likewise.
+ * config/i386/i386.h (TARGET_*): Remove.
+ (TARGET_CPU_P): New macro.
+ * config/i386/i386.md: Use newly named macro TARGET_CPU_P.
+ * config/i386/x86-tune-sched-atom.c (do_reorder_for_imul): Likewise.
+ (swap_top_of_ready_list): Likewise.
+ (ix86_atom_sched_reorder): Likewise.
+ * config/i386/x86-tune-sched-bd.c (ix86_bd_has_dispatch): Likewise.
+ * config/i386/x86-tune-sched.c (ix86_adjust_cost): Likewise.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * config/i386/i386-options.c (TARGET_EXPLICIT_NO_SAHF_P):
+ Define.
+ (SET_TARGET_NO_SAHF): Likewise.
+ (TARGET_EXPLICIT_PREFETCH_SSE_P): Likewise.
+ (SET_TARGET_PREFETCH_SSE): Likewise.
+ (TARGET_EXPLICIT_NO_TUNE_P): Likewise.
+ (SET_TARGET_NO_TUNE): Likewise.
+ (TARGET_EXPLICIT_NO_80387_P): Likewise.
+ (SET_TARGET_NO_80387): Likewise.
+ (DEF_PTA): New.
+ * config/i386/i386.h (TARGET_*): Remove.
+ * opth-gen.awk: Generate new used macros.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * config/i386/i386.h (PTA_*): Remove.
+ (enum pta_flag): New.
+ (DEF_PTA): Generate PTA_* values from i386-isa.def.
+ * config/i386/i386-isa.def: New file.
+
+2021-04-21 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/99988
+ * config/aarch64/aarch64-bti-insert.c (aarch64_bti_j_insn_p): New.
+ (rest_of_insert_bti): Avoid inserting duplicate bti j insns for
+ jump table targets.
+
+2021-04-21 H.J. Lu <hjl.tools@gmail.com>
+
+ * config.gcc: Install mwaitintrin.h for i[34567]86-*-* and
+ x86_64-*-* targets.
+ * common/config/i386/i386-common.c (OPTION_MASK_ISA2_MWAIT_SET):
+ New.
+ (OPTION_MASK_ISA2_MWAIT_UNSET): Likewise.
+ (ix86_handle_option): Handle -mmwait.
+ * config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins):
+ Replace OPTION_MASK_ISA_SSE3 with OPTION_MASK_ISA2_MWAIT on
+ __builtin_ia32_monitor and __builtin_ia32_mwait.
+ * config/i386/i386-options.c (isa2_opts): Add -mmwait.
+ (ix86_valid_target_attribute_inner_p): Likewise.
+ (ix86_option_override_internal): Enable mwait/monitor
+ instructions for -msse3.
+ * config/i386/i386.h (TARGET_MWAIT): New.
+ (TARGET_MWAIT_P): Likewise.
+ * config/i386/i386.opt: Add -mmwait.
+ * config/i386/mwaitintrin.h: New file.
+ * config/i386/pmmintrin.h: Include <mwaitintrin.h>.
+ * config/i386/sse.md (sse3_mwait): Replace TARGET_SSE3 with
+ TARGET_MWAIT.
+ (@sse3_monitor_<mode>): Likewise.
+ * config/i386/x86gprintrin.h: Include <mwaitintrin.h>.
+ * doc/extend.texi: Document mwait target attribute.
+ * doc/invoke.texi: Document -mmwait.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * config/i386/i386-options.c (DEF_ENUM): Remove it.
+ * config/i386/i386-opts.h (DEF_ENUM): Likewise.
+ * config/i386/stringop.def (DEF_ENUM): Likewise.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ * tree-cfg.c (gimple_verify_flow_info): Use qD instead
+ of print_generic_expr.
+
+2021-04-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/100148
+ * cprop.c (constprop_register): Use next_nondebug_insn instead of
+ NEXT_INSN.
+
+2021-04-21 Martin Liska <mliska@suse.cz>
+
+ PR ipa/98815
+ * cgraphunit.c (cgraph_node::analyze): Remove duplicate
+ free_dominance_info calls.
+
+2021-04-21 Richard Biener <rguenther@suse.de>
+
+ * gimple-fold.c (maybe_fold_reference): Remove is_lhs
+ parameter (and assume it to be false).
+ (fold_gimple_assign): Adjust, remove all callers of
+ maybe_fold_reference calling it with is_lhs true.
+ (gimple_fold_call): Likewise.
+ (fold_stmt_1): Likewise.
+
+2021-04-21 Richard Biener <rguenther@suse.de>
+
+ * fold-const.c (pedantic_non_lvalue_loc): Remove.
+ (fold_binary_loc): Adjust.
+ (fold_ternary_loc): Likewise.
+
+2021-04-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR middle-end/100130
+ * varasm.c (get_block_for_decl): Make sure that any use of the
+ retain attribute matches the section's retain flag.
+ (switch_to_section): Check for retain mismatches even when
+ changing sections, but do not warn if the given decl is the
+ section's named.decl.
+ (output_object_block): Pass the first decl in the block (if any)
+ to switch_to_section.
+
+2021-04-20 H.J. Lu <hjl.tools@gmail.com>
+
+ * config/i386/i386-c.c (ix86_target_macros_internal): Define
+ __CRC32__ for -mcrc32.
+ * config/i386/i386-options.c (ix86_option_override_internal):
+ Enable crc32 instruction for -msse4.2.
+ * config/i386/i386.md (sse4_2_crc32<mode>): Remove TARGET_SSE4_2
+ check.
+ (sse4_2_crc32di): Likewise.
+ * config/i386/ia32intrin.h: Use crc32 target option for CRC32
+ intrinsics.
+
+2021-04-20 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/100108
+ * config/rs6000/rs6000.c (rs6000_machine_from_flags): Do not consider
+ OPTION_MASK_ISEL.
+
+2021-04-20 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Fix typo.
+ * params.opt: Likewise.
+
+2021-04-20 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Document new param.
+
+2021-04-19 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/100081
+ * gimple-range-cache.h (ranger_cache): Inherit from gori_compute
+ rather than gori_compute_cache.
+ * gimple-range-gori.cc (is_gimple_logical_p): Move to top of file.
+ (range_def_chain::m_logical_depth): New member.
+ (range_def_chain::range_def_chain): Initialize m_logical_depth.
+ (range_def_chain::get_def_chain): Don't build defchains through more
+ than LOGICAL_LIMIT logical expressions.
+ * params.opt (param_ranger_logical_depth): New.
+
+2021-04-19 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/100067
+ * config/arm/arm.c (arm_configure_build_target): Do not strip
+ extended FPU/SIMD feature bits from the target ISA when -mfpu
+ is specified (partial revert of r11-8168).
+
+2021-04-19 Thomas Schwinge <thomas@codesourcery.com>
+
+ * params.opt (-param=openacc-kernels=): Add.
+ * omp-oacc-kernels-decompose.cc
+ (pass_omp_oacc_kernels_decompose::gate): Use it.
+ * doc/invoke.texi (-fopenacc-kernels=@var{mode}): Move...
+ (--param): ... here, 'openacc-kernels'.
+
+2021-04-19 Martin Liska <mliska@suse.cz>
+
+ PR c/100143
+ * gengtype.c (finish_root_table): Align function arguments
+ in between declaration and definition.
+
+2021-04-19 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/i386/winnt.c (i386_pe_seh_cold_init): Properly deal with
+ frames larger than the SEH maximum frame size.
+
+2021-04-18 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR rtl-optimization/99927
+ * combine.c (distribute_notes) [REG_UNUSED]: If the register already
+ is dead, just drop it.
+
+2021-04-17 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ PR d/99914
+ * config/i386/winnt-d.c (TARGET_D_TEMPLATES_ALWAYS_COMDAT): Define.
+ * doc/tm.texi: Regenerate.
+ * doc/tm.texi.in (D language and ABI): Add @hook for
+ TARGET_D_TEMPLATES_ALWAYS_COMDAT.
+
+2021-04-17 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * config/darwin-d.c (darwin_d_handle_target_object_format): New
+ function.
+ (darwin_d_register_target_info): New function.
+ (TARGET_D_REGISTER_OS_TARGET_INFO): Define.
+ * config/dragonfly-d.c (dragonfly_d_handle_target_object_format): New
+ function.
+ (dragonfly_d_register_target_info): New function.
+ (TARGET_D_REGISTER_OS_TARGET_INFO): Define.
+ * config/freebsd-d.c (freebsd_d_handle_target_object_format): New
+ function.
+ (freebsd_d_register_target_info): New function.
+ (TARGET_D_REGISTER_OS_TARGET_INFO): Define.
+ * config/glibc-d.c (glibc_d_handle_target_object_format): New
+ function.
+ (glibc_d_register_target_info): New function.
+ (TARGET_D_REGISTER_OS_TARGET_INFO): Define.
+ * config/i386/i386-d.c (ix86_d_handle_target_object_format): New
+ function.
+ (ix86_d_register_target_info): Add ix86_d_handle_target_object_format
+ as handler for objectFormat key.
+ * config/i386/winnt-d.c (winnt_d_handle_target_object_format): New
+ function.
+ (winnt_d_register_target_info): New function.
+ (TARGET_D_REGISTER_OS_TARGET_INFO): Define.
+ * config/netbsd-d.c (netbsd_d_handle_target_object_format): New
+ function.
+ (netbsd_d_register_target_info): New function.
+ (TARGET_D_REGISTER_OS_TARGET_INFO): Define.
+ * config/openbsd-d.c (openbsd_d_handle_target_object_format): New
+ function.
+ (openbsd_d_register_target_info): New function.
+ (TARGET_D_REGISTER_OS_TARGET_INFO): Define.
+ * config/pa/pa-d.c (pa_d_handle_target_object_format): New function.
+ (pa_d_register_target_info): Add pa_d_handle_target_object_format as
+ handler for objectFormat key.
+ * config/rs6000/rs6000-d.c (rs6000_d_handle_target_object_format): New
+ function.
+ (rs6000_d_register_target_info): Add
+ rs6000_d_handle_target_object_format as handler for objectFormat key.
+ * config/sol2-d.c (solaris_d_handle_target_object_format): New
+ function.
+ (solaris_d_register_target_info): New function.
+ (TARGET_D_REGISTER_OS_TARGET_INFO): Define.
+
+2021-04-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/91710
+ * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Change
+ abi_break argument from bool * to unsigned *, store there the pre-GCC 9
+ alignment.
+ (aarch64_layout_arg, aarch64_gimplify_va_arg_expr): Adjust callers.
+ (aarch64_function_arg_regno_p): Likewise. Only emit -Wpsabi note if
+ the old and new alignment after applying MIN/MAX to it is different.
+
+2021-04-16 Tamar Christina <tamar.christina@arm.com>
+
+ PR target/100048
+ * config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv<mode>): New.
+ * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_trn): Use new
+ TRN optab.
+ * config/aarch64/iterators.md (UNSPEC_TRN1_CONV): New.
+
+2021-04-16 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Revise
+ this section and its subsections.
+
+2021-04-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/100075
+ * config/aarch64/aarch64.md (*neg_asr_si2_extr, *extrsi5_insn_di): New
+ define_insn patterns.
+
+2021-04-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR rtl-optimization/98689
+ * reg-notes.def (UNTYPED_CALL): New note.
+ * combine.c (distribute_notes): Handle it.
+ * emit-rtl.c (try_split): Likewise.
+ * rtlanal.c (rtx_properties::try_to_add_insn): Likewise. Assume
+ that calls with the note implicitly set all return value registers.
+ * builtins.c (expand_builtin_apply): Add a REG_UNTYPED_CALL
+ to untyped_calls.
+
+2021-04-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR rtl-optimization/99596
+ * rtlanal.c (rtx_properties::try_to_add_insn): Don't add global
+ register accesses for const calls. Assume that pure functions
+ can only read from global registers. Ignore cases in which
+ the stack pointer has been marked global.
+
+2021-04-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/99767
+ * tree-vect-loop.c (vect_transform_loop): Don't remove just
+ dead scalar .MASK_LOAD calls, but also dead .COND_* calls - replace
+ them by their last argument.
+
+2021-04-15 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Other params don't use it, remove it.
+
+2021-04-15 Richard Biener <rguenther@suse.de>
+
+ * gimple-builder.h: Add deprecation note.
+
+2021-04-15 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR c++/98852
+ * attribs.h (restrict_type_identity_attributes_to): Declare.
+ * attribs.c (restrict_type_identity_attributes_to): New function.
+
+2021-04-15 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR c/98852
+ * attribs.h (affects_type_identity_attributes): Declare.
+ * attribs.c (remove_attributes_matching): New function.
+ (affects_type_identity_attributes): Likewise.
+
+2021-04-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/100056
+ * config/aarch64/aarch64.md (*<LOGICAL:optab>_<SHIFT:optab><mode>3):
+ Add combine splitters for *<LOGICAL:optab>_ashl<mode>3 with
+ ZERO_EXTEND, SIGN_EXTEND or AND.
+
+2021-04-14 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR rtl-optimization/99929
+ * rtl.h (same_vector_encodings_p): New function.
+ * cse.c (exp_equiv_p): Check that CONST_VECTORs have the same encoding.
+ * cselib.c (rtx_equal_for_cselib_1): Likewise.
+ * jump.c (rtx_renumbered_equal_p): Likewise.
+ * lra-constraints.c (operands_match_p): Likewise.
+ * reload.c (operands_match_p): Likewise.
+ * rtl.c (rtx_equal_p_cb, rtx_equal_p): Likewise.
+
+2021-04-14 Richard Sandiford <richard.sandiford@arm.com>
+
+ * print-rtl.c (rtx_writer::print_rtx_operand_codes_E_and_V): Print
+ more information about variable-length CONST_VECTORs.
+
+2021-04-14 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/100066
+ * lra-constraints.c (split_reg): Check paradoxical_subreg_p for
+ ordered modes when choosing splitting mode for hard reg.
+
+2021-04-14 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/99246
+ * config/aarch64/aarch64.c (aarch64_expand_sve_const_vector_sel):
+ New function.
+ (aarch64_expand_sve_const_vector): Use it for nelts_per_pattern==2.
+
+2021-04-14 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/s390/s390-builtins.def (O_M5, O_M12, ...): Add new macros
+ for mask operand types.
+ (s390_vec_permi_s64, s390_vec_permi_b64, s390_vec_permi_u64)
+ (s390_vec_permi_dbl, s390_vpdi): Use the M5 type for the immediate
+ operand.
+ (s390_vec_msum_u128, s390_vmslg): Use the M12 type for the
+ immediate operand.
+ * config/s390/s390.c (s390_const_operand_ok): Check the new
+ operand types and generate a list of valid values.
+
+2021-04-14 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * doc/tm.texi: Regenerate.
+ * doc/tm.texi.in (D language and ABI): Add @hook for
+ TARGET_D_REGISTER_OS_TARGET_INFO.
+
+2021-04-14 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * config/aarch64/aarch64-d.c (aarch64_d_handle_target_float_abi): New
+ function.
+ (aarch64_d_register_target_info): New function.
+ * config/aarch64/aarch64-protos.h (aarch64_d_register_target_info):
+ Declare.
+ * config/aarch64/aarch64.h (TARGET_D_REGISTER_CPU_TARGET_INFO):
+ Define.
+ * config/arm/arm-d.c (arm_d_handle_target_float_abi): New function.
+ (arm_d_register_target_info): New function.
+ * config/arm/arm-protos.h (arm_d_register_target_info): Declare.
+ * config/arm/arm.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define.
+ * config/i386/i386-d.c (ix86_d_handle_target_float_abi): New function.
+ (ix86_d_register_target_info): New function.
+ * config/i386/i386-protos.h (ix86_d_register_target_info): Declare.
+ * config/i386/i386.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define.
+ * config/mips/mips-d.c (mips_d_handle_target_float_abi): New function.
+ (mips_d_register_target_info): New function.
+ * config/mips/mips-protos.h (mips_d_register_target_info): Declare.
+ * config/mips/mips.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define.
+ * config/pa/pa-d.c (pa_d_handle_target_float_abi): New function.
+ (pa_d_register_target_info): New function.
+ * config/pa/pa-protos.h (pa_d_register_target_info): Declare.
+ * config/pa/pa.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define.
+ * config/riscv/riscv-d.c (riscv_d_handle_target_float_abi): New
+ function.
+ (riscv_d_register_target_info): New function.
+ * config/riscv/riscv-protos.h (riscv_d_register_target_info): Declare.
+ * config/riscv/riscv.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define.
+ * config/rs6000/rs6000-d.c (rs6000_d_handle_target_float_abi): New
+ function.
+ (rs6000_d_register_target_info): New function.
+ * config/rs6000/rs6000-protos.h (rs6000_d_register_target_info):
+ Declare.
+ * config/rs6000/rs6000.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define.
+ * config/s390/s390-d.c (s390_d_handle_target_float_abi): New function.
+ (s390_d_register_target_info): New function.
+ * config/s390/s390-protos.h (s390_d_register_target_info): Declare.
+ * config/s390/s390.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define.
+ * config/sparc/sparc-d.c (sparc_d_handle_target_float_abi): New
+ function.
+ (sparc_d_register_target_info): New function.
+ * config/sparc/sparc-protos.h (sparc_d_register_target_info): Declare.
+ * config/sparc/sparc.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define.
+ * doc/tm.texi: Regenerate.
+ * doc/tm.texi.in (D language and ABI): Add @hook for
+ TARGET_D_REGISTER_CPU_TARGET_INFO.
+
+2021-04-14 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * config/i386/i386-d.c (ix86_d_has_stdcall_convention): New function.
+ * config/i386/i386-protos.h (ix86_d_has_stdcall_convention): Declare.
+ * config/i386/i386.h (TARGET_D_HAS_STDCALL_CONVENTION): Define.
+ * doc/tm.texi: Regenerate.
+ * doc/tm.texi.in (D language and ABI): Add @hook for
+ TARGET_D_HAS_STDCALL_CONVENTION.
+
+2021-04-14 Richard Biener <rguenther@suse.de>
+
+ * tree-cfg.c (verify_gimple_assign_ternary): Verify that
+ VEC_COND_EXPRs have a gimple_val condition.
+ * tree-ssa-propagate.c (valid_gimple_rhs_p): VEC_COND_EXPR
+ can no longer have a GENERIC condition.
+
+2021-04-14 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/100067
+ * config/arm/arm.c (arm_configure_build_target): Strip isa_all_fpbits
+ from the isa_delta when -mfpu has been used.
+ (arm_options_perform_arch_sanity_checks): It's the architecture that
+ lacks an FPU not the processor.
+
+2021-04-13 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/100053
+ * tree-ssa-sccvn.c (vn_nary_op_get_predicated_value): Do
+ not use optimistic dominance queries for backedges to validate
+ predicated values.
+ (dominated_by_p_w_unex): Add parameter to ignore executable
+ state on backedges.
+ (rpo_elim::eliminate_avail): Adjust.
+
+2021-04-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/100028
+ * config/aarch64/aarch64.md (*aarch64_bfxil<mode>_extr,
+ *aarch64_bfxilsi_extrdi): New define_insn patterns.
+
+2021-04-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/99648
+ * simplify-rtx.c (simplify_immed_subreg): For MODE_COMPOSITE_P
+ outermode, return NULL if the result doesn't encode back to the
+ original byte sequence.
+ (simplify_gen_subreg): Don't create SUBREGs from constants to
+ MODE_COMPOSITE_P outermode.
+
+2021-04-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/99905
+ * combine.c (expand_compound_operation): If pos + len > modewidth,
+ perform the right shift by pos in inner_mode and then convert to mode,
+ instead of trying to simplify a shift of rtx with inner_mode by pos
+ as if it was a shift in mode.
+
+2021-04-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/99830
+ * combine.c (simplify_and_const_int_1): Don't optimize varop
+ away if it has side-effects.
+
+2021-04-12 Martin Liska <mliska@suse.cz>
+
+ * doc/extend.texi: Escape @smallexample content.
+
+2021-04-12 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * config/s390/s390.md ("*movdi_31", "*movdi_64"): Add
+ alternative in order to load a DFP zero.
+
+2021-04-12 Martin Liska <mliska@suse.cz>
+
+ * doc/extend.texi: Be more precise in documentation
+ of symver attribute.
+
+2021-04-12 Martin Liska <mliska@suse.cz>
+
+ PR sanitizer/99877
+ * gimplify.c (gimplify_expr): Right now, we unpoison all
+ variables before a goto <dest>. We should not do it if we are
+ in a omp context.
+
+2021-04-12 Cui,Lili <lili.cui@intel.com>
+
+ * common/config/i386/cpuinfo.h (get_intel_cpu): Handle
+ rocketlake.
+ * common/config/i386/i386-common.c (processor_names): Add
+ rocketlake.
+ (processor_alias_table): Add rocketlake.
+ * common/config/i386/i386-cpuinfo.h (processor_subtypes): Add
+ INTEL_COREI7_ROCKETLAKE.
+ * config.gcc: Add -march=rocketlake.
+ * config/i386/i386-c.c (ix86_target_macros_internal): Handle
+ rocketlake.
+ * config/i386/i386-options.c (m_ROCKETLAKE) : Define.
+ (processor_cost_table): Add rocketlake cost.
+ * config/i386/i386.h (ix86_size_cost) : Define
+ TARGET_ROCKETLAKE.
+ (processor_type) : Add PROCESSOR_ROCKETLAKE.
+ (PTA_ROCKETLAKE): Ditto.
+ * doc/extend.texi: Add rocketlake.
+ * doc/invoke.texi: Add rocketlake.
+
+2021-04-12 Cui,Lili <lili.cui@intel.com>
+
+ * config/i386/i386.h (PTA_ALDERLAKE): Change alderlake ISA list.
+ * config/i386/i386-options.c (m_CORE_AVX2): Add m_ALDERLAKE.
+ * common/config/i386/cpuinfo.h (get_intel_cpu): Add AlderLake model.
+ * doc/invoke.texi: Change alderlake ISA list.
+
+2021-04-11 Hafiz Abid Qadeer <abidh@codesourcery.com>
+
+ PR middle-end/98088
+ * omp-expand.c (expand_oacc_collapse_init): Update condition in
+ a gcc_assert.
+
+2021-04-10 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/99744
+ * config/i386/serializeintrin.h (_serialize): Defined as macro.
+
+2021-04-10 Jakub Jelinek <jakub@redhat.com>
+
+ PR lto/99849
+ * expr.c (expand_expr_addr_expr_1): Test is_global_var rather than
+ just TREE_STATIC on COMPOUND_LITERAL_EXPR_DECLs.
+
+2021-04-10 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/99989
+ * gimple-ssa-warn-alloca.c
+ (alloca_type_and_limit::alloca_type_and_limit): Initialize limit to
+ 0 with integer precision unconditionally.
+
+2021-04-10 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/98601
+ * rtlanal.c (rtx_addr_can_trap_p_1): Allow in assert unknown size
+ not just for BLKmode, but also for VOIDmode. For STRICT_ALIGNMENT
+ unaligned_mems handle VOIDmode like BLKmode.
+
+2021-04-10 Jan Hubicka <hubicka@ucw.cz>
+
+ PR lto/99857
+ * tree.c (free_lang_data_in_decl): Do not release body of
+ declare_variant_alt.
+
+2021-04-09 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_option_restore): If the
+ architecture was specified explicitly and the tuning wasn't,
+ tune for the architecture rather than the configured default CPU.
+
+2021-04-09 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.md (tlsdesc_small_sve_<mode>): Use X30
+ as the temporary register.
+
+2021-04-09 Martin Liska <mliska@suse.cz>
+
+ * doc/extend.texi: Move non-target attributes on the top level.
+
+2021-04-09 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Document minimum and maximum value of the
+ argument for both supported compression algorithms.
+
+2021-04-08 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/rs6000.c (rs6000_xcoff_select_section): Select
+ TLS BSS before TLS data.
+ * config/rs6000/xcoff.h (ASM_OUTPUT_TLS_COMMON): Use .comm.
+
+2021-04-08 Richard Sandiford <richard.sandiford@arm.com>
+
+ * doc/sourcebuild.texi (stdint_types_mbig_endian): Document.
+
+2021-04-08 Richard Sandiford <richard.sandiford@arm.com>
+
+ * match.pd: Extend vec_cond folds to handle shifts.
+
+2021-04-08 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * config/vax/vax.md: Fix comment for `*bit<mode>' pattern's
+ peephole.
+
+2021-04-08 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/99647
+ * config/arm/iterators.md (MVE_vecs): New.
+ (V_elem): Also handle V2DF.
+ * config/arm/mve.md (*mve_mov<mode>): Rename to ...
+ (*mve_vdup<mode>): ... this. Remove second alternative since
+ vec_duplicate of const_int is not canonical RTL, and we don't
+ want to match symbol_refs.
+ (*mve_vec_duplicate<mode>): Delete (pattern is redundant).
+
+2021-04-08 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * fold-const.c (fold_single_bit_test): Fix typo.
+ * print-rtl.c (print_rtx_insn_vec): Call print_rtl_single
+ instead.
+
+2021-04-07 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/97513
+ * tree-vect-slp.c (vect_add_slp_permutation): New function,
+ split out from...
+ (vectorizable_slp_permutation): ...here. Detect cases in which
+ all VEC_PERM_EXPRs are guaranteed to have the same stepped
+ permute vector and only generate one permute vector for that case.
+ Extend that case to handle variable-length vectors.
+
+2021-04-07 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/99873
+ * tree-vect-slp.c (vect_slp_prefer_store_lanes_p): New function.
+ (vect_build_slp_instance): Don't split store groups that could
+ use IFN_STORE_LANES.
+
+2021-04-07 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/99872
+ * varasm.c (output_constant_pool_contents): Don't strip name encoding
+ from XSTR (desc->sym, 0) or from label before passing those to
+ ASM_OUTPUT_DEF.
+
+2021-04-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99954
+ * tree-loop-distribution.c: Include tree-affine.h.
+ (generate_memcpy_builtin): Try using tree-affine to prove
+ non-overlap.
+ (loop_distribution::classify_builtin_ldst): Always classify
+ as PKIND_MEMMOVE.
+
+2021-04-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99947
+ * tree-vect-loop.c (vectorizable_induction): Pre-allocate
+ steps vector to avoid pushing elements from the reallocated
+ vector.
+
+2021-04-07 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-sccvn.h (print_vn_reference_ops): Declare.
+ * tree-ssa-pre.c (print_pre_expr): Factor out VN reference operand
+ printing...
+ * tree-ssa-sccvn.c (print_vn_reference_ops): ... into this new
+ function.
+ (debug_vn_reference_ops): New.
+
+2021-04-07 Bin Cheng <bin.cheng@linux.alibaba.com>
+
+ PR tree-optimization/98736
+ * tree-loop-distribution.c
+ * (loop_distribution::bb_top_order_init):
+ Compute RPO with programing order preserved by calling function
+ rev_post_order_and_mark_dfs_back_seme.
+
+2021-04-06 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR target/99781
+ * lra-constraints.c (split_reg): Don't check paradoxical_subreg_p.
+ * lra-lives.c (clear_sparseset_regnos, regnos_in_sparseset_p): New
+ functions.
+ (process_bb_lives): Don't update biggest mode of hard reg for
+ implicit in multi-register group. Use the new functions for
+ updating dead_set and unused_set by register notes.
+
+2021-04-06 Xianmiao Qu <xianmiao_qu@c-sky.com>
+
+ * config/csky/csky_pipeline_ck802.md : Use insn reservation name
+ instead of *.
+
+2021-04-06 H.J. Lu <hjl.tools@gmail.com>
+
+ * config/i386/x86-tune-costs.h (skylake_memcpy): Updated.
+ (skylake_memset): Likewise.
+ (skylake_cost): Change CLEAR_RATIO to 17.
+ * config/i386/x86-tune.def (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB):
+ Replace m_CANNONLAKE, m_ICELAKE_CLIENT, m_ICELAKE_SERVER,
+ m_TIGERLAKE and m_SAPPHIRERAPIDS with m_SKYLAKE and m_CORE_AVX512.
+
+2021-04-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99880
+ * tree-vect-loop.c (maybe_set_vectorized_backedge_value): Only
+ set vectorized defs of relevant PHIs.
+
+2021-04-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99924
+ * tree-vect-slp.c (vect_bb_partition_graph_r): Do not mark
+ nodes w/o scalar stmts as visited.
+
+2021-04-06 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/99748
+ * config/arm/arm.c (arm_libcall_uses_aapcs_base): Also use base
+ PCS for [su]fix_optab.
+
+2021-04-03 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.c (machopic_legitimize_pic_address): Check
+ that the current pic register is one of the hard reg set
+ before setting liveness.
+
+2021-04-03 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.c (machopic_legitimize_pic_address): Fix
+ whitespace, remove unused code.
+
+2021-04-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/99882
+ * gimple-ssa-store-merging.c (bswap_view_convert): Handle val with
+ pointer type.
+
+2021-04-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/99863
+ * dse.c (replace_read): Drop regs_live argument. Instead of
+ regs_live, use store_insn->fixed_regs_live if non-NULL,
+ otherwise punt if insns sequence clobbers or sets any hard
+ registers.
+
+2021-04-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR testsuite/98125
+ * targhooks.h (default_print_patchable_function_entry_1): Declare.
+ * targhooks.c (default_print_patchable_function_entry_1): New function,
+ copied from default_print_patchable_function_entry with an added flags
+ argument.
+ (default_print_patchable_function_entry): Rewritten into a small
+ wrapper around default_print_patchable_function_entry_1.
+ * config/rs6000/rs6000.c (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY):
+ Redefine.
+ (rs6000_print_patchable_function_entry): New function.
+
+2021-04-02 Eric Botcazou <ebotcazou@adacore.com>
+
+ * doc/invoke.texi (fdelete-dead-exceptions): Minor tweak.
+
+2021-04-01 Jason Merrill <jason@redhat.com>
+
+ PR c++/98481
+ * common.opt: Document v15 and v16.
+
+2021-04-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99863
+ * gimplify.c (gimplify_init_constructor): Recompute vector
+ constructor flags.
+
+2021-04-01 Jakub Jelinek <jakub@redhat.com>
+
+ * doc/extend.texi (symver attribute): Fix up syntax errors
+ in the examples.
+
+2021-04-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/96573
+ * gimple-ssa-store-merging.c (init_symbolic_number): Handle
+ also pointer types.
+
+2021-04-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99856
+ * tree-vect-patterns.c (vect_recog_over_widening_pattern): Promote
+ precision to vector element precision.
+
+2021-04-01 Martin Jambor <mjambor@suse.cz>
+
+ PR tree-optimization/97009
+ * tree-sra.c (access_or_its_child_written): New function.
+ (propagate_subaccesses_from_rhs): Use it instead of a simple grp_write
+ test.
+
+2021-03-31 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/98265
+ * cif-code.def (USES_COMDAT_LOCAL): Make CIF_FINAL_NORMAL.
+
+2021-03-31 Pat Haugen <pthaugen@linux.ibm.com>
+
+ PR target/99133
+ * config/rs6000/altivec.md (xxspltiw_v4si, xxspltiw_v4sf_inst,
+ xxspltidp_v2df_inst, xxsplti32dx_v4si_inst, xxsplti32dx_v4sf_inst,
+ xxblend_<mode>, xxpermx_inst, xxeval): Mark prefixed.
+ * config/rs6000/mma.md (mma_<vvi4i4i8>, mma_<avvi4i4i8>,
+ mma_<vvi4i4i2>, mma_<avvi4i4i2>, mma_<vvi4i4>, mma_<avvi4i4>,
+ mma_<pvi4i2>, mma_<apvi4i2>, mma_<vvi4i4i4>, mma_<avvi4i4i4>):
+ Likewise.
+ * config/rs6000/rs6000.c (rs6000_final_prescan_insn): Adjust test.
+ * config/rs6000/rs6000.md (define_attr "maybe_prefixed"): New.
+ (define_attr "prefixed"): Update initializer.
+
+2021-03-31 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/99490
+ * dwarf2out.c (debug_ranges_dwo_section): New variable.
+ (DW_RANGES_IDX_SKELETON): Define.
+ (struct dw_ranges): Add begin_entry and end_entry members.
+ (DEBUG_DWO_RNGLISTS_SECTION): Define.
+ (add_ranges_num): Adjust r initializer for addition of *_entry
+ members.
+ (add_ranges_by_labels): For -gsplit-dwarf and force_direct,
+ set idx to DW_RANGES_IDX_SKELETON.
+ (use_distinct_base_address_for_range): New function.
+ (index_rnglists): Don't set r->idx if it is equal to
+ DW_RANGES_IDX_SKELETON. Initialize r->begin_entry and
+ r->end_entry for -gsplit-dwarf if those will be needed by
+ output_rnglists.
+ (output_rnglists): Add DWO argument. If true, switch to
+ debug_ranges_dwo_section rather than debug_ranges_section.
+ Adjust l1/l2 label indexes. Only output the offset table when
+ dwo is true and don't include in there the skeleton range
+ entry if present. For -gsplit-dwarf, skip ranges that belong
+ to the other rnglists section. Change return type from void
+ to bool and return true if there are any range entries for
+ the other section. For dwarf_split_debug_info use
+ DW_RLE_startx_endx, DW_RLE_startx_length and DW_RLE_base_addressx
+ entries instead of DW_RLE_start_end, DW_RLE_start_length and
+ DW_RLE_base_address. Use use_distinct_base_address_for_range.
+ (init_sections_and_labels): Initialize debug_ranges_dwo_section
+ if -gsplit-dwarf and DWARF >= 5. Adjust ranges_section_label
+ and range_base_label indexes.
+ (dwarf2out_finish): Call index_rnglists earlier before finalizing
+ .debug_addr. Never emit DW_AT_rnglists_base attribute. For
+ -gsplit-dwarf and DWARF >= 5 call output_rnglists up to twice
+ with different dwo arguments.
+ (dwarf2out_c_finalize): Clear debug_ranges_dwo_section.
+
+2021-03-31 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/98268
+ * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Call
+ recompute_tree_invariant_for_addr_expr after successfully
+ folding a TARGET_MEM_REF that occurs inside an ADDR_EXPR.
+
+2021-03-31 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/99726
+ * tree-data-ref.c (create_intersect_range_checks_index): Bail
+ out if there is more than one access function SCEV for the loop
+ being versioned.
+
+2021-03-31 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR rtl-optimization/97141
+ PR rtl-optimization/98726
+ * emit-rtl.c (valid_for_const_vector_p): Return true for
+ CONST_POLY_INT_P.
+ * rtx-vector-builder.h (rtx_vector_builder::step): Return a
+ poly_wide_int instead of a wide_int.
+ (rtx_vector_builder::apply_set): Take a poly_wide_int instead
+ of a wide_int.
+ * rtx-vector-builder.c (rtx_vector_builder::apply_set): Likewise.
+ * config/aarch64/aarch64.c (aarch64_legitimate_constant_p): Return
+ false for CONST_VECTORs that cannot be forced to memory.
+ * config/aarch64/aarch64-simd.md (mov<mode>): If a CONST_VECTOR
+ is too complex to force to memory, build it up from individual
+ elements instead.
+
+2021-03-31 Jan Hubicka <jh@suse.cz>
+
+ PR lto/99447
+ * cgraph.c (cgraph_node::release_body): Fix overactive check.
+
+2021-03-31 Christophe Lyon <christophe.lyon@linaro.org>
+
+ PR target/99786
+ * config/arm/vec-common.md (mul<mode>3): Disable on iwMMXT, expect
+ for V4HI and V2SI.
+
+2021-03-31 H.J. Lu <hjl.tools@gmail.com>
+
+ * config/i386/i386-expand.c (expand_set_or_cpymem_via_rep):
+ For TARGET_PREFER_KNOWN_REP_MOVSB_STOSB, don't convert QImode
+ to SImode.
+ (decide_alg): For TARGET_PREFER_KNOWN_REP_MOVSB_STOSB, use
+ "rep movsb/stosb" only for known sizes.
+ * config/i386/i386-options.c (processor_cost_table): Use Ice
+ Lake cost for Cannon Lake, Ice Lake, Tiger Lake, Sapphire
+ Rapids and Alder Lake.
+ * config/i386/i386.h (TARGET_PREFER_KNOWN_REP_MOVSB_STOSB): New.
+ * config/i386/x86-tune-costs.h (icelake_memcpy): New.
+ (icelake_memset): Likewise.
+ (icelake_cost): Likewise.
+ * config/i386/x86-tune.def (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB):
+ New.
+
+2021-03-31 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/98119
+ * config/aarch64/aarch64.c
+ (aarch64_vectorize_preferred_vector_alignment): Query the size
+ of the provided SVE vector; do not assume that all SVE vectors
+ have the same size.
+
+2021-03-31 Jan Hubicka <jh@suse.cz>
+
+ PR lto/99447
+ * cgraph.c (cgraph_node::release_body): Remove all callers and
+ references.
+ * cgraphclones.c (cgraph_node::materialize_clone): Do not do it here.
+ * cgraphunit.c (cgraph_node::expand): And here.
+
+2021-03-31 Martin Liska <mliska@suse.cz>
+
+ * ipa-modref.c (analyze_ssa_name_flags): Fix coding style
+ and one negated condition.
+
+2021-03-31 Jakub Jelinek <jakub@redhat.com>
+ Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/99813
+ * config/aarch64/aarch64.md (*add<mode>3_poly_1): Swap Uai and Uav
+ constraints on operands[2] and similarly 0 and rk constraints
+ on operands[1] corresponding to that.
+
+2021-03-31 Jakub Jelinek <jakub@redhat.com>
+
+ PR bootstrap/98860
+ * configure.ac (HAVE_LD_BROKEN_PE_DWARF5): New AC_DEFINE if PECOFF
+ linker doesn't support DWARF sections new in DWARF5.
+ * config/i386/i386-options.c (ix86_option_override_internal): Default
+ to dwarf_version 4 if HAVE_LD_BROKEN_PE_DWARF5 for TARGET_PECOFF
+ targets.
+ * config.in: Regenerated.
+ * configure: Regenerated.
+
+2021-03-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/99820
+ * config/aarch64/aarch64.c (aarch64_analyze_loop_vinfo): Check for
+ available issue_info before using it.
+
+2021-03-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/99822
+ * config/aarch64/aarch64.md (sub<mode>3_compare1_imm): Do not allow zero
+ in operand 1.
+
+2021-03-30 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ PR target/99718
+ * config/rs6000/altivec.md (altivec_lvsl_reg): Change to ...
+ (altivec_lvsl_reg_<mode>): ... this.
+ (altivec_lvsr_reg): Change to ...
+ (altivec_lvsr_reg_<mode>): ... this.
+ * config/rs6000/predicates.md (vec_set_index_operand): New.
+ * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
+ Enable 32bit variable vec_insert for all TARGET_VSX.
+ * config/rs6000/rs6000.c (rs6000_expand_vector_set_var_p9):
+ Enable 32bit variable vec_insert for p9 and above.
+ (rs6000_expand_vector_set_var_p8): Rename to ...
+ (rs6000_expand_vector_set_var_p7): ... this.
+ (rs6000_expand_vector_set): Use TARGET_VSX and adjust assert
+ position.
+ * config/rs6000/vector.md (vec_set<mode>): Use vec_set_index_operand.
+ * config/rs6000/vsx.md (xl_len_r): Use gen_altivec_lvsl_reg_di and
+ gen_altivec_lvsr_reg_di.
+
+2021-03-30 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/99744
+ * config/i386/ia32intrin.h (__rdtsc): Defined as macro.
+ (__rdtscp): Likewise.
+
+2021-03-30 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/99825
+ * tree-vect-slp-patterns.c (vect_check_evenodd_blend):
+ Reject non-mult 2 lanes.
+
+2021-03-30 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/99773
+ * config/arm/arm.c (arm_file_start): Fix emission of
+ Tag_ABI_VFP_args attribute.
+
+2021-03-30 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99824
+ * stor-layout.c (set_min_and_max_values_for_integral_type):
+ Assert the precision is within the bounds of
+ WIDE_INT_MAX_PRECISION.
+ * tree-ssa-sccvn.c (ao_ref_init_from_vn_reference): Use
+ the outermost component ref only to lower the access size
+ and initialize that from the access type.
+
+2021-03-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/98136
+ * config/aarch64/aarch64.md (mov<mode>): Pass multi-instruction
+ CONST_INTs to aarch64_expand_mov_immediate when called after RA.
+
+2021-03-30 Mihailo Stojanovic <mihailo.stojanovic@typhoon-hil.com>
+
+ * config/aarch64/aarch64.md
+ (<optab>_trunc<fcvt_target><GPI:mode>2): Set the "arch"
+ attribute to disambiguate between SIMD and FP variants of the
+ instruction.
+
+2021-03-29 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (merge_call_lhs_flags): Correct handling of deref.
+ (analyze_ssa_name_flags): Fix typo in comment.
+
+2021-03-29 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/99216
+ * config/aarch64/aarch64-sve-builtins.cc
+ (function_builder::add_function): Add placeholder_p argument, use
+ placeholder decls if this is set.
+ (function_builder::add_unique_function): Instead of conditionally adding
+ direct overloads, unconditionally add either a direct overload or a
+ placeholder.
+ (function_builder::add_overloaded_function): Set placeholder_p if we're
+ using C++ overloads. Use the obstack for string storage instead
+ of relying on the tree nodes.
+ (function_builder::add_overloaded_functions): Don't return early for
+ m_direct_overloads: we need to add placeholders.
+ * config/aarch64/aarch64-sve-builtins.h
+ (function_builder::add_function): Add placeholder_p argument.
+
+2021-03-29 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99807
+ * tree-vect-slp.c (vect_slp_analyze_node_operations_1): Move
+ assert below VEC_PERM handling.
+
+2021-03-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/99037
+ * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Use
+ aarch64_simd_or_scalar_imm_zero to match zeroes. Remove pattern
+ matching const_int 0.
+ (move_lo_quad_internal_be_<mode>): Likewise.
+ (move_lo_quad_<mode>): Update for the above.
+ * config/aarch64/iterators.md (VQ_2E): Delete.
+
+2021-03-29 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/99777
+ * fold-const.c (extract_muldiv_1): For conversions, punt on casts from
+ types other than scalar integral types.
+
+2021-03-28 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/rs6000.c (rs6000_output_dwarf_dtprel): Do not add
+ XCOFF TLS reloc decorations.
+
+2021-03-28 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/analyzer.texi (Analyzer Internals): Update link to
+ "A Memory Model for Static Analysis of C Programs".
+
+2021-03-26 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/aix.h (ADJUST_FIELD_ALIGN): Call function.
+ * config/rs6000/rs6000-protos.h (rs6000_special_adjust_field_align):
+ Declare.
+ * config/rs6000/rs6000.c (rs6000_special_adjust_field_align): New.
+ (rs6000_special_round_type_align): Recursively check innermost first
+ field.
+
+2021-03-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/99334
+ * dwarf2out.h (struct dw_fde_node): Add rule18 member.
+ * dwarf2cfi.c (dwarf2out_frame_debug_expr): When handling (set hfp sp)
+ assignment with drap_reg active, queue reg save for hfp with offset 0
+ and flush queued reg saves. When handling a push with rule18,
+ defer queueing reg save for hfp and just assert the offset is 0.
+ (scan_trace): Assert that fde->rule18 is false.
+
+2021-03-26 Vladimir Makarov <vmakarov@redhat.com>
+
+ PR target/99766
+ * ira-costs.c (record_reg_classes): Put case with
+ CT_RELAXED_MEMORY adjacent to one with CT_MEMORY.
+ * ira.c (ira_setup_alts): Ditto.
+ * lra-constraints.c (process_alt_operands): Ditto.
+ * recog.c (asm_operand_ok): Ditto.
+ * reload.c (find_reloads): Ditto.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-protos.h
+ (cpu_addrcost_table::post_modify_ld3_st3): New member variable.
+ (cpu_addrcost_table::post_modify_ld4_st4): Likewise.
+ * config/aarch64/aarch64.c (generic_addrcost_table): Update
+ accordingly, using the same costs as for post_modify.
+ (exynosm1_addrcost_table, xgene1_addrcost_table): Likewise.
+ (thunderx2t99_addrcost_table, thunderx3t110_addrcost_table):
+ (tsv110_addrcost_table, qdf24xx_addrcost_table): Likewise.
+ (a64fx_addrcost_table): Likewise.
+ (neoversev1_addrcost_table): New.
+ (neoversev1_tunings): Use neoversev1_addrcost_table.
+ (aarch64_address_cost): Use the new post_modify costs for CImode
+ and XImode.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.opt
+ (-param=aarch64-loop-vect-issue-rate-niters=): New parameter.
+ * doc/invoke.texi: Document it.
+ * config/aarch64/aarch64-protos.h (aarch64_base_vec_issue_info)
+ (aarch64_scalar_vec_issue_info, aarch64_simd_vec_issue_info)
+ (aarch64_advsimd_vec_issue_info, aarch64_sve_vec_issue_info)
+ (aarch64_vec_issue_info): New structures.
+ (cpu_vector_cost): Write comments above the variables rather
+ than to the side.
+ (cpu_vector_cost::issue_info): New member variable.
+ * config/aarch64/aarch64.c: Include gimple-pretty-print.h
+ and tree-ssa-loop-niter.h.
+ (generic_vector_cost, a64fx_vector_cost, qdf24xx_vector_cost)
+ (thunderx_vector_cost, tsv110_vector_cost, cortexa57_vector_cost)
+ (exynosm1_vector_cost, xgene1_vector_cost, thunderx2t99_vector_cost)
+ (thunderx3t110_vector_cost): Initialize issue_info to null.
+ (neoversev1_scalar_issue_info, neoversev1_advsimd_issue_info)
+ (neoversev1_sve_issue_info, neoversev1_vec_issue_info): New structures.
+ (neoversev1_vector_cost): Use them.
+ (aarch64_vec_op_count, aarch64_sve_op_count): New structures.
+ (aarch64_vector_costs::saw_sve_only_op): New member variable.
+ (aarch64_vector_costs::num_vector_iterations): Likewise.
+ (aarch64_vector_costs::scalar_ops): Likewise.
+ (aarch64_vector_costs::advsimd_ops): Likewise.
+ (aarch64_vector_costs::sve_ops): Likewise.
+ (aarch64_vector_costs::seen_loads): Likewise.
+ (aarch64_simd_vec_costs_for_flags): New function.
+ (aarch64_analyze_loop_vinfo): Initialize num_vector_iterations.
+ Count the number of predicate operations required by SVE WHILE
+ instructions.
+ (aarch64_comparison_type, aarch64_multiply_add_p): New functions.
+ (aarch64_sve_only_stmt_p, aarch64_in_loop_reduction_latency): Likewise.
+ (aarch64_count_ops): Likewise.
+ (aarch64_add_stmt_cost): Record whether see an SVE operation
+ that cannot currently be implementing using Advanced SIMD.
+ Record issue information about the scalar, Advanced SIMD
+ and (where relevant) SVE versions of a loop.
+ (aarch64_vec_op_count::dump): New function.
+ (aarch64_sve_op_count::dump): Likewise.
+ (aarch64_estimate_min_cycles_per_iter): Likewise.
+ (aarch64_adjust_body_cost): If issue information is available,
+ try to compare the issue rates of the various loop implementations
+ and increase or decrease the vector body cost accordingly.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_detect_vector_stmt_subtype):
+ Assume a zero cost for induction phis.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_embedded_comparison_type): New
+ function.
+ (aarch64_adjust_stmt_cost): Add the costs of embedded scalar and
+ vector comparisons.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_detect_scalar_stmt_subtype):
+ New function.
+ (aarch64_add_stmt_cost): Call it.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-tuning-flags.def (matched_vector_throughput):
+ New tuning parameter.
+ * config/aarch64/aarch64.c (neoversev1_tunings): Use it.
+ (aarch64_estimated_sve_vq): New function.
+ (aarch64_vector_costs::analyzed_vinfo): New member variable.
+ (aarch64_vector_costs::is_loop): Likewise.
+ (aarch64_vector_costs::unrolled_advsimd_niters): Likewise.
+ (aarch64_vector_costs::unrolled_advsimd_stmts): Likewise.
+ (aarch64_record_potential_advsimd_unrolling): New function.
+ (aarch64_analyze_loop_vinfo, aarch64_analyze_bb_vinfo): Likewise.
+ (aarch64_add_stmt_cost): Call aarch64_analyze_loop_vinfo or
+ aarch64_analyze_bb_vinfo on the first use of a costs structure.
+ Detect whether we're vectorizing a loop for SVE that might be
+ completely unrolled if it used Advanced SIMD instead.
+ (aarch64_adjust_body_cost_for_latency): New function.
+ (aarch64_finish_cost): Call it.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_vector_costs): New structure.
+ (aarch64_init_cost): New function.
+ (aarch64_add_stmt_cost): Use aarch64_vector_costs instead of
+ the default unsigned[3].
+ (aarch64_finish_cost, aarch64_destroy_cost_data): New functions.
+ (TARGET_VECTORIZE_INIT_COST): Override.
+ (TARGET_VECTORIZE_FINISH_COST): Likewise.
+ (TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (neoversev1_advsimd_vector_cost)
+ (neoversev1_sve_vector_cost): New cost structures.
+ (neoversev1_vector_cost): Likewise.
+ (neoversev1_tunings): Use them. Enable use_new_vector_costs.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-protos.h
+ (sve_vec_cost::scatter_store_elt_cost): New member variable.
+ * config/aarch64/aarch64.c (generic_sve_vector_cost): Update
+ accordingly, taking the cost from the cost of a scalar_store.
+ (a64fx_sve_vector_cost): Likewise.
+ (aarch64_detect_vector_stmt_subtype): Detect scatter stores.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-protos.h
+ (simd_vec_cost::store_elt_extra_cost): New member variable.
+ * config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
+ accordingly, using the vec_to_scalar cost for the new field.
+ (generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
+ (a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
+ (thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
+ (cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
+ (xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
+ (thunderx3t110_advsimd_vector_cost): Likewise.
+ (aarch64_detect_vector_stmt_subtype): Detect single-element stores.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-protos.h (simd_vec_cost::ld2_st2_permute_cost)
+ (simd_vec_cost::ld3_st3_permute_cost): New member variables.
+ (simd_vec_cost::ld4_st4_permute_cost): Likewise.
+ * config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
+ accordingly, using zero for the new costs.
+ (generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
+ (a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
+ (thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
+ (cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
+ (xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
+ (thunderx3t110_advsimd_vector_cost): Likewise.
+ (aarch64_ld234_st234_vectors): New function.
+ (aarch64_adjust_stmt_cost): Likewise.
+ (aarch64_add_stmt_cost): Call aarch64_adjust_stmt_cost if using
+ the new vector costs.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-protos.h (sve_vec_cost): Turn into a
+ derived class of simd_vec_cost. Add information about CLAST[AB]
+ and FADDA instructions.
+ * config/aarch64/aarch64.c (generic_sve_vector_cost): Update
+ accordingly, using the vec_to_scalar costs for the new fields.
+ (a64fx_sve_vector_cost): Likewise.
+ (aarch64_reduc_type): New function.
+ (aarch64_sve_in_loop_reduction_latency): Likewise.
+ (aarch64_detect_vector_stmt_subtype): Take a vinfo parameter.
+ Use aarch64_sve_in_loop_reduction_latency to handle SVE reductions
+ that occur in the loop body.
+ (aarch64_add_stmt_cost): Update call accordingly.
+
+2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-tuning-flags.def (use_new_vector_costs):
+ New tuning flag.
+ * config/aarch64/aarch64-protos.h (simd_vec_cost): Put comments
+ above the fields rather than to the right.
+ (simd_vec_cost::reduc_i8_cost): New member variable.
+ (simd_vec_cost::reduc_i16_cost): Likewise.
+ (simd_vec_cost::reduc_i32_cost): Likewise.
+ (simd_vec_cost::reduc_i64_cost): Likewise.
+ (simd_vec_cost::reduc_f16_cost): Likewise.
+ (simd_vec_cost::reduc_f32_cost): Likewise.
+ (simd_vec_cost::reduc_f64_cost): Likewise.
+ * config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
+ accordingly, using the vec_to_scalar_cost for the new fields.
+ (generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
+ (a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
+ (thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
+ (cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
+ (xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
+ (thunderx3t110_advsimd_vector_cost): Likewise.
+ (aarch64_use_new_vector_costs_p): New function.
+ (aarch64_simd_vec_costs): New function, split out from...
+ (aarch64_builtin_vectorization_cost): ...here.
+ (aarch64_is_reduction): New function.
+ (aarch64_detect_vector_stmt_subtype): Likewise.
+ (aarch64_add_stmt_cost): Call aarch64_detect_vector_stmt_subtype if
+ using the new vector costs.
+
+2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ PR ipa/99466
+ * tree-emutls.c (get_emutls_init_templ_addr): Mark initializer of weak
+ TLS declarations as public.
+
+2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * config/aarch64/aarch64-d.c (IN_TARGET_CODE): Define.
+ * config/arm/arm-d.c (IN_TARGET_CODE): Likewise.
+ * config/i386/i386-d.c (IN_TARGET_CODE): Likewise.
+ * config/mips/mips-d.c (IN_TARGET_CODE): Likewise.
+ * config/pa/pa-d.c (IN_TARGET_CODE): Likewise.
+ * config/riscv/riscv-d.c (IN_TARGET_CODE): Likewise.
+ * config/rs6000/rs6000-d.c (IN_TARGET_CODE): Likewise.
+ * config/s390/s390-d.c (IN_TARGET_CODE): Likewise.
+ * config/sparc/sparc-d.c (IN_TARGET_CODE): Likewise.
+
+2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ PR d/91595
+ * config.gcc (*-*-cygwin*): Add winnt-d.o
+ (*-*-mingw*): Likewise.
+ * config/i386/cygwin.h (EXTRA_TARGET_D_OS_VERSIONS): New macro.
+ * config/i386/mingw32.h (EXTRA_TARGET_D_OS_VERSIONS): Likewise.
+ * config/i386/t-cygming: Add winnt-d.o.
+ * config/i386/winnt-d.c: New file.
+
+2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * config/freebsd-d.c: Include memmodel.h.
+
+2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ PR d/99691
+ * config.gcc (*-*-openbsd*): Add openbsd-d.o.
+ * config/t-openbsd: Add openbsd-d.o.
+ * config/openbsd-d.c: New file.
+
+2021-03-25 Stam Markianos-Wright <stam.markianos-wright@arm.com>
+
+ PR tree-optimization/96974
+ * tree-vect-stmts.c (vect_get_vector_types_for_stmt): Replace assert
+ with graceful exit.
+
+2021-03-25 H.J. Lu <hjl.tools@gmail.com>
+
+ Revert:
+ 2021-03-25 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/98209
+ PR target/99744
+ * config/i386/i386.c (ix86_can_inline_p): Don't check ISA for
+ always_inline in system headers.
+
+2021-03-25 Kewen Lin <linkw@linux.ibm.com>
+
+ * tree-vect-loop.c (vect_model_reduction_cost): Init inside_cost.
+
+2021-03-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/99565
+ * tree-core.h (enum operand_equal_flag): Add OEP_ADDRESS_OF_SAME_FIELD.
+ * fold-const.c (operand_compare::operand_equal_p): Don't compare
+ field offsets if OEP_ADDRESS_OF_SAME_FIELD.
+
+2021-03-25 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/98209
+ PR target/99744
+ * config/i386/i386.c (ix86_can_inline_p): Don't check ISA for
+ always_inline in system headers.
+
+2021-03-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99746
+ * tree-vect-slp-patterns.c (complex_pattern::build): Do not mark
+ the scalar stmt as patterned. Instead set up required things
+ manually.
+
+2021-03-25 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (power8_costs): Change l2 cache
+ from 256 to 512.
+
+2021-03-24 Martin Liska <mliska@suse.cz>
+
+ PR target/99753
+ * common/config/i386/i386-common.c (ARRAY_SIZE): Fix off-by-one
+ error.
+ * config/i386/i386-options.c (ix86_option_override_internal):
+ Add run-time assert.
+
+2021-03-24 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/99122
+ * ipa-cp.c (initialize_node_lattices): Mark as bottom all
+ parameters with unknown type.
+ (ipacp_value_safe_for_type): New function.
+ (propagate_vals_across_arith_jfunc): Verify that the constant type
+ can be used for a type of the formal parameter.
+ (propagate_vals_across_ancestor): Likewise.
+ (propagate_scalar_across_jump_function): Likewise. Pass the type
+ also to propagate_vals_across_ancestor.
+
+2021-03-24 Christophe Lyon <christophe.lyon@linaro.org>
+
+ PR target/99727
+ * config/arm/mve.md (movmisalign<mode>_mve_store): Use Ux
+ constraint.
+ (movmisalign<mode>_mve_load): Likewise.
+
+2021-03-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/99724
+ * config/arm/vec-common.md (one_cmpl<mode>2, neg<mode>2,
+ movmisalign<mode>): Disable expanders for TARGET_REALLY_IWMMXT.
+
+2021-03-24 Alexandre Oliva <oliva@adacore.com>
+
+ * doc/sourcebuild.texi (sysconf): New effective target.
+
+2021-03-24 Alexandre Oliva <oliva@adacore.com>
+
+ * config/i386/predicates.md (reg_or_const_vec_operand): New.
+ * config/i386/sse.md (ssse3_pshufbv8qi3): Add an expander for
+ the now *-prefixed insn_and_split, turn the splitter const vec
+ into an input for the insn, making it an ignored immediate for
+ non-split cases, and loaded into the scratch register
+ otherwise.
+
+2021-03-23 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR target/99581
+ * config/aarch64/constraints.md (Utq, UOb, UOh, UOw, UOd, UOty):
+ Use define_relaxed_memory_constraint for them.
+
+2021-03-23 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR target/99733
+ * config/host-darwin.c (darwin_gt_pch_use_address): Add a
+ colon to the diagnostic message.
+
+2021-03-23 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * fwprop.c (fwprop_propagation::fwprop_propagation): Look at
+ set_info's uses.
+ (try_fwprop_subst_note): Use set_info instead of insn_info.
+ (try_fwprop_subst_pattern): Likewise.
+ (try_fwprop_subst_notes): Likewise.
+ (try_fwprop_subst): Likewise.
+ (forward_propagate_subreg): Likewise.
+ (forward_propagate_and_simplify): Likewise.
+ (forward_propagate_into): Likewise.
+ * rtl-ssa/accesses.h (set_info::single_nondebug_use) New
+ method.
+ (set_info::single_nondebug_insn_use): Likewise.
+ (set_info::single_phi_use): Likewise.
+ * rtl-ssa/member-fns.inl (set_info::single_nondebug_use) New
+ method.
+ (set_info::single_nondebug_insn_use): Likewise.
+ (set_info::single_phi_use): Likewise.
+
+2021-03-23 Christophe Lyon <christophe.lyon@linaro.org>
+
+ * doc/sourcebuild.texi (arm_dsp_ok, arm_dsp): Document.
+
+2021-03-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/99540
+ * config/aarch64/aarch64.c (aarch64_add_offset): Tell
+ expand_mult to perform an unsigned rather than a signed
+ multiplication.
+
+2021-03-23 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/99704
+ * config/i386/cpuid.h (__cpuid): Add __volatile__.
+ (__cpuid_count): Likewise.
+
+2021-03-23 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/99721
+ * tree-vect-slp.c (vect_slp_analyze_node_operations):
+ Make sure we can schedule the node.
+
+2021-03-23 Marcus Comstedt <marcus@mc.pp.se>
+
+ * config/riscv/riscv.c (riscv_subword): Take endianness into
+ account when calculating the byte offset.
+
+2021-03-23 Marcus Comstedt <marcus@mc.pp.se>
+
+ * config/riscv/predicates.md (subreg_lowpart_operator): New predicate
+ * config/riscv/riscv.md (*addsi3_extended2, *subsi3_extended2)
+ (*negsi2_extended2, *mulsi3_extended2, *<optab>si3_mask)
+ (*<optab>si3_mask_1, *<optab>di3_mask, *<optab>di3_mask_1)
+ (*<optab>si3_extend_mask, *<optab>si3_extend_mask_1): Use
+ new predicate "subreg_lowpart_operator"
+
+2021-03-23 Marcus Comstedt <marcus@mc.pp.se>
+
+ * config/riscv/riscv.c (riscv_swap_instruction): New function
+ to byteswap an SImode rtx containing an instruction.
+ (riscv_trampoline_init): Byteswap the generated instructions
+ when needed.
+
+2021-03-23 Marcus Comstedt <marcus@mc.pp.se>
+
+ * common/config/riscv/riscv-common.c
+ (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness.
+ * config.gcc (riscv32be-*, riscv64be-*): Set
+ TARGET_BIG_ENDIAN_DEFAULT to 1.
+ * config/riscv/elf.h (LINK_SPEC): Change -melf* value
+ depending on default endianness.
+ * config/riscv/freebsd.h (LINK_SPEC): Likewise.
+ * config/riscv/linux.h (LINK_SPEC): Likewise.
+ * config/riscv/riscv.c (TARGET_DEFAULT_TARGET_FLAGS): Set
+ default endianness.
+ * config/riscv/riscv.h (DEFAULT_ENDIAN_SPEC): New macro.
+
+2021-03-23 Marcus Comstedt <marcus@mc.pp.se>
+
+ * config/riscv/elf.h (LINK_SPEC): Pass linker endianness flag.
+ * config/riscv/freebsd.h (LINK_SPEC): Likewise.
+ * config/riscv/linux.h (LINK_SPEC): Likewise.
+ * config/riscv/riscv.h (ASM_SPEC): Pass -mbig-endian and
+ -mlittle-endian.
+ (BYTES_BIG_ENDIAN): Handle big endian.
+ (WORDS_BIG_ENDIAN): Define to BYTES_BIG_ENDIAN.
+ * config/riscv/riscv.opt (-mbig-endian, -mlittle-endian): New
+ options.
+ * doc/invoke.texi (-mbig-endian, -mlittle-endian): Document.
+
+2021-03-23 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * regcprop.c (find_oldest_value_reg): Ask target whether
+ different mode is fine for replacement register.
+
+2021-03-23 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/99296
+ * value-range.cc (irange::irange_set_1bit_anti_range): New.
+ (irange::irange_set_anti_range): Call irange_set_1bit_anti_range
+ * value-range.h (irange::irange_set_1bit_anti_range): New.
+
2021-03-22 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/99581
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