-2023-12-16 David Malcolm <dmalcolm@redhat.com>
-
- * json.cc (print_escaped_json_string): New, taken from
- string::print.
- (object::print): Use it for printing keys.
- (string::print): Move implementation to
- print_escaped_json_string.
- (selftest::test_writing_objects): Add a key containing
- quote, backslash, and control characters.
-
-2023-12-16 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * config/aarch64/aarch64-feature-deps.h (fmv_deps_<FEAT_NAME>):
- Define aarch64_feature_flags mask foreach FMV feature.
- * config/aarch64/aarch64-option-extensions.def: Use new macros
- to define FMV feature extensions.
- * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
- Check for target_version attribute after processing target
- attribute.
- (aarch64_fmv_feature_data): New.
- (aarch64_parse_fmv_features): New.
- (aarch64_process_target_version_attr): New.
- (aarch64_option_valid_version_attribute_p): New.
- (get_feature_mask_for_version): New.
- (compare_feature_masks): New.
- (aarch64_compare_version_priority): New.
- (build_ifunc_arg_type): New.
- (make_resolver_func): New.
- (add_condition_to_bb): New.
- (dispatch_function_versions): New.
- (aarch64_generate_version_dispatcher_body): New.
- (aarch64_get_function_versions_dispatcher): New.
- (aarch64_common_function_versions): New.
- (aarch64_mangle_decl_assembler_name): New.
- (TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P): New implementation.
- (TARGET_OPTION_EXPANDED_CLONES_ATTRIBUTE): New implementation.
- (TARGET_OPTION_FUNCTION_VERSIONS): New implementation.
- (TARGET_COMPARE_VERSION_PRIORITY): New implementation.
- (TARGET_GENERATE_VERSION_DISPATCHER_BODY): New implementation.
- (TARGET_GET_FUNCTION_VERSIONS_DISPATCHER): New implementation.
- (TARGET_MANGLE_DECL_ASSEMBLER_NAME): New implementation.
- * config/aarch64/aarch64.h (TARGET_HAS_FMV_TARGET_ATTRIBUTE):
- Set target macro.
- * config/arm/aarch-common.h (enum aarch_parse_opt_result): Add
- new value to report duplicate FMV feature.
- * common/config/aarch64/cpuinfo.h: New file.
-
-2023-12-16 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * attribs.cc (decl_attributes): Pass attribute name to target.
- (is_function_default_version): Update comment to specify
- incompatibility with target_version attributes.
- * cgraphclones.cc (cgraph_node::create_version_clone_with_body):
- Call valid_version_attribute_p for target_version attributes.
- * defaults.h (TARGET_HAS_FMV_TARGET_ATTRIBUTE): New macro.
- * target.def (valid_version_attribute_p): New hook.
- * doc/tm.texi.in: Add new hook.
- * doc/tm.texi: Regenerate.
- * multiple_target.cc (create_dispatcher_calls): Remove redundant
- is_function_default_version check.
- (expand_target_clones): Use target macro to pick attribute name.
- * targhooks.cc (default_target_option_valid_version_attribute_p):
- New.
- * targhooks.h (default_target_option_valid_version_attribute_p):
- New.
- * tree.h (DECL_FUNCTION_VERSIONED): Update comment to include
- target_version attributes.
-
-2023-12-16 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * common/config/aarch64/aarch64-common.cc
- (struct aarch64_option_extension): Remove unused field.
- (all_extensions): Ditto.
- (aarch64_get_extension_string_for_isa_flags): Remove filtering
- of features without native detection.
- * config/aarch64/driver-aarch64.cc (host_detect_local_cpu):
- Explicitly add expected features that lack cpuinfo detection.
-
-2023-12-16 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * common/config/aarch64/aarch64-common.cc
- (aarch64_get_extension_string_for_isa_flags): Fix generation of
- the "+nocrypto" extension.
- * config/aarch64/aarch64.h (AARCH64_ISA_CRYPTO): Remove.
- (TARGET_CRYPTO): Remove.
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
- Don't use TARGET_CRYPTO.
-
-2023-12-15 Mary Bennett <mary.bennett@embecosm.com>
-
- * config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
- * config/riscv/corev.md: Likewise.
-
-2023-12-15 Mary Bennett <mary.bennett@embecosm.com>
-
- * common/config/riscv/riscv-common.cc: Add XCVelw.
- * config/riscv/corev.def: Likewise.
- * config/riscv/corev.md: Likewise.
- * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
- * config/riscv/riscv-ftypes.def: Likewise.
- * config/riscv/riscv.opt: Likewise.
- * doc/extend.texi: Add XCVelw builtin documentation.
- * doc/sourcebuild.texi: Likewise.
-
-2023-12-15 Jeff Law <jlaw@ventanamicro.com>
-
- PR target/110201
- * config/riscv/constraints.md (D03, DsA): Remove unused constraints.
- * config/riscv/predicates.md (const_0_3_operand): New predicate.
- (const_0_10_operand): Likewise.
- * config/riscv/crypto.md (riscv_aes32dsi): Use new predicate. Drop
- unnecessary constraint.
- (riscv_aes32dsmi, riscv_aes64im, riscv_aes32esi): Likewise.
- (riscv_aes32esmi, *riscv_<sm4_op>_si): Likewise.
- (riscv_<sm4_op>_di_extend, riscv_<sm4_op>_si): Likewise.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config.gcc: Add aarch64-ldp-fusion.o to extra_objs for aarch64.
- * config/aarch64/aarch64-passes.def: Add copies of pass_ldp_fusion
- before and after RA.
- * config/aarch64/aarch64-protos.h (make_pass_ldp_fusion): Declare.
- * config/aarch64/aarch64.opt (-mearly-ldp-fusion): New.
- (-mlate-ldp-fusion): New.
- (--param=aarch64-ldp-alias-check-limit): New.
- (--param=aarch64-ldp-writeback): New.
- * config/aarch64/t-aarch64: Add rule for aarch64-ldp-fusion.o.
- * config/aarch64/aarch64-ldp-fusion.cc: New file.
- * doc/invoke.texi (AArch64 Options): Document new
- -m{early,late}-ldp-fusion options.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64-ldpstp.md: Abstract ldp/stp
- representation from peepholes, allowing use of new form.
- * config/aarch64/aarch64-modes.def (V2x4QImode): Define.
- * config/aarch64/aarch64-protos.h
- (aarch64_finish_ldpstp_peephole): Declare.
- (aarch64_swap_ldrstr_operands): Delete declaration.
- (aarch64_gen_load_pair): Adjust parameters.
- (aarch64_gen_store_pair): Likewise.
- * config/aarch64/aarch64-simd.md (load_pair<DREG:mode><DREG2:mode>):
- Delete.
- (vec_store_pair<DREG:mode><DREG2:mode>): Delete.
- (load_pair<VQ:mode><VQ2:mode>): Delete.
- (vec_store_pair<VQ:mode><VQ2:mode>): Delete.
- * config/aarch64/aarch64.cc (aarch64_pair_mode_for_mode): New.
- (aarch64_gen_store_pair): Adjust to use new unspec form of stp.
- Drop second mem from parameters.
- (aarch64_gen_load_pair): Likewise.
- (aarch64_pair_mem_from_base): New.
- (aarch64_save_callee_saves): Emit REG_CFA_OFFSET notes for
- frame-related saves. Adjust call to aarch64_gen_store_pair
- (aarch64_restore_callee_saves): Adjust calls to
- aarch64_gen_load_pair to account for change in interface.
- (aarch64_process_components): Likewise.
- (aarch64_classify_address): Handle 32-byte pair mems in
- LDP_STP_N case.
- (aarch64_print_operand): Likewise.
- (aarch64_copy_one_block_and_progress_pointers): Adjust calls to
- account for change in aarch64_gen_{load,store}_pair interface.
- (aarch64_set_one_block_and_progress_pointer): Likewise.
- (aarch64_finish_ldpstp_peephole): New.
- (aarch64_gen_adjusted_ldpstp): Adjust to use generation helper.
- * config/aarch64/aarch64.md (ldpstp): New attribute.
- (load_pair_sw_<SX:mode><SX2:mode>): Delete.
- (load_pair_dw_<DX:mode><DX2:mode>): Delete.
- (load_pair_dw_<TX:mode><TX2:mode>): Delete.
- (*load_pair_<ldst_sz>): New.
- (*load_pair_16): New.
- (store_pair_sw_<SX:mode><SX2:mode>): Delete.
- (store_pair_dw_<DX:mode><DX2:mode>): Delete.
- (store_pair_dw_<TX:mode><TX2:mode>): Delete.
- (*store_pair_<ldst_sz>): New.
- (*store_pair_16): New.
- (*load_pair_extendsidi2_aarch64): Adjust to use new form.
- (*zero_extendsidi2_aarch64): Likewise.
- * config/aarch64/iterators.md (VPAIR): New.
- * config/aarch64/predicates.md (aarch64_mem_pair_operand): Change to
- a special predicate derived from aarch64_mem_pair_operator.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_ldpstp_operand_mode_p): Declare.
- * config/aarch64/aarch64.cc (aarch64_gen_storewb_pair): Build RTL
- directly instead of invoking named pattern.
- (aarch64_gen_loadwb_pair): Likewise.
- (aarch64_ldpstp_operand_mode_p): New.
- * config/aarch64/aarch64.md (loadwb_pair<GPI:mode>_<P:mode>): Replace with
- ...
- (*loadwb_post_pair_<ldst_sz>): ... this. Generalize as described
- in cover letter.
- (loadwb_pair<GPF:mode>_<P:mode>): Delete (superseded by the
- above).
- (*loadwb_post_pair_16): New.
- (*loadwb_pre_pair_<ldst_sz>): New.
- (loadwb_pair<TX:mode>_<P:mode>): Delete.
- (*loadwb_pre_pair_16): New.
- (storewb_pair<GPI:mode>_<P:mode>): Replace with ...
- (*storewb_pre_pair_<ldst_sz>): ... this. Generalize as
- described in cover letter.
- (*storewb_pre_pair_16): New.
- (storewb_pair<GPF:mode>_<P:mode>): Delete.
- (*storewb_post_pair_<ldst_sz>): New.
- (storewb_pair<TX:mode>_<P:mode>): Delete.
- (*storewb_post_pair_16): New.
- * config/aarch64/predicates.md (aarch64_mem_pair_operator): New.
- (pmode_plus_operator): New.
- (aarch64_ldp_reg_operand): New.
- (aarch64_stp_reg_operand): New.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_print_address_internal): Handle SVE
- modes when printing ldp/stp addresses.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_const_zero_rtx_p): New.
- * config/aarch64/aarch64.cc (aarch64_const_zero_rtx_p): New.
- Use it ...
- (aarch64_print_operand): ... here. Recognize CONST0_RTXes in
- modes other than VOIDmode.
-
-2023-12-15 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * common/config/riscv/riscv-common.cc:
- (riscv_implied_info): Add zvfbfmin item.
- (riscv_ext_version_table): Ditto.
- (riscv_ext_flag_table): Ditto.
- * config/riscv/riscv.opt:
- (MASK_ZVFBFMIN): New macro.
- (MASK_VECTOR_ELEN_BF_16): Ditto.
- (TARGET_ZVFBFMIN): Ditto.
-
-2023-12-15 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- * config/aarch64/aarch64.opt (aarch64_mops_memmove_size_threshold):
- Change default.
- * config/aarch64/aarch64.md (cpymemdi): Add a parameter.
- (movmemdi): Call aarch64_expand_cpymem.
- * config/aarch64/aarch64.cc (aarch64_copy_one_block): Rename function,
- simplify, support storing generated loads/stores.
- (aarch64_expand_cpymem): Support expansion of memmove.
- * config/aarch64/aarch64-protos.h (aarch64_expand_cpymem): Add bool arg.
-
-2023-12-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (shuffle_merge_patterns): Fix bug.
-
-2023-12-15 Jakub Jelinek <jakub@redhat.com>
-
- * target.h (struct bitint_info): Add abi_limb_mode member, adjust
- comment.
- * target.def (bitint_type_info): Mention abi_limb_mode instead of
- limb_mode.
- * varasm.cc (output_constant): Use abi_limb_mode rather than
- limb_mode.
- * stor-layout.cc (finish_bitfield_representative): Likewise. Assert
- that if precision is smaller or equal to abi_limb_mode precision or
- if info.big_endian is different from WORDS_BIG_ENDIAN, info.limb_mode
- must be the same as info.abi_limb_mode.
- (layout_type): Use abi_limb_mode rather than limb_mode.
- * gimple-fold.cc (clear_padding_bitint_needs_padding_p): Likewise.
- (clear_padding_type): Likewise.
- * config/i386/i386.cc (ix86_bitint_type_info): Also set
- info->abi_limb_mode.
- * doc/tm.texi: Regenerated.
-
-2023-12-15 Julian Brown <julian@codesourcery.com>
-
- * gimplify.cc (extract_base_bit_offset): Add VARIABLE_OFFSET parameter.
- (omp_get_attachment, omp_group_last, omp_group_base,
- omp_directive_maps_explicitly): Add GOMP_MAP_STRUCT_UNORD support.
- (omp_accumulate_sibling_list): Update calls to extract_base_bit_offset.
- Support GOMP_MAP_STRUCT_UNORD.
- (omp_build_struct_sibling_lists, gimplify_scan_omp_clauses,
- gimplify_adjust_omp_clauses, gimplify_omp_target_update): Add
- GOMP_MAP_STRUCT_UNORD support.
- * omp-low.cc (lower_omp_target): Add GOMP_MAP_STRUCT_UNORD support.
- * tree-pretty-print.cc (dump_omp_clause): Likewise.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- PR target/112906
- * config/aarch64/aarch64-sve.md (@aarch64_vec_duplicate_vq<mode>_le):
- Use force_reload_address to reload addresses that aren't suitable for
- ld1rq in the pre-RA splitter.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- PR target/112906
- * emit-rtl.cc (address_reload_context::emit_autoinc): New.
- (force_reload_address): New.
- * emit-rtl.h (struct address_reload_context): Declare.
- (force_reload_address): Declare.
- * lra-constraints.cc (class lra_autoinc_reload_context): New.
- (emit_inc): Drop IN parameter, invoke
- code moved to emit-rtl.cc:address_reload_context::emit_autoinc.
- (curr_insn_transform): Drop redundant IN parameter in call to
- emit_inc.
- * recog.h (class recog_data_saver): New.
-
-2023-12-15 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/113024
- * match.pd (two conversions in a row): Simplify scalar integer
- sign-extension followed by truncation.
-
-2023-12-15 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/113003
- * gimple-lower-bitint.cc (arith_overflow_arg_kind): New function.
- (gimple_lower_bitint): Use it to catch .{ADD,SUB,MUL}_OVERFLOW
- calls with large/huge INTEGER_CST arguments.
-
-2023-12-15 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/install.texi (Specific) <nvptx-*-none>: Update nvptx-tools
- Github link.
-
-2023-12-15 Hongyu Wang <hongyu.wang@intel.com>
-
- PR target/112824
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Sync ix86_move_max/ix86_store_max with prefer_vector_width when
- it is explicitly set.
-
-2023-12-15 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/driver-i386.cc (host_detect_local_cpu): Do not
- set Grand Ridge depending on RAO-INT.
- * config/i386/i386.h: Remove PTA_RAOINT from PTA_GRANDRIDGE.
- * doc/invoke.texi: Adjust documentation.
-
-2023-12-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112387
- * config/riscv/riscv.cc: Adapt generic cost model same ARM SVE.
-
-2023-12-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111153
- * tree-vect-loop.cc (vect_estimate_min_profitable_iters):
- Remove address cost for select_vl/decrement IV.
-
-2023-12-14 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR middle-end/111260
- * optabs.cc (emit_conditional_move): Change the modes to be
- equal before forcing the constant to a register.
-
-2023-12-14 Di Zhao <dizhao@os.amperecomputing.com>
-
- PR tree-optimization/110279
- * doc/invoke.texi: New parameter fully-pipelined-fma.
- * params.opt: New parameter fully-pipelined-fma.
- * tree-ssa-reassoc.cc (get_mult_latency_consider_fma): Return
- the latency of MULT_EXPRs that can't be hidden by the FMAs.
- (get_reassociation_width): Search for a smaller width
- considering the benefit of fully pipelined FMA.
- (rank_ops_for_fma): Return the number of MULT_EXPRs.
- (reassociate_bb): Pass the number of MULT_EXPRs to
- get_reassociation_width; avoid calling
- get_reassociation_width twice.
-
-2023-12-14 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112999
- * expmed.cc (extract_bit_field_1): Ensure better mode
- has fitting unit_precision.
-
-2023-12-14 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112773
- * config/riscv/autovec.md (vec_extract<mode>bi): New expander
- calling vec_extract<mode>qi.
- * config/riscv/riscv-protos.h (riscv_legitimize_poly_move):
- Export.
- (emit_vec_extract): Change argument from poly_int64 to rtx.
- * config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns):
- Ditto.
- * config/riscv/riscv.cc (riscv_legitimize_poly_move): Export.
- (riscv_legitimize_move): Use rtx instead of poly_int64.
- * expmed.cc (store_bit_field_1): Change BITSIZE to PRECISION.
- (extract_bit_field_1): Change BITSIZE to PRECISION and use
- return mode from insn_data as target mode.
-
-2023-12-14 Alex Coplan <alex.coplan@arm.com>
-
- * doc/extend.texi: Document AArch64 Operand Modifiers.
-
-2023-12-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/113018
- * tree-vect-slp.cc (vect_slp_check_for_roots): Only start
- SLP discovery from stmts with a LHS.
-
-2023-12-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112793
- * tree-vect-slp.cc (vect_schedule_slp_node): Already
- code-generated constant/external nodes are OK.
-
-2023-12-14 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-early-ra.cc (allocno_info::is_equiv): New
- member variable.
- (allocno_info::equiv_allocno): Replace with...
- (allocno_info::related_allocno): ...this member variable.
- (allocno_info::chain_prev): Put into an enum with...
- (allocno_info::last_use_point): ...this new member variable.
- (color_info::num_fpr_preferences): New member variable.
- (early_ra::m_shared_allocnos): Likewise.
- (allocno_info::is_shared): New member function.
- (allocno_info::is_equiv_to): Likewise.
- (early_ra::dump_allocnos): Dump sharing information. Tweak column
- widths.
- (early_ra::fpr_preference): Check ALLOWS_NONFPR before returning -2.
- (early_ra::start_new_region): Handle m_shared_allocnos.
- (early_ra::create_allocno_group): Set related_allocno rather than
- equiv_allocno.
- (early_ra::record_allocno_use): Likewise. Detect multiple calls
- for the same program point. Update last_use_point and is_equiv.
- Clear is_strong_copy_src rather than is_strong_copy_dest.
- (early_ra::record_allocno_def): Use related_allocno rather than
- equiv_allocno. Update last_use_point.
- (early_ra::valid_equivalence_p): Replace with...
- (early_ra::find_related_start): ...this new function.
- (early_ra::record_copy): Look for cases where a destination copy chain
- can be shared with the source allocno.
- (early_ra::find_strided_accesses): Update for equiv_allocno->
- related_allocno change. Only call consider_strong_copy_src_chain
- at the head of a copy chain.
- (early_ra::is_chain_candidate): Skip shared allocnos. Update for
- new representation of equivalent allocnos.
- (early_ra::chain_allocnos): Update for new representation of
- equivalent allocnos.
- (early_ra::try_to_chain_allocnos): Likewise.
- (early_ra::merge_fpr_info): New function, split out from...
- (early_ra::set_single_color_rep): ...here.
- (early_ra::form_chains): Handle shared allocnos.
- (early_ra::process_copies): Count the number of FPR preferences.
- (early_ra::cmp_decreasing_size): Rename to...
- (early_ra::cmp_allocation_order): ...this. Sort equal-sized groups
- by the number of FPR preferences.
- (early_ra::finalize_allocation): Handle shared allocnos.
- (early_ra::process_region): Reset chain_prev as well as chain_next.
-
-2023-12-14 Alexandre Oliva <oliva@adacore.com>
-
- PR middle-end/112938
- * ipa-strub.cc (pass_ipa_strub::execute): Pass volatile args
- by reference to internal strub wrapped bodies.
-
-2023-12-14 Alexandre Oliva <oliva@adacore.com>
-
- PR middle-end/112938
- * ipa-strub.cc (pass_ipa_strub::execute): Handle promoted
- volatile args in internal strub. Simplify.
-
-2023-12-14 Thomas Schwinge <thomas@codesourcery.com>
-
- * gimple-ssa-sccopy.cc: '#define INCLUDE_ALGORITHM' instead of
- '#include <algorithm>'.
-
-2023-12-14 Feng Wang <wangfeng@eswincomputing.com>
-
- Revert:
- 2023-12-12 Feng Wang <wangfeng@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
- Add AVAIL argument.
- (read_vl): Using AVAIL argument default value.
- (vlenb): Ditto.
- (vsetvl): Ditto.
- (vsetvlmax): Ditto.
- (vle): Ditto.
- (vse): Ditto.
- (vlm): Ditto.
- (vsm): Ditto.
- (vlse): Ditto.
- (vsse): Ditto.
- (vluxei8): Ditto.
- (vluxei16): Ditto.
- (vluxei32): Ditto.
- (vluxei64): Ditto.
- (vloxei8): Ditto.
- (vloxei16): Ditto.
- (vloxei32): Ditto.
- (vloxei64): Ditto.
- (vsuxei8): Ditto.
- (vsuxei16): Ditto.
- (vsuxei32): Ditto.
- (vsuxei64): Ditto.
- (vsoxei8): Ditto.
- (vsoxei16): Ditto.
- (vsoxei32): Ditto.
- (vsoxei64): Ditto.
- (vleff): Ditto.
- (vadd): Ditto.
- (vsub): Ditto.
- (vrsub): Ditto.
- (vneg): Ditto.
- (vwaddu): Ditto.
- (vwsubu): Ditto.
- (vwadd): Ditto.
- (vwsub): Ditto.
- (vwcvt_x): Ditto.
- (vwcvtu_x): Ditto.
- (vzext): Ditto.
- (vsext): Ditto.
- (vadc): Ditto.
- (vmadc): Ditto.
- (vsbc): Ditto.
- (vmsbc): Ditto.
- (vand): Ditto.
- (vor): Ditto.
- (vxor): Ditto.
- (vnot): Ditto.
- (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- (vnsrl): Ditto.
- (vnsra): Ditto.
- (vncvt_x): Ditto.
- (vmseq): Ditto.
- (vmsne): Ditto.
- (vmsltu): Ditto.
- (vmslt): Ditto.
- (vmsleu): Ditto.
- (vmsle): Ditto.
- (vmsgtu): Ditto.
- (vmsgt): Ditto.
- (vmsgeu): Ditto.
- (vmsge): Ditto.
- (vminu): Ditto.
- (vmin): Ditto.
- (vmaxu): Ditto.
- (vmax): Ditto.
- (vmul): Ditto.
- (vmulh): Ditto.
- (vmulhu): Ditto.
- (vmulhsu): Ditto.
- (vdivu): Ditto.
- (vdiv): Ditto.
- (vremu): Ditto.
- (vrem): Ditto.
- (vwmul): Ditto.
- (vwmulu): Ditto.
- (vwmulsu): Ditto.
- (vmacc): Ditto.
- (vnmsac): Ditto.
- (vmadd): Ditto.
- (vnmsub): Ditto.
- (vwmaccu): Ditto.
- (vwmacc): Ditto.
- (vwmaccsu): Ditto.
- (vwmaccus): Ditto.
- (vmerge): Ditto.
- (vmv_v): Ditto.
- (vsaddu): Ditto.
- (vsadd): Ditto.
- (vssubu): Ditto.
- (vssub): Ditto.
- (vaaddu): Ditto.
- (vaadd): Ditto.
- (vasubu): Ditto.
- (vasub): Ditto.
- (vsmul): Ditto.
- (vssrl): Ditto.
- (vssra): Ditto.
- (vnclipu): Ditto.
- (vnclip): Ditto.
- (vfadd): Ditto.
- (vfsub): Ditto.
- (vfrsub): Ditto.
- (vfadd_frm): Ditto.
- (vfsub_frm): Ditto.
- (vfrsub_frm): Ditto.
- (vfwadd): Ditto.
- (vfwsub): Ditto.
- (vfwadd_frm): Ditto.
- (vfwsub_frm): Ditto.
- (vfmul): Ditto.
- (vfdiv): Ditto.
- (vfrdiv): Ditto.
- (vfmul_frm): Ditto.
- (vfdiv_frm): Ditto.
- (vfrdiv_frm): Ditto.
- (vfwmul): Ditto.
- (vfwmul_frm): Ditto.
- (vfmacc): Ditto.
- (vfnmsac): Ditto.
- (vfmadd): Ditto.
- (vfnmsub): Ditto.
- (vfnmacc): Ditto.
- (vfmsac): Ditto.
- (vfnmadd): Ditto.
- (vfmsub): Ditto.
- (vfmacc_frm): Ditto.
- (vfnmacc_frm): Ditto.
- (vfmsac_frm): Ditto.
- (vfnmsac_frm): Ditto.
- (vfmadd_frm): Ditto.
- (vfnmadd_frm): Ditto.
- (vfmsub_frm): Ditto.
- (vfnmsub_frm): Ditto.
- (vfwmacc): Ditto.
- (vfwnmacc): Ditto.
- (vfwmsac): Ditto.
- (vfwnmsac): Ditto.
- (vfwmacc_frm): Ditto.
- (vfwnmacc_frm): Ditto.
- (vfwmsac_frm): Ditto.
- (vfwnmsac_frm): Ditto.
- (vfsqrt): Ditto.
- (vfsqrt_frm): Ditto.
- (vfrsqrt7): Ditto.
- (vfrec7): Ditto.
- (vfrec7_frm): Ditto.
- (vfmin): Ditto.
- (vfmax): Ditto.
- (vfsgnj): Ditto.
- (vfsgnjn): Ditto.
- (vfsgnjx): Ditto.
- (vfneg): Ditto.
- (vfabs): Ditto.
- (vmfeq): Ditto.
- (vmfne): Ditto.
- (vmflt): Ditto.
- (vmfle): Ditto.
- (vmfgt): Ditto.
- (vmfge): Ditto.
- (vfclass): Ditto.
- (vfmerge): Ditto.
- (vfmv_v): Ditto.
- (vfcvt_x): Ditto.
- (vfcvt_xu): Ditto.
- (vfcvt_rtz_x): Ditto.
- (vfcvt_rtz_xu): Ditto.
- (vfcvt_f): Ditto.
- (vfcvt_x_frm): Ditto.
- (vfcvt_xu_frm): Ditto.
- (vfcvt_f_frm): Ditto.
- (vfwcvt_x): Ditto.
- (vfwcvt_xu): Ditto.
- (vfwcvt_rtz_x): Ditto.
- (vfwcvt_rtz_xu) Ditto.:
- (vfwcvt_f): Ditto.
- (vfwcvt_x_frm): Ditto.
- (vfwcvt_xu_frm) Ditto.:
- (vfncvt_x): Ditto.
- (vfncvt_xu): Ditto.
- (vfncvt_rtz_x): Ditto.
- (vfncvt_rtz_xu): Ditto.
- (vfncvt_f): Ditto.
- (vfncvt_rod_f): Ditto.
- (vfncvt_x_frm): Ditto.
- (vfncvt_xu_frm): Ditto.
- (vfncvt_f_frm): Ditto.
- (vredsum): Ditto.
- (vredmaxu): Ditto.
- (vredmax): Ditto.
- (vredminu): Ditto.
- (vredmin): Ditto.
- (vredand): Ditto.
- (vredor): Ditto.
- (vredxor): Ditto.
- (vwredsum): Ditto.
- (vwredsumu): Ditto.
- (vfredusum): Ditto.
- (vfredosum): Ditto.
- (vfredmax): Ditto.
- (vfredmin): Ditto.
- (vfredusum_frm): Ditto.
- (vfredosum_frm): Ditto.
- (vfwredosum): Ditto.
- (vfwredusum): Ditto.
- (vfwredosum_frm): Ditto.
- (vfwredusum_frm): Ditto.
- (vmand): Ditto.
- (vmnand): Ditto.
- (vmandn): Ditto.
- (vmxor): Ditto.
- (vmor): Ditto.
- (vmnor): Ditto.
- (vmorn): Ditto.
- (vmxnor): Ditto.
- (vmmv): Ditto.
- (vmclr): Ditto.
- (vmset): Ditto.
- (vmnot): Ditto.
- (vcpop): Ditto.
- (vfirst): Ditto.
- (vmsbf): Ditto.
- (vmsif): Ditto.
- (vmsof): Ditto.
- (viota): Ditto.
- (vid): Ditto.
- (vmv_x): Ditto.
- (vmv_s): Ditto.
- (vfmv_f): Ditto.
- (vfmv_s): Ditto.
- (vslideup): Ditto.
- (vslidedown): Ditto.
- (vslide1up): Ditto.
- (vslide1down): Ditto.
- (vfslide1up): Ditto.
- (vfslide1down): Ditto.
- (vrgather): Ditto.
- (vrgatherei16): Ditto.
- (vcompress): Ditto.
- (vundefined): Ditto.
- (vreinterpret): Ditto.
- (vlmul_ext): Ditto.
- (vlmul_trunc): Ditto.
- (vset): Ditto.
- (vget): Ditto.
- (vcreate): Ditto.
- (vlseg): Ditto.
- (vsseg): Ditto.
- (vlsseg): Ditto.
- (vssseg): Ditto.
- (vluxseg): Ditto.
- (vloxseg): Ditto.
- (vsuxseg): Ditto.
- (vsoxseg): Ditto.
- (vlsegff): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): Using variadic macro.
- * config/riscv/riscv-vector-builtins.h (struct function_group_info):
- Add avail function interface into struct.
- * config/riscv/t-riscv: Add dependency
- * config/riscv/riscv-vector-builtins-avail.h: New file.The definition of AVAIL marco.
-
-2023-12-14 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112994
- * match.pd ((t * u) / (t * v) -> (u / v)): New simplification.
-
-2023-12-14 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112994
- * match.pd ((t * 2) / 2 -> t): Adjust comment to use u instead of 2.
- Punt without range checks if TYPE_OVERFLOW_SANITIZED.
- ((t * u) / v -> t * (u / v)): New simplification.
-
-2023-12-14 Filip Kastl <fkastl@suse.cz>
-
- * Makefile.in: Added sccopy pass.
- * passes.def: Added sccopy pass before LTO streaming and before
- RTL expansion.
- * tree-pass.h (make_pass_sccopy): Added sccopy pass.
- * gimple-ssa-sccopy.cc: New file.
-
-2023-12-14 Martin Jambor <mjambor@suse.cz>
-
- PR tree-optimization/111807
- * tree-sra.cc (build_ref_for_model): Allow offset smaller than
- model->offset when gsi is non-NULL. Adjust function comment.
-
-2023-12-14 liuhongt <hongtao.liu@intel.com>
-
- PR target/112992
- * config/i386/i386-expand.cc
- (ix86_convert_const_wide_int_to_broadcast): Don't convert to
- broadcast for vec_dup{v4di,v8si} when TARGET_AVX2 is not
- available.
- (ix86_broadcast_from_constant): Allow broadcast for V4DI/V8SI
- when !TARGET_AVX2 since it will be forced to memory later.
- (ix86_expand_vector_move): Force constant to mem for
- vec_dup{vssi,v4di} when TARGET_AVX2 is not available.
-
-2023-12-14 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111153
- * config/riscv/riscv-protos.h (struct common_vector_cost): New struct.
- (struct scalable_vector_cost): Ditto.
- (struct cpu_vector_cost): Ditto.
- * config/riscv/riscv-vector-costs.cc (costs::add_stmt_cost): Add RVV
- builtin vectorization cost
- * config/riscv/riscv.cc (struct riscv_tune_param): Ditto.
- (get_common_costs): New function.
- (riscv_builtin_vectorization_cost): Ditto.
- (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): New targethook.
-
-2023-12-13 Richard Ball <richard.ball@arm.com>
-
- * config.gcc: Adds new header to config.
- * config/aarch64/aarch64-builtins.cc (enum aarch64_type_qualifiers):
- Moved to header file.
- (ENTRY): Likewise.
- (enum aarch64_simd_type): Likewise.
- (struct aarch64_simd_type_info): Remove static.
- (GTY): Likewise.
- * config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64):
- Defines pragma for arm_neon_sve_bridge.h.
- * config/aarch64/aarch64-protos.h:
- Add handle_arm_neon_sve_bridge_h
- * config/aarch64/aarch64-sve-builtins-base.h: New intrinsics.
- * config/aarch64/aarch64-sve-builtins-base.cc
- (class svget_neonq_impl): New intrinsic implementation.
- (class svset_neonq_impl): Likewise.
- (class svdup_neonq_impl): Likewise.
- (NEON_SVE_BRIDGE_FUNCTION): New intrinsics.
- * config/aarch64/aarch64-sve-builtins-functions.h
- (NEON_SVE_BRIDGE_FUNCTION): Defines macro for NEON_SVE_BRIDGE
- functions.
- * config/aarch64/aarch64-sve-builtins-shapes.h: New shapes.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (parse_element_type): Add NEON element types.
- (parse_type): Likewise.
- (struct get_neonq_def): Defines function shape for get_neonq.
- (struct set_neonq_def): Defines function shape for set_neonq.
- (struct dup_neonq_def): Defines function shape for dup_neonq.
- * config/aarch64/aarch64-sve-builtins.cc
- (DEF_SVE_TYPE_SUFFIX): Changed to be called through
- SVE_NEON macro.
- (DEF_SVE_NEON_TYPE_SUFFIX): Defines
- macro for NEON_SVE_BRIDGE type suffixes.
- (DEF_NEON_SVE_FUNCTION): Defines
- macro for NEON_SVE_BRIDGE functions.
- (function_resolver::infer_neon128_vector_type): Infers type suffix
- for overloaded functions.
- (handle_arm_neon_sve_bridge_h): Handles #pragma arm_neon_sve_bridge.h.
- * config/aarch64/aarch64-sve-builtins.def
- (DEF_SVE_NEON_TYPE_SUFFIX): Macro for handling neon_sve type suffixes.
- (bf16): Replace entry with neon-sve entry.
- (f16): Likewise.
- (f32): Likewise.
- (f64): Likewise.
- (s8): Likewise.
- (s16): Likewise.
- (s32): Likewise.
- (s64): Likewise.
- (u8): Likewise.
- (u16): Likewise.
- (u32): Likewise.
- (u64): Likewise.
- * config/aarch64/aarch64-sve-builtins.h
- (GCC_AARCH64_SVE_BUILTINS_H): Include aarch64-builtins.h.
- (ENTRY): Add aarch64_simd_type definiton.
- (enum aarch64_simd_type): Add neon information to type_suffix_info.
- (struct type_suffix_info): New function.
- * config/aarch64/aarch64-sve.md
- (@aarch64_sve_get_neonq_<mode>): New intrinsic insn for big endian.
- (@aarch64_sve_set_neonq_<mode>): Likewise.
- * config/aarch64/iterators.md: Add UNSPEC_SET_NEONQ.
- * config/aarch64/aarch64-builtins.h: New file.
- * config/aarch64/aarch64-neon-sve-bridge-builtins.def: New file.
- * config/aarch64/arm_neon_sve_bridge.h: New file.
-
-2023-12-13 Patrick Palka <ppalka@redhat.com>
-
- * doc/invoke.texi (C++ Dialect Options): Document
- -fdiagnostics-all-candidates.
-
-2023-12-13 Julian Brown <julian@codesourcery.com>
-
- * gimplify.cc (omp_map_clause_descriptor_p): New function.
- (build_omp_struct_comp_nodes, omp_get_attachment, omp_group_base): Use
- above function.
- (omp_tsort_mapping_groups): Process nodes that have
- OMP_CLAUSE_MAP_RUNTIME_IMPLICIT_P set after those that don't. Add
- enter_exit_data parameter.
- (omp_resolve_clause_dependencies): Remove GOMP_MAP_TO_PSET mappings if
- we're mapping the whole containing derived-type variable.
- (omp_accumulate_sibling_list): Adjust GOMP_MAP_TO_PSET handling.
- Remove GOMP_MAP_ALWAYS_POINTER handling.
- (gimplify_scan_omp_clauses): Pass enter_exit argument to
- omp_tsort_mapping_groups. Don't adjust/remove GOMP_MAP_TO_PSET
- mappings for derived-type components here.
- * tree.h (OMP_CLAUSE_RELEASE_DESCRIPTOR): New macro.
- * tree-pretty-print.cc (dump_omp_clause): Show
- OMP_CLAUSE_RELEASE_DESCRIPTOR in dump output (with
- GOMP_MAP_TO_PSET-like syntax).
-
-2023-12-13 Julian Brown <julian@codesourcery.com>
-
- * gimplify.cc (build_struct_comp_nodes): Don't process
- GOMP_MAP_ATTACH_DETACH "middle" nodes here.
- (omp_mapping_group): Add REPROCESS_STRUCT and FRAGILE booleans for
- nested struct handling.
- (omp_strip_components_and_deref, omp_strip_indirections): Remove
- functions.
- (omp_get_attachment): Handle GOMP_MAP_DETACH here.
- (omp_group_last): Handle GOMP_MAP_*, GOMP_MAP_DETACH,
- GOMP_MAP_ATTACH_DETACH groups for "exit data" of reference-to-pointer
- component array sections.
- (omp_gather_mapping_groups_1): Initialise reprocess_struct and fragile
- fields.
- (omp_group_base): Handle GOMP_MAP_ATTACH_DETACH after GOMP_MAP_STRUCT.
- (omp_index_mapping_groups_1): Skip reprocess_struct groups.
- (omp_get_nonfirstprivate_group, omp_directive_maps_explicitly,
- omp_resolve_clause_dependencies, omp_first_chained_access_token): New
- functions.
- (omp_check_mapping_compatibility): Adjust accepted node combinations
- for "from" clauses using release instead of alloc.
- (omp_accumulate_sibling_list): Add GROUP_MAP, ADDR_TOKENS, FRAGILE_P,
- REPROCESSING_STRUCT, ADDED_TAIL parameters. Use OMP address tokenizer
- to analyze addresses. Reimplement nested struct handling, and
- implement "fragile groups".
- (omp_build_struct_sibling_lists): Adjust for changes to
- omp_accumulate_sibling_list. Recalculate bias for ATTACH_DETACH nodes
- after GOMP_MAP_STRUCT nodes.
- (gimplify_scan_omp_clauses): Call omp_resolve_clause_dependencies. Use
- OMP address tokenizer.
- (gimplify_adjust_omp_clauses_1): Use build_fold_indirect_ref_loc
- instead of build_simple_mem_ref_loc.
- * omp-general.cc (omp-general.h, tree-pretty-print.h): Include.
- (omp_addr_tokenizer): New namespace.
- (omp_addr_tokenizer::omp_addr_token): New.
- (omp_addr_tokenizer::omp_parse_component_selector,
- omp_addr_tokenizer::omp_parse_ref,
- omp_addr_tokenizer::omp_parse_pointer,
- omp_addr_tokenizer::omp_parse_access_method,
- omp_addr_tokenizer::omp_parse_access_methods,
- omp_addr_tokenizer::omp_parse_structure_base,
- omp_addr_tokenizer::omp_parse_structured_expr,
- omp_addr_tokenizer::omp_parse_array_expr,
- omp_addr_tokenizer::omp_access_chain_p,
- omp_addr_tokenizer::omp_accessed_addr): New functions.
- (omp_parse_expr, debug_omp_tokenized_addr): New functions.
- * omp-general.h (omp_addr_tokenizer::access_method_kinds,
- omp_addr_tokenizer::structure_base_kinds,
- omp_addr_tokenizer::token_type,
- omp_addr_tokenizer::omp_addr_token,
- omp_addr_tokenizer::omp_access_chain_p,
- omp_addr_tokenizer::omp_accessed_addr): New.
- (omp_addr_token, omp_parse_expr): New.
- * omp-low.cc (scan_sharing_clauses): Skip error check for references
- to pointers.
- * tree.h (OMP_CLAUSE_ATTACHMENT_MAPPING_ERASED): New macro.
-
-2023-12-13 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-hsa.h (NO_XNACK): Change the defaults.
- * config/gcn/gcn-opts.h (enum hsaco_attr_type): Add HSACO_ATTR_DEFAULT.
- * config/gcn/gcn.cc (gcn_option_override): Set the default flag_xnack.
- * config/gcn/gcn.opt: Add -mxnack=default.
- * doc/invoke.texi: Document the -mxnack default.
-
-2023-12-13 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-hsa.h (NO_XNACK): Ignore missing -march.
- (XNACKOPT): Match on/off; ignore any.
- * config/gcn/gcn-valu.md (gather<mode>_insn_1offset<exec>):
- Add xnack compatible alternatives.
- (gather<mode>_insn_2offsets<exec>): Likewise.
- * config/gcn/gcn.cc (gcn_option_override): Permit -mxnack for devices
- other than Fiji and gfx1030.
- (gcn_expand_epilogue): Remove early-clobber problems.
- (gcn_hsa_declare_function_name): Obey -mxnack setting.
- * config/gcn/gcn.md (xnack): New attribute.
- (enabled): Rework to include "xnack" attribute.
- (*movbi): Add xnack compatible alternatives.
- (*mov<mode>_insn): Likewise.
- (*mov<mode>_insn): Likewise.
- (*mov<mode>_insn): Likewise.
- (*movti_insn): Likewise.
- * config/gcn/gcn.opt (-mxnack): Change the default to "any".
- * doc/invoke.texi: Remove placeholder notice for -mxnack.
-
-2023-12-13 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * config/aarch64/x-aarch64: Add missing dependencies.
-
-2023-12-13 Roger Sayle <roger@nextmovesoftware.com>
- Jeff Law <jlaw@ventanamicro.com>
-
- * config/arc/arc.md (*extvsi_n_0): New define_insn_and_split to
- implement SImode sign extract using a AND, XOR and MINUS sequence.
-
-2023-12-13 Feng Wang <wangfeng@eswincomputing.com>
-
- * common/config/riscv/riscv-common.cc: Modify implied ISA info.
- * config/riscv/arch-canonicalize: Add crypto vector implied info.
-
-2023-12-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112929
- PR target/112988
- * config/riscv/riscv-vsetvl.cc
- (pre_vsetvl::compute_lcm_local_properties): Remove full available.
- (pre_vsetvl::pre_global_vsetvl_info): Add full available optimization.
-
-2023-12-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111317
- * tree-vect-loop.cc (vect_estimate_min_profitable_iters): Adjust for COST for decrement IV.
-
-2023-12-13 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112940
- * gimple-lower-bitint.cc (struct bitint_large_huge): Add another
- argument to prepare_data_in_out method defaulted to NULL_TREE.
- (bitint_large_huge::handle_operand): Pass another argument to
- prepare_data_in_out instead of emitting an assignment to set it.
- (bitint_large_huge::prepare_data_in_out): Add VAL_OUT argument.
- If non-NULL, use it as PHI argument instead of creating a new
- SSA_NAME.
- (bitint_large_huge::handle_cast): Pass rext as another argument
- to 2 prepare_data_in_out calls instead of emitting assignments
- to set them.
-
-2023-12-13 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112953
- * attribs.cc (free_attr_data): Use delete x rather than delete[] x.
-
-2023-12-13 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112962
- * config/i386/i386.cc (ix86_gimple_fold_builtin): For shifts
- and abs without lhs replace with nop.
-
-2023-12-13 Richard Biener <rguenther@suse.de>
-
- * emit-rtl.cc (set_mem_attributes_minus_bitpos): Preserve
- the offset when rewriting an exising MEM_REF base for
- stack slot sharing.
-
-2023-12-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112991
- PR tree-optimization/112961
- * tree-ssa-sccvn.h (do_rpo_vn): Add skip_entry_phis argument.
- * tree-ssa-sccvn.cc (do_rpo_vn): Likewise.
- (do_rpo_vn_1): Likewise, merge with auto-processing.
- (run_rpo_vn): Adjust.
- (pass_fre::execute): Likewise.
- * tree-if-conv.cc (tree_if_conversion): Revert last change.
- Value-number latch block but disable value-numbering of
- entry PHIs.
- * tree-ssa-uninit.cc (execute_early_warn_uninitialized): Adjust.
-
-2023-12-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112990
- * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..):
- Restrict to vector modes after lowering.
-
-2023-12-13 Richard Biener <rguenther@suse.de>
-
- PR middle-end/111591
- * cfgexpand.cc (update_alias_info_with_stack_vars): Document
- why not adjusting TBAA info on accesses is OK.
-
-2023-12-13 Alexandre Oliva <oliva@adacore.com>
-
- * doc/invoke.texi (multiflags): Drop extraneous period, use
- @pxref instead.
-
-2023-12-13 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-builtins.cc:
- (AARCH64_PLD): New enum aarch64_builtins entry.
- (AARCH64_PLDX): Likewise.
- (AARCH64_PLI): Likewise.
- (AARCH64_PLIX): Likewise.
- (aarch64_init_prefetch_builtin): New.
- (aarch64_general_init_builtins): Call prefetch init function.
- (aarch64_expand_prefetch_builtin): New.
- (aarch64_general_expand_builtin): Add prefetch expansion.
- (require_const_argument): New.
- * config/aarch64/aarch64.md (UNSPEC_PLDX): New.
- (aarch64_pldx): Likewise.
- * config/aarch64/arm_acle.h (__pld): Likewise.
- (__pli): Likewise.
- (__plix): Likewise.
- (__pldx): Likewise.
-
-2023-12-13 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/112788
- * value-range.h (range_compatible_p): Workaround same type mode but
- different type precision issue for rs6000 scalar float types
- _Float128 and long double.
-
-2023-12-13 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add code to use
- pli for 34bit constant.
-
-2023-12-13 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add new
- parameter to record number of instructions to build the constant.
- (num_insns_constant_gpr): Call rs6000_emit_set_long_const to compute
- num_insn.
-
-2023-12-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo): New function.
- (costs::record_potential_vls_unrolling): Ditto.
- (costs::prefer_unrolled_loop): Ditto.
- (costs::better_main_loop_than_p): Ditto.
- (costs::add_stmt_cost): Ditto.
- * config/riscv/riscv-vector-costs.h (enum cost_type_enum): New enum.
- * config/riscv/t-riscv: Add new include files.
-
-2023-12-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (get_current_lmul): Remove it.
- (compute_estimated_lmul): New function.
- (costs::costs): Refactor.
- (costs::preferred_new_lmul_p): Ditto.
- (preferred_new_lmul_p): Ditto.
- (costs::better_main_loop_than_p): Ditto.
- * config/riscv/riscv-vector-costs.h (struct autovec_info): Remove it.
-
-2023-12-12 Martin Jambor <mjambor@suse.cz>
-
- PR tree-optimization/112822
- * tree-sra.cc (load_assign_lhs_subreplacements): Invoke
- force_gimple_operand_gsi also when LHS has partial stores and RHS is a
- VIEW_CONVERT_EXPR.
-
-2023-12-12 Jason Merrill <jason@redhat.com>
- Nathaniel Shead <nathanieloshead@gmail.com>
-
- * tree-core.h (enum clobber_kind): Rename CLOBBER_EOL to
- CLOBBER_STORAGE_END. Add CLOBBER_STORAGE_BEGIN,
- CLOBBER_OBJECT_BEGIN, CLOBBER_OBJECT_END.
- * gimple-lower-bitint.cc
- * gimple-ssa-warn-access.cc
- * gimplify.cc
- * tree-inline.cc
- * tree-ssa-ccp.cc: Adjust for rename.
- * tree-pretty-print.cc: And handle new values.
-
-2023-12-12 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_override_options): Update.
- (aarch64_handle_attr_branch_protection): Update.
- * config/arm/aarch-common-protos.h (aarch_parse_branch_protection):
- Remove.
- (aarch_validate_mbranch_protection): Add new argument.
- * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
- Update.
- (aarch_handle_standard_branch_protection): Update.
- (aarch_handle_pac_ret_protection): Update.
- (aarch_handle_pac_ret_leaf): Update.
- (aarch_handle_pac_ret_b_key): Update.
- (aarch_handle_bti_protection): Update.
- (aarch_parse_branch_protection): Remove.
- (next_tok): New.
- (aarch_validate_mbranch_protection): Rewrite.
- * config/arm/aarch-common.h (struct aarch_branch_protect_type):
- Add field "alone".
- * config/arm/arm.cc (arm_configure_build_target): Update.
-
-2023-12-12 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_override_options_after_change_1):
- Do not override branch_protection options.
- (aarch64_override_options): Remove accepted_branch_protection_string.
- * config/arm/aarch-common.cc (BRANCH_PROTECT_STR_MAX): Remove.
- (aarch_parse_branch_protection): Remove
- accepted_branch_protection_string.
- * config/arm/arm.cc: Likewise.
-
-2023-12-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112736
- * tree-vect-stmts.cc (vectorizable_load): Extend optimization
- to avoid peeling for gaps to handle single-element non-groups
- we now allow with SLP.
-
-2023-12-12 Richard Biener <rguenther@suse.de>
-
- PR ipa/92606
- * ipa-icf.cc (sem_item_optimizer::merge_classes): Check
- both source and alias for the no_icf attribute.
- * doc/extend.texi (no_icf): Document variable attribute.
-
-2023-12-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112961
- * tree-if-conv.cc (tree_if_conversion): Instead of excluding
- the latch block from VN, add a fake entry edge.
-
-2023-12-12 Xi Ruoyao <xry111@xry111.site>
-
- PR middle-end/107723
- * convert.cc (convert_to_integer_1) [case BUILT_IN_TRUNC]: Break
- early if !flag_fp_int_builtin_inexact and flag_trapping_math.
-
-2023-12-12 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p):
- Disable the avl propogation for the vcompress.
-
-2023-12-12 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-opts.h (la_target): Move into #if
- for loongarch-def.h.
- (loongarch_init_target): Likewise.
- (loongarch_config_target): Likewise.
- (loongarch_update_gcc_opt_status): Likewise.
-
-2023-12-12 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
- Return true for SYMBOL_PCREL64. Return true for SYMBOL_GOT_DISP
- if TARGET_CMODEL_EXTREME.
- (loongarch_split_symbol): Check for la_opt_explicit_relocs !=
- EXPLICIT_RELOCS_NONE instead of TARGET_EXPLICIT_RELOCS.
- (loongarch_print_operand_reloc): Likewise.
- (loongarch_option_override_internal): Likewise.
- (loongarch_handle_model_attribute): Likewise.
- * doc/invoke.texi (-mcmodel=extreme): Update the compatibility
- between it and -mexplicit-relocs=.
-
-2023-12-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112939
- * tree-ssa-sccvn.cc (visit_phi): When all args are undefined
- make sure we end up with a value that was visited, otherwise
- fall back to .VN_TOP.
-
-2023-12-12 liuhongt <hongtao.liu@intel.com>
-
- PR target/112891
- * config/i386/i386.cc (ix86_avx_u128_mode_after): Return
- AVX_U128_ANY if callee_abi doesn't clobber all_sse_regs to
- align with ix86_avx_u128_mode_needed.
- (ix86_avx_u128_mode_needed): Return AVX_U128_ClEAN for
- sibling_call.
-
-2023-12-12 Alexandre Oliva <oliva@adacore.com>
-
- PR target/112334
- * builtins.h (target_builtins): Add fields for apply_args_size
- and apply_result_size.
- * builtins.cc (apply_args_size, apply_result_size): Cache
- results in fields rather than in static variables.
- (get_apply_args_size, set_apply_args_size): New.
- (get_apply_result_size, set_apply_result_size): New.
-
-2023-12-12 Hongyu Wang <hongyu.wang@intel.com>
-
- PR target/112943
- * config/i386/i386.md (ashl<mode>3): Add TARGET_APX_NDD to
- ix86_expand_binary_operator call.
- (<insn><mode>3): Likewise for rshift.
- (<insn>di3): Likewise for DImode rotate.
- (<insn><mode>3): Likewise for SWI124 rotate.
-
-2023-12-12 Feng Wang <wangfeng@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
- Add AVAIL argument.
- (read_vl): Using AVAIL argument default value.
- (vlenb): Ditto.
- (vsetvl): Ditto.
- (vsetvlmax): Ditto.
- (vle): Ditto.
- (vse): Ditto.
- (vlm): Ditto.
- (vsm): Ditto.
- (vlse): Ditto.
- (vsse): Ditto.
- (vluxei8): Ditto.
- (vluxei16): Ditto.
- (vluxei32): Ditto.
- (vluxei64): Ditto.
- (vloxei8): Ditto.
- (vloxei16): Ditto.
- (vloxei32): Ditto.
- (vloxei64): Ditto.
- (vsuxei8): Ditto.
- (vsuxei16): Ditto.
- (vsuxei32): Ditto.
- (vsuxei64): Ditto.
- (vsoxei8): Ditto.
- (vsoxei16): Ditto.
- (vsoxei32): Ditto.
- (vsoxei64): Ditto.
- (vleff): Ditto.
- (vadd): Ditto.
- (vsub): Ditto.
- (vrsub): Ditto.
- (vneg): Ditto.
- (vwaddu): Ditto.
- (vwsubu): Ditto.
- (vwadd): Ditto.
- (vwsub): Ditto.
- (vwcvt_x): Ditto.
- (vwcvtu_x): Ditto.
- (vzext): Ditto.
- (vsext): Ditto.
- (vadc): Ditto.
- (vmadc): Ditto.
- (vsbc): Ditto.
- (vmsbc): Ditto.
- (vand): Ditto.
- (vor): Ditto.
- (vxor): Ditto.
- (vnot): Ditto.
- (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- (vnsrl): Ditto.
- (vnsra): Ditto.
- (vncvt_x): Ditto.
- (vmseq): Ditto.
- (vmsne): Ditto.
- (vmsltu): Ditto.
- (vmslt): Ditto.
- (vmsleu): Ditto.
- (vmsle): Ditto.
- (vmsgtu): Ditto.
- (vmsgt): Ditto.
- (vmsgeu): Ditto.
- (vmsge): Ditto.
- (vminu): Ditto.
- (vmin): Ditto.
- (vmaxu): Ditto.
- (vmax): Ditto.
- (vmul): Ditto.
- (vmulh): Ditto.
- (vmulhu): Ditto.
- (vmulhsu): Ditto.
- (vdivu): Ditto.
- (vdiv): Ditto.
- (vremu): Ditto.
- (vrem): Ditto.
- (vwmul): Ditto.
- (vwmulu): Ditto.
- (vwmulsu): Ditto.
- (vmacc): Ditto.
- (vnmsac): Ditto.
- (vmadd): Ditto.
- (vnmsub): Ditto.
- (vwmaccu): Ditto.
- (vwmacc): Ditto.
- (vwmaccsu): Ditto.
- (vwmaccus): Ditto.
- (vmerge): Ditto.
- (vmv_v): Ditto.
- (vsaddu): Ditto.
- (vsadd): Ditto.
- (vssubu): Ditto.
- (vssub): Ditto.
- (vaaddu): Ditto.
- (vaadd): Ditto.
- (vasubu): Ditto.
- (vasub): Ditto.
- (vsmul): Ditto.
- (vssrl): Ditto.
- (vssra): Ditto.
- (vnclipu): Ditto.
- (vnclip): Ditto.
- (vfadd): Ditto.
- (vfsub): Ditto.
- (vfrsub): Ditto.
- (vfadd_frm): Ditto.
- (vfsub_frm): Ditto.
- (vfrsub_frm): Ditto.
- (vfwadd): Ditto.
- (vfwsub): Ditto.
- (vfwadd_frm): Ditto.
- (vfwsub_frm): Ditto.
- (vfmul): Ditto.
- (vfdiv): Ditto.
- (vfrdiv): Ditto.
- (vfmul_frm): Ditto.
- (vfdiv_frm): Ditto.
- (vfrdiv_frm): Ditto.
- (vfwmul): Ditto.
- (vfwmul_frm): Ditto.
- (vfmacc): Ditto.
- (vfnmsac): Ditto.
- (vfmadd): Ditto.
- (vfnmsub): Ditto.
- (vfnmacc): Ditto.
- (vfmsac): Ditto.
- (vfnmadd): Ditto.
- (vfmsub): Ditto.
- (vfmacc_frm): Ditto.
- (vfnmacc_frm): Ditto.
- (vfmsac_frm): Ditto.
- (vfnmsac_frm): Ditto.
- (vfmadd_frm): Ditto.
- (vfnmadd_frm): Ditto.
- (vfmsub_frm): Ditto.
- (vfnmsub_frm): Ditto.
- (vfwmacc): Ditto.
- (vfwnmacc): Ditto.
- (vfwmsac): Ditto.
- (vfwnmsac): Ditto.
- (vfwmacc_frm): Ditto.
- (vfwnmacc_frm): Ditto.
- (vfwmsac_frm): Ditto.
- (vfwnmsac_frm): Ditto.
- (vfsqrt): Ditto.
- (vfsqrt_frm): Ditto.
- (vfrsqrt7): Ditto.
- (vfrec7): Ditto.
- (vfrec7_frm): Ditto.
- (vfmin): Ditto.
- (vfmax): Ditto.
- (vfsgnj): Ditto.
- (vfsgnjn): Ditto.
- (vfsgnjx): Ditto.
- (vfneg): Ditto.
- (vfabs): Ditto.
- (vmfeq): Ditto.
- (vmfne): Ditto.
- (vmflt): Ditto.
- (vmfle): Ditto.
- (vmfgt): Ditto.
- (vmfge): Ditto.
- (vfclass): Ditto.
- (vfmerge): Ditto.
- (vfmv_v): Ditto.
- (vfcvt_x): Ditto.
- (vfcvt_xu): Ditto.
- (vfcvt_rtz_x): Ditto.
- (vfcvt_rtz_xu): Ditto.
- (vfcvt_f): Ditto.
- (vfcvt_x_frm): Ditto.
- (vfcvt_xu_frm): Ditto.
- (vfcvt_f_frm): Ditto.
- (vfwcvt_x): Ditto.
- (vfwcvt_xu): Ditto.
- (vfwcvt_rtz_x): Ditto.
- (vfwcvt_rtz_xu) Ditto.:
- (vfwcvt_f): Ditto.
- (vfwcvt_x_frm): Ditto.
- (vfwcvt_xu_frm) Ditto.:
- (vfncvt_x): Ditto.
- (vfncvt_xu): Ditto.
- (vfncvt_rtz_x): Ditto.
- (vfncvt_rtz_xu): Ditto.
- (vfncvt_f): Ditto.
- (vfncvt_rod_f): Ditto.
- (vfncvt_x_frm): Ditto.
- (vfncvt_xu_frm): Ditto.
- (vfncvt_f_frm): Ditto.
- (vredsum): Ditto.
- (vredmaxu): Ditto.
- (vredmax): Ditto.
- (vredminu): Ditto.
- (vredmin): Ditto.
- (vredand): Ditto.
- (vredor): Ditto.
- (vredxor): Ditto.
- (vwredsum): Ditto.
- (vwredsumu): Ditto.
- (vfredusum): Ditto.
- (vfredosum): Ditto.
- (vfredmax): Ditto.
- (vfredmin): Ditto.
- (vfredusum_frm): Ditto.
- (vfredosum_frm): Ditto.
- (vfwredosum): Ditto.
- (vfwredusum): Ditto.
- (vfwredosum_frm): Ditto.
- (vfwredusum_frm): Ditto.
- (vmand): Ditto.
- (vmnand): Ditto.
- (vmandn): Ditto.
- (vmxor): Ditto.
- (vmor): Ditto.
- (vmnor): Ditto.
- (vmorn): Ditto.
- (vmxnor): Ditto.
- (vmmv): Ditto.
- (vmclr): Ditto.
- (vmset): Ditto.
- (vmnot): Ditto.
- (vcpop): Ditto.
- (vfirst): Ditto.
- (vmsbf): Ditto.
- (vmsif): Ditto.
- (vmsof): Ditto.
- (viota): Ditto.
- (vid): Ditto.
- (vmv_x): Ditto.
- (vmv_s): Ditto.
- (vfmv_f): Ditto.
- (vfmv_s): Ditto.
- (vslideup): Ditto.
- (vslidedown): Ditto.
- (vslide1up): Ditto.
- (vslide1down): Ditto.
- (vfslide1up): Ditto.
- (vfslide1down): Ditto.
- (vrgather): Ditto.
- (vrgatherei16): Ditto.
- (vcompress): Ditto.
- (vundefined): Ditto.
- (vreinterpret): Ditto.
- (vlmul_ext): Ditto.
- (vlmul_trunc): Ditto.
- (vset): Ditto.
- (vget): Ditto.
- (vcreate): Ditto.
- (vlseg): Ditto.
- (vsseg): Ditto.
- (vlsseg): Ditto.
- (vssseg): Ditto.
- (vluxseg): Ditto.
- (vloxseg): Ditto.
- (vsuxseg): Ditto.
- (vsoxseg): Ditto.
- (vlsegff): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): Using variadic macro.
- * config/riscv/riscv-vector-builtins.h (struct function_group_info):
- Add avail function interface into struct.
- * config/riscv/t-riscv: Add dependency
- * config/riscv/riscv-vector-builtins-avail.h: New file.The definition of AVAIL marco.
-
-2023-12-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (estimated_poly_value): New function.
- * config/riscv/riscv-v.cc (estimated_poly_value): Ditto.
- * config/riscv/riscv.cc (riscv_estimated_poly_value): Move RVV POLY
- VALUE estimation to riscv-v.cc
-
-2023-12-12 Yang Yujie <yangyujie@loongson.cn>
-
- * config/loongarch/loongarch.cc: Do not restore the saved eh_return
- data registers ($r4-$r7) for a normal return of a function that calls
- __builtin_eh_return elsewhere.
- * config/loongarch/loongarch-protos.h: Same.
- * config/loongarch/loongarch.md: Same.
-
-2023-12-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * recog.cc (constrain_operands): Pass VOIDmode to
- strict_memory_address_p for 'p' constraints in asms.
- * rtl-ssa/changes.cc (recog_level2): Skip redundant constrain_operands
- for asms.
-
-2023-12-11 Jason Merrill <jason@redhat.com>
-
- * common.opt: Add comment.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- PR middle-end/112784
- * expr.cc (emit_block_move_via_loop): Call int_mode_for_size
- for maybe-too-wide sizes.
- (emit_block_cmp_via_loop): Likewise.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- PR target/112778
- * builtins.cc (can_store_by_multiple_pieces): New.
- (try_store_by_multiple_pieces): Call it.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- PR target/112804
- * builtins.cc (try_store_by_multiple_pieces): Use ptr's mode
- for the increment.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- * doc/invoke.texi (multiflags): Add period after @xref to
- silence warning.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- * config/rl78/rl78.cc (TARGET_HAVE_STRUB_SUPPORT_FOR): Disable.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- * ipa-strub.cc (pass_ipa_strub::execute): Check that we don't
- add indirection to pointer parameters, and document attribute
- access non-interactions.
-
-2023-12-11 Roger Sayle <roger@nextmovesoftware.com>
-
- PR rtl-optimization/112380
- * combine.cc (expand_field_assignment): Check if gen_lowpart
- returned a CLOBBER, and avoid calling gen_simplify_binary with
- it if so.
-
-2023-12-11 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR target/111867
- * config/aarch64/aarch64.cc (aarch64_float_const_representable_p): For BFmode,
- only accept +0.0.
-
-2023-12-11 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR tree-optimization/111972
- PR tree-optimization/110637
- * match.pd (`(convert)(zeroone !=/== CST)`): Match
- and simplify to ((convert)zeroone){,^1}.
- * fold-const.cc (fold_binary_loc): Remove
- transformation of `(~a) & 1` and `(a ^ 1) & 1`
- into `(convert)(a == 0)`.
-
-2023-12-11 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR middle-end/112935
- * expr.cc (expand_expr_real_2): Use
- gimple_zero_one_valued_p instead of tree_nonzero_bits
- to find boolean defined expressions.
-
-2023-12-11 Mikael Pettersson <mikpelinux@gmail.com>
-
- PR target/112413
- * config/m68k/linux.h (ASM_RETURN_CASE_JUMP): For
- TARGET_LONG_JUMP_TABLE_OFFSETS, reference the jump table
- via its label.
- * config/m68k/m68kelf.h (ASM_RETURN_CASE_JUMP): Likewise.
- * config/m68k/netbsd-elf.h (ASM_RETURN_CASE_JUMP): Likewise.
-
-2023-12-11 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * config/aarch64/aarch64.cc (lane_size): New function.
- (aarch64_simd_clone_compute_vecsize_and_simdlen): Determine simdlen according to NDS rule
- and reject combination of simdlen and types that lead to vectors larger than 128bits.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * rtl-ssa/insns.cc (function_info::record_use): Add !ordered_p case.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (get_gather_index_mode): New function.
- (shuffle_series_patterns): Robostify shuffle index.
- (shuffle_generic_patterns): Ditto.
-
-2023-12-11 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/arm_neon.h (vldap1_lane_u64): Add
- `const' to `__builtin_aarch64_simd_di *' cast.
- (vldap1q_lane_u64): Likewise.
- (vldap1_lane_s64): Cast __src to `const __builtin_aarch64_simd_di *'.
- (vldap1q_lane_s64): Likewise.
- (vldap1_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'.
- (vldap1q_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'.
- (vldap1_lane_p64): Add `const' to `__builtin_aarch64_simd_di *' cast.
- (vldap1q_lane_p64): Add `const' to `__builtin_aarch64_simd_di *' cast.
- (vstl1_lane_u64): remove stray `const'.
- (vstl1_lane_s64): Cast __src to `__builtin_aarch64_simd_di *'.
- (vstl1q_lane_s64): Likewise.
- (vstl1_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'.
- (vstl1q_lane_f64): Likewise.
-
-2023-12-11 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112853
- * config/riscv/riscv-v.cc (expand_const_vector): Fix step
- calculation.
- (modulo_sel_indices): Also perform modulo for variable-length
- constants.
- (shuffle_series): Recognize series permutations.
- (expand_vec_perm_const_1): Add shuffle_series.
-
-2023-12-11 liuhongt <hongtao.liu@intel.com>
-
- * match.pd (VCE (a cmp b ? -1 : 0) < 0) ? c : d ---> (VCE ((a
- cmp b) ? (VCE:c) : (VCE:d))): New gimple simplication.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Support highest overlap for wv instructions.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (extract_single_source): Fix ICE.
-
-2023-12-11 Jakub Jelinek <jakub@redhat.com>
-
- * doc/extend.texi (__sync_fetch_and_add, __sync_fetch_and_sub,
- __sync_fetch_and_or, __sync_fetch_and_and, __sync_fetch_and_xor,
- __sync_fetch_and_nand, __sync_add_and_fetch, __sync_sub_and_fetch,
- __sync_or_and_fetch, __sync_and_and_fetch, __sync_xor_and_fetch,
- __sync_nand_and_fetch, __sync_bool_compare_and_swap,
- __sync_val_compare_and_swap, __sync_lock_test_and_set,
- __sync_lock_release, __atomic_load_n, __atomic_load, __atomic_store_n,
- __atomic_store, __atomic_exchange_n, __atomic_exchange,
- __atomic_compare_exchange_n, __atomic_compare_exchange,
- __atomic_add_fetch, __atomic_sub_fetch, __atomic_and_fetch,
- __atomic_xor_fetch, __atomic_or_fetch, __atomic_nand_fetch,
- __atomic_fetch_add, __atomic_fetch_sub, __atomic_fetch_and,
- __atomic_fetch_xor, __atomic_fetch_or, __atomic_fetch_nand,
- __atomic_test_and_set, __atomic_clear, __atomic_thread_fence,
- __atomic_signal_fence, __atomic_always_lock_free,
- __atomic_is_lock_free, __builtin_add_overflow,
- __builtin_sadd_overflow, __builtin_saddl_overflow,
- __builtin_saddll_overflow, __builtin_uadd_overflow,
- __builtin_uaddl_overflow, __builtin_uaddll_overflow,
- __builtin_sub_overflow, __builtin_ssub_overflow,
- __builtin_ssubl_overflow, __builtin_ssubll_overflow,
- __builtin_usub_overflow, __builtin_usubl_overflow,
- __builtin_usubll_overflow, __builtin_mul_overflow,
- __builtin_smul_overflow, __builtin_smull_overflow,
- __builtin_smulll_overflow, __builtin_umul_overflow,
- __builtin_umull_overflow, __builtin_umulll_overflow,
- __builtin_add_overflow_p, __builtin_sub_overflow_p,
- __builtin_mul_overflow_p, __builtin_addc, __builtin_addcl,
- __builtin_addcll, __builtin_subc, __builtin_subcl, __builtin_subcll,
- __builtin_alloca, __builtin_alloca_with_align,
- __builtin_alloca_with_align_and_max, __builtin_speculation_safe_value,
- __builtin_nan, __builtin_nand32, __builtin_nand64, __builtin_nand128,
- __builtin_nanf, __builtin_nanl, __builtin_nanf@var{n},
- __builtin_nanf@var{n}x, __builtin_nans, __builtin_nansd32,
- __builtin_nansd64, __builtin_nansd128, __builtin_nansf,
- __builtin_nansl, __builtin_nansf@var{n}, __builtin_nansf@var{n}x,
- __builtin_ffs, __builtin_clz, __builtin_ctz, __builtin_clrsb,
- __builtin_popcount, __builtin_parity, __builtin_bswap16,
- __builtin_bswap32, __builtin_bswap64, __builtin_bswap128,
- __builtin_extend_pointer, __builtin_goacc_parlevel_id,
- __builtin_goacc_parlevel_size, vec_clrl, vec_clrr, vec_mulh, vec_mul,
- vec_div, vec_dive, vec_mod, __builtin_rx_mvtc): Use @var{...} around
- parameter names.
- (vec_rl, vec_sl, vec_sr, vec_sra): Likewise. Use @var{...} also
- around A, B and R in description.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-selftests.cc (riscv_run_selftests):
- Remove poly self test when FIXED-VLMAX.
-
-2023-12-11 Fei Gao <gaofei@eswincomputing.com>
- Xiao Zeng <zengxiao@eswincomputing.com>
-
- * ifcvt.cc (noce_cond_zero_binary_op_supported): Add support for AND.
- (noce_bbs_ok_for_cond_zero_arith): Likewise.
- (noce_try_cond_zero_arith): Likewise.
-
-2023-12-11 liuhongt <hongtao.liu@intel.com>
-
- PR target/112904
- * config/i386/mmx.md (*xop_pcmov_<mode>): New define_insn.
-
-2023-12-11 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/112707
- * config/rs6000/rs6000.h (TARGET_FCTID): Define.
- * config/rs6000/rs6000.md (lrint<mode>di2): Add guard TARGET_FCTID.
- * (lround<mode>di2): Replace TARGET_FPRND with TARGET_FCTID.
-
-2023-12-11 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/112707
- * config/rs6000/rs6000.md (expand lrint<mode>si2): New.
- (insn lrint<mode>si2): Rename to...
- (*lrint<mode>si): ...this.
- (lrint<mode>si_di): New.
-
-2023-12-10 Fei Gao <gaofei@eswincomputing.com>
- Xiao Zeng <zengxiao@eswincomputing.com>
-
- * ifcvt.cc (noce_cond_zero_binary_op_supported): Add support for shift
- like op.
-
-2023-12-10 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/112931
- PR target/112933
- * config/aarch64/aarch64-protos.h (aarch64_sve_reinterpret): Declare.
- * config/aarch64/aarch64.cc (aarch64_sve_reinterpret): New function.
- * config/aarch64/aarch64-sve-builtins-sme.cc (svread_za_impl::expand)
- (svwrite_za_impl::expand): Use it to cast the SVE register to the
- right mode.
-
-2023-12-10 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/112930
- * config/aarch64/aarch64.cc (aarch64_sme_mode_switch_regs::add_reg):
- Force specific SVE modes for single registers as well as structures.
-
-2023-12-10 Jason Merrill <jason@redhat.com>
-
- * doc/invoke.texi (-fpermissive): Mention ObjC++ for -Wnarrowing.
-
-2023-12-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/addsub.md (uaddv<mode>4, usubv<mode>4): New expanders.
- (uaddv): New define_insn_and_split plus post-reload pattern.
-
-2023-12-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/h8300-protos.h (use_extvsi): Prototype.
- * config/h8300/combiner.md: Two new define_insn_and_split patterns
- to implement signed bitfield extractions.
- * config/h8300/h8300.cc (use_extvsi): New function.
-
-2023-12-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/combiner.md (single bit signed bitfield extraction): Fix
- length computation when the bit we want is in the low half word.
-
-2023-12-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/h8300.cc (compute_a_shift_length): Fix computation
- of logical shifts on the H8/SX.
-
-2023-12-09 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112887
- * tree-ssa-phiopt.cc (hoist_adjacent_loads): Change type of
- param_align, param_align_bits, offset1, offset2, size2 and align1
- variables from int or unsigned int to unsigned HOST_WIDE_INT.
-
-2023-12-09 Costas Argyris <costas.argyris@gmail.com>
- Jakub Jelinek <jakub@redhat.com>
-
- PR driver/93019
- * gcc.cc (driver::finalize): Call XDELETEVEC on mdswitches before
- clearing it.
-
-2023-12-09 Jakub Jelinek <jakub@redhat.com>
-
- * attribs.h (any_nonignored_attribute_p): Declare.
- * attribs.cc (any_nonignored_attribute_p): New function.
-
-2023-12-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112932
- * config/riscv/vector.md (movmisalign<mode>): Fix VLSmode bugs.
-
-2023-12-09 Alexandre Oliva <oliva@adacore.com>
-
- * tree-emutls.cc: Include diagnostic-core.h.
- (pass_ipa_lower_emutls::gate): Skip if errors were seen.
-
-2023-12-08 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/112875
- * lra-eliminations.cc (lra_eliminate_regs_1): Change an assert.
- Add ASM_OPERANDS case.
-
-2023-12-08 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112109
- * config/riscv/riscv-protos.h (expand_strcmp): Declare.
- * config/riscv/riscv-string.cc (riscv_expand_strcmp): Add
- strategy handling and delegation to scalar and vector expanders.
- (expand_strcmp): Vectorized implementation.
- * config/riscv/riscv.md: Add TARGET_VECTOR to strcmp and strncmp
- expander.
-
-2023-12-08 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112109
- * config/riscv/riscv-protos.h (expand_rawmemchr): Add strlen
- parameter.
- * config/riscv/riscv-string.cc (riscv_expand_strlen): Call
- rawmemchr.
- (expand_rawmemchr): Add strlen handling.
- * config/riscv/riscv.md: Add TARGET_VECTOR to strlen expander.
-
-2023-12-08 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-early-ra.cc (allocno_info::chain_next):
- Put into an enum with...
- (allocno_info::last_def_point): ...new member variable.
- (allocno_info::m_current_bb_point): New member variable.
- (likely_operand_match_p): Switch based on get_constraint_type,
- rather than based on rtx code. Handle relaxed and special memory
- constraints.
- (early_ra::record_copy): Allow the source of an equivalence to be
- assigned to more than once.
- (early_ra::record_allocno_use): Invalidate any previous equivalence.
- Initialize last_def_point.
- (early_ra::record_allocno_def): Set last_def_point.
- (early_ra::valid_equivalence_p): New function, split out from...
- (early_ra::record_copy): ...here. Use last_def_point to handle
- source registers that have a later definition.
- (make_pass_aarch64_early_ra): Fix comment.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
- (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
- (vld1q_f16_x2, vld1q_f32_x2): New.
- (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
- (vld1q_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
- * config/arm/neon.md (vld1_x2<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
- (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
- (vld1q_f16_x3, vld1q_f32_x3): New.
- (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
- (vld1q_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
- * config/arm/neon.md (vld1_x3<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
- (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
- (vld1q_f16_x4, vld1q_f32_x4): New.
- (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
- (vld1q_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
- * config/arm/neon.md (vld1_x4<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
- (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
- (vst1_f16_x2, vst1_f32_x2): New.
- (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
- (vst1_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
- * config/arm/neon.md (vst1_x2<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
- (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
- (vst1_f16_x3, vst1_f32_x3): New.
- (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
- (vst1_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
- * config/arm/neon.md (vst1_x3<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
- (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
- (vst1_f16_x4, vst1_f32_x4): New.
- (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
- (vst1_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
- * config/arm/neon.md (vst1_x4<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
- (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
- (vst1q_f16_x2, vst1q_f32_x2): New.
- (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
- (vst1q_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vst1q_x2): New entries.
- * config/arm/neon.md
- (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
- neon_vst1_x2<mode>.
- * config/arm/iterators.md (VMEMX2): New mode iterator.
- (VMEMX2_q): New mode attribute.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
- (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
- (vst1q_f16_x3, vst1q_f32_x3): New.
- (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
- (vst1q_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
- * config/arm/neon.md (neon_vst1q_x3<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
- (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
- (vst1q_f16_x4, vst1q_f32_x4): New.
- (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
- (vst1q_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
- * config/arm/neon.md (neon_vst1q_x4<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New
- (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
- (vld1_f16_x2, vld1_f32_x2): New.
- (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
- (vld1_bf16_x2): New.
- (vld1q_types_x2): Updated to use vld1q_x2 from
- arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x2): Updated entries.
- (vld1q_x2): New entries, but comes from the old vld1_x2
- * config/arm/neon.md
- (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated
- from neon_vld1_x2<mode>.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New
- (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
- (vld1_f16_x3, vld1_f32_x3): New.
- (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
- (vld1_bf16_x3): New.
- (vld1q_types_x3): Updated to use vld1q_x3 from
- arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x3): Updated entries.
- (vld1q_x3): New entries, but comes from the old vld1_x2
- * config/arm/neon.md (neon_vld1q_x3<mode>): Updated from
- neon_vld1_x3<mode>.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New
- (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
- (vld1_f16_x4, vld1_f32_x4): New.
- (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
- (vld1_bf16_x4): New.
- (vld1q_types_x4): Updated to use vld1q_x4
- from arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x4): Updated entries.
- (vld1q_x4): New entries, but comes from the old vld1_x2
- * config/arm/neon.md (neon_vld1q_x4<mode>):
- Updated from neon_vld1_x4<mode>.
-
-2023-12-08 Tobias Burnus <tobias@codesourcery.com>
-
- * builtin-types.def (BT_FN_PTR_PTR_SIZE_PTRMODE_PTRMODE): New.
- * omp-builtins.def (BUILT_IN_GOMP_REALLOC): New.
- * builtins.cc (builtin_fnspec): Handle it.
- * gimple-ssa-warn-access.cc (fndecl_alloc_p,
- matching_alloc_calls_p): Likewise.
- * gimple.cc (nonfreeing_call_p): Likewise.
- * predict.cc (expr_expected_value_1): Likewise.
- * tree-ssa-ccp.cc (evaluate_stmt): Likewise.
- * tree.cc (fndecl_dealloc_argno): Likewise.
-
-2023-12-08 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112909
- * tree-ssa-uninit.cc (find_uninit_use): Look through a
- single level of SSA name copies with single use.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_try_expand_lsx_vshuf_const): Use
- simplify_gen_subreg instead of gen_rtx_SUBREG.
- (loongarch_expand_vec_perm_const_2): Ditto.
- (loongarch_expand_vec_cond_expr): Ditto.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_vector_costs::determine_suggested_unroll_factor):
- If m_has_recip is true, uf return 1.
- (loongarch_vector_costs::add_stmt_cost): Detect the use of approximate instruction sequence.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/genopts/loongarch.opt.in (recip_mask): New variable.
- (-mrecip, -mrecip): New options.
- * config/loongarch/lasx.md (div<mode>3): New expander.
- (*div<mode>3): Rename.
- (sqrt<mode>2): New expander.
- (*sqrt<mode>2): Rename.
- (rsqrt<mode>2): New expander.
- * config/loongarch/loongarch-protos.h (loongarch_emit_swrsqrtsf): New prototype.
- (loongarch_emit_swdivsf): Ditto.
- * config/loongarch/loongarch.cc (loongarch_option_override_internal): Set
- recip_mask for -mrecip and -mrecip= options.
- (loongarch_emit_swrsqrtsf): New function.
- (loongarch_emit_swdivsf): Ditto.
- * config/loongarch/loongarch.h (RECIP_MASK_NONE, RECIP_MASK_DIV, RECIP_MASK_SQRT
- RECIP_MASK_RSQRT, RECIP_MASK_VEC_DIV, RECIP_MASK_VEC_SQRT, RECIP_MASK_VEC_RSQRT
- RECIP_MASK_ALL): New bitmasks.
- (TARGET_RECIP_DIV, TARGET_RECIP_SQRT, TARGET_RECIP_RSQRT, TARGET_RECIP_VEC_DIV
- TARGET_RECIP_VEC_SQRT, TARGET_RECIP_VEC_RSQRT): New tests.
- * config/loongarch/loongarch.md (sqrt<mode>2): New expander.
- (*sqrt<mode>2): Rename.
- (rsqrt<mode>2): New expander.
- * config/loongarch/loongarch.opt (recip_mask): New variable.
- (-mrecip, -mrecip): New options.
- * config/loongarch/lsx.md (div<mode>3): New expander.
- (*div<mode>3): Rename.
- (sqrt<mode>2): New expander.
- (*sqrt<mode>2): Rename.
- (rsqrt<mode>2): New expander.
- * config/loongarch/predicates.md (reg_or_vecotr_1_operand): New predicate.
- * doc/invoke.texi (LoongArch Options): Document new options.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md (lasx_xvfrecip_<flasxfmt>): Renamed to ..
- (recip<mode>3): .. this.
- * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vfrecip_d): Redefine
- to new pattern name.
- (CODE_FOR_lsx_vfrecip_s): Ditto.
- (CODE_FOR_lasx_xvfrecip_d): Ditto.
- (CODE_FOR_lasx_xvfrecip_s): Ditto.
- (loongarch_expand_builtin_direct): For the vector recip instructions, construct a
- temporary parameter const1_vector.
- * config/loongarch/lsx.md (lsx_vfrecip_<flsxfmt>): Renamed to ..
- (recip<mode>3): .. this.
- * config/loongarch/predicates.md (const_vector_1_operand): New predicate.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md (lasx_xvfrsqrt_<flasxfmt>): Renamed to ..
- (rsqrt<mode>2): .. this.
- * config/loongarch/loongarch-builtins.cc
- (CODE_FOR_lsx_vfrsqrt_d): Redefine to standard pattern name.
- (CODE_FOR_lsx_vfrsqrt_s): Ditto.
- (CODE_FOR_lasx_xvfrsqrt_d): Ditto.
- (CODE_FOR_lasx_xvfrsqrt_s): Ditto.
- * config/loongarch/loongarch.cc (use_rsqrt_p): New function.
- (loongarch_optab_supported_p): Ditto.
- (TARGET_OPTAB_SUPPORTED_P): New hook.
- * config/loongarch/loongarch.md (*rsqrt<mode>a): Remove.
- (*rsqrt<mode>2): New insn pattern.
- (*rsqrt<mode>b): Remove.
- * config/loongarch/lsx.md (lsx_vfrsqrt_<flsxfmt>): Renamed to ..
- (rsqrt<mode>2): .. this.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/genopts/isa-evolution.in (fecipe): Add.
- * config/loongarch/larchintrin.h (__frecipe_s): New intrinsic.
- (__frecipe_d): Ditto.
- (__frsqrte_s): Ditto.
- (__frsqrte_d): Ditto.
- * config/loongarch/lasx.md (lasx_xvfrecipe_<flasxfmt>): New insn pattern.
- (lasx_xvfrsqrte_<flasxfmt>): Ditto.
- * config/loongarch/lasxintrin.h (__lasx_xvfrecipe_s): New intrinsic.
- (__lasx_xvfrecipe_d): Ditto.
- (__lasx_xvfrsqrte_s): Ditto.
- (__lasx_xvfrsqrte_d): Ditto.
- * config/loongarch/loongarch-builtins.cc (AVAIL_ALL): Add predicates.
- (LSX_EXT_BUILTIN): New macro.
- (LASX_EXT_BUILTIN): Ditto.
- * config/loongarch/loongarch-cpucfg-map.h: Regenerate.
- * config/loongarch/loongarch-c.cc: Add builtin macro "__loongarch_frecipe".
- * config/loongarch/loongarch-def.cc: Regenerate.
- * config/loongarch/loongarch-str.h (OPTSTR_FRECIPE): Regenerate.
- * config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump status for TARGET_FRECIPE.
- * config/loongarch/loongarch.md (loongarch_frecipe_<fmt>): New insn pattern.
- (loongarch_frsqrte_<fmt>): Ditto.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/lsx.md (lsx_vfrecipe_<flsxfmt>): New insn pattern.
- (lsx_vfrsqrte_<flsxfmt>): Ditto.
- * config/loongarch/lsxintrin.h (__lsx_vfrecipe_s): New intrinsic.
- (__lsx_vfrecipe_d): Ditto.
- (__lsx_vfrsqrte_s): Ditto.
- (__lsx_vfrsqrte_d): Ditto.
- * doc/extend.texi: Add documentation for LoongArch new builtins and intrinsics.
-
-2023-12-08 Richard Biener <rguenther@suse.de>
-
- * tree-outof-ssa.cc (rewrite_out_of_ssa): Dump GIMPLE once only,
- after final IL adjustments.
-
-2023-12-08 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector-iterators.md: Replace RVVM2SI to RVVM2SF
- for mode attr V_F2DI_CONVERT_BRIDGE.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md (xorsign<mode>3): New expander.
- * config/loongarch/loongarch.cc (loongarch_can_change_mode_class): Allow
- conversion between LSX vector mode and scalar fp mode.
- * config/loongarch/loongarch.md (@xorsign<mode>3): New expander.
- * config/loongarch/lsx.md (@xorsign<mode>3): Ditto.
-
-2023-12-08 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112902
- * gimple-lower-bitint.cc (gimple_lower_bitint): For a narrowing
- or same precision cast don't set SSA_NAME_VERSION in m_names only
- if use_stmt is mergeable_op or fall through into the check that
- use is a store or rhs1 is not mergeable or other reasons prevent
- merging.
-
-2023-12-08 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112901
- * vr-values.cc
- (simplify_using_ranges::simplify_float_conversion_using_ranges):
- Return false if rhs1 has BITINT_TYPE type with BLKmode TYPE_MODE.
-
-2023-12-08 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112411
- * haifa-sched.cc (extend_h_i_d): Use 3U instead of 3 in
- 3 * get_max_uid () / 2 calculation.
-
-2023-12-08 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/genopts/loongarch-strings: Delete STR_ISA_BASE_LA64V110.
- * config/loongarch/genopts/loongarch.opt.in: Likewise.
- * config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Delete macro.
- (fill_native_cpu_config): Define a new variable hw_isa_evolution record the
- extended instruction set support read from cpucfg.
- * config/loongarch/loongarch-def.cc: Set evolution at initialization.
- * config/loongarch/loongarch-def.h (ISA_BASE_LA64V100): Delete.
- (ISA_BASE_LA64V110): Likewise.
- (N_ISA_BASE_TYPES): Likewise.
- (defined): Likewise.
- * config/loongarch/loongarch-opts.cc: Likewise.
- * config/loongarch/loongarch-opts.h (TARGET_64BIT): Likewise.
- (ISA_BASE_IS_LA64V110): Likewise.
- * config/loongarch/loongarch-str.h (STR_ISA_BASE_LA64V110): Likewise.
- * config/loongarch/loongarch.opt: Regenerate.
-
-2023-12-08 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-def.h: Remove extern "C".
- (loongarch_isa_base_strings): Declare as loongarch_def_array
- instead of plain array.
- (loongarch_isa_ext_strings): Likewise.
- (loongarch_abi_base_strings): Likewise.
- (loongarch_abi_ext_strings): Likewise.
- (loongarch_cmodel_strings): Likewise.
- (loongarch_cpu_strings): Likewise.
- (loongarch_cpu_default_isa): Likewise.
- (loongarch_cpu_issue_rate): Likewise.
- (loongarch_cpu_multipass_dfa_lookahead): Likewise.
- (loongarch_cpu_cache): Likewise.
- (loongarch_cpu_align): Likewise.
- (loongarch_cpu_rtx_cost_data): Likewise.
- (loongarch_isa): Add a constructor and field setter functions.
- * config/loongarch/loongarch-opts.h (loongarch-defs.h): Do not
- include for target libraries.
- * config/loongarch/loongarch-opts.cc: Comment code that doesn't
- run and causes compilation errors.
- * config/loongarch/loongarch-tune.h (LOONGARCH_TUNE_H): Likewise.
- (struct loongarch_rtx_cost_data): Likewise.
- (struct loongarch_cache): Likewise.
- (struct loongarch_align): Likewise.
- * config/loongarch/t-loongarch: Compile loongarch-def.cc with the
- C++ compiler.
- * config/loongarch/loongarch-def-array.h: New file for a
- std:array like data structure with position setter function.
- * config/loongarch/loongarch-def.c: Rename to ...
- * config/loongarch/loongarch-def.cc: ... here.
- (loongarch_cpu_strings): Define as loongarch_def_array instead
- of plain array.
- (loongarch_cpu_default_isa): Likewise.
- (loongarch_cpu_cache): Likewise.
- (loongarch_cpu_align): Likewise.
- (loongarch_cpu_rtx_cost_data): Likewise.
- (loongarch_cpu_issue_rate): Likewise.
- (loongarch_cpu_multipass_dfa_lookahead): Likewise.
- (loongarch_isa_base_strings): Likewise.
- (loongarch_isa_ext_strings): Likewise.
- (loongarch_abi_base_strings): Likewise.
- (loongarch_abi_ext_strings): Likewise.
- (loongarch_cmodel_strings): Likewise.
- (abi_minimal_isa): Likewise.
- (loongarch_rtx_cost_optimize_size): Use field setter functions
- instead of designated initializers.
- (loongarch_rtx_cost_data): Implement default constructor.
-
-2023-12-08 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112411
- * params.opt (-param=min-nondebug-insn-uid=): Add
- IntegerRange(0, 1073741824).
- * lra.cc (check_and_expand_insn_recog_data): Use 3U rather than 3
- in * 3 / 2 computation and if the result is smaller or equal to
- index, use index + 1.
-
-2023-12-08 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Do not append "-mno-" for Xeon Phi ISAs.
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Emit a warning for KNL/KNM targets.
- * config/i386/i386.opt: Emit a warning for Xeon Phi ISAs.
-
-2023-12-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p):
- Remove redundant check.
-
-2023-12-08 Hao Liu <hliu@os.amperecomputing.com>
-
- PR tree-optimization/112774
- * tree-pretty-print.cc: if nonwrapping flag is set, chrec will be
- printed with additional <nw> info.
- * tree-scalar-evolution.cc: add record_nonwrapping_chrec and
- nonwrapping_chrec_p to set and check the new flag respectively.
- * tree-scalar-evolution.h: Likewise.
- * tree-ssa-loop-niter.cc (idx_infer_loop_bounds,
- infer_loop_bounds_from_pointer_arith, infer_loop_bounds_from_signedness,
- scev_probably_wraps_p): call record_nonwrapping_chrec before
- record_nonwrapping_iv, call nonwrapping_chrec_p to check the flag is
- set and return false from scev_probably_wraps_p.
- * tree-vect-loop.cc (vect_analyze_loop): call
- free_numbers_of_iterations_estimates explicitly.
- * tree-core.h: document the nothrow_flag usage in CHREC_NOWRAP
- * tree.h: add CHREC_NOWRAP(NODE), base.nothrow_flag is used to
- represent the nonwrapping info.
-
-2023-12-08 Fei Gao <gaofei@eswincomputing.com>
-
- * ifcvt.cc (noce_try_cond_zero_arith): New function.
- (noce_emit_czero, get_base_reg): Likewise.
- (noce_cond_zero_binary_op_supported): Likewise.
- (noce_bbs_ok_for_cond_zero_arith): Likewise.
- (noce_process_if_block): Use noce_try_cond_zero_arith.
- Co-authored-by: Xiao Zeng<zengxiao@eswincomputing.com>
-
-2023-12-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (expand_vec_series): Adapt function.
- * config/riscv/riscv-v.cc (rvv_builder::double_steps_npatterns_p): New function.
- (expand_vec_series): Adapt function.
- (expand_const_vector): Support new interleave vector with different step.
-
-2023-12-07 Richard Sandiford <richard.sandiford@arm.com>
-
- PR rtl-optimization/106694
- PR rtl-optimization/109078
- PR rtl-optimization/109391
- * config.gcc: Add aarch64-early-ra.o for AArch64 targets.
- * config/aarch64/t-aarch64 (aarch64-early-ra.o): New rule.
- * config/aarch64/aarch64-opts.h (aarch64_early_ra_scope): New enum.
- * config/aarch64/aarch64.opt (mearly_ra): New option.
- * doc/invoke.texi: Document it.
- * common/config/aarch64/aarch64-common.cc
- (aarch_option_optimization_table): Use -mearly-ra=strided by
- default for -O2 and above.
- * config/aarch64/aarch64-passes.def (pass_aarch64_early_ra): New pass.
- * config/aarch64/aarch64-protos.h (aarch64_strided_registers_p)
- (make_pass_aarch64_early_ra): Declare.
- * config/aarch64/aarch64-sme.md (@aarch64_sme_lut<LUTI_BITS><mode>):
- Add a stride_type attribute.
- (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): New pattern.
- (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
- * config/aarch64/aarch64-sve-builtins-base.cc (svld1_impl::expand)
- (svldnt1_impl::expand, svst1_impl::expand, svstn1_impl::expand): Handle
- new way of defining multi-register loads and stores.
- * config/aarch64/aarch64-sve.md (@aarch64_ld1<SVE_FULLx24:mode>)
- (@aarch64_ldnt1<SVE_FULLx24:mode>, @aarch64_st1<SVE_FULLx24:mode>)
- (@aarch64_stnt1<SVE_FULLx24:mode>): Delete.
- * config/aarch64/aarch64-sve2.md (@aarch64_<LD1_COUNT:optab><mode>)
- (@aarch64_<LD1_COUNT:optab><mode>_strided2): New patterns.
- (@aarch64_<LD1_COUNT:optab><mode>_strided4): Likewise.
- (@aarch64_<ST1_COUNT:optab><mode>): Likewise.
- (@aarch64_<ST1_COUNT:optab><mode>_strided2): Likewise.
- (@aarch64_<ST1_COUNT:optab><mode>_strided4): Likewise.
- * config/aarch64/aarch64.cc (aarch64_strided_registers_p): New
- function.
- * config/aarch64/aarch64.md (UNSPEC_LD1_SVE_COUNT): Delete.
- (UNSPEC_ST1_SVE_COUNT, UNSPEC_LDNT1_SVE_COUNT): Likewise.
- (UNSPEC_STNT1_SVE_COUNT): Likewise.
- (stride_type): New attribute.
- * config/aarch64/constraints.md (Uwd, Uwt): New constraints.
- * config/aarch64/iterators.md (UNSPEC_LD1_COUNT, UNSPEC_LDNT1_COUNT)
- (UNSPEC_ST1_COUNT, UNSPEC_STNT1_COUNT): New unspecs.
- (optab): Handle them.
- (LD1_COUNT, ST1_COUNT): New iterators.
- * config/aarch64/aarch64-early-ra.cc: New file.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New
- (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
- (vld1_f16_x4, vld1_f32_x4): New.
- (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
- (vld1_bf16_x4): New.
- (vld1q_types_x4): Updated to use vld1q_x4
- from arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x4): Updated entries.
- (vld1q_x4): New entries, but comes from the old vld1_x2
- * config/arm/neon.md (neon_vld1q_x4<mode>):
- Updated from neon_vld1_x4<mode>.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New
- (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
- (vld1_f16_x3, vld1_f32_x3): New.
- (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
- (vld1_bf16_x3): New.
- (vld1q_types_x3): Updated to use vld1q_x3 from
- arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x3): Updated entries.
- (vld1q_x3): New entries, but comes from the old vld1_x2
- * config/arm/neon.md (neon_vld1q_x3<mode>): Updated from
- neon_vld1_x3<mode>.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New
- (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
- (vld1_f16_x2, vld1_f32_x2): New.
- (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
- (vld1_bf16_x2): New.
- (vld1q_types_x2): Updated to use vld1q_x2 from
- arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x2): Updated entries.
- (vld1q_x2): New entries, but comes from the old vld1_x2
- * config/arm/neon.md
- (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated
- from neon_vld1_x2<mode>.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
- (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
- (vst1q_f16_x4, vst1q_f32_x4): New.
- (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
- (vst1q_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
- * config/arm/neon.md (neon_vst1q_x4<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
- (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
- (vst1q_f16_x3, vst1q_f32_x3): New.
- (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
- (vst1q_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
- * config/arm/neon.md (neon_vst1q_x3<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
- (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
- (vst1q_f16_x2, vst1q_f32_x2): New.
- (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
- (vst1q_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vst1q_x2): New entries.
- * config/arm/neon.md
- (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
- neon_vst1_x2<mode>.
- * config/arm/iterators.md (VMEMX2): New mode iterator.
- (VMEMX2_q): New mode attribute.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
- (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
- (vst1_f16_x4, vst1_f32_x4): New.
- (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
- (vst1_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
- * config/arm/neon.md (vst1_x4<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
- (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
- (vst1_f16_x3, vst1_f32_x3): New.
- (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
- (vst1_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
- * config/arm/neon.md (vst1_x3<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
- (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
- (vst1_f16_x2, vst1_f32_x2): New.
- (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
- (vst1_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
- * config/arm/neon.md (vst1_x2<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
- (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
- (vld1q_f16_x4, vld1q_f32_x4): New.
- (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
- (vld1q_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
- * config/arm/neon.md (vld1_x4<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
- (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
- (vld1q_f16_x3, vld1q_f32_x3): New.
- (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
- (vld1q_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
- * config/arm/neon.md (vld1_x3<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
- (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
- (vld1q_f16_x2, vld1q_f32_x2): New.
- (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
- (vld1q_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
- * config/arm/neon.md (vld1_x2<mode>): New.
-
-2023-12-07 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/vecintrin.h (vec_step): Expand vec_step to
- __builtin_s390_vec_step.
-
-2023-12-07 Alexandre Oliva <oliva@adacore.com>
-
- * target.def (have_strub_support_for): New hook.
- * doc/tm.texi.in: Document it.
- * doc/tm.texi: Rebuild.
- * ipa-strub.cc: Include target.h.
- (strub_target_support_p): New.
- (can_strub_p): Call it. Test for no flag_split_stack.
- (pass_ipa_strub::adjust_at_calls_call): Check for target
- support.
- * config/nvptx/nvptx.cc (TARGET_HAVE_STRUB_SUPPORT_FOR):
- Disable.
- * doc/sourcebuild.texi (strub): Document new effective
- target.
-
-2023-12-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-avlprop.cc (simplify_replace_avl): New function.
- (simplify_replace_vlmax_avl): Fix bug.
- * config/riscv/t-riscv: Add a new include file.
-
-2023-12-07 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/thead.cc (th_memidx_classify_address_index):
- Require TARGET_XTHEADMEMIDX for FP modes.
- * config/riscv/thead.md: Require TARGET_XTHEADMEMIDX for all
- XTheadFMemIdx pattern.
-
-2023-12-07 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112881
- * expr.cc (count_type_elements): Handle BITINT_TYPE like INTEGER_TYPE.
-
-2023-12-07 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112880
- * tree-ssa-dce.cc (maybe_optimize_arith_overflow): Use
- unsigned_type_for instead of conditionally calling
- build_nonstandard_integer_type.
-
-2023-12-07 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/arm_neon.h (vldap1_lane_u64): New.
- (vldap1q_lane_u64): Likewise.
- (vldap1_lane_s64): Likewise.
- (vldap1q_lane_s64): Likewise.
- (vldap1_lane_f64): Likewise.
- (vldap1q_lane_f64): Likewise.
- (vldap1_lane_p64): Likewise.
- (vldap1q_lane_p64): Likewise.
- (vstl1_lane_u64): Likewise.
- (vstl1q_lane_u64): Likewise.
- (vstl1_lane_s64): Likewise.
- (vstl1q_lane_s64): Likewise.
- (vstl1_lane_f64): Likewise.
- (vstl1q_lane_f64): Likewise.
- (vstl1_lane_p64): Likewise.
- (vstl1q_lane_p64): Likewise.
-
-2023-12-07 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-simd-builtins.def
- (vec_ldap1_lane): New.
- (vec_stl1_lane): Likewise.
- * config/aarch64/aarch64-simd.md
- (aarch64_vec_stl1_lanes<mode>_lane<Vel>): New.
- (aarch64_vec_stl1_lane<mode>): Likewise.
- (aarch64_vec_ldap1_lanes<mode>_lane<Vel>): Likewise.
- (aarch64_vec_ldap1_lane<mode>): Likewise.
- * config/aarch64/aarch64.md (UNSPEC_LDAP1_LANE): New.
- (UNSPEC_STL1_LANE): Likewise.
-
-2023-12-07 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/iterators.md (V12DIF): New.
- (V12DUP): Likewise.
- (VEL): Add support for all V12DIF-associated modes.
- (Vetype): Add support for V1DI and V1DF.
- (Vel): Likewise.
-
-2023-12-07 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-option-extensions.def (rcpc3): New.
- * config/aarch64/aarch64.h (AARCH64_ISA_RCPC3): Likewise.
- (TARGET_RCPC3): Likewise.
- * doc/invoke.texi (rcpc3): Document feature in AArch64 Options.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386-expand.cc (ix86_split_ashl_ndd): New
- function to split NDD form lshift.
- (ix86_split_rshift_ndd): Likewise for l/ashiftrt.
- * config/i386/i386-protos.h (ix86_split_ashl_ndd): New
- prototype.
- (ix86_split_rshift_ndd): Likewise.
- * config/i386/i386.md (ashl<mode>3_doubleword): Add NDD
- alternative, call ndd split function when operands[0]
- not equal to operands[1].
- (define_split for doubleword lshift): Likewise.
- (define_peephole for doubleword lshift): Likewise.
- (<insn><mode>3_doubleword): Likewise for l/ashiftrt.
- (define_split for doubleword l/ashiftrt): Likewise.
- (define_peephole for doubleword l/ashiftrt): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (*mov<mode>cc_noc): Extend with new constraints
- to support NDD.
- (*movsicc_noc_zext): Likewise.
- (*movsicc_noc_zext_1): Likewise.
- (*movqicc_noc): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (x86_64_shld_ndd): New define_insn.
- (x86_64_shld_ndd_1): Likewise.
- (*x86_64_shld_ndd_2): Likewise.
- (x86_shld_ndd): Likewise.
- (x86_shld_ndd_1): Likewise.
- (*x86_shld_ndd_2): Likewise.
- (x86_64_shrd_ndd): Likewise.
- (x86_64_shrd_ndd_1): Likewise.
- (*x86_64_shrd_ndd_2): Likewise.
- (x86_shrd_ndd): Likewise.
- (x86_shrd_ndd_1): Likewise.
- (*x86_shrd_ndd_2): Likewise.
- (*x86_64_shld_shrd_1_nozext): Adjust codegen under TARGET_APX_NDD.
- (*x86_shld_shrd_1_nozext): Likewise.
- (*x86_64_shrd_shld_1_nozext): Likewise.
- (*x86_shrd_shld_1_nozext): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (*<insn><mode>3_1): Extend with a new
- alternative to support NDD for SI/DI rotate, and adjust output
- template.
- (*<insn>si3_1_zext): Likewise.
- (*<insn><mode>3_1): Likewise for QI/HI modes.
- (rcrsi2): Likewise, and use nonimmediate_operand for operands[1]
- to accept memory input for NDD alternative.
- (rcrdi2): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (ashr<mode>3_cvt): Extend with new
- alternatives to support NDD, and adjust output templates.
- (*ashr<mode>3_1): Likewise for SI/DI mode.
- (*lshr<mode>3_1): Likewise.
- (*<insn>si3_1_zext): Likewise.
- (*ashr<mode>3_1): Likewise for QI/HI mode.
- (*lshrqi3_1): Likewise.
- (*lshrhi3_1): Likewise.
- (<insn><mode>3_cmp): Likewise.
- (*<insn><mode>3_cconly): Likewise.
- (*ashrsi3_cvt_zext): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
- (*highpartdisi2): Likewise.
- (*<insn>si3_cmp_zext): Likewise.
- (<insn><mode>3_carry): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (*ashl<mode>3_1): Extend with new
- alternatives to support NDD, limit the new alternative to
- generate sal only, and adjust output template for NDD.
- (*ashlsi3_1_zext): Likewise.
- (*ashlhi3_1): Likewise.
- (*ashlqi3_1): Likewise.
- (*ashl<mode>3_cmp): Likewise.
- (*ashlsi3_cmp_zext): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
- (*ashl<mode>3_cconly): Likewise.
- (*ashl<dwi>3_doubleword_highpart): Adjust codegen for NDD.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (<code><mode>3): Add new alternative for NDD
- and adjust output templates.
- (*<code><mode>_1): Likewise.
- (*<code>qi_1): Likewise.
- (*notxor<mode>_1): Likewise.
- (*<code>si_1_zext): Likewise.
- (*notxorqi_1): Likewise.
- (*<code><mode>_2): Likewise.
- (*<code>si_2_zext): Likewise.
- (*<code>si_2_zext_imm): Likewise.
- (*<code>si_1_zext_imm): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
- (*one_cmplsi2_2_zext): Likewise.
- (define_split for *one_cmplsi2_2_zext): Use nonimmediate_operand for
- operands[3].
- (*<code><dwi>3_doubleword): Add NDD constraints, adopt '&' to NDD dest
- and emit move for optimized case if operands[0] != operands[1] or
- operands[4] != operands[5].
- (define_split for QI highpart OR/XOR): Prohibit splitter to split NDD
- form OR/XOR insn to <any_logic:code>qi_ext<mode>_3.
- (define_split for QI strict_lowpart optimization): Prohibit splitter to
- split NDD form AND insn to *<code><mode>3_1_slp.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (and<mode>3): Add NDD alternatives and adjust
- output template.
- (*anddi_1): Likewise.
- (*and<mode>_1): Likewise.
- (*andqi_1): Likewise.
- (*andsi_1_zext): Likewise.
- (*anddi_2): Likewise.
- (*andsi_2_zext): Likewise.
- (*andqi_2_maybe_si): Likewise.
- (*and<mode>_2): Likewise.
- (*and<dwi>3_doubleword): Add NDD alternative, adopt '&' to NDD dest and
- emit move for optimized case if operands[0] not equal to operands[1].
- (define_split for QI highpart AND): Prohibit splitter to split NDD
- form AND insn to <any_logic:code>qi_ext<mode>_3.
- (define_split for QI strict_lowpart optimization): Prohibit splitter to
- split NDD form AND insn to *<code><mode>3_1_slp.
- (define_split for zero_extend and optimization): Prohibit splitter to
- split NDD form AND insn to zero_extend insn.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (one_cmpl<mode>2): Add new constraints for NDD
- and adjust output template.
- (*one_cmpl<mode>2_1): Likewise.
- (*one_cmplqi2_1): Likewise.
- (*one_cmpl<dwi>2_doubleword): Likewise, and adopt '&' to NDD dest.
- (*one_cmpl<mode>2_2): Likewise.
- (*one_cmplsi2_1_zext): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386-expand.cc (ix86_expand_unary_operator): Add use_ndd
- parameter and adjust for NDD.
- * config/i386/i386-protos.h: Add use_ndd parameter for
- ix86_unary_operator_ok and ix86_expand_unary_operator.
- * config/i386/i386.cc (ix86_unary_operator_ok): Add use_ndd parameter
- and adjust for NDD.
- * config/i386/i386.md (neg<mode>2): Add new constraint for NDD and
- adjust output template.
- (*neg<mode>_1): Likewise.
- (*neg<dwi>2_doubleword): Likewise and adopt '&' to NDD dest.
- (*neg<mode>_2): Likewise.
- (*neg<mode>_ccc_1): Likewise.
- (*neg<mode>_ccc_2): Likewise.
- (*negsi_1_zext): Likewise, and use nonimmediate_operand for operands[1]
- to accept memory input for NDD alternatives.
- (*negsi_2_zext): Likewise.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (*sub<dwi>3_doubleword): Add new alternative for
- NDD, adopt '&' modifier to NDD dest and emit move when operands[0] not
- equal to operands[1].
- (*sub<dwi>3_doubleword_zext): Likewise.
- (*subv<dwi>4_doubleword): Likewise.
- (*subv<dwi>4_doubleword_1): Likewise.
- (*subv<mode>4_overflow_1): Add NDD alternatives and adjust output
- templates.
- (*subv<mode>4_overflow_2): Likewise.
- (@sub<mode>3_carry): Likewise.
- (*addsi3_carry_zext_0r): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
- (*subsi3_carry_zext): Likewise.
- (subborrow<mode>): Parse TARGET_APX_NDD to ix86_binary_operator_ok.
- (subborrow<mode>_0): Likewise.
- (*sub<mode>3_eq): Likewise.
- (*sub<mode>3_ne): Likewise.
- (*sub<mode>3_eq_1): Likewise.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386-expand.cc (ix86_fixup_binary_operands_no_copy):
- Add use_ndd parameter and parse it.
- * config/i386/i386-protos.h (ix86_fixup_binary_operands_no_copy):
- Change define.
- * config/i386/i386.md (sub<mode>3): Add new alternatives for NDD
- and adjust output templates.
- (*sub<mode>_1): Likewise.
- (*sub<mode>_2): Likewise.
- (subv<mode>4): Likewise.
- (*subv<mode>4): Likewise.
- (subv<mode>4_1): Likewise.
- (usubv<mode>4): Likewise.
- (*sub<mode>_3): Likewise.
- (*subsi_1_zext): Likewise, and use nonimmediate_operand for operands[1]
- to accept memory input for NDD alternatives.
- (*subsi_2_zext): Likewise.
- (*subsi_3_zext): Likewise.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (*add<dwi>3_doubleword): Add ndd alternatives,
- adopt '&' to ndd dest and move operands[1] to operands[0] when they are
- not equal.
- (*add<dwi>3_doubleword_cc_overflow_1): Likewise.
- (*addv<dwi>4_doubleword): Likewise.
- (*addv<dwi>4_doubleword_1): Likewise.
- (*add<dwi>3_doubleword_zext): Likewise.
- (addv<mode>4_overflow_1): Add ndd alternatives.
- (*addv<mode>4_overflow_2): Likewise.
- (@add<mode>3_carry): Likewise.
- (*add<mode>3_carry_0): Likewise.
- (*addsi3_carry_zext): Likewise.
- (addcarry<mode>): Likewise.
- (addcarry<mode>_0): Likewise.
- (*addcarry<mode>_1): Likewise.
- (*add<mode>3_eq): Likewise.
- (*add<mode>3_ne): Likewise.
- (*addsi3_carry_zext_0): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/constraints.md (je): New constraint.
- * config/i386/i386-protos.h (x86_poff_operand_p): New function to
- check any *POFF constant in operand.
- * config/i386/i386.cc (x86_poff_operand_p): New prototype.
- * config/i386/i386.md (*add<mode>_1): Split out je alternative for add.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md: (addsi_1_zext): Add new alternatives for
- NDD and adjust output templates.
- (*add<mode>_2): Likewise.
- (*addsi_2_zext): Likewise.
- (*add<mode>_3): Likewise.
- (*addsi_3_zext): Likewise.
- (*adddi_4): Likewise.
- (*add<mode>_4): Likewise.
- (*add<mode>_5): Likewise.
- (*addv<mode>4): Likewise.
- (*addv<mode>4_1): Likewise.
- (*add<mode>3_cconly_overflow_1): Likewise.
- (*add<mode>3_cc_overflow_1): Likewise.
- (*addsi3_zext_cc_overflow_1): Likewise.
- (*add<mode>3_cconly_overflow_2): Likewise.
- (*add<mode>3_cc_overflow_2): Likewise.
- (*addsi3_zext_cc_overflow_2): Likewise.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386-expand.cc (ix86_fixup_binary_operands): Add
- new use_ndd flag to check whether ndd can be used for this binop
- and adjust operand emit.
- (ix86_binary_operator_ok): Likewise.
- (ix86_expand_binary_operator): Likewise, and void postreload
- expand generate lea pattern when use_ndd is explicit parsed.
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Prohibit apx subfeatures when not in 64bit mode.
- * config/i386/i386-protos.h (ix86_binary_operator_ok):
- Add use_ndd flag.
- (ix86_fixup_binary_operand): Likewise.
- (ix86_expand_binary_operand): Likewise.
- * config/i386/i386.md (*add<mode>_1): Extend with new alternatives
- to support NDD, and adjust output template.
- (*addhi_1): Likewise.
- (*addqi_1): Likewise.
-
-2023-12-07 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/103546
- PR analyzer/112850
- * doc/invoke.texi: Add -Wanalyzer-symbol-too-complex.
-
-2023-12-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (extract_single_source): new function.
- (pre_vsetvl::compute_lcm_local_properties): Fix ICE.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (AARCH64_RSR128): New
- `enum aarch64_builtins' value.
- (AARCH64_WSR128): Likewise.
- (aarch64_init_rwsr_builtins): Init `__builtin_aarch64_rsr128'
- and `__builtin_aarch64_wsr128' builtins.
- (aarch64_expand_rwsr_builtin): Extend function to handle
- `__builtin_aarch64_{rsr|wsr}128'.
- * config/aarch64/aarch64-protos.h (aarch64_retrieve_sysreg):
- Update function signature.
- * config/aarch64/aarch64.cc (F_REG_128): New.
- (aarch64_retrieve_sysreg): Add 128-bit register mode check.
- * config/aarch64/aarch64.md (UNSPEC_SYSREG_RTI): New.
- (UNSPEC_SYSREG_WTI): Likewise.
- (aarch64_read_sysregti): Likewise.
- (aarch64_write_sysregti): Likewise.
- * config/aarch64/arm_acle.h (__arm_rsr128): New.
- (__arm_wsr128): Likewise.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-option-extensions.def (gcs): New.
- * config/aarch64/aarch64.h (AARCH64_ISA_GCS): New.
- (TARGET_THE): Likewise.
- * doc/invoke.texi (AArch64 Options): Describe GCS.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-c.cc (__ARM_FEATURE_SYSREG128): New.
- * config/aarch64/aarch64-arches.def (armv8.9-a): New.
- (armv9.4-a): Likewise.
- * config/aarch64/aarch64-option-extensions.def (d128): Likewise.
- (the): Likewise.
- * config/aarch64/aarch64.h (AARCH64_ISA_V9_4A): Likewise.
- (AARCH64_ISA_V8_9A): Likewise.
- (TARGET_ARMV9_4): Likewise.
- (AARCH64_ISA_D128): Likewise.
- (AARCH64_ISA_THE): Likewise.
- (TARGET_D128): Likewise.
- * doc/invoke.texi (AArch64 Options): Document new -march flags
- and extensions.
-
-2023-12-06 Eric Gallager <egallager@gcc.gnu.org>
-
- * Makefile.in: Remove qmtest-related targets.
-
-2023-12-06 David Malcolm <dmalcolm@redhat.com>
-
- * common.opt (fdiagnostics-json-formatting): New.
- * diagnostic-format-json.cc: Add "formatted" boolean
- to json_output_format and subclasses, and to the
- diagnostic_output_format_init_json_* functions. Use it when
- printing JSON.
- * diagnostic-format-sarif.cc: Likewise for sarif_builder,
- sarif_output_format, and the various
- diagnostic_output_format_init_sarif_* functions.
- * diagnostic.cc (diagnostic_output_format_init): Add
- "json_formatting" boolean and pass on to the various cases.
- * diagnostic.h (diagnostic_output_format_init): Add
- "json_formatted" param.
- (diagnostic_output_format_init_json_stderr): Add "formatted" param
- (diagnostic_output_format_init_json_file): Likewise.
- (diagnostic_output_format_init_sarif_stderr): Likewise.
- (diagnostic_output_format_init_sarif_file): Likewise.
- (diagnostic_output_format_init_sarif_stream): Likewise.
- * doc/invoke.texi (-fdiagnostics-format=json): Remove discussion
- about JSON output needing formatting.
- (-fno-diagnostics-json-formatting): Add.
- * gcc.cc (driver_handle_option): Use
- opts->x_flag_diagnostics_json_formatting.
- * gcov.cc (generate_results): Pass "false" for new formatting
- option when printing json.
- * json.cc (value::dump): Add new "formatted" param.
- (object::print): Likewise, using it to add whitespace to format
- the JSON output.
- (array::print): Likewise.
- (float_number::print): Add new "formatted" param.
- (integer_number::print): Likewise.
- (string::print): Likewise.
- (literal::print): Likewise.
- (selftest::assert_print_eq): Add "formatted" param.
- (ASSERT_PRINT_EQ): Add "FORMATTED" param.
- (selftest::test_writing_objects): Test both formatted and
- unformatted printing.
- (selftest::test_writing_arrays): Likewise.
- (selftest::test_writing_float_numbers): Update for new param of
- ASSERT_PRINT_EQ.
- (selftest::test_writing_integer_numbers): Likewise.
- (selftest::test_writing_strings): Likewise.
- (selftest::test_writing_literals): Likewise.
- (selftest::test_formatting): New.
- (selftest::json_cc_tests): Call it.
- * json.h (value::print): Add "formatted" param.
- (value::dump): Likewise.
- (object::print): Likewise.
- (array::print): Likewise.
- (float_number::print): Likewise.
- (integer_number::print): Likewise.
- (string::print): Likewise.
- (literal::print): Likewise.
- * optinfo-emit-json.cc (optrecord_json_writer::write): Pass
- "false" for new formatting option when printing json.
- (selftest::test_building_json_from_dump_calls): Likewise.
- * opts.cc (common_handle_option): Use
- opts->x_flag_diagnostics_json_formatting.
-
-2023-12-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-json.cc (on_begin_diagnostic): Convert param
- to const reference.
- (on_end_diagnostic): Likewise.
- (json_output_format::on_end_diagnostic): Likewise.
- * diagnostic-format-sarif.cc
- (sarif_invocation::add_notification_for_ice): Likewise.
- (sarif_result::on_nested_diagnostic): Likewise.
- (sarif_ice_notification::sarif_ice_notification): Likewise.
- (sarif_builder::end_diagnostic): Likewise.
- (sarif_builder::make_result_object): Likewise.
- (make_reporting_descriptor_object_for_warning): Likewise.
- (sarif_builder::make_locations_arr): Likewise.
- (sarif_output_format::on_begin_diagnostic): Likewise.
- (sarif_output_format::on_end_diagnostic): Likewise.
- * diagnostic.cc (default_diagnostic_starter): Make diagnostic_info
- param const.
- (default_diagnostic_finalizer): Likewise.
- (diagnostic_context::report_diagnostic): Pass diagnostic by
- reference to on_{begin,end}_diagnostic.
- (diagnostic_text_output_format::on_begin_diagnostic): Convert
- param to const reference.
- (diagnostic_text_output_format::on_end_diagnostic): Likewise.
- * diagnostic.h (diagnostic_starter_fn): Make diagnostic_info param
- const.
- (diagnostic_finalizer_fn): Likeewise.
- (diagnostic_output_format::on_begin_diagnostic): Convert param to
- const reference.
- (diagnostic_output_format::on_end_diagnostic): Likewise.
- (diagnostic_text_output_format::on_begin_diagnostic): Likewise.
- (diagnostic_text_output_format::on_end_diagnostic): Likewise.
- (default_diagnostic_starter): Make diagnostic_info param const.
- (default_diagnostic_finalizer): Likewise.
- * langhooks-def.h (lhd_print_error_function): Make diagnostic_info
- param const.
- * langhooks.cc (lhd_print_error_function): Likewise.
- * langhooks.h (lang_hooks::print_error_function): Likewise.
- * tree-diagnostic.cc (diagnostic_report_current_function):
- Likewise.
- (default_tree_diagnostic_starter): Likewise.
- (virt_loc_aware_diagnostic_finalizer): Likewise.
- * tree-diagnostic.h (diagnostic_report_current_function):
- Likewise.
- (virt_loc_aware_diagnostic_finalizer): Likewise.
-
-2023-12-06 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-builtins.def (DISPATCH_PTR): New built-in.
- * config/gcn/gcn.cc (gcn_init_machine_status): Disable global
- addressing.
- (gcn_expand_builtin_1): Implement GCN_BUILTIN_DISPATCH_PTR.
-
-2023-12-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112855
- * config/riscv/riscv-vsetvl.cc
- (pre_vsetvl::compute_lcm_local_properties): Fix transparant LCM data.
- (pre_vsetvl::earliest_fuse_vsetvl_info): Disable earliest fusion for unrelated edge.
-
-2023-12-06 Marek Polacek <polacek@redhat.com>
-
- PR target/112762
- * config/linux.h: Redefine TARGET_FORTIFY_SOURCE_DEFAULT_LEVEL for
- glibc only.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64.cc
- (aarch64_test_sysreg_encoding_clashes): New.
- (aarch64_run_selftests): add call to
- aarch64_test_sysreg_encoding_clashes selftest.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (aarch64_general_check_builtin_call):
- New.
- * config/aarch64/aarch64-c.cc (aarch64_check_builtin_call):
- Add `aarch64_general_check_builtin_call' call.
- * config/aarch64/aarch64-protos.h (aarch64_general_check_builtin_call):
- New.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (enum aarch64_builtins):
- Add enums for new builtins.
- (aarch64_init_rwsr_builtins): New.
- (aarch64_general_init_builtins): Call aarch64_init_rwsr_builtins.
- (aarch64_expand_rwsr_builtin): New.
- (aarch64_general_expand_builtin): Call aarch64_general_expand_builtin.
- * config/aarch64/aarch64.md (read_sysregdi): New insn_and_split.
- (write_sysregdi): Likewise.
- * config/aarch64/arm_acle.h (__arm_rsr): New.
- (__arm_rsrp): Likewise.
- (__arm_rsr64): Likewise.
- (__arm_rsrf): Likewise.
- (__arm_rsrf64): Likewise.
- (__arm_wsr): Likewise.
- (__arm_wsrp): Likewise.
- (__arm_wsr64): Likewise.
- (__arm_wsrf): Likewise.
- (__arm_wsrf64): Likewise.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_valid_sysreg_name_p): New.
- (aarch64_retrieve_sysreg): Likewise.
- * config/aarch64/aarch64.cc (is_implem_def_reg): Likewise.
- (aarch64_valid_sysreg_name_p): Likewise.
- (aarch64_retrieve_sysreg): Likewise.
- (aarch64_register_sysreg): Likewise.
- (aarch64_init_sysregs): Likewise.
- (aarch64_lookup_sysreg_map): Likewise.
- * config/aarch64/predicates.md (aarch64_sysreg_string): New.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64.cc (sysreg_t): New.
- (aarch64_sysregs): Likewise.
- (AARCH64_FEATURE): Likewise.
- (AARCH64_FEATURES): Likewise.
- (AARCH64_NO_FEATURES): Likewise.
- * config/aarch64/aarch64.h (AARCH64_ISA_V8A): Add missing
- ISA flag.
- (AARCH64_ISA_V8_1A): Likewise.
- (AARCH64_ISA_V8_7A): Likewise.
- (AARCH64_ISA_V8_8A): Likewise.
- (AARCH64_NO_FEATURES): Likewise.
- (AARCH64_FL_RAS): New ISA flag alias.
- (AARCH64_FL_LOR): Likewise.
- (AARCH64_FL_PAN): Likewise.
- (AARCH64_FL_AMU): Likewise.
- (AARCH64_FL_SCXTNUM): Likewise.
- (AARCH64_FL_ID_PFR2): Likewise.
- (F_DEPRECATED): New.
- (F_REG_READ): Likewise.
- (F_REG_WRITE): Likewise.
- (F_ARCHEXT): Likewise.
- (F_REG_ALIAS): Likewise.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-sys-regs.def: New.
-
-2023-12-06 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112854
- PR target/112872
- * config/riscv/autovec.md (vec_init<mode>qi): New expander.
-
-2023-12-06 Jakub Jelinek <jakub@redhat.com>
-
- PR rtl-optimization/112760
- * config/i386/i386-passes.def (pass_insert_vzeroupper): Insert
- after pass_postreload_cse rather than pass_reload.
- * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
- Adjust comment for it.
-
-2023-12-06 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112809
- * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt): For
- separate_ext in kind == bitint_prec_huge mode if rem == 0, create for
- i == cnt - 1 the loop rather than using size_int (end).
-
-2023-12-06 Jakub Jelinek <jakub@redhat.com>
-
- * gcc.cc (driver_handle_option): Add /* FALLTHROUGH */ comment
- between OPT_pie and OPT_r cases.
-
-2023-12-06 Tobias Burnus <tobias@codesourcery.com>
-
- * tsystem.h (calloc, realloc): Declare when inhibit_libc.
-
-2023-12-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112843
- * tree-ssa-operands.cc (update_stmt_operands): Do not call
- update_stmt from ranger.
- * value-query.h (range_query::update_stmt): Remove.
- * gimple-range.h (gimple_ranger::update_stmt): Likewise.
- * gimple-range.cc (gimple_ranger::update_stmt): Likewise.
-
-2023-12-06 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv.md: Remove.
-
-2023-12-06 Alexandre Oliva <oliva@adacore.com>
-
- * Makefile.in (OBJS): Add ipa-strub.o.
- (GTFILES): Add ipa-strub.cc.
- * builtins.def (BUILT_IN_STACK_ADDRESS): New.
- (BUILT_IN___STRUB_ENTER): New.
- (BUILT_IN___STRUB_UPDATE): New.
- (BUILT_IN___STRUB_LEAVE): New.
- * builtins.cc: Include ipa-strub.h.
- (STACK_STOPS, STACK_UNSIGNED): Define.
- (expand_builtin_stack_address): New.
- (expand_builtin_strub_enter): New.
- (expand_builtin_strub_update): New.
- (expand_builtin_strub_leave): New.
- (expand_builtin): Call them.
- * common.opt (fstrub=*): New options.
- * doc/extend.texi (strub): New type attribute.
- (__builtin_stack_address): New function.
- (Stack Scrubbing): New section.
- * doc/invoke.texi (-fstrub=*): New options.
- (-fdump-ipa-*): New passes.
- * gengtype-lex.l: Ignore multi-line pp-directives.
- * ipa-inline.cc: Include ipa-strub.h.
- (can_inline_edge_p): Test strub_inlinable_to_p.
- * ipa-split.cc: Include ipa-strub.h.
- (execute_split_functions): Test strub_splittable_p.
- * ipa-strub.cc, ipa-strub.h: New.
- * passes.def: Add strub_mode and strub passes.
- * tree-cfg.cc (gimple_verify_flow_info): Note on debug stmts.
- * tree-pass.h (make_pass_ipa_strub_mode): Declare.
- (make_pass_ipa_strub): Declare.
- (make_pass_ipa_function_and_variable_visibility): Fix
- formatting.
- * tree-ssa-ccp.cc (optimize_stack_restore): Keep restores
- before strub leave.
- * attribs.cc: Include ipa-strub.h.
- (decl_attributes): Support applying attributes to function
- type, rather than pointer type, at handler's request.
- (comp_type_attributes): Combine strub_comptypes and target
- comp_type results.
- * doc/tm.texi.in (TARGET_STRUB_USE_DYNAMIC_ARRAY): New.
- (TARGET_STRUB_MAY_USE_MEMSET): New.
- * doc/tm.texi: Rebuilt.
- * cgraph.h (symtab_node::reset): Add preserve_comdat_group
- param, with a default.
- * cgraphunit.cc (symtab_node::reset): Use it.
-
-2023-12-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112851
- PR target/112852
- * config/riscv/riscv-v.cc (vls_mode_valid_p): Block VLSmodes according
- TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR.
-
-2023-12-05 David Faust <david.faust@oracle.com>
-
- PR debug/112849
- * btfout.cc (btf_collect_datasec): Avoid incorrectly creating an
- entry in a BTF_KIND_DATASEC record for extern variable decls without
- a known section.
-
-2023-12-05 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112606
- * config/rs6000/rs6000.md (copysign<mode>3): Change predicate
- of the last argument from gpc_reg_operand to any_operand. If
- operands[2] is CONST_DOUBLE, emit abs or neg abs depending on
- its sign, otherwise if it doesn't satisfy gpc_reg_operand,
- force it to REG using copy_to_mode_reg.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.cc (handle_ignored_attributes_option): Add extra
- braces to work around PR 16333 in older compilers.
- * config/aarch64/aarch64.cc (aarch64_gnu_attribute_table): Likewise.
- (aarch64_arm_attribute_table): Likewise.
- * config/arm/arm.cc (arm_gnu_attribute_table): Likewise.
- * config/i386/i386-options.cc (ix86_gnu_attribute_table): Likewise.
- * config/ia64/ia64.cc (ia64_gnu_attribute_table): Likewise.
- * config/rs6000/rs6000.cc (rs6000_gnu_attribute_table): Likewise.
- * target-def.h (TARGET_GNU_ATTRIBUTES): Likewise.
- * genhooks.cc (emit_init_macros): Likewise, when emitting the
- instantiation of TARGET_ATTRIBUTE_TABLE.
- * langhooks-def.h (LANG_HOOKS_INITIALIZER): Likewise, when
- instantiating LANG_HOOKS_ATTRIBUTE_TABLE.
- (LANG_HOOKS_ATTRIBUTE_TABLE): Define to be empty by default.
- * target.def (attribute_table): Likewise.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112860
- * passes.cc (should_skip_pass_p): Do not skip ISEL.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR sanitizer/111736
- * asan.cc (asan_protect_global): Do not protect globals
- in non-generic address-space.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR ipa/92606
- * ipa-icf.cc (sem_variable::equals_wpa): Compare address-spaces.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112830
- * gimplify.cc (gimplify_modify_expr): Avoid turning aggregate
- copy of non-generic address-spaces to memcpy.
- (gimplify_modify_expr_to_memcpy): Assert we are dealing with
- a copy inside the generic address-space.
- (gimplify_modify_expr_to_memset): Likewise.
- * tree-cfg.cc (verify_gimple_assign_single): Allow
- WITH_SIZE_EXPR as part of the RHS of an assignment.
- * builtins.cc (get_memory_address): Assert we are dealing
- with the generic address-space.
- * tree-ssa-dce.cc (ref_may_be_aliased): Handle WITH_SIZE_EXPR.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109689
- PR tree-optimization/112856
- * cfgloopmanip.h (unloop_loops): Adjust API.
- * tree-ssa-loop-ivcanon.cc (unloop_loops): Take edges_to_remove
- as parameter.
- (canonicalize_induction_variables): Adjust.
- (tree_unroll_loops_completely): Likewise.
- * tree-ssa-loop-ch.cc (ch_base::copy_headers): Rewrite into
- LC SSA if we unlooped some loops and we are in LC SSA.
-
-2023-12-05 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112845
- * config/i386/i386.md (movabsq $(i32 << shift), r64 peephole2): FAIL
- if the new immediate is ix86_endbr_immediate_operand.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (TARGET_STREAMING_SME2): New macro.
- (P_ALIASES): Likewise.
- (REGISTER_NAMES): Add pn aliases of the predicate registers.
- (W8_W11_REGNUM_P): New macro.
- (W8_W11_REGS): New register class.
- (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
- * config/aarch64/aarch64.cc (aarch64_print_operand): Add support
- for %K, which prints a predicate as a counter. Handle tuples of
- predicates.
- (aarch64_regno_regclass): Handle W8_W11_REGS.
- (aarch64_class_max_nregs): Likewise.
- * config/aarch64/constraints.md (Uci, Uw2, Uw4): New constraints.
- (x, y): Move further up file.
- (Uph): Redefine as the high predicate registers, renaming the old
- constraint to...
- (Uih): ...this.
- * config/aarch64/predicates.md (const_0_to_7_operand): New predicate.
- (const_0_to_4_step_4_operand, const_0_to_6_step_2_operand): Likewise.
- (const_0_to_12_step_4_operand, const_0_to_14_step_2_operand): Likewise.
- (aarch64_simd_shift_imm_qi): Use const_0_to_7_operand.
- * config/aarch64/iterators.md (VNx16SI_ONLY, VNx8SI_ONLY)
- (VNx8DI_ONLY, SVE_FULL_BHSIx2, SVE_FULL_HF, SVE_FULL_SIx2_SDIx4)
- (SVE_FULL_BHS, SVE_FULLx24, SVE_DIx24, SVE_BHSx24, SVE_Ix24)
- (SVE_Fx24, SVE_SFx24, SME_ZA_BIx24, SME_ZA_BHIx124, SME_ZA_BHIx24)
- (SME_ZA_HFx124, SME_ZA_HFx24, SME_ZA_HIx124, SME_ZA_HIx24)
- (SME_ZA_SDIx24, SME_ZA_SDFx24): New mode iterators.
- (UNSPEC_REVD, UNSPEC_CNTP_C, UNSPEC_PEXT, UNSPEC_PEXTx2): New unspecs.
- (UNSPEC_PSEL, UNSPEC_PTRUE_C, UNSPEC_SQRSHR, UNSPEC_SQRSHRN)
- (UNSPEC_SQRSHRU, UNSPEC_SQRSHRUN, UNSPEC_UQRSHR, UNSPEC_UQRSHRN)
- (UNSPEC_UZP, UNSPEC_UZPQ, UNSPEC_ZIP, UNSPEC_ZIPQ, UNSPEC_BFMLSLB)
- (UNSPEC_BFMLSLT, UNSPEC_FCVTN, UNSPEC_FDOT, UNSPEC_SQCVT): Likewise.
- (UNSPEC_SQCVTN, UNSPEC_SQCVTU, UNSPEC_SQCVTUN, UNSPEC_UQCVT): Likewise.
- (UNSPEC_SME_ADD, UNSPEC_SME_ADD_WRITE, UNSPEC_SME_BMOPA): Likewise.
- (UNSPEC_SME_BMOPS, UNSPEC_SME_FADD, UNSPEC_SME_FDOT, UNSPEC_SME_FVDOT)
- (UNSPEC_SME_FMLA, UNSPEC_SME_FMLS, UNSPEC_SME_FSUB, UNSPEC_SME_READ)
- (UNSPEC_SME_SDOT, UNSPEC_SME_SVDOT, UNSPEC_SME_SMLA, UNSPEC_SME_SMLS)
- (UNSPEC_SME_SUB, UNSPEC_SME_SUB_WRITE, UNSPEC_SME_SUDOT): Likewise.
- (UNSPEC_SME_SUVDOT, UNSPEC_SME_UDOT, UNSPEC_SME_UVDOT): Likewise.
- (UNSPEC_SME_UMLA, UNSPEC_SME_UMLS, UNSPEC_SME_USDOT): Likewise.
- (UNSPEC_SME_USVDOT, UNSPEC_SME_WRITE): Likewise.
- (Vetype, VNARROW, V2XWIDE, Ventype, V_INT_EQUIV, v_int_equiv)
- (VSINGLE, vsingle, b): Add tuple modes.
- (v2xwide, za32_offset_range, za64_offset_range, za32_long)
- (za32_last_offset, vg_modifier, z_suffix, aligned_operand)
- (aligned_fpr): New mode attributes.
- (SVE_INT_BINARY_MULTI, SVE_INT_BINARY_SINGLE, SVE_INT_BINARY_MULTI)
- (SVE_FP_BINARY_MULTI): New int iterators.
- (SVE_BFLOAT_TERNARY_LONG): Add UNSPEC_BFMLSLB and UNSPEC_BFMLSLT.
- (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
- (SVE_WHILE_ORDER, SVE2_INT_SHIFT_IMM_NARROWxN, SVE_QCVTxN)
- (SVE2_SFx24_UNARY, SVE2_x24_PERMUTE, SVE2_x24_PERMUTEQ)
- (UNSPEC_REVD_ONLY, SME2_INT_MOP, SME2_BMOP, SME_BINARY_SLICE_SDI)
- (SME_BINARY_SLICE_SDF, SME_BINARY_WRITE_SLICE_SDI, SME_INT_DOTPROD)
- (SME_INT_DOTPROD_LANE, SME_FP_DOTPROD, SME_FP_DOTPROD_LANE)
- (SME_INT_TERNARY_SLICE, SME_FP_TERNARY_SLICE, BHSD_BITS)
- (LUTI_BITS): New int iterators.
- (optab, sve_int_op): Handle the new unspecs.
- (sme_int_op, has_16bit_form): New int attributes.
- (bits_etype): Handle 64.
- * config/aarch64/aarch64.md (UNSPEC_LD1_SVE_COUNT): New unspec.
- (UNSPEC_ST1_SVE_COUNT, UNSPEC_LDNT1_SVE_COUNT): Likewise.
- (UNSPEC_STNT1_SVE_COUNT): Likewise.
- * config/aarch64/atomics.md (cas_short_expected_imm): Use Uhi
- rather than Uph for HImode immediates.
- * config/aarch64/aarch64-sve.md (@aarch64_ld1<SVE_FULLx24:mode>)
- (@aarch64_ldnt1<SVE_FULLx24:mode>, @aarch64_st1<SVE_FULLx24:mode>)
- (@aarch64_stnt1<SVE_FULLx24:mode>): New patterns.
- (@aarch64_<sur>dot_prod_lane<vsi2qi>): Extend to...
- (@aarch64_<sur>dot_prod_lane<SVE_FULL_SDI:mode><SVE_FULL_BHI:mode>)
- (@aarch64_<sur>dot_prod_lane<VNx4SI_ONLY:mode><VNx16QI_ONLY:mode>):
- ...these new patterns.
- (SVE_WHILE_B, SVE_WHILE_B_X2, SVE_WHILE_C): New constants. Add
- SVE_WHILE_B to existing while patterns.
- * config/aarch64/aarch64-sve2.md (@aarch64_sve_ptrue_c<BHSD_BITS>)
- (@aarch64_sve_pext<BHSD_BITS>, @aarch64_sve_pext<BHSD_BITS>x2)
- (@aarch64_sve_psel<BHSD_BITS>, *aarch64_sve_psel<BHSD_BITS>_plus)
- (@aarch64_sve_cntp_c<BHSD_BITS>, <frint_pattern><mode>2)
- (<optab><mode>3, *<optab><mode>3, @aarch64_sve_single_<optab><mode>)
- (@aarch64_sve_<sve_int_op><mode>): New patterns.
- (@aarch64_sve_single_<sve_int_op><mode>, @aarch64_sve_<su>clamp<mode>)
- (*aarch64_sve_<su>clamp<mode>_x, @aarch64_sve_<su>clamp_single<mode>)
- (@aarch64_sve_fclamp<mode>, *aarch64_sve_fclamp<mode>_x)
- (@aarch64_sve_fclamp_single<mode>, <optab><mode><v2xwide>2)
- (@aarch64_sve_<sur>dotvnx4sivnx8hi): New patterns.
- (@aarch64_sve_<maxmin_uns_op><mode>): Likewise.
- (*aarch64_sve_<maxmin_uns_op><mode>): Likewise.
- (@aarch64_sve_single_<maxmin_uns_op><mode>): Likewise.
- (aarch64_sve_fdotvnx4sfvnx8hf): Likewise.
- (aarch64_fdot_prod_lanevnx4sfvnx8hf): Likewise.
- (@aarch64_sve_<optab><VNx16QI_ONLY:mode><VNx16SI_ONLY:mode>): Likewise.
- (@aarch64_sve_<optab><VNx8HI_ONLY:mode><VNx8SI_ONLY:mode>): Likewise.
- (@aarch64_sve_<optab><VNx8HI_ONLY:mode><VNx8DI_ONLY:mode>): Likewise.
- (truncvnx8sf<mode>2, @aarch64_sve_cvtn<mode>): Likewise.
- (<optab><v_int_equiv><mode>2, <optab><mode><v_int_equiv>2): Likewise.
- (@aarch64_sve_sel<mode>): Likewise.
- (@aarch64_sve_while<while_optab_cmp>_b<BHSD_BITS>_x2): Likewise.
- (@aarch64_sve_while<while_optab_cmp>_c<BHSD_BITS>): Likewise.
- (@aarch64_pred_<optab><mode>, @cond_<optab><mode>): Likewise.
- (@aarch64_sve_<optab><mode>): Likewise.
- * config/aarch64/aarch64-sme.md (@aarch64_sme_<optab><mode><mode>)
- (*aarch64_sme_<optab><mode><mode>_plus, @aarch64_sme_read<mode>)
- (*aarch64_sme_read<mode>_plus, @aarch64_sme_write<mode>): New patterns.
- (*aarch64_sme_write<mode>_plus aarch64_sme_zero_zt0): Likewise.
- (@aarch64_sme_<optab><mode>, *aarch64_sme_<optab><mode>_plus)
- (@aarch64_sme_single_<optab><mode>): Likewise.
- (*aarch64_sme_single_<optab><mode>_plus): Likewise.
- (@aarch64_sme_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_single_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_single_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_single_sudot<VNx4SI_ONLY:mode><SME_ZA_BIx24:mode>)
- (*aarch64_sme_single_sudot<VNx4SI_ONLY:mode><SME_ZA_BIx24:mode>_plus)
- (@aarch64_sme_lane_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_lane_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_BHI:mode>)
- (*aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_BHI:mode>_plus)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx124:mode>)
- (*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx124:mode>)
- (@aarch64_sme_<optab><VNx2DI_ONLY:mode><VNx8HI_ONLY:mode>)
- (*aarch64_sme_<optab><VNx2DI_ONLY:mode><VNx8HI_ONLY:mode>_plus)
- (@aarch64_sme_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx24:mode>)
- (*aarch64_sme_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx24:mode>_plus)
- (@aarch64_sme_single_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx24:mode>)
- (*aarch64_sme_single_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx24:mode>_plus)
- (@aarch64_sme_lane_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx124:mode>)
- (*aarch64_sme_lane_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx124:mode>)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><VNx8HI_ONLY:mode>)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><VNx4SI_ONLY:mode>)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>)
- (*aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>_plus)
- (@aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>)
- (*aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>_plus)
- (@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>)
- (*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>_plus)
- (@aarch64_sme_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>)
- (*aarch64_sme_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>_plus)
- (@aarch64_sme_single_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>)
- (*aarch64_sme_single_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>_plus)
- (@aarch64_sme_lane_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>)
- (*aarch64_sme_lane_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>)
- (*aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>_plus)
- (@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx124:mode>)
- (*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx124:mode>)
- (@aarch64_sme_lut<LUTI_BITS><mode>): Likewise.
- (UNSPEC_SME_LUTI): New unspec.
- * config/aarch64/aarch64-sve-builtins.def (single): New mode suffix.
- (c8, c16, c32, c64): New type suffixes.
- (vg1x2, vg1x4, vg2, vg2x1, vg2x2, vg2x4, vg4, vg4x1, vg4x2)
- (vg4x4): New group suffixes.
- * config/aarch64/aarch64-sve-builtins.h (CP_READ_ZT0)
- (CP_WRITE_ZT0): New constants.
- (get_svbool_t): Delete.
- (function_resolver::report_mismatched_num_vectors): New member
- function.
- (function_resolver::resolve_conversion): Likewise.
- (function_resolver::infer_predicate_type): Likewise.
- (function_resolver::infer_64bit_scalar_integer_pair): Likewise.
- (function_resolver::require_matching_predicate_type): Likewise.
- (function_resolver::require_nonscalar_type): Likewise.
- (function_resolver::finish_opt_single_resolution): Likewise.
- (function_resolver::require_derived_vector_type): Add an
- expected_num_vectors parameter.
- (function_expander::map_to_rtx_codes): Add an extra parameter
- for unconditional FP unspecs.
- (function_instance::gp_type_index): New member function.
- (function_instance::gp_type): Likewise.
- (function_instance::gp_mode): Handle multi-vector operations.
- * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_count)
- (TYPES_all_pred_count, TYPES_c, TYPES_bhs_data, TYPES_bhs_widen)
- (TYPES_hs_data, TYPES_cvt_h_s_float, TYPES_cvt_s_s, TYPES_qcvt_x2)
- (TYPES_qcvt_x4, TYPES_qrshr_x2, TYPES_qrshru_x2, TYPES_qrshr_x4)
- (TYPES_qrshru_x4, TYPES_while_x, TYPES_while_x_c, TYPES_s_narrow_fsu)
- (TYPES_za_s_b_signed, TYPES_za_s_b_unsigned, TYPES_za_s_b_integer)
- (TYPES_za_s_h_integer, TYPES_za_s_h_data, TYPES_za_s_unsigned)
- (TYPES_za_s_float, TYPES_za_s_data, TYPES_za_d_h_integer): New type
- macros.
- (groups_x2, groups_x12, groups_x4, groups_x24, groups_x124)
- (groups_vg1x2, groups_vg1x4, groups_vg1x24, groups_vg2, groups_vg4)
- (groups_vg24): New group arrays.
- (function_instance::reads_global_state_p): Handle CP_READ_ZT0.
- (function_instance::modifies_global_state_p): Handle CP_WRITE_ZT0.
- (add_shared_state_attribute): Handle zt0 state.
- (function_builder::add_overloaded_functions): Skip MODE_single
- for non-tuple groups.
- (function_resolver::report_mismatched_num_vectors): New function.
- (function_resolver::resolve_to): Add a fallback error message for
- the general two-type case.
- (function_resolver::resolve_conversion): New function.
- (function_resolver::infer_predicate_type): Likewise.
- (function_resolver::infer_64bit_scalar_integer_pair): Likewise.
- (function_resolver::require_matching_predicate_type): Likewise.
- (function_resolver::require_matching_vector_type): Specifically
- diagnose mismatched vector counts.
- (function_resolver::require_derived_vector_type): Add an
- expected_num_vectors parameter. Extend to handle cases where
- tuples are expected.
- (function_resolver::require_nonscalar_type): New function.
- (function_resolver::check_gp_argument): Use gp_type_index rather
- than hard-coding VECTOR_TYPE_svbool_t.
- (function_resolver::finish_opt_single_resolution): New function.
- (function_checker::require_immediate_either_or): Remove hard-coded
- constants.
- (function_expander::direct_optab_handler): New function.
- (function_expander::use_pred_x_insn): Only add a strictness flag
- is the insn has an operand for it.
- (function_expander::map_to_rtx_codes): Take an unconditional
- FP unspec as an extra parameter. Handle tuples and MODE_single.
- (function_expander::map_to_unspecs): Handle tuples and MODE_single.
- * config/aarch64/aarch64-sve-builtins-functions.h (read_zt0)
- (write_zt0): New typedefs.
- (full_width_access::memory_vector): Use the function's
- vectors_per_tuple.
- (rtx_code_function_base): Add an optional unconditional FP unspec.
- (rtx_code_function::expand): Update accordingly.
- (rtx_code_function_rotated::expand): Likewise.
- (unspec_based_function_exact_insn::expand): Use tuple_mode instead
- of vector_mode.
- (unspec_based_uncond_function): New typedef.
- (cond_or_uncond_unspec_function): New class.
- (sme_1mode_function::expand): Handle single forms.
- (sme_2mode_function_t): Likewise, adding a template parameter for them.
- (sme_2mode_function): Update accordingly.
- (sme_2mode_lane_function): New typedef.
- (multireg_permute): New class.
- (class integer_conversion): Likewise.
- (while_comparison::expand): Handle svcount_t and svboolx2_t results.
- * config/aarch64/aarch64-sve-builtins-shapes.h
- (binary_int_opt_single_n, binary_opt_single_n, binary_single)
- (binary_za_slice_lane, binary_za_slice_int_opt_single)
- (binary_za_slice_opt_single, binary_za_slice_uint_opt_single)
- (binaryx, clamp, compare_scalar_count, count_pred_c)
- (dot_za_slice_int_lane, dot_za_slice_lane, dot_za_slice_uint_lane)
- (extract_pred, inherent_zt, ldr_zt, read_za, read_za_slice)
- (select_pred, shift_right_imm_narrowxn, storexn, str_zt)
- (unary_convertxn, unary_za_slice, unaryxn, write_za)
- (write_za_slice): Declare.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (za_group_is_pure_overload): New function.
- (apply_predication): Use the function's gp_type for the predicate,
- instead of hard-coding the use of svbool_t.
- (parse_element_type): Add support for "c" (svcount_t).
- (parse_type): Add support for "c0" and "c1" (conversion destination
- and source types).
- (binary_za_slice_lane_base): New class.
- (binary_za_slice_opt_single_base): Likewise.
- (load_contiguous_base::resolve): Pass the group suffix to r.resolve.
- (luti_lane_zt_base): New class.
- (binary_int_opt_single_n, binary_opt_single_n, binary_single)
- (binary_za_slice_lane, binary_za_slice_int_opt_single)
- (binary_za_slice_opt_single, binary_za_slice_uint_opt_single)
- (binaryx, clamp): New shapes.
- (compare_scalar_def::build): Allow the return type to be a tuple.
- (compare_scalar_def::expand): Pass the group suffix to r.resolve.
- (compare_scalar_count, count_pred_c, dot_za_slice_int_lane)
- (dot_za_slice_lane, dot_za_slice_uint_lane, extract_pred, inherent_zt)
- (ldr_zt, read_za, read_za_slice, select_pred, shift_right_imm_narrowxn)
- (storexn, str_zt): New shapes.
- (ternary_qq_lane_def, ternary_qq_opt_n_def): Replace with...
- (ternary_qq_or_011_lane_def, ternary_qq_opt_n_or_011_def): ...these
- new classes. Allow a second suffix that specifies the type of the
- second vector argument, and that is used to derive the third.
- (unary_def::build): Extend to handle tuple types.
- (unary_convert_def::build): Use the new c0 and c1 format specifiers.
- (unary_convertxn, unary_za_slice, unaryxn, write_za): New shapes.
- (write_za_slice): Likewise.
- * config/aarch64/aarch64-sve-builtins-base.cc (svbic_impl::expand)
- (svext_bhw_impl::expand): Update call to map_to_rtx_costs.
- (svcntp_impl::expand): Handle svcount_t variants.
- (svcvt_impl::expand): Handle unpredicated conversions separately,
- dealing with tuples.
- (svdot_impl::expand): Handle 2-way dot products.
- (svdotprod_lane_impl::expand): Likewise.
- (svld1_impl::fold): Punt on tuple loads.
- (svld1_impl::expand): Handle tuple loads.
- (svldnt1_impl::expand): Likewise.
- (svpfalse_impl::fold): Punt on svcount_t forms.
- (svptrue_impl::fold): Likewise.
- (svptrue_impl::expand): Handle svcount_t forms.
- (svrint_impl): New class.
- (svsel_impl::fold): Punt on tuple forms.
- (svsel_impl::expand): Handle tuple forms.
- (svst1_impl::fold): Punt on tuple loads.
- (svst1_impl::expand): Handle tuple loads.
- (svstnt1_impl::expand): Likewise.
- (svwhilelx_impl::fold): Punt on tuple forms.
- (svdot_lane): Use UNSPEC_FDOT.
- (svmax, svmaxnm, svmin, svminmm): Add unconditional FP unspecs.
- (rinta, rinti, rintm, rintn, rintp, rintx, rintz): Use svrint_impl.
- * config/aarch64/aarch64-sve-builtins-base.def (svcreate2, svget2)
- (svset2, svundef2): Add _b variants.
- (svcvt): Use unary_convertxn.
- (svdot): Use ternary_qq_opt_n_or_011.
- (svdot_lane): Use ternary_qq_or_011_lane.
- (svmax, svmaxnm, svmin, svminnm): Use binary_opt_single_n.
- (svpfalse): Add a form that returns svcount_t results.
- (svrinta, svrintm, svrintn, svrintp): Use unaryxn.
- (svsel): Use binaryxn.
- (svst1, svstnt1): Use storexn.
- * config/aarch64/aarch64-sve-builtins-sme.h
- (svadd_za, svadd_write_za, svbmopa_za, svbmops_za, svdot_za)
- (svdot_lane_za, svldr_zt, svluti2_lane_zt, svluti4_lane_zt)
- (svmla_za, svmla_lane_za, svmls_za, svmls_lane_za, svread_za)
- (svstr_zt, svsub_za, svsub_write_za, svsudot_za, svsudot_lane_za)
- (svsuvdot_lane_za, svusdot_za, svusdot_lane_za, svusvdot_lane_za)
- (svvdot_lane_za, svwrite_za, svzero_zt): Declare.
- * config/aarch64/aarch64-sve-builtins-sme.cc (load_store_za_base):
- Rename to...
- (load_store_za_zt0_base): ...this and extend to tuples.
- (load_za_base, store_za_base): Update accordingly.
- (expand_ldr_str_zt0): New function.
- (svldr_zt_impl, svluti_lane_zt_impl, svread_za_impl, svstr_zt_impl)
- (svsudot_za_impl, svwrite_za_impl, svzero_zt_impl): New classes.
- (svadd_za, svadd_write_za, svbmopa_za, svbmops_za, svdot_za)
- (svdot_lane_za, svldr_zt, svluti2_lane_zt, svluti4_lane_zt)
- (svmla_za, svmla_lane_za, svmls_za, svmls_lane_za, svread_za)
- (svstr_zt, svsub_za, svsub_write_za, svsudot_za, svsudot_lane_za)
- (svsuvdot_lane_za, svusdot_za, svusdot_lane_za, svusvdot_lane_za)
- (svvdot_lane_za, svwrite_za, svzero_zt): New functions.
- * config/aarch64/aarch64-sve-builtins-sme.def: Add SME2 intrinsics.
- * config/aarch64/aarch64-sve-builtins-sve2.h
- (svbfmlslb, svbfmlslb_lane, svbfmlslt, svbfmlslt_lane, svclamp)
- (svcvtn, svpext, svpsel, svqcvt, svqcvtn, svqrshr, svqrshrn)
- (svqrshru, svqrshrun, svrevd, svunpk, svuzp, svuzpq, svzip)
- (svzipq): Declare.
- * config/aarch64/aarch64-sve-builtins-sve2.cc (svclamp_impl)
- (svcvtn_impl, svpext_impl, svpsel_impl): New classes.
- (svqrshl_impl::fold): Update for change to svrshl shape.
- (svrshl_impl::fold): Punt on tuple forms.
- (svsqadd_impl::expand): Update call to map_to_rtx_codes.
- (svunpk_impl): New class.
- (svbfmlslb, svbfmlslb_lane, svbfmlslt, svbfmlslt_lane, svclamp)
- (svcvtn, svpext, svpsel, svqcvt, svqcvtn, svqrshr, svqrshrn)
- (svqrshru, svqrshrun, svrevd, svunpk, svuzp, svuzpq, svzip)
- (svzipq): New functions.
- * config/aarch64/aarch64-sve-builtins-sve2.def: Add SME2 intrinsics.
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
- or undefine __ARM_FEATURE_SME2.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.md (ZT0_REGNUM): New constant.
- (LAST_FAKE_REGNUM): Bump to include it.
- * config/aarch64/aarch64.h (FIXED_REGISTERS): Add an entry for ZT0.
- (CALL_REALLY_USED_REGISTERS, REGISTER_NAMES): Likewise.
- (REG_CLASS_CONTENTS): Likewise.
- (machine_function): Add zt0_save_buffer.
- (CUMULATIVE_ARGS): Add shared_zt0_flags;
- * config/aarch64/aarch64.cc (aarch64_check_state_string): Handle zt0.
- (aarch64_fntype_pstate_za, aarch64_fndecl_pstate_za): Likewise.
- (aarch64_function_arg): Add the shared ZT0 flags as an extra
- limb of the parallel.
- (aarch64_init_cumulative_args): Initialize shared_zt0_flags.
- (aarch64_extra_live_on_entry): Handle ZT0_REGNUM.
- (aarch64_epilogue_uses): Likewise.
- (aarch64_get_zt0_save_buffer, aarch64_save_zt0): New functions.
- (aarch64_restore_zt0): Likewise.
- (aarch64_start_call_args): Reject calls to functions that share
- ZT0 from functions that have no ZT0 state. Save ZT0 around shared-ZA
- calls that do not share ZT0.
- (aarch64_expand_call): Handle ZT0. Reject calls to functions that
- share ZT0 but not ZA from functions with ZA state.
- (aarch64_end_call_args): Restore ZT0 after calls to shared-ZA functions
- that do not share ZT0.
- (aarch64_set_current_function): Require +sme2 for functions that
- have ZT0 state.
- (aarch64_function_attribute_inlinable_p): Don't allow functions to
- be inlined if they have local zt0 state.
- (AARCH64_IPA_CLOBBERS_ZT0): New constant.
- (aarch64_update_ipa_fn_target_info): Record asms that clobber ZT0.
- (aarch64_can_inline_p): Don't inline callees that clobber ZT0
- into functions that have ZT0 state.
- (aarch64_comp_type_attributes): Check for compatible ZT0 sharing.
- (aarch64_optimize_mode_switching): Use mode switching if the
- function has ZT0 state.
- (aarch64_mode_emit_local_sme_state): Save and restore ZT0 around
- calls to private-ZA functions.
- (aarch64_mode_needed_local_sme_state): Require ZA to be active
- for instructions that access ZT0.
- (aarch64_mode_entry): Mark ZA as dead on entry if the function
- only shares state other than "za" itself.
- (aarch64_mode_exit): Likewise mark ZA as dead on return.
- (aarch64_md_asm_adjust): Extend handling of ZA clobbers to ZT0.
- * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
- Define __ARM_STATE_ZT0.
- * config/aarch64/aarch64-sme.md (UNSPECV_ASM_UPDATE_ZT0): New unspecv.
- (aarch64_asm_update_zt0): New insn.
- (UNSPEC_RESTORE_ZT0): New unspec.
- (aarch64_sme_ldr_zt0, aarch64_restore_zt0): New insns.
- (aarch64_sme_str_zt0): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-modes.def (VNx32BI): New mode.
- * config/aarch64/aarch64-protos.h (aarch64_split_double_move): Declare.
- * config/aarch64/aarch64-sve-builtins.cc
- (register_tuple_type): Handle tuples of predicates.
- (handle_arm_sve_h): Define svboolx2_t as a pair of two svbool_ts.
- * config/aarch64/aarch64-sve.md (movvnx32bi): New insn.
- * config/aarch64/aarch64.cc
- (pure_scalable_type_info::piece::get_rtx): Use VNx32BI for pairs
- of predicates.
- (pure_scalable_type_info::add_piece): Don't try to form pairs of
- predicates.
- (VEC_STRUCT): Generalize comment.
- (aarch64_classify_vector_mode): Handle VNx32BI.
- (aarch64_array_mode): Likewise. Return BLKmode for arrays of
- predicates that have no associated mode, rather than allowing
- an integer mode to be chosen.
- (aarch64_hard_regno_nregs): Handle VNx32BI.
- (aarch64_hard_regno_mode_ok): Likewise.
- (aarch64_split_double_move): New function, split out from...
- (aarch64_split_128bit_move): ...here.
- (aarch64_ptrue_reg): Tighten assert to aarch64_sve_pred_mode_p.
- (aarch64_pfalse_reg): Likewise.
- (aarch64_sve_same_pred_for_ptest_p): Likewise.
- (aarch64_sme_mode_switch_regs::add_reg): Handle VNx32BI.
- (aarch64_expand_mov_immediate): Restrict handling of boolean vector
- constants to single-predicate modes.
- (aarch64_classify_address): Handle VNx32BI, ensuring that both halves
- can be addressed.
- (aarch64_class_max_nregs): Handle VNx32BI.
- (aarch64_member_type_forces_blk): Don't for BLKmode for svboolx2_t.
- (aarch64_simd_valid_immediate): Allow all-zeros and all-ones for
- VNx32BI.
- (aarch64_mov_operand_p): Restrict predicate constant canonicalization
- to single-predicate modes.
- (aarch64_evpc_ext): Generalize exclusion to all predicate modes.
- (aarch64_evpc_rev_local, aarch64_evpc_dup): Likewise.
- * config/aarch64/constraints.md (PR_REGS): New predicate.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svreinterpret_impl::fold): Handle reinterprets between svbool_t
- and svcount_t.
- (svreinterpret_impl::expand): Likewise.
- * config/aarch64/aarch64-sve-builtins-base.def (svreinterpret): Add
- b<->c forms.
- * config/aarch64/aarch64-sve-builtins.cc (TYPES_reinterpret_b): New
- type suffix list.
- (wrap_type_in_struct, register_type_decl): New functions, split out
- from...
- (register_tuple_type): ...here.
- (register_builtin_types): Handle svcount_t.
- (handle_arm_sve_h): Don't create tuples of svcount_t.
- * config/aarch64/aarch64-sve-builtins.def (svcount_t): New type.
- (c): New type suffix.
- * config/aarch64/aarch64-sve-builtins.h (TYPE_count): New type class.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/invoke.texi: Document +sme2.
- * doc/sourcebuild.texi: Document aarch64_sme2.
- * config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION):
- Add sme2.
- * config/aarch64/aarch64.h (AARCH64_ISA_SME2, TARGET_SME2): New macros.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
- Enforce PSTATE.SM and PSTATE.ZA restrictions.
- (aarch64_expand_epilogue): Save and restore the arguments
- to a sibcall around any change to PSTATE.SM.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc: Include symbol-summary.h, ipa-prop.h,
- and ipa-fnsummary.h
- (aarch64_function_attribute_inlinable_p): New function.
- (AARCH64_IPA_SM_FIXED, AARCH64_IPA_CLOBBERS_ZA): New constants.
- (aarch64_need_ipa_fn_target_info): New function.
- (aarch64_update_ipa_fn_target_info): Likewise.
- (aarch64_can_inline_p): Restrict the previous ISA flag checks
- to non-modal features. Prevent callees that require a particular
- PSTATE.SM state from being inlined into callers that can't guarantee
- that state. Also prevent callees that have ZA state from being
- inlined into callers that don't. Finally, prevent callees that
- clobber ZA from being inlined into callers that have ZA state.
- (TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P): Define.
- (TARGET_NEED_IPA_FN_TARGET_INFO): Likewise.
- (TARGET_UPDATE_IPA_FN_TARGET_INFO): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc: Include except.h
- (aarch64_sme_mode_switch_regs::add_call_preserved_reg): New function.
- (aarch64_sme_mode_switch_regs::add_call_preserved_regs): Likewise.
- (aarch64_need_old_pstate_sm): Return true if the function has
- a nonlocal-goto or exception receiver.
- (aarch64_switch_pstate_sm_for_landing_pad): New function.
- (aarch64_switch_pstate_sm_for_jump): Likewise.
- (pass_switch_pstate_sm::gate): Enable the pass for all
- streaming and streaming-compatible functions.
- (pass_switch_pstate_sm::execute): Handle non-local gotos and their
- receivers. Handle exception handler entry points.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_arm_attribute_table): Add
- arm::locally_streaming.
- (aarch64_fndecl_is_locally_streaming): New function.
- (aarch64_fndecl_sm_state): Handle locally-streaming functions.
- (aarch64_cfun_enables_pstate_sm): New function.
- (aarch64_add_offset): Add an argument that specifies whether
- the streaming vector length should be used instead of the
- prevailing one.
- (aarch64_split_add_offset, aarch64_add_sp, aarch64_sub_sp): Likewise.
- (aarch64_allocate_and_probe_stack_space): Likewise.
- (aarch64_expand_mov_immediate): Update calls accordingly.
- (aarch64_need_old_pstate_sm): Return true for locally-streaming
- streaming-compatible functions.
- (aarch64_layout_frame): Force all call-preserved Z and P registers
- to be saved and restored if the function switches PSTATE.SM in the
- prologue.
- (aarch64_get_separate_components): Disable shrink-wrapping of
- such Z and P saves and restores.
- (aarch64_use_late_prologue_epilogue): New function.
- (aarch64_expand_prologue): Measure SVE lengths in the streaming
- vector length for locally-streaming functions, then emit code
- to enable streaming mode.
- (aarch64_expand_epilogue): Likewise in reverse.
- (TARGET_USE_LATE_PROLOGUE_EPILOGUE): Define.
- * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
- Define __arm_locally_streaming.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/invoke.texi: Document +sme-i16i64 and +sme-f64f64.
- * config.gcc (aarch64*-*-*): Add arm_sme.h to the list of headers
- to install and aarch64-sve-builtins-sme.o to the list of objects
- to build.
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
- or undefine TARGET_SME, TARGET_SME_I16I64 and TARGET_SME_F64F64.
- (aarch64_pragma_aarch64): Handle arm_sme.h.
- * config/aarch64/aarch64-option-extensions.def (sme-i16i64)
- (sme-f64f64): New extensions.
- * config/aarch64/aarch64-protos.h (aarch64_sme_vq_immediate)
- (aarch64_addsvl_addspl_immediate_p, aarch64_output_addsvl_addspl)
- (aarch64_output_sme_zero_za): Declare.
- (aarch64_output_move_struct): Delete.
- (aarch64_sme_ldr_vnum_offset): Declare.
- (aarch64_sve::handle_arm_sme_h): Likewise.
- * config/aarch64/aarch64.h (AARCH64_ISA_SM_ON): New macro.
- (AARCH64_ISA_SME_I16I64, AARCH64_ISA_SME_F64F64): Likewise.
- (TARGET_STREAMING, TARGET_STREAMING_SME): Likewise.
- (TARGET_SME_I16I64, TARGET_SME_F64F64): Likewise.
- * config/aarch64/aarch64.cc (aarch64_sve_rdvl_factor_p): Rename to...
- (aarch64_sve_rdvl_addvl_factor_p): ...this.
- (aarch64_sve_rdvl_immediate_p): Update accordingly.
- (aarch64_rdsvl_immediate_p, aarch64_add_offset): Likewise.
- (aarch64_sme_vq_immediate): Likewise. Make public.
- (aarch64_sve_addpl_factor_p): New function.
- (aarch64_sve_addvl_addpl_immediate_p): Use
- aarch64_sve_rdvl_addvl_factor_p and aarch64_sve_addpl_factor_p.
- (aarch64_addsvl_addspl_immediate_p): New function.
- (aarch64_output_addsvl_addspl): Likewise.
- (aarch64_cannot_force_const_mem): Return true for RDSVL immediates.
- (aarch64_classify_index): Handle .Q scaling for VNx1TImode.
- (aarch64_classify_address): Likewise for vnum offsets.
- (aarch64_output_sme_zero_za): New function.
- (aarch64_sme_ldr_vnum_offset_p): Likewise.
- * config/aarch64/predicates.md (aarch64_addsvl_addspl_immediate):
- New predicate.
- (aarch64_pluslong_operand): Include it for SME.
- * config/aarch64/constraints.md (Ucj, Uav): New constraints.
- * config/aarch64/iterators.md (VNx1TI_ONLY): New mode iterator.
- (SME_ZA_I, SME_ZA_SDI, SME_ZA_SDF_I, SME_MOP_BHI): Likewise.
- (SME_MOP_HSDF): Likewise.
- (UNSPEC_SME_ADDHA, UNSPEC_SME_ADDVA, UNSPEC_SME_FMOPA)
- (UNSPEC_SME_FMOPS, UNSPEC_SME_LD1_HOR, UNSPEC_SME_LD1_VER)
- (UNSPEC_SME_READ_HOR, UNSPEC_SME_READ_VER, UNSPEC_SME_SMOPA)
- (UNSPEC_SME_SMOPS, UNSPEC_SME_ST1_HOR, UNSPEC_SME_ST1_VER)
- (UNSPEC_SME_SUMOPA, UNSPEC_SME_SUMOPS, UNSPEC_SME_UMOPA)
- (UNSPEC_SME_UMOPS, UNSPEC_SME_USMOPA, UNSPEC_SME_USMOPS)
- (UNSPEC_SME_WRITE_HOR, UNSPEC_SME_WRITE_VER): New unspecs.
- (elem_bits): Handle x2 and x4 structure modes, plus VNx1TI.
- (Vetype, Vesize, VPRED): Handle VNx1TI.
- (b): New mode attribute.
- (SME_LD1, SME_READ, SME_ST1, SME_WRITE, SME_BINARY_SDI, SME_INT_MOP)
- (SME_FP_MOP): New int iterators.
- (optab): Handle SME unspecs.
- (hv): New int attribute.
- * config/aarch64/aarch64.md (*add<mode>3_aarch64): Handle ADDSVL
- and ADDSPL.
- * config/aarch64/aarch64-sme.md (UNSPEC_SME_LDR): New unspec.
- (@aarch64_sme_<optab><mode>, @aarch64_sme_<optab><mode>_plus)
- (aarch64_sme_ldr0, @aarch64_sme_ldrn<mode>): New patterns.
- (UNSPEC_SME_STR): New unspec.
- (@aarch64_sme_<optab><mode>, @aarch64_sme_<optab><mode>_plus)
- (aarch64_sme_str0, @aarch64_sme_strn<mode>): New patterns.
- (@aarch64_sme_<optab><v_int_container><mode>): Likewise.
- (*aarch64_sme_<optab><v_int_container><mode>_plus): Likewise.
- (@aarch64_sme_<optab><VNx1TI_ONLY:mode><SVE_FULL:mode>): Likewise.
- (@aarch64_sme_<optab><v_int_container><mode>): Likewise.
- (*aarch64_sme_<optab><v_int_container><mode>_plus): Likewise.
- (@aarch64_sme_<optab><VNx1TI_ONLY:mode><SVE_FULL:mode>): Likewise.
- (UNSPEC_SME_ZERO): New unspec.
- (aarch64_sme_zero): New pattern.
- (@aarch64_sme_<SME_BINARY_SDI:optab><mode>): Likewise.
- (@aarch64_sme_<SME_INT_MOP:optab><mode>): Likewise.
- (@aarch64_sme_<SME_FP_MOP:optab><mode>): Likewise.
- * config/aarch64/aarch64-sve-builtins.def: Add ZA type suffixes.
- Include aarch64-sve-builtins-sme.def.
- (DEF_SME_ZA_FUNCTION): New macro.
- * config/aarch64/aarch64-sve-builtins.h (CP_READ_ZA): New call
- property.
- (CP_WRITE_ZA): Likewise.
- (PRED_za_m): New predication type.
- (type_suffix_index): Handle DEF_SME_ZA_SUFFIX.
- (type_suffix_info): Add vector_p and za_p fields.
- (function_instance::num_za_tiles): New member function.
- (function_builder::get_attributes): Add an aarch64_feature_flags
- argument.
- (function_expander::get_contiguous_base): Take a base argument
- number, a vnum argument number, and an argument that indicates
- whether the vnum parameter is a factor of the SME vector length
- or the prevailing vector length.
- (function_expander::add_integer_operand): Take a poly_int64.
- (sve_switcher::sve_switcher): Take a base set of flags.
- (sme_switcher): New class.
- (scalar_types): Add a null entry for NUM_VECTOR_TYPES.
- * config/aarch64/aarch64-sve-builtins.cc: Include
- aarch64-sve-builtins-sme.h.
- (pred_suffixes): Add an entry for PRED_za_m.
- (type_suffixes): Initialize vector_p and za_p. Handle ZA suffixes.
- (TYPES_all_za, TYPES_d_za, TYPES_za_bhsd_data, TYPES_za_all_data)
- (TYPES_za_s_integer, TYPES_za_d_integer, TYPES_mop_base)
- (TYPES_mop_base_signed, TYPES_mop_base_unsigned, TYPES_mop_i16i64)
- (TYPES_mop_i16i64_signed, TYPES_mop_i16i64_unsigned, TYPES_za): New
- type suffix macros.
- (preds_m, preds_za_m): New predication lists.
- (function_groups): Handle DEF_SME_ZA_FUNCTION.
- (scalar_types): Add an entry for NUM_VECTOR_TYPES.
- (find_type_suffix_for_scalar_type): Check positively for vectors
- rather than negatively for predicates.
- (check_required_extensions): Handle PSTATE.SM and PSTATE.ZA
- requirements.
- (report_out_of_range): Handle the case where the minimum and
- maximum are the same.
- (function_instance::reads_global_state_p): Return true for functions
- that read ZA.
- (function_instance::modifies_global_state_p): Return true for functions
- that write to ZA.
- (sve_switcher::sve_switcher): Add a base flags argument.
- (function_builder::get_name): Handle "__arm_" prefixes.
- (add_attribute): Add an overload that takes a namespaces.
- (add_shared_state_attribute): New function.
- (function_builder::get_attributes): Take the required feature flags
- as argument. Add streaming and ZA attributes where appropriate.
- (function_builder::add_unique_function): Update calls accordingly.
- (function_resolver::check_gp_argument): Assert that the predication
- isn't ZA _m predication.
- (function_checker::function_checker): Don't bias the argument
- number for ZA _m predication.
- (function_expander::get_contiguous_base): Add arguments that
- specify the base argument number, the vnum argument number,
- and an argument that indicates whether the vnum parameter is
- a factor of the SME vector length or the prevailing vector length.
- Handle the SME case.
- (function_expander::add_input_operand): Handle pmode_register_operand.
- (function_expander::add_integer_operand): Take a poly_int64.
- (init_builtins): Call handle_arm_sme_h for LTO.
- (handle_arm_sve_h): Skip SME intrinsics.
- (handle_arm_sme_h): New function.
- * config/aarch64/aarch64-sve-builtins-functions.h
- (read_write_za, write_za): New classes.
- (unspec_based_sme_function, za_arith_function): New using aliases.
- (quiet_za_arith_function): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.h
- (binary_za_int_m, binary_za_m, binary_za_uint_m, bool_inherent)
- (inherent_za, inherent_mask_za, ldr_za, load_za, read_za_m, store_za)
- (str_za, unary_za_m, write_za_m): Declare.
- * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
- Expect za_m functions to have an existing governing predicate.
- (binary_za_m_base, binary_za_int_m_def, binary_za_m_def): New classes.
- (binary_za_uint_m_def, bool_inherent_def, inherent_za_def): Likewise.
- (inherent_mask_za_def, ldr_za_def, load_za_def, read_za_m_def)
- (store_za_def, str_za_def, unary_za_m_def, write_za_m_def): Likewise.
- * config/aarch64/arm_sme.h: New file.
- * config/aarch64/aarch64-sve-builtins-sme.h: Likewise.
- * config/aarch64/aarch64-sve-builtins-sme.cc: Likewise.
- * config/aarch64/aarch64-sve-builtins-sme.def: Likewise.
- * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
- aarch64-sve-builtins-sme.def and aarch64-sve-builtins-sme.h.
- (aarch64-sve-builtins-sme.o): New rule.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_shape::has_merge_argument_p): New member function.
- * config/aarch64/aarch64-sve-builtins.cc:
- (function_resolver::check_gp_argument): Use it.
- (function_expander::get_fallback_value): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (apply_predication): Likewise.
- (unary_convert_narrowt_def::has_merge_argument_p): New function.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-functions.h
- (unspec_based_function_base): Allow type suffix 1 to determine
- the mode of the operation.
- (unspec_based_function): Update accordingly.
- (unspec_based_fused_function): Likewise.
- (unspec_based_fused_lane_function): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-modes.def: Add VNx1TI.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (W12_W15_REGNUM_P): New macro.
- (W12_W15_REGS): New register class.
- (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add entries for it.
- * config/aarch64/aarch64.cc (aarch64_regno_regclass)
- (aarch64_class_max_nregs, aarch64_register_move_cost): Handle
- W12_W15_REGS.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-isa-modes.def (ZA_ON): New ISA mode.
- * config/aarch64/aarch64-protos.h (aarch64_rdsvl_immediate_p)
- (aarch64_output_rdsvl, aarch64_optimize_mode_switching)
- (aarch64_restore_za): Declare.
- * config/aarch64/constraints.md (UsR): New constraint.
- * config/aarch64/aarch64.md (LOWERING_REGNUM, TPIDR_BLOCK_REGNUM)
- (SME_STATE_REGNUM, TPIDR2_SETUP_REGNUM, ZA_FREE_REGNUM)
- (ZA_SAVED_REGNUM, ZA_REGNUM, FIRST_FAKE_REGNUM): New constants.
- (LAST_FAKE_REGNUM): Likewise.
- (UNSPEC_SAVE_NZCV, UNSPEC_RESTORE_NZCV, UNSPEC_SME_VQ): New unspecs.
- (arches): Add sme.
- (arch_enabled): Handle it.
- (*cb<optab><mode>1): Rename to...
- (aarch64_cb<optab><mode>1): ...this.
- (*movsi_aarch64): Add an alternative for RDSVL.
- (*movdi_aarch64): Likewise.
- (aarch64_save_nzcv, aarch64_restore_nzcv): New insns.
- * config/aarch64/aarch64-sme.md (UNSPEC_SMSTOP_ZA)
- (UNSPEC_INITIAL_ZERO_ZA, UNSPEC_TPIDR2_SAVE, UNSPEC_TPIDR2_RESTORE)
- (UNSPEC_READ_TPIDR2, UNSPEC_WRITE_TPIDR2, UNSPEC_SETUP_LOCAL_TPIDR2)
- (UNSPEC_RESTORE_ZA, UNSPEC_START_PRIVATE_ZA_CALL): New unspecs.
- (UNSPEC_END_PRIVATE_ZA_CALL, UNSPEC_COMMIT_LAZY_SAVE): Likewise.
- (UNSPECV_ASM_UPDATE_ZA): New unspecv.
- (aarch64_tpidr2_save, aarch64_smstart_za, aarch64_smstop_za)
- (aarch64_initial_zero_za, aarch64_setup_local_tpidr2)
- (aarch64_clear_tpidr2, aarch64_write_tpidr2, aarch64_read_tpidr2)
- (aarch64_tpidr2_restore, aarch64_restore_za, aarch64_asm_update_za)
- (aarch64_start_private_za_call, aarch64_end_private_za_call)
- (aarch64_commit_lazy_save): New patterns.
- * config/aarch64/aarch64.h (AARCH64_ISA_ZA_ON, TARGET_ZA): New macros.
- (FIXED_REGISTERS, REGISTER_NAMES): Add the new fake ZA registers.
- (CALL_USED_REGISTERS): Replace with...
- (CALL_REALLY_USED_REGISTERS): ...this and add the fake ZA registers.
- (FIRST_PSEUDO_REGISTER): Bump to include the fake ZA registers.
- (FAKE_REGS): New register class.
- (REG_CLASS_NAMES): Update accordingly.
- (REG_CLASS_CONTENTS): Likewise.
- (machine_function::tpidr2_block): New member variable.
- (machine_function::tpidr2_block_ptr): Likewise.
- (machine_function::za_save_buffer): Likewise.
- (machine_function::next_asm_update_za_id): Likewise.
- (CUMULATIVE_ARGS::shared_za_flags): Likewise.
- (aarch64_mode_entity, aarch64_local_sme_state): New enums.
- (aarch64_tristate_mode): Likewise.
- (OPTIMIZE_MODE_SWITCHING, NUM_MODES_FOR_MODE_SWITCHING): Define.
- * config/aarch64/aarch64.cc (AARCH64_STATE_SHARED, AARCH64_STATE_IN)
- (AARCH64_STATE_OUT): New constants.
- (aarch64_attribute_shared_state_flags): New function.
- (aarch64_lookup_shared_state_flags, aarch64_fndecl_has_new_state)
- (aarch64_check_state_string, cmp_string_csts): Likewise.
- (aarch64_merge_string_arguments, aarch64_check_arm_new_against_type)
- (handle_arm_new, handle_arm_shared): Likewise.
- (handle_arm_new_za_attribute): New
- (aarch64_arm_attribute_table): Add new, preserves, in, out, and inout.
- (aarch64_hard_regno_nregs): Handle FAKE_REGS.
- (aarch64_hard_regno_mode_ok): Likewise.
- (aarch64_fntype_shared_flags, aarch64_fntype_pstate_za): New functions.
- (aarch64_fntype_isa_mode): Include aarch64_fntype_pstate_za.
- (aarch64_fndecl_has_state, aarch64_fndecl_pstate_za): New functions.
- (aarch64_fndecl_isa_mode): Include aarch64_fndecl_pstate_za.
- (aarch64_cfun_incoming_pstate_za, aarch64_cfun_shared_flags)
- (aarch64_cfun_has_new_state, aarch64_cfun_has_state): New functions.
- (aarch64_sme_vq_immediate, aarch64_sme_vq_unspec_p): Likewise.
- (aarch64_rdsvl_immediate_p, aarch64_output_rdsvl): Likewise.
- (aarch64_expand_mov_immediate): Handle RDSVL immediates.
- (aarch64_function_arg): Add the ZA sharing flags as a third limb
- of the PARALLEL.
- (aarch64_init_cumulative_args): Record the ZA sharing flags.
- (aarch64_extra_live_on_entry): New function. Handle the new
- ZA-related fake registers.
- (aarch64_epilogue_uses): Handle the new ZA-related fake registers.
- (aarch64_cannot_force_const_mem): Handle UNSPEC_SME_VQ constants.
- (aarch64_get_tpidr2_block, aarch64_get_tpidr2_ptr): New functions.
- (aarch64_init_tpidr2_block, aarch64_restore_za): Likewise.
- (aarch64_layout_frame): Check whether the current function creates
- new ZA state. Record that it clobbers LR if so.
- (aarch64_expand_prologue): Handle functions that create new ZA state.
- (aarch64_expand_epilogue): Likewise.
- (aarch64_create_tpidr2_block): New function.
- (aarch64_restore_za): Likewise.
- (aarch64_start_call_args): Disallow calls to shared-ZA functions
- from functions that have no ZA state. Emit a marker instruction
- before calls to private-ZA functions from functions that have
- SME state.
- (aarch64_expand_call): Add return registers for state that is
- managed via attributes. Record the use and clobber information
- for the ZA registers.
- (aarch64_end_call_args): New function.
- (aarch64_regno_regclass): Handle FAKE_REGS.
- (aarch64_class_max_nregs): Likewise.
- (aarch64_override_options_internal): Require TARGET_SME for
- functions that have ZA state.
- (aarch64_conditional_register_usage): Handle FAKE_REGS.
- (aarch64_mov_operand_p): Handle RDSVL immediates.
- (aarch64_comp_type_attributes): Check that the ZA sharing flags
- are equal.
- (aarch64_merge_decl_attributes): New function.
- (aarch64_optimize_mode_switching, aarch64_mode_emit_za_save_buffer)
- (aarch64_mode_emit_local_sme_state, aarch64_mode_emit): Likewise.
- (aarch64_insn_references_sme_state_p): Likewise.
- (aarch64_mode_needed_local_sme_state): Likewise.
- (aarch64_mode_needed_za_save_buffer, aarch64_mode_needed): Likewise.
- (aarch64_mode_after_local_sme_state, aarch64_mode_after): Likewise.
- (aarch64_local_sme_confluence, aarch64_mode_confluence): Likewise.
- (aarch64_one_shot_backprop, aarch64_local_sme_backprop): Likewise.
- (aarch64_mode_backprop, aarch64_mode_entry): Likewise.
- (aarch64_mode_exit, aarch64_mode_eh_handler): Likewise.
- (aarch64_mode_priority, aarch64_md_asm_adjust): Likewise.
- (TARGET_END_CALL_ARGS, TARGET_MERGE_DECL_ATTRIBUTES): Define.
- (TARGET_MODE_EMIT, TARGET_MODE_NEEDED, TARGET_MODE_AFTER): Likewise.
- (TARGET_MODE_CONFLUENCE, TARGET_MODE_BACKPROP): Likewise.
- (TARGET_MODE_ENTRY, TARGET_MODE_EXIT): Likewise.
- (TARGET_MODE_EH_HANDLER, TARGET_MODE_PRIORITY): Likewise.
- (TARGET_EXTRA_LIVE_ON_ENTRY): Likewise.
- (TARGET_MD_ASM_ADJUST): Use aarch64_md_asm_adjust.
- * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
- Define __arm_new, __arm_preserves,__arm_in, __arm_out, and __arm_inout.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-passes.def
- (pass_late_thread_prologue_and_epilogue): New pass.
- * config/aarch64/aarch64-sme.md: New file.
- * config/aarch64/aarch64.md: Include it.
- (*tb<optab><mode>1): Rename to...
- (@aarch64_tb<optab><mode>): ...this.
- (call, call_value, sibcall, sibcall_value): Don't require operand 2
- to be a CONST_INT.
- * config/aarch64/aarch64-protos.h (aarch64_emit_call_insn): Return
- the insn.
- (make_pass_switch_sm_state): Declare.
- * config/aarch64/aarch64.h (TARGET_STREAMING_COMPATIBLE): New macro.
- (CALL_USED_REGISTER): Mark VG as call-preserved.
- (aarch64_frame::old_svcr_offset): New member variable.
- (machine_function::call_switches_sm_state): Likewise.
- (CUMULATIVE_ARGS::num_sme_mode_switch_args): Likewise.
- (CUMULATIVE_ARGS::sme_mode_switch_args): Likewise.
- * config/aarch64/aarch64.cc: Include tree-pass.h and cfgbuild.h.
- (aarch64_cfun_incoming_pstate_sm): New function.
- (aarch64_call_switches_pstate_sm): Likewise.
- (aarch64_reg_save_mode): Return DImode for VG_REGNUM.
- (aarch64_callee_isa_mode): New function.
- (aarch64_insn_callee_isa_mode): Likewise.
- (aarch64_guard_switch_pstate_sm): Likewise.
- (aarch64_switch_pstate_sm): Likewise.
- (aarch64_sme_mode_switch_regs): New class.
- (aarch64_record_sme_mode_switch_args): New function.
- (aarch64_finish_sme_mode_switch_args): Likewise.
- (aarch64_function_arg): Handle the end marker by returning a
- PARALLEL that contains the ABI cookie that we used previously
- alongside the result of aarch64_finish_sme_mode_switch_args.
- (aarch64_init_cumulative_args): Initialize num_sme_mode_switch_args.
- (aarch64_function_arg_advance): If a call would switch SM state,
- record all argument registers that would need to be saved around
- the mode switch.
- (aarch64_need_old_pstate_sm): New function.
- (aarch64_layout_frame): Decide whether the frame needs to store the
- incoming value of PSTATE.SM and allocate a save slot for it if so.
- If a function switches SME state, arrange to save the old value
- of the DWARF VG register. Handle the case where this is the only
- register save slot above the FP.
- (aarch64_save_callee_saves): Handles saves of the DWARF VG register.
- (aarch64_get_separate_components): Prevent such saves from being
- shrink-wrapped.
- (aarch64_old_svcr_mem): New function.
- (aarch64_read_old_svcr): Likewise.
- (aarch64_guard_switch_pstate_sm): Likewise.
- (aarch64_expand_prologue): Handle saves of the DWARF VG register.
- Initialize any SVCR save slot.
- (aarch64_expand_call): Allow the cookie to be PARALLEL that contains
- both the UNSPEC_CALLEE_ABI value and a list of registers that need
- to be preserved across a change to PSTATE.SM. If the call does
- involve such a change to PSTATE.SM, record the registers that
- would be clobbered by this process. Also emit an instruction
- to mark the temporary change in VG. Update call_switches_pstate_sm.
- (aarch64_emit_call_insn): Return the emitted instruction.
- (aarch64_frame_pointer_required): New function.
- (aarch64_conditional_register_usage): Prevent VG_REGNUM from being
- treated as a register operand.
- (aarch64_switch_pstate_sm_for_call): New function.
- (pass_data_switch_pstate_sm): New pass variable.
- (pass_switch_pstate_sm): New pass class.
- (make_pass_switch_pstate_sm): New function.
- (TARGET_FRAME_POINTER_REQUIRED): Define.
- * config/aarch64/t-aarch64 (s-check-sve-md): Add aarch64-sme.md.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (TARGET_NON_STREAMING): New macro.
- (TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Use it.
- (TARGET_SVE2_SHA3, TARGET_SVE2_SM4): Likewise.
- * config/aarch64/aarch64-sve-builtins-base.def: Separate out
- the functions that require PSTATE.SM to be 0 and guard them
- with AARCH64_FL_SM_OFF.
- * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
- * config/aarch64/aarch64-sve-builtins.cc (check_required_extensions):
- Enforce AARCH64_FL_SM_OFF requirements.
- * config/aarch64/aarch64-sve.md (aarch64_wrffr): Require
- TARGET_NON_STREAMING
- (aarch64_rdffr, aarch64_rdffr_z, *aarch64_rdffr_z_ptest): Likewise.
- (*aarch64_rdffr_ptest, *aarch64_rdffr_z_cc, *aarch64_rdffr_cc)
- (@aarch64_ld<fn>f1<mode>): Likewise.
- (@aarch64_ld<fn>f1_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>)
- (gather_load<mode><v_int_container>): Likewise
- (mask_gather_load<mode><v_int_container>): Likewise.
- (mask_gather_load<mode><v_int_container>): Likewise.
- (*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
- (*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
- (*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>)
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked)
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_sxtw): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather<mode>, @aarch64_ldff1_gather<mode>): Likewise.
- (*aarch64_ldff1_gather<mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather<mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
- <VNx4_NARROW:mode>): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_uxtw): Likewise.
- (@aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx4SI_ONLY:mode>)
- (@aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>)
- (*aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>_sxtw)
- (*aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>_uxtw)
- (scatter_store<mode><v_int_container>): Likewise.
- (mask_scatter_store<mode><v_int_container>): Likewise.
- (*mask_scatter_store<mode><v_int_container>_<su>xtw_unpacked)
- (*mask_scatter_store<mode><v_int_container>_sxtw): Likewise.
- (*mask_scatter_store<mode><v_int_container>_uxtw): Likewise.
- (@aarch64_scatter_store_trunc<VNx4_NARROW:mode><VNx4_WIDE:mode>)
- (@aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>)
- (*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_sxtw)
- (*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_uxtw)
- (@aarch64_sve_ld1ro<mode>, @aarch64_adr<mode>): Likewise.
- (*aarch64_adr_sxtw, *aarch64_adr_uxtw_unspec): Likewise.
- (*aarch64_adr_uxtw_and, @aarch64_adr<mode>_shift): Likewise.
- (*aarch64_adr<mode>_shift, *aarch64_adr_shift_sxtw): Likewise.
- (*aarch64_adr_shift_uxtw, @aarch64_sve_add_<optab><vsi2qi>): Likewise.
- (@aarch64_sve_<sve_fp_op><mode>, fold_left_plus_<mode>): Likewise.
- (mask_fold_left_plus_<mode>, @aarch64_sve_compact<mode>): Likewise.
- * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>)
- (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
- <SVE_PARTIAL_I:mode>): Likewise.
- (@aarch64_sve2_histcnt<mode>, @aarch64_sve2_histseg<mode>): Likewise.
- (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
- (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
- (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
- * config/aarch64/iterators.md (SVE_FP_UNARY_INT): Make FEXPA
- depend on TARGET_NON_STREAMING.
- (SVE_BFLOAT_TERNARY_LONG): Likewise BFMMLA.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (TARGET_BASE_SIMD): New macro.
- (TARGET_SIMD): Require PSTATE.SM to be 0.
- (AARCH64_ISA_SM_OFF): New macro.
- * config/aarch64/aarch64.cc (aarch64_array_mode_supported_p):
- Allow Advanced SIMD structure modes for TARGET_BASE_SIMD.
- (aarch64_print_operand): Support '%Z'.
- (aarch64_secondary_reload): Expect SVE moves to be used for
- Advanced SIMD modes if SVE is enabled and non-streaming
- Advanced SIMD isn't.
- (aarch64_register_move_cost): Likewise.
- (aarch64_simd_container_mode): Extend Advanced SIMD mode
- handling to TARGET_BASE_SIMD.
- (aarch64_expand_cpymem): Expand commentary.
- * config/aarch64/aarch64.md (arches): Add base_simd and nobase_simd.
- (arch_enabled): Handle it.
- (*mov<mode>_aarch64): Extend UMOV alternative to TARGET_BASE_SIMD.
- (*movti_aarch64): Use an SVE move instruction if non-streaming
- SIMD isn't available.
- (*mov<TFD:mode>_aarch64): Likewise.
- (load_pair_dw_tftf): Extend to TARGET_BASE_SIMD.
- (store_pair_dw_tftf): Likewise.
- (loadwb_pair<TX:mode>_<P:mode>): Likewise.
- (storewb_pair<TX:mode>_<P:mode>): Likewise.
- * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
- Allow UMOV in streaming mode.
- (*aarch64_simd_mov<VQMOV:mode>): Use an SVE move instruction
- if non-streaming SIMD isn't available.
- (aarch64_store_lane0<mode>): Depend on TARGET_FLOAT rather than
- TARGET_SIMD.
- (aarch64_simd_mov_from_<mode>low): Likewise. Use fmov if
- Advanced SIMD is completely disabled.
- (aarch64_simd_mov_from_<mode>high): Use SVE EXT instructions if
- non-streaming SIMD isn't available.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/invoke.texi: Document SME.
- * doc/sourcebuild.texi: Document aarch64_sve.
- * config/aarch64/aarch64-option-extensions.def (sme): Define.
- * config/aarch64/aarch64.h (AARCH64_ISA_SME): New macro.
- (TARGET_SME): Likewise.
- * config/aarch64/aarch64.cc (aarch64_override_options_internal):
- Ensure that SME is present when compiling streaming code.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-isa-modes.def: New file.
- * config/aarch64/aarch64.h: Include it in the feature enumerations.
- (AARCH64_FL_SM_STATE, AARCH64_FL_ISA_MODES): New constants.
- (AARCH64_FL_DEFAULT_ISA_MODE): Likewise.
- (AARCH64_ISA_MODE): New macro.
- (CUMULATIVE_ARGS): Add an isa_mode field.
- * config/aarch64/aarch64-protos.h (aarch64_gen_callee_cookie): Declare.
- (aarch64_tlsdesc_abi_id): Return an arm_pcs.
- * config/aarch64/aarch64.cc (attr_streaming_exclusions)
- (aarch64_gnu_attributes, aarch64_gnu_attribute_table)
- (aarch64_arm_attributes, aarch64_arm_attribute_table): New tables.
- (aarch64_attribute_table): Redefine to include the gnu and arm
- attributes.
- (aarch64_fntype_pstate_sm, aarch64_fntype_isa_mode): New functions.
- (aarch64_fndecl_pstate_sm, aarch64_fndecl_isa_mode): Likewise.
- (aarch64_gen_callee_cookie, aarch64_callee_abi): Likewise.
- (aarch64_insn_callee_cookie, aarch64_insn_callee_abi): Use them.
- (aarch64_function_arg, aarch64_output_mi_thunk): Likewise.
- (aarch64_init_cumulative_args): Initialize the isa_mode field.
- (aarch64_output_mi_thunk): Use aarch64_gen_callee_cookie to get
- the ABI cookie.
- (aarch64_override_options): Add the ISA mode to the feature set.
- (aarch64_temporary_target::copy_from_fndecl): Likewise.
- (aarch64_fndecl_options, aarch64_handle_attr_arch): Likewise.
- (aarch64_set_current_function): Maintain the correct ISA mode.
- (aarch64_tlsdesc_abi_id): Return an arm_pcs.
- (aarch64_comp_type_attributes): Handle arm::streaming and
- arm::streaming_compatible.
- * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
- Define __arm_streaming and __arm_streaming_compatible.
- * config/aarch64/aarch64.md (tlsdesc_small_<mode>): Use
- aarch64_gen_callee_cookie to get the ABI cookie.
- * config/aarch64/t-aarch64 (TM_H): Add all feature-related .def files.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svreinterpret_impl::fold): Punt on tuple forms.
- (svreinterpret_impl::expand): Use tuple_mode instead of vector_mode.
- * config/aarch64/aarch64-sve-builtins-base.def (svreinterpret):
- Extend to x1234 groups.
- * config/aarch64/aarch64-sve-builtins-functions.h
- (multi_vector_function::vectors_per_tuple): If the function has
- a group suffix, get the number of vectors from there.
- * config/aarch64/aarch64-sve-builtins-shapes.h (reinterpret): Declare.
- * config/aarch64/aarch64-sve-builtins-shapes.cc (reinterpret_def)
- (reinterpret): New function shape.
- * config/aarch64/aarch64-sve-builtins.cc (function_groups): Handle
- DEF_SVE_FUNCTION_GS.
- * config/aarch64/aarch64-sve-builtins.def (DEF_SVE_FUNCTION_GS): New
- macro.
- (DEF_SVE_FUNCTION): Forward to DEF_SVE_FUNCTION_GS by default.
- * config/aarch64/aarch64-sve-builtins.h
- (function_instance::tuple_mode): New member function.
- (function_base::vectors_per_tuple): Take the function instance
- as argument and get the number from the group suffix.
- (function_instance::vectors_per_tuple): Update accordingly.
- * config/aarch64/iterators.md (SVE_FULLx2, SVE_FULLx3, SVE_FULLx4)
- (SVE_ALL_STRUCT): New mode iterators.
- (SVE_STRUCT): Redefine in terms of SVE_FULL*.
- * config/aarch64/aarch64-sve.md (@aarch64_sve_reinterpret<mode>)
- (*aarch64_sve_reinterpret<mode>): Extend to SVE structure modes.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.cc
- (function_resolver::require_derived_vector_type): Add a specific
- error message for the case in which the caller wants a single
- vector whose element type matches a previous tuyple argument.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_resolver::lookup_form): Add an overload that takes
- an sve_type rather than type and group suffixes.
- (function_resolver::resolve_to): Likewise.
- (function_resolver::infer_vector_or_tuple_type): Return an sve_type.
- (function_resolver::infer_tuple_type): Likewise.
- (function_resolver::require_matching_vector_type): Take an sve_type
- rather than a type_suffix_index.
- (function_resolver::require_derived_vector_type): Likewise.
- * config/aarch64/aarch64-sve-builtins.cc (num_vectors_to_group):
- New function.
- (function_resolver::lookup_form): Add an overload that takes
- an sve_type rather than type and group suffixes.
- (function_resolver::resolve_to): Likewise.
- (function_resolver::infer_vector_or_tuple_type): Return an sve_type.
- (function_resolver::infer_tuple_type): Likewise.
- (function_resolver::infer_vector_type): Update accordingly.
- (function_resolver::require_matching_vector_type): Take an sve_type
- rather than a type_suffix_index.
- (function_resolver::require_derived_vector_type): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.cc (get_def::resolve)
- (set_def::resolve, store_def::resolve, tbl_tuple_def::resolve): Update
- calls accordingly.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_resolver::require_matching_vector_type): Add a parameter
- that specifies the number of the earlier argument that is being
- matched against.
- * config/aarch64/aarch64-sve-builtins.cc
- (function_resolver::require_matching_vector_type): Likewise.
- (require_derived_vector_type): Update calls accordingly.
- (function_resolver::resolve_unary): Likewise.
- (function_resolver::resolve_uniform): Likewise.
- (function_resolver::resolve_uniform_opt_n): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (binary_long_lane_def::resolve): Likewise.
- (clast_def::resolve, ternary_uint_def::resolve): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_resolver::infer_sve_type): New member function.
- (function_resolver::report_incorrect_num_vectors): Likewise.
- * config/aarch64/aarch64-sve-builtins.cc
- (function_resolver::infer_sve_type): New function,.
- (function_resolver::report_incorrect_num_vectors): New function,
- split out from...
- (function_resolver::infer_vector_or_tuple_type): ...here. Use
- infer_sve_type.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h (sve_type): New struct.
- (sve_type::operator==): New function.
- (function_resolver::get_vector_type): Delete.
- (function_resolver::report_no_such_form): Take an sve_type rather
- than a type_suffix_index.
- * config/aarch64/aarch64-sve-builtins.cc (get_vector_type): New
- function.
- (function_resolver::get_vector_type): Delete.
- (function_resolver::report_no_such_form): Take an sve_type rather
- than a type_suffix_index.
- (find_sve_type): New function, split out from...
- (function_resolver::infer_vector_or_tuple_type): ...here.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Take
- a group suffix index parameter.
- (build_32_64, build_all): Update accordingly. Iterate over all
- group suffixes.
- * config/aarch64/aarch64-sve-builtins-sve2.cc (svqrshl_impl::fold)
- (svqshl_impl::fold, svrshl_impl::fold): Update function_instance
- constructors.
- * config/aarch64/aarch64-sve-builtins.cc (group_suffixes): New array.
- (groups_none): New constant.
- (function_groups): Initialize the groups field.
- (function_instance::hash): Hash the group index.
- (function_builder::get_name): Add the group suffix.
- (function_builder::add_overloaded_functions): Iterate over all
- group suffixes.
- (function_resolver::lookup_form): Take a group suffix parameter.
- (function_resolver::resolve_to): Likewise.
- * config/aarch64/aarch64-sve-builtins.def (DEF_SVE_GROUP_SUFFIX): New
- macro.
- (x2, x3, x4): New group suffixes.
- * config/aarch64/aarch64-sve-builtins.h (group_suffix_index): New enum.
- (group_suffix_info): New structure.
- (function_group_info::groups): New member variable.
- (function_instance::group_suffix_id): Likewise.
- (group_suffixes): New array.
- (function_instance::operator==): Compare the group suffixes.
- (function_instance::group_suffix): New function.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.cc (function_groups): Remove
- implied requirement on SVE.
- * config/aarch64/aarch64-sve-builtins-base.def: Explicitly require SVE.
- * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_sve_rdvl_immediate_p)
- (aarch64_output_sve_rdvl): Declare.
- * config/aarch64/aarch64.cc (aarch64_sve_cnt_factor_p): New
- function, split out from...
- (aarch64_sve_cnt_immediate_p): ...here.
- (aarch64_sve_rdvl_factor_p): New function.
- (aarch64_sve_rdvl_immediate_p): Likewise.
- (aarch64_output_sve_rdvl): Likewise.
- (aarch64_offset_temporaries): Rewrite the SVE handling to use RDVL
- for some cases.
- (aarch64_expand_mov_immediate): Handle RDVL immediates.
- (aarch64_mov_operand_p): Likewise.
- * config/aarch64/constraints.md (Usr): New constraint.
- * config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64): Add an RDVL
- alternative.
- (*movsi_aarch64, *movdi_aarch64): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h:
- (function_checker::require_immediate_lane_index): Add an argument
- for the index of the indexed vector argument.
- * config/aarch64/aarch64-sve-builtins.cc
- (function_checker::require_immediate_lane_index): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (ternary_bfloat_lane_base::check): Update accordingly.
- (ternary_qq_lane_base::check): Likewise.
- (binary_lane_def::check): Likewise.
- (binary_long_lane_def::check): Likewise.
- (ternary_lane_def::check): Likewise.
- (ternary_lane_rotate_def::check): Likewise.
- (ternary_long_lane_def::check): Likewise.
- (ternary_qq_lane_rotate_def::check): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (md_asm_adjust): Add a uses parameter.
- * doc/tm.texi: Regenerate.
- * cfgexpand.cc (expand_asm_loc): Update call to md_asm_adjust.
- Handle any USEs created by the target.
- (expand_asm_stmt): Likewise.
- * recog.cc (asm_noperands): Handle asms with USEs.
- (decode_asm_operands): Likewise.
- * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Add uses
- parameter.
- * config/arm/aarch-common.cc (arm_md_asm_adjust): Likewise.
- * config/arm/arm.cc (thumb1_md_asm_adjust): Likewise.
- * config/avr/avr.cc (avr_md_asm_adjust): Likewise.
- * config/cris/cris.cc (cris_md_asm_adjust): Likewise.
- * config/i386/i386.cc (ix86_md_asm_adjust): Likewise.
- * config/mn10300/mn10300.cc (mn10300_md_asm_adjust): Likewise.
- * config/nds32/nds32.cc (nds32_md_asm_adjust): Likewise.
- * config/pdp11/pdp11.cc (pdp11_md_asm_adjust): Likewise.
- * config/rs6000/rs6000.cc (rs6000_md_asm_adjust): Likewise.
- * config/s390/s390.cc (s390_md_asm_adjust): Likewise.
- * config/vax/vax.cc (vax_md_asm_adjust): Likewise.
- * config/visium/visium.cc (visium_md_asm_adjust): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/tm.texi.in: Add TARGET_START_CALL_ARGS.
- * doc/tm.texi: Regenerate.
- * target.def (start_call_args): New hook.
- (call_args, end_call_args): Add a parameter for the cumulative
- argument information.
- * hooks.h (hook_void_rtx_tree): Delete.
- * hooks.cc (hook_void_rtx_tree): Likewise.
- * targhooks.h (hook_void_CUMULATIVE_ARGS): Declare.
- (hook_void_CUMULATIVE_ARGS_rtx_tree): Likewise.
- * targhooks.cc (hook_void_CUMULATIVE_ARGS): New function.
- (hook_void_CUMULATIVE_ARGS_rtx_tree): Likewise.
- * calls.cc (expand_call): Call start_call_args before computing
- and storing stack parameters. Pass the cumulative argument
- information to call_args and end_call_args.
- (emit_library_call_value_1): Likewise.
- * config/nvptx/nvptx.cc (nvptx_call_args): Add a cumulative
- argument parameter.
- (nvptx_end_call_args): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/tm.texi.in: Add TARGET_EMIT_EPILOGUE_FOR_SIBCALL.
- * doc/tm.texi: Regenerate.
- * target.def (emit_epilogue_for_sibcall): New hook.
- * calls.cc (can_implement_as_sibling_call_p): Use it.
- * function.cc (thread_prologue_and_epilogue_insns): Likewise.
- (reposition_prologue_and_epilogue_notes): Likewise.
- * config/aarch64/aarch64-protos.h (aarch64_expand_epilogue): Take
- an rtx_call_insn * rather than a bool.
- * config/aarch64/aarch64.cc (aarch64_expand_epilogue): Likewise.
- (TARGET_EMIT_EPILOGUE_FOR_SIBCALL): Define.
- * config/aarch64/aarch64.md (epilogue): Update call.
- (sibcall_epilogue): Delete.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (use_late_prologue_epilogue): New hook.
- * doc/tm.texi.in: Add TARGET_USE_LATE_PROLOGUE_EPILOGUE.
- * doc/tm.texi: Regenerate.
- * passes.def (pass_late_thread_prologue_and_epilogue): New pass.
- * tree-pass.h (make_pass_late_thread_prologue_and_epilogue): Declare.
- * function.cc (pass_thread_prologue_and_epilogue::gate): New function.
- (pass_data_late_thread_prologue_and_epilogue): New pass variable.
- (pass_late_thread_prologue_and_epilogue): New pass class.
- (make_pass_late_thread_prologue_and_epilogue): New function.
-
-2023-12-05 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_subset_list::check_conflict_ext): Check zcd conflicts
- with zcmt and zcmp.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- PR rtl-optimization/112278
- * lra-int.h (lra_update_biggest_mode): New function.
- * lra-coalesce.cc (merge_pseudos): Use it.
- * lra-lives.cc (process_bb_lives): Likewise.
- * lra.cc (new_insn_reg): Likewise.
-
-2023-12-05 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112843
- * gimple-lower-bitint.cc (gimple_lower_bitint): Change lhs of stmt
- to lhs2 before building and inserting lhs = (cast) lhs2; assignment.
- Adjust stmt operands before adjusting lhs.
-
-2023-12-05 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-v.cc (sew64_scalar_helper): Bugfix.
-
-2023-12-05 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112816
- * config/i386/sse.md ((eq (eq (lshiftrt x elt_bits-1) 0) 0)): New
- splitter to turn psrld $31; pcmpeq; pcmpeq into psrad $31.
-
-2023-12-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Add blocker.
- * config/riscv/riscv-protos.h (gather_scatter_valid_offset_p): New function.
- * config/riscv/riscv-v.cc (gather_scatter_valid_offset_p): Ditto.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112827
- PR tree-optimization/112848
- * tree-scalar-evolution.cc (final_value_replacement_loop):
- Compute the insert location for each insert.
-
-2023-12-05 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
- Count sse_reg/gpr_regs for components not loaded from memory.
- (ix86_vector_costs:ix86_vector_costs): New constructor.
- (ix86_vector_costs::m_num_gpr_needed[3]): New private memeber.
- (ix86_vector_costs::m_num_sse_needed[3]): Ditto.
- (ix86_vector_costs::finish_cost): Estimate overall register
- pressure cost.
- (ix86_vector_costs::ix86_vect_estimate_reg_pressure): New
- function.
-
-2023-12-05 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (udot_prodv64qi): New expander.
- (udot_prod<mode>): Emulates with VEC_UNPACKU_EXPR +
- DOT_PROD (short, int).
-
-2023-12-05 Marek Polacek <polacek@redhat.com>
-
- PR c++/107687
- PR c++/110997
- * doc/invoke.texi: Document -fno-immediate-escalation.
-
-2023-12-04 Andrew Pinski <quic_apinski@quicinc.com>
-
- * match.pd (zero_one_valued_p): For convert
- make sure type is not a signed 1-bit integer.
-
-2023-12-04 Jeff Law <jlaw@ventanamicro.com>
-
- * config/microblaze/microblaze.md (movhi): Use %i for half-word
- loads to properly select between lhu/lhui.
-
-2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-string.cc (expand_rawmemchr): Increment
- source address by vl * element_size.
-
-2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum):
- Rename...
- (enum stringop_strategy_enum): ... to this.
- * config/riscv/riscv-string.cc (riscv_expand_block_move): New
- wrapper expander handling the strategies and delegation.
- (riscv_expand_block_move_scalar): Rename function and make
- static.
- (expand_block_move): Remove strategy handling.
- * config/riscv/riscv.md: Call expander wrapper.
- * config/riscv/riscv.opt: Rename.
-
-2023-12-04 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112785
- * function.h (get_new_clique): New inline function handling
- last_clique overflow.
- * cfgrtl.cc (duplicate_insn_chain): Use it.
- * tree-cfg.cc (gimple_duplicate_bb): Likewise.
- * tree-inline.cc (remap_dependence_clique): Likewise.
-
-2023-12-04 Christoph Müllner <christoph.muellner@vrull.eu>
-
- PR target/112650
- * doc/invoke.texi: Document riscv-strcmp-inline-limit.
-
-2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Fix incorrect overlap in v0.
-
-2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Add highest-number overlap support.
-
-2023-12-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112818
- * tree-vect-stmts.cc (vectorizable_bswap): Check input and
- output vector types have the same size.
-
-2023-12-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112827
- * tree-scalar-evolution.cc (final_value_replacement_loop):
- Do not release SSA name but keep a dead initialization around.
-
-2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Remove earlyclobber from widen reduction.
-
-2023-12-04 Indu Bhagat <indu.bhagat@oracle.com>
-
- PR debug/112656
- * btfout.cc (btf_asm_type): Fixup ctti_name for all
- BTF types of kind BTF_KIND_FUNC_PROTO.
-
-2023-12-04 Indu Bhagat <indu.bhagat@oracle.com>
-
- PR debug/112768
- * btfout.cc (get_btf_type_name): New definition.
- (btf_collect_datasec): Update dtd_name to the original type name
- string.
- (btf_asm_type_ref): Use the new get_btf_type_name function
- instead.
- (btf_asm_type): Likewise.
- (btf_asm_func_type): Likewise.
-
-2023-12-04 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112837
- * config/i386/i386.cc (ix86_elim_entry_set_got): Before checking
- for UNSPEC_SET_GOT check that SET_SRC is UNSPEC. Use SET_SRC and
- SET_DEST macros instead of XEXP, rename vec variable to set.
-
-2023-12-04 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112816
- * config/i386/sse.md (signbit<mode>2): Force operands[1] into a REG.
-
-2023-12-04 Feng Wang <wangfeng@eswincomputing.com>
-
- * common/config/riscv/riscv-common.cc: Add zvkb ISA info.
- * config/riscv/riscv.opt: Add Mask(ZVKB)
-
-2023-12-04 Fei Gao <gaofei@eswincomputing.com>
- Xiao Zeng <zengxiao@eswincomputing.com>
-
- * config/riscv/riscv.md (*mov<GPR:mode><X:mode>cc):move to sfb.md
- * config/riscv/sfb.md: New file.
-
-2023-12-04 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-cores.def: Add sifive-x280.
- * doc/invoke.texi (RISC-V Options): Add sifive-x280
-
-2023-12-04 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc (riscv_implied_predicator_t): New.
- (riscv_implied_info_t::riscv_implied_info_t): New.
- (riscv_implied_info_t::match): New.
- (riscv_implied_info): New entry for zcf.
- (riscv_subset_list::handle_implied_ext): Use
- riscv_implied_info_t::match.
- (riscv_subset_list::check_implied_ext): Ditto.
- (riscv_subset_list::handle_combine_ext): Ditto.
- (riscv_subset_list::parse): Move zcf implication handling to
- riscv_implied_infos.
-
-2023-12-04 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_subset_list::check_conflict_ext): New.
- (riscv_subset_list::parse): Move checking conflict ext. to
- check_conflict_ext.
- * config/riscv/riscv-subset.h:
- Add riscv_subset_list::check_conflict_ext.
-
-2023-12-04 Hu, Lin1 <lin1.hu@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR
- to the correct location.
-
-2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.md: Rostify the constraints.
-
-2023-12-04 chenxiaolong <chenxiaolong@loongson.cn>
-
- * doc/extend.texi: Add information about the intrinsic function of the vector
- instruction.
-
-2023-12-03 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112807
- * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
- When choosing type0 and type1 types, if prec3 has small/middle bitint
- kind, use maximum of type0 and type1's precision instead of prec3.
-
-2023-12-03 Jeff Law <jlaw@ventanamicro.com>
-
- * config/frv/frv.h (TRANSFER_FROM_TRAMPOLINE): Add prototype for exit.
-
-2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.cc (comp_type_attributes): Pass the full TREE_PURPOSE
- to lookup_attribute_spec, rather than just the name.
- (remove_attributes_matching): Likewise.
-
-2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.cc (find_same_attribute): New function.
- (decl_attributes, comp_type_attributes): Use it when looking
- up one list's attributes in another list.
-
-2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * Makefile.in (GTFILES): Add attribs.cc.
- * attribs.cc (gnu_namespace_cache): New variable.
- (get_gnu_namespace): New function.
- (lookup_attribute_spec): Use it instead of get_identifier ("gnu").
- (get_attribute_namespace, attribs_cc_tests): Likewise.
-
-2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.h (scoped_attribute_specs): New structure.
- (register_scoped_attributes): Take a reference to a
- scoped_attribute_specs instead of separate namespace and array
- parameters.
- * plugin.h (register_scoped_attributes): Likewise.
- * attribs.cc (register_scoped_attributes): Likewise.
- (attribute_tables): Change into an array of scoped_attribute_specs
- pointers. Reduce to 1 element for frontends and 1 element for targets.
- (empty_attribute_table): Delete.
- (check_attribute_tables): Update for changes to attribute_tables.
- Use a hash_set to identify duplicates.
- (handle_ignored_attributes_option): Update for above changes.
- (init_attributes): Likewise.
- (excl_pair): Delete.
- (test_attribute_exclusions): Update for above changes. Don't
- enforce symmetry for standard attributes in the top-level namespace.
- * langhooks-def.h (LANG_HOOKS_COMMON_ATTRIBUTE_TABLE): Delete.
- (LANG_HOOKS_FORMAT_ATTRIBUTE_TABLE): Likewise.
- (LANG_HOOKS_INITIALIZER): Update accordingly.
- (LANG_HOOKS_ATTRIBUTE_TABLE): Define to an empty constructor.
- * langhooks.h (lang_hooks::common_attribute_table): Delete.
- (lang_hooks::format_attribute_table): Likewise.
- (lang_hooks::attribute_table): Redefine to an array of
- scoped_attribute_specs pointers.
- * target-def.h (TARGET_GNU_ATTRIBUTES): New macro.
- * target.def (attribute_spec): Redefine to return an array of
- scoped_attribute_specs pointers.
- * tree-inline.cc (function_attribute_inlinable_p): Update accordingly.
- * doc/tm.texi: Regenerate.
- * config/aarch64/aarch64.cc (aarch64_attribute_table): Define using
- TARGET_GNU_ATTRIBUTES.
- * config/alpha/alpha.cc (vms_attribute_table): Likewise.
- * config/avr/avr.cc (avr_attribute_table): Likewise.
- * config/bfin/bfin.cc (bfin_attribute_table): Likewise.
- * config/bpf/bpf.cc (bpf_attribute_table): Likewise.
- * config/csky/csky.cc (csky_attribute_table): Likewise.
- * config/epiphany/epiphany.cc (epiphany_attribute_table): Likewise.
- * config/gcn/gcn.cc (gcn_attribute_table): Likewise.
- * config/h8300/h8300.cc (h8300_attribute_table): Likewise.
- * config/loongarch/loongarch.cc (loongarch_attribute_table): Likewise.
- * config/m32c/m32c.cc (m32c_attribute_table): Likewise.
- * config/m32r/m32r.cc (m32r_attribute_table): Likewise.
- * config/m68k/m68k.cc (m68k_attribute_table): Likewise.
- * config/mcore/mcore.cc (mcore_attribute_table): Likewise.
- * config/microblaze/microblaze.cc (microblaze_attribute_table):
- Likewise.
- * config/mips/mips.cc (mips_attribute_table): Likewise.
- * config/msp430/msp430.cc (msp430_attribute_table): Likewise.
- * config/nds32/nds32.cc (nds32_attribute_table): Likewise.
- * config/nvptx/nvptx.cc (nvptx_attribute_table): Likewise.
- * config/riscv/riscv.cc (riscv_attribute_table): Likewise.
- * config/rl78/rl78.cc (rl78_attribute_table): Likewise.
- * config/rx/rx.cc (rx_attribute_table): Likewise.
- * config/s390/s390.cc (s390_attribute_table): Likewise.
- * config/sh/sh.cc (sh_attribute_table): Likewise.
- * config/sparc/sparc.cc (sparc_attribute_table): Likewise.
- * config/stormy16/stormy16.cc (xstormy16_attribute_table): Likewise.
- * config/v850/v850.cc (v850_attribute_table): Likewise.
- * config/visium/visium.cc (visium_attribute_table): Likewise.
- * config/arc/arc.cc (arc_attribute_table): Likewise. Move further
- down file.
- * config/arm/arm.cc (arm_attribute_table): Update for above changes,
- using...
- (arm_gnu_attributes, arm_gnu_attribute_table): ...these new globals.
- * config/i386/i386-options.h (ix86_attribute_table): Delete.
- (ix86_gnu_attribute_table): Declare.
- * config/i386/i386-options.cc (ix86_attribute_table): Replace with...
- (ix86_gnu_attributes, ix86_gnu_attribute_table): ...these two globals.
- * config/i386/i386.cc (ix86_attribute_table): Define as an array of
- scoped_attribute_specs pointers.
- * config/ia64/ia64.cc (ia64_attribute_table): Update for above changes,
- using...
- (ia64_gnu_attributes, ia64_gnu_attribute_table): ...these new globals.
- * config/rs6000/rs6000.cc (rs6000_attribute_table): Update for above
- changes, using...
- (rs6000_gnu_attributes, rs6000_gnu_attribute_table): ...these new
- globals.
-
-2023-12-02 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/riscv/riscv-vsetvl.cc (csetvl_info::parse_insn): Rename
- local variable from demand_flags to dflags, to avoid conflicting
- with (enumeration) type of the same name.
-
-2023-12-02 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
- Supplementary function prototype.
- (loongarch_is_even_extraction): Adjust.
- (loongarch_try_expand_lsx_vshuf_const): Adjust.
- (loongarch_is_extraction_permutation): Adjust.
- (loongarch_expand_vec_perm_const_2): Adjust.
-
-2023-12-02 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.md (v2di): Used to simplify the
- following templates.
- (popcount<mode>2): New.
-
-2023-12-02 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.h (CTZ_DEFINED_VALUE_AT_ZERO): Add
- description.
- (CLZ_DEFINED_VALUE_AT_ZERO): Remove duplicate definition.
-
-2023-12-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112801
- * config/riscv/vector.md: Add !TARGET_64BIT.
-
-2023-12-02 Pan Li <pan2.li@intel.com>
-
- PR target/112743
- * config/riscv/riscv.cc (riscv_legitimize_move): Take the
- exist (U *mode) and handle DFmode like DImode when EEW is
- 32bits for ZVE32F.
-
-2023-12-01 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-fold.h (range_compatible_p): Relocate.
- * value-range.h (range_compatible_p): Here.
- * range-op-mixed.h (operand_equal::operand_check_p): Call
- range_compatible_p rather than comparing precision.
- (operand_not_equal::operand_check_p): Ditto.
- (operand_not_lt::operand_check_p): Ditto.
- (operand_not_le::operand_check_p): Ditto.
- (operand_not_gt::operand_check_p): Ditto.
- (operand_not_ge::operand_check_p): Ditto.
- (operand_plus::operand_check_p): Ditto.
- (operand_abs::operand_check_p): Ditto.
- (operand_minus::operand_check_p): Ditto.
- (operand_negate::operand_check_p): Ditto.
- (operand_mult::operand_check_p): Ditto.
- (operand_bitwise_not::operand_check_p): Ditto.
- (operand_bitwise_xor::operand_check_p): Ditto.
- (operand_bitwise_and::operand_check_p): Ditto.
- (operand_bitwise_or::operand_check_p): Ditto.
- (operand_min::operand_check_p): Ditto.
- (operand_max::operand_check_p): Ditto.
- * range-op.cc (operand_lshift::operand_check_p): Ditto.
- (operand_rshift::operand_check_p): Ditto.
- (operand_logical_and::operand_check_p): Ditto.
- (operand_logical_or::operand_check_p): Ditto.
- (operand_logical_not::operand_check_p): Ditto.
-
-2023-12-01 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR target/112445
- * lra.h (lra): Add one more arg.
- * lra-int.h (lra_verbose, lra_dump_insns): New externals.
- (lra_dump_insns_if_possible): Ditto.
- * lra.cc (lra_dump_insns): Dump all insns.
- (lra_dump_insns_if_possible): Dump all insns for lra_verbose >= 7.
- (lra_verbose): New global.
- (lra): Add new arg. Setup lra_verbose from its value.
- * lra-assigns.cc (lra_split_hard_reg_for): Dump insns if rtl
- was changed.
- * lra-remat.cc (lra_remat): Dump insns if rtl was changed.
- * lra-constraints.cc (lra_inheritance): Dump insns.
- (lra_constraints, lra_undo_inheritance): Dump insns if rtl
- was changed.
- (remove_inheritance_pseudos): Use restore reg if it is set up.
- * ira.cc: (lra): Pass internal_flag_ira_verbose.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- * doc/extend.texi (__builtin_addc, __builtin_addcl, __builtin_addcll,
- __builtin_subc, __builtin_subcl, __builtin_subcll,
- __builtin_stdc_bit_width, __builtin_stdc_count_ones,
- __builtin_stdc_count_zeros, __builtin_stdc_first_leading_one,
- __builtin_stdc_first_leading_zero, __builtin_stdc_first_trailing_one,
- __builtin_stdc_first_trailing_zero, __builtin_stdc_has_single_bit,
- __builtin_stdc_leading_ones, __builtin_stdc_leading_zeros,
- __builtin_stdc_trailing_ones, __builtin_stdc_trailing_zeros,
- __builtin_nvptx_brev, __builtin_nvptx_brevll, __builtin_darn,
- __builtin_darn_raw, __builtin_ia32_vec_ext_v2di,
- __builtin_ia32_crc32qi, __builtin_ia32_crc32hi,
- __builtin_ia32_crc32si, __builtin_ia32_crc32di): Put {}s around
- return type with spaces in it.
- (__builtin_rx_mvfachi, __builtin_rx_mvfacmi): Remove superfluous
- whitespace.
-
-2023-12-01 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-core.h (emit_diagnostic_valist): New overload decl.
- * diagnostic-format-sarif.cc (sarif_builder::make_result_object):
- When we have metadata, call its maybe_add_sarif_properties vfunc.
- * diagnostic-metadata.h (class sarif_object): Forward decl.
- (diagnostic_metadata::~diagnostic_metadata): New.
- (diagnostic_metadata::maybe_add_sarif_properties): New vfunc.
- * diagnostic.cc (emit_diagnostic_valist): New overload.
-
-2023-12-01 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/103533
- * doc/extend.texi: Remove stray reference to
- -fanalyzer-checker=taint.
-
-2023-12-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Support highpart overlap for vx/vf.
-
-2023-12-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Support highpart overlap for indexed load.
-
-2023-12-01 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (vect_get_vec_defs): Re-order arguments.
- * tree-vect-stmts.cc (vect_get_vec_defs): Likewise.
- (vectorizable_condition): Update caller.
- (vectorizable_comparison_1): Likewise.
- (vectorizable_conversion): Specify the vector type to be
- used for invariant/external defs.
- * tree-vect-loop.cc (vect_transform_reduction): Update caller.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112770
- * gimple-lower-bitint.cc (gimple_lower_bitint): When adjusting
- lhs of middle _BitInt setter which ends bb, insert cast on
- the fallthru edge rather than after stmt.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112771
- * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
- Use mp = 1 if it is zero.
-
-2023-12-01 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.cc (bpf_asm_named_section): New function.
- (TARGET_ASM_NAMED_SECTION): Set to bpf_asm_named_section.
-
-2023-12-01 Di Zhao <dizhao@os.amperecomputing.com>
-
- * config/aarch64/aarch64-tuning-flags.def
- (AARCH64_EXTRA_TUNING_OPTION): New tuning option to avoid
- cross-loop FMA.
- * config/aarch64/aarch64.cc
- (aarch64_override_options_internal): Set
- param_avoid_fma_max_bits according to tuning option.
- * config/aarch64/tuning_models/ampere1.h (ampere1_tunings):
- Modify tunings related with FMA.
- * config/aarch64/tuning_models/ampere1a.h (ampere1a_tunings):
- Likewise.
- * config/aarch64/tuning_models/ampere1b.h (ampere1b_tunings):
- Likewise.
-
-2023-12-01 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_expander::result_mode): New member function.
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svld234_impl::expand): Use it.
- * config/aarch64/aarch64-sve-builtins.cc
- (function_expander::get_reg_target): Likewise.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- * gimple-lower-bitint.cc (range_to_prec): Don't return -1 for
- signed types.
- (bitint_large_huge::lower_addsub_overflow): Fix up computation of
- prec2.
- (bitint_large_huge::lower_mul_overflow): Likewise.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- * gimple-lower-bitint.cc (bitint_large_huge::finish_arith_overflow):
- When replacing use_stmt which is gsi_stmt (m_gsi), update m_gsi to
- the new statement.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112750
- * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
- Use NE_EXPR rather than EQ_EXPR for g2 if !single_comparison and
- adjust probabilities.
-
-2023-12-01 Xi Ruoyao <xry111@xry111.site>
-
- * doc/install.texi: Deem srcdir == objdir broken, but objdir
- as a subdirectory of srcdir fine.
-
-2023-12-01 Juergen Christ <jchrist@linux.ibm.com>
-
- PR target/112753
- * config/s390/s390.cc (s390_md_asm_adjust): Return after dealing
- with the outputs, if no further processing of long doubles is
- required.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112725
- * config/s390/s390.cc (s390_invalid_arg_for_unprototyped_fn): Return
- NULL for __builtin_classify_type calls with vector arguments.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document
- -Wdeclaration-missing-parameter-type.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document changes.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document that
- -Wreturn-mismatch is a permerror in C99 and later.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- PR c/91093
- PR c/96284
- * doc/invoke.texi (Warning Options): Document changes.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document changes.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document changes.
-
-2023-12-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112776
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::pre_global_vsetvl_info): Fix ratio.
-
-2023-11-30 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- PR target/111404
- * config/aarch64/aarch64.cc (aarch64_split_compare_and_swap):
- For 128-bit store the loaded value and loop if needed.
-
-2023-11-30 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- PR target/103100
- * config/aarch64/aarch64.md (cpymemdi): Remove pattern condition.
- (setmemdi): Likewise.
- * config/aarch64/aarch64.cc (aarch64_expand_cpymem): Support
- strict-align. Cleanup condition for using MOPS.
- (aarch64_expand_setmem): Likewise.
-
-2023-11-30 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112767
- * tree-scalar-evolution.cc (final_value_replacement_loop):
- Propagate constants to immediate uses immediately.
-
-2023-11-30 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112766
- * gimple-predicate-analysis.cc (find_var_cmp_const):
- Support continuing the iteration and report every candidate.
- (uninit_analysis::overlap): Iterate over all flag var
- candidates.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Add widening overlap of vf2/vf4.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Remove earlyclobber for wx/wf instructions.
-
-2023-11-30 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112733
- * wide-int.cc (wi::mul_internal): Don't allocate twice as much
- space for u, v and r as needed.
- (divmod_internal_2): Change return type from void to int, for n == 1
- return 1, otherwise before writing b_dividend into b_remainder set
- n to MIN (n, m) and at the end return it.
- (wi::divmod_internal): Don't allocate 4 times as much space for
- b_quotient, b_remainder, b_dividend and b_divisor. Set n to
- result of divmod_internal_2.
- (wide_int_cc_tests): Add test for unsigned widest_int
- wi::multiple_of_p of 1 and -128.
-
-2023-11-30 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (sdot_prodv64qi): New expander.
- (sseunpackmodelower): New mode attr.
- (sdot_prod<mode>): Emulate sdot_prodv*qi with sodt_prov*hi
- when TARGET_VNNIINT8 is not available.
-
-2023-11-30 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md: (reduc_plus_scal_<mode>): Use
- vec_extract_lo instead of subreg.
- (reduc_<code>_scal_<mode>): Ditto.
- (reduc_<code>_scal_<mode>): Ditto.
- (reduc_<code>_scal_<mode>): Ditto.
- (reduc_<code>_scal_<mode>): Ditto.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Add widenning overlap.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Fix constraint.
- * config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Rename vconstraint into group_overlap.
- (no,yes): Ditto.
- (none,W21,W42,W84,W43,W86,W87): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Support highpart overlap for vext.vf2
-
-2023-11-29 Philipp Tomsich <philipp.tomsich@vrull.eu>
-
- * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add ampere-1b
- * config/aarch64/aarch64-cost-tables.h: Add ampere1b_extra_costs
- * config/aarch64/aarch64-tune.md: Regenerate
- * config/aarch64/aarch64.cc: Include ampere1b tuning model
- * doc/invoke.texi: Document -mcpu=ampere1b
- * config/aarch64/tuning_models/ampere1b.h: New file.
-
-2023-11-29 David Faust <david.faust@oracle.com>
-
- * config/bpf/bpf.h (ASM_COMMENT_START): Change from ';' to '#'.
-
-2023-11-29 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112725
- * config/rs6000/rs6000.cc (invalid_arg_for_unprototyped_fn): Return
- NULL for __builtin_classify_type calls with vector arguments.
-
-2023-11-29 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/111922
- * ipa-cp.cc (ipa_vr_operation_and_type_effects): Check the
- operands are valid before calling fold_range.
-
-2023-11-29 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (operator_equal::operand_check_p): New.
- (operator_not_equal::operand_check_p): New.
- (operator_lt::operand_check_p): New.
- (operator_le::operand_check_p): New.
- (operator_gt::operand_check_p): New.
- (operator_ge::operand_check_p): New.
- (operator_plus::operand_check_p): New.
- (operator_abs::operand_check_p): New.
- (operator_minus::operand_check_p): New.
- (operator_negate::operand_check_p): New.
- (operator_mult::operand_check_p): New.
- (operator_bitwise_not::operand_check_p): New.
- (operator_bitwise_xor::operand_check_p): New.
- (operator_bitwise_and::operand_check_p): New.
- (operator_bitwise_or::operand_check_p): New.
- (operator_min::operand_check_p): New.
- (operator_max::operand_check_p): New.
- * range-op.cc (range_op_handler::fold_range): Check operand
- parameter types.
- (range_op_handler::op1_range): Ditto.
- (range_op_handler::op2_range): Ditto.
- (range_op_handler::operand_check_p): New.
- (range_operator::operand_check_p): New.
- (operator_lshift::operand_check_p): New.
- (operator_rshift::operand_check_p): New.
- (operator_logical_and::operand_check_p): New.
- (operator_logical_or::operand_check_p): New.
- (operator_logical_not::operand_check_p): New.
- * range-op.h (range_operator::operand_check_p): New.
- (range_op_handler::operand_check_p): New.
-
-2023-11-29 Martin Jambor <mjambor@suse.cz>
-
- PR tree-optimization/112711
- PR tree-optimization/112721
- * tree-sra.cc (build_access_from_call_arg): New parameter
- CAN_BE_RETURNED, disqualify any candidate passed by reference if it is
- true. Adjust leading comment.
- (scan_function): Pass appropriate value to CAN_BE_RETURNED of
- build_access_from_call_arg.
-
-2023-11-29 Thomas Schwinge <thomas@codesourcery.com>
-
- * doc/sourcebuild.texi (Final Actions): Document
- 'only_for_offload_target' wrapper.
-
-2023-11-29 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
-
- PR testsuite/112729
- * doc/sourcebuild.texi (Effective-Target Keywords, Environment
- attributes): Document cfi.
-
-2023-11-29 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110237
- * internal-fn.cc (expand_partial_load_optab_fn): Clear
- MEM_EXPR and MEM_OFFSET.
- (expand_partial_store_optab_fn): Likewise.
-
-2023-11-29 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112733
- * fold-const.cc (multiple_of_p): Pass SIGNED rather than
- UNSIGNED for wi::multiple_of_p on widest_int arguments.
-
-2023-11-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
- kito-cheng <kito.cheng@gmail.com>
-
- PR target/112431
- * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): New register filters.
- * config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Ditto.
- (no,yes): Ditto.
- * config/riscv/vector.md: Support highpart register overlap for vwcvt.
-
-2023-11-29 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_option_override): Eliminate warning.
-
-2023-11-29 Jakub Jelinek <jakub@redhat.com>
-
- PR bootstrap/111601
- * fold-mem-offsets.cc (get_uses): Ignore DEBUG_INSN uses. Otherwise,
- punt if use is in a different basic block from INSN or appears before
- INSN in the same basic block. Formatting fixes.
- (get_single_def_in_bb): Formatting fixes.
- (fold_offsets_1, pass_fold_mem_offsets::execute): Comment formatting
- fixes.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/simd.md (LSX_SCALAR_FRINT): New int iterator.
- (VLSX_FOR_FMODE): New mode attribute.
- (<simd_for_scalar_frint_pattern><mode>2): New expander,
- expanding to vreplvei.{w/d} + frint{rp/rz/rm/rne}.{s.d}.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (lrint_allow_inexact): Remove.
- (<lrint_pattern><ANYF:mode><ANYFI:mode>2): Check if <LRINT>
- == UNSPEC_FTINT instead of <lrint_allow_inexact>.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/lsx.md (bitimm): Move to ...
- (UNSPEC_LSX_VROTR): Remove.
- (lsx_vrotr_<lsxfmt>): Remove.
- (lsx_vrotri_<lsxfmt>): Remove.
- * config/loongarch/lasx.md (UNSPEC_LASX_XVROTR): Remove.
- (lsx_vrotr_<lsxfmt>): Remove.
- (lsx_vrotri_<lsxfmt>): Remove.
- * config/loongarch/simd.md (bitimm): ... here. Expand it to
- cover LASX modes.
- (vrotr<mode>3): New define_insn.
- (vrotri<mode>3): New define_insn.
- * config/loongarch/loongarch-builtins.cc:
- (CODE_FOR_lsx_vrotr_b): Use standard pattern name.
- (CODE_FOR_lsx_vrotr_h): Likewise.
- (CODE_FOR_lsx_vrotr_w): Likewise.
- (CODE_FOR_lsx_vrotr_d): Likewise.
- (CODE_FOR_lasx_xvrotr_b): Likewise.
- (CODE_FOR_lasx_xvrotr_h): Likewise.
- (CODE_FOR_lasx_xvrotr_w): Likewise.
- (CODE_FOR_lasx_xvrotr_d): Likewise.
- (CODE_FOR_lsx_vrotri_b): Define to standard pattern name.
- (CODE_FOR_lsx_vrotri_h): Likewise.
- (CODE_FOR_lsx_vrotri_w): Likewise.
- (CODE_FOR_lsx_vrotri_d): Likewise.
- (CODE_FOR_lasx_xvrotri_b): Likewise.
- (CODE_FOR_lasx_xvrotri_h): Likewise.
- (CODE_FOR_lasx_xvrotri_w): Likewise.
- (CODE_FOR_lasx_xvrotri_d): Likewise.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/simd.md (muh): New code attribute mapping
- any_extend to smul_highpart or umul_highpart.
- (<su>mul<mode>3_highpart): New define_insn.
- * config/loongarch/lsx.md (UNSPEC_LSX_VMUH_S): Remove.
- (UNSPEC_LSX_VMUH_U): Remove.
- (lsx_vmuh_s_<lsxfmt>): Remove.
- (lsx_vmuh_u_<lsxfmt>): Remove.
- * config/loongarch/lasx.md (UNSPEC_LASX_XVMUH_S): Remove.
- (UNSPEC_LASX_XVMUH_U): Remove.
- (lasx_xvmuh_s_<lasxfmt>): Remove.
- (lasx_xvmuh_u_<lasxfmt>): Remove.
- * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vmuh_b):
- Redefine to standard pattern name.
- (CODE_FOR_lsx_vmuh_h): Likewise.
- (CODE_FOR_lsx_vmuh_w): Likewise.
- (CODE_FOR_lsx_vmuh_d): Likewise.
- (CODE_FOR_lsx_vmuh_bu): Likewise.
- (CODE_FOR_lsx_vmuh_hu): Likewise.
- (CODE_FOR_lsx_vmuh_wu): Likewise.
- (CODE_FOR_lsx_vmuh_du): Likewise.
- (CODE_FOR_lasx_xvmuh_b): Likewise.
- (CODE_FOR_lasx_xvmuh_h): Likewise.
- (CODE_FOR_lasx_xvmuh_w): Likewise.
- (CODE_FOR_lasx_xvmuh_d): Likewise.
- (CODE_FOR_lasx_xvmuh_bu): Likewise.
- (CODE_FOR_lasx_xvmuh_hu): Likewise.
- (CODE_FOR_lasx_xvmuh_wu): Likewise.
- (CODE_FOR_lasx_xvmuh_du): Likewise.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112578
- * config/loongarch/lsx.md (UNSPEC_LSX_VFTINT_S,
- UNSPEC_LSX_VFTINTRNE, UNSPEC_LSX_VFTINTRP,
- UNSPEC_LSX_VFTINTRM, UNSPEC_LSX_VFRINTRNE_S,
- UNSPEC_LSX_VFRINTRNE_D, UNSPEC_LSX_VFRINTRZ_S,
- UNSPEC_LSX_VFRINTRZ_D, UNSPEC_LSX_VFRINTRP_S,
- UNSPEC_LSX_VFRINTRP_D, UNSPEC_LSX_VFRINTRM_S,
- UNSPEC_LSX_VFRINTRM_D): Remove.
- (ILSX, FLSX): Move into ...
- (VIMODE): Move into ...
- (FRINT_S, FRINT_D): Remove.
- (frint_pattern_s, frint_pattern_d, frint_suffix): Remove.
- (lsx_vfrint_<flsxfmt>, lsx_vftint_s_<ilsxfmt>_<flsxfmt>,
- lsx_vftintrne_w_s, lsx_vftintrne_l_d, lsx_vftintrp_w_s,
- lsx_vftintrp_l_d, lsx_vftintrm_w_s, lsx_vftintrm_l_d,
- lsx_vfrintrne_s, lsx_vfrintrne_d, lsx_vfrintrz_s,
- lsx_vfrintrz_d, lsx_vfrintrp_s, lsx_vfrintrp_d,
- lsx_vfrintrm_s, lsx_vfrintrm_d,
- <FRINT_S:frint_pattern_s>v4sf2,
- <FRINT_D:frint_pattern_d>v2df2, round<mode>2,
- fix_trunc<mode>2): Remove.
- * config/loongarch/lasx.md: Likewise.
- * config/loongarch/simd.md: New file.
- (ILSX, ILASX, FLSX, FLASX, VIMODE): ... here.
- (IVEC, FVEC): New mode iterators.
- (VIMODE): ... here. Extend it to work for all LSX/LASX vector
- modes.
- (x, wu, simd_isa, WVEC, vimode, simdfmt, simdifmt_for_f,
- elebits): New mode attributes.
- (UNSPEC_SIMD_FRINTRP, UNSPEC_SIMD_FRINTRZ, UNSPEC_SIMD_FRINT,
- UNSPEC_SIMD_FRINTRM, UNSPEC_SIMD_FRINTRNE): New unspecs.
- (SIMD_FRINT): New int iterator.
- (simd_frint_rounding, simd_frint_pattern): New int attributes.
- (<simd_isa>_<x>vfrint<simd_frint_rounding>_<simdfmt>): New
- define_insn template for frint instructions.
- (<simd_isa>_<x>vftint<simd_frint_rounding>_<simdifmt_for_f>_<simdfmt>):
- Likewise, but for ftint instructions.
- (<simd_frint_pattern><mode>2): New define_expand with
- flag_fp_int_builtin_inexact checked.
- (l<simd_frint_pattern><mode><vimode>2): Likewise.
- (ftrunc<mode>2): New define_expand. It does not require
- flag_fp_int_builtin_inexact.
- (fix_trunc<mode><vimode>2): New define_insn_and_split. It does
- not require flag_fp_int_builtin_inexact.
- (include): Add lsx.md and lasx.md.
- * config/loongarch/loongarch.md (include): Include simd.md,
- instead of including lsx.md and lasx.md directly.
- * config/loongarch/loongarch-builtins.cc
- (CODE_FOR_lsx_vftint_w_s, CODE_FOR_lsx_vftint_l_d,
- CODE_FOR_lasx_xvftint_w_s, CODE_FOR_lasx_xvftint_l_d):
- Remove.
-
-2023-11-29 Alexandre Oliva <oliva@adacore.com>
-
- * doc/extend.texi (hardbool): New type attribute.
- * doc/invoke.texi (-ftrivial-auto-var-init): Document
- representation vs values.
-
-2023-11-29 Alexandre Oliva <oliva@adacore.com>
-
- * expr.cc (emit_block_move_hints): Take ctz of len. Obey
- -finline-stringops. Use oriented or sized loop.
- (emit_block_move): Take ctz of len, and pass it on.
- (emit_block_move_via_sized_loop): New.
- (emit_block_move_via_oriented_loop): New.
- (emit_block_move_via_loop): Take incr. Move an incr-sized
- block per iteration.
- (emit_block_cmp_via_cmpmem): Take ctz of len. Obey
- -finline-stringops.
- (emit_block_cmp_via_loop): New.
- * expr.h (emit_block_move): Add ctz of len defaulting to zero.
- (emit_block_move_hints): Likewise.
- (emit_block_cmp_hints): Likewise.
- * builtins.cc (expand_builtin_memory_copy_args): Pass ctz of
- len to emit_block_move_hints.
- (try_store_by_multiple_pieces): Support starting with a loop.
- (expand_builtin_memcmp): Pass ctz of len to
- emit_block_cmp_hints.
- (expand_builtin): Allow inline expansion of memset, memcpy,
- memmove and memcmp if requested.
- * common.opt (finline-stringops): New.
- (ilsop_fn): New enum.
- * flag-types.h (enum ilsop_fn): New.
- * doc/invoke.texi (-finline-stringops): Add.
-
-2023-11-29 Pan Li <pan2.li@intel.com>
-
- PR target/112743
- * config/riscv/riscv-string.cc (expand_block_move): Add
- precondition check for exact_div.
-
-2023-11-28 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md: Make output template whitespace consistent.
-
-2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * varasm.cc (assemble_external_libcall): Refer in assert only ifdef
- ASM_OUTPUT_EXTERNAL.
-
-2023-11-28 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR tree-optimization/112738
- * match.pd (`(nop_convert)-(convert)a`): Reject
- when the outer type is boolean.
-
-2023-11-28 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112732
- * tree.cc (build_opaque_vector_type): Reset TYPE_ALIAS_SET
- of the newly built type.
-
-2023-11-28 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112494
- * config/i386/i386.md (cmpstrnqi_1): Set FLAGS_REG to its previous
- value when operand 2 equals zero.
- (*cmpstrnqi_1): Ditto.
- (*cmpstrnqi_1 peephole2): Ditto.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- Revert:
- 2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf.cc (bpf_output_call): Report error in case the
- function call is for a builtin.
- (bpf_external_libcall): Added target hook to detect and report
- error when other external calls that are not builtins.
-
-2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- PR target/109253
- * varasm.cc (pending_libcall_symbols): New variable.
- (process_pending_assemble_externals): Process
- pending_libcall_symbols.
- (assemble_external_libcall): Defer emitting external libcall
- symbols to process_pending_assemble_externals.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * btfout.cc (btf_calc_num_vbytes): Fixed logic for enum64.
- (btf_asm_enum_const): Corrected logic for enum64 and smaller
- than 4 bytes values.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf.cc (bpf_output_call): Report error in case the
- function call is for a builtin.
- (bpf_external_libcall): Added target hook to detect and report
- error when other external calls that are not builtins.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf.cc (bpf_use_by_pieces_infrastructure_p): Added
- function to bypass default behaviour.
- * config/bpf/bpf.h (COMPARE_MAX_PIECES): Defined to 1024 bytes.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/core-builtins.cc (core_mark_as_access_index):
- Corrected check.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/core-builtins.cc
- (bpf_resolve_overloaded_core_builtin): Removed call.
- (execute_lower_bpf_core): Added all to remove_parser_plugin.
-
-2023-11-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112694
- * config/riscv/riscv-v.cc (expand_vec_perm_const): Disallow poly size (1, 1) VLA SLP.
-
-2023-11-28 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112719
- * match.pd (parity(X)^parity(Y) -> parity(X^Y)): Handle case of
- mismatched types.
- * gimple-match-exports.cc (build_call_internal): Add special-case for
- bit query ifns on large/huge BITINT_TYPE before bitint lowering.
-
-2023-11-28 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112719
- * match.pd (popcount (X) + popcount (Y) -> POPCOUNT (X | Y)): Deal
- with argument types with different precisions.
-
-2023-11-28 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/109077
- * Makefile.in (PLUGIN_HEADERS): Add analyzer headers.
- (install-plugin): Keep the directory structure for files in
- "analyzer".
-
-2023-11-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112713
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix regression.
-
-2023-11-28 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc (layout::maybe_add_location_range):
- Don't print annotation lines for ranges when there's no column
- info.
- (selftest::test_one_liner_no_column): New.
- (selftest::test_diagnostic_show_locus_one_liner): Call it.
-
-2023-11-28 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_get_location_text): Convert to...
- (diagnostic_context::get_location_text): ...this, and convert
- return type from char * to label_text.
- (diagnostic_build_prefix): Update for above change.
- (default_diagnostic_start_span_fn): Likewise.
- (selftest::assert_location_text): Likewise.
- * diagnostic.h (diagnostic_context::get_location_text): New decl.
-
-2023-11-27 Andrew Pinski <quic_apinski@quicinc.com>
-
- * config/aarch64/aarch64.cc (aarch64_if_then_else_costs):
- Handle csinv/csinc case of 1/-1.
-
-2023-11-27 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
- Richard Sandiford <richard.sandiford@arm.com>
-
- PR middle-end/111754
- * fold-const.cc (fold_vec_perm_cst): Set result's encoding to sel's
- encoding, and set res_nelts_per_pattern to 2 if sel contains stepped
- sequence but input vectors do not.
- (test_nunits_min_2): New test Case 8.
- (test_nunits_min_4): New tests Case 8 and Case 9.
-
-2023-11-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_needs_frame_chain): Do not
- force frame chain for eh_return.
-
-2023-11-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_eh_return_handler_rtx):
- Remove.
- * config/aarch64/aarch64.cc (aarch64_return_address_signing_enabled):
- Sign return address even in functions with eh_return.
- (aarch64_expand_epilogue): Conditionally return with br or ret.
- (aarch64_eh_return_handler_rtx): Remove.
- * config/aarch64/aarch64.h (EH_RETURN_TAKEN_RTX): Define.
- (EH_RETURN_STACKADJ_RTX): Change to R5.
- (EH_RETURN_HANDLER_RTX): Change to R6.
- * df-scan.cc: Handle EH_RETURN_TAKEN_RTX.
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in: Document EH_RETURN_TAKEN_RTX.
- * except.cc (expand_eh_return): Handle EH_RETURN_TAKEN_RTX.
-
-2023-11-27 Thomas Schwinge <thomas@codesourcery.com>
-
- * config.gcc <amdgcn-*-amdhsa> (extra_gcc_objs): Don't set.
- * config/gcn/driver-gcn.cc: Remove.
- * config/gcn/gcn-hsa.h (ASM_SPEC, EXTRA_SPEC_FUNCTIONS): Remove
- 'last_arg' spec function.
- * config/gcn/t-gcn-hsa (driver-gcn.o): Remove.
-
-2023-11-27 Thomas Schwinge <thomas@codesourcery.com>
-
- PR target/112669
- * config/gcn/gcn.opt (march=, mtune=): Tag as 'Negative' of
- themselves.
-
-2023-11-27 Samuel Thibault <samuel.thibault@gnu.org>
-
- * config/i386/gnu.h: Use PIE_SPEC, add static-pie case.
- * config/i386/gnu64.h: Use PIE_SPEC, add static-pie case.
-
-2023-11-27 Samuel Thibault <samuel.thibault@gnu.org>
-
- * config/i386/t-gnu64: New file.
- * config.gcc [x86_64-*-gnu*]: Add i386/t-gnu64 to
- tmake_file.
-
-2023-11-27 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/106326
- * config/aarch64/aarch64-sve-builtins.h (is_ptrue): Declare.
- * config/aarch64/aarch64-sve-builtins.cc (is_ptrue): New function.
- (gimple_folder::redirect_pred_x): Likewise.
- (gimple_folder::fold): Use it.
-
-2023-11-27 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h (vector_cst_all_same): Declare.
- * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same): New
- function, a generalized replacement of...
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svlast_impl::vect_all_same): ...this.
- (svlast_impl::fold): Update accordingly.
-
-2023-11-27 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112653
- * gimple-ssa.h (gimple_df): Add escaped_return solution.
- * tree-ssa.cc (init_tree_ssa): Reset it.
- (delete_tree_ssa): Likewise.
- * tree-ssa-structalias.cc (escaped_return_id): New.
- (find_func_aliases): Handle non-IPA return stmts by
- adding to ESCAPED_RETURN.
- (set_uids_in_ptset): Adjust HEAP escaping to also cover
- escapes through return.
- (init_base_vars): Initialize ESCAPED_RETURN.
- (compute_points_to_sets): Replace ESCAPED post-processing
- with recording the ESCAPED_RETURN solution.
- * tree-ssa-alias.cc (ref_may_alias_global_p_1): Check
- the ESCAPED_RETUNR solution.
- (dump_alias_info): Dump it.
- * cfgexpand.cc (update_alias_info_with_stack_vars): Update it.
- * ipa-icf.cc (sem_item_optimizer::fixup_points_to_sets):
- Likewise.
- * tree-inline.cc (expand_call_inline): Reset it.
- * tree-parloops.cc (parallelize_loops): Likewise.
- * tree-sra.cc (maybe_add_sra_candidate): Check it.
-
-2023-11-27 Richard Biener <rguenther@suse.de>
- Richard Sandiford <richard.sandiford@arm.com>
-
- PR tree-optimization/112661
- * tree-vect-slp.cc (vect_get_and_check_slp_defs): Defer duplicate-and-
- interleave test to...
- (vect_build_slp_tree_2): ...here, once we have all the operands.
- Skip the test for uniform vectors.
- (vect_create_constant_vectors): Detect uniform vectors. Avoid
- redundant conversions in that case. Use gimple_build_vector_from_val
- to build the vector.
-
-2023-11-27 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.cc (excl_hash_traits): Delete.
- (test_attribute_exclusions): Use pair_hash and nofree_string_hash
- instead.
-
-2023-11-27 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Disallow TImode.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtin-types.def (BT_FN_UV8HI_UV8HI_UINT):
- Add missing builtin type.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtin-types.def: Remove types.
- * config/s390/s390-builtins.def (O_U64): Remove 64-bit literal support.
- Don't restrict s390_vec_rli and s390_verll[bhfg] to immediates.
- * config/s390/s390.cc (s390_const_operand_ok): Remove 64-bit
- literal support.
-
-2023-11-27 Alex Coplan <alex.coplan@arm.com>
- Iain Sandoe <iain@sandoe.co.uk>
-
- PR c++/60512
- * doc/cpp.texi: Document __has_{feature,extension}.
-
-2023-11-27 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112706
- * match.pd (ptr + o ==/!=/- ptr + o'): New patterns.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtin-types.def: Add/remove types.
- * config/s390/s390-builtins.def
- (s390_vclfnhs,s390_vclfnls,s390_vcrnfs,s390_vcfn,s390_vcnf):
- Replace type V8HI with UV8HI.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtins.def
- (s390_vcefb,s390_vcdgb,s390_vcelfb,s390_vcdlgb,s390_vcfeb,s390_vcgdb,
- s390_vclfeb,s390_vclgdb): Remove flags for non-existing operands
- 2 and 3.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.md (*cmphi_ccu): For immediate operand 1 make
- use of constraint n instead of D and chop of high bits in the
- output template.
-
-2023-11-27 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112300
- * config.gcc (mips*-sde-elf*): Append to tm_defines rather than
- overwriting them.
-
-2023-11-27 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md
- (mask_len_gather_load<RATIO1:mode><RATIO1:mode>):
- Remove gather_scatter_valid_offset_mode_p.
- (mask_len_gather_load<mode><mode>): Ditto.
- (mask_len_scatter_store<RATIO1:mode><RATIO1:mode>): Ditto.
- (mask_len_scatter_store<mode><mode>): Ditto.
- * config/riscv/predicates.md (const_1_or_8_operand): New predicate.
- (vector_gs_scale_operand_64): Remove.
- * config/riscv/riscv-protos.h (gather_scatter_valid_offset_mode_p): Remove.
- * config/riscv/riscv-v.cc (expand_gather_scatter): Refine code.
- (gather_scatter_valid_offset_mode_p): Remove.
- * config/riscv/vector-iterators.md: Fix iterator bugs.
-
-2023-11-27 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_ext_version_table): Set version to ratified 2.0.
- (riscv_subset_list::parse_std_ext): Allow RV64E.
- * config.gcc: Parse base ISA 'rv64e' and ABI 'lp64e'.
- * config/riscv/arch-canonicalize: Parse base ISA 'rv64e'.
- * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
- Define different macro per XLEN. Add handling for ABI_LP64E.
- * config/riscv/riscv-d.cc (riscv_d_handle_target_float_abi):
- Add handling for ABI_LP64E.
- * config/riscv/riscv-opts.h (enum riscv_abi_type): Add ABI_LP64E.
- * config/riscv/riscv.cc (riscv_option_override): Enhance error
- handling to support RV64E and LP64E.
- (riscv_conditional_register_usage): Change "RV32E" in a comment
- to "RV32E/RV64E".
- * config/riscv/riscv.h
- (UNITS_PER_FP_ARG): Add handling for ABI_LP64E.
- (STACK_BOUNDARY): Ditto.
- (ABI_STACK_BOUNDARY): Ditto.
- (MAX_ARGS_IN_REGISTERS): Ditto.
- (ABI_SPEC): Add support for "lp64e".
- * config/riscv/riscv.opt: Parse -mabi=lp64e as ABI_LP64E.
- * doc/invoke.texi: Add documentation of the LP64E ABI.
-
-2023-11-27 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf-helpers.h: Remove.
- * config.gcc: Adapt accordingly.
-
-2023-11-27 Guo Jie <guojie@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_split_plus_constant):
- avoid left shift of negative value -0x8000.
-
-2023-11-27 Guo Jie <guojie@loongson.cn>
-
- * config/loongarch/loongarch.cc
- (enum loongarch_load_imm_method): Add new method.
- (loongarch_build_integer): Add relevant implementations for
- new method.
- (loongarch_move_integer): Ditto.
-
-2023-11-26 Alexander Monakov <amonakov@ispras.ru>
-
- * sort.cc: Use 'sorting networks' in comments.
-
-2023-11-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112599
- * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Add slidedown.
- (vlmax_ta_p): Ditto.
- (pass_avlprop::get_vlmax_ta_preferred_avl): Ditto.
-
-2023-11-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-avlprop.cc (alv_can_be_propagated_p): Fix typo.
- (avl_can_be_propagated_p): Ditto.
- (vlmax_ta_p): Ditto.
-
-2023-11-25 Gerald Pfeifer <gerald@pfeifer.com>
-
- PR other/69374
- * doc/install.texi (Downloading the source): Sort the list of
- front ends and add D, Go, and Modula-2.
-
-2023-11-25 Gerald Pfeifer <gerald@pfeifer.com>
-
- PR target/69374
- * doc/install.texi (Specific) <*-*-freebsd*>: Remove older
- contents referencing GCC 4.x.
-
-2023-11-25 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/standards.texi (Standards): Update ISO C++ reference.
-
-2023-11-25 Jakub Jelinek <jakub@redhat.com>
-
- PR target/111408
- * config/i386/i386.md (*jcc_bt<mode>_mask,
- *jcc_bt<SWI48:mode>_mask_1): Add (const_int 0) as expected
- second operand of bt_comparison_operator.
-
-2023-11-25 Andrew Pinski <pinskia@gmail.com>
- Jakub Jelinek <jakub@redhat.com>
-
- PR target/109977
- * config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use <vwcore>
- rather than %<vw> for alternative with r constraint on input operand.
-
-2023-11-24 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/install.texi (amdgcn-*-amdhsa): Fix URL to ROCm;
- change 'in the future' to 'in LLVM 18'.
-
-2023-11-24 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa.cc (pa_emit_move_sequence): Use INT14_OK_STRICT
- in a couple of places.
-
-2023-11-24 Martin Jambor <mjambor@suse.cz>
-
- PR middle-end/109849
- * tree-sra.cc (passed_by_ref_in_call): New.
- (sra_initialize): Allocate passed_by_ref_in_call.
- (sra_deinitialize): Free passed_by_ref_in_call.
- (create_access): Add decl pool candidates only if they are not
- already candidates.
- (build_access_from_expr_1): Bail out on ADDR_EXPRs.
- (build_access_from_call_arg): New function.
- (asm_visit_addr): Rename to scan_visit_addr, change the
- disqualification dump message.
- (scan_function): Check taken addresses for all non-call statements,
- including phi nodes. Process all call arguments, including the static
- chain, build_access_from_call_arg.
- (maybe_add_sra_candidate): Relax need_to_live_in_memory check to allow
- non-escaped local variables.
- (sort_and_splice_var_accesses): Disallow smaller-than-precision
- replacements for aggregates passed by reference to functions.
- (sra_modify_expr): Use a separate stmt iterator for adding satements
- before the processed statement and after it.
- (enum out_edge_check): New type.
- (abnormal_edge_after_stmt_p): New function.
- (sra_modify_call_arg): New function.
- (sra_modify_assign): Adjust calls to sra_modify_expr.
- (sra_modify_function_body): Likewise, use sra_modify_call_arg to
- process call arguments, including the static chain.
-
-2023-11-24 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112686
- * config/i386/i386.cc (ix86_expand_split_stack_prologue): Load
- function address to a register for ix86_cmodel == CM_LARGE.
-
-2023-11-24 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/invoke.texi (-Wopenmp): Add.
- * gimplify.cc (gimplify_omp_for): Add OPT_Wopenmp to warning_at.
- * omp-expand.cc (expand_omp_ordered_sink): Likewise.
- * omp-general.cc (omp_check_context_selector): Likewise.
- * omp-low.cc (scan_omp_for, check_omp_nesting_restrictions,
- lower_omp_ordered_clauses): Likewise.
- * omp-simd-clone.cc (simd_clone_clauses_extract): Likewise.
-
-2023-11-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112694
- * config/riscv/riscv-v.cc (preferred_simd_mode): Allow poly_int (1,1) vectors.
-
-2023-11-24 Alexander Monakov <amonakov@ispras.ru>
-
- * config.in: Regenerate.
- * configure: Regenerate.
- * configure.ac: Delete manual checks for old Valgrind headers.
- * system.h (VALGRIND_MAKE_MEM_NOACCESS): Delete.
- (VALGRIND_MAKE_MEM_DEFINED): Delete.
- (VALGRIND_MAKE_MEM_UNDEFINED): Delete.
- (VALGRIND_MALLOCLIKE_BLOCK): Delete.
- (VALGRIND_FREELIKE_BLOCK): Delete.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112681
- * config/i386/i386-expand.cc (ix86_expand_branch): Use
- ix86_expand_vector_logical_operator to expand vector XOR rather than
- gen_rtx_SET on gen_rtx_XOR.
-
-2023-11-24 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/access-utils.h (filter_accesses): New.
- (remove_regno_access): New.
- (check_remove_regno_access): New.
- * rtl-ssa/accesses.cc (rtl_ssa::remove_note_accesses_base): Use
- new filter_accesses helper.
-
-2023-11-24 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/accesses.cc (function_info::create_set): New.
- * rtl-ssa/accesses.h (access_info::is_temporary): New.
- * rtl-ssa/changes.cc (move_insn): Handle new (temporary) insns.
- (function_info::finalize_new_accesses): Handle new/temporary
- user-created accesses.
- (function_info::apply_changes_to_insn): Ensure m_is_temp flag
- on new insns gets cleared.
- (function_info::change_insns): Handle new/temporary insns.
- (function_info::create_insn): New.
- * rtl-ssa/changes.h (class insn_change): Make function_info a
- friend class.
- * rtl-ssa/functions.h (function_info): Declare new entry points:
- create_set, create_insn. Declare new change_alloc helper.
- * rtl-ssa/insns.cc (insn_info::print_full): Identify temporary insns in
- dump.
- * rtl-ssa/insns.h (insn_info): Add new m_is_temp flag and accompanying
- is_temporary accessor.
- * rtl-ssa/internals.inl (insn_info::insn_info): Initialize m_is_temp to
- false.
- * rtl-ssa/member-fns.inl (function_info::change_alloc): New.
- * rtl-ssa/movement.h (restrict_movement_for_defs_ignoring): Add
- handling for temporary defs.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112673
- * match.pd (bit_field_ref (vce @0) -> bit_field_ref @0): Only simplify
- if either @0 doesn't have scalar integral type or if it has mode
- precision.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112679
- * gimple-lower-bitint.cc (gimple_lower_bitint): Also stop first loop on
- floating point SSA_NAME set in FLOAT_EXPR assignment from BITINT_TYPE
- INTEGER_CST. Set has_large_huge for those if that BITINT_TYPE is large
- or huge. Set kind to such FLOAT_EXPR assignment rhs1 BITINT_TYPE's kind.
-
-2023-11-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112677
- * tree-vect-loop.cc (vectorizable_reduction): Use alloca
- to allocate vectype_op.
-
-2023-11-24 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * expr.cc (by_pieces_ninsns): Include by pieces compare when
- do the adjustment for overlap operations. Replace mov_optab
- checks with gcc assertion.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112668
- * gimple-iterator.h (gsi_end, gsi_end_bb): New inline functions.
- * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): After
- temporarily adding statements after m_init_gsi, update m_init_gsi
- such that later additions after it will be after the added statements.
- (bitint_large_huge::handle_load): Likewise. When splitting
- gsi_bb (m_init_gsi) basic block, update m_preheader_bb if needed
- and update saved m_gsi as well if needed.
- (bitint_large_huge::lower_mergeable_stmt,
- bitint_large_huge::lower_comparison_stmt,
- bitint_large_huge::lower_mul_overflow,
- bitint_large_huge::lower_bit_query): Use gsi_end_bb.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/112619
- * tree.cc (try_catch_may_fallthru): If second operand of
- TRY_CATCH_EXPR is not a STATEMENT_LIST, handle it as if it was a
- STATEMENT_LIST containing a single statement.
-
-2023-11-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112344
- * tree-chrec.cc (chrec_apply): Only use an unsigned add
- when the overall increment doesn't fit the signed type.
-
-2023-11-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112599
- * config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns): New function.
- (expand_vec_perm_const_1): Add new optimization.
-
-2023-11-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (shuffle_bswap_pattern): Disable for NUNIT < 4.
-
-2023-11-24 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/112643
- * config/i386/driver-i386.cc (check_avx10_avx512_features):
- Renamed to ...
- (check_avx512_features): this and remove avx10 check.
- (host_detect_local_cpu): Never append -mno-avx10.1-{256,512} to
- avoid emitting warnings when building GCC with native arch.
- * config/i386/i386-builtin.def (BDESC): Add missing AVX512VL for
- 128/256 bit builtin for AVX512VP2INTERSECT.
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Also check whether the AVX512 flags is set when trying to reset.
- * config/i386/i386.h
- (PTA_SKYLAKE_AVX512): Add missing PTA_EVEX512.
- (PTA_ZNVER4): Ditto.
-
-2023-11-23 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/86776
- * config/avr/avr.cc (TARGET_HAVE_SPECULATION_SAFE_VALUE): Define
- to speculation_safe_value_not_needed.
-
-2023-11-23 Marek Polacek <polacek@redhat.com>
-
- * common.opt (Whardened, fhardened): New options.
- * config.in: Regenerate.
- * config/bpf/bpf.cc: Include "opts.h".
- (bpf_option_override): If flag_stack_protector_set_by_fhardened_p, do
- not inform that -fstack-protector does not work.
- * config/i386/i386-options.cc (ix86_option_override_internal): When
- -fhardened, maybe enable -fcf-protection=full.
- * config/linux-protos.h (linux_fortify_source_default_level): Declare.
- * config/linux.cc (linux_fortify_source_default_level): New.
- * config/linux.h (TARGET_FORTIFY_SOURCE_DEFAULT_LEVEL): Redefine.
- * configure: Regenerate.
- * configure.ac: Check if the linker supports '-z now' and '-z relro'.
- Check if -fhardened is supported on $target_os.
- * doc/invoke.texi: Document -fhardened and -Whardened.
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in (TARGET_FORTIFY_SOURCE_DEFAULT_LEVEL): Add.
- * gcc.cc (driver_handle_option): Remember if any link options or -static
- were specified on the command line.
- (process_command): When -fhardened, maybe enable -pie and
- -Wl,-z,relro,-z,now.
- * opts.cc (flag_stack_protector_set_by_fhardened_p): New global.
- (finish_options): When -fhardened, enable
- -ftrivial-auto-var-init=zero and -fstack-protector-strong.
- (print_help_hardened): New.
- (print_help): Call it.
- * opts.h (flag_stack_protector_set_by_fhardened_p): Declare.
- * target.def (fortify_source_default_level): New target hook.
- * targhooks.cc (default_fortify_source_default_level): New.
- * targhooks.h (default_fortify_source_default_level): Declare.
- * toplev.cc (process_options): When -fhardened, enable
- -fstack-clash-protection. If flag_stack_protector_set_by_fhardened_p,
- do not warn that -fstack-protector not supported for this target.
- Don't enable -fhardened when !HAVE_FHARDENED_SUPPORT.
-
-2023-11-23 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-functions.h
- (full_width_access::memory_vector_mode): Add default clause.
-
-2023-11-23 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112672
- * config/i386/i386.md (parityhi2):
- Use temporary register in the call to gen_parityhi2_cmp.
-
-2023-11-23 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/89316
- * config/i386/i386.cc (ix86_expand_split_stack_prologue): Obtain
- scratch regno when flag_force_indirect_call is set. On 64-bit
- targets, call __morestack_large_model when flag_force_indirect_call
- is set and on 32-bit targets with -fpic, manually expand PIC sequence
- to call __morestack. Move the function address to an indirect
- call scratch register.
-
-2023-11-23 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- PR tree-optimization/112678
- * tree-profile.cc (tree_profiling): Do not use atomic operations
- for -fprofile-update=single.
-
-2023-11-23 Juergen Christ <jchrist@linux.ibm.com>
-
- * config/s390/s390-c.cc (s390_cpu_cpp_builtins): Define
- __GCC_ASM_FLAG_OUTPUTS__.
- * config/s390/s390.cc (s390_canonicalize_comparison): More
- UNSPEC_CC_TO_INT cases.
- (s390_md_asm_adjust): Implement flags output.
- * config/s390/s390.md (ccstore4): Allow mask operands.
- * doc/extend.texi: Document flags output.
-
-2023-11-23 Juergen Christ <jchrist@linux.ibm.com>
-
- * config/s390/s390.md: Split TImode loads.
-
-2023-11-23 Juergen Christ <jchrist@linux.ibm.com>
-
- * config/s390/vector.md: (*vec_extract) Fix.
-
-2023-11-23 Di Zhao <dizhao@os.amperecomputing.com>
-
- * tree-ssa-reassoc.cc (get_reassociation_width): check
- for loop dependent FMAs.
- (reassociate_bb): For 3 ops, refine the condition to call
- swap_ops_for_binary_stmt.
-
-2023-11-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (emit_vec_extract): New function.
- * config/riscv/riscv-v.cc (emit_vec_extract): Ditto.
- * config/riscv/riscv.cc (riscv_legitimize_move): Refine codes.
-
-2023-11-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112599
- PR target/112670
- * config/riscv/riscv-avlprop.cc (alv_can_be_propagated_p): New function.
- (vlmax_ta_p): Disable vrgather AVL propagation.
-
-2023-11-23 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112336
- * expr.cc (EXTEND_BITINT): Don't call reduce_to_bit_field_precision
- if modifier is EXPAND_INITIALIZER.
-
-2023-11-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Refine codes.
- (emit_vlmax_masked_gather_mu_insn): Ditto.
- (modulo_sel_indices): Ditto.
- (expand_vec_perm): Ditto.
- (shuffle_generic_patterns): Ditto.
-
-2023-11-23 Jakub Jelinek <jakub@redhat.com>
-
- * doc/extend.texi (__builtin_stdc_bit_ceil, __builtin_stdc_bit_floor,
- __builtin_stdc_bit_width, __builtin_stdc_count_ones,
- __builtin_stdc_count_zeros, __builtin_stdc_first_leading_one,
- __builtin_stdc_first_leading_zero, __builtin_stdc_first_trailing_one,
- __builtin_stdc_first_trailing_zero, __builtin_stdc_has_single_bit,
- __builtin_stdc_leading_ones, __builtin_stdc_leading_zeros,
- __builtin_stdc_trailing_ones, __builtin_stdc_trailing_zeros): Document.
-
-2023-11-23 Richard Biener <rguenther@suse.de>
-
- PR middle-end/32667
- * doc/md.texi (cpymem): Document that exact overlap of source
- and destination needs to work.
- * doc/standards.texi (ffreestanding): Mention memcpy is required
- to handle the exact overlap case.
-
-2023-11-23 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/110348
- * doc/invoke.texi (-Wno-c++26-extensions): Document.
-
-2023-11-23 Manolis Tsamis <manolis.tsamis@vrull.eu>
-
- * ifcvt.cc (noce_convert_multiple_sets_1): Remove old code.
-
-2023-11-23 Pan Li <pan2.li@intel.com>
-
- PR target/111720
- * dse.cc (get_stored_val): Allow vector mode if read size is
- less than or equal to stored size.
-
-2023-11-23 Costas Argyris <costas.argyris@gmail.com>
-
- * configure.ac: Handle new --enable-win32-utf8-manifest
- option.
- * config.host: allow win32 utf8 manifest to be disabled
- by user.
- * configure: Regenerate.
-
-2023-11-22 John David Anglin <danglin@gcc.gnu.org>
-
- PR target/112592
- * config/pa/pa.h (MAX_FIXED_MODE_SIZE): Define.
-
-2023-11-22 John David Anglin <danglin@gcc.gnu.org>
-
- PR target/112617
- * config/pa/predicates.md (integer_store_memory_operand): Return
- true for REG+D addresses when reload_in_progress is true.
-
-2023-11-22 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112344
- * tree-chrec.cc (chrec_apply): Perform the overall increment
- calculation and increment in an unsigned type.
-
-2023-11-22 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md (*mov<mode>_4reg): Disparage AVGPR use when a
- reload is required.
-
-2023-11-22 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/112610
- * ira-costs.cc: (find_costs_and_classes): Remove arg.
- Use ira_dump_file for printing.
- (print_allocno_costs, print_pseudo_costs): Ditto.
- (ira_costs): Adjust call of find_costs_and_classes.
- (ira_set_pseudo_classes): Set up and restore ira_dump_file.
-
-2023-11-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112598
- * config/riscv/riscv-v.cc (shuffle_compress_patterns): Fix vcompress bug.
-
-2023-11-22 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-simd.md
- (aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip,
- aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip): Split into...
- (aarch64_uaddw<mode>_lo_zip, aarch64_uaddw<mode>_hi_zip,
- "aarch64_usubw<mode>_lo_zip, "aarch64_usubw<mode>_hi_zip): ... This.
- * config/aarch64/iterators.md (PERM_EXTEND, perm_index): Remove.
- (perm_hilo): Remove UNSPEC_ZIP1, UNSPEC_ZIP2.
-
-2023-11-22 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins.cc
- (function_resolver::infer_pointer_type): Remove spurious line.
-
-2023-11-22 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/lsx.md (vec_perm<mode:LSX>): Make the
- selector VIMODE.
- * config/loongarch/loongarch.cc (loongarch_expand_vec_perm):
- Use the mode of the selector (instead of the shuffled vector)
- for truncating it. Operate on subregs in the selector mode if
- the shuffled vector has a different mode (i. e. it's a
- floating-point vector).
-
-2023-11-22 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (push2_di): Adjust operand order for AT&T
- syntax.
- (pop2_di): Likewise.
- (push2p_di): Likewise.
- (pop2p_di): Likewise.
-
-2023-11-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112598
- * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Adapt the priority.
- (shuffle_generic_patterns): Fix permutation indice bug.
- * config/riscv/vector-iterators.md: Fix VEI16 bug.
-
-2023-11-22 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (cbranch<mode>4): Extend to Vector
- HI/QImode.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- PR target/111815
- * config/vax/vax.cc (index_term_p): Only accept the index scaler
- as the RHS operand to ASHIFT.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/predicates.md (order_operator): Remove predicate.
- * config/riscv/riscv.cc (riscv_rtx_costs): Update accordingly.
- * config/riscv/riscv.md (*branch<mode>, *mov<GPR:mode><X:mode>cc)
- (cstore<mode>4): Likewise.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv-protos.h (riscv_expand_float_scc): Add
- `invert_ptr' parameter.
- * config/riscv/riscv.cc (riscv_emit_float_compare): Add NE
- inversion handling.
- (riscv_expand_float_scc): Pass `invert_ptr' through to
- `riscv_emit_float_compare'.
- (riscv_expand_conditional_move): Pass `&invert' to
- `riscv_expand_float_scc'.
- * config/riscv/riscv.md (add<mode>cc): Likewise.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_emit_float_compare) <NE>: Handle
- separately.
- <EQ, LE, LT, GE, GT>: Return operands supplied as is.
- (riscv_emit_binary): Call `riscv_emit_binary' directly rather
- than going through a temporary register for word-mode targets.
- (riscv_expand_conditional_branch): Canonicalize the comparison
- if not against constant zero.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/predicates.md (ne_operator): New predicate.
- * config/riscv/riscv.cc (riscv_insn_cost): Handle branches on a
- floating-point condition.
- * config/riscv/riscv.md (@cbranch<mode>4): Rename expander to...
- (@cbranch<ANYF:mode>4): ... this. Only expand the RTX via
- `riscv_expand_conditional_branch' for `!signed_order_operator'
- operators, otherwise let it through.
- (*cbranch<ANYF:mode>4, *cbranch<ANYF:mode>4): New insns and
- splitters.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Don't
- bail out in floating-point conditions.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_float_scc): Suppress the
- use of SUBREG if the conditional-set target is word-mode.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.md (add<mode>cc): New expander.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/predicates.md (movcc_operand): New predicate.
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Handle
- generic targets.
- * config/riscv/riscv.md (mov<mode>cc): Likewise.
- * config/riscv/riscv.opt (mmovcc): New option.
- * doc/invoke.texi (Option Summary): Document it.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv-protos.h (riscv_emit_unary): New prototype.
- * config/riscv/riscv.cc (riscv_emit_unary): New function.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Unify
- conditional-move handling across all the relevant targets.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
- accept constants for T-Head data input operands.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
- accept constants for T-Head comparison operands.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Remove
- the check for operand 1 being constant 0 in the Ventana/Zicond
- case for equality comparisons.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
- invert the condition for GEU and LEU.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_insn_cost): New function.
- (riscv_max_noce_ifcvt_seq_cost): Likewise.
- (riscv_noce_conversion_profitable_p): Likewise.
- (TARGET_INSN_COST): New macro.
- (TARGET_MAX_NOCE_IFCVT_SEQ_COST): New macro.
- (TARGET_NOCE_CONVERSION_PROFITABLE_P): New macro.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Remove
- extraneous variable for EQ vs NE operation selection.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Use
- `nullptr' rather than 0 to initialize a pointer.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Use
- `mode0' and `mode1' for `GET_MODE (op0)' and `GET_MODE (op1)'.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Use
- `mode' for `GET_MODE (dest)' throughout.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_emit_int_compare): Bail out if
- NEED_EQ_NE_P but the comparison is neither EQ nor NE.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.md (mov<mode>cc): Move comment on SFB
- patterns over to...
- (*mov<GPR:mode><X:mode>cc): ... here.
-
-2023-11-21 Robin Dapp <rdapp@ventanamicro.com>
-
- PR middle-end/112406
- * tree-vect-loop.cc (vectorize_fold_left_reduction): Allow
- reduction index != 1.
- (vect_transform_reduction): Handle reduction index != 1.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * common.md (aligned_register_operand): New predicate.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * ira-int.h (ira_allocno): Add a register_filters field.
- (ALLOCNO_REGISTER_FILTERS): New macro.
- (ALLOCNO_SET_REGISTER_FILTERS): Likewise.
- * ira-build.cc (ira_create_allocno): Initialize register_filters.
- (create_cap_allocno): Propagate register_filters.
- (propagate_allocno_info): Likewise.
- (propagate_some_info_from_allocno): Likewise.
- * ira-lives.cc (process_register_constraint_filters): New function.
- (process_bb_node_lives): Use it to record register filter
- information.
- * ira-color.cc (assign_hard_reg): Check register filters.
- (improve_allocation, fast_allocation): Likewise.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * lra-constraints.cc (process_alt_operands): Check register filters.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * recog.h (operand_alternative): Add a register_filters field.
- (alternative_register_filters): New function.
- * recog.cc (preprocess_constraints): Calculate the filters field.
- (constrain_operands): Check register filters.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl.def (DEFINE_REGISTER_CONSTRAINT): Add an optional filter
- operand.
- * doc/md.texi (define_register_constraint): Document it.
- * doc/tm.texi.in: Reference it in discussion about aligned registers.
- * doc/tm.texi: Regenerate.
- * gensupport.h (register_filters, get_register_filter_id): Declare.
- * gensupport.cc (register_filter_map, register_filters): New variables.
- (get_register_filter_id): New function.
- (process_define_register_constraint): Likewise.
- (process_rtx): Pass define_register_constraints to
- process_define_register_constraint.
- * genconfig.cc (main): Emit a definition of NUM_REGISTER_FILTERS.
- * genpreds.cc (constraint_data): Add a filter field.
- (add_constraint): Update accordingly.
- (process_define_register_constraint): Pass the filter operand.
- (write_init_reg_class_start_regs): New function.
- (write_get_register_filter): Likewise.
- (write_get_register_filter_id): Likewise.
- (write_tm_preds_h): Write a definition of target_constraints,
- plus helpers to test its contents. Write the get_register_filter*
- functions.
- (write_insn_preds_c): Write init_reg_class_start_regs.
- * reginfo.cc (init_reg_class_start_regs): Declare.
- (init_reg_sets): Call it.
- * target-globals.h (this_target_constraints): Declare.
- (target_globals): Add a constraints field.
- (restore_target_globals): Update accordingly.
- * target-globals.cc: Include tm_p.h.
- (default_target_globals): Initialize the constraints field.
- (save_target_globals): Handle the constraints field.
- (target_globals::~target_globals): Likewise.
-
-2023-11-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112623
- * tree-ssa-forwprop.cc (simplify_vector_constructor):
- Check the source mode of the insn for vector pack/unpacks.
-
-2023-11-21 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (vect_analyze_loop_2): Move check
- of VF against max_vf until VF is final.
-
-2023-11-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112598
- * config/riscv/riscv.cc (riscv_const_insns): Disallow DI CONST_VECTOR on RV32.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_override_options): Rework warnings.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- PR target/111370
- * config/aarch64/aarch64-arches.def (armv9-a, armv9.1-a, armv9.2-a,
- armv9.3-a): Update to generic-armv9-a.
- * config/aarch64/aarch64-cores.def (generic-armv9-a): New.
- * config/aarch64/aarch64-tune.md: Regenerate.
- * config/aarch64/aarch64.cc: Include generic_armv9_a.h.
- * config/aarch64/tuning_models/generic_armv9_a.h: New file.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- PR target/111370
- * config/aarch64/aarch64-arches.def (armv8-9, armv8-a, armv8.1-a,
- armv8.2-a, armv8.3-a, armv8.4-a, armv8.5-a, armv8.6-a, armv8.7-a,
- armv8.8-a): Update to generic_armv8_a.
- * config/aarch64/aarch64-cores.def (generic-armv8-a): New.
- * config/aarch64/aarch64-tune.md: Regenerate.
- * config/aarch64/aarch64.cc: Include generic_armv8_a.h
- * config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Change to
- TARGET_CPU_generic_armv8_a.
- * config/aarch64/tuning_models/generic_armv8_a.h: New file.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- PR target/111370
- * config/aarch64/aarch64-cores.def: Add generic.
- * config/aarch64/aarch64-opts.h (enum aarch64_proc): Remove generic.
- * config/aarch64/aarch64-tune.md: Regenerate
- * config/aarch64/aarch64.cc (all_cores): Remove generic
- * config/aarch64/aarch64.h (enum target_cpus): Remove
- TARGET_CPU_generic.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- PR target/111370
- * config/aarch64/aarch64.cc (generic_addrcost_table,
- exynosm1_addrcost_table,
- xgene1_addrcost_table,
- thunderx2t99_addrcost_table,
- thunderx3t110_addrcost_table,
- tsv110_addrcost_table,
- qdf24xx_addrcost_table,
- a64fx_addrcost_table,
- neoversev1_addrcost_table,
- neoversen2_addrcost_table,
- neoversev2_addrcost_table,
- generic_regmove_cost,
- cortexa57_regmove_cost,
- cortexa53_regmove_cost,
- exynosm1_regmove_cost,
- thunderx_regmove_cost,
- xgene1_regmove_cost,
- qdf24xx_regmove_cost,
- thunderx2t99_regmove_cost,
- thunderx3t110_regmove_cost,
- tsv110_regmove_cost,
- a64fx_regmove_cost,
- neoversen2_regmove_cost,
- neoversev1_regmove_cost,
- neoversev2_regmove_cost,
- generic_vector_cost,
- a64fx_vector_cost,
- qdf24xx_vector_cost,
- thunderx_vector_cost,
- tsv110_vector_cost,
- cortexa57_vector_cost,
- exynosm1_vector_cost,
- xgene1_vector_cost,
- thunderx2t99_vector_cost,
- thunderx3t110_vector_cost,
- ampere1_vector_cost,
- generic_branch_cost,
- generic_tunings,
- cortexa35_tunings,
- cortexa53_tunings,
- cortexa57_tunings,
- cortexa72_tunings,
- cortexa73_tunings,
- exynosm1_tunings,
- thunderxt88_tunings,
- thunderx_tunings,
- tsv110_tunings,
- xgene1_tunings,
- emag_tunings,
- qdf24xx_tunings,
- saphira_tunings,
- thunderx2t99_tunings,
- thunderx3t110_tunings,
- neoversen1_tunings,
- ampere1_tunings,
- ampere1a_tunings,
- neoversev1_vector_cost,
- neoversev1_tunings,
- neoverse512tvb_vector_cost,
- neoverse512tvb_tunings,
- neoversen2_vector_cost,
- neoversen2_tunings,
- neoversev2_vector_cost,
- neoversev2_tunings
- a64fx_tunings): Split into own files.
- * config/aarch64/tuning_models/a64fx.h: New file.
- * config/aarch64/tuning_models/ampere1.h: New file.
- * config/aarch64/tuning_models/ampere1a.h: New file.
- * config/aarch64/tuning_models/cortexa35.h: New file.
- * config/aarch64/tuning_models/cortexa53.h: New file.
- * config/aarch64/tuning_models/cortexa57.h: New file.
- * config/aarch64/tuning_models/cortexa72.h: New file.
- * config/aarch64/tuning_models/cortexa73.h: New file.
- * config/aarch64/tuning_models/emag.h: New file.
- * config/aarch64/tuning_models/exynosm1.h: New file.
- * config/aarch64/tuning_models/generic.h: New file.
- * config/aarch64/tuning_models/neoverse512tvb.h: New file.
- * config/aarch64/tuning_models/neoversen1.h: New file.
- * config/aarch64/tuning_models/neoversen2.h: New file.
- * config/aarch64/tuning_models/neoversev1.h: New file.
- * config/aarch64/tuning_models/neoversev2.h: New file.
- * config/aarch64/tuning_models/qdf24xx.h: New file.
- * config/aarch64/tuning_models/saphira.h: New file.
- * config/aarch64/tuning_models/thunderx.h: New file.
- * config/aarch64/tuning_models/thunderx2t99.h: New file.
- * config/aarch64/tuning_models/thunderx3t110.h: New file.
- * config/aarch64/tuning_models/thunderxt88.h: New file.
- * config/aarch64/tuning_models/tsv110.h: New file.
- * config/aarch64/tuning_models/xgene1.h: New file.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-simd.md (vec_unpack<su>_lo_<mode,
- vec_unpack<su>_lo_<mode): Split into...
- (vec_unpacku_lo_<mode, vec_unpacks_lo_<mode,
- vec_unpacku_lo_<mode, vec_unpacks_lo_<mode): ...These.
- (aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip): New.
- (aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip): New.
- * config/aarch64/iterators.md (PERM_EXTEND, perm_index): New.
- (perm_hilo): Add UNSPEC_ZIP1, UNSPEC_ZIP2.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_adjust_stmt_cost): Guard mla.
- (aarch64_vector_costs::count_ops): Likewise.
-
-2023-11-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- PR middle-end/112634
- * tree-profile.cc (gen_assign_counter_update): Cast the unsigned result type of
- __atomic_add_fetch() to the signed counter type.
- (gen_counter_update): Fix formatting.
-
-2023-11-21 Jakub Jelinek <jakub@redhat.com>
-
- * tree-profile.cc (gen_counter_update, tree_profiling): Formatting
- fixes.
-
-2023-11-21 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112639
- * builtins.cc (fold_builtin_bit_query): If arg0 has side-effects, arg1
- is specified but cleared, call save_expr on arg0.
-
-2023-11-21 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386-expand.h (gen_push): Add default bool
- parameter.
- (gen_pop): Likewise.
- * config/i386/i386-opts.h (enum apx_features): Add apx_ppx, add
- it to apx_all.
- * config/i386/i386.cc (ix86_emit_restore_reg_using_pop): Add
- ppx_p parameter for function declaration.
- (gen_push2): Add ppx_p parameter, emit push2p if ppx_p is true.
- (gen_push): Likewise.
- (ix86_emit_restore_reg_using_pop2): Likewise for pop2p.
- (ix86_emit_save_regs): Emit pushp/push2p under TARGET_APX_PPX.
- (ix86_emit_restore_reg_using_pop): Add ppx_p, emit popp insn
- and adjust cfi when ppx_p is ture.
- (ix86_emit_restore_reg_using_pop2): Add ppx_p and parse to its
- callee.
- (ix86_emit_restore_regs_using_pop2): Likewise.
- (ix86_expand_epilogue): Parse TARGET_APX_PPX to
- ix86_emit_restore_reg_using_pop.
- * config/i386/i386.h (TARGET_APX_PPX): New.
- * config/i386/i386.md (UNSPEC_APX_PPX): New unspec.
- (pushp_di): New define_insn.
- (popp_di): Likewise.
- (push2p_di): Likewise.
- (pop2p_di): Likewise.
- * config/i386/i386.opt: Add apx_ppx enum.
-
-2023-11-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111970
- * tree-vect-stmts.cc (vectorizable_load): Fix offset calculation
- for SLP gather load.
- (vectorizable_store): Likewise for SLP scatter store.
-
-2023-11-21 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-def.h (stdint.h): Guard with #if to
- exclude it for target libraries.
- (loongarch_isa_base_features): Likewise.
- (loongarch_isa): Likewise.
- (loongarch_abi): Likewise.
- (loongarch_target): Likewise.
- (loongarch_cpu_default_isa): Likewise.
-
-2023-11-21 liuhongt <hongtao.liu@intel.com>
-
- PR target/112325
- * config/i386/i386-expand.cc (emit_reduc_half): Hanlde
- V8QImode.
- * config/i386/mmx.md (reduc_<code>_scal_<mode>): New expander.
- (reduc_<code>_scal_v4qi): Ditto.
-
-2023-11-20 Marc Poulhiès <dkm@kataplop.net>
-
- * config/nvptx/nvptx.h (struct machine_function): Fix typo in variadic.
- * config/nvptx/nvptx.cc (nvptx_function_arg_advance): Adjust to use fixed name.
- (nvptx_declare_function_name): Likewise.
- (nvptx_call_args): Likewise.
- (nvptx_expand_call): Likewise.
-
-2023-11-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * tree-profile.cc (gen_counter_update): Use unshare_expr() for the
- counter expression in the second gimple_build_assign().
-
-2023-11-20 Jan Hubicka <jh@suse.cz>
-
- * cgraph.cc (add_detected_attribute_1): New function.
- (cgraph_node::add_detected_attribute): Likewise.
- * cgraph.h (cgraph_node::add_detected_attribute): Declare.
- * common.opt: Add -Wsuggest-attribute=returns_nonnull.
- * doc/invoke.texi: Document new flag.
- * gimple-range-fold.cc (fold_using_range::range_of_call):
- Use known reutrn value ranges.
- * ipa-prop.cc (struct ipa_return_value_summary): New type.
- (class ipa_return_value_sum_t): New type.
- (ipa_return_value_sum): New summary.
- (ipa_record_return_value_range): New function.
- (ipa_return_value_range): New function.
- * ipa-prop.h (ipa_return_value_range): Declare.
- (ipa_record_return_value_range): Declare.
- * ipa-pure-const.cc (warn_function_returns_nonnull): New funcion.
- * ipa-utils.h (warn_function_returns_nonnull): Declare.
- * symbol-summary.h: Fix comment.
- * tree-vrp.cc (execute_ranger_vrp): Record return values.
-
-2023-11-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112618
- * tree-vect-loop.cc (vect_transform_loop_stmt): For not
- relevant and unused .MASK_CALL make sure we remove the
- scalar stmt.
-
-2023-11-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112281
- * tree-loop-distribution.cc
- (loop_distribution::pg_add_dependence_edges): For = in the
- innermost common loop record a partition conflict.
-
-2023-11-20 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112622
- * convert.cc (convert_to_real_1): Use element_precision
- where a vector type might appear. Provide specific
- diagnostic for unexpected vector argument.
-
-2023-11-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112597
- * config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE.
- * config/riscv/vector.md: Fix slide1 intermediate mode bug.
-
-2023-11-20 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-v.cc (gather_scatter_valid_offset_mode_p):
- Add check for XLEN == 32.
- * config/riscv/vector-iterators.md: Change VLS part of the
- demote iterator to 2x elements modes
- * config/riscv/vector.md: Adjust iterators and insn conditions.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-base.cc (vld1_impl, vld1q)
- (vst1_impl, vst1q): New.
- * config/arm/arm-mve-builtins-base.def (vld1q, vst1q): New.
- * config/arm/arm-mve-builtins-base.h (vld1q, vst1q): New.
- * config/arm/arm_mve.h
- (vld1q): Delete.
- (vst1q): Delete.
- (vld1q_s8): Delete.
- (vld1q_s32): Delete.
- (vld1q_s16): Delete.
- (vld1q_u8): Delete.
- (vld1q_u32): Delete.
- (vld1q_u16): Delete.
- (vld1q_f32): Delete.
- (vld1q_f16): Delete.
- (vst1q_f32): Delete.
- (vst1q_f16): Delete.
- (vst1q_s8): Delete.
- (vst1q_s32): Delete.
- (vst1q_s16): Delete.
- (vst1q_u8): Delete.
- (vst1q_u32): Delete.
- (vst1q_u16): Delete.
- (__arm_vld1q_s8): Delete.
- (__arm_vld1q_s32): Delete.
- (__arm_vld1q_s16): Delete.
- (__arm_vld1q_u8): Delete.
- (__arm_vld1q_u32): Delete.
- (__arm_vld1q_u16): Delete.
- (__arm_vst1q_s8): Delete.
- (__arm_vst1q_s32): Delete.
- (__arm_vst1q_s16): Delete.
- (__arm_vst1q_u8): Delete.
- (__arm_vst1q_u32): Delete.
- (__arm_vst1q_u16): Delete.
- (__arm_vld1q_f32): Delete.
- (__arm_vld1q_f16): Delete.
- (__arm_vst1q_f32): Delete.
- (__arm_vst1q_f16): Delete.
- (__arm_vld1q): Delete.
- (__arm_vst1q): Delete.
- * config/arm/mve.md (mve_vld1q_f<mode>): Rename into ...
- (@mve_vld1q_f<mode>): ... this.
- (mve_vld1q_<supf><mode>): Rename into ...
- (@mve_vld1q_<supf><mode>) ... this.
- (mve_vst1q_f<mode>): Rename into ...
- (@mve_vst1q_f<mode>): ... this.
- (mve_vst1q_<supf><mode>): Rename into ...
- (@mve_vst1q_<supf><mode>) ... this.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (load, store): New.
- * config/arm/arm-mve-builtins-shapes.h (load, store): New.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-functions.h (multi_vector_function)
- (full_width_access): New classes.
- * config/arm/arm-mve-builtins.cc
- (find_type_suffix_for_scalar_type, infer_pointer_type)
- (require_pointer_type, get_contiguous_base, add_mem_operand)
- (add_fixed_operand, use_contiguous_load_insn)
- (use_contiguous_store_insn): New.
- * config/arm/arm-mve-builtins.h (memory_vector_mode)
- (infer_pointer_type, require_pointer_type, get_contiguous_base)
- (add_mem_operand)
- (add_fixed_operand, use_contiguous_load_insn)
- (use_contiguous_store_insn): New.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (build_const_pointer):
- New.
- (parse_type): Add support for '_', 'al' and 'as'.
- * config/arm/arm-mve-builtins.h (function_instance): Add
- memory_scalar_type.
- (function_base): Likewise.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Fix
- initialization of arm_simd_types[].eltype.
- * config/arm/arm-mve-builtins.def (DEF_MVE_TYPE): Fix scalar
- types.
-
-2023-11-20 Jakub Jelinek <jakub@redhat.com>
-
- * typeclass.h (enum type_class): Add vector_type_class.
- * builtins.cc (type_to_class): Return vector_type_class for
- VECTOR_TYPE.
- * doc/extend.texi (__builtin_classify_type): Mention bit-precise
- integer types and vector types.
-
-2023-11-20 Robin Dapp <rdapp@ventanamicro.com>
-
- PR middle-end/112406
- * tree-vect-patterns.cc (vect_recog_mask_conversion_pattern):
- Convert masks for conditional operations as well.
-
-2023-11-20 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/90693
- * tree-ssa-math-opts.cc (match_single_bit_test): Mark POPCOUNT with
- result only used in equality comparison against 1 with direct optab
- support as .POPCOUNT call with 2 arguments.
- * internal-fn.h (expand_POPCOUNT): Declare.
- * internal-fn.def (DEF_INTERNAL_INT_EXT_FN): New macro, document it,
- undefine at the end.
- (POPCOUNT): Use it instead of DEF_INTERNAL_INT_FN.
- * internal-fn.cc (DEF_INTERNAL_INT_EXT_FN): Define to nothing before
- inclusion to define expanders.
- (expand_POPCOUNT): New function.
-
-2023-11-20 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/90693
- * tree-ssa-math-opts.cc (match_single_bit_test): New function.
- (math_opts_dom_walker::after_dom_children): Call it for EQ_EXPR
- and NE_EXPR assignments and GIMPLE_CONDs.
-
-2023-11-20 Jakub Jelinek <jakub@redhat.com>
-
- * internal-fn.def: Document missing DEF_INTERNAL* macros and make sure
- they are all undefined at the end.
- * internal-fn.cc (lookup_hilo_internal_fn, lookup_evenodd_internal_fn,
- widening_fn_p, get_len_internal_fn): Don't undef DEF_INTERNAL_*FN
- macros after inclusion of internal-fn.def.
-
-2023-11-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Add avx10_set and version and detect avx10.1.
- (cpu_indicator_init): Handle avx10.1-512.
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA2_AVX10_1_256_SET): New.
- (OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto.
- (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
- (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
- (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1.
- (ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512.
- Add indicator for explicit no-avx512 and no-avx10.1 options.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- AVX10_1_256 and AVX10_1_512.
- * config/i386/cpuid.h (bit_AVX10): New.
- (bit_AVX10_256): Ditto.
- (bit_AVX10_512): Ditto.
- * config/i386/driver-i386.cc (check_avx10_avx512_features): New.
- (host_detect_local_cpu): Do not append "-mno-" options under
- specific scenarios to avoid emitting a warning.
- * config/i386/i386-isa.def
- (EVEX512): Add DEF_PTA(EVEX512).
- (AVX10_1_256): Add DEF_PTA(AVX10_1_256).
- (AVX10_1_512): Add DEF_PTA(AVX10_1_512).
- * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and
- -mavx10.1-512.
- (ix86_function_specific_save): Save explicit no indicator.
- (ix86_function_specific_restore): Restore explicit no indicator.
- (ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and
- avx10.1-512.
- (ix86_valid_target_attribute_tree): Handle avx512 function
- attributes with avx10.1 command line option.
- (ix86_option_override_internal): Handle AVX10.1 options.
- * config/i386/i386.h: Add PTA_EVEX512 for AVX512 target
- machines.
- * config/i386/i386.opt: Add variable ix86_no_avx512_explicit and
- ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and
- -mavx10.1-512.
- * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
- * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
- * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
- and avx10.1-512.
-
-2023-11-20 liuhongt <hongtao.liu@intel.com>
-
- PR target/112325
- * config/i386/sse.md (reduc_<code>_scal_<mode>): New expander.
- (REDUC_ANY_LOGIC_MODE): New iterator.
- (REDUC_PLUS_MODE): Extend to VxHI/SI/DImode.
- (REDUC_SSE_PLUS_MODE): Ditto.
-
-2023-11-20 xuli <xuli1@eswincomputing.com>
-
- PR target/112537
- * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum): Strategy enum.
- * config/riscv/riscv-string.cc (riscv_expand_block_move): Disabled based on options.
- (expand_block_move): Ditto.
- * config/riscv/riscv.opt: Add -mmemcpy-strategy=.
-
-2023-11-20 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix.
-
-2023-11-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Optimize constant AVL.
-
-2023-11-19 Philipp Tomsich <philipp.tomsich@vrull.eu>
-
- * config/riscv/riscv-protos.h (extract_base_offset_in_addr): Prototype.
- * config/riscv/riscv.cc (riscv_fusion_pairs): New enum.
- (riscv_tune_param): Add fusible_ops field.
- (riscv_tune_param_rocket_tune_info): Initialize new field.
- (riscv_tune_param_sifive_7_tune_info): Likewise.
- (thead_c906_tune_info): Likewise.
- (generic_oo_tune_info): Likewise.
- (optimize_size_tune_info): Likewise.
- (riscv_macro_fusion_p): New function.
- (riscv_fusion_enabled_p): Likewise.
- (riscv_macro_fusion_pair_p): Likewise.
- (TARGET_SCHED_MACRO_FUSION_P): Define.
- (TARGET_SCHED_MACRO_FUSION_PAIR_P): Likewise.
- (extract_base_offset_in_addr): Moved into riscv.cc from...
- * config/riscv/thead.cc: Here.
- Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
- Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
-
-2023-11-19 Jeff Law <jlaw@ventanamicro.com>
-
- * config/c6x/c6x.md (mvilc): Add mode to UNSPEC source.
- * config/mips/mips.md (rdhwr_synci_step_<mode>): Likewise.
- * config/riscv/riscv.md (riscv_frcsr, riscv_frflags): Likewise.
- * config/s390/s390.md (@split_stack_call<mode>): Likewise.
- (@split_stack_cond_call<mode>): Likewise.
- * config/sh/sh.md (sp_switch_1): Likewise.
-
-2023-11-19 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.h: Include "rich-location.h".
- * edit-context.h (class fixit_hint): New forward decl.
- * gcc-rich-location.h: Include "rich-location.h".
- * genmatch.cc: Likewise.
- * pretty-print.h: Likewise.
-
-2023-11-19 David Malcolm <dmalcolm@redhat.com>
-
- * Makefile.in (CPPLIB_H): Add libcpp/include/rich-location.h.
- * coretypes.h (class rich_location): New forward decl.
-
-2023-11-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_tuple_move): Fix bug.
-
-2023-11-19 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/107573
- * doc/invoke.texi: Add -Wanalyzer-undefined-behavior-strtok.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/predicates.md (const_call_insn_operand):
- Remove buggy "HAVE_AS_SUPPORT_CALL36" conditions. Change "1" to
- "true" to make the coding style consistent.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/genopts/isa-evolution.in: (lam-bh, lamcas):
- Add.
- * config/loongarch/loongarch-str.h: Regenerate.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/loongarch-cpucfg-map.h: Regenerate.
- * config/loongarch/loongarch-cpu.cc
- (ISA_BASE_LA64V110_FEATURES): Include OPTION_MASK_ISA_LAM_BH
- and OPTION_MASK_ISA_LAMCAS.
- * config/loongarch/sync.md (atomic_add<mode:SHORT>): Use
- TARGET_LAM_BH instead of ISA_BASE_IS_LA64V110. Remove empty
- lines from assembly output.
- (atomic_exchange<mode>_short): Likewise.
- (atomic_exchange<mode:SHORT>): Likewise.
- (atomic_fetch_add<mode>_short): Likewise.
- (atomic_fetch_add<mode:SHORT>): Likewise.
- (atomic_cas_value_strong<mode>_amcas): Use TARGET_LAMCAS instead
- of ISA_BASE_IS_LA64V110.
- (atomic_compare_and_swap<mode>): Likewise.
- (atomic_compare_and_swap<mode:GPR>): Likewise.
- (atomic_compare_and_swap<mode:SHORT>): Likewise.
- * config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump
- status if -mlam-bh and -mlamcas if -fverbose-asm.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc (loongarch_print_operand): Don't
- print dbar 0x700 if TARGET_LD_SEQ_SA.
- * config/loongarch/sync.md (atomic_load<mode>): Likewise.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (DIV): New mode iterator.
- (<optab:ANY_DIV><mode:GPR>3): Don't expand if TARGET_DIV32.
- (<optab:ANY_DIV>di3_fake): Disable if TARGET_DIV32.
- (*<optab:ANY_DIV><mode:GPR>3): Allow SImode if TARGET_DIV32.
- (<optab:ANY_DIV>si3_extended): New insn if TARGET_DIV32.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-def.h:
- (loongarch_isa_base_features): Declare. Define it in ...
- * config/loongarch/loongarch-cpu.cc
- (loongarch_isa_base_features): ... here.
- (fill_native_cpu_config): If we know the base ISA of the CPU
- model from PRID, use it instead of la64 (v1.0). Check if all
- expected features of this base ISA is available, emit a warning
- if not.
- * config/loongarch/loongarch-opts.cc (config_target_isa): Enable
- the features implied by the base ISA if not -march=native.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/genopts/isa-evolution.in: New data file.
- * config/loongarch/genopts/genstr.sh: Translate info in
- isa-evolution.in when generating loongarch-str.h, loongarch.opt,
- and loongarch-cpucfg-map.h.
- * config/loongarch/genopts/loongarch.opt.in (isa_evolution):
- New variable.
- * config/loongarch/t-loongarch: (loongarch-cpucfg-map.h): New
- rule.
- (loongarch-str.h): Depend on isa-evolution.in.
- (loongarch.opt): Depend on isa-evolution.in.
- (loongarch-cpu.o): Depend on loongarch-cpucfg-map.h.
- * config/loongarch/loongarch-str.h: Regenerate.
- * config/loongarch/loongarch-def.h (loongarch_isa): Add field
- for evolution features. Add helper function to enable features
- in this field.
- Probe native CPU capability and save the corresponding options
- into preset.
- * config/loongarch/loongarch-cpu.cc (fill_native_cpu_config):
- Probe native CPU capability and save the corresponding options
- into preset.
- (cache_cpucfg): Simplify with C++11-style for loop.
- (cpucfg_useful_idx, N_CPUCFG_WORDS): Move to ...
- * config/loongarch/loongarch.cc
- (loongarch_option_override_internal): Enable the ISA evolution
- feature options implied by -march and not explicitly disabled.
- (loongarch_asm_code_end): New function, print ISA information as
- comments in the assembly if -fverbose-asm. It makes easier to
- debug things like -march=native.
- (TARGET_ASM_CODE_END): Define.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/loongarch-cpucfg-map.h: Generate.
- (cpucfg_useful_idx, N_CPUCFG_WORDS) ... here.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/genopts/loongarch-strings:
- (STR_ISA_BASE_LA64V110): Add.
- * config/loongarch/genopts/loongarch.opt.in:
- (ISA_BASE_LA64V110): Add.
- * config/loongarch/loongarch-def.c
- (loongarch_isa_base_strings): Initialize [ISA_BASE_LA64V110]
- to STR_ISA_BASE_LA64V110.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/loongarch-str.h: Regenerate.
-
-2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * doc/invoke.texi (-fprofile-update): Clarify default method. Document
- the atomic method behaviour.
- * tree-profile.cc (enum counter_update_method): New.
- (counter_update): Likewise.
- (gen_counter_update): Use counter_update_method. Split the
- atomic counter update in two 32-bit atomic operations if
- necessary.
- (tree_profiling): Select counter_update_method.
-
-2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * tree-profile.cc (gen_assign_counter_update): New.
- (gen_counter_update): Likewise.
- (gimple_gen_edge_profiler): Use gen_counter_update().
- (gimple_gen_time_profiler): Likewise.
-
-2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * config/rtems.h (TARGET_HAVE_LIBATOMIC): Define.
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in (TARGET_HAVE_LIBATOMIC): Add.
- * target.def (have_libatomic): New.
-
-2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- Revert:
- 2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * config/sparc/rtemself.h (SPARC_GCOV_TYPE_SIZE): Define.
- * config/sparc/sparc.c (sparc_gcov_type_size): New.
- (TARGET_GCOV_TYPE_SIZE): Redefine if SPARC_GCOV_TYPE_SIZE is defined.
- * coverage.c (get_gcov_type): Use targetm.gcov_type_size().
- * doc/tm.texi (TARGET_GCOV_TYPE_SIZE): Add hook under "Misc".
- * doc/tm.texi.in: Regenerate.
- * target.def (gcov_type_size): New target hook.
- * targhooks.c (default_gcov_type_size): New.
- * targhooks.h (default_gcov_type_size): Declare.
- * tree-profile.c (gimple_gen_edge_profiler): Use precision of
- gcov_type_node.
- (gimple_gen_time_profiler): Likewise.
-
-2023-11-18 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-target-attr.cc
- (riscv_target_attr_parser::parse_arch): Use char[] for
- std::unique_ptr to prevent mismatched new delete issue.
- (riscv_process_one_target_attr): Ditto.
- (riscv_process_target_attr): Ditto.
-
-2023-11-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Refactor iterators.
-
-2023-11-18 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/sync.md (atomic_load<mode>): New template.
-
-2023-11-18 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch-def.h: Add comments.
- * config/loongarch/loongarch-opts.h (ISA_BASE_IS_LA64V110): Define macro.
- * config/loongarch/loongarch.cc (loongarch_memmodel_needs_rel_acq_fence):
- Remove redundant code implementations.
- * config/loongarch/sync.md (d): Added QI, HI support.
- (atomic_add<mode>): New template.
- (atomic_exchange<mode>_short): Likewise.
- (atomic_cas_value_strong<mode>_amcas): Likewise..
- (atomic_fetch_add<mode>_short): Likewise.
-
-2023-11-18 Lulu Cheng <chenglulu@loongson.cn>
-
- * config.gcc: Support LA664.
- * config/loongarch/genopts/loongarch-strings: Likewise.
- * config/loongarch/genopts/loongarch.opt.in: Likewise.
- * config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Likewise.
- * config/loongarch/loongarch-def.c: Likewise.
- * config/loongarch/loongarch-def.h (N_ISA_BASE_TYPES): Likewise.
- (ISA_BASE_LA64V110): Define macro.
- (N_ARCH_TYPES): Update value.
- (N_TUNE_TYPES): Update value.
- (CPU_LA664): New macro.
- * config/loongarch/loongarch-opts.cc (isa_default_abi): Likewise.
- (isa_base_compat_p): Likewise.
- * config/loongarch/loongarch-opts.h (TARGET_64BIT): This parameter is enabled
- when la_target.isa.base is equal to ISA_BASE_LA64V100 or ISA_BASE_LA64V110.
- (TARGET_uARCH_LA664): Define macro.
- * config/loongarch/loongarch-str.h (STR_CPU_LA664): Likewise.
- * config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width):
- Add LA664 support.
- * config/loongarch/loongarch.opt: Regenerate.
-
-2023-11-18 Lulu Cheng <chenglulu@loongson.cn>
- Xi Ruoyao <xry111@xry111.site>
-
- * config.in: Regenerate.
- * config/loongarch/loongarch-opts.h (HAVE_AS_SUPPORT_CALL36): Define macro.
- * config/loongarch/loongarch.cc (loongarch_legitimize_call_address):
- If binutils supports call36, the function call is not split over expand.
- * config/loongarch/loongarch.md: Add call36 generation code.
- * config/loongarch/predicates.md: Likewise.
- * configure: Regenerate.
- * configure.ac: Check whether binutils supports call36.
-
-2023-11-18 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/106147
- * Makefile.in (ANALYZER_OBJS): Add analyzer/infinite-loop.o.
- * doc/invoke.texi: Add -fdump-analyzer-infinite-loop and
- -Wanalyzer-infinite-loop. Add missing CWE link for
- -Wanalyzer-infinite-recursion.
- * timevar.def (TV_ANALYZER_INFINITE_LOOPS): New.
-
-2023-11-17 Robin Dapp <rdapp@ventanamicro.com>
-
- PR middle-end/112406
- PR middle-end/112552
- * tree-vect-loop.cc (vect_transform_reduction): Pass truth
- vectype for mask operand.
-
-2023-11-17 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/107571
- * gimplify.cc (expand_FALLTHROUGH_r): Use wi->removed_stmt after
- gsi_remove, change the way of passing fallthrough stmt at the end
- of sequence to expand_FALLTHROUGH. Diagnose IFN_FALLTHROUGH
- with GF_CALL_NOTHROW flag.
- (expand_FALLTHROUGH): Change loc into array of 2 location_t elts,
- don't test wi.callback_result, instead check whether first
- elt is not UNKNOWN_LOCATION and in that case pedwarn with the
- second location.
- * gimple-walk.cc (walk_gimple_seq_mod): Clear wi->removed_stmt
- after the flag has been used.
- * internal-fn.def (FALLTHROUGH): Mention in comment the special
- meaning of the TREE_NOTHROW/GF_CALL_NOTHROW flag on the calls.
-
-2023-11-17 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112566
- PR tree-optimization/83171
- * match.pd (ctz(ext(X)) -> ctz(X), popcount(zext(X)) -> popcount(X),
- parity(ext(X)) -> parity(X), ffs(ext(X)) -> ffs(X)): New
- simplifications.
- ( __builtin_ffs (X) == 0 -> X == 0): Use FFS rather than
- BUILT_IN_FFS BUILT_IN_FFSL BUILT_IN_FFSLL BUILT_IN_FFSIMAX.
-
-2023-11-17 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112374
- * tree-vect-loop.cc (check_reduction_path): Perform the cond_fn_p
- special case only if op_use_stmt == use_stmt, use as_a rather than
- dyn_cast in that case.
-
-2023-11-17 Richard Biener <rguenther@suse.de>
-
- Revert:
- 2023-11-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112281
- * tree-loop-distribution.cc (pg_add_dependence_edges):
- Preserve stmt order when the innermost loop has exact
- overlap.
-
-2023-11-17 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/53372
- * config/avr/avr.cc (avr_asm_named_section) [AVR_SECTION_PROGMEM]:
- Only return some .progmem*.data section if the user did not
- specify a section attribute.
- (avr_section_type_flags) [avr_progmem_p]: Unset SECTION_NOTYPE
- in returned section flags.
-
-2023-11-17 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/lsx.md (copysign<mode>3): Allow operand[2] to
- be an reg_or_vector_same_val_operand. If it's a const vector
- with same negative elements, expand the copysign with a bitset
- instruction. Otherwise, force it into an register.
- * config/loongarch/lasx.md (copysign<mode>3): Likewise.
-
-2023-11-17 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/111449
- * config/rs6000/vsx.md (*vsx_le_mem_to_mem_mov_ti): New.
-
-2023-11-17 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/111449
- * config/rs6000/altivec.md (cbranchv16qi4): New expand pattern.
- * config/rs6000/rs6000.cc (rs6000_generate_compare): Generate
- insn sequence for V16QImode equality compare.
- * config/rs6000/rs6000.h (MOVE_MAX_PIECES): Define.
- (STORE_MAX_PIECES): Define.
-
-2023-11-17 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.h (CLZ_DEFINED_VALUE_AT_ZERO):
- Implement.
- (CTZ_DEFINED_VALUE_AT_ZERO): Same.
-
-2023-11-17 Richard Biener <rguenther@suse.de>
-
- * dwarf2out.cc (add_AT_die_ref): Assert we do not add
- a self-ref DW_AT_abstract_origin or DW_AT_specification.
-
-2023-11-17 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/loongarch.cc
- (loongarch_builtin_vectorization_cost): Adjust.
-
-2023-11-16 Andrew Pinski <pinskia@gmail.com>
-
- PR rtl-optimization/112483
- * simplify-rtx.cc (simplify_binary_operation_1) <case COPYSIGN>:
- Call simplify_unary_operation for NEG instead of
- simplify_gen_unary.
-
-2023-11-16 Edwin Lu <ewlu@rivosinc.com>
-
- PR target/111557
- * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro name
-
-2023-11-16 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/78904
- * config/i386/i386.md (*addqi_ext2<mode>_0):
- New define_insn_and_split pattern.
- (*subqi_ext2<mode>_0): Ditto.
- (*<code>qi_ext2<mode>_0): Ditto.
-
-2023-11-16 John David Anglin <danglin@gcc.gnu.org>
-
- PR rtl-optimization/112415
- * config/pa/pa.cc (pa_legitimate_address_p): Allow 14-bit
- displacements before reload. Simplify logic flow. Revise
- comments.
- * config/pa/pa.h (TARGET_ELF64): New define.
- (INT14_OK_STRICT): Update define and comment.
- * config/pa/pa64-linux.h (TARGET_ELF64): Define.
- * config/pa/predicates.md (base14_operand): Don't check
- alignment of short displacements.
- (integer_store_memory_operand): Don't return true when
- reload_in_progress is true. Remove INT_5_BITS check.
- (floating_point_store_memory_operand): Don't return true when
- reload_in_progress is true. Use INT14_OK_STRICT to check
- whether long displacements are always okay.
-
-2023-11-16 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112567
- * config/i386/i386.md (*<any_logic:code>qi_ext<mode>_1_slp):
- Fix generation of invalid RTX in split pattern.
-
-2023-11-16 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_context::set_option_hooks): Add
- "lang_mask" param.
- * diagnostic.h (diagnostic_context::option_enabled_p): Update for
- move of m_lang_mask.
- (diagnostic_context::set_option_hooks): Add "lang_mask" param.
- (diagnostic_context::get_lang_mask): New.
- (diagnostic_context::m_lang_mask): Move into m_option_callbacks,
- thus making private.
- * lto-wrapper.cc (main): Update for new lang_mask param of
- set_option_hooks.
- * toplev.cc (init_asm_output): Use get_lang_mask.
- (general_init): Move initialization of global_dc's lang_mask to
- new lang_mask param of set_option_hooks.
-
-2023-11-16 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/111878
- * tree-vect-loop-manip.cc (find_loop_location): Skip edges check if
- latch incorrect.
-
-2023-11-16 Kito Cheng <kito.cheng@sifive.com>
-
- * config.gcc (riscv): Add riscv-target-attr.o.
- * config/riscv/riscv-protos.h (riscv_declare_function_size) New.
- (riscv_option_valid_attribute_p): New.
- (riscv_override_options_internal): New.
- (struct riscv_tune_info): New.
- (riscv_parse_tune): New.
- * config/riscv/riscv-target-attr.cc
- (class riscv_target_attr_parser): New.
- (struct riscv_attribute_info): New.
- (riscv_attributes): New.
- (riscv_target_attr_parser::parse_arch): New.
- (riscv_target_attr_parser::handle_arch): New.
- (riscv_target_attr_parser::handle_cpu): New.
- (riscv_target_attr_parser::handle_tune): New.
- (riscv_target_attr_parser::update_settings): New.
- (riscv_process_one_target_attr): New.
- (num_occurences_in_str): New.
- (riscv_process_target_attr): New.
- (riscv_option_valid_attribute_p): New.
- * config/riscv/riscv.cc: Include target-globals.h and
- riscv-subset.h.
- (struct riscv_tune_info): Move to riscv-protos.h.
- (get_tune_str): New.
- (riscv_parse_tune): New parameter null_p.
- (riscv_declare_function_size): New.
- (riscv_option_override): Build target_option_default_node and
- target_option_current_node.
- (riscv_save_restore_target_globals): New.
- (riscv_option_restore): New.
- (riscv_previous_fndecl): New.
- (riscv_set_current_function): Apply the target attribute.
- (TARGET_OPTION_RESTORE): Define.
- (TARGET_OPTION_VALID_ATTRIBUTE_P): Ditto.
- * config/riscv/riscv.h (SWITCHABLE_TARGET): Define to 1.
- (ASM_DECLARE_FUNCTION_SIZE) Define.
- * config/riscv/riscv.opt (mtune=): Add Save attribute.
- (mcpu=): Ditto.
- (mcmodel=): Ditto.
- * config/riscv/t-riscv: Add build rule for riscv-target-attr.o
- * doc/extend.texi: Add doc for target attribute.
-
-2023-11-16 Kito Cheng <kito.cheng@sifive.com>
-
- PR target/112478
- * config/riscv/riscv.cc (riscv_save_return_addr_reg_p): Check ra
- is ever lived.
-
-2023-11-16 liuhongt <hongtao.liu@intel.com>
-
- PR target/112532
- * config/i386/mmx.md (*vec_dup<mode>): Extend for V4HI and
- V2HI.
-
-2023-11-16 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112526
- * config/i386/i386.md
- (mov imm,%rax; mov %rdi,%rdx; mulx %rax -> mov imm,%rdx; mulx %rdi):
- Verify in define_peephole2 that operands[2] dies or is overwritten
- at the end of multiplication.
-
-2023-11-16 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112536
- * tree-vect-slp.cc (arg0_map): New variable.
- (vect_get_operand_map): For IFN_CLZ or IFN_CTZ, return arg0_map.
-
-2023-11-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR middle-end/112554
- * tree-vect-loop.cc (vect_determine_partial_vectors_and_peeling):
- Clear SELECT_VL_P for non-partial vectorization.
-
-2023-11-16 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/sse.md (vec_extract_hi_<mode>): Add noavx512vl
- alternative with attr addr gpr16 and "jm" constraint.
- (vec_extract_hi_<mode>): Likewise for SF vector modes.
- (@vec_extract_hi_<mode>): Likewise.
- (*vec_extractv2ti): Likewise.
- (vec_set_hi_<mode><mask_name>): Likewise.
- * config/i386/mmx.md (@sse4_1_insertps_<mode>): Correct gpr16 attr for
- each alternative.
-
-2023-11-15 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/78904
- * config/i386/i386.md (*movstrictqi_ext<mode>_1): New insn pattern.
- (*addqi_ext<mode>_2_slp): New define_insn_and_split pattern.
- (*subqi_ext<mode>_2_slp): Ditto.
- (*<any_logic:code>qi_ext<mode>_2_slp): Ditto.
-
-2023-11-15 Patrick O'Neill <patrick@rivosinc.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_subset_list::parse_std_ext): Emit an error and skip to
- the next extension when a non-canonical ordering is detected.
-
-2023-11-15 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
-
- * gcc-rich-location.cc (maybe_range_label_for_tree_type_mismatch::get_text):
- Revert using the macro CAN_HAVE_LOCATION_P.
-
-2023-11-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112447
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Insert
- local vsetvl info before LCM suggested one.
- Tested-by: Patrick O'Neill <patrick@rivosinc.com> # pre-commit-CI #679
- Co-developed-by: Vineet Gupta <vineetg@rivosinc.com>
-
-2023-11-15 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_sign_extend_if_not_subreg_prom): New.
- * (riscv_extend_comparands): Call New function on operands.
-
-2023-11-15 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (*addqi_ext<mode>_1_slp):
- Add "&& " before "reload_completed" in split condition.
- (*subqi_ext<mode>_1_slp): Ditto.
- (*<any_logic:code>qi_ext<mode>_1_slp): Ditto.
-
-2023-11-15 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112540
- * config/i386/i386.md (*addqi_ext<mode>_1_slp):
- Correct operand numbers in split pattern. Replace !Q constraint
- of operand 1 with !qm. Add insn constrain.
- (*subqi_ext<mode>_1_slp): Ditto.
- (*<any_logic:code>qi_ext<mode>_1_slp): Ditto.
-
-2023-11-15 Thomas Schwinge <thomas@codesourcery.com>
-
- * doc/extend.texi (Nvidia PTX Built-in Functions): Fix
- copy'n'paste-o in '__builtin_nvptx_brev' description.
-
-2023-11-15 Roger Sayle <roger@nextmovesoftware.com>
- Thomas Schwinge <thomas@codesourcery.com>
-
- * config/nvptx/nvptx.md (UNSPEC_BITREV): Delete.
- (bitrev<mode>2): Represent using bitreverse.
-
-2023-11-15 Andrew Stubbs <ams@codesourcery.com>
- Andrew Jenner <andrew@codesourcery.com>
-
- * config/gcn/constraints.md: Add "a" AVGPR constraint.
- * config/gcn/gcn-valu.md (*mov<mode>): Add AVGPR alternatives.
- (*mov<mode>_4reg): Likewise.
- (@mov<mode>_sgprbase): Likewise.
- (gather<mode>_insn_1offset<exec>): Likewise.
- (gather<mode>_insn_1offset_ds<exec>): Likewise.
- (gather<mode>_insn_2offsets<exec>): Likewise.
- (scatter<mode>_expr<exec_scatter>): Likewise.
- (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
- (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
- * config/gcn/gcn.cc (MAX_NORMAL_AVGPR_COUNT): Define.
- (gcn_class_max_nregs): Handle AVGPR_REGS and ALL_VGPR_REGS.
- (gcn_hard_regno_mode_ok): Likewise.
- (gcn_regno_reg_class): Likewise.
- (gcn_spill_class): Allow spilling to AVGPRs on TARGET_CDNA1_PLUS.
- (gcn_sgpr_move_p): Handle AVGPRs.
- (gcn_secondary_reload): Reload AVGPRs via VGPRs.
- (gcn_conditional_register_usage): Handle AVGPRs.
- (gcn_vgpr_equivalent_register_operand): New function.
- (gcn_valid_move_p): Check for validity of AVGPR moves.
- (gcn_compute_frame_offsets): Handle AVGPRs.
- (gcn_memory_move_cost): Likewise.
- (gcn_register_move_cost): Likewise.
- (gcn_vmem_insn_p): Handle TYPE_VOP3P_MAI.
- (gcn_md_reorg): Handle AVGPRs.
- (gcn_hsa_declare_function_name): Likewise.
- (print_reg): Likewise.
- (gcn_dwarf_register_number): Likewise.
- * config/gcn/gcn.h (FIRST_AVGPR_REG): Define.
- (AVGPR_REGNO): Define.
- (LAST_AVGPR_REG): Define.
- (SOFT_ARG_REG): Update.
- (FRAME_POINTER_REGNUM): Update.
- (DWARF_LINK_REGISTER): Update.
- (FIRST_PSEUDO_REGISTER): Update.
- (AVGPR_REGNO_P): Define.
- (enum reg_class): Add AVGPR_REGS and ALL_VGPR_REGS.
- (REG_CLASS_CONTENTS): Add new register classes and add entries for
- AVGPRs to all classes.
- (REGISTER_NAMES): Add AVGPRs.
- * config/gcn/gcn.md (FIRST_AVGPR_REG, LAST_AVGPR_REG): Define.
- (AP_REGNUM, FP_REGNUM): Update.
- (define_attr "type"): Add vop3p_mai.
- (define_attr "unit"): Handle vop3p_mai.
- (define_attr "gcn_version"): Add "cdna2".
- (define_attr "enabled"): Handle cdna2.
- (*mov<mode>_insn): Add AVGPR alternatives.
- (*movti_insn): Likewise.
- * config/gcn/mkoffload.cc (isa_has_combined_avgprs): New.
- (process_asm): Process avgpr_count.
- * config/gcn/predicates.md (gcn_avgpr_register_operand): New.
- (gcn_avgpr_hard_register_operand): New.
- * doc/md.texi: Document the "a" constraint.
-
-2023-11-15 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md (mov<mode>_sgprbase): Add @ modifier.
- (reload_in<mode>): Delete.
- (reload_out<mode>): Delete.
- * config/gcn/gcn.cc (CODE_FOR): Delete.
- (get_code_for_##PREFIX##vN##SUFFIX): Delete.
- (CODE_FOR_OP): Delete.
- (get_code_for_##PREFIX): Delete.
- (gcn_secondary_reload): Replace "get_code_for" with "code_for".
-
-2023-11-15 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/t-s390: Generate s390-gen-builtins.h without
- linemarkers.
-
-2023-11-15 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112282
- * tree-if-conv.cc (ifcvt_hoist_invariants): Only hoist from
- the loop header.
-
-2023-11-15 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_slp_region): Also clear visited flag when
- we skipped an instance due to -fdbg-cnt.
-
-2023-11-15 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc
- (loongarch_memmodel_needs_release_fence): Remove.
- (loongarch_cas_failure_memorder_needs_acquire): New static
- function.
- (loongarch_print_operand): Redefine 'G' for the barrier on CAS
- failure.
- * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
- Remove the redundant barrier before the LL instruction, and
- emit an acquire barrier on failure if needed by
- failure_memorder.
- (atomic_cas_value_cmp_and_7_<mode>): Likewise.
- (atomic_cas_value_add_7_<mode>): Remove the unnecessary barrier
- before the LL instruction.
- (atomic_cas_value_sub_7_<mode>): Likewise.
- (atomic_cas_value_and_7_<mode>): Likewise.
- (atomic_cas_value_xor_7_<mode>): Likewise.
- (atomic_cas_value_or_7_<mode>): Likewise.
- (atomic_cas_value_nand_7_<mode>): Likewise.
- (atomic_cas_value_exchange_7_<mode>): Likewise.
-
-2023-11-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_vector_init_trailing_same_elem): New function.
- (expand_vec_init): Add trailing optimization.
-
-2023-11-15 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (rvv_builder::get_merge_scalar_mask):
- Add inner_mode mask arg for mask int mode.
- (get_repeating_sequence_dup_machine_mode): Add mask_bit_mode arg
- to get the good enough vector int mode on precision.
- (expand_vector_init_merge_repeating_sequence): Pass required args
- to above func.
-
-2023-11-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112535
- * config/riscv/riscv.cc (riscv_legitimate_address_p): Disallow RVV modes base address.
-
-2023-11-15 David Malcolm <dmalcolm@redhat.com>
-
- * json.cc (selftest::assert_print_eq): Add "loc" param and use
- ASSERT_STREQ_AT.
- (ASSERT_PRINT_EQ): New macro.
- (selftest::test_writing_objects): Use ASSERT_PRINT_EQ to capture
- source location of assertion.
- (selftest::test_writing_arrays): Likewise.
- (selftest::test_writing_float_numbers): Likewise.
- (selftest::test_writing_integer_numbers): Likewise.
- (selftest::test_writing_strings): Likewise.
- (selftest::test_writing_literals): Likewise.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/103533
- * doc/invoke.texi (Static Analyzer Options): Add the six
- -Wanalyzer-tainted-* warnings. Update documentation of each
- warning to reflect removed requirement to use
- -fanalyzer-checker=taint. Remove discussion of
- -fanalyzer-checker=taint.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-json.cc
- (json_output_format::on_end_diagnostic): Update calls to m_context
- callbacks to use member functions; tighten up scopes.
- * diagnostic-format-sarif.cc (sarif_builder::make_result_object):
- Likewise.
- (sarif_builder::make_reporting_descriptor_object_for_warning):
- Likewise.
- * diagnostic.cc (diagnostic_context::initialize): Update for
- callbacks being moved into m_option_callbacks and being renamed.
- (diagnostic_context::set_option_hooks): New.
- (diagnostic_option_classifier::classify_diagnostic): Update call
- to global_dc->m_option_enabled to use option_enabled_p.
- (diagnostic_context::print_option_information): Update calls to
- m_context callbacks to use member functions; tighten up scopes.
- (diagnostic_context::diagnostic_enabled): Likewise.
- * diagnostic.h (diagnostic_option_enabled_cb): New typedef.
- (diagnostic_make_option_name_cb): New typedef.
- (diagnostic_make_option_url_cb): New typedef.
- (diagnostic_context::option_enabled_p): New.
- (diagnostic_context::make_option_name): New.
- (diagnostic_context::make_option_url): New.
- (diagnostic_context::set_option_hooks): New decl.
- (diagnostic_context::m_option_enabled): Rename to
- m_option_enabled_cb and move within m_option_callbacks, using
- typedef.
- (diagnostic_context::m_option_state): Move within
- m_option_callbacks.
- (diagnostic_context::m_option_name): Rename to
- m_make_option_name_cb and move within m_option_callbacks, using
- typedef.
- (diagnostic_context::m_get_option_url): Likewise, renaming to
- m_make_option_url_cb.
- * lto-wrapper.cc (print_lto_docs_link): Update call to m_context
- callback to use member function.
- (main): Use diagnostic_context::set_option_hooks.
- * opts-diagnostic.h (option_name): Make context param const.
- (get_option_url): Likewise.
- * opts.cc (option_name): Likewise.
- (get_option_url): Likewise.
- * toplev.cc (general_init): Use
- diagnostic_context::set_option_hooks.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * selftest-diagnostic.cc
- (test_diagnostic_context::test_diagnostic_context): Use
- diagnostic_start_span.
- * tree-diagnostic-path.cc (struct event_range): Likewise.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc (diagnostic_context::show_locus):
- Update for renaming of text callbacks fields.
- * diagnostic.cc (diagnostic_context::initialize): Likewise.
- * diagnostic.h (class diagnostic_context): Add "friend" for
- accessors to m_text_callbacks.
- (diagnostic_context::m_text_callbacks): Make private, and add an
- "m_" prefix to field names.
- (diagnostic_starter): Convert from macro to inline function.
- (diagnostic_start_span): New.
- (diagnostic_finalizer): Convert from macro to inline function.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.h (diagnostic_ready_p): Convert from macro to inline
- function.
-
-2023-11-14 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/78904
- * config/i386/i386.md (*addqi_ext<mode>_1_slp):
- New define_insn_and_split pattern.
- (*subqi_ext<mode>_1_slp): Ditto.
- (*<any_logic:code>qi_ext<mode>_1_slp): Ditto.
-
-2023-11-14 Andrew Stubbs <ams@codesourcery.com>
-
- PR target/112481
- * expr.cc (store_constructor): Use OPTAB_WIDEN for mask adjustment.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-sarif.cc (sarif_builder::get_sarif_column):
- Use m_context's file_cache.
- (sarif_builder::maybe_make_artifact_content_object): Likewise.
- (sarif_builder::get_source_lines): Likewise.
- * diagnostic-show-locus.cc
- (exploc_with_display_col::exploc_with_display_col): Add file_cache
- param.
- (layout::m_file_cache): New field.
- (make_range): Add file_cache param.
- (selftest::test_layout_range_for_single_point): Create and use a
- temporary file_cache.
- (selftest::test_layout_range_for_single_line): Likewise.
- (selftest::test_layout_range_for_multiple_lines): Likewise.
- (layout::layout): Initialize m_file_cache from the context and use it.
- (layout::maybe_add_location_range): Use m_file_cache.
- (layout::calculate_x_offset_display): Likewise.
- (get_affected_range): Add file_cache param.
- (get_printed_columns): Likewise.
- (line_corrections::line_corrections): Likewwise.
- (line_corrections::m_file_cache): New field.
- (source_line::source_line): Add file_cache param.
- (line_corrections::add_hint): Use m_file_cache.
- (layout::print_trailing_fixits): Likewise.
- (layout::print_line): Likewise.
- (selftest::test_layout_x_offset_display_utf8): Create and use a
- temporary file_cache.
- (selftest::test_layout_x_offset_display_tab): Likewise.
- (selftest::test_diagnostic_show_locus_one_liner_utf8): Likewise.
- (selftest::test_add_location_if_nearby): Pass global_dc's
- file_cache to temp_source_file ctor.
- (selftest::test_overlapped_fixit_printing): Create and use a
- temporary file_cache.
- (selftest::test_overlapped_fixit_printing_utf8): Likewise.
- (selftest::test_overlapped_fixit_printing_2): Use dc's file_cache.
- * diagnostic.cc (diagnostic_context::initialize): Always create a
- file_cache.
- (diagnostic_context::initialize_input_context): Assume
- m_file_cache has already been created.
- (diagnostic_context::create_edit_context): Pass m_file_cache to
- edit_context.
- (convert_column_unit): Add file_cache param.
- (diagnostic_context::converted_column): Use context's file_cache.
- (print_parseable_fixits): Add file_cache param.
- (diagnostic_context::report_diagnostic): Use context's file_cache.
- (selftest::test_print_parseable_fixits_none): Create and use a
- temporary file_cache.
- (selftest::test_print_parseable_fixits_insert): Likewise.
- (selftest::test_print_parseable_fixits_remove): Likewise.
- (selftest::test_print_parseable_fixits_replace): Likewise.
- (selftest::test_print_parseable_fixits_bytes_vs_display_columns):
- Likewise.
- * diagnostic.h (diagnostic_context::file_cache_init): Delete.
- (diagnostic_context::get_file_cache): Convert return type from
- pointer to reference.
- * edit-context.cc (edited_file::get_file_cache): New.
- (edited_file::m_edit_context): New.
- (edit_context::edit_context): Add file_cache param.
- (edit_context::get_or_insert_file): Pass this to edited_file's
- ctor.
- (edited_file::edited_file): Add edit_context param.
- (edited_file::print_content): Use get_file_cache.
- (edited_file::print_diff_hunk): Likewise.
- (edited_file::print_run_of_changed_lines): Likewise.
- (edited_file::get_or_insert_line): Likewise.
- (edited_file::get_num_lines): Likewise.
- (edited_line::edited_line): Pass in file_cache and use it.
- (selftest::test_get_content): Create and use a
- temporary file_cache.
- (selftest::test_applying_fixits_insert_before): Likewise.
- (selftest::test_applying_fixits_insert_after): Likewise.
- (selftest::test_applying_fixits_insert_after_at_line_end):
- Likewise.
- (selftest::test_applying_fixits_insert_after_failure): Likewise.
- (selftest::test_applying_fixits_insert_containing_newline):
- Likewise.
- (selftest::test_applying_fixits_growing_replace): Likewise.
- (selftest::test_applying_fixits_shrinking_replace): Likewise.
- (selftest::test_applying_fixits_replace_containing_newline):
- Likewise.
- (selftest::test_applying_fixits_remove): Likewise.
- (selftest::test_applying_fixits_multiple): Likewise.
- (selftest::test_applying_fixits_multiple_lines): Likewise.
- (selftest::test_applying_fixits_modernize_named_init): Likewise.
- (selftest::test_applying_fixits_modernize_named_init): Likewise.
- (selftest::test_applying_fixits_unreadable_file): Likewise.
- (selftest::test_applying_fixits_line_out_of_range): Likewise.
- (selftest::test_applying_fixits_column_validation): Likewise.
- (selftest::test_applying_fixits_column_validation): Likewise.
- (selftest::test_applying_fixits_column_validation): Likewise.
- (selftest::test_applying_fixits_column_validation): Likewise.
- * edit-context.h (edit_context::edit_context): Add file_cache
- param.
- (edit_context::get_file_cache): New.
- (edit_context::m_file_cache): New.
- * final.cc: Include "diagnostic.h".
- (asm_show_source): Use global_dc's file_cache.
- * gcc-rich-location.cc (blank_line_before_p): Add file_cache
- param.
- (use_new_line): Likewise.
- (gcc_rich_location::add_fixit_insert_formatted): Use global dc's
- file_cache.
- * input.cc (diagnostic_file_cache_init): Delete.
- (diagnostic_context::file_cache_init): Delete.
- (diagnostics_file_cache_forcibly_evict_file): Delete.
- (file_cache::missing_trailing_newline_p): New.
- (file_cache::evicted_cache_tab_entry): Don't call
- diagnostic_file_cache_init.
- (location_get_source_line): Delete.
- (get_source_text_between): Add file_cache param.
- (get_source_file_content): Delete.
- (location_missing_trailing_newline): Delete.
- (location_compute_display_column): Add file_cache param.
- (dump_location_info): Create and use temporary file_cache.
- (get_substring_ranges_for_loc): Add file_cache param.
- (get_location_within_string): Likewise.
- (get_source_range_for_char): Likewise.
- (get_num_source_ranges_for_substring): Likewise.
- (selftest::test_reading_source_line): Create and use temporary
- file_cache.
- (selftest::lexer_test::m_file_cache): New field.
- (selftest::assert_char_at_range): Use test.m_file_cache.
- (selftest::assert_num_substring_ranges): Likewise.
- (selftest::assert_has_no_substring_ranges): Likewise.
- (selftest::test_lexer_string_locations_concatenation_2): Likewise.
- * input.h (class file_cache): New forward decl.
- (location_compute_display_column): Add file_cache param.
- (location_get_source_line): Delete.
- (get_source_text_between): Add file_cache param.
- (get_source_file_content): Delete.
- (location_missing_trailing_newline): Delete.
- (file_cache::missing_trailing_newline_p): New decl.
- (diagnostics_file_cache_forcibly_evict_file): Delete.
- * selftest.cc (named_temp_file::named_temp_file): Add file_cache
- param.
- (named_temp_file::~named_temp_file): Optionally evict the file
- from the given file_cache.
- (temp_source_file::temp_source_file): Add file_cache param.
- * selftest.h (class file_cache): New forward decl.
- (named_temp_file::named_temp_file): Add file_cache param.
- (named_temp_file::m_file_cache): New field.
- (temp_source_file::temp_source_file): Add file_cache param.
- * substring-locations.h (get_location_within_string): Add
- file_cache param.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-json.cc: Use type-specific "set_*" functions
- of json::object to avoid naked new of json value subclasses.
- * diagnostic-format-sarif.cc: Likewise.
- * gcov.cc: Likewise.
- * json.cc (object::set_string): New.
- (object::set_integer): New.
- (object::set_float): New.
- (object::set_bool): New.
- (selftest::test_writing_objects): Use object::set_string.
- * json.h (object::set_string): New decl.
- (object::set_integer): New decl.
- (object::set_float): New decl.
- (object::set_bool): New decl.
- * optinfo-emit-json.cc: Use type-specific "set_*" functions of
- json::object to avoid naked new of json value subclasses.
- * timevar.cc: Likewise.
- * tree-diagnostic-path.cc: Likewise.
-
-2023-11-14 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/112509
- * tree-vrp.cc (find_case_label_range): Create range from case labels.
-
-2023-11-14 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtin-types.def: Add/remove types.
- * config/s390/s390-builtins.def (s390_vec_scatter_element_flt):
- The type for the offset should be UV4SI instead of V4SF.
-
-2023-11-14 Saurabh Jha <saurabh.jha@arm.com>
-
- PR target/112337
- * config/arm/arm.cc (mve_vector_mem_operand): Add a REG_P check for INC
- and DEC operations.
-
-2023-11-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111233
- PR tree-optimization/111652
- PR tree-optimization/111727
- PR tree-optimization/111838
- PR tree-optimization/112113
- * tree-ssa-loop-split.cc (patch_loop_exit): Get the new
- guard code instead of the old guard stmt.
- (split_loop): Adjust.
-
-2023-11-14 Richard Biener <rguenther@suse.de>
-
- * tree-loop-distribution.cc (loop_distribution::data_dep_in_cycle_p):
- Consider all loops in the nest when looking for
- lambda_vector_zerop.
-
-2023-11-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112281
- * tree-loop-distribution.cc (pg_add_dependence_edges):
- Preserve stmt order when the innermost loop has exact
- overlap.
-
-2023-11-14 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112523
- PR ada/112514
- * config/i386/i386.md (<insn><dwi>3_doubleword_lowpart): Move
- operands[1] aka low part of input rather than operands[3] aka high
- part of input to output if not the same register.
-
-2023-11-14 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config.gcc: Add s390-gen-builtins.h to target_gtfiles.
- * config/s390/s390-builtins.h (s390_builtin_types)
- (s390_builtin_fn_types, s390_builtin_decls): Add GTY marker.
- * config/s390/t-s390 (EXTRA_GTYPE_DEPS): Add s390-gen-builtins.h.
- Add build rule for s390-gen-builtins.h.
-
-2023-11-14 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config/s390/s390-c.cc (s390_fn_types_compatible): Add a check
- for error_mark_node.
-
-2023-11-14 Jakub Jelinek <jakub@redhat.com>
-
- PR c/111309
- * builtins.def (BUILT_IN_CLZG, BUILT_IN_CTZG, BUILT_IN_CLRSBG,
- BUILT_IN_FFSG, BUILT_IN_PARITYG, BUILT_IN_POPCOUNTG): New
- builtins.
- * builtins.cc (fold_builtin_bit_query): New function.
- (fold_builtin_1): Use it for
- BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
- (fold_builtin_2): Use it for BUILT_IN_{CLZ,CTZ}G.
- * fold-const-call.cc: Fix comment typo on tm.h inclusion.
- (fold_const_call_ss): Handle
- CFN_BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
- (fold_const_call_sss): New function.
- (fold_const_call_1): Call it for 2 argument functions returning
- scalar when passed 2 INTEGER_CSTs.
- * genmatch.cc (cmp_operand): For function calls also compare
- number of arguments.
- (fns_cmp): New function.
- (dt_node::gen_kids): Sort fns and generic_fns.
- (dt_node::gen_kids_1): Handle fns with the same id but different
- number of arguments.
- * match.pd (CLZ simplifications): Drop checks for defined behavior
- at zero. Add variant of simplifications for IFN_CLZ with 2 arguments.
- (CTZ simplifications): Drop checks for defined behavior at zero,
- don't optimize precisions above MAX_FIXED_MODE_SIZE. Add variant of
- simplifications for IFN_CTZ with 2 arguments.
- (a != 0 ? CLZ(a) : CST -> .CLZ(a)): Use TREE_TYPE (@3) instead of
- type, add BITINT_TYPE handling, create 2 argument IFN_CLZ rather than
- one argument. Add variant for matching CLZ with 2 arguments.
- (a != 0 ? CTZ(a) : CST -> .CTZ(a)): Similarly.
- * gimple-lower-bitint.cc (bitint_large_huge::lower_bit_query): New
- method.
- (bitint_large_huge::lower_call): Use it for IFN_{CLZ,CTZ,CLRSB,FFS}
- and IFN_{PARITY,POPCOUNT} calls.
- * gimple-range-op.cc (cfn_clz::fold_range): Don't check
- CLZ_DEFINED_VALUE_AT_ZERO for m_gimple_call_internal_p, instead
- assume defined value at zero if the call has 2 arguments and use
- second argument value for that case.
- (cfn_ctz::fold_range): Similarly.
- (gimple_range_op_handler::maybe_builtin_call): Use op_cfn_clz_internal
- or op_cfn_ctz_internal only if internal fn call has 2 arguments and
- set m_op2 in that case.
- * tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern,
- vect_recog_popcount_clz_ctz_ffs_pattern): For value defined at zero
- use second argument of calls if present, otherwise assume UB at zero,
- create 2 argument .CLZ/.CTZ calls if needed.
- * tree-vect-stmts.cc (vectorizable_call): Handle 2 argument .CLZ/.CTZ
- calls.
- * tree-ssa-loop-niter.cc (build_cltz_expr): Create 2 argument
- .CLZ/.CTZ calls if needed.
- * tree-ssa-forwprop.cc (simplify_count_trailing_zeroes): Create 2
- argument .CTZ calls if needed.
- * tree-ssa-phiopt.cc (cond_removal_in_builtin_zero_pattern): Handle
- 2 argument .CLZ/.CTZ calls, handle BITINT_TYPE, create 2 argument
- .CLZ/.CTZ calls.
- * doc/extend.texi (__builtin_clzg, __builtin_ctzg, __builtin_clrsbg,
- __builtin_ffsg, __builtin_parityg, __builtin_popcountg): Document.
-
-2023-11-14 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112330
- * config/loongarch/genopts/loongarch.opt.in: Add
- -m[no]-pass-relax-to-as. Change the default of -m[no]-relax to
- account conditional branch relaxation support status.
- * config/loongarch/loongarch.opt: Regenerate.
- * configure.ac (gcc_cv_as_loongarch_cond_branch_relax): Check if
- the assembler supports conditional branch relaxation.
- * configure: Regenerate.
- * config.in: Regenerate. Note that there are some unrelated
- changes introduced by r14-5424 (which does not contain a
- config.in regeneration).
- * config/loongarch/loongarch-opts.h
- (HAVE_AS_COND_BRANCH_RELAXATION): Define to 0 if not defined.
- * config/loongarch/loongarch-driver.h (ASM_MRELAX_DEFAULT):
- Define.
- (ASM_MRELAX_SPEC): Define.
- (ASM_SPEC): Use ASM_MRELAX_SPEC instead of "%{mno-relax}".
- * config/loongarch/loongarch.cc: Take the setting of
- -m[no-]relax into account when determining the default of
- -mexplicit-relocs=.
- * doc/invoke.texi: Document -m[no-]relax and
- -m[no-]pass-mrelax-to-as for LoongArch. Update the default
- value of -mexplicit-relocs=.
-
-2023-11-14 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/112496
- * tree-vect-loop.cc (vectorizable_nonlinear_induction): Return
- false when !tree_nop_conversion_p (TREE_TYPE (vectype),
- TREE_TYPE (init_expr)).
-
-2023-11-14 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/sync.md (mem_thread_fence): Remove redundant
- check.
- (mem_thread_fence_1): Emit finer-grained DBAR hints for
- different memory models, instead of 0.
-
-2023-11-14 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112511
- * tree.cc (type_contains_placeholder_1): Handle BITINT_TYPE like
- INTEGER_TYPE.
-
-2023-11-14 Jakub Jelinek <jakub@redhat.com>
- Hu, Lin1 <lin1.hu@intel.com>
-
- PR target/112435
- * config/i386/sse.md (avx512vl_shuf_<shuffletype>32x4_1<mask_name>,
- <mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): Add
- alternative with just x instead of v constraints and xjm instead of
- vm and use vblendps as optimization only with that alternative.
-
-2023-11-14 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/105735
- PR tree-optimization/111972
- * tree-scalar-evolution.cc
- (analyze_and_compute_bitop_with_inv_effect): Handle bitop with
- INTEGER_CST.
-
-2023-11-13 Arsen Arsenović <arsen@aarsen.me>
-
- * configure: Regenerate.
- * aclocal.m4: Regenerate.
- * Makefile.in (LIBDEPS): Remove (potential) ./ prefix from
- LIBINTL_DEP.
- * doc/install.texi: Document new (notable) flags added by the
- optional gettext tree and by AM_GNU_GETTEXT. Document libintl/libc
- with gettext dependency.
-
-2023-11-13 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.h (gen_pushfl): New prototype.
- (gen_popfl): Ditto.
- * config/i386/i386-expand.cc (ix86_expand_builtin)
- [case IX86_BUILTIN_READ_FLAGS]: Use gen_pushfl.
- [case IX86_BUILTIN_WRITE_FLAGS]: Use gen_popfl.
- * config/i386/i386.cc (gen_pushfl): New function.
- (gen_popfl): Ditto.
- * config/i386/i386.md (unspec): Add UNSPEC_PUSHFL and UNSPEC_POPFL.
- (@pushfl<mode>2): Rename from *pushfl<mode>2.
- Rewrite as unspec using UNSPEC_PUSHFL.
- (@popfl<mode>1): Rename from *popfl<mode>1.
- Rewrite as unspec using UNSPEC_POPFL.
-
-2023-11-13 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112494
- * config/i386/i386.cc (ix86_cc_mode) [default]: Return CCmode.
-
-2023-11-13 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-vsetvl.cc (source_equal_p): Use pointer
- equality for REG_EQUAL.
-
-2023-11-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112495
- * tree-data-ref.cc (runtime_alias_check_p): Reject checks
- between different address spaces.
-
-2023-11-13 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112487
- * tree-inline.cc (setup_one_parameter): When the parameter
- is unused only insert a debug bind when there's not a gross
- mismatch in value and declared parameter type. Do not assert
- there effectively isn't.
-
-2023-11-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc
- (rvv_builder::combine_sequence_use_merge_profitable_p): New function.
- (expand_vector_init_merge_combine_sequence): Ditto.
- (expand_vec_init): Adapt for new optimization.
-
-2023-11-13 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386-expand.cc
- (ix86_expand_vector_init_duplicate): Handle V4HF/V4BF and
- V2HF/V2BF.
- (ix86_expand_vector_init_one_nonzero): Ditto.
- (ix86_expand_vector_init_one_var): Ditto.
- (ix86_expand_vector_init_general): Ditto.
- (ix86_expand_vector_set_var): Ditto.
- (ix86_expand_vector_set): Ditto.
- (ix86_expand_vector_extract): Ditto.
- * config/i386/mmx.md
- (mmxdoublevecmode): Extend to V4HF/V4BF/V2HF/V2BF.
- (*mmx_pinsrw): Extend to V4FI_64, add a new alternative (&x,
- x, x), add a new define_split after the pattern.
- (*mmx_pextrw<mode>): New define_insn.
- (mmx_pshufw_1): Rename to ..
- (mmx_pshufw<mode>_1): .. this, extend to V4FI_64.
- (*mmx_pblendw64): Extend to V4FI_64.
- (*vec_dup<mode>): New define_insn.
- (vec_setv4hi): Rename to ..
- (vec_set<mode>): .. this, and extend to V4FI_64
- (vec_extractv4hihi): Rename to ..
- (vec_extract<mode><mmxscalarmodelower>): .. this, and extend
- to V4FI_64.
- (vec_init<mode><mmxscalarmodelower>): New define_insn.
- (*pinsrw): Extend to V2FI_32, add a new alternative (&x,
- x, x), and add a new define_split after it.
- (*pextrw<mode>): New define_insn.
- (vec_setv2hi): Rename to ..
- (vec_set<mode>): .. this, extend to V2FI_32.
- (vec_extractv2hihi): Rename to ..
- (vec_extract<mode><mmxscalarmodelower>): .. this, extend to
- V2FI_32.
- (*punpckwd): Extend to V2FI_32.
- (*pshufw_1): Rename to ..
- (*pshufw<mode>_1): .. this, extend to V2FI_32.
- (vec_initv2hihi): Rename to ..
- (vec_init<mode><mmxscalarmodelower>): .. this, and extend to
- V2FI_32.
- (*vec_dup<mode>): New define_insn.
- * config/i386/sse.md (*vec_extract<mode>): Refine constraint
- from v to Yw.
-
-2023-11-13 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md (UNSPEC_ARC_CC_NEZ): New UNSPEC that
- represents the carry flag being set if the operand is non-zero.
- (adc_f): New define_insn representing adc with updated flags.
- (ashrdi3): New define_expand that only handles shifts by 1.
- (ashrdi3_cnt1): New pre-reload define_insn_and_split.
- (lshrdi3): New define_expand that only handles shifts by 1.
- (lshrdi3_cnt1): New pre-reload define_insn_and_split.
- (rrcsi2): New define_insn for rrc (SImode rotate right through carry).
- (rrcsi2_carry): Likewise for rrc.f, as above but updating flags.
- (rotldi3): New define_expand that only handles rotates by 1.
- (rotldi3_cnt1): New pre-reload define_insn_and_split.
- (rotrdi3): New define_expand that only handles rotates by 1.
- (rotrdi3_cnt1): New pre-reload define_insn_and_split.
- (lshrsi3_cnt1_carry): New define_insn for lsr.f.
- (ashrsi3_cnt1_carry): New define_insn for asr.f.
- (btst_0_carry): New define_insn for asr.f without result.
-
-2023-11-13 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.cc (TARGET_FOLD_BUILTIN): Define to
- arc_fold_builtin.
- (arc_fold_builtin): New function. Convert ARC_BUILTIN_SWAP
- into a rotate. Evaluate ARC_BUILTIN_NORM and
- ARC_BUILTIN_NORMW of constant arguments.
- * config/arc/arc.md (UNSPEC_ARC_SWAP): Delete.
- (normw): Make output template/assembler whitespace consistent.
- (swap): Remove define_insn, only use of SWAP UNSPEC.
- * config/arc/builtins.def: Tweak indentation.
- (SWAP): Expand using rotlsi2_cnt16 instead of using swap.
-
-2023-11-13 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386.md (<insn><dwi>3_doubleword_lowpart): New
- define_insn_and_split to optimize register usage of doubleword
- right shifts followed by truncation.
-
-2023-11-13 Jakub Jelinek <jakub@redhat.com>
-
- * config/i386/constraints.md: Remove j constraint letter from list of
- unused letters.
-
-2023-11-13 Xi Ruoyao <xry111@xry111.site>
-
- PR rtl-optimization/112483
- * simplify-rtx.cc (simplify_binary_operation_1) <case COPYSIGN>:
- Fix the simplification of (fcopysign x, NEGATIVE_CONST).
-
-2023-11-13 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/111967
- * gimple-range-cache.cc (block_range_cache::set_bb_range): Grow
- m_ssa_ranges to num_ssa_names rather than num_ssa_names + 1.
- (block_range_cache::dump): Iterate from 1 rather than 0. Don't use
- ssa_name (x) unless m_ssa_ranges[x] is non-NULL. Iterate to
- m_ssa_ranges.length () rather than num_ssa_names.
-
-2023-11-13 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (LD_AT_LEAST_32_BIT): New mode
- iterator.
- (ST_ANY): New mode iterator.
- (define_peephole2): Use LD_AT_LEAST_32_BIT instead of GPR and
- ST_ANY instead of QHWD for applicable patterns.
-
-2023-11-13 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112476
- * config/loongarch/loongarch.cc
- (loongarch_expand_vec_cond_mask_expr): Call simplify_gen_subreg
- instead of gen_rtx_SUBREG.
-
-2023-11-13 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Add bridge mode to lrint and lround
- pattern.
- * config/riscv/riscv-protos.h (expand_vec_lrint): Add new arg
- bridge machine mode.
- (expand_vec_lround): Ditto.
- * config/riscv/riscv-v.cc (emit_vec_widden_cvt_f_f): New helper
- func impl to emit vfwcvt.f.f.
- (emit_vec_rounding_to_integer): Handle the HF to DI rounding
- with the bridge mode.
- (expand_vec_lrint): Reorder the args.
- (expand_vec_lround): Ditto.
- (expand_vec_lceil): Ditto.
- (expand_vec_lfloor): Ditto.
- * config/riscv/vector-iterators.md: Add vector HFmode and bridge
- mode for converting to DI.
-
-2023-11-12 Jeff Law <jlaw@ventanamicro.com>
-
- Revert:
- 2023-11-11 Jin Ma <jinma@linux.alibaba.com>
-
- * haifa-sched.cc (use_or_clobber_starts_range_p): New.
- (prune_ready_list): USE or CLOBBER should delay execution
- if it starts a new live range.
-
-2023-11-12 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (*stack_protect_set_4s_<mode>_di):
- Remove alternative 0.
-
-2023-11-11 Eric Botcazou <ebotcazou@adacore.com>
-
- * ipa-cp.cc (print_ipcp_constant_value): Move to...
- (values_equal_for_ipcp_p): Deal with VAR_DECLs from the
- constant pool.
- * ipa-prop.cc (ipa_print_constant_value): ...here. Likewise.
- (ipa_print_node_jump_functions_for_edge): Call the function
- ipa_print_constant_value to print IPA_JF_CONST elements.
-
-2023-11-11 Jin Ma <jinma@linux.alibaba.com>
-
- * haifa-sched.cc (use_or_clobber_starts_range_p): New.
- (prune_ready_list): USE or CLOBBER should delay execution
- if it starts a new live range.
-
-2023-11-11 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112430
- * tree-ssa-math-opts.cc (match_uaddc_usubc): Remove temp_stmts in the
- order they were pushed rather than in reverse order. Call
- release_defs after gsi_remove.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.backprop): New hook.
- * doc/tm.texi.in (TARGET_MODE_BACKPROP): New @hook.
- * doc/tm.texi: Regenerate.
- * mode-switching.cc (struct bb_info): Add single_succ.
- (confluence_info): Add transp field.
- (single_succ_confluence_n, single_succ_transfer): New functions.
- (backprop_confluence_n, backprop_transfer): Likewise.
- (optimize_mode_switching): Use them. Push mode transitions onto
- a block's incoming edges, if the backprop hook requires it.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.confluence): New hook.
- * doc/tm.texi (TARGET_MODE_CONFLUENCE): New @hook.
- * doc/tm.texi.in: Regenerate.
- * mode-switching.cc (confluence_info): New variable.
- (mode_confluence, forward_confluence_n, forward_transfer): New
- functions.
- (optimize_mode_switching): Use them to calculate mode_in when
- TARGET_MODE_CONFLUENCE is defined.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (commit_mode_sets): Use 1-based edge aux values.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.after): Add a regs_live parameter.
- * doc/tm.texi: Regenerate.
- * config/epiphany/epiphany-protos.h (epiphany_mode_after): Update
- accordingly.
- * config/epiphany/epiphany.cc (epiphany_mode_needed): Likewise.
- (epiphany_mode_after): Likewise.
- * config/i386/i386.cc (ix86_mode_after): Likewise.
- * config/riscv/riscv.cc (riscv_mode_after): Likewise.
- * config/sh/sh.cc (sh_mode_after): Likewise.
- * mode-switching.cc (optimize_mode_switching): Likewise.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.needed): Add a regs_live parameter.
- * doc/tm.texi: Regenerate.
- * config/epiphany/epiphany-protos.h (epiphany_mode_needed): Update
- accordingly.
- * config/epiphany/epiphany.cc (epiphany_mode_needed): Likewise.
- * config/epiphany/mode-switch-use.cc (insert_uses): Likewise.
- * config/i386/i386.cc (ix86_mode_needed): Likewise.
- * config/riscv/riscv.cc (riscv_mode_needed): Likewise.
- * config/sh/sh.cc (sh_mode_needed): Likewise.
- * mode-switching.cc (optimize_mode_switching): Likewise.
- (create_pre_exit): Likewise, using the DF simulate functions
- to calculate the required information.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.eh_handler): New hook.
- * doc/tm.texi.in (TARGET_MODE_EH_HANDLER): New @hook.
- * doc/tm.texi: Regenerate.
- * mode-switching.cc (optimize_mode_switching): Use eh_handler
- to get the mode on entry to an exception handler.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (optimize_mode_switching): Mark the exit
- block as nontransparent if it requires a specific mode.
- Handle the entry and exit mode as sibling rather than nested
- concepts. Remove outdated comment.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (optimize_mode_switching): Initially
- compute transparency in a bit-per-block bitmap.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (seginfo): Add a prev_mode field.
- (new_seginfo): Take and initialize the prev_mode.
- (optimize_mode_switching): Update calls accordingly.
- Use the recorded modes during the emit phase, rather than
- computing one on the fly.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (add_seginfo): Replace head pointer with
- a pointer to the tail pointer.
- (optimize_mode_switching): Update calls accordingly.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (optimize_mode_switching): Call
- df_note_add_problem.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def: Tweak documentation of mode-switching hooks.
- * doc/tm.texi.in (OPTIMIZE_MODE_SWITCHING): Tweak documentation.
- (NUM_MODES_FOR_MODE_SWITCHING): Likewise.
- * doc/tm.texi: Regenerate.
-
-2023-11-11 Martin Uecker <uecker@tugraz.at>
-
- PR c/110815
- PR c/112428
- * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
- remove warning for parameters declared with `static`.
-
-2023-11-11 Joern Rennecke <joern.rennecke@embecosm.com>
-
- * doc/sourcebuild.texi (Scan the assembly output): Document change.
-
-2023-11-10 Mao <sray@live.com>
-
- PR middle-end/110983
- * doc/invoke.texi (Option Summary): Add -fpatchable-function-entry.
-
-2023-11-10 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.md (length): Fix indentation for branch and
- jump length calculation expressions.
-
-2023-11-10 Eric Botcazou <ebotcazou@adacore.com>
-
- * fold-const.cc (operand_compare::operand_equal_p) <CONSTRUCTOR>:
- Deal with nonempty constant CONSTRUCTORs.
- (operand_compare::hash_operand) <CONSTRUCTOR>: Hash DECL_FIELD_OFFSET
- and DECL_FIELD_BIT_OFFSET for FIELD_DECLs.
-
-2023-11-10 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR target/112337
- * ira-costs.cc: (validate_autoinc_and_mem_addr_p): New function.
- (equiv_can_be_consumed_p): Use it.
-
-2023-11-10 Richard Sandiford <richard.sandiford@arm.com>
-
- * read-rtl.cc (md_reader::read_mapping): Allow iterators to
- include other iterators.
- * doc/md.texi: Document the change.
- * config/aarch64/iterators.md (DREG2, VQ2, TX2, DX2, SX2): Include
- the iterator that is being duplicated, rather than reproducing it.
- (VSTRUCT_D): Redefine using VSTRUCT_[234]D.
- (VSTRUCT_Q): Likewise VSTRUCT_[234]Q.
- (VSTRUCT_2QD, VSTRUCT_3QD, VSTRUCT_4QD, VSTRUCT_QD): Redefine using
- the individual D and Q iterators.
-
-2023-11-10 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (stack_protect_set_1 peephole2):
- Explicitly check operand 2 for word_mode.
- (stack_protect_set_1 peephole2 #2): Ditto.
- (stack_protect_set_2 peephole2): Ditto.
- (stack_protect_set_3 peephole2): Ditto.
- (*stack_protect_set_4z_<mode>_di): New insn patter.
- (*stack_protect_set_4s_<mode>_di): Ditto.
- (stack_protect_set_4 peephole2): New peephole2 pattern to
- substitute stack protector scratch register clear with unrelated
- register initialization involving zero/sign-extend instruction.
-
-2023-11-10 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (shift): Use SAL insted of SLL
- for ashift insn mnemonic.
-
-2023-11-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR tree-optimization/112438
- * tree-vect-loop.cc (vectorizable_induction): Bugfix when
- LOOP_VINFO_USING_SELECT_VL_P.
-
-2023-11-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- * config/riscv/riscv-v.cc
- (rvv_builder::combine_sequence_use_slideup_profitable_p): New function.
- (expand_vector_init_slideup_combine_sequence): Ditto.
- (expand_vec_init): Add slideup combine optimization.
-
-2023-11-10 Robin Dapp <rdapp@ventanamicro.com>
-
- PR tree-optimization/112464
- * tree-vect-loop.cc (vectorize_fold_left_reduction): Use
- vect_orig_stmt on scalar_dest_def_info.
-
-2023-11-10 Jin Ma <jinma@linux.alibaba.com>
-
- * config/riscv/riscv.cc (riscv_for_each_saved_reg): Place the interrupt
- operation before the XTheadMemPair.
-
-2023-11-10 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110221
- * tree-vect-slp.cc (vect_schedule_slp_node): When loop
- masking / len is applied make sure to not schedule
- intenal defs outside of the loop.
-
-2023-11-10 Andrew Stubbs <ams@codesourcery.com>
-
- * expr.cc (store_constructor): Add "and" operation to uniform mask
- generation.
-
-2023-11-10 Andrew Stubbs <ams@codesourcery.com>
-
- PR target/112308
- * config/gcn/gcn-valu.md (add<mode>3<exec_clobber>): Fix B constraint
- and switch to the new format.
- (add<mode>3_dup<exec_clobber>): Likewise.
- (add<mode>3_vcc<exec_vcc>): Likewise.
- (add<mode>3_vcc_dup<exec_vcc>): Likewise.
- (add<mode>3_vcc_zext_dup): Likewise.
- (add<mode>3_vcc_zext_dup_exec): Likewise.
- (add<mode>3_vcc_zext_dup2): Likewise.
- (add<mode>3_vcc_zext_dup2_exec): Likewise.
-
-2023-11-10 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112469
- * match.pd (cond ? op a : b -> .COND_op (cond, a, b)): Add
- missing view_converts.
-
-2023-11-10 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn.cc (gcn_expand_reduc_scalar): Add clobber to DImode
- min/max instructions.
-
-2023-11-10 Chenghui Pan <panchenghui@loongson.cn>
-
- * config/loongarch/lsx.md: Fix instruction name typo in
- lsx_vreplgr2vr_<lsxfmt_f> template.
-
-2023-11-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (vec_init<mode><vel>): Split patterns.
-
-2023-11-10 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-11-10 Pan Li <pan2.li@intel.com>
- * config/riscv/riscv-v.cc (expand_vector_init_trailing_same_elem):
- New fun impl to expand the insn when trailing same elements.
- (expand_vec_init): Try trailing same elements when vec_init.
-
-2023-11-10 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (expand_vector_init_trailing_same_elem):
- New fun impl to expand the insn when trailing same elements.
- (expand_vec_init): Try trailing same elements when vec_init.
-
-2023-11-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_copysign<mode>): Remove.
- * config/riscv/autovec.md (cond_copysign<mode>): New pattern.
-
-2023-11-10 Pan Li <pan2.li@intel.com>
-
- PR target/112432
- * internal-fn.def (LRINT): Add FLOATN support.
- (LROUND): Ditto.
- (LLRINT): Ditto.
- (LLROUND): Ditto.
-
-2023-11-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/combiner.md (single bit sign_extract): Avoid recently
- added patterns for H8/SX.
- (single bit zero_extract): New patterns.
-
-2023-11-10 liuhongt <hongtao.liu@intel.com>
-
- PR target/112443
- * config/i386/sse.md (*avx2_pcmp<mode>3_4): Fix swap condition
- from LT to GT since there's not in the pattern.
- (*avx2_pcmp<mode>3_5): Ditto.
-
-2023-11-10 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.cc (bpf_print_register): Accept modifier code 'W'
- to force emitting register names using the wN form.
- * config/bpf/bpf.md (*mulsidi3_zeroextend): Force operands to
- always use wN written form in pseudo-C assembly syntax.
-
-2023-11-09 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc (layout::m_line_table): New field.
- (compatible_locations_p): Convert to...
- (layout::compatible_locations_p): ...this, replacing uses of
- line_table global with m_line_table.
- (layout::layout): Convert "richloc" param from a pointer to a
- const reference. Initialize m_line_table member.
- (layout::maybe_add_location_range): Replace uses of line_table
- global with m_line_table. Pass the latter to
- linemap_client_expand_location_to_spelling_point.
- (layout::print_leading_fixits): Pass m_line_table to
- affects_line_p.
- (layout::print_trailing_fixits): Likewise.
- (gcc_rich_location::add_location_if_nearby): Update for change
- to layout ctor params.
- (diagnostic_show_locus): Convert to...
- (diagnostic_context::maybe_show_locus): ...this, converting
- richloc param from a pointer to a const reference. Make "loc"
- const. Split out printing part of function to...
- (diagnostic_context::show_locus): ...this.
- (selftest::test_offset_impl): Update for change to layout ctor
- params.
- (selftest::test_layout_x_offset_display_utf8): Likewise.
- (selftest::test_layout_x_offset_display_tab): Likewise.
- (selftest::test_tab_expansion): Likewise.
- * diagnostic.h (diagnostic_context::maybe_show_locus): New decl.
- (diagnostic_context::show_locus): New decl.
- (diagnostic_show_locus): Convert from a decl to an inline function.
- * gdbinit.in (break-on-diagnostic): Update from a breakpoint
- on diagnostic_show_locus to one on
- diagnostic_context::maybe_show_locus.
- * genmatch.cc (linemap_client_expand_location_to_spelling_point):
- Add "set" param and use it in place of line_table global.
- * input.cc (expand_location_1): Likewise.
- (expand_location): Update for new param of expand_location_1.
- (expand_location_to_spelling_point): Likewise.
- (linemap_client_expand_location_to_spelling_point): Add "set"
- param and use it in place of line_table global.
- * tree-diagnostic-path.cc (event_range::print): Pass line_table
- for new param of linemap_client_expand_location_to_spelling_point.
-
-2023-11-09 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (@stack_protect_set_1_<PTR:mode>_<W:mode>):
- Use W mode iterator instead of SWI48. Output MOV instead of XOR
- for TARGET_USE_MOV0.
- (stack_protect_set_1 peephole2): Use integer modes with
- mode size <= word mode size for operand 3.
- (stack_protect_set_1 peephole2 #2): New peephole2 pattern to
- substitute stack protector scratch register clear with unrelated
- register initialization, originally in front of stack
- protector sequence.
- (*stack_protect_set_3_<PTR:mode>_<SWI48:mode>): New insn pattern.
- (stack_protect_set_1 peephole2): New peephole2 pattern to
- substitute stack protector scratch register clear with unrelated
- register initialization involving LEA instruction.
-
-2023-11-09 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/110215
- * ira-lives.cc: (add_conflict_from_region_landing_pads): New
- function.
- (process_bb_node_lives): Use it.
-
-2023-11-09 Alexandre Oliva <oliva@adacore.com>
-
- * config/i386/i386.cc (symbolic_base_address_p,
- base_address_p): New, factored out from...
- (extract_base_offset_in_addr): ... here and extended to
- recognize REG+GOTOFF, as in gcc.target/i386/sse2-load-multi.c
- and sse2-store-multi.c with PIE enabled by default.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64-sve.md (cond_copysign<mode>): New.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64.md (copysign<GPF:mode>3): Handle
- copysign (x, -1).
- * config/aarch64/aarch64-simd.md (copysign<mode>3): Likewise.
- * config/aarch64/aarch64-sve.md (copysign<mode>3): Likewise.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64.md (<optab><mode>3): Add SVE split case.
- * config/aarch64/aarch64-simd.md (ior<mode>3<vczle><vczbe>): Likewise.
- * config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64.md (*mov<mode>_aarch64, *movsi_aarch64,
- *movdi_aarch64): Add new w -> Z case.
- * config/aarch64/iterators.md (Vbtype): Add QI and HI.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p,
- aarch64_maybe_generate_simd_constant): New.
- * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VQMOV:mode>,
- *aarch64_simd_mov<VDMOV:mode>): Add new coden for special constants.
- * config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int):
- Take optional mode.
- (aarch64_simd_special_constant_p,
- aarch64_maybe_generate_simd_constant): New.
- * config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for
- special constants.
- * config/aarch64/constraints.md (Dx): new.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * internal-fn.def (COPYSIGN): New.
- * match.pd (UNCOND_BINARY, COND_BINARY): Map IFN_COPYSIGN to
- IFN_COND_COPYSIGN.
- * optabs.def (cond_copysign_optab, cond_len_copysign_optab): New.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * match.pd: Add new neg+abs rule, remove inverse copysign rule.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * match.pd: expand existing copysign optimizations.
-
-2023-11-09 Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
-
- PR driver/111605
- * collect2.cc (main): Do not prepend target triple to
- -fuse-ld=lld,mold.
-
-2023-11-09 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111133
- * tree-vect-stmts.cc (vect_build_scatter_store_calls):
- Remove and refactor to ...
- (vect_build_one_scatter_store_call): ... this new function.
- (vectorizable_store): Use vect_check_scalar_mask to record
- the SLP node for the mask operand. Code generate scatters
- with builtin decls from the main scatter vectorization
- path and prepare that for SLP.
- * tree-vect-slp.cc (vect_get_operand_map): Do not look
- at the VDEF to decide between scatter or gather since that
- doesn't work for patterns. Use the LHS being an SSA_NAME
- or not instead.
-
-2023-11-09 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv.cc (riscv_frm_emit_after_bb_end): Only
- perform once emit when at least one succ edge is abnormal.
-
-2023-11-09 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (vect_verify_full_masking_avx512):
- Check we have integer mode masks as required by
- vect_get_loop_mask.
-
-2023-11-09 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112444
- * tree-ssa-sccvn.cc (visit_phi): Avoid using not visited
- defs as undefined vals.
-
-2023-11-09 YunQiang Su <yunqiang.su@cipunited.com>
-
- * config/mips/mips.cc(mips_option_override): Set mips_abs to
- 2008, if mips_abs is default and mips_nan is 2008.
-
-2023-11-09 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document
- -Wreturn-mismatch. Update -Wreturn-type documentation.
-
-2023-11-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.md: Remove UNSPEC_VEC_ELTSWAP.
- * config/s390/vector.md (eltswapv16qi): New expander.
- (*eltswapv16qi): New insn and splitter.
- (eltswapv8hi): New insn and splitter.
- (eltswap<mode>): New insn and splitter for modes V_HW_4 as well
- as V_HW_2.
- * config/s390/vx-builtins.md (eltswap<mode>): Remove.
- (*eltswapv16qi): Remove.
- (*eltswap<mode>): Remove.
- (*eltswap<mode>_emu): Remove.
-
-2023-11-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.cc (expand_perm_with_rot): Remove.
- (expand_perm_reverse_elements): New.
- (expand_perm_with_vster): Remove.
- (expand_perm_with_vstbrq): Remove.
- (vectorize_vec_perm_const_1): Replace removed functions with new
- one.
-
-2023-11-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.cc (expand_perm_with_merge): Deal with cases
- where vmr{l,h} are still applicable if the operands are swapped.
- (expand_perm_with_vpdi): Likewise for vpdi.
-
-2023-11-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.md (VX_CONV_INT): Remove iterator.
- (gf): Add float mappings.
- (TOINT, toint): New attribute.
- (*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13):
- Remove.
- (*fixuns_trunc<mode><toint>2_z13): Add.
- (*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13):
- Remove.
- (*fix_trunc<mode><toint>2_bfp_z13): Add.
- (*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13): Remove.
- (*floatuns<toint><mode>2_z13): Add.
- * config/s390/vector.md (VX_VEC_CONV_INT): Remove iterator.
- (float<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2): Remove.
- (float<tointvec><mode>2): Add.
- (floatuns<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2): Remove.
- (floatuns<tointvec><mode>2): Add.
- (fix_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2):
- Remove.
- (fix_trunc<mode><tointvec>2): Add.
- (fixuns_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2):
- Remove.
- (fixuns_trunc<VX_VEC_CONV_BFP:mode><tointvec>2): Add.
-
-2023-11-09 Jakub Jelinek <jakub@redhat.com>
-
- PR c/112339
- * attribs.cc (attribute_ignored_p): Only return true for
- attr_namespace_ignored_p if as is NULL.
- (decl_attributes): Never add ignored attributes.
-
-2023-11-09 Jin Ma <jinma@linux.alibaba.com>
-
- * config/riscv/bitmanip.md: Avoid the conflict between
- zbb and xtheadmemidx in patterns.
-
-2023-11-09 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Record
- to the correct simd_clone_info.
-
-2023-11-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (costs::preferred_new_lmul_p): Fix ICE.
-
-2023-11-09 Alexandre Oliva <oliva@adacore.com>
-
- * tree-cfg.cc (assign_discriminators): Handle debug stmts.
-
-2023-11-08 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/82524
- * config/i386/i386.md (*add<mode>_1_slp):
- Split insn only for unmatched operand 0.
- (*sub<mode>_1_slp): Ditto.
- (*<any_logic:code><mode>_1_slp): Merge pattern from "*and<mode>_1_slp"
- and "*<any_logic:code><mode>_1_slp" using any_logic code iterator.
- Split insn only for unmatched operand 0.
- (*neg<mode>1_slp): Split insn only for unmatched operand 0.
- (*one_cmpl<mode>_1_slp): Ditto.
- (*ashl<mode>3_1_slp): Ditto.
- (*<any_shiftrt:insn><mode>_1_slp): Ditto.
- (*<any_rotate:insn><mode>_1_slp): Ditto.
- (*addqi_ext<mode>_1): Redefine as define_insn_and_split. Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*<plusminus:insn>qi_ext<mode>_2): Merge pattern from
- "*addqi_ext<mode>_2" and "*subqi_ext<mode>_2" using plusminus code
- iterator. Redefine as define_insn_and_split. Add alternative 1
- and split insn after reload for unmatched operand 0.
- (*subqi_ext<mode>_1): Redefine as define_insn_and_split. Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*<any_logic:code>qi_ext<mode>_0): Merge pattern from
- "*andqi_ext<mode>_0" and and "*<any_logic:code>qi_ext<mode>_0" using
- any_logic code iterator.
- (*<any_logic:code>qi_ext<mode>_1): Merge pattern from
- "*andqi_ext<mode>_1" and "*<any_logic:code>qi_ext<mode>_1" using
- any_logic code iterator. Redefine as define_insn_and_split. Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*<any_logic:code>qi_ext<mode>_1_cc): Merge pattern from
- "*andqi_ext<mode>_1_cc" and "*xorqi_ext<mode>_1_cc" using any_logic
- code iterator. Redefine as define_insn_and_split. Add alternative 1
- and split insn after reload for unmatched operand 0.
- (*<any_logic:code>qi_ext<mode>_2): Merge pattern from
- "*andqi_ext<mode>_2" and "*<any_or:code>qi_ext<mode>_2" using
- any_logic code iterator. Redefine as define_insn_and_split. Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*<any_logic:code>qi_ext<mode>_3): Redefine as define_insn_and_split.
- Add alternative 1 and split insn after reload for unmatched operand 0.
- (*negqi_ext<mode>_1): Rename from "*negqi_ext<mode>_2". Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*one_cmplqi_ext<mode>_1): Ditto.
- (*ashlqi_ext<mode>_1): Ditto.
- (*<any_shiftrt:insn>qi_ext<mode>_1): Ditto.
-
-2023-11-08 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_load): Adjust offset
- vector gathering for SLP of emulated gathers.
-
-2023-11-08 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (vect_slp_child_index_for_operand):
- Add gatherscatter_p argument.
- * tree-vect-slp.cc (vect_slp_child_index_for_operand): Likewise.
- Pass it on.
- * tree-vect-stmts.cc (vect_check_store_rhs): Turn the rhs
- argument into an output, also output the SLP node associated
- with it.
- (vectorizable_simd_clone_call): Adjust.
- (vectorizable_store): Likewise.
- (vectorizable_load): Likewise.
-
-2023-11-08 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_load): Use the correct
- vectorized mask operand.
-
-2023-11-08 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/vector.md (*vsetvldi_no_side_effects_si_extend):
- New combine pattern.
-
-2023-11-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc: Fix ICE.
-
-2023-11-08 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-c.cc (riscv_check_builtin_call): Eliminate warning.
-
-2023-11-08 Hongyu Wang <hongyu.wang@intel.com>
-
- PR target/112394
- * config/i386/constraints.md (jc): New constraint that prohibits
- EGPR on -mno-avx.
- * config/i386/i386.md (*movdi_internal): Change r constraint
- corresponds to Yd.
- (*movti_internal): Likewise.
-
-2023-11-08 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Mention C diagnostics
- for -fpermissive.
-
-2023-11-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112092
- * config/riscv/riscv-vector-builtins-bases.cc: Normalize the vsetvls.
-
-2023-11-08 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/111907
- * config/i386/i386.md (avx_noavx512vl): New definition for isa
- attribute.
- * config/i386/sse.md (*andnot<mode>3): Change isa attribute from
- avx_noavx512f to avx_noavx512vl.
-
-2023-11-07 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Remove the size check of lfloor.
- * config/riscv/riscv-v.cc (expand_vec_lfloor): Leverage
- emit_vec_rounding_to_integer for floor.
-
-2023-11-07 Robin Dapp <rdapp@ventanamicro.com>
-
- PR tree-optimization/112361
- PR target/112359
- PR middle-end/112406
- * tree-if-conv.cc (convert_scalar_cond_reduction): Remember if
- loop was versioned and only then create COND_OPs.
- (predicate_scalar_phi): Do not create COND_OP when not
- vectorizing.
- * tree-vect-loop.cc (vect_expand_fold_left): Re-create
- VEC_COND_EXPR.
- (vectorize_fold_left_reduction): Pass mask to
- vect_expand_fold_left.
-
-2023-11-07 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/predicates.md ("flags_reg_operand"):
- Make predicate special to avoid automatic mode checks.
-
-2023-11-07 Martin Jambor <mjambor@suse.cz>
-
- * configure: Regenerate.
-
-2023-11-07 Kwok Cheung Yeung <kcy@codesourcery.com>
-
- * lto-cgraph.cc (enum LTO_symtab_tags): Add tag for indirect
- functions.
- (output_offload_tables): Write indirect functions.
- (input_offload_tables): read indirect functions.
- * lto-section-names.h (OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): New.
- * omp-builtins.def (BUILT_IN_GOMP_TARGET_MAP_INDIRECT_PTR): New.
- * omp-offload.cc (offload_ind_funcs): New.
- (omp_discover_implicit_declare_target): Add functions marked with
- 'omp declare target indirect' to indirect functions list.
- (omp_finish_file): Add indirect functions to section for offload
- indirect functions.
- (execute_omp_device_lower): Redirect indirect calls on target by
- passing function pointer to BUILT_IN_GOMP_TARGET_MAP_INDIRECT_PTR.
- (pass_omp_device_lower::gate): Run pass_omp_device_lower if
- indirect functions are present on an accelerator device.
- * omp-offload.h (offload_ind_funcs): New.
- * tree-core.h (omp_clause_code): Add OMP_CLAUSE_INDIRECT.
- * tree.cc (omp_clause_num_ops): Add entry for OMP_CLAUSE_INDIRECT.
- (omp_clause_code_name): Likewise.
- * tree.h (OMP_CLAUSE_INDIRECT_EXPR): New.
- * config/gcn/mkoffload.cc (process_asm): Process offload_ind_funcs
- section. Count number of indirect functions.
- (process_obj): Emit number of indirect functions.
- * config/nvptx/mkoffload.cc (ind_func_ids, ind_funcs_tail): New.
- (process): Emit offload_ind_func_table in PTX code. Emit indirect
- function names and count in image.
- * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Mark
- indirect functions in PTX code with IND_FUNC_MAP.
-
-2023-11-07 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/invoke.texi (-fopenmp, -fopenmp-simd): Adjust wording for
- attribute syntax supported also in C.
-
-2023-11-07 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_print_operand): Add a %Z
- modifier for SVE registers.
-
-2023-11-07 Joseph Myers <joseph@codesourcery.com>
-
- * builtins.def (DEF_C2X_BUILTIN): Rename to DEF_C23_BUILTIN and
- use flag_isoc23 and function_c23_misc.
- * config/rl78/rl78.cc (rl78_option_override): Compare
- lang_hooks.name with "GNU C23" not "GNU C2X".
- * coretypes.h (function_c2x_misc): Rename to function_c23_misc.
- * doc/cpp.texi (@code{__has_attribute}): Refer to C23 instead of
- C2x.
- * doc/extend.texi: Likewise.
- * doc/invoke.texi: Likewise.
- * dwarf2out.cc (highest_c_language, gen_compile_unit_die): Compare
- against and return "GNU C23" language string instead of "GNU C2X".
- * ginclude/float.h: Refer to C23 instead of C2X in comments.
- * ginclude/stdint-gcc.h: Likewise.
- * glimits.h: Likewise.
- * tree.h: Likewise.
-
-2023-11-07 Alexandre Oliva <oliva@adacore.com>
-
- * doc/sourcebuild.texi (opt_mstrict_align): New target.
-
-2023-11-07 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_len_<optab><v_double_trunc><mode>):
- New combine pattern.
- (*cond_len_<optab><v_quad_trunc><mode>): Ditto.
- (*cond_len_<optab><v_oct_trunc><mode>): Ditto.
- (*cond_len_extend<v_double_trunc><mode>): Ditto.
- (*cond_len_widen_reduc_plus_scal_<mode>): Ditto.
-
-2023-11-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112399
- * config/riscv/riscv-avlprop.cc
- (pass_avlprop::get_vlmax_ta_preferred_avl): Enhance AVL propagation.
- * config/riscv/t-riscv: Add new include.
-
-2023-11-07 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Remove the size check of lceil.l
- * config/riscv/riscv-v.cc (expand_vec_lceil): Leverage
- emit_vec_rounding_to_integer for ceil.
-
-2023-11-06 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa.cc (pa_asm_trampoline_template): Fix typo.
-
-2023-11-06 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa-linux.h (NEED_INDICATE_EXEC_STACK): Define to 1.
-
-2023-11-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc (class colorizer): Take just a
- pretty_printer rather than a diagnostic_context.
- (layout::layout): Make context param a const reference,
- and pretty_printer param non-optional.
- (layout::m_context): Drop field.
- (layout::m_options): New field.
- (layout::m_colorize_source_p): Drop field.
- (layout::m_show_labels_p): Drop field.
- (layout::m_show_line_numbers_p): Drop field.
- (layout::print_gap_in_line_numbering): Use m_options.
- (layout::calculate_line_spans): Likewise.
- (layout::calculate_linenum_width): Likewise.
- (layout::calculate_x_offset_display): Likewise.
- (layout::print_source_line): Likewise.
- (layout::start_annotation_line): Likewise.
- (layout::print_annotation_line): Likewise.
- (layout::print_line): Likewise.
- (gcc_rich_location::add_location_if_nearby): Update for changes to
- layout ctor.
- (diagnostic_show_locus): Likewise.
- (selftest::test_offset_impl): Likewise.
- (selftest::test_layout_x_offset_display_utf8): Likewise.
- (selftest::test_layout_x_offset_display_tab): Likewise.
- (selftest::test_tab_expansion): Likewise.
- * diagnostic.h (diagnostic_context::m_source_printing): Move
- declaration of struct outside diagnostic_context as...
- (struct diagnostic_source_printing_options)... this.
-
-2023-11-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_context::push_diagnostics): Convert
- to...
- (diagnostic_option_classifier::push): ...this.
- (diagnostic_context::pop_diagnostics): Convert to...
- (diagnostic_option_classifier::pop): ...this.
- (diagnostic_context::initialize): Move code to...
- (diagnostic_option_classifier::init): ...this new function.
- (diagnostic_context::finish): Move code to...
- (diagnostic_option_classifier::fini): ...this new function.
- (diagnostic_context::classify_diagnostic): Convert to...
- (diagnostic_option_classifier::classify_diagnostic): ...this.
- (diagnostic_context::update_effective_level_from_pragmas): Convert
- to...
- (diagnostic_option_classifier::update_effective_level_from_pragmas):
- ...this.
- (diagnostic_context::diagnostic_enabled): Update for refactoring.
- * diagnostic.h (struct diagnostic_classification_change_t): Move into...
- (class diagnostic_option_classifier): ...this new class.
- (diagnostic_context::option_unspecified_p): Update for move of
- fields into m_option_classifier.
- (diagnostic_context::classify_diagnostic): Likewise.
- (diagnostic_context::push_diagnostics): Likewise.
- (diagnostic_context::pop_diagnostics): Likewise.
- (diagnostic_context::update_effective_level_from_pragmas): Delete.
- (diagnostic_context::m_classify_diagnostic): Move into class
- diagnostic_option_classifier.
- (diagnostic_context::m_option_classifier): Likewise.
- (diagnostic_context::m_classification_history): Likewise.
- (diagnostic_context::m_n_classification_history): Likewise.
- (diagnostic_context::m_push_list): Likewise.
- (diagnostic_context::m_n_push): Likewise.
- (diagnostic_context::m_option_classifier): New.
-
-2023-11-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_context::set_urlifier): New.
- * diagnostic.h (diagnostic_context::set_urlifier): New decl.
- (diagnostic_context::m_urlifier): Make private.
- * gcc.cc (driver::global_initializations): Use set_urlifier rather
- than directly setting field.
- * toplev.cc (general_init): Likewise.
-
-2023-11-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_context::check_max_errors): Replace
- uses of diagnostic_kind_count with simple field acesss.
- (diagnostic_context::report_diagnostic): Likewise.
- (diagnostic_text_output_format::~diagnostic_text_output_format):
- Replace use of diagnostic_kind_count with
- diagnostic_context::diagnostic_count.
- * diagnostic.h (diagnostic_kind_count): Delete.
- (errorcount): Replace use of diagnostic_kind_count with
- diagnostic_context::diagnostic_count.
- (warningcount): Likewise.
- (werrorcount): Likewise.
- (sorrycount): Likewise.
-
-2023-11-06 Christophe Lyon <christophe.lyon@linaro.org>
-
- * doc/sourcebuild.texi (Other attributes): Document thread_fence
- effective-target.
-
-2023-11-06 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/constraints.md (Bc): Remove constraint.
- (Bn): Rewrite to use x86_extended_reg_mentioned_p predicate.
- * config/i386/i386.cc (ix86_memory_address_reg_class):
- Do not limit processing to TARGET_APX_EGPR. Exit early for
- NULL insn. Do not check recog_data.insn before calling
- extract_insn_cached.
- (ix86_insn_base_reg_class): Handle ADDR_GPR8.
- (ix86_regno_ok_for_insn_base_p): Ditto.
- (ix86_insn_index_reg_class): Ditto.
- * config/i386/i386.md (*cmpqi_ext<mode>_1_mem_rex64):
- Remove insn pattern and corresponding peephole2 pattern.
- (*cmpi_ext<mode>_1): Remove (m,Q) alternative.
- Change (QBc,Q) alternative to (QBn,Q). Add "addr" attribute.
- (*cmpqi_ext<mode>_3_mem_rex64): Remove insn pattern
- and corresponding peephole2 pattern.
- (*cmpi_ext<mode>_3): Remove (Q,m) alternative.
- Change (Q,QnBc) alternative to (Q,QnBn). Add "addr" attribute.
- (*extzvqi_mem_rex64): Remove insn pattern and
- corresponding peephole2 pattern.
- (*extzvqi): Remove (Q,m) alternative. Change (Q,QnBc)
- alternative to (Q,QnBn). Add "addr" attribute.
- (*insvqi_1_mem_rex64): Remove insn pattern and
- corresponding peephole2 pattern.
- (*insvqi_1): Remove (Q,m) alternative. Change (Q,QnBc)
- alternative to (Q,QnBn). Add "addr" attribute.
- (@insv<mode>_1): Ditto.
- (*addqi_ext<mode>_0): Remove (m,0,Q) alternative. Change (QBc,0,Q)
- alternative to (QBn,0,Q). Add "addr" attribute.
- (*subqi_ext<mode>_0): Ditto.
- (*andqi_ext<mode>_0): Ditto.
- (*<any_or:code>qi_ext<mode>_0): Ditto.
- (*addqi_ext<mode>_1): Remove (Q,0,m) alternative. Change (Q,0,QnBc)
- alternative to (Q,0,QnBn). Add "addr" attribute.
- (*andqi_ext<mode>_1): Ditto.
- (*andqi_ext<mode>_1_cc): Ditto.
- (*<any_or:code>qi_ext<mode>_1): Ditto.
- (*xorqi_ext<mode>_1_cc): Ditto.
- * config/i386/predicates.md (nonimm_x64constmem_operand):
- Remove predicate.
- (general_x64constmem_operand): Ditto.
- (norex_memory_operand): Ditto.
-
-2023-11-06 Joseph Myers <joseph@codesourcery.com>
-
- PR c/107954
- * doc/cpp.texi (__STDC_VERSION__): Refer to -std=c23 and
- -std=gnu23 instead of -std=c2x and -std=gnu2x.
- * doc/extend.texi (Attribute Syntax): Refer to C23 and -std=c23
- instead of C2x and -std=c2x.
- * doc/invoke.texi (-Wc11-c23-compat, -std=c23, -std=gnu23)
- (-std=iso9899:2024): Document, with -Wc11-c2x-compat, -std=c2x and
- -std=gnu2x as deprecated aliases. Update descriptions of C23.
- * doc/standards.texi (Standards): Describe C23 with C2X as an old
- name.
-
-2023-11-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * config/nvptx/nvptx.h (MAKE_DECL_ONE_ONLY): Define.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112405
- * tree-vect-stmts.cc (vectorizable_simd_clone_call):
- Properly handle invariant and/or loop mask passing.
-
-2023-11-06 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Remove the size check of lround.
- * config/riscv/riscv-v.cc (expand_vec_lround): Leverage
- emit_vec_rounding_to_integer for round.
-
-2023-11-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/predicates.md: Adapt predicate.
- * config/riscv/riscv-protos.h (can_be_broadcasted_p): New function.
- * config/riscv/riscv-v.cc (can_be_broadcasted_p): Ditto.
- * config/riscv/vector.md (vec_duplicate<mode>): New pattern.
- (*vec_duplicate<mode>): Adapt vec_duplicate insn pattern.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111950
- * tree-vect-loop-manip.cc (slpeel_duplicate_current_defs_from_edges):
- Remove.
- (find_guard_arg): Likewise.
- (slpeel_update_phi_nodes_for_guard2): Likewise.
- (slpeel_tree_duplicate_loop_to_edge_cfg): Remove calls to
- slpeel_duplicate_current_defs_from_edges, do not elide
- LC-PHIs for invariant values.
- (vect_do_peeling): Materialize PHI arguments for the edge
- around the epilog from the PHI defs of the main loop exit.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112404
- * tree-vectorizer.h (get_mask_type_for_scalar_type): Declare
- overload with SLP node argument.
- * tree-vect-stmts.cc (get_mask_type_for_scalar_type): Implement it.
- (vect_check_scalar_mask): Use it.
- * tree-vect-slp.cc (vect_gather_slp_loads): Properly identify
- loads also for nodes with children, like .MASK_LOAD.
- * tree-vect-loop.cc (vect_analyze_loop_2): Look at the
- representative for load nodes and check whether it is a grouped
- access before looking for load-lanes support.
-
-2023-11-06 Robin Dapp <rdapp@ventanamicro.com>
-
- PR tree-optimization/111760
- * config/riscv/autovec.md (vcond_mask_len_<mode><vm>): Add
- expander.
- * config/riscv/riscv-protos.h (enum insn_type): Add.
- * config/riscv/riscv-v.cc (needs_fp_rounding): Add !pred_mov.
- * doc/md.texi: Add vcond_mask_len.
- * gimple-match-exports.cc (maybe_resimplify_conditional_op):
- Create VCOND_MASK_LEN when length masking.
- * gimple-match.h (gimple_match_op::gimple_match_op): Always
- initialize len and bias.
- * internal-fn.cc (vec_cond_mask_len_direct): Add.
- (direct_vec_cond_mask_len_optab_supported_p): Add.
- (internal_fn_len_index): Add VCOND_MASK_LEN.
- (internal_fn_mask_index): Ditto.
- * internal-fn.def (VCOND_MASK_LEN): New internal function.
- * match.pd: Combine unconditional unary, binary and ternary
- operations into the respective COND_LEN operations.
- * optabs.def (OPTAB_D): Add vcond_mask_len optab.
-
-2023-11-06 Richard Sandiford <richard.sandiford@arm.com>
-
- * explow.cc (align_dynamic_address): Do nothing if the required
- alignment is a byte.
-
-2023-11-06 Richard Sandiford <richard.sandiford@arm.com>
-
- * function.h (get_stack_dynamic_offset): Declare.
- * function.cc (get_stack_dynamic_offset): New function,
- split out from...
- (get_stack_dynamic_offset): ...here.
- * explow.cc (allocate_dynamic_stack_space): Handle calls made
- after virtual registers have been instantiated.
-
-2023-11-06 liuhongt <hongtao.liu@intel.com>
-
- PR target/112393
- * config/i386/i386-expand.cc (ix86_expand_vec_perm_vpermt2):
- Avoid generating RTL code when d->testing_p.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112369
- * tree.cc (strip_float_extensions): Use element_precision.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112296
- * doc/extend.texi (__builtin_constant_p): Clarify that
- side-effects are discarded.
-
-2023-11-06 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/111828
- * config.in: Regenerate.
- * config/rs6000/rs6000.cc (rs6000_update_ipa_fn_target_info): Guard
- inline asm handling under !HAVE_AS_POWER10_HTM.
- * configure: Regenerate.
- * configure.ac: Detect assembler support for HTM insns at power10.
-
-2023-11-06 xuli <xuli1@eswincomputing.com>
- Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): New function for the hook.
- (riscv_register_pragmas): Register the hook.
- * config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl.
- * config/riscv/riscv-vector-builtins-bases.cc: New function impl.
- * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Register overloaded function.
- * config/riscv/riscv-vector-builtins.cc (struct non_overloaded_registered_function_hasher):
- New hash table.
- (function_builder::add_function): Add overloaded arg.
- (function_builder::add_unique_function): Map overloaded function to non-overloaded function.
- (function_builder::add_overloaded_function): New API impl.
- (registered_function::overloaded_hash): Calculate hash value.
- (has_vxrm_or_frm_p): New function impl.
- (non_overloaded_registered_function_hasher::hash): Ditto.
- (non_overloaded_registered_function_hasher::equal): Ditto.
- (handle_pragma_vector): Allocate space for hash table.
- (resolve_overloaded_builtin): New function impl.
- * config/riscv/riscv-vector-builtins.h (function_base::may_require_frm_p): Ditto.
- (function_base::may_require_vxrm_p): Ditto.
-
-2023-11-06 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/111889
- * config/i386/avx512bf16intrin.h: Push no-evex512 target.
- * config/i386/avx512bf16vlintrin.h: Ditto.
- * config/i386/avx512bitalgvlintrin.h: Ditto.
- * config/i386/avx512bwintrin.h: Ditto.
- * config/i386/avx512dqintrin.h: Ditto.
- * config/i386/avx512fintrin.h: Ditto.
- * config/i386/avx512fp16intrin.h: Ditto.
- * config/i386/avx512fp16vlintrin.h: Ditto.
- * config/i386/avx512ifmavlintrin.h: Ditto.
- * config/i386/avx512vbmi2vlintrin.h: Ditto.
- * config/i386/avx512vbmivlintrin.h: Ditto.
- * config/i386/avx512vlbwintrin.h: Ditto.
- * config/i386/avx512vldqintrin.h: Ditto.
- * config/i386/avx512vlintrin.h: Ditto.
- * config/i386/avx512vnnivlintrin.h: Ditto.
- * config/i386/avx512vp2intersectvlintrin.h: Ditto.
- * config/i386/avx512vpopcntdqvlintrin.h: Ditto.
-
-2023-11-06 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512bf16vlintrin.h
- (_mm_avx512_castsi128_ps): New.
- (_mm256_avx512_castsi256_ps): Ditto.
- (_mm_avx512_slli_epi32): Ditto.
- (_mm256_avx512_slli_epi32): Ditto.
- (_mm_avx512_cvtepi16_epi32): Ditto.
- (_mm256_avx512_cvtepi16_epi32): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512bwintrin.h
- (_mm_avx512_set_epi32): New.
- (_mm_avx512_set_epi16): Ditto.
- (_mm_avx512_set_epi8): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512fp16intrin.h: Ditto.
- * config/i386/avx512fp16vlintrin.h
- (_mm_avx512_set1_ps): New.
- (_mm256_avx512_set1_ps): Ditto.
- (_mm_avx512_and_si128): Ditto.
- (_mm256_avx512_and_si256): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512vlbwintrin.h
- (_mm_avx512_set1_epi32): New.
- (_mm_avx512_set1_epi16): Ditto.
- (_mm_avx512_set1_epi8): Ditto.
- (_mm256_avx512_set_epi16): Ditto.
- (_mm256_avx512_set_epi8): Ditto.
- (_mm256_avx512_set1_epi16): Ditto.
- (_mm256_avx512_set1_epi32): Ditto.
- (_mm256_avx512_set1_epi8): Ditto.
- (_mm_avx512_max_epi16): Ditto.
- (_mm_avx512_min_epi16): Ditto.
- (_mm_avx512_max_epu16): Ditto.
- (_mm_avx512_min_epu16): Ditto.
- (_mm_avx512_max_epi8): Ditto.
- (_mm_avx512_min_epi8): Ditto.
- (_mm_avx512_max_epu8): Ditto.
- (_mm_avx512_min_epu8): Ditto.
- (_mm256_avx512_max_epi16): Ditto.
- (_mm256_avx512_min_epi16): Ditto.
- (_mm256_avx512_max_epu16): Ditto.
- (_mm256_avx512_min_epu16): Ditto.
- (_mm256_avx512_insertf128_ps): Ditto.
- (_mm256_avx512_extractf128_pd): Ditto.
- (_mm256_avx512_extracti128_si256): Ditto.
- (_MM256_AVX512_REDUCE_OPERATOR_BASIC_EPI16): Ditto.
- (_MM256_AVX512_REDUCE_OPERATOR_MAX_MIN_EP16): Ditto.
- (_MM256_AVX512_REDUCE_OPERATOR_BASIC_EPI8): Ditto.
- (_MM256_AVX512_REDUCE_OPERATOR_MAX_MIN_EP8): Ditto.
- (__attribute__): Change intrin call.
-
-2023-11-06 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512bf16vlintrin.h: Change intrin call.
- * config/i386/avx512fintrin.h
- (_mm_avx512_undefined_ps): New.
- (_mm_avx512_undefined_pd): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512vbmivlintrin.h: Ditto.
- * config/i386/avx512vlbwintrin.h: Ditto.
- * config/i386/avx512vldqintrin.h: Ditto.
- * config/i386/avx512vlintrin.h
- (_mm_avx512_undefined_si128): New.
- (_mm256_avx512_undefined_ps): Ditto.
- (_mm256_avx512_undefined_pd): Ditto.
- (_mm256_avx512_undefined_si256): Ditto.
- (__attribute__): Change intrin call.
-
-2023-11-06 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512bitalgvlintrin.h: Change intrin call.
- * config/i386/avx512dqintrin.h: Ditto.
- * config/i386/avx512fintrin.h:
- (_mm_avx512_setzero_ps): New.
- (_mm_avx512_setzero_pd): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512fp16intrin.h: Ditto.
- * config/i386/avx512fp16vlintrin.h: Ditto.
- * config/i386/avx512vbmi2vlintrin.h: Ditto.
- * config/i386/avx512vbmivlintrin.h: Ditto.
- * config/i386/avx512vlbwintrin.h: Ditto.
- * config/i386/avx512vldqintrin.h: Ditto.
- * config/i386/avx512vlintrin.h
- (_mm_avx512_setzero_si128): New.
- (_mm256_avx512_setzero_pd): Ditto.
- (_mm256_avx512_setzero_ps): Ditto.
- (_mm256_avx512_setzero_si256): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512vpopcntdqvlintrin.h: Ditto.
- * config/i386/gfniintrin.h: Ditto.
-
-2023-11-05 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.h (enum reg_class): Add LEGACY_INDEX_REGS.
- Rename LEGACY_REGS to LEGACY_GENERAL_REGS.
- (REG_CLASS_NAMES): Ditto.
- (REG_CLASS_CONTENTS): Ditto.
- * config/i386/constraints.md ("R"): Update for rename.
-
-2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc: Remove unused forward references.
- (seginfo): Remove bbnum.
- (new_seginfo): Remove associated argument.
- (optimize_mode_switching): Update calls accordingly.
-
-2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * read-rtl.cc (read_rtx_operand): Avoid spinning endlessly for
- invalid [...] operands.
-
-2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/112105
- * config/aarch64/aarch64.cc (aarch64_modes_compatible_p): New
- function, with the core logic extracted from...
- (aarch64_can_change_mode_class): ...here. Extend the previous rules
- to allow changes between partial SVE modes and other modes if
- the other mode is no bigger than an element, and if no other rule
- prevents it. Use the aarch64_modes_tieable_p handling of
- partial Advanced SIMD structure modes.
- (aarch64_modes_tieable_p): Use aarch64_modes_compatible_p.
- Allow all vector mode ties that it allows.
-
-2023-11-05 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Remove the size check of lrint.
- * config/riscv/riscv-v.cc (emit_vec_narrow_cvt_x_f): New help
- emit func impl.
- (emit_vec_widden_cvt_x_f): New help emit func impl.
- (emit_vec_rounding_to_integer): New func impl to emit the
- rounding from FP to integer.
- (expand_vec_lrint): Leverage emit_vec_rounding_to_integer.
- * config/riscv/vector.md: Take V_VLSF for vfncvt.
-
-2023-11-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix bug.
-
-2023-11-04 Sergei Trofimovich <siarheit@google.com>
-
- PR bootstrap/112379
- * gcc-urlifier.cc (get_url_suffix_for_quoted_text): Mark as
- ATTRIBUTE_UNUSED.
-
-2023-11-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector-iterators.md: Remove HF modes.
-
-2023-11-04 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc: Include "pretty-print-urlifier.h".
- (diagnostic_context::initialize): Initialize m_urlifier.
- (diagnostic_context::finish): Clean up m_urlifier
- (diagnostic_report::diagnostic): m_urlifier to pp_format.
- * diagnostic.h (diagnostic_context::m_urlifier): New field.
- * gcc-urlifier.cc: New file.
- * gcc-urlifier.def: New file.
- * gcc-urlifier.h: New file.
- * gcc.cc: Include "gcc-urlifier.h".
- (driver::global_initializations): Initialize global_dc->m_urlifier.
- * pretty-print-urlifier.h: New file.
- * pretty-print.cc: Include "pretty-print-urlifier.h".
- (obstack_append_string): New.
- (urlify_quoted_string): New.
- (pp_format): Add "urlifier" param and use it to implement optional
- urlification of quoted text strings.
- (pp_output_formatted_text): Make buffer a const pointer.
- (selftest::pp_printf_with_urlifier): New.
- (selftest::test_urlification): New.
- (selftest::pretty_print_cc_tests): Call it.
- * pretty-print.h (class urlifier): New forward declaration.
- (pp_format): Add optional urlifier param.
- * selftest-run-tests.cc (selftest::run_tests): Call
- selftest::gcc_urlifier_cc_tests .
- * selftest.h (selftest::gcc_urlifier_cc_tests): New decl.
- * toplev.cc: Include "gcc-urlifier.h".
- (general_init): Initialize global_dc->m_urlifier.
-
-2023-11-04 David Malcolm <dmalcolm@redhat.com>
-
- * Makefile.in (GCC_OBJS): Add gcc-urlifier.o.
- (OBJS): Likewise.
-
-2023-11-04 David Malcolm <dmalcolm@redhat.com>
-
- * common.opt (fdiagnostics-text-art-charset=): Remove refererence
- to diagnostic-text-art.h.
- * coretypes.h (struct diagnostic_context): Replace forward decl
- with...
- (class diagnostic_context): ...this.
- * diagnostic-format-json.cc: Update for changes to
- diagnostic_context.
- * diagnostic-format-sarif.cc: Likewise.
- * diagnostic-show-locus.cc: Likewise.
- * diagnostic-text-art.h: Deleted file, moving content...
- (enum diagnostic_text_art_charset): ...to diagnostic.h,
- (DIAGNOSTICS_TEXT_ART_CHARSET_DEFAULT): ...deleting,
- (diagnostics_text_art_charset_init): ...deleting in favor of
- diagnostic_context::set_text_art_charset.
- * diagnostic.cc: Remove include of "diagnostic-text-art.h".
- (pedantic_warning_kind): Update for field renaming.
- (permissive_error_kind): Likewise.
- (permissive_error_option): Likewise.
- (diagnostic_initialize): Convert to...
- (diagnostic_context::initialize): ...this, updating for field
- renamings.
- (diagnostic_color_init): Convert to...
- (diagnostic_context::color_init): ...this.
- (diagnostic_urls_init): Convert to...
- (diagnostic_context::urls_init): ...this.
- (diagnostic_initialize_input_context): Convert to...
- (diagnostic_context::initialize_input_context): ...this.
- (diagnostic_finish): Convert to...
- (diagnostic_context::finish): ...this, updating for field
- renamings.
- (diagnostic_context::set_output_format): New.
- (diagnostic_context::set_client_data_hooks): New.
- (diagnostic_context::create_edit_context): New.
- (diagnostic_converted_column): Convert to...
- (diagnostic_context::converted_column): ...this.
- (diagnostic_get_location_text): Update for field renaming.
- (diagnostic_check_max_errors): Convert to...
- (diagnostic_context::check_max_errors): ...this, updating for
- field renamings.
- (diagnostic_action_after_output): Convert to...
- (diagnostic_context::action_after_output): ...this, updating for
- field renamings.
- (last_module_changed_p): Delete.
- (set_last_module): Delete.
- (includes_seen): Convert to...
- (diagnostic_context::includes_seen_p): ...this, updating for field
- renamings.
- (diagnostic_report_current_module): Convert to...
- (diagnostic_context::report_current_module): ...this, updating for
- field renamings, and replacing uses of last_module_changed_p and
- set_last_module to simple field accesses.
- (diagnostic_show_any_path): Convert to...
- (diagnostic_context::show_any_path): ...this.
- (diagnostic_classify_diagnostic): Convert to...
- (diagnostic_context::classify_diagnostic): ...this, updating for
- field renamings.
- (diagnostic_push_diagnostics): Convert to...
- (diagnostic_context::push_diagnostics): ...this, updating for field
- renamings.
- (diagnostic_pop_diagnostics): Convert to...
- (diagnostic_context::pop_diagnostics): ...this, updating for field
- renamings.
- (get_any_inlining_info): Convert to...
- (diagnostic_context::get_any_inlining_info): ...this, updating for
- field renamings.
- (update_effective_level_from_pragmas): Convert to...
- (diagnostic_context::update_effective_level_from_pragmas):
- ...this, updating for field renamings.
- (print_any_cwe): Convert to...
- (diagnostic_context::print_any_cwe): ...this.
- (print_any_rules): Convert to...
- (diagnostic_context::print_any_rules): ...this.
- (print_option_information): Convert to...
- (diagnostic_context::print_option_information): ...this, updating
- for field renamings.
- (diagnostic_enabled): Convert to...
- (diagnostic_context::diagnostic_enabled): ...this, updating for
- field renamings.
- (warning_enabled_at): Convert to...
- (diagnostic_context::warning_enabled_at): ...this.
- (diagnostic_report_diagnostic): Convert to...
- (diagnostic_context::report_diagnostic): ...this, updating for
- field renamings and conversions to member functions.
- (diagnostic_append_note): Update for field renaming.
- (diagnostic_impl): Use diagnostic_context::report_diagnostic
- directly.
- (diagnostic_n_impl): Likewise.
- (diagnostic_emit_diagram): Convert to...
- (diagnostic_context::emit_diagram): ...this, updating for field
- renamings.
- (error_recursion): Convert to...
- (diagnostic_context::error_recursion): ...this.
- (diagnostic_text_output_format::~diagnostic_text_output_format):
- Use accessor.
- (diagnostics_text_art_charset_init): Convert to...
- (diagnostic_context::set_text_art_charset): ...this.
- (assert_location_text): Update for field renamings.
- * diagnostic.h (enum diagnostic_text_art_charset): Move here from
- diagnostic-text-art.h.
- (struct diagnostic_context): Convert to...
- (class diagnostic_context): ...this.
- (diagnostic_context::ice_handler_callback_t): New typedef.
- (diagnostic_context::set_locations_callback_t): New typedef.
- (diagnostic_context::initialize): New decl.
- (diagnostic_context::color_init): New decl.
- (diagnostic_context::urls_init): New decl.
- (diagnostic_context::file_cache_init): New decl.
- (diagnostic_context::finish): New decl.
- (diagnostic_context::set_set_locations_callback): New.
- (diagnostic_context::initialize_input_context): New decl.
- (diagnostic_context::warning_enabled_at): New decl.
- (diagnostic_context::option_unspecified_p): New.
- (diagnostic_context::report_diagnostic): New decl.
- (diagnostic_context::report_current_module): New decl.
- (diagnostic_context::check_max_errors): New decl.
- (diagnostic_context::action_after_output): New decl.
- (diagnostic_context::classify_diagnostic): New decl.
- (diagnostic_context::push_diagnostics): New decl.
- (diagnostic_context::pop_diagnostics): New decl.
- (diagnostic_context::emit_diagram): New decl.
- (diagnostic_context::set_output_format): New decl.
- (diagnostic_context::set_text_art_charset): New decl.
- (diagnostic_context::set_client_data_hooks): New decl.
- (diagnostic_context::create_edit_context): New decl.
- (diagnostic_context::set_warning_as_error_requested): New.
- (diagnostic_context::set_report_bug): New.
- (diagnostic_context::set_extra_output_kind): New.
- (diagnostic_context::set_show_cwe): New.
- (diagnostic_context::set_show_rules): New.
- (diagnostic_context::set_path_format): New.
- (diagnostic_context::set_show_path_depths): New.
- (diagnostic_context::set_show_option_requested): New.
- (diagnostic_context::set_max_errors): New.
- (diagnostic_context::set_escape_format): New.
- (diagnostic_context::set_ice_handler_callback): New.
- (diagnostic_context::warning_as_error_requested_p): New.
- (diagnostic_context::show_path_depths_p): New.
- (diagnostic_context::get_path_format): New.
- (diagnostic_context::get_escape_format): New.
- (diagnostic_context::get_file_cache): New.
- (diagnostic_context::get_edit_context): New.
- (diagnostic_context::get_client_data_hooks): New.
- (diagnostic_context::get_diagram_theme): New.
- (diagnostic_context::converted_column): New decl.
- (diagnostic_context::diagnostic_count): New.
- (diagnostic_context::includes_seen_p): New decl.
- (diagnostic_context::print_any_cwe): New decl.
- (diagnostic_context::print_any_rules): New decl.
- (diagnostic_context::print_option_information): New decl.
- (diagnostic_context::show_any_path): New decl.
- (diagnostic_context::error_recursion): New decl.
- (diagnostic_context::diagnostic_enabled): New decl.
- (diagnostic_context::get_any_inlining_info): New decl.
- (diagnostic_context::update_effective_level_from_pragmas): New
- decl.
- (diagnostic_context::m_file_cache): Make private.
- (diagnostic_context::diagnostic_count): Rename to...
- (diagnostic_context::m_diagnostic_count): ...this and make
- private.
- (diagnostic_context::warning_as_error_requested): Rename to...
- (diagnostic_context::m_warning_as_error_requested): ...this and
- make private.
- (diagnostic_context::n_opts): Rename to...
- (diagnostic_context::m_n_opts): ...this and make private.
- (diagnostic_context::classify_diagnostic): Rename to...
- (diagnostic_context::m_classify_diagnostic): ...this and make
- private.
- (diagnostic_context::classification_history): Rename to...
- (diagnostic_context::m_classification_history): ...this and make
- private.
- (diagnostic_context::n_classification_history): Rename to...
- (diagnostic_context::m_n_classification_history): ...this and make
- private.
- (diagnostic_context::push_list): Rename to...
- (diagnostic_context::m_push_list): ...this and make private.
- (diagnostic_context::n_push): Rename to...
- (diagnostic_context::m_n_push): ...this and make private.
- (diagnostic_context::show_cwe): Rename to...
- (diagnostic_context::m_show_cwe): ...this and make private.
- (diagnostic_context::show_rules): Rename to...
- (diagnostic_context::m_show_rules): ...this and make private.
- (diagnostic_context::path_format): Rename to...
- (diagnostic_context::m_path_format): ...this and make private.
- (diagnostic_context::show_path_depths): Rename to...
- (diagnostic_context::m_show_path_depths): ...this and make
- private.
- (diagnostic_context::show_option_requested): Rename to...
- (diagnostic_context::m_show_option_requested): ...this and make
- private.
- (diagnostic_context::abort_on_error): Rename to...
- (diagnostic_context::m_abort_on_error): ...this.
- (diagnostic_context::show_column): Rename to...
- (diagnostic_context::m_show_column): ...this.
- (diagnostic_context::pedantic_errors): Rename to...
- (diagnostic_context::m_pedantic_errors): ...this.
- (diagnostic_context::permissive): Rename to...
- (diagnostic_context::m_permissive): ...this.
- (diagnostic_context::opt_permissive): Rename to...
- (diagnostic_context::m_opt_permissive): ...this.
- (diagnostic_context::fatal_errors): Rename to...
- (diagnostic_context::m_fatal_errors): ...this.
- (diagnostic_context::dc_inhibit_warnings): Rename to...
- (diagnostic_context::m_inhibit_warnings): ...this.
- (diagnostic_context::dc_warn_system_headers): Rename to...
- (diagnostic_context::m_warn_system_headers): ...this.
- (diagnostic_context::max_errors): Rename to...
- (diagnostic_context::m_max_errors): ...this and make private.
- (diagnostic_context::internal_error): Rename to...
- (diagnostic_context::m_internal_error): ...this.
- (diagnostic_context::option_enabled): Rename to...
- (diagnostic_context::m_option_enabled): ...this.
- (diagnostic_context::option_state): Rename to...
- (diagnostic_context::m_option_state): ...this.
- (diagnostic_context::option_name): Rename to...
- (diagnostic_context::m_option_name): ...this.
- (diagnostic_context::get_option_url): Rename to...
- (diagnostic_context::m_get_option_url): ...this.
- (diagnostic_context::print_path): Rename to...
- (diagnostic_context::m_print_path): ...this.
- (diagnostic_context::make_json_for_path): Rename to...
- (diagnostic_context::m_make_json_for_path): ...this.
- (diagnostic_context::x_data): Rename to...
- (diagnostic_context::m_client_aux_data): ...this.
- (diagnostic_context::last_location): Rename to...
- (diagnostic_context::m_last_location): ...this.
- (diagnostic_context::last_module): Rename to...
- (diagnostic_context::m_last_module): ...this and make private.
- (diagnostic_context::lock): Rename to...
- (diagnostic_context::m_lock): ...this and make private.
- (diagnostic_context::lang_mask): Rename to...
- (diagnostic_context::m_lang_mask): ...this.
- (diagnostic_context::inhibit_notes_p): Rename to...
- (diagnostic_context::m_inhibit_notes_p): ...this.
- (diagnostic_context::report_bug): Rename to...
- (diagnostic_context::m_report_bug): ...this and make private.
- (diagnostic_context::extra_output_kind): Rename to...
- (diagnostic_context::m_extra_output_kind): ...this and make
- private.
- (diagnostic_context::column_unit): Rename to...
- (diagnostic_context::m_column_unit): ...this and make private.
- (diagnostic_context::column_origin): Rename to...
- (diagnostic_context::m_column_origin): ...this and make private.
- (diagnostic_context::tabstop): Rename to...
- (diagnostic_context::m_tabstop): ...this and make private.
- (diagnostic_context::escape_format): Rename to...
- (diagnostic_context::m_escape_format): ...this and make private.
- (diagnostic_context::edit_context_ptr): Rename to...
- (diagnostic_context::m_edit_context_ptr): ...this and make
- private.
- (diagnostic_context::set_locations_cb): Rename to...
- (diagnostic_context::m_set_locations_cb): ...this and make
- private.
- (diagnostic_context::ice_handler_cb): Rename to...
- (diagnostic_context::m_ice_handler_cb): ...this and make private.
- (diagnostic_context::includes_seen): Rename to...
- (diagnostic_context::m_includes_seen): ...this and make private.
- (diagnostic_inhibit_notes): Update for field renaming.
- (diagnostic_context_auxiliary_data): Likewise.
- (diagnostic_abort_on_error): Convert from macro to inline function
- and update for field renaming.
- (diagnostic_kind_count): Convert from macro to inline function and
- use diagnostic_count accessor.
- (diagnostic_report_warnings_p): Update for field renaming.
- (diagnostic_initialize): Convert decl to inline function calling
- into diagnostic_context.
- (diagnostic_color_init): Likewise.
- (diagnostic_urls_init): Likewise.
- (diagnostic_urls_init): Likewise.
- (diagnostic_finish): Likewise.
- (diagnostic_report_current_module): Likewise.
- (diagnostic_show_any_path): Delete decl.
- (diagnostic_initialize_input_context): Convert decl to inline
- function calling into diagnostic_context.
- (diagnostic_classify_diagnostic): Likewise.
- (diagnostic_push_diagnostics): Likewise.
- (diagnostic_pop_diagnostics): Likewise.
- (diagnostic_report_diagnostic): Likewise.
- (diagnostic_action_after_output): Likewise.
- (diagnostic_check_max_errors): Likewise.
- (diagnostic_file_cache_fini): Delete decl.
- (diagnostic_converted_column): Delete decl.
- (warning_enabled_at): Convert decl to inline function calling into
- diagnostic_context.
- (option_unspecified_p): New.
- (diagnostic_emit_diagram): Delete decl.
- * gcc.cc: Remove include of "diagnostic-text-art.h".
- Update for changes to diagnostic_context.
- * input.cc (diagnostic_file_cache_init): Move implementation
- to...
- (diagnostic_context::file_cache_init): ...this new member
- function.
- (diagnostic_file_cache_fini): Delete.
- (diagnostics_file_cache_forcibly_evict_file): Update for
- m_file_cache becoming private.
- (location_get_source_line): Likewise.
- (get_source_file_content): Likewise.
- (location_missing_trailing_newline): Likewise.
- * input.h (diagnostics_file_cache_fini): Delete.
- * langhooks.cc: Update for changes to diagnostic_context.
- * lto-wrapper.cc: Likewise.
- * opts.cc: Remove include of "diagnostic-text-art.h".
- Update for changes to diagnostic_context.
- * selftest-diagnostic.cc: Update for changes to
- diagnostic_context.
- * toplev.cc: Likewise.
- * tree-diagnostic-path.cc: Likewise.
- * tree-diagnostic.cc: Likewise.
-
-2023-11-03 Martin Uecker <uecker@tugraz.at>
-
- PR c/98541
- * gimple-ssa-warn-access.cc
- (pass_waccess::maybe_check_access_sizes): For VLA bounds
- in parameters, only warn about null pointers with 'static'.
-
-2023-11-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Allow unmasked
- calls to use masked simdclones.
-
-2023-11-03 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_initialize): Update for consolidation
- of group-based fields.
- (diagnostic_report_diagnostic): Likewise.
- (diagnostic_context::begin_group): New, based on body of
- auto_diagnostic_group's ctor.
- (diagnostic_context::end_group): New, based on body of
- auto_diagnostic_group's dtor.
- (auto_diagnostic_group::auto_diagnostic_group): Convert to a call
- to begin_group.
- (auto_diagnostic_group::~auto_diagnostic_group): Convert to a call
- to end_group.
- * diagnostic.h (diagnostic_context::begin_group): New decl.
- (diagnostic_context::end_group): New decl.
- (diagnostic_context::diagnostic_group_nesting_depth): Rename to...
- (diagnostic_context::m_diagnostic_groups.m_nesting_depth):
- ...this.
- (diagnostic_context::diagnostic_group_emission_count): Rename
- to...
- (diagnostic_context::m_diagnostic_groups::m_emission_count):
- ...this.
-
-2023-11-03 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/111766
- * range-op.cc (operator_equal::fold_range): Check constants
- against the bitmask.
- (operator_not_equal::fold_range): Ditto.
- * value-range.h (irange_bitmask::member_p): New.
-
-2023-11-03 Andrew MacLeod <amacleod@redhat.com>
-
- * value-range.cc (irange_bitmask::adjust_range): New.
- (irange::intersect_bitmask): Call adjust_range.
- * value-range.h (irange_bitmask::adjust_range): New prototype.
-
-2023-11-03 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
- Rename to ...
- (ix86_memory_address_reg_class): ... this. Generalize address
- register class handling to allow multiple address register classes.
- Return maximal class for unrecognized instructions. Improve comments.
- (ix86_insn_base_reg_class): Rewrite to handle
- multiple address register classes.
- (ix86_regno_ok_for_insn_base_p): Ditto.
- (ix86_insn_index_reg_class): Ditto.
- * config/i386/i386.md: Rename "gpr32" attribute to "addr"
- and substitute its values with "0" -> "gpr16", "1" -> "*".
- (addr): New attribute to limit allowed address register set.
- (gpr32): Remove.
- * config/i386/mmx.md: Rename "gpr32" attribute to "addr"
- and substitute its values with "0" -> "gpr16", "1" -> "*".
- * config/i386/sse.md: Ditto.
-
-2023-11-03 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (vectorizable_live_operation): Simplify
- LC PHI replacement.
-
-2023-11-03 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md (addsi3): Fix GNU-style code formatting.
- (adddi3): Change define_expand to generate a *adddi3.
- (*adddi3): New define_insn_and_split to lower DImode additions
- during the split1 pass (after combine and before reload).
- (ashldi3): New define_expand to (only) generate *ashldi3_cnt1
- for DImode left shifts by a single bit.
- (*ashldi3_cnt1): New define_insn_and_split to lower DImode
- left shifts by one bit to an *adddi3.
-
-2023-11-03 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.md (*cmov_uxtw_insn_insv): Remove
- can_create_pseudo_p condition.
-
-2023-11-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-slp.cc (vect_get_and_check_slp_defs): Support SLP for dummy mask -1.
- * tree-vect-stmts.cc (vectorizable_load): Ditto.
-
-2023-11-03 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112366
- * tree-vect-loop.cc (vectorizable_live_operation): Remove
- assert.
-
-2023-11-03 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112310
- * tree-ssa-pre.cc (do_hoist_insertion): Keep the union
- of expressions, validate dependences are contained within
- the hoistable set before hoisting.
-
-2023-11-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
- (lround<mode><v_i_l_ll_convert>2): Ditto.
- (lceil<mode><v_i_l_ll_convert>2): Ditto.
- (lfloor<mode><v_i_l_ll_convert>2): Ditto.
- (lrint<mode><v_f2si_convert>2): New pattern for cvt from
- FP to SI.
- (lround<mode><v_f2si_convert>2): Ditto.
- (lceil<mode><v_f2si_convert>2): Ditto.
- (lfloor<mode><v_f2si_convert>2): Ditto.
- (lrint<mode><v_f2di_convert>2): New pattern for cvt from
- FP to DI.
- (lround<mode><v_f2di_convert>2): Ditto.
- (lceil<mode><v_f2di_convert>2): Ditto.
- (lfloor<mode><v_f2di_convert>2): Ditto.
- * config/riscv/vector-iterators.md: Renew iterators for both
- the SI and DI.
-
-2023-11-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112326
- * config/riscv/riscv-avlprop.cc (get_insn_vtype_mode): New function.
- (simplify_replace_vlmax_avl): Ditto.
- (pass_avlprop::execute): Add immediate AVL simplification.
- * config/riscv/riscv-protos.h (imm_avl_p): Rename.
- * config/riscv/riscv-v.cc (const_vlmax_p): Ditto.
- (imm_avl_p): Ditto.
- (emit_vlmax_insn): Adapt for new interface name.
- * config/riscv/vector.md (mode_idx): New attribute.
-
-2023-11-03 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-11-02 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
- (lround<mode><v_i_l_ll_convert>2): Ditto.
- (lceil<mode><v_i_l_ll_convert>2): Ditto.
- (lfloor<mode><v_i_l_ll_convert>2): Ditto.
- (lrint<mode><v_f2si_convert>2): New pattern for cvt from
- FP to SI.
- (lround<mode><v_f2si_convert>2): Ditto.
- (lceil<mode><v_f2si_convert>2): Ditto.
- (lfloor<mode><v_f2si_convert>2): Ditto.
- (lrint<mode><v_f2di_convert>2): New pattern for cvt from
- FP to DI.
- (lround<mode><v_f2di_convert>2): Ditto.
- (lceil<mode><v_f2di_convert>2): Ditto.
- (lfloor<mode><v_f2di_convert>2): Ditto.
- * config/riscv/vector-iterators.md: Renew iterators for both
- the SI and DI.
-
-2023-11-02 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled assert
-
-2023-11-02 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/combiner.md: Add new patterns for single bit
- sign extractions.
-
-2023-11-02 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
- (lround<mode><v_i_l_ll_convert>2): Ditto.
- (lceil<mode><v_i_l_ll_convert>2): Ditto.
- (lfloor<mode><v_i_l_ll_convert>2): Ditto.
- (lrint<mode><v_f2si_convert>2): New pattern for cvt from
- FP to SI.
- (lround<mode><v_f2si_convert>2): Ditto.
- (lceil<mode><v_f2si_convert>2): Ditto.
- (lfloor<mode><v_f2si_convert>2): Ditto.
- (lrint<mode><v_f2di_convert>2): New pattern for cvt from
- FP to DI.
- (lround<mode><v_f2di_convert>2): Ditto.
- (lceil<mode><v_f2di_convert>2): Ditto.
- (lfloor<mode><v_f2di_convert>2): Ditto.
- * config/riscv/vector-iterators.md: Renew iterators for both
- the SI and DI.
-
-2023-11-02 Sam James <sam@gentoo.org>
-
- * doc/passes.texi (Dead code elimination): Explicitly say 'lifetime'
- as this has become the standard term for what we're doing here.
-
-2023-11-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-avlprop.cc
- (pass_avlprop::get_vlmax_ta_preferred_avl): Don't allow
- non-real insn AVL propation.
-
-2023-11-02 Robin Dapp <rdapp@ventanamicro.com>
-
- PR middle-end/111401
- * internal-fn.cc (internal_fn_else_index): New function.
- * internal-fn.h (internal_fn_else_index): Define.
- * tree-if-conv.cc (convert_scalar_cond_reduction): Emit COND_OP
- if supported.
- (predicate_scalar_phi): Add whitespace.
- * tree-vect-loop.cc (fold_left_reduction_fn): Add IFN_COND_OP.
- (neutral_op_for_reduction): Return -0 for PLUS.
- (check_reduction_path): Don't count else operand in COND_OP.
- (vect_is_simple_reduction): Ditto.
- (vect_create_epilog_for_reduction): Fix whitespace.
- (vectorize_fold_left_reduction): Add COND_OP handling.
- (vectorizable_reduction): Don't count else operand in COND_OP.
- (vect_transform_reduction): Add COND_OP handling.
- * tree-vectorizer.h (neutral_op_for_reduction): Add default
- parameter.
-
-2023-11-02 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112320
- * gimple-fold.h (rewrite_to_defined_overflow): New overload
- for in-place operation.
- * gimple-fold.cc (rewrite_to_defined_overflow): Add stmt
- iterator argument to worker, define separate API for
- in-place and not in-place operation.
- * tree-if-conv.cc (predicate_statements): Simplify.
- * tree-scalar-evolution.cc (final_value_replacement_loop):
- Likewise.
- * tree-ssa-ifcombine.cc (pass_tree_ifcombine::execute): Adjust.
- * tree-ssa-reassoc.cc (update_range_test): Likewise.
-
-2023-11-02 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md: Move stack protector patterns
- above mov $0,%reg -> xor %reg,%reg peephole2 pattern.
-
-2023-11-02 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/mmx.md (cmlav4hf4): New expander.
- (cmla_conjv4hf4): Ditto.
- (cmulv4hf3): Ditto.
- (cmul_conjv4hf3): Ditto.
-
-2023-11-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix redundant codes in attributes.
-
-2023-11-02 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Expand non-tuple intrinsics.
- * config/riscv/riscv-vector-builtins-functions.def (vcreate): Define non-tuple intrinsics.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def): Ditto.
- * config/riscv/riscv-vector-builtins.cc: Add arg types.
-
-2023-11-02 Pan Li <pan2.li@intel.com>
-
- * tree-vect-stmts.cc (vectorizable_internal_function): Add type
- size check for vectype_out doesn't participating for optab query.
- (vectorizable_call): Remove the type size check.
-
-2023-11-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112327
- * config/riscv/vector.md: Add '0'.
-
-2023-11-01 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110551
- * config/i386/i386.md (*bmi2_umul<mode><dwi>3_1): Tidy condition
- as operands[2] with predicate register_operand must be !MEM_P.
- (peephole2): Optimize a mulx followed by a register-to-register
- move, to place result in the correct destination if possible.
-
-2023-11-01 Patrick O'Neill <patrick@rivosinc.com>
-
- * config/riscv/sync.md: Use riscv_subword_address function to
- calculate the address and shift in atomic_test_and_set.
-
-2023-11-01 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_promote_function_mode): Fix mode
- returned for libcall case.
-
-2023-11-01 Martin Uecker <uecker@tugraz.at>
-
- PR c/71219
- * doc/invoke.texi: Document -Walloc-size option.
-
-2023-11-01 Edwin Lu <ewlu@rivosinc.com>
-
- * genautomata.cc (write_automata): move endif
-
-2023-11-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * omp-simd-clone.cc (simd_clone_adjust_return_type): Hoist out code to
- create return array and don't return new type.
- (simd_clone_adjust_argument_types): Hoist out code that creates
- ipa_param_body_adjustments and don't return them.
- (simd_clone_adjust): Call TARGET_SIMD_CLONE_ADJUST after return and
- argument types have been vectorized, create adjustments and return array
- after the hook.
- (expand_simd_clones): Call TARGET_SIMD_CLONE_ADJUST after return and
- argument types have been vectorized.
-
-2023-11-01 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112332
- * config/i386/i386.md (stack_protexct_set_2 peephole2):
- Use general_gr_operand as operand 4 predicate.
-
-2023-11-01 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (stack_protect_set): Explicitly
- generate scratch register in word mode.
- (@stack_protect_set_1_<mode>): Rename to ...
- (@stack_protect_set_1_<PTR:mode>_<SWI48:mode>): ... this.
- Use SWI48 mode iterator to match scratch register.
- (stack_protexct_set_1 peephole2): Use PTR, W and SWI48 mode
- iterators to match peephole sequence. Use general_operand
- predicate for operand 4. Allow different operand 2 and operand 3
- registers and use peep2_reg_dead_p to ensure new scratch
- register is dead before peephole seqeunce. Use peep2_reg_dead_p
- to ensure old scratch register is dead after peephole sequence.
- (*stack_protect_set_2_<mode>): Rename to ...
- (*stack_protect_set_2_<mode>_si): .. this.
- (*stack_protect_set_3): Rename to ...
- (*stack_protect_set_2_<mode>_di): ... this.
- Use PTR mode iterator to match stack protector memory move.
- Use earlyclobber for all alternatives of operand 1.
- (stack_protexct_set_2 peephole2): Use PTR, W and SWI48 mode
- iterators to match peephole sequence. Use general_operand
- predicate for operand 4. Allow different operand 2 and operand 3
- registers and use peep2_reg_dead_p to ensure new scratch
- register is dead before peephole seqeunce. Use peep2_reg_dead_p
- to ensure old scratch register is dead after peephole sequence.
-
-2023-11-01 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-functions.def (vundefined): Add vundefine
- intrinsics for tuple types.
- * config/riscv/riscv-vector-builtins.cc: Ditto.
- * config/riscv/vector.md (@vundefined<mode>): Ditto.
-
-2023-11-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-slp.cc (vect_build_slp_tree_1): Fix whitespace.
-
-2023-10-31 David Malcolm <dmalcolm@redhat.com>
-
- * Makefile.in (ANALYZER_OBJS): Add analyzer/record-layout.o.
-
-2023-10-31 David Malcolm <dmalcolm@redhat.com>
-
- * input.cc (dump_location_info): Update for removal of
- MACRO_MAP_EXPANSION_POINT_LOCATION.
- * tree-diagnostic.cc (maybe_unwind_expanded_macro_loc):
- Likewise.
-
-2023-10-31 David Malcolm <dmalcolm@redhat.com>
-
- * opts.cc (get_option_url): Update comment; the requirement to
- pass DOCUMENTATION_ROOT_URL's value via -D was removed in
- r10-8065-ge33a1eae25b8a8.
-
-2023-10-31 David Malcolm <dmalcolm@redhat.com>
-
- * pretty-print.cc (pretty_printer::pretty_printer): Initialize
- m_skipping_null_url.
- (pp_begin_url): Handle URL being null.
- (pp_end_url): Likewise.
- (selftest::test_null_urls): New.
- (selftest::pretty_print_cc_tests): Call it.
- * pretty-print.h (pretty_printer::m_skipping_null_url): New.
-
-2023-10-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-slp.cc (vect_get_operand_map): Add MASK_LEN_GATHER_LOAD.
- (vect_build_slp_tree_1): Ditto.
- (vect_build_slp_tree_2): Ditto.
-
-2023-10-31 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf-passes.def (pass_lower_bpf_core): Added pass.
- * config/bpf/bpf-protos.h: Added prototype for new pass.
- * config/bpf/bpf.cc (bpf_delegitimize_address): New function.
- * config/bpf/bpf.md (mov_reloc_core<MM:mode>): Prefixed
- name with '*'.
- * config/bpf/core-builtins.cc (cr_builtins) Added access_node to
- struct.
- (is_attr_preserve_access): Improved check.
- (core_field_info): Make use of root_for_core_field_info
- function.
- (process_field_expr): Adapted to new functions.
- (pack_type): Small improvement.
- (bpf_handle_plugin_finish_type): Adapted to GTY(()).
- (bpf_init_core_builtins): Changed to new function names.
- (construct_builtin_core_reloc): Improved implementation.
- (bpf_resolve_overloaded_core_builtin): Changed how
- __builtin_preserve_access_index is converted.
- (compute_field_expr): Corrected implementation. Added
- access_node argument.
- (bpf_core_get_index): Added valid argument.
- (root_for_core_field_info, pack_field_expr)
- (core_expr_with_field_expr_plus_base, make_core_safe_access_index)
- (replace_core_access_index_comp_expr, maybe_get_base_for_field_expr)
- (core_access_clean, core_is_access_index, core_mark_as_access_index)
- (make_gimple_core_safe_access_index, execute_lower_bpf_core)
- (make_pass_lower_bpf_core): Added functions.
- (pass_data_lower_bpf_core): New pass struct.
- (pass_lower_bpf_core): New gimple_opt_pass class.
- (pack_field_expr_for_preserve_field)
- (bpf_replace_core_move_operands): Removed function.
- (bpf_enum_value_kind): Added GTY(()).
- * config/bpf/core-builtins.h (bpf_field_info_kind, bpf_type_id_kind)
- (bpf_type_info_kind, bpf_enum_value_kind): New enum.
- * config/bpf/t-bpf: Added pass bpf-passes.def to PASSES_EXTRA.
-
-2023-10-31 Neal Frager <neal.frager@amd.com>
-
- * config/microblaze/microblaze.cc: Fix mcpu version check.
-
-2023-10-31 Patrick O'Neill <patrick@rivosinc.com>
-
- * config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Remove
- TARGET_ATOMIC constraint
- (atomic_store_rvwmo<mode>): Ditto.
- * config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Ditto.
- (atomic_store_ztso<mode>): Ditto.
- * config/riscv/sync.md (atomic_load<mode>): Ditto.
- (atomic_store<mode>): Ditto.
-
-2023-10-31 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.cc (riscv_index_reg_class):
- Return GR_REGS for XTheadFMemIdx.
- (riscv_regno_ok_for_index_p): Add support for XTheadFMemIdx.
- * config/riscv/riscv.h (HARDFP_REG_P): New macro.
- * config/riscv/thead.cc (is_fmemidx_mode): New function.
- (th_memidx_classify_address_index): Add support for XTheadFMemIdx.
- (th_fmemidx_output_index): New function.
- (th_output_move): Add support for XTheadFMemIdx.
- * config/riscv/thead.md (TH_M_ANYF): New mode iterator.
- (TH_M_NOEXTF): Likewise.
- (*th_fmemidx_movsf_hardfloat): New INSN.
- (*th_fmemidx_movdf_hardfloat_rv64): Likewise.
- (*th_fmemidx_I_a): Likewise.
- (*th_fmemidx_I_c): Likewise.
- (*th_fmemidx_US_a): Likewise.
- (*th_fmemidx_US_c): Likewise.
- (*th_fmemidx_UZ_a): Likewise.
- (*th_fmemidx_UZ_c): Likewise.
-
-2023-10-31 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/constraints.md (th_m_mia): New constraint.
- (th_m_mib): Likewise.
- (th_m_mir): Likewise.
- (th_m_miu): Likewise.
- * config/riscv/riscv-protos.h (enum riscv_address_type):
- Add new address types ADDRESS_REG_REG, ADDRESS_REG_UREG,
- and ADDRESS_REG_WB and their documentation.
- (struct riscv_address_info): Add new field 'shift' and
- document the field usage for the new address types.
- (riscv_valid_base_register_p): New prototype.
- (th_memidx_legitimate_modify_p): Likewise.
- (th_memidx_legitimate_index_p): Likewise.
- (th_classify_address): Likewise.
- (th_output_move): Likewise.
- (th_print_operand_address): Likewise.
- * config/riscv/riscv.cc (riscv_index_reg_class):
- Return GR_REGS for XTheadMemIdx.
- (riscv_regno_ok_for_index_p): Add support for XTheadMemIdx.
- (riscv_classify_address): Call th_classify_address() on top.
- (riscv_output_move): Call th_output_move() on top.
- (riscv_print_operand_address): Call th_print_operand_address()
- on top.
- * config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): New macro.
- (HAVE_PRE_MODIFY_DISP): Likewise.
- * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2): Disable
- for XTheadMemIdx.
- (*zero_extendqi<SUPERQI:mode>2_internal): Convert to expand,
- create INSN with same name and disable it for XTheadMemIdx.
- (extendsidi2): Likewise.
- (*extendsidi2_internal): Disable for XTheadMemIdx.
- * config/riscv/thead.cc (valid_signed_immediate): New helper
- function.
- (th_memidx_classify_address_modify): New function.
- (th_memidx_legitimate_modify_p): Likewise.
- (th_memidx_output_modify): Likewise.
- (is_memidx_mode): Likewise.
- (th_memidx_classify_address_index): Likewise.
- (th_memidx_legitimate_index_p): Likewise.
- (th_memidx_output_index): Likewise.
- (th_classify_address): Likewise.
- (th_output_move): Likewise.
- (th_print_operand_address): Likewise.
- * config/riscv/thead.md (*th_memidx_operand): New splitter.
- (*th_memidx_zero_extendqi<SUPERQI:mode>2): New INSN.
- (*th_memidx_extendsidi2): Likewise.
- (*th_memidx_zero_extendsidi2): Likewise.
- (*th_memidx_zero_extendhi<GPR:mode>2): Likewise.
- (*th_memidx_extend<SHORT:mode><SUPERQI:mode>2): Likewise.
- (*th_memidx_bb_zero_extendsidi2): Likewise.
- (*th_memidx_bb_zero_extendhi<GPR:mode>2): Likewise.
- (*th_memidx_bb_extendhi<GPR:mode>2): Likewise.
- (*th_memidx_bb_extendqi<SUPERQI:mode>2): Likewise.
- (TH_M_ANYI): New mode iterator.
- (TH_M_NOEXTI): Likewise.
- (*th_memidx_I_a): New combiner optimization.
- (*th_memidx_I_b): Likewise.
- (*th_memidx_I_c): Likewise.
- (*th_memidx_US_a): Likewise.
- (*th_memidx_US_b): Likewise.
- (*th_memidx_US_c): Likewise.
- (*th_memidx_UZ_a): Likewise.
- (*th_memidx_UZ_b): Likewise.
- (*th_memidx_UZ_c): Likewise.
-
-2023-10-31 Carl Love <cel@us.ibm.com>
-
- * doc/extend.texi (__builtin_bcdsub_le, __builtin_bcdsub_ge): Add
- documentation for the builti-ins.
-
-2023-10-31 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/111971
- * lra-constraints.cc: (process_alt_operands): Don't check start
- hard regs for regs originated from register variables.
-
-2023-10-31 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<ieee_fmaxmin_op><mode>3): fmax/fmin
- expanders.
- (cond_<ieee_fmaxmin_op><mode>): Ditto.
- (cond_len_<ieee_fmaxmin_op><mode>): Ditto.
- (reduc_fmax_scal_<mode>): Ditto.
- (reduc_fmin_scal_<mode>): Ditto.
- * config/riscv/riscv-v.cc (needs_fp_rounding): Add fmin/fmax.
- * config/riscv/vector-iterators.md (fmin): New UNSPEC.
- (UNSPEC_VFMIN): Ditto.
- * config/riscv/vector.md (@pred_<ieee_fmaxmin_op><mode>): Add
- UNSPEC insn patterns.
- (@pred_<ieee_fmaxmin_op><mode>_scalar): Ditto.
-
-2023-10-31 Robin Dapp <rdapp@ventanamicro.com>
-
- PR bootstrap/84402
- PR target/111600
- * Makefile.in: Handle split insn-emit.cc.
- * configure: Regenerate.
- * configure.ac: Add --with-insnemit-partitions.
- * genemit.cc (output_peephole2_scratches): Print to file instead
- of stdout.
- (print_code): Ditto.
- (gen_rtx_scratch): Ditto.
- (gen_exp): Ditto.
- (gen_emit_seq): Ditto.
- (emit_c_code): Ditto.
- (gen_insn): Ditto.
- (gen_expand): Ditto.
- (gen_split): Ditto.
- (output_add_clobbers): Ditto.
- (output_added_clobbers_hard_reg_p): Ditto.
- (print_overload_arguments): Ditto.
- (print_overload_test): Ditto.
- (handle_overloaded_code_for): Ditto.
- (handle_overloaded_gen): Ditto.
- (print_header): New function.
- (handle_arg): New function.
- (main): Split output into 10 files.
- * gensupport.cc (count_patterns): New function.
- * gensupport.h (count_patterns): Define.
- * read-md.cc (md_reader::print_md_ptr_loc): Add file argument.
- * read-md.h (class md_reader): Change definition.
-
-2023-10-31 Alexandre Oliva <oliva@adacore.com>
-
- PR tree-optimization/111943
- * gimple-harden-control-flow.cc: Adjust copyright year.
- (rt_bb_visited): Add vfalse and vtrue data members.
- Zero-initialize them in the ctor.
- (rt_bb_visited::insert_exit_check_on_edge): Upon encountering
- abnormal edges, insert initializers for vfalse and vtrue on
- entry, and insert the check sequence guarded by a conditional
- in the dest block.
-
-2023-10-31 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112305
- * tree-scalar-evolution.h (expression_expensive): Adjust.
- * tree-scalar-evolution.cc (expression_expensive): Record
- when we see a COND_EXPR.
- (final_value_replacement_loop): When the replacement contains
- a COND_EXPR, rewrite it to defined overflow.
- * tree-ssa-loop-ivopts.cc (may_eliminate_iv): Adjust.
-
-2023-10-31 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112299
- * config/loongarch/loongarch-opts.h (HAVE_AS_TLS): Define to 0
- if not defined yet.
-
-2023-10-31 Lehua Ding <lehua.ding@rivai.ai>
-
- * gimple-match.h (gimple_match_op::gimple_match_op):
- Add interfaces for more arguments.
- (gimple_match_op::set_op): Add interfaces for more arguments.
- * match.pd: Add support of combining cond_len_op + vec_cond
-
-2023-10-31 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512cdintrin.h (target): Push evex512 for
- avx512cd.
- * config/i386/avx512vlintrin.h (target): Split avx512cdvl part
- out from avx512vl.
- * config/i386/i386-builtin.def (BDESC): Do not check evex512
- for builtins not needed.
-
-2023-10-31 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec.md (<float_cvt><mode><vnnconvert>2):
- Change to define_expand.
-
-2023-10-31 liuhongt <hongtao.liu@intel.com>
-
- PR target/112276
- * config/i386/mmx.md (*mmx_pblendvb_v8qi_1): Change
- define_split to define_insn_and_split to handle
- immediate_operand for comparison.
- (*mmx_pblendvb_v8qi_2): Ditto.
- (*mmx_pblendvb_<mode>_1): Ditto.
- (*mmx_pblendvb_v4qi_2): Ditto.
- (<code><mode>3): Remove define_split after it.
- (<code>v8qi3): Ditto.
- (<code><mode>3): Ditto.
- (<ode>v2hi3): Ditto.
-
-2023-10-31 Andrew Pinski <pinskia@gmail.com>
-
- * match.pd (`a == 1 ? b : a OP b`): New pattern.
- (`a == -1 ? b : a & b`): New pattern.
-
-2023-10-31 Andrew Pinski <pinskia@gmail.com>
-
- * match.pd: (`a == 0 ? b : b + a`,
- `a == 0 ? b : b - a`): New patterns.
-
-2023-10-31 Neal Frager <neal.frager@amd.com>
-
- * config/microblaze/microblaze.cc: Fix mcpu version check.
-
-2023-10-30 Mayshao <mayshao-oc@zhaoxin.com>
-
- * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize yongfeng.
- * common/config/i386/i386-common.cc: Add yongfeng.
- * common/config/i386/i386-cpuinfo.h (enum processor_subtypes):
- Add ZHAOXIN_FAM7H_YONGFENG.
- * config.gcc: Add yongfeng.
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Let -march=native recognize yongfeng processors.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Add yongfeng.
- * config/i386/i386-options.cc (m_YONGFENG): New definition.
- (m_ZHAOXIN): Ditto.
- * config/i386/i386.h (enum processor_type): Add PROCESSOR_YONGFENG.
- * config/i386/i386.md: Add yongfeng.
- * config/i386/lujiazui.md: Fix typo.
- * config/i386/x86-tune-costs.h (struct processor_costs):
- Add yongfeng costs.
- * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add yongfeng.
- (ix86_adjust_cost): Ditto.
- * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Replace
- m_LUJIAZUI with m_ZHAOXIN.
- (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.
- (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.
- (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto.
- (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto.
- (X86_TUNE_MOVX): Ditto.
- (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto.
- (X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto.
- (X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto.
- (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto.
- (X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto.
- (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto.
- (X86_TUNE_USE_LEAVE): Ditto.
- (X86_TUNE_PUSH_MEMORY): Ditto.
- (X86_TUNE_LCP_STALL): Ditto.
- (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto.
- (X86_TUNE_OPT_AGU): Ditto.
- (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto.
- (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto.
- (X86_TUNE_USE_SAHF): Ditto.
- (X86_TUNE_USE_BT): Ditto.
- (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto.
- (X86_TUNE_ONE_IF_CONV_INSN): Ditto.
- (X86_TUNE_AVOID_MFENCE): Ditto.
- (X86_TUNE_EXPAND_ABS): Ditto.
- (X86_TUNE_USE_SIMODE_FIOP): Ditto.
- (X86_TUNE_USE_FFREEP): Ditto.
- (X86_TUNE_EXT_80387_CONSTANTS): Ditto.
- (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto.
- (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto.
- (X86_TUNE_SSE_TYPELESS_STORES): Ditto.
- (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto.
- (X86_TUNE_USE_GATHER_2PARTS): Add m_YONGFENG.
- (X86_TUNE_USE_GATHER_4PARTS): Ditto.
- (X86_TUNE_USE_GATHER_8PARTS): Ditto.
- (X86_TUNE_AVOID_128FMA_CHAINS): Ditto.
- * doc/extend.texi: Add details about yongfeng.
- * doc/invoke.texi: Ditto.
- * config/i386/yongfeng.md: New file to describe yongfeng processor.
-
-2023-10-30 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/111157
- * ipa-prop.h (struct ipa_argagg_value): Newf flag killed.
- * ipa-modref.cc (ipcp_argagg_and_kill_overlap_p): New function.
- (update_signature): Mark any any IPA-CP aggregate constants at
- positions known to be killed as killed. Move check that there is
- clone_info after this pruning.
- * ipa-cp.cc (ipa_argagg_value_list::dump): Dump the killed flag.
- (ipa_argagg_value_list::push_adjusted_values): Clear the new flag.
- (push_agg_values_from_plats): Likewise.
- (ipa_push_agg_values_from_jfunc): Likewise.
- (estimate_local_effects): Likewise.
- (push_agg_values_for_index_from_edge): Likewise.
- * ipa-prop.cc (write_ipcp_transformation_info): Stream the killed
- flag.
- (read_ipcp_transformation_info): Likewise.
- (ipcp_get_aggregate_const): Update comment, assert that encountered
- record does not have killed flag set.
- (ipcp_transform_function): Prune all aggregate constants with killed
- set.
-
-2023-10-30 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/111157
- * ipa-prop.h (ipcp_transformation): New member function template
- remove_argaggs_if.
- * ipa-sra.cc (zap_useless_ipcp_results): Use remove_argaggs_if to
- filter aggreagate constants.
-
-2023-10-30 Roger Sayle <roger@nextmovesoftware.com>
-
- PR middle-end/101955
- * config/arc/arc.md (*extvsi_1_0): New define_insn_and_split
- to convert sign extract of the least significant bit into an
- AND $1 then a NEG when !TARGET_BARREL_SHIFTER.
-
-2023-10-30 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.cc (arc_rtx_costs): Improve cost estimates.
- Provide reasonable values for SHIFTS and ROTATES by constant
- bit counts depending upon TARGET_BARREL_SHIFTER.
- (arc_insn_cost): Use insn attributes if the instruction is
- recognized. Avoid calling get_attr_length for type "multi",
- i.e. define_insn_and_split patterns without explicit type.
- Fall-back to set_rtx_cost for single_set and pattern_cost
- otherwise.
- * config/arc/arc.h (COSTS_N_BYTES): Define helper macro.
- (BRANCH_COST): Improve/correct definition.
- (LOGICAL_OP_NON_SHORT_CIRCUIT): Preserve previous behavior.
-
-2023-10-30 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.cc (arc_split_ashl): Use lsl16 on TARGET_SWAP.
- (arc_split_ashr): Use swap and sign-extend on TARGET_SWAP.
- (arc_split_lshr): Use lsr16 on TARGET_SWAP.
- (arc_split_rotl): Use swap on TARGET_SWAP.
- (arc_split_rotr): Likewise.
- * config/arc/arc.md (ANY_ROTATE): New code iterator.
- (<ANY_ROTATE>si2_cnt16): New define_insn for alternate form of
- swap instruction on TARGET_SWAP.
- (ashlsi2_cnt16): Rename from *ashlsi16_cnt16 and move earlier.
- (lshrsi2_cnt16): New define_insn for LSR16 instruction.
- (*ashlsi2_cnt16): See above.
-
-2023-10-30 Richard Ball <richard.ball@arm.com>
-
- * config/arm/aout.h: Change to use the Lrtx label.
- * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Remove arm targets
- from (!target_pure_code) condition.
- (ADDR_VEC_ALIGN): Add align for tables in rodata section.
- * config/arm/arm.cc (arm_output_casesi): Alter the function to include
- .Lrtx label and remove adr instructions.
- * config/arm/arm.md
- (arm_casesi_internal): Use force_reg to generate ldr instructions that
- would otherwise be out of range, and change rtl to accommodate force reg.
- Additionally remove unnecessary register temp.
- (casesi): Remove pure code check for Arm.
- * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Remove arm
- targets from JUMP_TABLES_IN_TEXT_SECTION definition.
-
-2023-10-30 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
-
- PR target/106907
- * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Change bitwise
- xor to an equality and fix comment indentation.
-
-2023-10-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (sew64_scalar_helper): Fix bug.
- * config/riscv/riscv-v.cc (sew64_scalar_helper): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-10-30 liuhongt <hongtao.liu@intel.com>
-
- PR target/104610
- * config/i386/i386-expand.cc (ix86_expand_branch): Handle
- 512-bit vector with vpcmpeq + kortest.
- * config/i386/i386.md (cbranchxi4): New expander.
- * config/i386/sse.md: (cbranch<mode>4): Extend to V16SImode
- and V8DImode.
-
-2023-10-30 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/111449
- * expr.cc (qi_vector_mode_supported_p): Rename to...
- (by_pieces_mode_supported_p): ...this, and extends it to do
- the checking for both scalar and vector mode.
- (widest_fixed_size_mode_for_size): Call
- by_pieces_mode_supported_p to examine the mode.
- (op_by_pieces_d::smallest_fixed_size_mode_for_size): Likewise.
-
-2023-10-29 Martin Uecker <uecker@tugraz.at>
-
- PR tree-optimization/109334
- * tree-object-size.cc (parm_object_size): Allow size
- computation for implicit access attributes.
-
-2023-10-29 Max Filippov <jcmvbkbc@gmail.com>
-
- * config/xtensa/xtensa.h (TARGET_SALT): Change HW version from
- 260000 (which corresponds to RF-2014.0) to 270000 (which
- corresponds to RG-2015.0, the release where salt/saltu opcodes
- were introduced).
-
-2023-10-29 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Use
- reference type to prevent copying.
-
-2023-10-27 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/112107
- * ira-costs.cc: (calculate_equiv_gains): Use NONDEBUG_INSN_P
- instead of INSN_P.
-
-2023-10-27 Andrew Stubbs <ams@codesourcery.com>
-
- PR target/112088
- * config/gcn/gcn.cc (gcn_expand_epilogue): Fix kernel epilogue register
- conflict.
-
-2023-10-27 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md
- (vec_extract<V_1REG:mode><V_1REG_ALT:mode>_nop): Mention "operands" in
- condition to silence the warnings.
- (vec_extract<V_2REG:mode><V_2REG_ALT:mode>_nop): Likewise.
- * config/gcn/gcn.md (*movti_insn): Likewise.
-
-2023-10-27 Richard Sandiford <richard.sandiford@arm.com>
-
- * recog.cc (insn_propagation::apply_to_pattern_1): Handle shared
- ASM_OPERANDS.
-
-2023-10-27 Yangyu Chen <chenyangyu@isrc.iscas.ac.cn>
-
- * config/riscv/riscv.cc (rocket_tune_info): Fix int_div cost.
- (sifive_7_tune_info, thead_c906_tune_info): Likewise.
-
-2023-10-27 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (rawmemchr<ANYI:mode>): New expander.
- * config/riscv/riscv-protos.h (gen_no_side_effects_vsetvl_rtx):
- Define.
- (expand_rawmemchr): Define.
- * config/riscv/riscv-v.cc (force_vector_length_operand): Remove
- static.
- (expand_block_move): Move from here...
- * config/riscv/riscv-string.cc (expand_block_move): ...to here.
- (expand_rawmemchr): Add vectorized expander.
- * internal-fn.cc (expand_RAWMEMCHR): Fix typo.
-
-2023-10-27 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * ira-costs.cc: (get_equiv_regno, calculate_equiv_gains):
- Process reg equivalence invariants.
-
-2023-10-27 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/x86-tune.def (X86_TUNE_PARTIAL_MEMORY_READ_STALL):
- i386: Fiy typo in "partial_memory_read_stall" tune option.
-
-2023-10-27 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_print_operand): Add
- support for CONST_STRING.
-
-2023-10-27 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110551
- * config/i386/i386.md (<u>mul<mode><dwi>3): Make operands 1 and
- 2 take "regiser_operand" and "nonimmediate_operand" respectively.
- (<u>mulqihi3): Likewise.
- (*bmi2_umul<mode><dwi>3_1): Operand 2 needs to be register_operand
- matching the %d constraint. Use umul_highpart RTX to represent
- the highpart multiplication.
- (*umul<mode><dwi>3_1): Operand 2 should use regiser_operand
- predicate, and "a" rather than "0" as operands 0 and 2 have
- different modes.
- (define_split): For mul to mulx conversion, use the new
- umul_highpart RTX representation.
- (*mul<mode><dwi>3_1): Operand 1 should be register_operand
- and the constraint %a as operands 0 and 1 have different modes.
- (*<u>mulqihi3_1): Operand 1 should be register_operand matching
- the constraint %0.
- (define_peephole2): Providing widening multiplication variants
- of the peephole2s that tweak highpart multiplication register
- allocation.
-
-2023-10-27 Lewis Hyatt <lhyatt@gmail.com>
-
- PR preprocessor/87299
- * toplev.cc (no_backend): New static global.
- (finalize): Remove argument no_backend, which is now a
- static global.
- (process_options): Likewise.
- (do_compile): Likewise.
- (target_reinit): Don't do anything in preprocess-only mode.
- (toplev::main): Adapt to no_backend change.
- (toplev::finalize): Likewise.
-
-2023-10-27 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/101590
- PR tree-optimization/94884
- * match.pd (`(X BIT_OP Y) CMP X`): New pattern.
-
-2023-10-27 liuhongt <hongtao.liu@intel.com>
-
- PR target/103861
- * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Handle
- V2HF/V2BF/V4HF/V4BFmode.
- * config/i386/i386.cc (ix86_get_mask_mode): Return QImode when
- data_mode is V4HF/V2HFmode.
- * config/i386/mmx.md (vec_cmpv4hfqi): New expander.
- (vcond_mask_<mode>v4hi): Ditto.
- (vcond_mask_<mode>qi): Ditto.
- (vec_cmpv2hfqi): Ditto.
- (vcond_mask_<mode>v2hi): Ditto.
- (mmx_plendvb_<mode>): Add 2 combine splitters after the
- patterns.
- (mmx_pblendvb_v8qi): Ditto.
- (<code>v2hi3): Add a combine splitter after the pattern.
- (<code><mode>3): Ditto.
- (<code>v8qi3): Ditto.
- (<code><mode>3): Ditto.
- * config/i386/sse.md (vcond<mode><mode>): Merge this with ..
- (vcond<sseintvecmodelower><mode>): .. this into ..
- (vcond<VI2HFBF_AVX512VL:mode><VHF_AVX512VL:mode>): .. this,
- and extend to V8BF/V16BF/V32BFmode.
-
-2023-10-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-opts.h (TARGET_MAX_LMUL): New macro.
- * config/riscv/riscv-v.cc (preferred_simd_mode): Adapt macro.
- (autovectorize_vector_modes): Ditto.
- (can_find_related_mode_p): Ditto.
-
-2023-10-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111318
- PR target/111888
- * config.gcc: Add AVL propagation pass.
- * config/riscv/riscv-passes.def (INSERT_PASS_AFTER): Ditto.
- * config/riscv/riscv-protos.h (make_pass_avlprop): Ditto.
- * config/riscv/t-riscv: Ditto.
- * config/riscv/riscv-avlprop.cc: New file.
-
-2023-10-26 David Malcolm <dmalcolm@redhat.com>
-
- * doc/extend.texi (Common Function Attributes): Add
- null_terminated_string_arg.
-
-2023-10-26 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/111957
- * match.pd (`a != C1 ? abs(a) : C2`): New pattern.
-
-2023-10-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (range_operator::fold_range): Delete unused
- variable.
-
-2023-10-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (range_operator::fold_range): Remove
- superfluous code.
- (range_operator::rv_fold): Remove unneeded arguments.
- (operator_plus::rv_fold): Same.
- (operator_minus::rv_fold): Same.
- (operator_mult::rv_fold): Same.
- (operator_div::rv_fold): Same.
- * range-op-mixed.h: Remove lb, ub, and maybe_nan arguments from
- rv_fold methods.
- * range-op.h: Same.
-
-2023-10-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (range_operator::fold_range): Pass frange
- argument to rv_fold.
- (range_operator::rv_fold): Add frange argument.
- (operator_plus::rv_fold): Same.
- (operator_minus::rv_fold): Same.
- (operator_mult::rv_fold): Same.
- (operator_div::rv_fold): Same.
- * range-op-mixed.h: Add frange argument to rv_fold methods.
- * range-op.h: Same.
-
-2023-10-26 Richard Ball <richard.ball@arm.com>
-
- * config/arm/aout.h (ASM_OUTPUT_ADDR_DIFF_ELT): Add table output
- for different machine modes for arm.
- * config/arm/arm-protos.h (arm_output_casesi): New prototype.
- * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Make arm use
- ASM_OUTPUT_ADDR_DIFF_ELT.
- (CASE_VECTOR_SHORTEN_MODE): Change table size calculation for
- TARGET_ARM.
- (LABEL_ALIGN_AFTER_BARRIER): Change to accommodate .p2align 2
- for TARGET_ARM.
- * config/arm/arm.cc (arm_output_casesi): New function.
- * config/arm/arm.md (arm_casesi_internal): Change casesi expand
- and insn.
- for arm to use new function arm_output_casesi.
-
-2023-10-26 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.h
- (darwin_label_is_anonymous_local_objc_name): Make metadata names
- linker-visibile for GNU objective C.
-
-2023-10-26 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * dwarf2out.cc (reg_loc_descriptor): Use lra_eliminate_regs when
- LRA is used.
- * ira-costs.cc: Include regset.h.
- (equiv_can_be_consumed_p, get_equiv_regno, calculate_equiv_gains):
- New functions.
- (find_costs_and_classes): Call calculate_equiv_gains and redefine
- mem_cost of pseudos with equivs when LRA is used.
- * var-tracking.cc: Include ira.h and lra.h.
- (vt_initialize): Use lra_eliminate_regs when LRA is used.
-
-2023-10-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * doc/md.texi: Adapt COND_LEN pseudo code.
-
-2023-10-26 Roger Sayle <roger@nextmovesoftware.com>
- Richard Biener <rguenther@suse.de>
-
- PR rtl-optimization/91865
- * combine.cc (make_compound_operation): Avoid creating a
- ZERO_EXTEND of a ZERO_EXTEND.
-
-2023-10-26 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md (vcond_mask_<ILASX:mode><ILASX:mode>): Change to
- (vcond_mask_<mode><mode256_i>): this.
- * config/loongarch/lsx.md (vcond_mask_<ILSX:mode><ILSX:mode>): Change to
- (vcond_mask_<mode><mode_i>): this.
-
-2023-10-26 Thomas Schwinge <thomas@codesourcery.com>
-
- * ipa-icf.cc (sem_item::target_supports_symbol_aliases_p):
- 'gcc_checking_assert (TARGET_SUPPORTS_ALIASES);' before
- 'return true;'.
- * ipa-visibility.cc (function_and_variable_visibility): Change
- '#ifdef ASM_OUTPUT_DEF' to 'if (TARGET_SUPPORTS_ALIASES)'.
- * varasm.cc (output_constant_pool_contents)
- [#ifdef ASM_OUTPUT_DEF]:
- 'gcc_checking_assert (TARGET_SUPPORTS_ALIASES);'.
- (do_assemble_alias) [#ifdef ASM_OUTPUT_DEF]:
- 'if (!TARGET_SUPPORTS_ALIASES)',
- 'gcc_checking_assert (seen_error ());'.
- (assemble_alias): Change '#if !defined (ASM_OUTPUT_DEF)' to
- 'if (!TARGET_SUPPORTS_ALIASES)'.
- (default_asm_output_anchor):
- 'gcc_checking_assert (TARGET_SUPPORTS_ALIASES);'.
-
-2023-10-26 Alexandre Oliva <oliva@adacore.com>
-
- PR tree-optimization/111520
- * gimple-harden-conditionals.cc
- (pass_harden_compares::execute): Set EH edge probability and
- EH block execution count.
-
-2023-10-26 Alexandre Oliva <oliva@adacore.com>
-
- * tree-eh.h (make_eh_edges): Rename to...
- (make_eh_edge): ... this.
- * tree-eh.cc: Likewise. Adjust all callers...
- * gimple-harden-conditionals.cc: ... here, ...
- * gimple-harden-control-flow.cc: ... here, ...
- * tree-cfg.cc: ... here, ...
- * tree-inline.cc: ... and here.
-
-2023-10-25 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.cc (darwin_override_options): Handle fPIE.
-
-2023-10-25 Iain Sandoe <iain@sandoe.co.uk>
-
- * config.gcc: Use -E to to sed to indicate that we are using
- extended REs.
-
-2023-10-25 Jason Merrill <jason@redhat.com>
-
- * tree-core.h (struct tree_base): Update address_space comment.
-
-2023-10-25 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_internal_mov_immediate)
- Add support for immediates using MOV/EOR bitmask.
-
-2023-10-25 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/111698
- * config/i386/x86-tune.def (X86_TUNE_PARTIAL_MEMORY_READ_STALL):
- New tune.
- * config/i386/i386.h (TARGET_PARTIAL_MEMORY_READ_STALL): New macro.
- * config/i386/i386.md: New peephole pattern to narrow test
- instructions with immediate operands that test memory locations
- for zero.
-
-2023-10-25 Andrew MacLeod <amacleod@redhat.com>
-
- * value-range.cc (irange::union_append): New.
- (irange::union_): Call union_append when appropriate.
- * value-range.h (irange::union_append): New prototype.
-
-2023-10-25 Chenghui Pan <panchenghui@loongson.cn>
-
- * config/loongarch/lasxintrin.h (__lasx_xvftintrnel_l_s): Fix comments.
- (__lasx_xvfrintrne_s): Ditto.
- (__lasx_xvfrintrne_d): Ditto.
- (__lasx_xvfrintrz_s): Ditto.
- (__lasx_xvfrintrz_d): Ditto.
- (__lasx_xvfrintrp_s): Ditto.
- (__lasx_xvfrintrp_d): Ditto.
- (__lasx_xvfrintrm_s): Ditto.
- (__lasx_xvfrintrm_d): Ditto.
- * config/loongarch/lsxintrin.h (__lsx_vftintrneh_l_s): Ditto.
- (__lsx_vfrintrne_s): Ditto.
- (__lsx_vfrintrne_d): Ditto.
- (__lsx_vfrintrz_s): Ditto.
- (__lsx_vfrintrz_d): Ditto.
- (__lsx_vfrintrp_s): Ditto.
- (__lsx_vfrintrp_d): Ditto.
- (__lsx_vfrintrm_s): Ditto.
- (__lsx_vfrintrm_d): Ditto.
-
-2023-10-25 chenxiaolong <chenxiaolong@loongson.cn>
-
- * config/loongarch/loongarch.md (get_thread_pointer<mode>):Adds the
- instruction template corresponding to the __builtin_thread_pointer
- function.
- * doc/extend.texi:Add the __builtin_thread_pointer function support
- description to the documentation.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * Makefile.in (OBJS): Add rtl-ssa/movement.o.
- * rtl-ssa/access-utils.h (accesses_include_nonfixed_hard_registers)
- (single_set_info): New functions.
- (remove_uses_of_def, accesses_reference_same_resource): Declare.
- (insn_clobbers_resources): Likewise.
- * rtl-ssa/accesses.cc (rtl_ssa::remove_uses_of_def): New function.
- (rtl_ssa::accesses_reference_same_resource): Likewise.
- (rtl_ssa::insn_clobbers_resources): Likewise.
- * rtl-ssa/movement.h (can_move_insn_p): Declare.
- * rtl-ssa/movement.cc: New file.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/functions.h (function_info::remains_available_at_insn):
- New member function.
- * rtl-ssa/accesses.cc (function_info::remains_available_at_insn):
- Likewise.
- (function_info::make_use_available): Avoid false negatives for
- queries within an EBB.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/changes.cc: Include sreal.h.
- (rtl_ssa::changes_are_worthwhile): When optimizing for speed,
- scale the cost of each instruction by its execution frequency.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/access-utils.h (next_call_clobbers): New function.
- (is_single_dominating_def, remains_available_on_exit): Replace with...
- * rtl-ssa/functions.h (function_info::is_single_dominating_def)
- (function_info::remains_available_on_exit): ...these new member
- functions.
- (function_info::m_clobbered_by_calls): New member variable.
- * rtl-ssa/functions.cc (function_info::function_info): Explicitly
- initialize m_clobbered_by_calls.
- * rtl-ssa/insns.cc (function_info::record_call_clobbers): Update
- m_clobbered_by_calls for each call-clobber note.
- * rtl-ssa/member-fns.inl (function_info::is_single_dominating_def):
- New function. Check for call clobbers.
- * rtl-ssa/accesses.cc (function_info::remains_available_on_exit):
- Likewise.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/internals.h (build_info::exit_block_dominator): New
- member variable.
- * rtl-ssa/blocks.cc (build_info::build_info): Initialize it.
- (bb_walker::bb_walker): Use it, moving the computation of the
- dominator to...
- (function_info::process_all_blocks): ...here.
- (function_info::place_phis): Add dominance frontiers for the
- exit block.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/functions.h (function_info::process_uses_of_deleted_def):
- New member function.
- * rtl-ssa/changes.cc (function_info::process_uses_of_deleted_def):
- Likewise.
- (function_info::change_insns): Use it.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
- If a change describes a set of memory, ensure that that set
- is kept, regardless of the insn pattern.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/changes.cc (function_info::apply_changes_to_insn): Remove
- call to add_reg_unused_notes and instead...
- (function_info::change_insns): ...use a separate loop here.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/blocks.cc (function_info::add_artificial_accesses): Force
- global registers to be live on exit. Handle any block with zero
- successors like an exit block.
-
-2023-10-25 Thomas Schwinge <thomas@codesourcery.com>
-
- * omp-oacc-kernels-decompose.cc (omp_oacc_kernels_decompose_1):
- Handle 'OMP_CLAUSE_SELF' like 'OMP_CLAUSE_IF'.
- * omp-expand.cc (expand_omp_target): Handle 'OMP_CLAUSE_SELF' for
- 'GF_OMP_TARGET_KIND_OACC_DATA_KERNELS'.
-
-2023-10-25 Thomas Schwinge <thomas@codesourcery.com>
-
- * tree-core.h (omp_clause_code): Move 'OMP_CLAUSE_SELF' after
- 'OMP_CLAUSE_IF'.
- * tree-pretty-print.cc (dump_omp_clause): Adjust.
- * tree.cc (omp_clause_num_ops, omp_clause_code_name): Likewise.
- * tree.h: Likewise.
-
-2023-10-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (has_vl_op): Export from riscv-vsetvl to riscv-v
- (tail_agnostic_p): Ditto.
- (validate_change_or_fail): Ditto.
- (nonvlmax_avl_type_p): Ditto.
- (vlmax_avl_p): Ditto.
- (get_sew): Ditto.
- (enum vlmul_type): Ditto.
- (count_regno_occurrences): Ditto.
- * config/riscv/riscv-v.cc (has_vl_op): Ditto.
- (get_default_ta): Ditto.
- (tail_agnostic_p): Ditto.
- (validate_change_or_fail): Ditto.
- (nonvlmax_avl_type_p): Ditto.
- (vlmax_avl_p): Ditto.
- (get_sew): Ditto.
- (enum vlmul_type): Ditto.
- (get_vlmul): Ditto.
- (count_regno_occurrences): Ditto.
- * config/riscv/riscv-vsetvl.cc (vlmax_avl_p): Ditto.
- (has_vl_op): Ditto.
- (get_sew): Ditto.
- (get_vlmul): Ditto.
- (get_default_ta): Ditto.
- (tail_agnostic_p): Ditto.
- (count_regno_occurrences): Ditto.
- (validate_change_or_fail): Ditto.
-
-2023-10-25 Chung-Lin Tang <cltang@codesourcery.com>
-
- * gimplify.cc (gimplify_scan_omp_clauses): Add OMP_CLAUSE_SELF case.
- (gimplify_adjust_omp_clauses): Likewise.
- * omp-expand.cc (expand_omp_target): Add OMP_CLAUSE_SELF expansion code,
- * omp-low.cc (scan_sharing_clauses): Add OMP_CLAUSE_SELF case.
- * tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_SELF enum.
- * tree-nested.cc (convert_nonlocal_omp_clauses): Add OMP_CLAUSE_SELF
- case.
- (convert_local_omp_clauses): Likewise.
- * tree-pretty-print.cc (dump_omp_clause): Add OMP_CLAUSE_SELF case.
- * tree.cc (omp_clause_num_ops): Add OMP_CLAUSE_SELF entry.
- (omp_clause_code_name): Likewise.
- * tree.h (OMP_CLAUSE_SELF_EXPR): New macro.
-
-2023-10-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (vlmax_avl_type_p): New function.
- * config/riscv/riscv-v.cc (vlmax_avl_type_p): Ditto.
- * config/riscv/riscv-vsetvl.cc (get_avl): Adapt function.
- * config/riscv/vector.md: Change avl_type into avl_type_idx.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * recog.cc (constrain_operands): Remove UNARY_P handling.
- * reload.cc (find_reloads): Likewise.
-
-2023-10-24 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * gcov-io.h: Fix record length encoding in comment.
-
-2023-10-24 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-features.cc (compute_convert_gain): Provide
- more accurate values (sizes) for inter-unit moves with -Os.
-
-2023-10-24 Roger Sayle <roger@nextmovesoftware.com>
- Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc-protos.h (output_shift): Rename to...
- (output_shift_loop): Tweak API to take an explicit rtx_code.
- (arc_split_ashl): Prototype new function here.
- (arc_split_ashr): Likewise.
- (arc_split_lshr): Likewise.
- (arc_split_rotl): Likewise.
- (arc_split_rotr): Likewise.
- * config/arc/arc.cc (output_shift): Delete local prototype. Rename.
- (output_shift_loop): New function replacing output_shift to output
- a zero overheap loop for SImode shifts and rotates on ARC targets
- without barrel shifter (i.e. no hardware support for these insns).
- (arc_split_ashl): New helper function to split *ashlsi3_nobs.
- (arc_split_ashr): New helper function to split *ashrsi3_nobs.
- (arc_split_lshr): New helper function to split *lshrsi3_nobs.
- (arc_split_rotl): New helper function to split *rotlsi3_nobs.
- (arc_split_rotr): New helper function to split *rotrsi3_nobs.
- (arc_print_operand): Correct whitespace.
- (arc_rtx_costs): Likewise.
- (hwloop_optimize): Likewise.
- * config/arc/arc.md (ANY_SHIFT_ROTATE): New define_code_iterator.
- (define_code_attr insn): New code attribute to map to pattern name.
- (<ANY_SHIFT_ROTATE>si3): New expander unifying previous ashlsi3,
- ashrsi3 and lshrsi3 define_expands. Adds rotlsi3 and rotrsi3.
- (*<ANY_SHIFT_ROTATE>si3_nobs): New define_insn_and_split that
- unifies the previous *ashlsi3_nobs, *ashrsi3_nobs and *lshrsi3_nobs.
- We now call arc_split_<insn> in arc.cc to implement each split.
- (shift_si3): Delete define_insn, all shifts/rotates are now split.
- (shift_si3_loop): Rename to...
- (<insn>si3_loop): define_insn to handle loop implementations of
- SImode shifts and rotates, calling ouput_shift_loop for template.
- (rotrsi3): Rename to...
- (*rotrsi3_insn): define_insn for TARGET_BARREL_SHIFTER's ror.
- (*rotlsi3): New define_insn_and_split to transform left rotates
- into right rotates before reload.
- (rotlsi3_cnt1): New define_insn_and_split to implement a left
- rotate by one bit using an add.f followed by an adc.
- * config/arc/predicates.md (shiftr4_operator): Delete.
-
-2023-10-24 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc.md (mulsi3_700): Update pattern.
- (mulsi3_v2): Likewise.
- * config/arc/predicates.md (mpy_dest_reg_operand): Remove it.
-
-2023-10-24 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/104376
- PR tree-optimization/101541
- * tree-ssa-phiopt.cc (factor_out_conditional_operation):
- Allow nop conversions even if it is defined by a statement
- inside the conditional.
-
-2023-10-24 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/111913
- * match.pd (`popcount(X&Y) + popcount(X|Y)`): Add the resulting
- type for popcount.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/blocks.cc (function_info::create_degenerate_phi): Check
- whether the requested phi already exists.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa.h: Include cfgbuild.h.
- * rtl-ssa/movement.h (can_insert_after): Replace is_jump with the
- more comprehensive control_flow_insn_p.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/changes.cc (function_info::perform_pending_updates): Check
- whether an insn has been replaced by a note.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/member-fns.inl (first_any_insn_use): Handle null
- m_first_use.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/i386/i386-expand.cc (ix86_split_mmx_punpck): Allow the
- destination to be wider than the sources. Take the mode from the
- first source.
- (ix86_expand_sse_extend): Pass the destination directly to
- ix86_split_mmx_punpck, rather than using a fresh register that
- is half the size.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/i386/predicates.md (aeswidekl_operation): Protect
- REGNO check with REG_P.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_insn_cost): New function.
- (TARGET_INSN_COST): Define.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/atomics.md (aarch64_atomic_exchange<mode>): Require
- !TARGET_LSE.
-
-2023-10-24 xuli <xuli1@eswincomputing.com>
-
- PR target/111935
- * config/riscv/riscv-vector-builtins-bases.cc: fix bug.
-
-2023-10-24 Mark Harmstone <mark@harmstone.com>
-
- * opts.cc (debug_type_names): Remove stabs and xcoff.
- (df_set_names): Adjust.
-
-2023-10-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111947
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Add REGNO check.
-
-2023-10-23 Lewis Hyatt <lhyatt@gmail.com>
-
- PR preprocessor/36887
- * toplev.h (ident_hash_extra): Declare...
- * stringpool.cc (ident_hash_extra): ...this new global variable.
- (init_stringpool): Handle ident_hash_extra as well as ident_hash.
- (ggc_mark_stringpool): Likewise.
- (ggc_purge_stringpool): Likewise.
- (struct string_pool_data_extra): New struct.
- (spd2): New GC root variable.
- (gt_pch_save_stringpool): Use spd2 to handle ident_hash_extra,
- analogous to how spd is used to handle ident_hash.
- (gt_pch_restore_stringpool): Likewise.
-
-2023-10-23 Robin Dapp <rdapp@ventanamicro.com>
-
- PR tree-optimization/111794
- * tree-vect-stmts.cc (vectorizable_assignment): Add
- same-precision exception for dest and source.
-
-2023-10-23 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (popcount<mode>2): New expander.
- * config/riscv/riscv-protos.h (expand_popcount): Define.
- * config/riscv/riscv-v.cc (expand_popcount): Vectorize popcount
- with the WWG algorithm.
-
-2023-10-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111916
- * tree-sra.cc (sra_modify_assign): Do not lower all
- BIT_FIELD_REF reads that are sra_handled_bf_read_p.
-
-2023-10-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111915
- * tree-vect-slp.cc (vect_build_slp_tree_1): Check all
- accesses are either grouped or not.
-
-2023-10-23 Richard Biener <rguenther@suse.de>
-
- PR ipa/111914
- * tree-inline.cc (setup_one_parameter): Move code emitting
- a dummy load when not optimizing ...
- (initialize_inlined_parameters): ... here to after when
- we remapped the parameter type.
-
-2023-10-23 Oleg Endo <olegendo@gcc.gnu.org>
-
- PR target/111001
- * config/sh/sh_treg_combine.cc (sh_treg_combine::record_set_of_reg):
- Skip over nop move insns.
-
-2023-10-23 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/111860
- * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
- Drop .MEM nodes only.
-
-2023-10-23 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`(A - B) CMP 0 ? (A - B) : (B - A)`):
- New patterns.
-
-2023-10-23 Andrew Pinski <pinskia@gmail.com>
-
- * convert.cc (convert_to_pointer_1): Return error_mark_node
- after an error.
- (convert_to_real_1): Likewise.
- (convert_to_integer_1): Likewise.
- (convert_to_complex_1): Likewise.
-
-2023-10-23 Andrew Pinski <pinskia@gmail.com>
-
- PR c/111903
- * convert.cc (convert_to_complex_1): Return
- error_mark_node if either convert was an error
- when converting from a scalar.
-
-2023-10-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111917
- * tree-ssa-loop-unswitch.cc (hoist_guard): Always insert
- new conditional after last stmt.
-
-2023-10-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111927
- * config/riscv/riscv-vsetvl.cc: Fix bug.
-
-2023-10-23 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): Add insn type
- arg.
- (expand_vec_trunc): Take MA instead of MU for cvt_x_f_rtz.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * doc/invoke.texi (-mexplicit-relocs=style): Document.
- (-mexplicit-relocs): Document as an alias of
- -mexplicit-relocs=always.
- (-mno-explicit-relocs): Document as an alias of
- -mexplicit-relocs=none.
- (-mcmodel=extreme): Mention -mexplicit-relocs=always instead of
- -mexplicit-relocs.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/predicates.md (symbolic_pcrel_operand): New
- predicate.
- * config/loongarch/loongarch.md (define_peephole2): Optimize
- la.local + ld/st to pcalau12i + ld/st if the address is only used
- once if -mexplicit-relocs=auto and -mcmodel=normal or medium.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
- Return true for TLS symbol types if -mexplicit-relocs=auto.
- (loongarch_call_tls_get_addr): Replace TARGET_EXPLICIT_RELOCS
- with la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE.
- (loongarch_legitimize_tls_address): Likewise.
- * config/loongarch/loongarch.md (@tls_low<mode>): Remove
- TARGET_EXPLICIT_RELOCS from insn condition.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-protos.h
- (loongarch_explicit_relocs_p): Declare new function.
- * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
- Implement.
- (loongarch_symbol_insns): Call loongarch_explicit_relocs_p for
- SYMBOL_GOT_DISP, instead of using TARGET_EXPLICIT_RELOCS.
- (loongarch_split_symbol): Call loongarch_explicit_relocs_p for
- deciding if return early, instead of using
- TARGET_EXPLICIT_RELOCS.
- (loongarch_output_move): CAll loongarch_explicit_relocs_p
- instead of using TARGET_EXPLICIT_RELOCS.
- * config/loongarch/loongarch.md (*low<mode>): Remove
- TARGET_EXPLICIT_RELOCS from insn condition.
- (@ld_from_got<mode>): Likewise.
- * config/loongarch/predicates.md (move_operand): Call
- loongarch_explicit_relocs_p instead of using
- TARGET_EXPLICIT_RELOCS.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/genopts/loongarch-strings: Add strings for
- -mexplicit-relocs={auto,none,always}.
- * config/loongarch/genopts/loongarch.opt.in: Add options for
- -mexplicit-relocs={auto,none,always}.
- * config/loongarch/loongarch-str.h: Regenerate.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/loongarch-def.h
- (EXPLICIT_RELOCS_AUTO): Define.
- (EXPLICIT_RELOCS_NONE): Define.
- (EXPLICIT_RELOCS_ALWAYS): Define.
- (N_EXPLICIT_RELOCS_TYPES): Define.
- * config/loongarch/loongarch.cc
- (loongarch_option_override_internal): Error out if the old-style
- -m[no-]explicit-relocs option is used with
- -mexplicit-relocs={auto,none,always} together. Map
- -mno-explicit-relocs to -mexplicit-relocs=none and
- -mexplicit-relocs to -mexplicit-relocs=always for backward
- compatibility. Set a proper default for -mexplicit-relocs=
- based on configure-time probed linker capability. Update a
- diagnostic message to mention -mexplicit-relocs=always instead
- of the old-style -mexplicit-relocs.
- (loongarch_handle_model_attribute): Update a diagnostic message
- to mention -mexplicit-relocs=always instead of the old-style
- -mexplicit-relocs.
- * config/loongarch/loongarch.h (TARGET_EXPLICIT_RELOCS): Define.
-
-2023-10-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info): Fix typo.
- (pre_vsetvl::pre_global_vsetvl_info): Ditto.
-
-2023-10-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix avl_type attribute of tuple mov<mode>.
-
-2023-10-23 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/111784
- * tree-vect-stmts.cc (vectorizable_store): Adjust costing way for
- adjacent vector stores, by costing them with the total number
- rather than costing them one by one.
- (vectorizable_load): Adjust costing way for adjacent vector
- loads, by costing them with the total number rather than costing
- them one by one.
-
-2023-10-23 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/111753
- * config/i386/i386.cc (ix86_standard_x87sse_constant_load_p):
- Do not split to xmm16+ when !TARGET_AVX512VL.
-
-2023-10-23 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-protos.h (enum insn_type): Add new type
- values.
- * config/riscv/riscv-v.cc (emit_vec_cvt_x_f): Add undef merge
- operand handling.
- (expand_vec_ceil): Take MA instead of MU for tmp register.
- (expand_vec_floor): Ditto.
- (expand_vec_nearbyint): Ditto.
- (expand_vec_rint): Ditto.
- (expand_vec_round): Ditto.
- (expand_vec_roundeven): Ditto.
-
-2023-10-23 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch.h (CLEAR_INSN_CACHE): New definition.
-
-2023-10-23 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/111449
- * expr.cc (can_use_qi_vectors): New function to return true if
- we know how to implement OP using vectors of bytes.
- (qi_vector_mode_supported_p): New function to check if optabs
- exists for the mode and certain by pieces operations.
- (widest_fixed_size_mode_for_size): Replace the second argument
- with the type of by pieces operations. Call can_use_qi_vectors
- and qi_vector_mode_supported_p to do the check. Call
- scalar_mode_supported_p to check if the scalar mode is supported.
- (by_pieces_ninsns): Pass the type of by pieces operation to
- widest_fixed_size_mode_for_size.
- (class op_by_pieces_d): Remove m_qi_vector_mode. Add m_op to
- record the type of by pieces operations.
- (op_by_pieces_d::op_by_pieces_d): Change last argument to the
- type of by pieces operations, initialize m_op with it. Pass
- m_op to function widest_fixed_size_mode_for_size.
- (op_by_pieces_d::get_usable_mode): Pass m_op to function
- widest_fixed_size_mode_for_size.
- (op_by_pieces_d::smallest_fixed_size_mode_for_size): Call
- can_use_qi_vectors and qi_vector_mode_supported_p to do the
- check.
- (op_by_pieces_d::run): Pass m_op to function
- widest_fixed_size_mode_for_size.
- (move_by_pieces_d::move_by_pieces_d): Set m_op to MOVE_BY_PIECES.
- (store_by_pieces_d::store_by_pieces_d): Set m_op with the op.
- (can_store_by_pieces): Pass the type of by pieces operations to
- widest_fixed_size_mode_for_size.
- (clear_by_pieces): Initialize class store_by_pieces_d with
- CLEAR_BY_PIECES.
- (compare_by_pieces_d::compare_by_pieces_d): Set m_op to
- COMPARE_BY_PIECES.
-
-2023-10-23 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/111820
- PR tree-optimization/111833
- * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Give
- up vectorization for nonlinear iv vect_step_op_mul when
- step_expr is not exact_log2 and niters is greater than
- TYPE_PRECISION (TREE_TYPE (step_expr)). Also don't vectorize
- for nagative niters_skip which will be used by fully masked
- loop.
- (vect_can_advance_ivs_p): Pass whole phi_info to
- vect_can_peel_nonlinear_iv_p.
- * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Optimize
- init_expr * pow (step_expr, skipn) to init_expr
- << (log2 (step_expr) * skipn) when step_expr is exact_log2.
-
-2023-10-23 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/mmx.md (mmx_pinsrw): Remove.
-
-2023-10-22 Andrew Pinski <pinskia@gmail.com>
-
- PR target/110986
- * config/aarch64/aarch64.md (*cmov<mode>_insn_insv): New pattern.
- (*cmov_uxtw_insn_insv): Likewise.
-
-2023-10-22 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-
- * doc/invoke.texi: Document the new -nodefaultrpaths option.
- * doc/install.texi: Document the new --with-darwin-extra-rpath
- option.
-
-2023-10-22 Iain Sandoe <iain@sandoe.co.uk>
-
- * Makefile.in: set ENABLE_DARWIN_AT_RPATH in site.tmp.
-
-2023-10-22 Iain Sandoe <iain@sandoe.co.uk>
-
- * configure.ac: Add --with-darwin-extra-rpath option.
- * config/darwin.h: Handle DARWIN_EXTRA_RPATH.
- * config.in: Regenerate.
- * configure: Regenerate.
-
-2023-10-22 Iain Sandoe <iain@sandoe.co.uk>
-
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
- * configure.ac: Handle Darwin rpaths.
- * config/darwin.h: Handle Darwin rpaths.
- * config/darwin.opt: Handle Darwin rpaths.
- * Makefile.in: Handle Darwin rpaths.
-
-2023-10-22 Iain Sandoe <iain@sandoe.co.uk>
-
- * gcc.cc (RUNPATH_OPTION): New.
- (do_spec_1): Provide '%P' as a spec to insert rpaths for
- each compiler startfile path.
-
-2023-10-22 Andrew Burgess <andrew.burgess@embecosm.com>
- Maxim Blinov <maxim.blinov@embecosm.com>
- Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
- Iain Sandoe <iain@sandoe.co.uk>
-
- * config.gcc: Default to heap trampolines on macOS 11 and above.
- * config/i386/darwin.h: Define X86_CUSTOM_FUNCTION_TEST.
- * config/i386/i386.h: Define X86_CUSTOM_FUNCTION_TEST.
- * config/i386/i386.cc: Use X86_CUSTOM_FUNCTION_TEST.
-
-2023-10-22 Andrew Burgess <andrew.burgess@embecosm.com>
- Maxim Blinov <maxim.blinov@embecosm.com>
- Iain Sandoe <iain@sandoe.co.uk>
- Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-
- * builtins.def (BUILT_IN_NESTED_PTR_CREATED): Define.
- (BUILT_IN_NESTED_PTR_DELETED): Ditto.
- * common.opt (ftrampoline-impl): Add option to control
- generation of trampoline instantiation (heap or stack).
- * coretypes.h: Define enum trampoline_impl.
- * tree-nested.cc (convert_tramp_reference_op): Don't bother calling
- __builtin_adjust_trampoline for heap trampolines.
- (finalize_nesting_tree_1): Emit calls to
- __builtin_nested_...{created,deleted} if we're generating with
- -ftrampoline-impl=heap.
- * tree.cc (build_common_builtin_nodes): Build
- __builtin_nested_...{created,deleted}.
- * doc/invoke.texi (-ftrampoline-impl): Document.
-
-2023-10-22 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
- Prohibit 'E' and 'H' combinations.
-
-2023-10-22 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc (riscv_ext_version_table):
- Change version number of the 'Zfa' extension to 1.0.
-
-2023-10-21 Pan Li <pan2.li@intel.com>
-
- PR target/111857
- * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Remove.
- * config/riscv/riscv-protos.h (vls_mode_valid_p): New func decl.
- * config/riscv/riscv-v.cc (autovectorize_vector_modes): Replace
- macro reference to func.
- (vls_mode_valid_p): New func impl for vls mode valid or not.
- * config/riscv/riscv-vector-switch.def (VLS_ENTRY): Replace
- macro reference to func.
- * config/riscv/vector-iterators.md: Ditto.
-
-2023-10-20 Roger Sayle <roger@nextmovesoftware.com>
- Uros Bizjak <ubizjak@gmail.com>
-
- PR middle-end/101955
- PR tree-optimization/106245
- * config/i386/i386.md (*extv<mode>_1_0): New define_insn_and_split.
-
-2023-10-20 David Edelsohn <dje.gcc@gmail.com>
-
- * gimple-harden-control-flow.cc: Include memmodel.h.
-
-2023-10-20 David Edelsohn <dje.gcc@gmail.com>
-
- * gimple-harden-control-flow.cc: Include tm_p.h.
-
-2023-10-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR tree-optimization/111882
- * tree-if-conv.cc (get_bitfield_rep): Return NULL_TREE for bitfields
- with non-constant offsets.
-
-2023-10-20 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/111866
- * tree-vect-loop-manip.cc (vect_do_peeling): Pass null as vinfo to
- vect_set_loop_condition during prolog peeling.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111445
- * tree-scalar-evolution.cc (simple_iv_with_niters):
- Add missing check for a sign-conversion.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110243
- PR tree-optimization/111336
- * tree-ssa-loop-ivopts.cc (strip_offset_1): Rewrite
- operations with undefined behavior on overflow to
- unsigned arithmetic.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111891
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fix
- assert.
-
-2023-10-20 Andrew Stubbs <ams@codesourcery.com>
-
- * config.gcc: Allow --with-arch=gfx1030.
- * config/gcn/gcn-hsa.h (NO_XNACK): gfx1030 does not support xnack.
- (ASM_SPEC): gfx1030 needs -mattr=+wavefrontsize64 set.
- * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1030.
- (TARGET_GFX1030): New.
- (TARGET_RDNA2): New.
- * config/gcn/gcn-valu.md (@dpp_move<mode>): Disable for RDNA2.
- (addc<mode>3<exec_vcc>): Add RDNA2 syntax variant.
- (subc<mode>3<exec_vcc>): Likewise.
- (<convop><mode><vndi>2_exec): Add RDNA2 alternatives.
- (vec_cmp<mode>di): Likewise.
- (vec_cmp<u><mode>di): Likewise.
- (vec_cmp<mode>di_exec): Likewise.
- (vec_cmp<u><mode>di_exec): Likewise.
- (vec_cmp<mode>di_dup): Likewise.
- (vec_cmp<mode>di_dup_exec): Likewise.
- (reduc_<reduc_op>_scal_<mode>): Disable for RDNA2.
- (*<reduc_op>_dpp_shr_<mode>): Likewise.
- (*plus_carry_dpp_shr_<mode>): Likewise.
- (*plus_carry_in_dpp_shr_<mode>): Likewise.
- * config/gcn/gcn.cc (gcn_option_override): Recognise gfx1030.
- (gcn_global_address_p): RDNA2 only allows smaller offsets.
- (gcn_addr_space_legitimate_address_p): Likewise.
- (gcn_omp_device_kind_arch_isa): Recognise gfx1030.
- (gcn_expand_epilogue): Use VGPRs instead of SGPRs.
- (output_file_start): Configure gfx1030.
- * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __RDNA2__;
- (ASSEMBLER_DIALECT): New.
- * config/gcn/gcn.md (rdna): New define_attr.
- (enabled): Use "rdna" attribute.
- (gcn_return): Remove s_dcache_wb.
- (addcsi3_scalar): Add RDNA2 syntax variant.
- (addcsi3_scalar_zero): Likewise.
- (addptrdi3): Likewise.
- (mulsi3): v_mul_lo_i32 should be v_mul_lo_u32 on all ISA.
- (*memory_barrier): Add RDNA2 syntax variant.
- (atomic_load<mode>): Add RDNA2 cache control variants, and disable
- scalar atomics for RDNA2.
- (atomic_store<mode>): Likewise.
- (atomic_exchange<mode>): Likewise.
- * config/gcn/gcn.opt (gpu_type): Add gfx1030.
- * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1030): New.
- (main): Recognise -march=gfx1030.
- * config/gcn/t-omp-device: Add gfx1030 isa.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111000
- * stor-layout.h (element_precision): Move ..
- * tree.h (element_precision): .. here.
- * tree-ssa-loop-im.cc (movement_possibility_1): Restrict
- motion of shifts and rotates.
-
-2023-10-20 Alexandre Oliva <oliva@adacore.com>
-
- * tree-core.h (ECF_XTHROW): New macro.
- * tree.cc (set_call_expr): Add expected_throw attribute when
- ECF_XTHROW is set.
- (build_common_builtin_node): Add ECF_XTHROW to
- __cxa_end_cleanup and _Unwind_Resume or _Unwind_SjLj_Resume.
- * calls.cc (flags_from_decl_or_type): Check for expected_throw
- attribute to set ECF_XTHROW.
- * gimple.cc (gimple_build_call_from_tree): Propagate
- ECF_XTHROW from decl flags to gimple call...
- (gimple_call_flags): ... and back.
- * gimple.h (GF_CALL_XTHROW): New gf_mask flag.
- (gimple_call_set_expected_throw): New.
- (gimple_call_expected_throw_p): New.
- * Makefile.in (OBJS): Add gimple-harden-control-flow.o.
- * builtins.def (BUILT_IN___HARDCFR_CHECK): New.
- * common.opt (fharden-control-flow-redundancy): New.
- (-fhardcfr-check-returning-calls): New.
- (-fhardcfr-check-exceptions): New.
- (-fhardcfr-check-noreturn-calls=*): New.
- (Enum hardcfr_check_noreturn_calls): New.
- (fhardcfr-skip-leaf): New.
- * doc/invoke.texi: Document them.
- (hardcfr-max-blocks, hardcfr-max-inline-blocks): New params.
- * flag-types.h (enum hardcfr_noret): New.
- * gimple-harden-control-flow.cc: New.
- * params.opt (-param=hardcfr-max-blocks=): New.
- (-param=hradcfr-max-inline-blocks=): New.
- * passes.def (pass_harden_control_flow_redundancy): Add.
- * tree-pass.h (make_pass_harden_control_flow_redundancy):
- Declare.
- * doc/extend.texi: Document expected_throw attribute.
-
-2023-10-20 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/changes.cc (function_info::change_insns): Ensure we call
- ::remove_insn on deleted insns.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- * doc/generic.texi ({L,R}ROTATE_EXPR): Document.
-
-2023-10-20 Oleg Endo <olegendo@gcc.gnu.org>
-
- PR target/101177
- * config/sh/sh.md (unnamed split pattern): Fix comparison of
- find_regno_note result.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (update_epilogue_loop_vinfo): Rewrite
- both STMT_VINFO_GATHER_SCATTER_P and VMAT_GATHER_SCATTER
- stmt refs.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (off_map, off_op0_map, off_arg2_map,
- off_arg3_arg2_map): New.
- (vect_get_operand_map): Get flag whether the stmt was
- recognized as gather or scatter and use the above
- accordingly.
- (vect_get_and_check_slp_defs): Adjust.
- (vect_build_slp_tree_2): Likewise.
-
-2023-10-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info): Rename variables.
- (pre_vsetvl::pre_global_vsetvl_info): Ditto.
- (pre_vsetvl::emit_vsetvl): Ditto.
-
-2023-10-20 Tamar Christina <tamar.christina@arm.com>
- Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-if-conv.cc (if_convertible_loop_p_1): Move check from here ...
- (get_loop_body_if_conv_order): ... to here.
- (if_convertible_loop_p): Remove single_exit check.
- (tree_if_conversion): Move single_exit check to if-conversion part and
- support multiple exits.
-
-2023-10-20 Tamar Christina <tamar.christina@arm.com>
- Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-vect-patterns.cc (vect_init_pattern_stmt): Copy STMT_VINFO_TYPE
- from original statement.
- (vect_recog_bitfield_ref_pattern): Support bitfields in gcond.
-
-2023-10-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111848
- * config/riscv/riscv-selftests.cc (run_const_vector_selftests): Adapt selftest.
- * config/riscv/riscv-v.cc (expand_const_vector): Change it into vec_duplicate splitter.
-
-2023-10-20 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/111037
- PR target/111234
- PR target/111725
- * config/riscv/riscv-vsetvl.cc (bitmap_union_of_preds_with_entry): New.
- (debug): Removed.
- (compute_reaching_defintion): New.
- (enum vsetvl_type): Moved.
- (vlmax_avl_p): Moved.
- (enum emit_type): Moved.
- (vlmul_to_str): Moved.
- (vlmax_avl_insn_p): Removed.
- (policy_to_str): Moved.
- (loop_basic_block_p): Removed.
- (valid_sew_p): Removed.
- (vsetvl_insn_p): Moved.
- (vsetvl_vtype_change_only_p): Removed.
- (after_or_same_p): Removed.
- (before_p): Removed.
- (anticipatable_occurrence_p): Removed.
- (available_occurrence_p): Removed.
- (insn_should_be_added_p): Removed.
- (get_all_sets): Moved.
- (get_same_bb_set): Moved.
- (gen_vsetvl_pat): Removed.
- (calculate_vlmul): Moved.
- (get_max_int_sew): New.
- (emit_vsetvl_insn): Removed.
- (get_max_float_sew): New.
- (eliminate_insn): Removed.
- (insert_vsetvl): Removed.
- (count_regno_occurrences): Moved.
- (get_vl_vtype_info): Removed.
- (enum def_type): Moved.
- (validate_change_or_fail): Moved.
- (change_insn): Removed.
- (get_all_real_uses): Moved.
- (get_forward_read_vl_insn): Removed.
- (get_backward_fault_first_load_insn): Removed.
- (change_vsetvl_insn): Removed.
- (avl_source_has_vsetvl_p): Removed.
- (source_equal_p): Moved.
- (calculate_sew): Removed.
- (same_equiv_note_p): Moved.
- (get_expr_id): New.
- (incompatible_avl_p): Removed.
- (get_regno): New.
- (different_sew_p): Removed.
- (get_bb_index): New.
- (different_lmul_p): Removed.
- (has_no_uses): Moved.
- (different_ratio_p): Removed.
- (different_tail_policy_p): Removed.
- (different_mask_policy_p): Removed.
- (possible_zero_avl_p): Removed.
- (enum demand_flags): New.
- (second_ratio_invalid_for_first_sew_p): Removed.
- (second_ratio_invalid_for_first_lmul_p): Removed.
- (enum class): New.
- (float_insn_valid_sew_p): Removed.
- (second_sew_less_than_first_sew_p): Removed.
- (first_sew_less_than_second_sew_p): Removed.
- (class vsetvl_info): New.
- (compare_lmul): Removed.
- (second_lmul_less_than_first_lmul_p): Removed.
- (second_ratio_less_than_first_ratio_p): Removed.
- (DEF_INCOMPATIBLE_COND): Removed.
- (greatest_sew): Removed.
- (first_sew): Removed.
- (second_sew): Removed.
- (first_vlmul): Removed.
- (second_vlmul): Removed.
- (first_ratio): Removed.
- (second_ratio): Removed.
- (vlmul_for_first_sew_second_ratio): Removed.
- (vlmul_for_greatest_sew_second_ratio): Removed.
- (ratio_for_second_sew_first_vlmul): Removed.
- (class vsetvl_block_info): New.
- (DEF_SEW_LMUL_FUSE_RULE): New.
- (always_unavailable): Removed.
- (avl_unavailable_p): Removed.
- (class demand_system): New.
- (sew_unavailable_p): Removed.
- (lmul_unavailable_p): Removed.
- (ge_sew_unavailable_p): Removed.
- (ge_sew_lmul_unavailable_p): Removed.
- (ge_sew_ratio_unavailable_p): Removed.
- (DEF_UNAVAILABLE_COND): Removed.
- (same_sew_lmul_demand_p): Removed.
- (propagate_avl_across_demands_p): Removed.
- (reg_available_p): Removed.
- (support_relaxed_compatible_p): Removed.
- (demands_can_be_fused_p): Removed.
- (earliest_pred_can_be_fused_p): Removed.
- (vsetvl_dominated_by_p): Removed.
- (avl_info::avl_info): Removed.
- (avl_info::single_source_equal_p): Removed.
- (avl_info::multiple_source_equal_p): Removed.
- (DEF_SEW_LMUL_RULE): New.
- (avl_info::operator=): Removed.
- (avl_info::operator==): Removed.
- (DEF_POLICY_RULE): New.
- (avl_info::operator!=): Removed.
- (avl_info::has_non_zero_avl): Removed.
- (vl_vtype_info::vl_vtype_info): Removed.
- (vl_vtype_info::operator==): Removed.
- (DEF_AVL_RULE): New.
- (vl_vtype_info::operator!=): Removed.
- (vl_vtype_info::same_avl_p): Removed.
- (vl_vtype_info::same_vtype_p): Removed.
- (vl_vtype_info::same_vlmax_p): Removed.
- (vector_insn_info::operator>=): Removed.
- (vector_insn_info::operator==): Removed.
- (class pre_vsetvl): New.
- (vector_insn_info::parse_insn): Removed.
- (vector_insn_info::compatible_p): Removed.
- (vector_insn_info::skip_avl_compatible_p): Removed.
- (vector_insn_info::compatible_avl_p): Removed.
- (vector_insn_info::compatible_vtype_p): Removed.
- (vector_insn_info::available_p): Removed.
- (vector_insn_info::fuse_avl): Removed.
- (vector_insn_info::fuse_sew_lmul): Removed.
- (vector_insn_info::fuse_tail_policy): Removed.
- (vector_insn_info::fuse_mask_policy): Removed.
- (vector_insn_info::local_merge): Removed.
- (vector_insn_info::global_merge): Removed.
- (vector_insn_info::get_avl_or_vl_reg): Removed.
- (vector_insn_info::update_fault_first_load_avl): Removed.
- (vector_insn_info::dump): Removed.
- (vector_infos_manager::vector_infos_manager): Removed.
- (vector_infos_manager::create_expr): Removed.
- (vector_infos_manager::get_expr_id): Removed.
- (vector_infos_manager::all_same_ratio_p): Removed.
- (vector_infos_manager::all_avail_in_compatible_p): Removed.
- (vector_infos_manager::all_same_avl_p): Removed.
- (vector_infos_manager::expr_set_num): Removed.
- (vector_infos_manager::release): Removed.
- (vector_infos_manager::create_bitmap_vectors): Removed.
- (vector_infos_manager::free_bitmap_vectors): Removed.
- (vector_infos_manager::dump): Removed.
- (class pass_vsetvl): Adjust.
- (pass_vsetvl::get_vector_info): Removed.
- (pass_vsetvl::get_block_info): Removed.
- (pass_vsetvl::update_vector_info): Removed.
- (pass_vsetvl::update_block_info): Removed.
- (pre_vsetvl::compute_avl_def_data): New.
- (pass_vsetvl::simple_vsetvl): Removed.
- (pass_vsetvl::compute_local_backward_infos): Removed.
- (pass_vsetvl::need_vsetvl): Removed.
- (pass_vsetvl::transfer_before): Removed.
- (pass_vsetvl::transfer_after): Removed.
- (pre_vsetvl::compute_vsetvl_def_data): New.
- (pass_vsetvl::emit_local_forward_vsetvls): Removed.
- (pass_vsetvl::prune_expressions): Removed.
- (pass_vsetvl::compute_local_properties): Removed.
- (pre_vsetvl::compute_lcm_local_properties): New.
- (pass_vsetvl::earliest_fusion): Removed.
- (pre_vsetvl::fuse_local_vsetvl_info): New.
- (pass_vsetvl::vsetvl_fusion): Removed.
- (pass_vsetvl::can_refine_vsetvl_p): Removed.
- (pre_vsetvl::earliest_fuse_vsetvl_info): New.
- (pass_vsetvl::refine_vsetvls): Removed.
- (pass_vsetvl::cleanup_vsetvls): Removed.
- (pass_vsetvl::commit_vsetvls): Removed.
- (pass_vsetvl::pre_vsetvl): Removed.
- (pass_vsetvl::get_vsetvl_at_end): Removed.
- (local_avl_compatible_p): Removed.
- (pass_vsetvl::local_eliminate_vsetvl_insn): Removed.
- (pre_vsetvl::pre_global_vsetvl_info): New.
- (get_first_vsetvl_before_rvv_insns): Removed.
- (pass_vsetvl::global_eliminate_vsetvl_insn): Removed.
- (pre_vsetvl::emit_vsetvl): New.
- (pass_vsetvl::ssa_post_optimization): Removed.
- (pre_vsetvl::cleaup): New.
- (pre_vsetvl::remove_avl_operand): New.
- (pass_vsetvl::df_post_optimization): Removed.
- (pre_vsetvl::remove_unused_dest_operand): New.
- (pass_vsetvl::init): Removed.
- (pass_vsetvl::done): Removed.
- (pass_vsetvl::compute_probabilities): Removed.
- (pass_vsetvl::lazy_vsetvl): Adjust.
- (pass_vsetvl::execute): Adjust.
- * config/riscv/riscv-vsetvl.def (DEF_INCOMPATIBLE_COND): Removed.
- (DEF_SEW_LMUL_RULE): New.
- (DEF_SEW_LMUL_FUSE_RULE): Removed.
- (DEF_POLICY_RULE): New.
- (DEF_UNAVAILABLE_COND): Removed
- (DEF_AVL_RULE): New demand type.
- (sew_lmul): New demand type.
- (ratio_only): New demand type.
- (sew_only): New demand type.
- (ge_sew): New demand type.
- (ratio_and_ge_sew): New demand type.
- (tail_mask_policy): New demand type.
- (tail_policy_only): New demand type.
- (mask_policy_only): New demand type.
- (ignore_policy): New demand type.
- (avl): New demand type.
- (non_zero_avl): New demand type.
- (ignore_avl): New demand type.
- * config/riscv/t-riscv: Removed riscv-vsetvl.h
- * config/riscv/riscv-vsetvl.h: Removed.
-
-2023-10-20 Alexandre Oliva <oliva@adacore.com>
-
- * tree-eh.cc (make_eh_edges): Return the new edge.
- * tree-eh.h (make_eh_edges): Likewise.
-
-2023-10-19 Marek Polacek <polacek@redhat.com>
-
- * doc/contrib.texi: Add entry for Patrick Palka.
-
-2023-10-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * omp-simd-clone.cc (simd_clone_adjust_argument_types): Make function
- compatible with mask parameters in clone.
- * tree-vect-stmts.cc (vect_build_all_ones_mask): Allow vector boolean
- typed masks.
- (vectorizable_simd_clone_call): Enable the use of masked clones in
- fully masked loops.
-
-2023-10-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR tree-optimization/110485
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Disable partial
- vectors usage if a notinbranch simdclone has been selected.
-
-2023-10-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-vect-data-refs.cc (vect_get_smallest_scalar_type): Special case
- simd clone calls and only use types that are mapped to vectors.
- (simd_clone_call_p): New helper function.
-
-2023-10-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-parloops.cc (try_transform_to_exit_first_loop_alt): Accept
- poly NIT and ALT_BOUND.
-
-2023-10-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-parloops.cc (create_loop_fn): Copy specific target and
- optimization options to clone.
-
-2023-10-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * omp-simd-clone.cc (simd_clone_subparts): Remove.
- (simd_clone_init_simd_arrays): Replace simd_clone_supbarts with
- TYPE_VECTOR_SUBPARTS.
- (ipa_simd_modify_function_body): Likewise.
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Likewise.
- (simd_clone_subparts): Remove.
-
-2023-10-19 Jason Merrill <jason@redhat.com>
-
- * ABOUT-GCC-NLS: Add usage guidance.
-
-2023-10-19 Jason Merrill <jason@redhat.com>
-
- * diagnostic-core.h (permerror): Rename new overloads...
- (permerror_opt): To this.
- * diagnostic.cc: Likewise.
-
-2023-10-19 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/111860
- * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
- Remove PHI nodes that dominate loop.
-
-2023-10-19 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111131
- * tree-vect-loop.cc (update_epilogue_loop_vinfo): Make
- sure to update all gather/scatter stmt DRs, not only those
- that eventually got VMAT_GATHER_SCATTER set.
- * tree-vect-slp.cc (_slp_oprnd_info::first_gs_info): Add.
- (vect_get_and_check_slp_defs): Handle gathers/scatters,
- adding the offset as SLP operand and comparing base and scale.
- (vect_build_slp_tree_1): Handle gathers.
- (vect_build_slp_tree_2): Likewise.
-
-2023-10-19 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vect_build_gather_load_calls): Rename
- to ...
- (vect_build_one_gather_load_call): ... this. Refactor,
- inline widening/narrowing support ...
- (vectorizable_load): ... here, do gather vectorization
- with builtin decls along other gather vectorization.
-
-2023-10-19 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64.md (load_pair_dw_tftf): Rename to ...
- (load_pair_dw_<TX:mode><TX2:mode>): ... this.
- (store_pair_dw_tftf): Rename to ...
- (store_pair_dw_<TX:mode><TX2:mode>): ... this.
- * config/aarch64/iterators.md (TX2): New.
-
-2023-10-19 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add new
- parameter to give final insn position, infer use of mem if it isn't
- specified explicitly.
- (function_info::change_insns): Pass down final insn position to
- finalize_new_accesses.
- * rtl-ssa/functions.h: Add parameter to finalize_new_accesses.
-
-2023-10-19 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/accesses.cc (function_info::reparent_use): New.
- * rtl-ssa/functions.h (function_info): Declare new member
- function reparent_use.
-
-2023-10-19 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/access-utils.h (drop_memory_access): New.
-
-2023-10-19 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/insns.cc (function_info::add_insn_after): Ensure we
- update the prev pointer on the following nondebug insn in the
- case that !insn->is_debug_insn () && next->is_debug_insn ().
-
-2023-10-19 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386.h: Correct the ISA enabled for Arrow Lake.
- Also make Clearwater Forest depends on Sierra Forest.
- * config/i386/i386-options.cc: Revise the order of the macro
- definition to avoid confusion.
- * doc/extend.texi: Revise documentation.
- * doc/invoke.texi: Correct documentation.
-
-2023-10-19 Andrew Stubbs <ams@codesourcery.com>
-
- * config.gcc (amdgcn): Switch default to --with-arch=gfx900.
- Implement support for --with-multilib-list.
- * config/gcn/t-gcn-hsa: Likewise.
- * doc/install.texi: Likewise.
- * doc/invoke.texi: Mark Fiji deprecated.
-
-2023-10-19 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_vector_costs): Inherit from
- vector_costs. Add a constructor.
- (loongarch_vector_costs::add_stmt_cost): Use adjust_cost_for_freq to
- adjust the cost for inner loops.
- (loongarch_vector_costs::count_operations): New function.
- (loongarch_vector_costs::determine_suggested_unroll_factor): Ditto.
- (loongarch_vector_costs::finish_cost): Ditto.
- (loongarch_builtin_vectorization_cost): Adjust.
- * config/loongarch/loongarch.opt (loongarch-vect-unroll-limit): New parameter.
- (loongarcg-vect-issue-info): Ditto.
- (mmemvec-cost): Delete.
- * config/loongarch/genopts/loongarch.opt.in
- (loongarch-vect-unroll-limit): Ditto.
- (loongarcg-vect-issue-info): Ditto.
- (mmemvec-cost): Delete.
- * doc/invoke.texi (loongarcg-vect-unroll-limit): Document new option.
-
-2023-10-19 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md
- (vec_widen_<su>mult_even_v8si): New patterns.
- (vec_widen_<su>add_hi_<mode>): Ditto.
- (vec_widen_<su>add_lo_<mode>): Ditto.
- (vec_widen_<su>sub_hi_<mode>): Ditto.
- (vec_widen_<su>sub_lo_<mode>): Ditto.
- (vec_widen_<su>mult_hi_<mode>): Ditto.
- (vec_widen_<su>mult_lo_<mode>): Ditto.
- * config/loongarch/loongarch.md (u_bool): New iterator.
- * config/loongarch/loongarch-protos.h
- (loongarch_expand_vec_widen_hilo): New prototype.
- * config/loongarch/loongarch.cc
- (loongarch_expand_vec_interleave): New function.
- (loongarch_expand_vec_widen_hilo): New function.
-
-2023-10-19 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md
- (avg<mode>3_ceil): New patterns.
- (uavg<mode>3_ceil): Ditto.
- (avg<mode>3_floor): Ditto.
- (uavg<mode>3_floor): Ditto.
- (usadv32qi): Ditto.
- (ssadv32qi): Ditto.
- * config/loongarch/lsx.md
- (avg<mode>3_ceil): New patterns.
- (uavg<mode>3_ceil): Ditto.
- (avg<mode>3_floor): Ditto.
- (uavg<mode>3_floor): Ditto.
- (usadv16qi): Ditto.
- (ssadv16qi): Ditto.
-
-2023-10-18 Andrew Pinski <pinskia@gmail.com>
-
- PR middle-end/111863
- * expr.cc (do_store_flag): Don't over write arg0
- when stripping off `& POW2`.
-
-2023-10-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- PR tree-optimization/111648
- * fold-const.cc (valid_mask_for_fold_vec_perm_cst_p): If a1
- chooses base element from arg, ensure that it's a natural stepped
- sequence.
- (build_vec_cst_rand): New param natural_stepped and use it to
- construct a naturally stepped sequence.
- (test_nunits_min_2): Add new unit tests Case 6 and Case 7.
-
-2023-10-18 Dimitar Dimitrov <dimitar@dinux.eu>
-
- * config/pru/pru.cc (pru_insn_cost): New function.
- (TARGET_INSN_COST): Define for PRU.
-
-2023-10-18 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_test_fractional_cost):
- Test <= instead of testing < twice.
-
-2023-10-18 Jakub Jelinek <jakub@redhat.com>
-
- PR bootstrap/111852
- * cse.cc (cse_insn): Add workaround for GCC 4.8-4.9, instead of
- using rtx_def type for memory_extend_buf, use unsigned char
- arrayy with size of rtx_def and its alignment.
-
-2023-10-18 Jason Merrill <jason@redhat.com>
-
- * doc/invoke.texi: Move -fpermissive to Warning Options.
- * diagnostic.cc (update_effective_level_from_pragmas): Remove
- redundant system header check.
- (diagnostic_report_diagnostic): Move down syshdr/-w check.
- (diagnostic_impl): Handle DK_PERMERROR with an option number.
- (permerror): Add new overloads.
- * diagnostic-core.h (permerror): Declare them.
-
-2023-10-18 Tobias Burnus <tobias@codesourcery.com>
-
- * gimplify.cc (gimplify_bind_expr): Remove "omp allocate" attribute
- to avoid that auxillary statement list reaches LTO.
-
-2023-10-18 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/111845
- * tree-ssa-math-opts.cc (match_uaddc_usubc): Remember temporary
- statements for the 4 operand addition or subtraction of 3 operands
- from 1 operand cases and remove them when successful. Look for
- nested additions even from rhs[2], not just rhs[1].
-
-2023-10-18 Tobias Burnus <tobias@codesourcery.com>
-
- PR target/111093
- * config/nvptx/nvptx.cc (nvptx_option_override): Issue fatal error
- instead of an assert ICE when no -march= has been specified.
-
-2023-10-18 Iain Sandoe <iain@sandoe.co.uk>
-
- * config.in: Regenerate.
- * config/darwin.cc (darwin_file_start): Add assembler directives
- for the target OS version, where these are supported by the
- assembler.
- (darwin_override_options): Check for building >= macOS 10.14.
- * configure: Regenerate.
- * configure.ac: Check for assembler support of .build_version
- directives.
-
-2023-10-18 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * tree-if-conv.cc (INCLUDE_ALGORITHM): Remove.
- (typedef struct ifcvt_arg_entry): New.
- (cmp_arg_entry): New.
- (gen_phi_arg_condition, gen_phi_nest_statement,
- predicate_scalar_phi): Use them.
-
-2023-10-18 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
- Rewrite to new syntax.
- (*aarch64_simd_mov<VQMOV:mode): Rewrite to new syntax and merge in
- splits.
-
-2023-10-18 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * tree-if-conv.cc (if_convertible_stmt_p): Allow any const IFN.
-
-2023-10-18 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * match.pd: Add new cond_op rule.
-
-2023-10-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (movfcc): Use fcmp.caf.s for
- zeroing a fcc.
-
-2023-10-18 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_simd_clone_call):
- Relax check to again allow passing integer mode masks
- as traditional vectors.
-
-2023-10-18 Tamar Christina <tamar.christina@arm.com>
-
- * tree-loop-distribution.cc (copy_loop_before): Request no LCSSA.
- * tree-vect-loop-manip.cc (adjust_phi_and_debug_stmts): Add additional
- asserts.
- (slpeel_tree_duplicate_loop_to_edge_cfg): Keep LCSSA during peeling.
- (find_guard_arg): Look value up through explicit edge and original defs.
- (vect_do_peeling): Use it.
- (slpeel_update_phi_nodes_for_guard2): Take explicit exit edge.
- (slpeel_update_phi_nodes_for_lcssa, slpeel_update_phi_nodes_for_loops):
- Remove.
- * tree-vect-loop.cc (vect_create_epilog_for_reduction): Initialize phi.
- * tree-vectorizer.h (slpeel_tree_duplicate_loop_to_edge_cfg): Add
- optional param to turn off LCSSA mode.
-
-2023-10-18 Tamar Christina <tamar.christina@arm.com>
-
- * tree-if-conv.cc (tree_if_conversion): Record exits in aux.
- * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
- it.
- * tree-vect-loop.cc (vect_get_loop_niters): Determine main exit.
- (vec_init_loop_exit_info): Extend analysis when multiple exits.
- (vect_analyze_loop_form): Record conds and determine main cond.
- (vect_create_loop_vinfo): Extend bookkeeping of conds.
- (vect_analyze_loop): Release conds.
- * tree-vectorizer.h (LOOP_VINFO_LOOP_CONDS,
- LOOP_VINFO_LOOP_IV_COND): New.
- (struct vect_loop_form_info): Add conds, alt_loop_conds;
- (struct loop_vec_info): Add conds, loop_iv_cond.
-
-2023-10-18 Tamar Christina <tamar.christina@arm.com>
-
- * tree-loop-distribution.cc (copy_loop_before): Pass exit explicitly.
- (loop_distribution::distribute_loop): Bail out of not single exit.
- * tree-scalar-evolution.cc (get_loop_exit_condition): New.
- * tree-scalar-evolution.h (get_loop_exit_condition): New.
- * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment): Pass exit
- explicitly.
- * tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors,
- vect_set_loop_condition_partial_vectors_avx512,
- vect_set_loop_condition_normal, vect_set_loop_condition): Explicitly
- take exit.
- (slpeel_tree_duplicate_loop_to_edge_cfg): Explicitly take exit and
- return new peeled corresponding peeled exit.
- (slpeel_can_duplicate_loop_p): Explicitly take exit.
- (find_loop_location): Handle not knowing an explicit exit.
- (vect_update_ivs_after_vectorizer, vect_gen_vector_loop_niters_mult_vf,
- find_guard_arg, slpeel_update_phi_nodes_for_loops,
- slpeel_update_phi_nodes_for_guard2): Use new exits.
- (vect_do_peeling): Update bookkeeping to keep track of exits.
- * tree-vect-loop.cc (vect_get_loop_niters): Explicitly take exit to
- analyze.
- (vec_init_loop_exit_info): New.
- (_loop_vec_info::_loop_vec_info): Initialize vec_loop_iv,
- vec_epilogue_loop_iv, scalar_loop_iv.
- (vect_analyze_loop_form): Initialize exits.
- (vect_create_loop_vinfo): Set main exit.
- (vect_create_epilog_for_reduction, vectorizable_live_operation,
- vect_transform_loop): Use it.
- (scale_profile_for_vect_loop): Explicitly take exit to scale.
- * tree-vectorizer.cc (set_uid_loop_bbs): Initialize loop exit.
- * tree-vectorizer.h (LOOP_VINFO_IV_EXIT, LOOP_VINFO_EPILOGUE_IV_EXIT,
- LOOP_VINFO_SCALAR_IV_EXIT): New.
- (struct loop_vec_info): Add vec_loop_iv, vec_epilogue_loop_iv,
- scalar_loop_iv.
- (vect_set_loop_condition, slpeel_can_duplicate_loop_p,
- slpeel_tree_duplicate_loop_to_edge_cfg): Take explicit exits.
- (vec_init_loop_exit_info): New.
- (struct vect_loop_form_info): Add loop_exit.
-
-2023-10-18 Tamar Christina <tamar.christina@arm.com>
-
- * tree-vect-stmts.cc (vectorizable_comparison): Refactor, splitting body
- to ...
- (vectorizable_comparison_1): ...This.
-
-2023-10-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (shuffle_consecutive_patterns): New function.
- (expand_vec_perm_const_1): Add consecutive pattern recognition.
-
-2023-10-18 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_intel_cpu): Add Panther
- Lake.
- * common/config/i386/i386-common.cc (processor_name):
- Ditto.
- (processor_alias_table): Ditto.
- * common/config/i386/i386-cpuinfo.h (enum processor_types):
- Add INTEL_PANTHERLAKE.
- * config.gcc: Add -march=pantherlake.
- * config/i386/driver-i386.cc (host_detect_local_cpu): Refactor
- the if clause. Handle pantherlake.
- * config/i386/i386-c.cc (ix86_target_macros_internal):
- Handle pantherlake.
- * config/i386/i386-options.cc (processor_cost_table): Ditto.
- (m_PANTHERLAKE): New.
- (m_CORE_HYBRID): Add pantherlake.
- * config/i386/i386.h (enum processor_type): Ditto.
- * doc/extend.texi: Ditto.
- * doc/invoke.texi: Ditto.
-
-2023-10-18 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-options.cc (m_CORE_HYBRID): New.
- * config/i386/x86-tune.def: Replace hybrid client tune to
- m_CORE_HYBRID.
-
-2023-10-18 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h
- (get_intel_cpu): Handle Clearwater Forest.
- * common/config/i386/i386-common.cc (processor_name):
- Add Clearwater Forest.
- (processor_alias_table): Ditto.
- * common/config/i386/i386-cpuinfo.h (enum processor_types):
- Add INTEL_CLEARWATERFOREST.
- * config.gcc: Add -march=clearwaterforest.
- * config/i386/driver-i386.cc (host_detect_local_cpu): Handle
- clearwaterforest.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
- * config/i386/i386-options.cc (processor_cost_table): Ditto.
- (m_CLEARWATERFOREST): New.
- (m_CORE_ATOM): Add clearwaterforest.
- * config/i386/i386.h (enum processor_type): Ditto.
- * doc/extend.texi: Ditto.
- * doc/invoke.texi: Ditto.
-
-2023-10-18 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/mmx.md (fma<mode>4): New expander.
- (fms<mode>4): Ditto.
- (fnma<mode>4): Ditto.
- (fnms<mode>4): Ditto.
- (vec_fmaddsubv4hf4): Ditto.
- (vec_fmsubaddv4hf4): Ditto.
-
-2023-10-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111832
- * config/riscv/riscv-vector-costs.cc (get_biggest_mode): New function.
-
-2023-10-17 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Don't make
- the position of the LR save slot dependent on stack clash
- protection unless shadow call stacks are enabled.
-
-2023-10-17 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame): Add vectors that
- store the list saved GPRs, FPRs and predicate registers.
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Initialize
- the lists of saved registers. Use them to choose push candidates.
- Invalidate pop candidates if we're not going to do a pop.
- (aarch64_next_callee_save): Delete.
- (aarch64_save_callee_saves): Take a list of registers,
- rather than a range. Make !skip_wb select only write-back
- candidates.
- (aarch64_expand_prologue): Update calls accordingly.
- (aarch64_restore_callee_saves): Take a list of registers,
- rather than a range. Always skip pop candidates. Also skip
- LR if shadow call stacks are enabled.
- (aarch64_expand_epilogue): Update calls accordingly.
-
-2023-10-17 Richard Sandiford <richard.sandiford@arm.com>
-
- * cfgbuild.h (find_sub_basic_blocks): Declare.
- * cfgbuild.cc (update_profile_for_new_sub_basic_block): New function,
- split out from...
- (find_many_sub_basic_blocks): ...here.
- (find_sub_basic_blocks): New function.
- * function.cc (thread_prologue_and_epilogue_insns): Handle
- epilogues that contain jumps.
-
-2023-10-17 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110817
- * tree-ssanames.cc (ssa_name_has_boolean_range): Remove the
- check for boolean type as they don't have "[0,1]" range.
-
-2023-10-17 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/111432
- * match.pd (`a & (x | CST)`): New pattern.
-
-2023-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-cfg.cc (move_sese_region_to_fn): Initialize profile_count for
- new basic block.
-
-2023-10-17 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111846
- * tree-vectorizer.h (_slp_tree::simd_clone_info): Add.
- (SLP_TREE_SIMD_CLONE_INFO): New.
- * tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize
- SLP_TREE_SIMD_CLONE_INFO.
- (_slp_tree::~_slp_tree): Release it.
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
- SLP_TREE_SIMD_CLONE_INFO or STMT_VINFO_SIMD_CLONE_INFO
- dependent on if we're doing SLP.
-
-2023-10-17 Jakub Jelinek <jakub@redhat.com>
-
- * wide-int-print.h (print_dec_buf_size): For length, divide number
- of bits by 3 and add 3 instead of division by 4 and adding 4.
- * wide-int-print.cc (print_decs): Remove superfluous ()s. Don't call
- print_hex, instead call print_decu on either negated value after
- printing - or on wi itself.
- (print_decu): Don't call print_hex, instead print even large numbers
- decimally.
- (pp_wide_int_large): Assume len from print_dec_buf_size is big enough
- even if it returns false.
- * pretty-print.h (pp_wide_int): Use print_dec_buf_size to check if
- pp_wide_int_large should be used.
- * tree-pretty-print.cc (dump_generic_node): Use print_hex_buf_size
- to compute needed buffer size.
-
-2023-10-17 Richard Biener <rguenther@suse.de>
-
- PR middle-end/111818
- * tree-ssa.cc (maybe_optimize_var): When clearing
- DECL_NOT_GIMPLE_REG_P always rewrite into SSA.
-
-2023-10-17 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111807
- * tree-sra.cc (build_ref_for_model): Only call
- build_reconstructed_reference when the offsets are the same.
-
-2023-10-17 Vineet Gupta <vineetg@rivosinc.com>
-
- PR target/111466
- * expr.cc (expand_expr_real_2): Do not clear SUBREG_PROMOTED_VAR_P.
-
-2023-10-17 Chenghui Pan <panchenghui@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
- fix impl related to vec_initv32qiv16qi template to avoid ICE.
-
-2023-10-17 Lulu Cheng <chenglulu@loongson.cn>
- Chenghua Xu <xuchenghua@loongson.cn>
-
- * config/loongarch/loongarch.h (ASM_OUTPUT_ALIGN_WITH_NOP):
- Delete.
-
-2023-10-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (max_number_of_live_regs): Fix big LMUL issue.
- (get_store_value): New function.
-
-2023-10-16 Jeff Law <jlaw@ventanamicro.com>
-
- * explow.cc (probe_stack_range): Handle case when expand_binop
- does not construct its result in the expected location.
-
-2023-10-16 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_initialize): When LANG=C, update
- default for -fdiagnostics-text-art-charset from emoji to ascii.
- * doc/invoke.texi (fdiagnostics-text-art-charset): Document the above.
-
-2023-10-16 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_initialize): Ensure
- context->extra_output_kind is initialized.
-
-2023-10-16 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.cc (ix86_can_inline_p):
- Handle CM_LARGE and CM_LARGE_PIC.
- (x86_elf_aligned_decl_common): Ditto.
- (x86_output_aligned_bss): Ditto.
- * config/i386/i386.opt: Update doc for -mlarge-data-threshold=.
- * doc/invoke.texi: Update doc for -mlarge-data-threshold=.
-
-2023-10-16 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv-protos.h (emit_block_move): Remove redundant
- prototype. Improve comment.
- * config/riscv/riscv.cc (riscv_block_move_straight): Move from riscv.cc
- into riscv-string.cc.
- (riscv_adjust_block_mem, riscv_block_move_loop): Likewise.
- (riscv_expand_block_move): Likewise.
- * config/riscv/riscv-string.cc (riscv_block_move_straight): Add moved
- function.
- (riscv_adjust_block_mem, riscv_block_move_loop): Likewise.
- (riscv_expand_block_move): Likewise.
-
-2023-10-16 Manolis Tsamis <manolis.tsamis@vrull.eu>
-
- * Makefile.in: Add fold-mem-offsets.o.
- * passes.def: Schedule a new pass.
- * tree-pass.h (make_pass_fold_mem_offsets): Declare.
- * common.opt: New options.
- * doc/invoke.texi: Document new option.
- * fold-mem-offsets.cc: New file.
-
-2023-10-16 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/101541
- * match.pd (A CMP 0 ? A : -A): Improve
- using bitwise_equal_p.
-
-2023-10-16 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/31531
- * match.pd (~X op ~Y): Allow for an optional nop convert.
- (~X op C): Likewise.
-
-2023-10-16 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md (*ashlsi3_1): New pre-reload splitter to
- use bset dst,0,src to implement 1<<x on !TARGET_BARREL_SHIFTER.
-
-2023-10-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/vector.md (popcountv8hi2_vx): Sign extend each
- unsigned vector element.
-
-2023-10-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (costs::preferred_new_lmul_p): Use VLS modes.
-
-2023-10-16 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * fold-const.cc (expr_not_equal_to): Replace get_global_range_query
- by get_range_query.
- * gimple-fold.cc (size_must_be_zero_p): Likewise.
- * gimple-range-fold.cc (fur_source::fur_source): Likewise.
- * gimple-ssa-warn-access.cc (check_nul_terminated_array): Likewise.
- * tree-dfa.cc (get_ref_base_and_extent): Likewise.
-
-2023-10-16 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/mmx.md (V2FI_32): New mode iterator
- (movd_v2hf_to_sse): Rename to ..
- (movd_<mode>_to_sse): .. this.
- (movd_v2hf_to_sse_reg): Rename to ..
- (movd_<mode>_to_sse_reg): .. this.
- (fix<fixunssuffix>_trunc<mode><mmxintvecmodelower>2): New
- expander.
- (fix<fixunssuffix>_truncv2hfv2si2): Ditto.
- (float<floatunssuffix><mmxintvecmodelower><mode>2): Ditto.
- (float<floatunssuffix>v2siv2hf2): Ditto.
- (extendv2hfv2sf2): Ditto.
- (truncv2sfv2hf2): Ditto.
- * config/i386/sse.md (*vec_concatv8hf_movss): Rename to ..
- (*vec_concat<mode>_movss): .. this.
-
-2023-10-16 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386-expand.cc (ix86_sse_copysign_to_positive):
- Handle HFmode.
- (ix86_expand_round_sse4): Ditto.
- * config/i386/i386.md (roundhf2): New expander.
- (lroundhf<mode>2): Ditto.
- (lrinthf<mode>2): Ditto.
- (l<rounding_insn>hf<mode>2): Ditto.
- * config/i386/mmx.md (sqrt<mode>2): Ditto.
- (btrunc<mode>2): Ditto.
- (nearbyint<mode>2): Ditto.
- (rint<mode>2): Ditto.
- (lrint<mode><mmxintvecmodelower>2): Ditto.
- (floor<mode>2): Ditto.
- (lfloor<mode><mmxintvecmodelower>2): Ditto.
- (ceil<mode>2): Ditto.
- (lceil<mode><mmxintvecmodelower>2): Ditto.
- (round<mode>2): Ditto.
- (lround<mode><mmxintvecmodelower>2): Ditto.
- * config/i386/sse.md (lrint<mode><sseintvecmodelower>2): Ditto.
- (lfloor<mode><sseintvecmodelower>2): Ditto.
- (lceil<mode><sseintvecmodelower>2): Ditto.
- (lround<mode><sseintvecmodelower>2): Ditto.
- (sse4_1_round<ssescalarmodesuffix>): Extend to V8HF.
- (round<mode>2): Extend to V8HF/V16HF/V32HF.
-
-2023-10-15 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/invoke.texi (-fopenacc, -fopenmp, -fopenmp-simd): Use @samp not
- @code; document more completely the supported Fortran sentinels.
-
-2023-10-15 Roger Sayle <roger@nextmovesoftware.com>
-
- * optabs.cc (expand_subword_shift): Call simplify_expand_binop
- instead of expand_binop. Optimize cases (i.e. avoid generating
- RTL) when CARRIES or INTO_INPUT is zero. Use one_cmpl_optab
- (i.e. NOT) instead of xor_optab with ~0 to calculate ~OP1.
-
-2023-10-15 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/111800
- * wide-int-print.h (print_dec_buf_size, print_decs_buf_size,
- print_decu_buf_size, print_hex_buf_size): New inline functions.
- * wide-int.cc (assert_deceq): Use print_dec_buf_size.
- (assert_hexeq): Use print_hex_buf_size.
- * wide-int-print.cc (print_decs): Use print_decs_buf_size.
- (print_decu): Use print_decu_buf_size.
- (print_hex): Use print_hex_buf_size.
- (pp_wide_int_large): Use print_dec_buf_size.
- * value-range.cc (irange_bitmask::dump): Use print_hex_buf_size.
- * value-range-pretty-print.cc (vrange_printer::print_irange_bitmasks):
- Likewise.
- * tree-ssa-loop-niter.cc (do_warn_aggressive_loop_optimizations): Use
- print_dec_buf_size. Use TYPE_SIGN macro in print_dec call argument.
-
-2023-10-15 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * combine.cc (simplify_compare_const): Fix handling of unsigned
- constants.
-
-2023-10-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Fix vsingle incorrect attribute for RVVM2x2QI.
-
-2023-10-14 Tobias Burnus <tobias@codesourcery.com>
-
- * gimplify.cc (gimplify_bind_expr): Handle Fortran's
- 'omp allocate' for stack variables.
-
-2023-10-14 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * tree-core.h (struct tree_base): Remove int_length.offset
- member, change type of int_length.unextended and int_length.extended
- from unsigned char to unsigned short.
- * tree.h (TREE_INT_CST_OFFSET_NUNITS): Remove.
- (wi::extended_tree <N>::get_len): Don't use TREE_INT_CST_OFFSET_NUNITS,
- instead compute it at runtime from TREE_INT_CST_EXT_NUNITS and
- TREE_INT_CST_NUNITS.
- * tree.cc (wide_int_to_tree_1): Don't assert
- TREE_INT_CST_OFFSET_NUNITS value.
- (make_int_cst): Don't initialize TREE_INT_CST_OFFSET_NUNITS.
- * wide-int.h (WIDE_INT_MAX_ELTS): Change from 255 to 1024.
- (WIDEST_INT_MAX_ELTS): Change from 510 to 2048, adjust comment.
- (trailing_wide_int_storage): Change m_len type from unsigned char *
- to unsigned short *.
- (trailing_wide_int_storage::trailing_wide_int_storage): Change second
- argument from unsigned char * to unsigned short *.
- (trailing_wide_ints): Change m_max_len type from unsigned char to
- unsigned short. Change m_len element type from
- struct{unsigned char len;} to unsigned short.
- (trailing_wide_ints <N>::operator []): Remove .len from m_len
- accesses.
- * value-range-storage.h (irange_storage::lengths_address): Change
- return type from const unsigned char * to const unsigned short *.
- (irange_storage::write_lengths_address): Change return type from
- unsigned char * to unsigned short *.
- * value-range-storage.cc (irange_storage::write_lengths_address):
- Likewise.
- (irange_storage::lengths_address): Change return type from
- const unsigned char * to const unsigned short *.
- (write_wide_int): Change len argument type from unsigned char *&
- to unsigned short *&.
- (irange_storage::set_irange): Change len variable type from
- unsigned char * to unsigned short *.
- (read_wide_int): Change len argument type from unsigned char to
- unsigned short. Use trailing_wide_int_storage <unsigned short>
- instead of trailing_wide_int_storage and
- trailing_wide_int <unsigned short> instead of trailing_wide_int.
- (irange_storage::get_irange): Change len variable type from
- unsigned char * to unsigned short *.
- (irange_storage::size): Multiply n by sizeof (unsigned short)
- in len_size variable initialization.
- (irange_storage::dump): Change len variable type from
- unsigned char * to unsigned short *.
-
-2023-10-14 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Remove redundant iterators.
-
-2023-10-13 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/111622
- * value-relation.cc (equiv_oracle::add_partial_equiv): Do not
- register a partial equivalence if an operand has no uses.
-
-2023-10-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111795
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Handle
- integer mode mask arguments.
-
-2023-10-13 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (mask_call_maps): New.
- (vect_get_operand_map): Handle IFN_MASK_CALL.
- (vect_build_slp_tree_1): Likewise.
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Handle
- SLP.
-
-2023-10-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111779
- * tree-sra.cc (sra_handled_bf_read_p): New function.
- (build_access_from_expr_1): Handle some BIT_FIELD_REFs.
- (sra_modify_expr): Likewise.
- (make_fancy_name_1): Skip over BIT_FIELD_REF.
-
-2023-10-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111773
- * tree-ssa-dce.cc (mark_stmt_if_obviously_necessary): Do
- not elide noreturn calls that are reflected to the IL.
-
-2023-10-13 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump
- max_power to 64.
- * config/riscv/riscv.h (MAX_POLY_VARIANT): New.
-
-2023-10-13 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lfloor<mode><v_i_l_ll_convert>2): New
- pattern for lfloor/lfloorf.
- * config/riscv/riscv-protos.h (enum insn_type): New enum value.
- (expand_vec_lfloor): New func decl for expanding lfloor.
- * config/riscv/riscv-v.cc (expand_vec_lfloor): New func impl
- for expanding lfloor.
-
-2023-10-13 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lceil<mode><v_i_l_ll_convert>2): New
- pattern] for lceil/lceilf.
- * config/riscv/riscv-protos.h (enum insn_type): New enum value.
- (expand_vec_lceil): New func decl for expanding lceil.
- * config/riscv/riscv-v.cc (expand_vec_lceil): New func impl
- for expanding lceil.
-
-2023-10-12 Michael Meissner <meissner@linux.ibm.com>
-
- PR target/111778
- * config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Protect
- code from shifts that are undefined.
- (can_be_built_by_li_lis_and_rldicr): Likewise.
- (can_be_built_by_li_and_rldic): Protect code from shifts that
- undefined. Also replace uses of 1ULL with HOST_WIDE_INT_1U.
-
-2023-10-12 Alex Coplan <alex.coplan@arm.com>
-
- * reg-notes.def (NOALIAS): Correct comment.
-
-2023-10-12 Jakub Jelinek <jakub@redhat.com>
-
- PR bootstrap/111787
- * tree.h (wi::int_traits <unextended_tree>::needs_write_val_arg): New
- static data member.
- (int_traits <extended_tree <N>>::needs_write_val_arg): Likewise.
- (wi::ints_for): Provide separate partial specializations for
- generic_wide_int <extended_tree <N>> and INL_CONST_PRECISION or that
- and CONST_PRECISION, rather than using
- int_traits <extended_tree <N> >::precision_type as the second template
- argument.
- * rtl.h (wi::int_traits <rtx_mode_t>::needs_write_val_arg): New
- static data member.
- * double-int.h (wi::int_traits <double_int>::needs_write_val_arg):
- Likewise.
-
-2023-10-12 Mary Bennett <mary.bennett@embecosm.com>
-
- PR middle-end/111777
- * doc/extend.texi: Change subsubsection to subsection for
- CORE-V built-ins.
-
-2023-10-12 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Add undef.
-
-2023-10-12 Jakub Jelinek <jakub@redhat.com>
-
- * wide-int.h (widest_int_storage <N>::write_val): If l is small
- and there is space in u.val array, store a canary value at the
- end when checking.
- (widest_int_storage <N>::set_len): Check the canary hasn't been
- overwritten.
-
-2023-10-12 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * wide-int.h: Adjust file comment.
- (WIDE_INT_MAX_INL_ELTS): Define to former value of WIDE_INT_MAX_ELTS.
- (WIDE_INT_MAX_INL_PRECISION): Define.
- (WIDE_INT_MAX_ELTS): Change to 255. Assert that WIDE_INT_MAX_INL_ELTS
- is smaller than WIDE_INT_MAX_ELTS.
- (RWIDE_INT_MAX_ELTS, RWIDE_INT_MAX_PRECISION, WIDEST_INT_MAX_ELTS,
- WIDEST_INT_MAX_PRECISION): Define.
- (WI_BINARY_RESULT_VAR, WI_UNARY_RESULT_VAR): Change write_val callers
- to pass 0 as a new argument.
- (class widest_int_storage): Likewise.
- (widest_int, widest2_int): Change typedefs to use widest_int_storage
- rather than fixed_wide_int_storage.
- (enum wi::precision_type): Add INL_CONST_PRECISION enumerator.
- (struct binary_traits): Add partial specializations for
- INL_CONST_PRECISION.
- (generic_wide_int): Add needs_write_val_arg static data member.
- (int_traits): Likewise.
- (wide_int_storage): Replace val non-static data member with a union
- u of it and HOST_WIDE_INT *valp. Declare copy constructor, copy
- assignment operator and destructor. Add unsigned int argument to
- write_val.
- (wide_int_storage::wide_int_storage): Initialize precision to 0
- in the default ctor. Remove unnecessary {}s around STATIC_ASSERTs.
- Assert in non-default ctor T's precision_type is not
- INL_CONST_PRECISION and allocate u.valp for large precision. Add
- copy constructor.
- (wide_int_storage::~wide_int_storage): New.
- (wide_int_storage::operator=): Add copy assignment operator. In
- assignment operator remove unnecessary {}s around STATIC_ASSERTs,
- assert ctor T's precision_type is not INL_CONST_PRECISION and
- if precision changes, deallocate and/or allocate u.valp.
- (wide_int_storage::get_val): Return u.valp rather than u.val for
- large precision.
- (wide_int_storage::write_val): Likewise. Add an unused unsigned int
- argument.
- (wide_int_storage::set_len): Use write_val instead of writing val
- directly.
- (wide_int_storage::from, wide_int_storage::from_array): Adjust
- write_val callers.
- (wide_int_storage::create): Allocate u.valp for large precisions.
- (wi::int_traits <wide_int_storage>::get_binary_precision): New.
- (fixed_wide_int_storage::fixed_wide_int_storage): Make default
- ctor defaulted.
- (fixed_wide_int_storage::write_val): Add unused unsigned int argument.
- (fixed_wide_int_storage::from, fixed_wide_int_storage::from_array):
- Adjust write_val callers.
- (wi::int_traits <fixed_wide_int_storage>::get_binary_precision): New.
- (WIDEST_INT): Define.
- (widest_int_storage): New template class.
- (wi::int_traits <widest_int_storage>): New.
- (trailing_wide_int_storage::write_val): Add unused unsigned int
- argument.
- (wi::get_binary_precision): Use
- wi::int_traits <WI_BINARY_RESULT (T1, T2)>::get_binary_precision
- rather than get_precision on get_binary_result.
- (wi::copy): Adjust write_val callers. Don't call set_len if
- needs_write_val_arg.
- (wi::bit_not): If result.needs_write_val_arg, call write_val
- again with upper bound estimate of len.
- (wi::sext, wi::zext, wi::set_bit): Likewise.
- (wi::bit_and, wi::bit_and_not, wi::bit_or, wi::bit_or_not,
- wi::bit_xor, wi::add, wi::sub, wi::mul, wi::mul_high, wi::div_trunc,
- wi::div_floor, wi::div_ceil, wi::div_round, wi::divmod_trunc,
- wi::mod_trunc, wi::mod_floor, wi::mod_ceil, wi::mod_round,
- wi::lshift, wi::lrshift, wi::arshift): Likewise.
- (wi::bswap, wi::bitreverse): Assert result.needs_write_val_arg
- is false.
- (gt_ggc_mx, gt_pch_nx): Remove generic template for all
- generic_wide_int, instead add functions and templates for each
- storage of generic_wide_int. Make functions for
- generic_wide_int <wide_int_storage> and templates for
- generic_wide_int <widest_int_storage <N>> deleted.
- (wi::mask, wi::shifted_mask): Adjust write_val calls.
- * wide-int.cc (zeros): Decrease array size to 1.
- (BLOCKS_NEEDED): Use CEIL.
- (canonize): Use HOST_WIDE_INT_M1.
- (wi::from_buffer): Pass 0 to write_val.
- (wi::to_mpz): Use CEIL.
- (wi::from_mpz): Likewise. Pass 0 to write_val. Use
- WIDE_INT_MAX_INL_ELTS instead of WIDE_INT_MAX_ELTS.
- (wi::mul_internal): Use WIDE_INT_MAX_INL_PRECISION instead of
- MAX_BITSIZE_MODE_ANY_INT in automatic array sizes, for prec
- above WIDE_INT_MAX_INL_PRECISION estimate precision from
- lengths of operands. Use XALLOCAVEC allocated buffers for
- prec above WIDE_INT_MAX_INL_PRECISION.
- (wi::divmod_internal): Likewise.
- (wi::lshift_large): For len > WIDE_INT_MAX_INL_ELTS estimate
- it from xlen and skip.
- (rshift_large_common): Remove xprecision argument, add len
- argument with len computed in caller. Don't return anything.
- (wi::lrshift_large, wi::arshift_large): Compute len here
- and pass it to rshift_large_common, for lengths above
- WIDE_INT_MAX_INL_ELTS using estimations from xlen if possible.
- (assert_deceq, assert_hexeq): For lengths above
- WIDE_INT_MAX_INL_ELTS use XALLOCAVEC allocated buffer.
- (test_printing): Use WIDE_INT_MAX_INL_PRECISION instead of
- WIDE_INT_MAX_PRECISION.
- * wide-int-print.h (WIDE_INT_PRINT_BUFFER_SIZE): Use
- WIDE_INT_MAX_INL_PRECISION instead of WIDE_INT_MAX_PRECISION.
- * wide-int-print.cc (print_decs, print_decu, print_hex): For
- lengths above WIDE_INT_MAX_INL_ELTS use XALLOCAVEC allocated buffer.
- * tree.h (wi::int_traits<extended_tree <N>>): Change precision_type
- to INL_CONST_PRECISION for N == ADDR_MAX_PRECISION.
- (widest_extended_tree): Use WIDEST_INT_MAX_PRECISION instead of
- WIDE_INT_MAX_PRECISION.
- (wi::ints_for): Use int_traits <extended_tree <N> >::precision_type
- instead of hard coded CONST_PRECISION.
- (widest2_int_cst): Use WIDEST_INT_MAX_PRECISION instead of
- WIDE_INT_MAX_PRECISION.
- (wi::extended_tree <N>::get_len): Use WIDEST_INT_MAX_PRECISION rather
- than WIDE_INT_MAX_PRECISION.
- (wi::ints_for::zero): Use
- wi::int_traits <wi::extended_tree <N> >::precision_type instead of
- wi::CONST_PRECISION.
- * tree.cc (build_replicated_int_cst): Formatting fix. Use
- WIDE_INT_MAX_INL_ELTS rather than WIDE_INT_MAX_ELTS.
- * print-tree.cc (print_node): Don't print TREE_UNAVAILABLE on
- INTEGER_CSTs, TREE_VECs or SSA_NAMEs.
- * double-int.h (wi::int_traits <double_int>::precision_type): Change
- to INL_CONST_PRECISION from CONST_PRECISION.
- * poly-int.h (struct poly_coeff_traits): Add partial specialization
- for wi::INL_CONST_PRECISION.
- * cfgloop.h (bound_wide_int): New typedef.
- (struct nb_iter_bound): Change bound type from widest_int to
- bound_wide_int.
- (struct loop): Change nb_iterations_upper_bound,
- nb_iterations_likely_upper_bound and nb_iterations_estimate type from
- widest_int to bound_wide_int.
- * cfgloop.cc (record_niter_bound): Return early if wi::min_precision
- of i_bound is too large for bound_wide_int. Adjustments for the
- widest_int to bound_wide_int type change in non-static data members.
- (get_estimated_loop_iterations, get_max_loop_iterations,
- get_likely_max_loop_iterations): Adjustments for the widest_int to
- bound_wide_int type change in non-static data members.
- * tree-vect-loop.cc (vect_transform_loop): Likewise.
- * tree-ssa-loop-niter.cc (do_warn_aggressive_loop_optimizations): Use
- XALLOCAVEC allocated buffer for i_bound len above
- WIDE_INT_MAX_INL_ELTS.
- (record_estimate): Return early if wi::min_precision of i_bound is too
- large for bound_wide_int. Adjustments for the widest_int to
- bound_wide_int type change in non-static data members.
- (wide_int_cmp): Use bound_wide_int instead of widest_int.
- (bound_index): Use bound_wide_int instead of widest_int.
- (discover_iteration_bound_by_body_walk): Likewise. Use
- widest_int::from to convert it to widest_int when passed to
- record_niter_bound.
- (maybe_lower_iteration_bound): Use widest_int::from to convert it to
- widest_int when passed to record_niter_bound.
- (estimate_numbers_of_iteration): Don't record upper bound if
- loop->nb_iterations has too large precision for bound_wide_int.
- (n_of_executions_at_most): Use widest_int::from.
- * tree-ssa-loop-ivcanon.cc (remove_redundant_iv_tests): Adjust for
- the widest_int to bound_wide_int changes.
- * match.pd (fold_sign_changed_comparison simplification): Use
- wide_int::from on wi::to_wide instead of wi::to_widest.
- * value-range.h (irange::maybe_resize): Avoid using memcpy on
- non-trivially copyable elements.
- * value-range.cc (irange_bitmask::dump): Use XALLOCAVEC allocated
- buffer for mask or value len above WIDE_INT_PRINT_BUFFER_SIZE.
- * fold-const.cc (fold_convert_const_int_from_int, fold_unary_loc):
- Use wide_int::from on wi::to_wide instead of wi::to_widest.
- * tree-ssa-ccp.cc (bit_value_binop): Zero extend r1max from width
- before calling wi::udiv_trunc.
- * lto-streamer-out.cc (output_cfg): Adjustments for the widest_int to
- bound_wide_int type change in non-static data members.
- * lto-streamer-in.cc (input_cfg): Likewise.
- (lto_input_tree_1): Use WIDE_INT_MAX_INL_ELTS rather than
- WIDE_INT_MAX_ELTS. For length above WIDE_INT_MAX_INL_ELTS use
- XALLOCAVEC allocated buffer. Formatting fix.
- * data-streamer-in.cc (streamer_read_wide_int,
- streamer_read_widest_int): Likewise.
- * tree-affine.cc (aff_combination_expand): Use placement new to
- construct name_expansion.
- (free_name_expansion): Destruct name_expansion.
- * gimple-ssa-strength-reduction.cc (struct slsr_cand_d): Change
- index type from widest_int to offset_int.
- (class incr_info_d): Change incr type from widest_int to offset_int.
- (alloc_cand_and_find_basis, backtrace_base_for_ref,
- restructure_reference, slsr_process_ref, create_mul_ssa_cand,
- create_mul_imm_cand, create_add_ssa_cand, create_add_imm_cand,
- slsr_process_add, cand_abs_increment, replace_mult_candidate,
- replace_unconditional_candidate, incr_vec_index,
- create_add_on_incoming_edge, create_phi_basis_1,
- replace_conditional_candidate, record_increment,
- record_phi_increments_1, phi_incr_cost_1, phi_incr_cost,
- lowest_cost_path, total_savings, ncd_with_phi, ncd_of_cand_and_phis,
- nearest_common_dominator_for_cands, insert_initializers,
- all_phi_incrs_profitable_1, replace_one_candidate,
- replace_profitable_candidates): Use offset_int rather than widest_int
- and wi::to_offset rather than wi::to_widest.
- * real.cc (real_to_integer): Use WIDE_INT_MAX_INL_ELTS rather than
- 2 * WIDE_INT_MAX_ELTS and for words above that use XALLOCAVEC
- allocated buffer.
- * tree-ssa-loop-ivopts.cc (niter_for_exit): Use placement new
- to construct tree_niter_desc and destruct it on failure.
- (free_tree_niter_desc): Destruct tree_niter_desc if value is non-NULL.
- * gengtype.cc (main): Remove widest_int handling.
- * graphite-isl-ast-to-gimple.cc (widest_int_from_isl_expr_int): Use
- WIDEST_INT_MAX_ELTS instead of WIDE_INT_MAX_ELTS.
- * gimple-ssa-warn-alloca.cc (pass_walloca::execute): Use
- WIDE_INT_MAX_INL_PRECISION instead of WIDE_INT_MAX_PRECISION and
- assert get_len () fits into it.
- * value-range-pretty-print.cc (vrange_printer::print_irange_bitmasks):
- For mask or value lengths above WIDE_INT_MAX_INL_ELTS use XALLOCAVEC
- allocated buffer.
- * gimple-ssa-sprintf.cc (adjust_range_for_overflow): Use
- wide_int::from on wi::to_wide instead of wi::to_widest.
- * omp-general.cc (score_wide_int): New typedef.
- (omp_context_compute_score): Use score_wide_int instead of widest_int
- and adjust for those changes.
- (struct omp_declare_variant_entry): Change score and
- score_in_declare_simd_clone non-static data member type from widest_int
- to score_wide_int.
- (omp_resolve_late_declare_variant, omp_resolve_declare_variant): Use
- score_wide_int instead of widest_int and adjust for those changes.
- (omp_lto_output_declare_variant_alt): Likewise.
- (omp_lto_input_declare_variant_alt): Likewise.
- * godump.cc (go_output_typedef): Assert get_len () is smaller than
- WIDE_INT_MAX_INL_ELTS.
-
-2023-10-12 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lround<mode><v_i_l_ll_convert>2): New
- pattern for lround/lroundf.
- * config/riscv/riscv-protos.h (enum insn_type): New enum value.
- (expand_vec_lround): New func decl for expanding lround.
- * config/riscv/riscv-v.cc (expand_vec_lround): New func impl
- for expanding lround.
-
-2023-10-12 Jakub Jelinek <jakub@redhat.com>
-
- * dwarf2out.h (wide_int_ptr): Remove.
- (dw_wide_int_ptr): New typedef.
- (struct dw_val_node): Change type of val_wide from wide_int_ptr
- to dw_wide_int_ptr.
- (struct dw_wide_int): New type.
- (dw_wide_int::elt): New method.
- (dw_wide_int::operator ==): Likewise.
- * dwarf2out.cc (get_full_len): Change argument type to
- const dw_wide_int & from const wide_int &. Use CEIL. Call
- get_precision method instead of calling wi::get_precision.
- (alloc_dw_wide_int): New function.
- (add_AT_wide): Change w argument type to const wide_int_ref &
- from const wide_int &. Use alloc_dw_wide_int.
- (mem_loc_descriptor, loc_descriptor): Use alloc_dw_wide_int.
- (insert_wide_int): Change val argument type to const wide_int_ref &
- from const wide_int &.
- (add_const_value_attribute): Pass rtx_mode_t temporary directly to
- add_AT_wide instead of using a temporary variable.
-
-2023-10-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111764
- * tree-vect-loop.cc (check_reduction_path): Remove the attempt
- to allow x + x via special-casing of assigns.
-
-2023-10-12 Hu, Lin1 <lin1.hu@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Detect USER_MSR.
- * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_USER_MSR_SET): New.
- (OPTION_MASK_ISA2_USER_MSR_UNSET): Ditto.
- (ix86_handle_option): Handle -musermsr.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_USER_MSR.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for usermsr.
- * config.gcc: Add usermsrintrin.h
- * config/i386/cpuid.h (bit_USER_MSR): New.
- * config/i386/i386-builtin-types.def:
- Add DEF_FUNCTION_TYPE (VOID, UINT64, UINT64).
- * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins):
- Add __builtin_urdmsr and __builtin_uwrmsr.
- * config/i386/i386-builtins.h (ix86_builtins):
- Add IX86_BUILTIN_URDMSR and IX86_BUILTIN_UWRMSR.
- * config/i386/i386-c.cc (ix86_target_macros_internal):
- Define __USER_MSR__.
- * config/i386/i386-expand.cc (ix86_expand_builtin):
- Handle new builtins.
- * config/i386/i386-isa.def (USER_MSR): Add DEF_PTA(USER_MSR).
- * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
- Handle usermsr.
- * config/i386/i386.md (urdmsr): New define_insn.
- (uwrmsr): Ditto.
- * config/i386/i386.opt: Add option -musermsr.
- * config/i386/x86gprintrin.h: Include usermsrintrin.h
- * doc/extend.texi: Document usermsr.
- * doc/invoke.texi: Document -musermsr.
- * doc/sourcebuild.texi: Document target usermsr.
- * config/i386/usermsrintrin.h: New file.
-
-2023-10-12 Yang Yujie <yangyujie@loongson.cn>
-
- * config.gcc: Add loongarch-driver.h to tm_files.
- * config/loongarch/loongarch.h: Do not include loongarch-driver.h.
- * config/loongarch/t-loongarch: Append loongarch-multilib.h to $(GTM_H)
- instead of $(TM_H) for building generator programs.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/111367
- * config/rs6000/rs6000.md (stack_protect_setsi): Support prefixed
- instruction emission and incorporate to stack_protect_set<mode>.
- (stack_protect_setdi): Rename to ...
- (stack_protect_set<mode>): ... this, adjust constraint.
- (stack_protect_testsi): Support prefixed instruction emission and
- incorporate to stack_protect_test<mode>.
- (stack_protect_testdi): Rename to ...
- (stack_protect_test<mode>): ... this, adjust constraint.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_store): Consider generated
- VEC_PERM_EXPR stmt for VMAT_CONTIGUOUS_REVERSE in costing as
- vec_perm.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_model_store_cost): Remove.
- (vectorizable_store): Adjust the costing for the remaining memory
- access types VMAT_CONTIGUOUS{, _DOWN, _REVERSE}.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_model_store_cost): Assert it will never
- get VMAT_CONTIGUOUS_PERMUTE and remove VMAT_CONTIGUOUS_PERMUTE related
- handlings.
- (vectorizable_store): Adjust the cost handling on
- VMAT_CONTIGUOUS_PERMUTE without calling vect_model_store_cost.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_model_store_cost): Assert it will never
- get VMAT_LOAD_STORE_LANES.
- (vectorizable_store): Adjust the cost handling on VMAT_LOAD_STORE_LANES
- without calling vect_model_store_cost. Factor out new lambda function
- update_prologue_cost.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_model_store_cost): Assert it won't get
- VMAT_ELEMENTWISE and VMAT_STRIDED_SLP any more, and remove their
- related handlings.
- (vectorizable_store): Adjust the cost handling on VMAT_ELEMENTWISE
- and VMAT_STRIDED_SLP without calling vect_model_store_cost.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_store): Adjust costing on
- vectorizable_scan_store without calling vect_model_store_cost
- any more.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_model_store_cost): Assert it won't get
- VMAT_GATHER_SCATTER any more, remove VMAT_GATHER_SCATTER related
- handlings and the related parameter gs_info.
- (vect_build_scatter_store_calls): Add the handlings on costing with
- one more argument cost_vec.
- (vectorizable_store): Adjust the cost handling on VMAT_GATHER_SCATTER
- without calling vect_model_store_cost any more.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_store): Move and duplicate the call
- to vect_model_store_cost down to some different transform paths
- according to the handlings of different vect_memory_access_types
- or some special handling need.
-
-2023-10-12 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_store): Ensure the generated
- vector store for some case of VMAT_ELEMENTWISE is supported.
-
-2023-10-12 Mo, Zewei <zewei.mo@intel.com>
- Hu Lin1 <lin1.hu@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.cc (gen_push2): New function to emit push2
- and adjust cfa offset.
- (ix86_pro_and_epilogue_can_use_push2_pop2): New function to
- determine whether push2/pop2 can be used.
- (ix86_compute_frame_layout): Adjust preferred stack boundary
- and stack alignment needed for push2/pop2.
- (ix86_emit_save_regs): Emit push2 when available.
- (ix86_emit_restore_reg_using_pop2): New function to emit pop2
- and adjust cfa info.
- (ix86_emit_restore_regs_using_pop2): New function to loop
- through the saved regs and call above.
- (ix86_expand_epilogue): Call ix86_emit_restore_regs_using_pop2
- when push2pop2 available.
- * config/i386/i386.md (push2_di): New pattern for push2.
- (pop2_di): Likewise for pop2.
-
-2023-10-12 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lrint<mode><vlconvert>2): Rename from.
- (lrint<mode><v_i_l_ll_convert>2): Rename to.
- * config/riscv/vector-iterators.md: Rename and remove TARGET_64BIT.
-
-2023-10-11 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-opts.h (TARGET_MIN_VLEN_OPTS): New.
-
-2023-10-11 Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/riscv.md (jump): Adjust sequence to use a "jump"
- pseudo op instead of a "call" pseudo op.
-
-2023-10-11 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-subset.h (riscv_subset_list::parse_single_std_ext):
- New.
- (riscv_subset_list::parse_single_multiletter_ext): Ditto.
- (riscv_subset_list::clone): Ditto.
- (riscv_subset_list::parse_single_ext): Ditto.
- (riscv_subset_list::set_loc): Ditto.
- (riscv_set_arch_by_subset_list): Ditto.
- * common/config/riscv/riscv-common.cc
- (riscv_subset_list::parse_single_std_ext): New.
- (riscv_subset_list::parse_single_multiletter_ext): Ditto.
- (riscv_subset_list::clone): Ditto.
- (riscv_subset_list::parse_single_ext): Ditto.
- (riscv_subset_list::set_loc): Ditto.
- (riscv_set_arch_by_subset_list): Ditto.
-
-2023-10-11 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting
- from argument rather than get setting from global setting.
- (riscv_override_options_internal): New, splited from
- riscv_override_options, also take a gcc_options argument.
- (riscv_option_override): Splited most part to
- riscv_override_options_internal.
-
-2023-10-11 Kito Cheng <kito.cheng@sifive.com>
-
- * doc/options.texi (Mask): Document TARGET_<NAME>_P and
- TARGET_<NAME>_OPTS_P.
- (InverseMask): Ditto.
- * opth-gen.awk (Mask): Generate TARGET_<NAME>_P and
- TARGET_<NAME>_OPTS_P macro.
- (InverseMask): Ditto.
-
-2023-10-11 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/111282
- * match.pd (`a & ~(a ^ b)`, `a & (a == b)`,
- `a & ((~a) ^ b)`): New patterns.
-
-2023-10-11 Mary Bennett <mary.bennett@embecosm.com>
-
- * common/config/riscv/riscv-common.cc: Add the XCValu
- extension.
- * config/riscv/constraints.md: Add builtins for the XCValu
- extension.
- * config/riscv/predicates.md (immediate_register_operand):
- Likewise.
- * config/riscv/corev.def: Likewise.
- * config/riscv/corev.md: Likewise.
- * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
- (RISCV_ATYPE_UHI): Likewise.
- * config/riscv/riscv-ftypes.def: Likewise.
- * config/riscv/riscv.opt: Likewise.
- * config/riscv/riscv.cc (riscv_print_operand): Likewise.
- * doc/extend.texi: Add XCValu documentation.
- * doc/sourcebuild.texi: Likewise.
-
-2023-10-11 Mary Bennett <mary.bennett@embecosm.com>
-
- * common/config/riscv/riscv-common.cc: Add XCVmac.
- * config/riscv/riscv-ftypes.def: Add XCVmac builtins.
- * config/riscv/riscv-builtins.cc: Likewise.
- * config/riscv/riscv.md: Likewise.
- * config/riscv/riscv.opt: Likewise.
- * doc/extend.texi: Add XCVmac builtin documentation.
- * doc/sourcebuild.texi: Likewise.
- * config/riscv/corev.def: New file.
- * config/riscv/corev.md: New file.
-
-2023-10-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Fix index bug.
- * config/riscv/riscv-protos.h (gather_scatter_valid_offset_mode_p): New function.
- * config/riscv/riscv-v.cc (expand_gather_scatter): Fix index bug.
- (gather_scatter_valid_offset_mode_p): New function.
-
-2023-10-11 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lrint<mode><vlconvert>2): New pattern
- for lrint/lintf.
- * config/riscv/riscv-protos.h (expand_vec_lrint): New func decl
- for expanding lint.
- * config/riscv/riscv-v.cc (emit_vec_cvt_x_f): New helper func impl
- for vfcvt.x.f.v.
- (expand_vec_lrint): New function impl for expanding lint.
- * config/riscv/vector-iterators.md: New mode attr and iterator.
-
-2023-10-11 Richard Biener <rguenther@suse.de>
- Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/111519
- * tree-ssa-strlen.cc (strlen_pass::count_nonzero_bytes): Add vuse
- argument and pass it through to recursive calls and
- count_nonzero_bytes_addr calls. Don't shadow the stmt argument, but
- change stmt for gimple_assign_single_p statements for which we don't
- immediately punt.
- (strlen_pass::count_nonzero_bytes_addr): Add vuse argument and pass
- it through to recursive calls and count_nonzero_bytes calls. Don't
- use get_strinfo if gimple_vuse (stmt) is different from vuse. Don't
- shadow the stmt argument.
-
-2023-10-11 Roger Sayle <roger@nextmovesoftware.com>
-
- PR middle-end/101955
- PR tree-optimization/106245
- * simplify-rtx.cc (simplify_relational_operation_1): Simplify
- the RTL (ne:SI (subreg:QI (ashift:SI x 7) 0) 0) to (and:SI x 1).
-
-2023-10-11 liuhongt <hongtao.liu@intel.com>
-
- PR target/111745
- * config/i386/mmx.md (divv4hf3): Refine predicate of
- operands[2] with register_operand.
-
-2023-10-10 Andrew Waterman <andrew@sifive.com>
- Philipp Tomsich <philipp.tomsich@vrull.eu>
- Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/riscv.cc (struct machine_function): Track if a
- far-branch/jump is used within a function (and $ra needs to be
- saved).
- (riscv_print_operand): Implement 'N' (inverse integer branch).
- (riscv_far_jump_used_p): Implement.
- (riscv_save_return_addr_reg_p): New function.
- (riscv_save_reg_p): Use riscv_save_return_addr_reg_p.
- * config/riscv/riscv.h (FIXED_REGISTERS): Update $ra.
- (CALL_USED_REGISTERS): Update $ra.
- * config/riscv/riscv.md: Add new types "ret" and "jalr".
- (length attribute): Handle long conditional and unconditional
- branches.
- (conditional branch pattern): Handle case where jump can not
- reach the intended target.
- (indirect_jump, tablejump): Use new "jalr" type.
- (simple_return): Use new "ret" type.
- (simple_return_internal, eh_return_internal): Likewise.
- (gpr_restore_return, riscv_mret): Likewise.
- (riscv_uret, riscv_sret): Likewise.
- * config/riscv/generic.md (generic_branch): Also recognize jalr & ret
- types.
- * config/riscv/sifive-7.md (sifive_7_jump): Likewise.
-
-2023-10-10 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/111679
- * match.pd (`a | ((~a) ^ b)`): New pattern.
-
-2023-10-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111751
- * config/riscv/autovec.md: Add VLS BOOL modes.
-
-2023-10-10 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111751
- * fold-const.cc (fold_view_convert_expr): Up the buffer size
- to 128 bytes.
- * tree-ssa-sccvn.cc (visit_reference_op_load): Special case
- constants, giving up when re-interpretation to the target type
- fails.
-
-2023-10-10 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111751
- * tree-ssa-sccvn.cc (visit_reference_op_load): Exempt
- BLKmode result from the padding bits check.
-
-2023-10-10 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc.cc (arc_select_cc_mode): Match NEG code with
- the first operand.
- * config/arc/arc.md (addsi_compare): Make pattern canonical.
- (addsi_compare_2): Fix identation, constraint letters.
- (addsi_compare_3): Likewise.
-
-2023-10-09 Eugene Rozenfeld <erozen@microsoft.com>
-
- * auto-profile.cc (afdo_calculate_branch_prob): Fix count comparisons
- * tree-vect-loop-manip.cc (vect_do_peeling): Guard against zero count
- when scaling loop profile
-
-2023-10-09 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/111694
- * gimple-range-cache.cc (ranger_cache::fill_block_cache): Adjust
- equivalence range.
- * value-relation.cc (adjust_equivalence_range): New.
- * value-relation.h (adjust_equivalence_range): New prototype.
-
-2023-10-09 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (gori_compute::compute_operand1_range): Do
- not call get_identity_relation.
- (gori_compute::compute_operand2_range): Ditto.
- * value-relation.cc (get_identity_relation): Remove.
- * value-relation.h (get_identity_relation): Remove protyotype.
-
-2023-10-09 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
- * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
- Add generic_ooo.
- * config/riscv/riscv.cc (riscv_sched_adjust_cost): Implement
- scheduler hook.
- (TARGET_SCHED_ADJUST_COST): Define.
- * config/riscv/riscv.md (no,yes"): Include generic-ooo.md
- * config/riscv/riscv.opt: Add -madjust-lmul-cost.
- * config/riscv/generic-ooo.md: New file.
- * config/riscv/vector.md: Add vsetvl_pre.
-
-2023-10-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-opts.h (TARGET_VECTOR_MISALIGN_SUPPORTED): New macro.
- * config/riscv/riscv.cc (riscv_support_vector_misalignment): Depend on movmisalign pattern.
- * config/riscv/vector.md (movmisalign<mode>): New pattern.
-
-2023-10-09 Xianmiao Qu <cooper.qu@linux.alibaba.com>
-
- * config/riscv/thead.cc (th_mempair_save_regs): Fix missing CFI
- directives for store-pair instruction.
-
-2023-10-09 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111715
- * alias.cc (reference_alias_ptr_type_1): When we have
- a type-punning ref at the base search for the access
- path part that's still semantically valid.
-
-2023-10-09 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (shuffle_bswap_pattern): New func impl
- for shuffle bswap.
- (expand_vec_perm_const_1): Add handling for shuffle bswap pattern.
-
-2023-10-09 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_split_ashr): Split shifts by
- one into ashr[sd]i3_carry followed by rcr[sd]i2, if TARGET_USE_RCR
- or -Oz.
- (ix86_split_lshr): Likewise, split shifts by one bit into
- lshr[sd]i3_carry followed by rcr[sd]i2, if TARGET_USE_RCR or -Oz.
- * config/i386/i386.h (TARGET_USE_RCR): New backend macro.
- * config/i386/i386.md (rcrsi2): New define_insn for rcrl.
- (rcrdi2): New define_insn for rcrq.
- (<anyshiftrt><mode>3_carry): New define_insn for right shifts that
- set the carry flag from the least significant bit, modelled using
- UNSPEC_CC_NE.
- * config/i386/x86-tune.def (X86_TUNE_USE_RCR): New tuning parameter
- controlling use of rcr 1 vs. shrd, which is significantly faster on
- AMD processors.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386.opt: Allow -mno-evex512.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
- Hu, Lin1 <lin1.hu@intel.com>
-
- * config/i386/sse.md (V48H_AVX512VL): Add TARGET_EVEX512.
- (VFH): Ditto.
- (VF2H): Ditto.
- (VFH_AVX512VL): Ditto.
- (VHFBF): Ditto.
- (VHF_AVX512VL): Ditto.
- (VI2H_AVX512VL): Ditto.
- (VI2F_256_512): Ditto.
- (VF48_I1248): Remove unused iterator.
- (VF48H_AVX512VL): Add TARGET_EVEX512.
- (VF_AVX512): Remove unused iterator.
- (REDUC_PLUS_MODE): Add TARGET_EVEX512.
- (REDUC_SMINMAX_MODE): Ditto.
- (FMAMODEM): Ditto.
- (VFH_SF_AVX512VL): Ditto.
- (VEC_PERM_AVX2): Ditto.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
- Hu, Lin1 <lin1.hu@intel.com>
-
- * config/i386/sse.md (VI1_AVX512VL): Add TARGET_EVEX512.
- (VI8_FVL): Ditto.
- (VI1_AVX512F): Ditto.
- (VI1_AVX512VNNI): Ditto.
- (VI1_AVX512VL_F): Ditto.
- (VI12_VI48F_AVX512VL): Ditto.
- (*avx512f_permvar_truncv32hiv32qi_1): Ditto.
- (sdot_prod<mode>): Ditto.
- (VEC_PERM_AVX2): Ditto.
- (VPERMI2): Ditto.
- (VPERMI2I): Ditto.
- (vpmadd52<vpmadd52type>v8di): Ditto.
- (usdot_prod<mode>): Ditto.
- (vpdpbusd_v16si): Ditto.
- (vpdpbusds_v16si): Ditto.
- (vpdpwssd_v16si): Ditto.
- (vpdpwssds_v16si): Ditto.
- (VI48_AVX512VP2VL): Ditto.
- (avx512vp2intersect_2intersectv16si): Ditto.
- (VF_AVX512BF16VL): Ditto.
- (VF1_AVX512_256): Ditto.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate):
- Make sure there is EVEX512 enabled.
- (ix86_expand_vecop_qihi2): Refuse V32QI->V32HI when no EVEX512.
- * config/i386/i386.cc (ix86_hard_regno_mode_ok): Disable 64 bit mask
- when !TARGET_EVEX512.
- * config/i386/i386.md (avx512bw_512): New.
- (SWI1248_AVX512BWDQ_64): Add TARGET_EVEX512.
- (*zero_extendsidi2): Change isa to avx512bw_512.
- (kmov_isa): Ditto.
- (*anddi_1): Ditto.
- (*andn<mode>_1): Change isa to kmov_isa.
- (*<code><mode>_1): Ditto.
- (*notxor<mode>_1): Ditto.
- (*one_cmpl<mode>2_1): Ditto.
- (*one_cmplsi2_1_zext): Change isa to avx512bw_512.
- (*ashl<mode>3_1): Change isa to kmov_isa.
- (*lshr<mode>3_1): Ditto.
- * config/i386/sse.md (VI12HFBF_AVX512VL): Add TARGET_EVEX512.
- (VI1248_AVX512VLBW): Ditto.
- (VHFBF_AVX512VL): Ditto.
- (VI): Ditto.
- (VIHFBF): Ditto.
- (VI_AVX2): Ditto.
- (VI1_AVX512): Ditto.
- (VI12_256_512_AVX512VL): Ditto.
- (VI2_AVX2_AVX512BW): Ditto.
- (VI2_AVX512VNNIBW): Ditto.
- (VI2_AVX512VL): Ditto.
- (VI2HFBF_AVX512VL): Ditto.
- (VI8_AVX2_AVX512BW): Ditto.
- (VIMAX_AVX2_AVX512BW): Ditto.
- (VIMAX_AVX512VL): Ditto.
- (VI12_AVX2_AVX512BW): Ditto.
- (VI124_AVX2_24_AVX512F_1_AVX512BW): Ditto.
- (VI248_AVX512VL): Ditto.
- (VI248_AVX512VLBW): Ditto.
- (VI248_AVX2_8_AVX512F_24_AVX512BW): Ditto.
- (VI248_AVX512BW): Ditto.
- (VI248_AVX512BW_AVX512VL): Ditto.
- (VI248_512): Ditto.
- (VI124_256_AVX512F_AVX512BW): Ditto.
- (VI_AVX512BW): Ditto.
- (VIHFBF_AVX512BW): Ditto.
- (SWI1248_AVX512BWDQ): Ditto.
- (SWI1248_AVX512BW): Ditto.
- (SWI1248_AVX512BWDQ2): Ditto.
- (*knotsi_1_zext): Ditto.
- (define_split for zero_extend + not): Ditto.
- (kunpckdi): Ditto.
- (REDUC_SMINMAX_MODE): Ditto.
- (VEC_EXTRACT_MODE): Ditto.
- (*avx512bw_permvar_truncv16siv16hi_1): Ditto.
- (*avx512bw_permvar_truncv16siv16hi_1_hf): Ditto.
- (truncv32hiv32qi2): Ditto.
- (avx512bw_<code>v32hiv32qi2): Ditto.
- (avx512bw_<code>v32hiv32qi2_mask): Ditto.
- (avx512bw_<code>v32hiv32qi2_mask_store): Ditto.
- (usadv64qi): Ditto.
- (VEC_PERM_AVX2): Ditto.
- (AVX512ZEXTMASK): Ditto.
- (SWI24_MASK): New.
- (vec_pack_trunc_<mode>): Change iterator to SWI24_MASK.
- (avx512bw_packsswb<mask_name>): Add TARGET_EVEX512.
- (avx512bw_packssdw<mask_name>): Ditto.
- (avx512bw_interleave_highv64qi<mask_name>): Ditto.
- (avx512bw_interleave_lowv64qi<mask_name>): Ditto.
- (<mask_codefor>avx512bw_pshuflwv32hi<mask_name>): Ditto.
- (<mask_codefor>avx512bw_pshufhwv32hi<mask_name>): Ditto.
- (vec_unpacks_lo_di): Ditto.
- (SWI48x_MASK): New.
- (vec_unpacks_hi_<mode>): Change iterator to SWI48x_MASK.
- (avx512bw_umulhrswv32hi3<mask_name>): Add TARGET_EVEX512.
- (VI1248_AVX512VL_AVX512BW): Ditto.
- (avx512bw_<code>v32qiv32hi2<mask_name>): Ditto.
- (*avx512bw_zero_extendv32qiv32hi2_1): Ditto.
- (*avx512bw_zero_extendv32qiv32hi2_2): Ditto.
- (<insn>v32qiv32hi2): Ditto.
- (pbroadcast_evex_isa): Change isa attribute to avx512bw_512.
- (VPERMI2): Add TARGET_EVEX512.
- (VPERMI2I): Ditto.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-expand.cc (ix86_expand_sse2_mulvxdi3):
- Add TARGET_EVEX512 for 512 bit usage.
- * config/i386/i386.cc (standard_sse_constant_opcode): Ditto.
- * config/i386/sse.md (VF1_VF2_AVX512DQ): Ditto.
- (VF1_128_256VL): Ditto.
- (VF2_AVX512VL): Ditto.
- (VI8_256_512): Ditto.
- (<mask_codefor>fixuns_trunc<mode><sseintvecmodelower>2<mask_name>):
- Ditto.
- (AVX512_VEC): Ditto.
- (AVX512_VEC_2): Ditto.
- (VI4F_BRCST32x2): Ditto.
- (VI8F_BRCST64x2): Ditto.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-builtins.cc
- (ix86_vectorize_builtin_gather): Disable 512 bit gather
- when !TARGET_EVEX512.
- * config/i386/i386-expand.cc (ix86_valid_mask_cmp_mode):
- Add TARGET_EVEX512.
- (ix86_expand_int_sse_cmp): Ditto.
- (ix86_expand_vector_init_one_nonzero): Disable subroutine
- when !TARGET_EVEX512.
- (ix86_emit_swsqrtsf): Add TARGET_EVEX512.
- (ix86_vectorize_vec_perm_const): Disable subroutine when
- !TARGET_EVEX512.
- * config/i386/i386.cc
- (standard_sse_constant_p): Add TARGET_EVEX512.
- (standard_sse_constant_opcode): Ditto.
- (ix86_get_ssemov): Ditto.
- (ix86_legitimate_constant_p): Ditto.
- (ix86_vectorize_builtin_scatter): Diable 512 bit scatter
- when !TARGET_EVEX512.
- * config/i386/i386.md (avx512f_512): New.
- (movxi): Add TARGET_EVEX512.
- (*movxi_internal_avx512f): Ditto.
- (*movdi_internal): Change alternative 12 to ?Yv. Adjust mode
- for alternative 13.
- (*movsi_internal): Change alternative 8 to ?Yv. Adjust mode for
- alternative 9.
- (*movhi_internal): Change alternative 11 to *Yv.
- (*movdf_internal): Change alternative 12 to Yv.
- (*movsf_internal): Change alternative 5 to Yv. Adjust mode for
- alternative 5 and 6.
- (*mov<mode>_internal): Change alternative 4 to Yv.
- (define_split for convert SF to DF): Add TARGET_EVEX512.
- (extendbfsf2_1): Ditto.
- * config/i386/predicates.md (bcst_mem_operand): Disable predicate
- for 512 bit when !TARGET_EVEX512.
- * config/i386/sse.md (VMOVE): Add TARGET_EVEX512.
- (V48_AVX512VL): Ditto.
- (V48_256_512_AVX512VL): Ditto.
- (V48H_AVX512VL): Ditto.
- (VI12_AVX512VL): Ditto.
- (V): Ditto.
- (V_512): Ditto.
- (V_256_512): Ditto.
- (VF): Ditto.
- (VF1_VF2_AVX512DQ): Ditto.
- (VFH): Ditto.
- (VFB): Ditto.
- (VF1): Ditto.
- (VF1_AVX2): Ditto.
- (VF2): Ditto.
- (VF2H): Ditto.
- (VF2_512_256): Ditto.
- (VF2_512_256VL): Ditto.
- (VF_512): Ditto.
- (VFB_512): Ditto.
- (VI48_AVX512VL): Ditto.
- (VI1248_AVX512VLBW): Ditto.
- (VF_AVX512VL): Ditto.
- (VFH_AVX512VL): Ditto.
- (VF1_AVX512VL): Ditto.
- (VI): Ditto.
- (VIHFBF): Ditto.
- (VI_AVX2): Ditto.
- (VI8): Ditto.
- (VI8_AVX512VL): Ditto.
- (VI2_AVX512F): Ditto.
- (VI4_AVX512F): Ditto.
- (VI4_AVX512VL): Ditto.
- (VI48_AVX512F_AVX512VL): Ditto.
- (VI8_AVX2_AVX512F): Ditto.
- (VI8_AVX_AVX512F): Ditto.
- (V8FI): Ditto.
- (V16FI): Ditto.
- (VI124_AVX2_24_AVX512F_1_AVX512BW): Ditto.
- (VI248_AVX512VLBW): Ditto.
- (VI248_AVX2_8_AVX512F_24_AVX512BW): Ditto.
- (VI248_AVX512BW): Ditto.
- (VI248_AVX512BW_AVX512VL): Ditto.
- (VI48_AVX512F): Ditto.
- (VI48_AVX_AVX512F): Ditto.
- (VI12_AVX_AVX512F): Ditto.
- (VI148_512): Ditto.
- (VI124_256_AVX512F_AVX512BW): Ditto.
- (VI48_512): Ditto.
- (VI_AVX512BW): Ditto.
- (VIHFBF_AVX512BW): Ditto.
- (VI4F_256_512): Ditto.
- (VI48F_256_512): Ditto.
- (VI48F): Ditto.
- (VI12_VI48F_AVX512VL): Ditto.
- (V32_512): Ditto.
- (AVX512MODE2P): Ditto.
- (STORENT_MODE): Ditto.
- (REDUC_PLUS_MODE): Ditto.
- (REDUC_SMINMAX_MODE): Ditto.
- (*andnot<mode>3): Change isa attribute to avx512f_512.
- (*andnot<mode>3): Ditto.
- (<code><mode>3): Ditto.
- (<code>tf3): Ditto.
- (FMAMODEM): Add TARGET_EVEX512.
- (FMAMODE_AVX512): Ditto.
- (VFH_SF_AVX512VL): Ditto.
- (avx512f_fix_notruncv16sfv16si<mask_name><round_name>): Ditto.
- (fix<fixunssuffix>_truncv16sfv16si2<mask_name><round_saeonly_name>):
- Ditto.
- (avx512f_cvtdq2pd512_2): Ditto.
- (avx512f_cvtpd2dq512<mask_name><round_name>): Ditto.
- (fix<fixunssuffix>_truncv8dfv8si2<mask_name><round_saeonly_name>):
- Ditto.
- (<mask_codefor>avx512f_cvtpd2ps512<mask_name><round_name>): Ditto.
- (vec_unpacks_lo_v16sf): Ditto.
- (vec_unpacks_hi_v16sf): Ditto.
- (vec_unpacks_float_hi_v16si): Ditto.
- (vec_unpacks_float_lo_v16si): Ditto.
- (vec_unpacku_float_hi_v16si): Ditto.
- (vec_unpacku_float_lo_v16si): Ditto.
- (vec_pack_sfix_trunc_v8df): Ditto.
- (avx512f_vec_pack_sfix_v8df): Ditto.
- (<mask_codefor>avx512f_unpckhps512<mask_name>): Ditto.
- (<mask_codefor>avx512f_unpcklps512<mask_name>): Ditto.
- (<mask_codefor>avx512f_movshdup512<mask_name>): Ditto.
- (<mask_codefor>avx512f_movsldup512<mask_name>): Ditto.
- (AVX512_VEC): Ditto.
- (AVX512_VEC_2): Ditto.
- (vec_extract_lo_v64qi): Ditto.
- (vec_extract_hi_v64qi): Ditto.
- (VEC_EXTRACT_MODE): Ditto.
- (<mask_codefor>avx512f_unpckhpd512<mask_name>): Ditto.
- (avx512f_movddup512<mask_name>): Ditto.
- (avx512f_unpcklpd512<mask_name>): Ditto.
- (*<avx512>_vternlog<mode>_all): Ditto.
- (*<avx512>_vpternlog<mode>_1): Ditto.
- (*<avx512>_vpternlog<mode>_2): Ditto.
- (*<avx512>_vpternlog<mode>_3): Ditto.
- (avx512f_shufps512_mask): Ditto.
- (avx512f_shufps512_1<mask_name>): Ditto.
- (avx512f_shufpd512_mask): Ditto.
- (avx512f_shufpd512_1<mask_name>): Ditto.
- (<mask_codefor>avx512f_interleave_highv8di<mask_name>): Ditto.
- (<mask_codefor>avx512f_interleave_lowv8di<mask_name>): Ditto.
- (vec_dupv2df<mask_name>): Ditto.
- (trunc<pmov_src_lower><mode>2): Ditto.
- (*avx512f_<code><pmov_src_lower><mode>2): Ditto.
- (*avx512f_vpermvar_truncv8div8si_1): Ditto.
- (avx512f_<code><pmov_src_lower><mode>2_mask): Ditto.
- (avx512f_<code><pmov_src_lower><mode>2_mask_store): Ditto.
- (truncv8div8qi2): Ditto.
- (avx512f_<code>v8div16qi2): Ditto.
- (*avx512f_<code>v8div16qi2_store_1): Ditto.
- (*avx512f_<code>v8div16qi2_store_2): Ditto.
- (avx512f_<code>v8div16qi2_mask): Ditto.
- (*avx512f_<code>v8div16qi2_mask_1): Ditto.
- (*avx512f_<code>v8div16qi2_mask_store_1): Ditto.
- (avx512f_<code>v8div16qi2_mask_store_2): Ditto.
- (vec_widen_umult_even_v16si<mask_name>): Ditto.
- (*vec_widen_umult_even_v16si<mask_name>): Ditto.
- (vec_widen_smult_even_v16si<mask_name>): Ditto.
- (*vec_widen_smult_even_v16si<mask_name>): Ditto.
- (VEC_PERM_AVX2): Ditto.
- (one_cmpl<mode>2): Ditto.
- (<mask_codefor>one_cmpl<mode>2<mask_name>): Ditto.
- (*one_cmpl<mode>2_pternlog_false_dep): Ditto.
- (define_split to xor): Ditto.
- (*andnot<mode>3): Ditto.
- (define_split for ior): Ditto.
- (*iornot<mode>3): Ditto.
- (*xnor<mode>3): Ditto.
- (*<nlogic><mode>3): Ditto.
- (<mask_codefor>avx512f_interleave_highv16si<mask_name>): Ditto.
- (<mask_codefor>avx512f_interleave_lowv16si<mask_name>): Ditto.
- (avx512f_pshufdv3_mask): Ditto.
- (avx512f_pshufd_1<mask_name>): Ditto.
- (*vec_extractv4ti): Ditto.
- (VEXTRACTI128_MODE): Ditto.
- (define_split to vec_extract): Ditto.
- (VI1248_AVX512VL_AVX512BW): Ditto.
- (<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>): Ditto.
- (<insn>v16qiv16si2): Ditto.
- (avx512f_<code>v16hiv16si2<mask_name>): Ditto.
- (<insn>v16hiv16si2): Ditto.
- (avx512f_zero_extendv16hiv16si2_1): Ditto.
- (avx512f_<code>v8qiv8di2<mask_name>): Ditto.
- (*avx512f_<code>v8qiv8di2<mask_name>_1): Ditto.
- (*avx512f_<code>v8qiv8di2<mask_name>_2): Ditto.
- (<insn>v8qiv8di2): Ditto.
- (avx512f_<code>v8hiv8di2<mask_name>): Ditto.
- (<insn>v8hiv8di2): Ditto.
- (avx512f_<code>v8siv8di2<mask_name>): Ditto.
- (*avx512f_zero_extendv8siv8di2_1): Ditto.
- (*avx512f_zero_extendv8siv8di2_2): Ditto.
- (<insn>v8siv8di2): Ditto.
- (avx512f_roundps512_sfix): Ditto.
- (vashrv8di3): Ditto.
- (vashrv16si3): Ditto.
- (pbroadcast_evex_isa): Change isa attribute to avx512f_512.
- (vec_dupv4sf): Add TARGET_EVEX512.
- (*vec_dupv4si): Ditto.
- (*vec_dupv2di): Ditto.
- (vec_dup<mode>): Change isa attribute to avx512f_512.
- (VPERMI2): Add TARGET_EVEX512.
- (VPERMI2I): Ditto.
- (VEC_INIT_MODE): Ditto.
- (VEC_INIT_HALF_MODE): Ditto.
- (<mask_codefor>avx512f_vcvtph2ps512<mask_name><round_saeonly_name>):
- Ditto.
- (avx512f_vcvtps2ph512_mask_sae): Ditto.
- (<mask_codefor>avx512f_vcvtps2ph512<mask_name><round_saeonly_name>):
- Ditto.
- (*avx512f_vcvtps2ph512<merge_mask_name>): Ditto.
- (INT_BROADCAST_MODE): Ditto.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-expand.cc (ix86_broadcast_from_constant):
- Disable zmm broadcast for !TARGET_EVEX512.
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Do not use PVW_512 when no-evex512.
- (ix86_simd_clone_adjust): Add evex512 target into string.
- * config/i386/i386.cc (type_natural_mode): Report ABI warning
- when using zmm register w/o evex512.
- (ix86_return_in_memory): Do not allow zmm when !TARGET_EVEX512.
- (ix86_hard_regno_mode_ok): Ditto.
- (ix86_set_reg_reg_cost): Ditto.
- (ix86_rtx_costs): Ditto.
- (ix86_vector_mode_supported_p): Ditto.
- (ix86_preferred_simd_mode): Ditto.
- (ix86_get_mask_mode): Ditto.
- (ix86_simd_clone_compute_vecsize_and_simdlen): Disable 512 bit
- libmvec call when !TARGET_EVEX512.
- (ix86_simd_clone_usable): Ditto.
- * config/i386/i386.h (BIGGEST_ALIGNMENT): Disable 512 alignment
- when !TARGET_EVEX512
- (MOVE_MAX): Do not use PVW_512 when !TARGET_EVEX512.
- (STORE_MAX_PIECES): Ditto.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-builtin.def (BDESC): Add
- OPTION_MASK_ISA2_EVEX512.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-builtin.def (BDESC): Add
- OPTION_MASK_ISA2_EVEX512.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-builtin.def (BDESC): Add
- OPTION_MASK_ISA2_EVEX512.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-builtin.def (BDESC): Add
- OPTION_MASK_ISA2_EVEX512.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-builtin.def (BDESC): Add
- OPTION_MASK_ISA2_EVEX512.
- * config/i386/i386-builtins.cc
- (ix86_init_mmx_sse_builtins): Ditto.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
- Hu, Lin1 <lin1.hu@intel.com>
-
- * config/i386/avx512fp16intrin.h: Add evex512 target for 512 bit
- intrins.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config.gcc: Add avx512bitalgvlintrin.h.
- * config/i386/avx5124fmapsintrin.h: Add evex512 target for 512 bit
- intrins.
- * config/i386/avx5124vnniwintrin.h: Ditto.
- * config/i386/avx512bf16intrin.h: Ditto.
- * config/i386/avx512bitalgintrin.h: Add evex512 target for 512 bit
- intrins. Split 128/256 bit intrins to avx512bitalgvlintrin.h.
- * config/i386/avx512erintrin.h: Add evex512 target for 512 bit
- intrins
- * config/i386/avx512ifmaintrin.h: Ditto
- * config/i386/avx512pfintrin.h: Ditto
- * config/i386/avx512vbmi2intrin.h: Ditto.
- * config/i386/avx512vbmiintrin.h: Ditto.
- * config/i386/avx512vnniintrin.h: Ditto.
- * config/i386/avx512vp2intersectintrin.h: Ditto.
- * config/i386/avx512vpopcntdqintrin.h: Ditto.
- * config/i386/gfniintrin.h: Ditto.
- * config/i386/immintrin.h: Add avx512bitalgvlintrin.h.
- * config/i386/vaesintrin.h: Add evex512 target for 512 bit intrins.
- * config/i386/vpclmulqdqintrin.h: Ditto.
- * config/i386/avx512bitalgvlintrin.h: New.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512bwintrin.h: Add evex512 target for 512 bit
- intrins.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512dqintrin.h: Add evex512 target for 512 bit
- intrins.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512fintrin.h: Add evex512 target for 512 bit intrins.
-
-2023-10-09 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA2_EVEX512_SET): New.
- (OPTION_MASK_ISA2_EVEX512_UNSET): Ditto.
- (ix86_handle_option): Handle EVEX512.
- * config/i386/i386-c.cc
- (ix86_target_macros_internal): Handle EVEX512. Add __EVEX256__
- when AVX512VL is set.
- * config/i386/i386-options.cc: (isa2_opts): Handle EVEX512.
- (ix86_valid_target_attribute_inner_p): Ditto.
- (ix86_option_override_internal): Set EVEX512 target if it is not
- explicitly set when AVX512 is enabled. Disable
- AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512.
- * config/i386/i386.opt: Add mevex512. Temporaily RejectNegative.
-
-2023-10-09 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/88558
- * config/rs6000/rs6000.md (lrint<mode>di2): Remove TARGET_FPRND
- from insn condition.
- (lrint<mode>si2): New insn pattern for 32bit lrint.
-
-2023-10-09 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/88558
- * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
- Enable SImode on FP registers for P7.
- * config/rs6000/rs6000.md (*movsi_internal1): Add fmr for SImode
- move between FP registers. Set attribute isa of stfiwx to "*"
- and attribute of stxsiwx to "p7".
-
-2023-10-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.md: Make use of new copysign RTL.
-
-2023-10-09 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/sse.md (vec_concatv2di): Replace constraint "m"
- with "jm" for alternative 0 and 1 of operand 2.
- (sse4_1_<code><mode>3<mask_name>): Replace constraint "Bm" with
- "ja" for alternative 0 and 1 of operand2.
-
-2023-10-08 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/111155
- * text-art/table.cc (table::maybe_set_cell_span): New.
- (table::add_other_table): New.
- * text-art/table.h (class table::cell_placement): Add class table
- as a friend.
- (table::add_rows): New.
- (table::add_row): Reimplement in terms of add_rows.
- (table::maybe_set_cell_span): New decl.
- (table::add_other_table): New decl.
- * text-art/types.h (operator+): New operator for rect + coord.
-
-2023-10-08 David Malcolm <dmalcolm@redhat.com>
-
- * genmatch.cc (main): Update for "m_" prefix of some fields of
- line_maps.
- * input.cc (make_location): Update for removal of
- COMBINE_LOCATION_DATA.
- (dump_line_table_statistics): Update for "m_" prefix of some
- fields of line_maps.
- (location_with_discriminator): Update for removal of
- COMBINE_LOCATION_DATA.
- (line_table_test::line_table_test): Update for "m_" prefix of some
- fields of line_maps.
- * toplev.cc (general_init): Likewise.
- * tree.cc (set_block): Update for removal of
- COMBINE_LOCATION_DATA.
- (set_source_range): Likewise.
-
-2023-10-08 David Malcolm <dmalcolm@redhat.com>
-
- * input.cc (make_location): Move implementation to
- line_maps::make_location.
-
-2023-10-08 David Malcolm <dmalcolm@redhat.com>
-
- PR driver/111700
- * input.cc (file_cache::add_file): Update leading comment to
- clarify that it can fail.
- (file_cache::lookup_or_add_file): Likewise.
- (file_cache::get_source_file_content): Gracefully handle
- lookup_or_add_file failing.
-
-2023-10-08 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386.cc (ix86_build_const_vector): Handle V2HF
- and V4HFmode.
- (ix86_build_signbit_mask): Ditto.
- * config/i386/mmx.md (mmxintvecmode): Ditto.
- (<code><mode>2): New define_expand.
- (*mmx_<code><mode>): New define_insn_and_split.
- (*mmx_nabs<mode>2): Ditto.
- (*mmx_andnot<mode>3): New define_insn.
- (<code><mode>3): Ditto.
- (copysign<mode>3): New define_expand.
- (xorsign<mode>3): Ditto.
- (signbit<mode>2): Ditto.
-
-2023-10-08 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/mmx.md (VHF_32_64): New mode iterator.
- (<insn><mode>3): New define_expand, merged from ..
- (<insn>v4hf3): .. this and
- (<insn>v2hf3): .. this.
- (movd_v2hf_to_sse_reg): New define_expand, splitted from ..
- (movd_v2hf_to_sse): .. this.
- (<code><mode>3): New define_expand.
-
-2023-10-08 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (can_be_built_by_li_and_rldic): New function.
- (rs6000_emit_set_long_const): Call can_be_built_by_li_and_rldic.
-
-2023-10-08 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): New
- function.
- (can_be_built_by_li_lis_and_rldicr): New function.
- (rs6000_emit_set_long_const): Call can_be_built_by_li_lis_and_rldicr and
- can_be_built_by_li_lis_and_rldicl.
-
-2023-10-08 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (can_be_rotated_to_negative_lis): New
- function.
- (can_be_built_by_li_and_rotldi): Rename to ...
- (can_be_built_by_li_lis_and_rotldi): ... this function.
- (rs6000_emit_set_long_const): Call can_be_built_by_li_lis_and_rotldi.
-
-2023-10-08 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (can_be_built_by_li_and_rotldi): New function.
- (rs6000_emit_set_long_const): Call can_be_built_by_li_and_rotldi.
-
-2023-10-08 Yanzhang Wang <yanzhang.wang@intel.com>
-
- * config/riscv/linux.h: Pass the static-pie specific options to
- the linker.
-
-2023-10-07 Saurabh Jha <saurabh.jha@arm.com>
-
- * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add support for
- cortex-x4 core.
- * config/aarch64/aarch64-tune.md: Regenerated.
- * doc/invoke.texi: Add command-line option for cortex-x4 core.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/constraints.md (jb): New constraint for vsib memory
- that does not allow gpr32.
- * config/i386/i386.md: (setcc_<mode>_sse): Replace m to jm for avx
- alternative and set attr_gpr32 to 0.
- (movmsk_df): Split avx/noavx alternatives and replace "r" to "jr" for
- avx alternative.
- (<sse>_rcp<mode>2): Split avx/noavx alternatives and replace
- "m/Bm" to "jm/ja" for avx alternative, set its gpr32 attr to 0.
- (*rsqrtsf2_sse): Likewise.
- * config/i386/mmx.md (mmx_pmovmskb): Split alternative 1 to
- avx/noavx and assign jr/r constraint to dest.
- * config/i386/sse.md (<sse>_movmsk<ssemodesuffix><avxsizesuffix>):
- Split avx/noavx alternatives and replace "r" to "jr" for avx alternative.
- (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): Likewise.
- (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_lt): Likewise.
- (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): Likewise.
- (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_shift): Likewise.
- (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): Likewise.
- (<sse2_avx2>_pmovmskb): Likewise.
- (*<sse2_avx2>_pmovmskb_zext): Likewise.
- (*sse2_pmovmskb_ext): Likewise.
- (*<sse2_avx2>_pmovmskb_lt): Likewise.
- (*<sse2_avx2>_pmovmskb_zext_lt): Likewise.
- (*sse2_pmovmskb_ext_lt): Likewise.
- (<sse>_rcp<mode>2): Split avx/noavx alternatives and replace
- "m/Bm" to "jm/ja" for avx alternative, set its attr_gpr32 to 0.
- (sse_vmrcpv4sf2): Likewise.
- (*sse_vmrcpv4sf2): Likewise.
- (rsqrt<mode>2): Likewise.
- (sse_vmrsqrtv4sf2): Likewise.
- (*sse_vmrsqrtv4sf2): Likewise.
- (avx_h<insn>v4df3): Likewise.
- (sse3_hsubv2df3): Likewise.
- (avx_h<insn>v8sf3): Likewise.
- (sse3_h<insn>v4sf3): Likewise.
- (<sse3>_lddqu<avxsizesuffix>): Likewise.
- (avx_cmp<mode>3): Likewise.
- (avx_vmcmp<mode>3): Likewise.
- (*sse2_gt<mode>3): Likewise.
- (sse_ldmxcsr): Likewise.
- (sse_stmxcsr): Likewise.
- (avx_vtest<ssemodesuffix><avxsizesuffix>): Replace m to jm for
- avx alternative and set attr_gpr32 to 0.
- (avx2_permv2ti): Likewise.
- (*avx_vperm2f128<mode>_full): Likewise.
- (*avx_vperm2f128<mode>_nozero): Likewise.
- (vec_set_lo_v32qi): Likewise.
- (<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Likewise.
- (<avx_avx2>_maskstore<ssemodesuffix><avxsi)zesuffix>: Likewise.
- (avx_cmp<mode>3): Likewise.
- (avx_vmcmp<mode>3): Likewise.
- (*<sse>_maskcmp<mode>3_comm): Likewise.
- (*avx2_gathersi<VEC_GATHER_MODE:mode>): Replace Tv to jb and set
- attr_gpr32 to 0.
- (*avx2_gathersi<VEC_GATHER_MODE:mode>_2): Likewise.
- (*avx2_gatherdi<VEC_GATHER_MODE:mode>): Likewise.
- (*avx2_gatherdi<VEC_GATHER_MODE:mode>_2): Likewise.
- (*avx2_gatherdi<VI4F_256:mode>_3): Likewise.
- (*avx2_gatherdi<VI4F_256:mode>_4): Likewise.
- (avx_vbroadcastf128_<mode>): Restrict non-egpr alternative to
- noavx512vl, set its constraint to jm and set attr_gpr32 to 0.
- (vec_set_lo_<mode><mask_name>): Likewise.
- (vec_set_lo_<mode><mask_name>): Likewise for SF/SI modes.
- (vec_set_hi_<mode><mask_name>): Likewise.
- (vec_set_hi_<mode><mask_name>): Likewise for SF/SI modes.
- (vec_set_hi_<mode>): Likewise.
- (vec_set_lo_<mode>): Likewise.
- (avx2_set_hi_v32qi): Likewise.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/i386.md (*movhi_internal): Split out non-gpr
- supported pextrw with mem constraint to avx/noavx alternatives,
- set jm and attr gpr32 0 to the noavx alternative.
- (*mov<mode>_internal): Likewise.
- * config/i386/mmx.md (mmx_pshufbv8qi3): Change "r/m/Bm" to
- "jr/jm/ja" and set_attr gpr32 0 for noavx alternative.
- (mmx_pshufbv4qi3): Likewise.
- (*mmx_pinsrd): Likewise.
- (*mmx_pinsrb): Likewise.
- (*pinsrb): Likewise.
- (mmx_pshufbv8qi3): Likewise.
- (mmx_pshufbv4qi3): Likewise.
- (@sse4_1_insertps_<mode>): Likewise.
- (*mmx_pextrw): Split altrenatives and map non-EGPR
- constraints, attr_gpr32 and attr_isa to noavx mnemonics.
- (*movv2qi_internal): Likewise.
- (*pextrw): Likewise.
- (*mmx_pextrb): Likewise.
- (*mmx_pextrb_zext): Likewise.
- (*pextrb): Likewise.
- (*pextrb_zext): Likewise.
- (vec_extractv2si_1): Likewise.
- (vec_extractv2si_1_zext): Likewise.
- * config/i386/sse.md: (vi128_h_r): New mode attr for
- pinsr{bw}/pextr{bw} with reg operand.
- (*abs<mode>2): Split altrenatives and %v in mnemonics, map
- non-EGPR constraints, gpr32 and isa attrs to noavx mnemonics.
- (*vec_extract<mode>): Likewise.
- (*vec_extract<mode>): Likewise for HFBF pattern.
- (*vec_extract<PEXTR_MODE12:mode>_zext): Likewise.
- (*vec_extractv4si_1): Likewise.
- (*vec_extractv4si_zext): Likewise.
- (*vec_extractv2di_1): Likewise.
- (*vec_concatv2si_sse4_1): Likewise.
- (<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
- (vec_concatv2di): Likewise.
- (*sse4_1_<code>v2qiv2di2<mask_name>_1): Likewise.
- (ssse3_avx2>_pshufb<mode>3<mask_name>): Change "r/m/Bm" to
- "jr/jm/ja" and set_attr gpr32 0 for noavx alternative, split
- %v for avx/noavx alternatives if necessary.
- (*vec_concatv2sf_sse4_1): Likewise.
- (*sse4_1_extractps): Likewise.
- (vec_set<mode>_0): Likewise for VI4F_128.
- (*vec_setv4sf_sse4_1): Likewise.
- (@sse4_1_insertps<mode>): Likewise.
- (ssse3_pmaddubsw128): Likewise.
- (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Likewise.
- (<sse4_1_avx2>_packusdw<mask_name>): Likewise.
- (<ssse3_avx2>_palignr<mode>): Likewise.
- (<vi8_sse4_1_avx2_avx512>_movntdqa): Likewise.
- (<sse4_1_avx2>_mpsadbw): Likewise.
- (*sse4_1_mulv2siv2di3<mask_name>): Likewise.
- (*<sse4_1_avx2>_mul<mode>3<mask_name>): Likewise.
- (*sse4_1_<code><mode>3<mask_name>): Likewise.
- (*<code>v8hi3): Likewise.
- (*<code>v16qi3): Likewise.
- (*sse4_1_<code>v8qiv8hi2<mask_name>_1): Likewise.
- (*sse4_1_zero_extendv8qiv8hi2_3): Likewise.
- (*sse4_1_zero_extendv8qiv8hi2_4): Likewise.
- (*sse4_1_<code>v4qiv4si2<mask_name>_1): Likewise.
- (*sse4_1_<code>v4hiv4si2<mask_name>_1): Likewise.
- (*sse4_1_zero_extendv4hiv4si2_3): Likewise.
- (*sse4_1_zero_extendv4hiv4si2_4): Likewise.
- (*sse4_1_<code>v2hiv2di2<mask_name>_1): Likewise.
- (*sse4_1_<code>v2siv2di2<mask_name>_1): Likewise.
- (*sse4_1_zero_extendv2siv2di2_3): Likewise.
- (*sse4_1_zero_extendv2siv2di2_4): Likewise.
- (aesdec): Likewise.
- (aesdeclast): Likewise.
- (aesenc): Likewise.
- (aesenclast): Likewise.
- (pclmulqdq): Likewise.
- (vgf2p8affineinvqb_<mode><mask_name>): Likewise.
- (vgf2p8affineqb_<mode><mask_name>): Likewise.
- (vgf2p8mulb_<mode><mask_name>): Likewise.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/i386-protos.h (x86_evex_reg_mentioned_p): New
- prototype.
- * config/i386/i386.cc (x86_evex_reg_mentioned_p): New
- function.
- * config/i386/i386.md (sse4_1_round<mode>2): Set attr gpr32 0
- and constraint jm to all non-evex alternatives, adjust
- alternative outputs if evex reg is mentioned.
- * config/i386/sse.md (<sse4_1>_ptest<mode>): Set attr gpr32 0
- and constraint jm/ja to all non-evex alternatives.
- (ptesttf2): Likewise.
- (<sse4_1>_round<ssemodesuffix><avxsizesuffix): Likewise.
- (sse4_1_round<ssescalarmodesuffix>): Likewise.
- (sse4_2_pcmpestri): Likewise.
- (sse4_2_pcmpestrm): Likewise.
- (sse4_2_pcmpestr_cconly): Likewise.
- (sse4_2_pcmpistr): Likewise.
- (sse4_2_pcmpistri): Likewise.
- (sse4_2_pcmpistrm): Likewise.
- (sse4_2_pcmpistr_cconly): Likewise.
- (aesimc): Likewise.
- (aeskeygenassist): Likewise.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3): Set
- attr gpr32 0 and constraint jm/ja to all mem alternatives.
- (ssse3_ph<plusminus_mnemonic>wv8hi3): Likewise.
- (ssse3_ph<plusminus_mnemonic>wv4hi3): Likewise.
- (avx2_ph<plusminus_mnemonic>dv8si3): Likewise.
- (ssse3_ph<plusminus_mnemonic>dv4si3): Likewise.
- (ssse3_ph<plusminus_mnemonic>dv2si3): Likewise.
- (<ssse3_avx2>_psign<mode>3): Likewise.
- (ssse3_psign<mode>3): Likewise.
- (<sse4_1>_blend<ssemodesuffix><avxsizesuffix): Likewise.
- (<sse4_1>_blendv<ssemodesuffix><avxsizesuffix): Likewise.
- (*<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>_lt): Likewise.
- (*<sse4_1>_blendv<ssefltmodesuff)ix><avxsizesuffix>_not_ltint: Likewise.
- (<sse4_1>_dp<ssemodesuffix><avxsizesuffix>): Likewise.
- (<sse4_1_avx2>_mpsadbw): Likewise.
- (<sse4_1_avx2>_pblendvb): Likewise.
- (*<sse4_1_avx2>_pblendvb_lt): Likewise.
- (sse4_1_pblend<ssemodesuffix>): Likewise.
- (*avx2_pblend<ssemodesuffix>): Likewise.
- (avx2_permv2ti): Likewise.
- (*avx_vperm2f128<mode>_nozero): Likewise.
- (*avx2_eq<mode>3): Likewise.
- (*sse4_1_eqv2di3): Likewise.
- (sse4_2_gtv2di3): Likewise.
- (avx2_gt<mode>3): Likewise.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/i386.md (<xsave>): Set attr gpr32 0 and constraint
- jm.
- (<xsave>_rex64): Likewise.
- (<xrstor>_rex64): Likewise.
- (<xrstor>64): Likewise.
- (fxsave64): Likewise.
- (fxstore64): Likewise.
-
-2023-10-07 Hongyu Wang <hongyu.wang@intel.com>
- Kong Lingling <lingling.kong@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/i386.cc (ix86_get_ssemov): Check if egpr is used,
- adjust mnemonic for vmovduq/vmovdqa.
- * config/i386/sse.md (*<extract_type>_vinsert<shuffletype><extract_suf>_0):
- Check if egpr is used, adjust mnemonic for vmovdqu/vmovdqa.
- (avx_vec_concat<mode>): Likewise, and separate alternative 0 to
- avx_noavx512f.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/i386.cc (map_egpr_constraints): New funciton to
- map common constraints to EGPR prohibited constraints.
- (ix86_md_asm_adjust): Calls map_egpr_constraints.
- * config/i386/i386.opt: Add option mapx-inline-asm-use-gpr32.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/i386-protos.h (ix86_insn_base_reg_class): New
- prototype.
- (ix86_regno_ok_for_insn_base_p): Likewise.
- (ix86_insn_index_reg_class): Likewise.
- * config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
- New helper function to scan the insn.
- (ix86_insn_base_reg_class): New function to choose BASE_REG_CLASS.
- (ix86_regno_ok_for_insn_base_p): Likewise for base regno.
- (ix86_insn_index_reg_class): Likewise for INDEX_REG_CLASS.
- * config/i386/i386.h (INSN_BASE_REG_CLASS): Define.
- (REGNO_OK_FOR_INSN_BASE_P): Likewise.
- (INSN_INDEX_REG_CLASS): Likewise.
- (enum reg_class): Add INDEX_GPR16.
- (GENERAL_GPR16_REGNO_P): Define.
- * config/i386/i386.md (gpr32): New attribute.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/constraints.md (jr): New register constraint
- that prohibits EGPR.
- (jR): Constraint that force usage of EGPR.
- (jm): New memory constraint that prohibits EGPR.
- (ja): Likewise for Bm constraint.
- (jb): Likewise for Tv constraint.
- (j<): New auto-dec memory constraint that prohibits EGPR.
- (j>): Likewise for ">" constraint.
- (jo): Likewise for "o" constraint.
- (jv): Likewise for "V" constraint.
- (jp): Likewise for "p" constraint.
- * config/i386/i386.h (enum reg_class): Add new reg class
- GENERAL_GPR16.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * config/i386/i386-protos.h (x86_extended_rex2reg_mentioned_p):
- New function prototype.
- * config/i386/i386.cc (regclass_map): Add mapping for 16 new
- general registers.
- (debugger64_register_map): Likewise.
- (ix86_conditional_register_usage): Clear REX2 register when APX
- disabled.
- (ix86_code_end): Add handling for REX2 reg.
- (print_reg): Likewise.
- (ix86_output_jmp_thunk_or_indirect): Likewise.
- (ix86_output_indirect_branch_via_reg): Likewise.
- (ix86_attr_length_vex_default): Likewise.
- (ix86_emit_save_regs): Adjust to allow saving r31.
- (ix86_register_priority): Set REX2 reg priority same as REX.
- (x86_extended_reg_mentioned_p): Add check for REX2 regs.
- (x86_extended_rex2reg_mentioned_p): New function.
- * config/i386/i386.h (CALL_USED_REGISTERS): Add new extended
- registers.
- (REG_ALLOC_ORDER): Likewise.
- (FIRST_REX2_INT_REG): Define.
- (LAST_REX2_INT_REG): Ditto.
- (GENERAL_REGS): Add 16 new registers.
- (INT_SSE_REGS): Likewise.
- (FLOAT_INT_REGS): Likewise.
- (FLOAT_INT_SSE_REGS): Likewise.
- (INT_MASK_REGS): Likewise.
- (ALL_REGS):Likewise.
- (REX2_INT_REG_P): Define.
- (REX2_INT_REGNO_P): Ditto.
- (GENERAL_REGNO_P): Add REX2_INT_REGNO_P.
- (REGNO_OK_FOR_INDEX_P): Ditto.
- (REG_OK_FOR_INDEX_NONSTRICT_P): Add new extended registers.
- * config/i386/i386.md: Add 16 new integer general
- registers.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * common/config/i386/cpuinfo.h (XSTATE_APX_F): New macro.
- (XCR_APX_F_ENABLED_MASK): Likewise.
- (get_available_features): Detect APX_F under
- * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_APX_F_SET): New.
- (OPTION_MASK_ISA2_APX_F_UNSET): Likewise.
- (ix86_handle_option): Handle -mapxf.
- * common/config/i386/i386-cpuinfo.h (FEATURE_APX_F): New.
- * common/config/i386/i386-isas.h: Add entry for APX_F.
- * config/i386/cpuid.h (bit_APX_F): New.
- * config/i386/i386.h (bit_APX_F): (TARGET_APX_EGPR,
- TARGET_APX_PUSH2POP2, TARGET_APX_NDD): New define.
- * config/i386/i386-opts.h (enum apx_features): New enum.
- * config/i386/i386-isa.def (APX_F): New DEF_PTA.
- * config/i386/i386-options.cc (ix86_function_specific_save):
- Save ix86_apx_features.
- (ix86_function_specific_restore): Restore it.
- (ix86_valid_target_attribute_inner_p): Add mapxf.
- (ix86_option_override_internal): Set ix86_apx_features for PTA
- and TARGET_APX_F. Also reports error when APX_F is set but not
- having TARGET_64BIT.
- * config/i386/i386.opt: (-mapxf): New ISA flag option.
- (-mapx=): New enumeration option.
- (apx_features): New enum type.
- (apx_none): New enum value.
- (apx_egpr): Likewise.
- (apx_push2pop2): Likewise.
- (apx_ndd): Likewise.
- (apx_all): Likewise.
- * doc/invoke.texi: Document mapxf.
-
-2023-10-07 Hongyu Wang <hongyu.wang@intel.com>
- Kong Lingling <lingling.kong@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * addresses.h (index_reg_class): New wrapper function like
- base_reg_class.
- * doc/tm.texi: Document INSN_INDEX_REG_CLASS.
- * doc/tm.texi.in: Ditto.
- * lra-constraints.cc (index_part_to_reg): Pass index_class.
- (process_address_1): Calls index_reg_class with curr_insn and
- replace INDEX_REG_CLASS with its return value index_cl.
- * reload.cc (find_reloads_address): Likewise.
- (find_reloads_address_1): Likewise.
-
-2023-10-07 Kong Lingling <lingling.kong@intel.com>
- Hongyu Wang <hongyu.wang@intel.com>
- Hongtao Liu <hongtao.liu@intel.com>
-
- * addresses.h (base_reg_class): Add insn argument and new macro
- INSN_BASE_REG_CLASS.
- (regno_ok_for_base_p_1): Add insn argument and new macro
- REGNO_OK_FOR_INSN_BASE_P.
- (regno_ok_for_base_p): Add insn argument and parse to ok_for_base_p_1.
- * doc/tm.texi: Document INSN_BASE_REG_CLASS and
- REGNO_OK_FOR_INSN_BASE_P.
- * doc/tm.texi.in: Ditto.
- * lra-constraints.cc (process_address_1): Pass insn to
- base_reg_class.
- (curr_insn_transform): Ditto.
- * reload.cc (find_reloads): Ditto.
- (find_reloads_address): Ditto.
- (find_reloads_address_1): Ditto.
- (find_reloads_subreg_address): Ditto.
- * reload1.cc (maybe_fix_stack_asms): Ditto.
-
-2023-10-07 Jiufu Guo <guojiufu@linux.ibm.com>
-
- PR target/108338
- * config/rs6000/rs6000.md (movsf_from_si): Update to generate mtvsrws
- for P9.
-
-2023-10-07 Jiufu Guo <guojiufu@linux.ibm.com>
-
- PR target/108338
- * config/rs6000/predicates.md (lowpart_subreg_operator): New
- define_predicate.
- * config/rs6000/rs6000.md (any_rshift): New code_iterator.
- (movsf_from_si2): Rename to ...
- (movsf_from_si2_<code>): ... this.
-
-2023-10-07 Pan Li <pan2.li@intel.com>
-
- PR target/111634
- * config/riscv/riscv.cc (riscv_legitimize_address): Ensure
- object is a REG before extracting its' REGNO.
-
-2023-10-06 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_split_ashl): Split shifts by
- one into add3_cc_overflow_1 followed by add3_carry.
- * config/i386/i386.md (@add<mode>3_cc_overflow_1): Renamed from
- "*add<mode>3_cc_overflow_1" to provide generator function.
-
-2023-10-06 Roger Sayle <roger@nextmovesoftware.com>
- Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.cc (ix86_avoid_lea_for_addr): Split LEAs used
- to perform left shifts into shorter instructions with -Oz.
-
-2023-10-06 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.md (mvconst_internal): Add !ira_in_progress.
-
-2023-10-06 Sandra Loosemore <sandra@codesourcery.com>
-
- * doc/extend.texi (Function Attributes): Mention standard attribute
- syntax.
- (Variable Attributes): Likewise.
- (Type Attributes): Likewise.
- (Attribute Syntax): Likewise.
-
-2023-10-06 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md (*mov<mode>): Convert to compact syntax.
- (mov<mode>_exec): Likewise.
- (mov<mode>_sgprbase): Likewise.
- * config/gcn/gcn.md (*mov<mode>_insn): Likewise.
- (*movti_insn): Likewise.
-
-2023-10-06 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn.cc (print_operand): Adjust xcode type to fix warning.
-
-2023-10-06 Andrew Pinski <pinskia@gmail.com>
-
- PR middle-end/111699
- * match.pd ((c ? a : b) op d, (c ? a : b) op (c ? d : e),
- (v ? w : 0) ? a : b, c1 ? c2 ? a : b : b): Enable only for GIMPLE.
-
-2023-10-06 Jakub Jelinek <jakub@redhat.com>
-
- * ipa-prop.h (ipa_bits): Remove.
- (struct ipa_jump_func): Remove bits member.
- (struct ipcp_transformation): Remove bits member, adjust
- ctor and dtor.
- (ipa_get_ipa_bits_for_value): Remove.
- * ipa-prop.cc (struct ipa_bit_ggc_hash_traits): Remove.
- (ipa_bits_hash_table): Remove.
- (ipa_print_node_jump_functions_for_edge): Don't print bits.
- (ipa_get_ipa_bits_for_value): Remove.
- (ipa_set_jfunc_bits): Remove.
- (ipa_compute_jump_functions_for_edge): For pointers query
- pointer alignment before ipa_set_jfunc_vr and update_bitmask
- in there. For integral types, just rely on bitmask already
- being handled in value ranges.
- (ipa_check_create_edge_args): Don't create ipa_bits_hash_table.
- (ipcp_transformation_initialize): Neither here.
- (ipcp_transformation_t::duplicate): Don't copy bits vector.
- (ipa_write_jump_function): Don't stream bits here.
- (ipa_read_jump_function): Neither here.
- (useful_ipcp_transformation_info_p): Don't test bits vec.
- (write_ipcp_transformation_info): Don't stream bits here.
- (read_ipcp_transformation_info): Neither here.
- (ipcp_get_parm_bits): Get mask and value from m_vr rather
- than bits.
- (ipcp_update_bits): Remove.
- (ipcp_update_vr): For pointers, set_ptr_info_alignment from
- bitmask stored in value range.
- (ipcp_transform_function): Don't test bits vector, don't call
- ipcp_update_bits.
- * ipa-cp.cc (propagate_bits_across_jump_function): Don't use
- jfunc->bits, instead get mask and value from jfunc->m_vr.
- (ipcp_store_bits_results): Remove.
- (ipcp_store_vr_results): Incorporate parts of
- ipcp_store_bits_results here, merge the bitmasks with value
- range if both are supplied.
- (ipcp_driver): Don't call ipcp_store_bits_results.
- * ipa-sra.cc (zap_useless_ipcp_results): Remove *ts->bits
- clearing.
-
-2023-10-06 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Update comments.
-
-2023-10-05 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa32-linux.h (MALLOC_ABI_ALIGNMENT): Delete.
-
-2023-10-05 Andrew MacLeod <amacleod@redhat.com>
-
- * timevar.def (TV_TREE_FAST_VRP): New.
- * tree-pass.h (make_pass_fast_vrp): New prototype.
- * tree-vrp.cc (class fvrp_folder): New.
- (fvrp_folder::fvrp_folder): New.
- (fvrp_folder::~fvrp_folder): New.
- (fvrp_folder::value_of_expr): New.
- (fvrp_folder::value_on_edge): New.
- (fvrp_folder::value_of_stmt): New.
- (fvrp_folder::pre_fold_bb): New.
- (fvrp_folder::post_fold_bb): New.
- (fvrp_folder::pre_fold_stmt): New.
- (fvrp_folder::fold_stmt): New.
- (execute_fast_vrp): New.
- (pass_data_fast_vrp): New.
- (pass_vrp:execute): Check for fast VRP pass.
- (make_pass_fast_vrp): New.
-
-2023-10-05 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range.cc (dom_ranger::dom_ranger): New.
- (dom_ranger::~dom_ranger): New.
- (dom_ranger::range_of_expr): New.
- (dom_ranger::edge_range): New.
- (dom_ranger::range_on_edge): New.
- (dom_ranger::range_in_bb): New.
- (dom_ranger::range_of_stmt): New.
- (dom_ranger::maybe_push_edge): New.
- (dom_ranger::pre_bb): New.
- (dom_ranger::post_bb): New.
- * gimple-range.h (class dom_ranger): New.
-
-2023-10-05 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (gori_stmt_info::gori_stmt_info): New.
- (gori_calc_operands): New.
- (gori_on_edge): New.
- (gori_name_helper): New.
- (gori_name_on_edge): New.
- * gimple-range-gori.h (gori_on_edge): New prototype.
- (gori_name_on_edge): New prototype.
-
-2023-10-05 Sergei Trofimovich <siarheit@google.com>
-
- PR ipa/111283
- PR gcov-profile/111559
- * ipa-utils.cc (ipa_merge_profiles): Avoid producing
- uninitialized probabilities when merging counters with zero
- denominators.
-
-2023-10-05 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/111657
- * config/i386/i386-expand.cc (alg_usable_p): Reject libcall
- strategy for non-default address spaces.
- (decide_alg): Use loop strategy as a fallback strategy for
- non-default address spaces.
-
-2023-10-05 Jakub Jelinek <jakub@redhat.com>
-
- * sreal.cc (verify_aritmetics): Rename to ...
- (verify_arithmetics): ... this.
- (sreal_verify_arithmetics): Adjust caller.
-
-2023-10-05 Martin Jambor <mjambor@suse.cz>
-
- Revert:
- 2023-10-03 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/108007
- * cgraph.h (cgraph_edge): Add a parameter to
- redirect_call_stmt_to_callee.
- * ipa-param-manipulation.h (ipa_param_adjustments): Add a
- parameter to modify_call.
- * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
- parameter killed_ssas, pass it to padjs->modify_call.
- * ipa-param-manipulation.cc (purge_transitive_uses): New function.
- (ipa_param_adjustments::modify_call): New parameter killed_ssas.
- Instead of substituting uses, invoke purge_transitive_uses. If
- hash of killed SSAs has not been provided, create a temporary one
- and release SSAs that have been added to it.
- * tree-inline.cc (redirect_all_calls): Create
- id->killed_new_ssa_names earlier, pass it to edge redirection,
- adjust a comment.
- (copy_body): Release SSAs in id->killed_new_ssa_names.
-
-2023-10-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (@vec_series<mode>): Remove @.
- (vec_series<mode>): Ditto.
- * config/riscv/riscv-v.cc (expand_const_vector): Ditto.
- (shuffle_decompress_patterns): Ditto.
-
-2023-10-05 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc-passes.def: Remove arc_ifcvt pass.
- * config/arc/arc-protos.h (arc_ccfsm_branch_deleted_p): Remove.
- (arc_ccfsm_record_branch_deleted): Likewise.
- (arc_ccfsm_cond_exec_p): Likewise.
- (arc_ccfsm): Likewise.
- (arc_ccfsm_record_condition): Likewise.
- (make_pass_arc_ifcvt): Likewise.
- * config/arc/arc.cc (arc_ccfsm): Remove.
- (arc_ccfsm_current): Likewise.
- (ARC_CCFSM_BRANCH_DELETED_P): Likewise.
- (ARC_CCFSM_RECORD_BRANCH_DELETED): Likewise.
- (ARC_CCFSM_COND_EXEC_P): Likewise.
- (CCFSM_ISCOMPACT): Likewise.
- (CCFSM_DBR_ISCOMPACT): Likewise.
- (machine_function): Remove ccfsm related fields.
- (arc_ifcvt): Remove pass.
- (arc_print_operand): Remove `#` punct operand and other ccfsm
- related code.
- (arc_ccfsm_advance): Remove.
- (arc_ccfsm_at_label): Likewise.
- (arc_ccfsm_record_condition): Likewise.
- (arc_ccfsm_post_advance): Likewise.
- (arc_ccfsm_branch_deleted_p): Likewise.
- (arc_ccfsm_record_branch_deleted): Likewise.
- (arc_ccfsm_cond_exec_p): Likewise.
- (arc_get_ccfsm_cond): Likewise.
- (arc_final_prescan_insn): Remove ccfsm references.
- (arc_internal_label): Likewise.
- (arc_reorg): Likewise.
- (arc_output_libcall): Likewise.
- * config/arc/arc.md: Remove ccfsm references and update related
- instruction patterns.
-
-2023-10-05 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc.cc (arc_init): Remove '^' punct char.
- (arc_print_operand): Remove related code.
- * config/arc/arc.md: Update patterns which uses '%&'.
-
-2023-10-05 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc-protos.h (arc_clear_unalign): Remove.
- (arc_toggle_unalign): Likewise.
- * config/arc/arc.cc (machine_function) Remove unalign.
- (arc_init): Remove `&` punct character.
- (arc_print_operand): Remove `&` related functions.
- (arc_verify_short): Update function's number of parameters.
- (output_short_suffix): Update function.
- (arc_short_long): Likewise.
- (arc_clear_unalign): Remove.
- (arc_toggle_unalign): Likewise.
- * config/arc/arc.h (ASM_OUTPUT_CASE_END): Remove.
- (ASM_OUTPUT_ALIGN): Update.
- * config/arc/arc.md: Remove all `%&` references.
- * config/arc/arc.opt (mannotate-align): Ignore option.
- * doc/invoke.texi (mannotate-align): Update description.
-
-2023-10-05 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_build_slp_tree_1): Do not
- ask for internal_fn_p (CFN_LAST).
-
-2023-10-05 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Not
- visited value numbers are available itself.
-
-2023-10-05 Richard Biener <rguenther@suse.de>
-
- PR ipa/111643
- * doc/extend.texi (attribute flatten): Clarify.
-
-2023-10-04 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc-protos.h (emit_shift): Delete prototype.
- (arc_pre_reload_split): New function prototype.
- * config/arc/arc.cc (emit_shift): Delete function.
- (arc_pre_reload_split): New predicate function, copied from i386,
- to schedule define_insn_and_split splitters to the split1 pass.
- * config/arc/arc.md (ashlsi3): Expand RTL template unconditionally.
- (ashrsi3): Likewise.
- (lshrsi3): Likewise.
- (shift_si3): Move after other shift patterns, and disable when
- operands[2] is one (which is handled by its own define_insn).
- Use shiftr4_operator, instead of shift4_operator, as this is no
- longer used for left shifts.
- (shift_si3_loop): Likewise. Additionally remove match_scratch.
- (*ashlsi3_nobs): New pre-reload define_insn_and_split.
- (*ashrsi3_nobs): Likewise.
- (*lshrsi3_nobs): Likewise.
- (rotrsi3_cnt1): Rename define_insn from *rotrsi3_cnt1.
- (add_shift): Rename define_insn from *add_shift.
- * config/arc/predicates.md (shiftl4_operator): Delete.
- (shift4_operator): Delete.
-
-2023-10-04 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md (ashlsi3_cnt1): Rename define_insn *ashlsi2_cnt1.
- Change type attribute to "unary", as this doesn't have operands[2].
- Change length attribute to "*,4" to allow compact representation.
- (lshrsi3_cnt1): Rename define_insn from *lshrsi3_cnt1. Change
- insn type attribute to "unary", as this doesn't have operands[2].
- (ashrsi3_cnt1): Rename define_insn from *ashrsi3_cnt1. Change
- insn type attribute to "unary", as this doesn't have operands[2].
-
-2023-10-04 Roger Sayle <roger@nextmovesoftware.com>
-
- PR rtl-optimization/110701
- * combine.cc (record_dead_and_set_regs_1): Split comment into
- pieces placed before the relevant clauses. When the SET_DEST
- is a partial_subreg_p, mark the bits outside of the updated
- portion of the destination as undefined.
-
-2023-10-04 Kito Cheng <kito.cheng@sifive.com>
-
- PR bootstrap/111664
- * opt-read.awk: Drop multidimensional arrays.
- * opth-gen.awk: Ditto.
-
-2023-10-04 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (UNSPEC_FCOPYSIGN): Delete.
- (copysign<mode>3): Use copysign RTL instead of UNSPEC.
-
-2023-10-04 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/111369
- * match.pd (x == cstN ? cst4 : cst3): Use
- build_nonstandard_integer_type only if type1 is BOOLEAN_TYPE.
- Fix comment typo. Formatting fix.
- (a?~t:t -> (-(a))^t): Always convert to type rather
- than using build_nonstandard_integer_type. Perform negation
- only if type has precision > 1 and is not signed BOOLEAN_TYPE.
-
-2023-10-04 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/111668
- * match.pd (a ? CST1 : CST2): Handle the a ? -1 : 0 and
- a ? 0 : -1 cases before the powerof2cst cases and differentiate
- between 1-bit precision types, larger precision boolean types
- and other integral types. Fix comment pastos and formatting.
-
-2023-10-03 Andrew MacLeod <amacleod@redhat.com>
-
- * tree-ssanames.cc (set_range_info): Use get_ptr_info for
- pointers rather than range_info_get_range.
-
-2023-10-03 Martin Jambor <mjambor@suse.cz>
-
- * ipa-modref.h (modref_summary::dump): Make const.
- * ipa-modref.cc (modref_summary::dump): Likewise.
- (dump_lto_records): Dump to out instead of dump_file.
-
-2023-10-03 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/110378
- * ipa-param-manipulation.cc
- (ipa_param_body_adjustments::mark_dead_statements): Verify that any
- return uses of PARAM will be removed.
- (ipa_param_body_adjustments::mark_clobbers_dead): Likewise.
- * ipa-sra.cc (isra_param_desc): New fields
- remove_only_when_retval_removed and split_only_when_retval_removed.
- (struct gensum_param_desc): Likewise. Fix comment long line.
- (ipa_sra_function_summaries::duplicate): Copy the new flags.
- (dump_gensum_param_descriptor): Dump the new flags.
- (dump_isra_param_descriptor): Likewise.
- (isra_track_scalar_value_uses): New parameter desc. Set its flag
- remove_only_when_retval_removed when encountering a simple return.
- (isra_track_scalar_param_local_uses): Replace parameter call_uses_p
- with desc. Pass it to isra_track_scalar_value_uses and set its
- call_uses.
- (ptr_parm_has_nonarg_uses): Accept parameter descriptor as a
- parameter. If there is a direct return use, mark any..
- (create_parameter_descriptors): Pass the whole parameter descriptor to
- isra_track_scalar_param_local_uses and ptr_parm_has_nonarg_uses.
- (process_scan_results): Copy the new flags.
- (isra_write_node_summary): Stream the new flags.
- (isra_read_node_info): Likewise.
- (adjust_parameter_descriptions): Check that transformations
- requring return removal only happen when return value is removed.
- Restructure main loop. Adjust dump message.
-
-2023-10-03 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/108007
- * cgraph.h (cgraph_edge): Add a parameter to
- redirect_call_stmt_to_callee.
- * ipa-param-manipulation.h (ipa_param_adjustments): Add a
- parameter to modify_call.
- * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
- parameter killed_ssas, pass it to padjs->modify_call.
- * ipa-param-manipulation.cc (purge_transitive_uses): New function.
- (ipa_param_adjustments::modify_call): New parameter killed_ssas.
- Instead of substituting uses, invoke purge_transitive_uses. If
- hash of killed SSAs has not been provided, create a temporary one
- and release SSAs that have been added to it.
- * tree-inline.cc (redirect_all_calls): Create
- id->killed_new_ssa_names earlier, pass it to edge redirection,
- adjust a comment.
- (copy_body): Release SSAs in id->killed_new_ssa_names.
-
-2023-10-03 Andrew MacLeod <amacleod@redhat.com>
-
- * passes.def (pass_vrp): Pass "final pass" flag as parameter.
- * tree-vrp.cc (vrp_pass_num): Remove.
- (pass_vrp::my_pass): Remove.
- (pass_vrp::pass_vrp): Add warn_p as a parameter.
- (pass_vrp::final_p): New.
- (pass_vrp::set_pass_param): Set final_p param.
- (pass_vrp::execute): Call execute_range_vrp with no conditions.
- (make_pass_vrp): Pass additional parameter.
- (make_pass_early_vrp): Ditto.
-
-2023-10-03 Andrew MacLeod <amacleod@redhat.com>
-
- * tree-ssanames.cc (set_range_info): Return true only if the
- current value changes.
-
-2023-10-03 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_set_info_translated): Update for "m_"
- prefixes to text_info fields.
- (diagnostic_report_diagnostic): Likewise.
- (verbatim): Use text_info ctor.
- (simple_diagnostic_path::add_event): Likewise.
- (simple_diagnostic_path::add_thread_event): Likewise.
- * dumpfile.cc (dump_pretty_printer::decode_format): Update for
- "m_" prefixes to text_info fields.
- (dump_context::dump_printf_va): Use text_info ctor.
- * graphviz.cc (graphviz_out::graphviz_out): Use text_info ctor.
- (graphviz_out::print): Likewise.
- * opt-problem.cc (opt_problem::opt_problem): Likewise.
- * pretty-print.cc (pp_format): Update for "m_" prefixes to
- text_info fields.
- (pp_printf): Use text_info ctor.
- (pp_verbatim): Likewise.
- (assert_pp_format_va): Likewise.
- * pretty-print.h (struct text_info): Add ctors. Add "m_" prefix
- to all fields.
- * text-art/styled-string.cc (styled_string::from_fmt_va): Use
- text_info ctor.
- * tree-diagnostic.cc (default_tree_printer): Update for "m_"
- prefixes to text_info fields.
- * tree-pretty-print.h (pp_ti_abstract_origin): Likewise.
-
-2023-10-03 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md (CC_ltu): New mode iterator for CC and CC_C.
- (scc_ltu_<mode>): New define_insn to handle LTU form of scc_insn.
- (*scc_insn): Don't split to a conditional move sequence for LTU.
-
-2023-10-03 Andrea Corallo <andrea.corallo@arm.com>
-
- * config/aarch64/aarch64.md (@ccmp<CC_ONLY:mode><GPI:mode>)
- (@ccmp<CC_ONLY:mode><GPI:mode>_rev, *call_insn, *call_value_insn)
- (*mov<mode>_aarch64, load_pair_sw_<SX:mode><SX2:mode>)
- (load_pair_dw_<DX:mode><DX2:mode>)
- (store_pair_sw_<SX:mode><SX2:mode>)
- (store_pair_dw_<DX:mode><DX2:mode>, *extendsidi2_aarch64)
- (*zero_extendsidi2_aarch64, *load_pair_zero_extendsidi2_aarch64)
- (*extend<SHORT:mode><GPI:mode>2_aarch64)
- (*zero_extend<SHORT:mode><GPI:mode>2_aarch64)
- (*extendqihi2_aarch64, *zero_extendqihi2_aarch64)
- (*add<mode>3_aarch64, *addsi3_aarch64_uxtw, *add<mode>3_poly_1)
- (add<mode>3_compare0, *addsi3_compare0_uxtw)
- (*add<mode>3_compareC_cconly, add<mode>3_compareC)
- (*add<mode>3_compareV_cconly_imm, add<mode>3_compareV_imm)
- (*add<mode>3nr_compare0, subdi3, subv<GPI:mode>_imm)
- (*cmpv<GPI:mode>_insn, sub<mode>3_compare1_imm, neg<mode>2)
- (cmp<mode>, fcmp<mode>, fcmpe<mode>, *cmov<mode>_insn)
- (*cmovsi_insn_uxtw, <optab><mode>3, *<optab>si3_uxtw)
- (*and<mode>3_compare0, *andsi3_compare0_uxtw, one_cmpl<mode>2)
- (*<NLOGICAL:optab>_one_cmpl<mode>3, *and<mode>3nr_compare0)
- (*aarch64_ashl_sisd_or_int_<mode>3)
- (*aarch64_lshr_sisd_or_int_<mode>3)
- (*aarch64_ashr_sisd_or_int_<mode>3, *ror<mode>3_insn)
- (*<optab>si3_insn_uxtw, <optab>_trunc<fcvt_target><GPI:mode>2)
- (<optab><fcvt_target><GPF:mode>2)
- (<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3)
- (<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3)
- (*aarch64_<optab><mode>3_cssc, copysign<GPF:mode>3_insn): Update
- to new syntax.
- * config/aarch64/aarch64-sve2.md (@aarch64_scatter_stnt<mode>)
- (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
- (*aarch64_mul_unpredicated_<mode>)
- (@aarch64_pred_<sve_int_op><mode>, *cond_<sve_int_op><mode>_2)
- (*cond_<sve_int_op><mode>_3, *cond_<sve_int_op><mode>_any)
- (*cond_<sve_int_op><mode>_z, @aarch64_pred_<sve_int_op><mode>)
- (*cond_<sve_int_op><mode>_2, *cond_<sve_int_op><mode>_3)
- (*cond_<sve_int_op><mode>_any, @aarch64_sve_<sve_int_op><mode>)
- (@aarch64_sve_<sve_int_op>_lane_<mode>)
- (@aarch64_sve_add_mul_lane_<mode>)
- (@aarch64_sve_sub_mul_lane_<mode>, @aarch64_sve2_xar<mode>)
- (*aarch64_sve2_bcax<mode>, @aarch64_sve2_eor3<mode>)
- (*aarch64_sve2_nor<mode>, *aarch64_sve2_nand<mode>)
- (*aarch64_sve2_bsl<mode>, *aarch64_sve2_nbsl<mode>)
- (*aarch64_sve2_bsl1n<mode>, *aarch64_sve2_bsl2n<mode>)
- (*aarch64_sve2_sra<mode>, @aarch64_sve_add_<sve_int_op><mode>)
- (*aarch64_sve2_<su>aba<mode>, @aarch64_sve_add_<sve_int_op><mode>)
- (@aarch64_sve_add_<sve_int_op>_lane_<mode>)
- (@aarch64_sve_qadd_<sve_int_op><mode>)
- (@aarch64_sve_qadd_<sve_int_op>_lane_<mode>)
- (@aarch64_sve_sub_<sve_int_op><mode>)
- (@aarch64_sve_sub_<sve_int_op>_lane_<mode>)
- (@aarch64_sve_qsub_<sve_int_op><mode>)
- (@aarch64_sve_qsub_<sve_int_op>_lane_<mode>)
- (@aarch64_sve_<sve_fp_op><mode>, @aarch64_<sve_fp_op>_lane_<mode>)
- (@aarch64_pred_<sve_int_op><mode>)
- (@aarch64_pred_<sve_fp_op><mode>, *cond_<sve_int_op><mode>_2)
- (*cond_<sve_int_op><mode>_z, @aarch64_sve_<optab><mode>)
- (@aarch64_<optab>_lane_<mode>, @aarch64_sve_<optab><mode>)
- (@aarch64_<optab>_lane_<mode>, @aarch64_pred_<sve_fp_op><mode>)
- (*cond_<sve_fp_op><mode>_any_relaxed)
- (*cond_<sve_fp_op><mode>_any_strict)
- (@aarch64_pred_<sve_int_op><mode>, *cond_<sve_int_op><mode>)
- (@aarch64_pred_<sve_fp_op><mode>, *cond_<sve_fp_op><mode>)
- (*cond_<sve_fp_op><mode>_strict): Update to new syntax.
- * config/aarch64/aarch64-sve.md (*aarch64_sve_mov<mode>_ldr_str)
- (*aarch64_sve_mov<mode>_no_ldr_str, @aarch64_pred_mov<mode>)
- (*aarch64_sve_mov<mode>, aarch64_wrffr)
- (mask_scatter_store<mode><v_int_container>)
- (*mask_scatter_store<mode><v_int_container>_<su>xtw_unpacked)
- (*mask_scatter_store<mode><v_int_container>_sxtw)
- (*mask_scatter_store<mode><v_int_container>_uxtw)
- (@aarch64_scatter_store_trunc<VNx4_NARROW:mode><VNx4_WIDE:mode>)
- (@aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>)
- (*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_sxtw)
- (*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_uxtw)
- (*vec_duplicate<mode>_reg, vec_shl_insert_<mode>)
- (vec_series<mode>, @extract_<last_op>_<mode>)
- (@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2)
- (*cond_<optab><mode>_any, @aarch64_pred_<optab><mode>)
- (@aarch64_sve_revbhw_<SVE_ALL:mode><PRED_HSD:mode>)
- (@cond_<optab><mode>)
- (*<optab><SVE_PARTIAL_I:mode><SVE_HSDI:mode>2)
- (@aarch64_pred_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>)
- (@aarch64_cond_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>)
- (*cond_uxt<mode>_2, *cond_uxt<mode>_any, *cnot<mode>)
- (*cond_cnot<mode>_2, *cond_cnot<mode>_any)
- (@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2_relaxed)
- (*cond_<optab><mode>_2_strict, *cond_<optab><mode>_any_relaxed)
- (*cond_<optab><mode>_any_strict, @aarch64_pred_<optab><mode>)
- (*cond_<optab><mode>_2, *cond_<optab><mode>_3)
- (*cond_<optab><mode>_any, add<mode>3, sub<mode>3)
- (@aarch64_pred_<su>abd<mode>, *aarch64_cond_<su>abd<mode>_2)
- (*aarch64_cond_<su>abd<mode>_3, *aarch64_cond_<su>abd<mode>_any)
- (@aarch64_sve_<optab><mode>, @aarch64_pred_<optab><mode>)
- (*cond_<optab><mode>_2, *cond_<optab><mode>_z)
- (@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2)
- (*cond_<optab><mode>_3, *cond_<optab><mode>_any, <optab><mode>3)
- (*cond_bic<mode>_2, *cond_bic<mode>_any)
- (@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2_const)
- (*cond_<optab><mode>_any_const, *cond_<sve_int_op><mode>_m)
- (*cond_<sve_int_op><mode>_z, *sdiv_pow2<mode>3)
- (*cond_<sve_int_op><mode>_2, *cond_<sve_int_op><mode>_any)
- (@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2_relaxed)
- (*cond_<optab><mode>_2_strict, *cond_<optab><mode>_any_relaxed)
- (*cond_<optab><mode>_any_strict, @aarch64_pred_<optab><mode>)
- (*cond_<optab><mode>_2_relaxed, *cond_<optab><mode>_2_strict)
- (*cond_<optab><mode>_2_const_relaxed)
- (*cond_<optab><mode>_2_const_strict)
- (*cond_<optab><mode>_3_relaxed, *cond_<optab><mode>_3_strict)
- (*cond_<optab><mode>_any_relaxed, *cond_<optab><mode>_any_strict)
- (*cond_<optab><mode>_any_const_relaxed)
- (*cond_<optab><mode>_any_const_strict)
- (@aarch64_pred_<optab><mode>, *cond_add<mode>_2_const_relaxed)
- (*cond_add<mode>_2_const_strict)
- (*cond_add<mode>_any_const_relaxed)
- (*cond_add<mode>_any_const_strict, @aarch64_pred_<optab><mode>)
- (*cond_<optab><mode>_2_relaxed, *cond_<optab><mode>_2_strict)
- (*cond_<optab><mode>_any_relaxed, *cond_<optab><mode>_any_strict)
- (@aarch64_pred_<optab><mode>, *cond_sub<mode>_3_const_relaxed)
- (*cond_sub<mode>_3_const_strict, *cond_sub<mode>_const_relaxed)
- (*cond_sub<mode>_const_strict, *aarch64_pred_abd<mode>_relaxed)
- (*aarch64_pred_abd<mode>_strict)
- (*aarch64_cond_abd<mode>_2_relaxed)
- (*aarch64_cond_abd<mode>_2_strict)
- (*aarch64_cond_abd<mode>_3_relaxed)
- (*aarch64_cond_abd<mode>_3_strict)
- (*aarch64_cond_abd<mode>_any_relaxed)
- (*aarch64_cond_abd<mode>_any_strict, @aarch64_pred_<optab><mode>)
- (@aarch64_pred_fma<mode>, *cond_fma<mode>_2, *cond_fma<mode>_4)
- (*cond_fma<mode>_any, @aarch64_pred_fnma<mode>)
- (*cond_fnma<mode>_2, *cond_fnma<mode>_4, *cond_fnma<mode>_any)
- (<sur>dot_prod<vsi2qi>, @aarch64_<sur>dot_prod_lane<vsi2qi>)
- (@<sur>dot_prod<vsi2qi>, @aarch64_<sur>dot_prod_lane<vsi2qi>)
- (@aarch64_sve_add_<optab><vsi2qi>, @aarch64_pred_<optab><mode>)
- (*cond_<optab><mode>_2_relaxed, *cond_<optab><mode>_2_strict)
- (*cond_<optab><mode>_4_relaxed, *cond_<optab><mode>_4_strict)
- (*cond_<optab><mode>_any_relaxed, *cond_<optab><mode>_any_strict)
- (@aarch64_<optab>_lane_<mode>, @aarch64_pred_<optab><mode>)
- (*cond_<optab><mode>_4_relaxed, *cond_<optab><mode>_4_strict)
- (*cond_<optab><mode>_any_relaxed, *cond_<optab><mode>_any_strict)
- (@aarch64_<optab>_lane_<mode>, @aarch64_sve_tmad<mode>)
- (@aarch64_sve_<sve_fp_op>vnx4sf)
- (@aarch64_sve_<sve_fp_op>_lanevnx4sf)
- (@aarch64_sve_<sve_fp_op><mode>, *vcond_mask_<mode><vpred>)
- (@aarch64_sel_dup<mode>, @aarch64_pred_cmp<cmp_op><mode>)
- (*cmp<cmp_op><mode>_cc, *cmp<cmp_op><mode>_ptest)
- (@aarch64_pred_fcm<cmp_op><mode>, @fold_extract_<last_op>_<mode>)
- (@aarch64_fold_extract_vector_<last_op>_<mode>)
- (@aarch64_sve_splice<mode>)
- (@aarch64_sve_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>)
- (@aarch64_sve_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>)
- (*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>_relaxed)
- (*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>_strict)
- (*cond_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>)
- (@aarch64_sve_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>)
- (@aarch64_sve_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>)
- (*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>_relaxed)
- (*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>_strict)
- (*cond_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>)
- (@aarch64_sve_<optab>_trunc<SVE_FULL_SDF:mode><SVE_FULL_HSF:mode>)
- (*cond_<optab>_trunc<SVE_FULL_SDF:mode><SVE_FULL_HSF:mode>)
- (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
- (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
- (@aarch64_sve_<optab>_nontrunc<SVE_FULL_HSF:mode><SVE_FULL_SDF:mode>)
- (*cond_<optab>_nontrunc<SVE_FULL_HSF:mode><SVE_FULL_SDF:mode>)
- (@aarch64_brk<brk_op>, *aarch64_sve_<inc_dec><mode>_cntp): Update
- to new syntax.
- * config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>)
- (load_pair<DREG:mode><DREG2:mode>)
- (vec_store_pair<DREG:mode><DREG2:mode>, aarch64_simd_stp<mode>)
- (aarch64_simd_mov_from_<mode>low)
- (aarch64_simd_mov_from_<mode>high, and<mode>3<vczle><vczbe>)
- (ior<mode>3<vczle><vczbe>, aarch64_simd_ashr<mode><vczle><vczbe>)
- (aarch64_simd_bsl<mode>_internal<vczle><vczbe>)
- (*aarch64_simd_bsl<mode>_alt<vczle><vczbe>)
- (aarch64_simd_bsldi_internal, aarch64_simd_bsldi_alt)
- (store_pair_lanes<mode>, *aarch64_combine_internal<mode>)
- (*aarch64_combine_internal_be<mode>, *aarch64_combinez<mode>)
- (*aarch64_combinez_be<mode>)
- (aarch64_cm<optab><mode><vczle><vczbe>, *aarch64_cm<optab>di)
- (aarch64_cm<optab><mode><vczle><vczbe>, *aarch64_mov<mode>)
- (*aarch64_be_mov<mode>, *aarch64_be_movoi): Update to new syntax.
-
-2023-10-03 Andrea Corallo <andrea.corallo@arm.com>
-
- * gensupport.cc (convert_syntax): Skip spaces before "cons:"
- in new compact pattern syntax.
-
-2023-10-03 Richard Sandiford <richard.sandiford@arm.com>
-
- * gensupport.cc (convert_syntax): Updated to support unordered
- constraints in compact syntax.
-
-2023-10-02 Michael Meissner <meissner@linux.ibm.com>
-
- * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete.
- (copysign<mode>3_fcpsg): Use copysign RTL instead of UNSPEC.
- (copysign<mode>3_hard): Likewise.
- (copysign<mode>3_soft): Likewise.
- * config/rs6000/vector.md (vector_copysign<mode>3): Use copysign RTL
- instead of UNSPEC.
- * config/rs6000/vsx.md (vsx_copysign<mode>3): Use copysign RTL instead
- of UNSPEC.
-
-2023-10-02 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-json.cc (toplevel_array): Remove global in
- favor of json_output_format::m_top_level_array.
- (cur_group): Likewise, for json_output_format::m_cur_group.
- (cur_children_array): Likewise, for
- json_output_format::m_cur_children_array.
- (class json_output_format): New.
- (json_begin_diagnostic): Remove, in favor of
- json_output_format::on_begin_diagnostic.
- (json_end_diagnostic): Convert to...
- (json_output_format::on_end_diagnostic): ...this.
- (json_begin_group): Remove, in favor of
- json_output_format::on_begin_group.
- (json_end_group): Remove, in favor of
- json_output_format::on_end_group.
- (json_flush_to_file): Remove, in favor of
- json_output_format::flush_to_file.
- (json_stderr_final_cb): Remove, in favor of json_output_format
- dtor.
- (json_output_base_file_name): Remove global.
- (class json_stderr_output_format): New.
- (json_file_final_cb): Remove.
- (class json_file_output_format): New.
- (json_emit_diagram): Remove.
- (diagnostic_output_format_init_json): Update.
- (diagnostic_output_format_init_json_file): Update.
- * diagnostic-format-sarif.cc (the_builder): Remove this global,
- moving to a field of the sarif_output_format.
- (sarif_builder::maybe_make_artifact_content_object): Use the
- context's m_file_cache.
- (get_source_lines): Convert to...
- (sarif_builder::get_source_lines): ...this, using context's
- m_file_cache.
- (sarif_begin_diagnostic): Remove, in favor of
- sarif_output_format::on_begin_diagnostic.
- (sarif_end_diagnostic): Remove, in favor of
- sarif_output_format::on_end_diagnostic.
- (sarif_begin_group): Remove, in favor of
- sarif_output_format::on_begin_group.
- (sarif_end_group): Remove, in favor of
- sarif_output_format::on_end_group.
- (sarif_flush_to_file): Delete.
- (sarif_stderr_final_cb): Delete.
- (sarif_output_base_file_name): Delete.
- (sarif_file_final_cb): Delete.
- (class sarif_output_format): New.
- (sarif_emit_diagram): Delete.
- (class sarif_stream_output_format): New.
- (class sarif_file_output_format): New.
- (diagnostic_output_format_init_sarif): Update.
- (diagnostic_output_format_init_sarif_stderr): Update.
- (diagnostic_output_format_init_sarif_file): Update.
- (diagnostic_output_format_init_sarif_stream): Update.
- * diagnostic-show-locus.cc (diagnostic_show_locus): Update.
- * diagnostic.cc (default_diagnostic_final_cb): Delete, moving to
- diagnostic_text_output_format's dtor.
- (diagnostic_initialize): Update, making a new instance of
- diagnostic_text_output_format.
- (diagnostic_finish): Delete m_output_format, rather than calling
- final_cb.
- (diagnostic_report_diagnostic): Assert that m_output_format is
- non-NULL. Replace call to begin_group_cb with call to
- m_output_format->on_begin_group. Replace call to
- diagnostic_starter with call to
- m_output_format->on_begin_diagnostic. Replace call to
- diagnostic_finalizer with call to
- m_output_format->on_end_diagnostic.
- (diagnostic_emit_diagram): Replace both optional call to
- m_diagrams.m_emission_cb and default implementation with call to
- m_output_format->on_diagram. Move default implementation to
- diagnostic_text_output_format::on_diagram.
- (auto_diagnostic_group::~auto_diagnostic_group): Replace call to
- end_group_cb with call to m_output_format->on_end_group.
- (diagnostic_text_output_format::~diagnostic_text_output_format):
- New, based on default_diagnostic_final_cb.
- (diagnostic_text_output_format::on_begin_diagnostic): New, based
- on code from diagnostic_report_diagnostic.
- (diagnostic_text_output_format::on_end_diagnostic): Likewise.
- (diagnostic_text_output_format::on_diagram): New, based on code
- from diagnostic_emit_diagram.
- * diagnostic.h (class diagnostic_output_format): New.
- (class diagnostic_text_output_format): New.
- (diagnostic_context::begin_diagnostic): Move to...
- (diagnostic_context::m_text_callbacks::begin_diagnostic): ...here.
- (diagnostic_context::start_span): Move to...
- (diagnostic_context::m_text_callbacks::start_span): ...here.
- (diagnostic_context::end_diagnostic): Move to...
- (diagnostic_context::m_text_callbacks::end_diagnostic): ...here.
- (diagnostic_context::begin_group_cb): Remove, in favor of
- m_output_format->on_begin_group.
- (diagnostic_context::end_group_cb): Remove, in favor of
- m_output_format->on_end_group.
- (diagnostic_context::final_cb): Remove, in favor of
- m_output_format's dtor.
- (diagnostic_context::m_output_format): New field.
- (diagnostic_context::m_diagrams.m_emission_cb): Remove, in favor
- of m_output_format->on_diagram.
- (diagnostic_starter): Update.
- (diagnostic_finalizer): Update.
- (diagnostic_output_format_init_sarif_stream): New.
- * input.cc (location_get_source_line): Move implementation apart from
- call to diagnostic_file_cache_init to...
- (file_cache::get_source_line): ...this new function...
- (location_get_source_line): ...and reintroduce, rewritten in terms of
- file_cache::get_source_line.
- (get_source_file_content): Likewise, refactor into...
- (file_cache::get_source_file_content): ...this new function.
- * input.h (file_cache::get_source_line): New decl.
- (file_cache::get_source_file_content): New decl.
- * selftest-diagnostic.cc
- (test_diagnostic_context::test_diagnostic_context): Update.
- * tree-diagnostic-path.cc (event_range::print): Update for
- change to diagnostic_context's start_span callback.
-
-2023-10-02 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc: Update for reorganization of
- source-printing fields of diagnostic_context.
- * diagnostic.cc (diagnostic_set_caret_max_width): Likewise.
- (diagnostic_initialize): Likewise.
- * diagnostic.h (diagnostic_context::show_caret): Move to...
- (diagnostic_context::m_source_printing::enabled): ...here.
- (diagnostic_context::caret_max_width): Move to...
- (diagnostic_context::m_source_printing::max_width): ...here.
- (diagnostic_context::caret_chars): Move to...
- (diagnostic_context::m_source_printing::caret_chars): ...here.
- (diagnostic_context::colorize_source_p): Move to...
- (diagnostic_context::m_source_printing::colorize_source_p): ...here.
- (diagnostic_context::show_labels_p): Move to...
- (diagnostic_context::m_source_printing::show_labels_p): ...here.
- (diagnostic_context::show_line_numbers_p): Move to...
- (diagnostic_context::m_source_printing::show_line_numbers_p): ...here.
- (diagnostic_context::min_margin_width): Move to...
- (diagnostic_context::m_source_printing::min_margin_width): ...here.
- (diagnostic_context::show_ruler_p): Move to...
- (diagnostic_context::m_source_printing::show_ruler_p): ...here.
- (diagnostic_same_line): Update for above changes.
- * opts.cc (common_handle_option): Update for reorganization of
- source-printing fields of diagnostic_context.
- * selftest-diagnostic.cc
- (test_diagnostic_context::test_diagnostic_context): Likewise.
- * toplev.cc (general_init): Likewise.
- * tree-diagnostic-path.cc (struct event_range): Likewise.
-
-2023-10-02 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_initialize): Initialize
- set_locations_cb to nullptr.
-
-2023-10-02 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- PR target/111235
- * config/arm/constraints.md: Remove Pf constraint.
- * config/arm/sync.md (arm_atomic_load<mode>): Add new pattern.
- (arm_atomic_load_acquire<mode>): Likewise.
- (arm_atomic_store<mode>): Likewise.
- (arm_atomic_store_release<mode>): Likewise.
- (atomic_load<mode>): Switch patterns to define_expand.
- (atomic_store<mode>): Likewise.
- (arm_atomic_loaddi2_ldrd): Remove predication.
- (arm_load_exclusive<mode>): Likewise.
- (arm_load_acquire_exclusive<mode>): Likewise.
- (arm_load_exclusivesi): Likewise.
- (arm_load_acquire_exclusivesi): Likewise.
- (arm_load_exclusivedi): Likewise.
- (arm_load_acquire_exclusivedi): Likewise.
- (arm_store_exclusive<mode>): Likewise.
- (arm_store_release_exclusivedi): Likewise.
- (arm_store_release_exclusive<mode>): Likewise.
- * config/arm/unspecs.md: Add VUNSPEC_LDR and VUNSPEC_STR.
-
-2023-10-02 Tamar Christina <tamar.christina@arm.com>
-
- Revert:
- 2023-10-02 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * tree-if-conv.cc (INCLUDE_ALGORITHM): Remove.
- (cmp_arg_entry): New.
- (predicate_scalar_phi): Use it.
-
-2023-10-02 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-simd.md (xorsign<mode>3): Renamed to..
- (@xorsign<mode>3): ...This.
- * config/aarch64/aarch64.md (xorsign<mode>3): Renamed to...
- (@xorsign<mode>3): ..This and emit vectors directly
- * config/aarch64/iterators.md (VCONQ): Add SF and DF.
-
-2023-10-02 Tamar Christina <tamar.christina@arm.com>
-
- * emit-rtl.cc (validate_subreg): Relax subreg rule.
-
-2023-10-02 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * tree-if-conv.cc (INCLUDE_ALGORITHM): Remove.
- (cmp_arg_entry): New.
- (predicate_scalar_phi): Use it.
-
-2023-10-02 Richard Sandiford <richard.sandiford@arm.com>
-
- PR bootstrap/111642
- * rtl-tests.cc (const_poly_int_tests<N>::run): Use a local
- poly_int64 typedef.
- * simplify-rtx.cc (simplify_const_poly_int_tests<N>::run): Likewise.
-
-2023-10-02 Joern Rennecke <joern.rennecke@embecosm.com>
- Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (riscv_vector::expand_block_move):
- Declare.
- * config/riscv/riscv-v.cc (riscv_vector::expand_block_move):
- New function.
- * config/riscv/riscv.md (cpymemsi): Use riscv_vector::expand_block_move.
- Change to ..
- (cpymem<P:mode>) .. this.
-
-2023-10-01 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * combine.cc (simplify_compare_const): Properly handle unsigned
- constants while narrowing comparison of memory and constants.
-
-2023-10-01 Feng Wang <wangfeng@eswincomputing.com>
-
- * config/riscv/riscv-opts.h (MASK_ZICSR): Delete.
- (MASK_ZIFENCEI): Delete;
- (MASK_ZIHINTNTL): Ditto.
- (MASK_ZIHINTPAUSE): Ditto.
- (TARGET_ZICSR): Ditto.
- (TARGET_ZIFENCEI): Ditto.
- (TARGET_ZIHINTNTL): Ditto.
- (TARGET_ZIHINTPAUSE): Ditto.
- (MASK_ZAWRS): Ditto.
- (TARGET_ZAWRS): Ditto.
- (MASK_ZBA): Ditto.
- (MASK_ZBB): Ditto.
- (MASK_ZBC): Ditto.
- (MASK_ZBS): Ditto.
- (TARGET_ZBA): Ditto.
- (TARGET_ZBB): Ditto.
- (TARGET_ZBC): Ditto.
- (TARGET_ZBS): Ditto.
- (MASK_ZFINX): Ditto.
- (MASK_ZDINX): Ditto.
- (MASK_ZHINX): Ditto.
- (MASK_ZHINXMIN): Ditto.
- (TARGET_ZFINX): Ditto.
- (TARGET_ZDINX): Ditto.
- (TARGET_ZHINX): Ditto.
- (TARGET_ZHINXMIN): Ditto.
- (MASK_ZBKB): Ditto.
- (MASK_ZBKC): Ditto.
- (MASK_ZBKX): Ditto.
- (MASK_ZKNE): Ditto.
- (MASK_ZKND): Ditto.
- (MASK_ZKNH): Ditto.
- (MASK_ZKR): Ditto.
- (MASK_ZKSED): Ditto.
- (MASK_ZKSH): Ditto.
- (MASK_ZKT): Ditto.
- (TARGET_ZBKB): Ditto.
- (TARGET_ZBKC): Ditto.
- (TARGET_ZBKX): Ditto.
- (TARGET_ZKNE): Ditto.
- (TARGET_ZKND): Ditto.
- (TARGET_ZKNH): Ditto.
- (TARGET_ZKR): Ditto.
- (TARGET_ZKSED): Ditto.
- (TARGET_ZKSH): Ditto.
- (TARGET_ZKT): Ditto.
- (MASK_ZTSO): Ditto.
- (TARGET_ZTSO): Ditto.
- (MASK_VECTOR_ELEN_32): Ditto.
- (MASK_VECTOR_ELEN_64): Ditto.
- (MASK_VECTOR_ELEN_FP_32): Ditto.
- (MASK_VECTOR_ELEN_FP_64): Ditto.
- (MASK_VECTOR_ELEN_FP_16): Ditto.
- (TARGET_VECTOR_ELEN_32): Ditto.
- (TARGET_VECTOR_ELEN_64): Ditto.
- (TARGET_VECTOR_ELEN_FP_32): Ditto.
- (TARGET_VECTOR_ELEN_FP_64): Ditto.
- (TARGET_VECTOR_ELEN_FP_16): Ditto.
- (MASK_ZVBB): Ditto.
- (MASK_ZVBC): Ditto.
- (TARGET_ZVBB): Ditto.
- (TARGET_ZVBC): Ditto.
- (MASK_ZVKG): Ditto.
- (MASK_ZVKNED): Ditto.
- (MASK_ZVKNHA): Ditto.
- (MASK_ZVKNHB): Ditto.
- (MASK_ZVKSED): Ditto.
- (MASK_ZVKSH): Ditto.
- (MASK_ZVKN): Ditto.
- (MASK_ZVKNC): Ditto.
- (MASK_ZVKNG): Ditto.
- (MASK_ZVKS): Ditto.
- (MASK_ZVKSC): Ditto.
- (MASK_ZVKSG): Ditto.
- (MASK_ZVKT): Ditto.
- (TARGET_ZVKG): Ditto.
- (TARGET_ZVKNED): Ditto.
- (TARGET_ZVKNHA): Ditto.
- (TARGET_ZVKNHB): Ditto.
- (TARGET_ZVKSED): Ditto.
- (TARGET_ZVKSH): Ditto.
- (TARGET_ZVKN): Ditto.
- (TARGET_ZVKNC): Ditto.
- (TARGET_ZVKNG): Ditto.
- (TARGET_ZVKS): Ditto.
- (TARGET_ZVKSC): Ditto.
- (TARGET_ZVKSG): Ditto.
- (TARGET_ZVKT): Ditto.
- (MASK_ZVL32B): Ditto.
- (MASK_ZVL64B): Ditto.
- (MASK_ZVL128B): Ditto.
- (MASK_ZVL256B): Ditto.
- (MASK_ZVL512B): Ditto.
- (MASK_ZVL1024B): Ditto.
- (MASK_ZVL2048B): Ditto.
- (MASK_ZVL4096B): Ditto.
- (MASK_ZVL8192B): Ditto.
- (MASK_ZVL16384B): Ditto.
- (MASK_ZVL32768B): Ditto.
- (MASK_ZVL65536B): Ditto.
- (TARGET_ZVL32B): Ditto.
- (TARGET_ZVL64B): Ditto.
- (TARGET_ZVL128B): Ditto.
- (TARGET_ZVL256B): Ditto.
- (TARGET_ZVL512B): Ditto.
- (TARGET_ZVL1024B): Ditto.
- (TARGET_ZVL2048B): Ditto.
- (TARGET_ZVL4096B): Ditto.
- (TARGET_ZVL8192B): Ditto.
- (TARGET_ZVL16384B): Ditto.
- (TARGET_ZVL32768B): Ditto.
- (TARGET_ZVL65536B): Ditto.
- (MASK_ZICBOZ): Ditto.
- (MASK_ZICBOM): Ditto.
- (MASK_ZICBOP): Ditto.
- (TARGET_ZICBOZ): Ditto.
- (TARGET_ZICBOM): Ditto.
- (TARGET_ZICBOP): Ditto.
- (MASK_ZICOND): Ditto.
- (TARGET_ZICOND): Ditto.
- (MASK_ZFA): Ditto.
- (TARGET_ZFA): Ditto.
- (MASK_ZFHMIN): Ditto.
- (MASK_ZFH): Ditto.
- (MASK_ZVFHMIN): Ditto.
- (MASK_ZVFH): Ditto.
- (TARGET_ZFHMIN): Ditto.
- (TARGET_ZFH): Ditto.
- (TARGET_ZVFHMIN): Ditto.
- (TARGET_ZVFH): Ditto.
- (MASK_ZMMUL): Ditto.
- (TARGET_ZMMUL): Ditto.
- (MASK_ZCA): Ditto.
- (MASK_ZCB): Ditto.
- (MASK_ZCE): Ditto.
- (MASK_ZCF): Ditto.
- (MASK_ZCD): Ditto.
- (MASK_ZCMP): Ditto.
- (MASK_ZCMT): Ditto.
- (TARGET_ZCA): Ditto.
- (TARGET_ZCB): Ditto.
- (TARGET_ZCE): Ditto.
- (TARGET_ZCF): Ditto.
- (TARGET_ZCD): Ditto.
- (TARGET_ZCMP): Ditto.
- (TARGET_ZCMT): Ditto.
- (MASK_SVINVAL): Ditto.
- (MASK_SVNAPOT): Ditto.
- (TARGET_SVINVAL): Ditto.
- (TARGET_SVNAPOT): Ditto.
- (MASK_XTHEADBA): Ditto.
- (MASK_XTHEADBB): Ditto.
- (MASK_XTHEADBS): Ditto.
- (MASK_XTHEADCMO): Ditto.
- (MASK_XTHEADCONDMOV): Ditto.
- (MASK_XTHEADFMEMIDX): Ditto.
- (MASK_XTHEADFMV): Ditto.
- (MASK_XTHEADINT): Ditto.
- (MASK_XTHEADMAC): Ditto.
- (MASK_XTHEADMEMIDX): Ditto.
- (MASK_XTHEADMEMPAIR): Ditto.
- (MASK_XTHEADSYNC): Ditto.
- (TARGET_XTHEADBA): Ditto.
- (TARGET_XTHEADBB): Ditto.
- (TARGET_XTHEADBS): Ditto.
- (TARGET_XTHEADCMO): Ditto.
- (TARGET_XTHEADCONDMOV): Ditto.
- (TARGET_XTHEADFMEMIDX): Ditto.
- (TARGET_XTHEADFMV): Ditto.
- (TARGET_XTHEADINT): Ditto.
- (TARGET_XTHEADMAC): Ditto.
- (TARGET_XTHEADMEMIDX): Ditto.
- (TARGET_XTHEADMEMPAIR): Ditto.
- (TARGET_XTHEADSYNC): Ditto.
- (MASK_XVENTANACONDOPS): Ditto.
- (TARGET_XVENTANACONDOPS): Ditto.
- * config/riscv/riscv.opt: Add new Mask defination.
- * doc/options.texi: Add explanation for this new usage.
- * opt-functions.awk: Add new function to find the index
- of target variable from extra_target_vars.
- * opt-read.awk: Add new function to store the Mask flags.
- * opth-gen.awk: Add new function to output the defination of
- Mask Macro and Target Macro.
-
-2023-10-01 Joern Rennecke <joern.rennecke@embecosm.com>
- Juzhe-Zhong <juzhe.zhong@rivai.ai>
- Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111566
- * config/riscv/riscv-protos.h (riscv_vector::legitimize_move):
- Change second parameter to rtx *.
- * config/riscv/riscv-v.cc (risv_vector::legitimize_move): Likewise.
- * config/riscv/vector.md: Changed callers of
- riscv_vector::legitimize_move.
- (*mov<mode>_mem_to_mem): Remove.
-
-2023-09-30 Jakub Jelinek <jakub@redhat.com>
-
- PR target/111649
- * config/riscv/riscv-vsetvl.cc (vector_infos_manager::vector_infos_manager):
- Replace safe_grow with safe_grow_cleared.
-
-2023-09-30 Jakub Jelinek <jakub@redhat.com>
-
- * gimple-match-head.cc (gimple_bitwise_inverted_equal_p): Fix a pasto
- in function comment.
-
-2023-09-30 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/111625
- PR middle-end/111637
- * gimple-lower-bitint.cc (range_to_prec): Use prec or -prec if
- r.undefined_p ().
- (bitint_large_huge::handle_operand_addr): For uninitialized operands
- use limb_prec or -limb_prec precision.
-
-2023-09-30 Jakub Jelinek <jakub@redhat.com>
-
- * vec.h (quick_grow): Uncomment static_assert.
-
-2023-09-30 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * config/riscv/bitmanip.md (*<optab>_not_const<mode>): Added type attribute
-
-2023-09-29 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_rtx_costs): Better handle costing
- SETs when the outer code is INSN.
-
-2023-09-29 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * config/riscv/bitmanip.md (*<optab>_not_const<mode>): New split
- pattern.
-
-2023-09-29 Richard Sandiford <richard.sandiford@arm.com>
-
- * poly-int.h (poly_int_pod): Delete.
- (poly_coeff_traits::init_cast): New type.
- (poly_int_full, poly_int_hungry, poly_int_fullness): New structures.
- (poly_int): Replace constructors that take 1 and 2 coefficients with
- a general one that takes an arbitrary number of coefficients.
- Delegate initialization to two new private constructors, one of
- which uses the coefficients as-is and one of which adds an extra
- zero of the appropriate type (and precision, where applicable).
- (gt_ggc_mx, gt_pch_nx): Operate on poly_ints rather than poly_int_pods.
- * poly-int-types.h (poly_uint16_pod, poly_int64_pod, poly_uint64_pod)
- (poly_offset_int_pod, poly_wide_int_pod, poly_widest_int_pod): Delete.
- * gengtype.cc (main): Don't register poly_int64_pod.
- * calls.cc (initialize_argument_information): Use poly_int rather
- than poly_int_pod.
- (combine_pending_stack_adjustment_and_call): Likewise.
- * config/aarch64/aarch64.cc (pure_scalable_type_info): Likewise.
- * data-streamer.h (bp_unpack_poly_value): Likewise.
- * dwarf2cfi.cc (struct dw_trace_info): Likewise.
- (struct queued_reg_save): Likewise.
- * dwarf2out.h (struct dw_cfa_location): Likewise.
- * emit-rtl.h (struct incoming_args): Likewise.
- (struct rtl_data): Likewise.
- * expr.cc (get_bit_range): Likewise.
- (get_inner_reference): Likewise.
- * expr.h (get_bit_range): Likewise.
- * fold-const.cc (split_address_to_core_and_offset): Likewise.
- (ptr_difference_const): Likewise.
- * fold-const.h (ptr_difference_const): Likewise.
- * function.cc (try_fit_stack_local): Likewise.
- (instantiate_new_reg): Likewise.
- * function.h (struct expr_status): Likewise.
- (struct args_size): Likewise.
- * genmodes.cc (ZERO_COEFFS): Likewise.
- (mode_size_inline): Likewise.
- (mode_nunits_inline): Likewise.
- (emit_mode_precision): Likewise.
- (emit_mode_size): Likewise.
- (emit_mode_nunits): Likewise.
- * gimple-fold.cc (get_base_constructor): Likewise.
- * gimple-ssa-store-merging.cc (struct symbolic_number): Likewise.
- * inchash.h (class hash): Likewise.
- * ipa-modref-tree.cc (modref_access_node::dump): Likewise.
- * ipa-modref.cc (modref_access_analysis::merge_call_side_effects):
- Likewise.
- * ira-int.h (ira_spilled_reg_stack_slot): Likewise.
- * lra-eliminations.cc (self_elim_offsets): Likewise.
- * machmode.h (mode_size, mode_precision, mode_nunits): Likewise.
- * omp-low.cc (omplow_simd_context): Likewise.
- * pretty-print.cc (pp_wide_integer): Likewise.
- * pretty-print.h (pp_wide_integer): Likewise.
- * reload.cc (struct decomposition): Likewise.
- * reload.h (struct reload): Likewise.
- * reload1.cc (spill_stack_slot_width): Likewise.
- (struct elim_table): Likewise.
- (offsets_at): Likewise.
- (init_eliminable_invariants): Likewise.
- * rtl.h (union rtunion): Likewise.
- (poly_int_rtx_p): Likewise.
- (strip_offset): Likewise.
- (strip_offset_and_add): Likewise.
- * rtlanal.cc (strip_offset): Likewise.
- * tree-dfa.cc (get_ref_base_and_extent): Likewise.
- (get_addr_base_and_unit_offset_1): Likewise.
- (get_addr_base_and_unit_offset): Likewise.
- * tree-dfa.h (get_ref_base_and_extent): Likewise.
- (get_addr_base_and_unit_offset_1): Likewise.
- (get_addr_base_and_unit_offset): Likewise.
- * tree-ssa-loop-ivopts.cc (struct iv_use): Likewise.
- (strip_offset): Likewise.
- * tree-ssa-sccvn.h (struct vn_reference_op_struct): Likewise.
- * tree.cc (ptrdiff_tree_p): Likewise.
- * tree.h (poly_int_tree_p): Likewise.
- (ptrdiff_tree_p): Likewise.
- (get_inner_reference): Likewise.
-
-2023-09-29 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa.md (memory_barrier): Revise comment.
- (memory_barrier_64, memory_barrier_32): Use ldcw,co on PA 2.0.
- * config/pa/pa.opt (coherent-ldcw): Change default to disabled.
-
-2023-09-29 Jakub Jelinek <jakub@redhat.com>
-
- * vec.h (quick_insert, ordered_remove, unordered_remove,
- block_remove, qsort, sort, stablesort, quick_grow): Guard
- std::is_trivially_{copyable,default_constructible} and
- vec_detail::is_trivially_copyable_or_pair static assertions
- with GCC_VERSION >= 5000.
- (vec_detail::is_trivially_copyable_or_pair): Guard definition
- with GCC_VERSION >= 5000.
-
-2023-09-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
-
- * config/aarch64/aarch64-opts.h (enum aarch64_ldp_policy): Removed.
- (enum aarch64_ldp_stp_policy): Merged enums aarch64_ldp_policy
- and aarch64_stp_policy to aarch64_ldp_stp_policy.
- (enum aarch64_stp_policy): Removed.
- * config/aarch64/aarch64-protos.h (struct tune_params): Removed
- aarch64_ldp_policy_model and aarch64_stp_policy_model enum types
- and left only the definitions to the aarch64-opts one.
- * config/aarch64/aarch64.cc (aarch64_parse_ldp_policy): Removed.
- (aarch64_parse_stp_policy): Removed.
- (aarch64_override_options_internal): Removed calls to parsing
- functions and added obvious direct assignments.
- (aarch64_mem_ok_with_ldpstp_policy_model): Improved
- code quality based on the new changes.
- * config/aarch64/aarch64.opt: Use single enum type
- aarch64_ldp_stp_policy for both ldp and stp options.
-
-2023-09-29 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111583
- * tree-loop-distribution.cc (find_single_drs): Ensure the
- load/store are always executed.
-
-2023-09-29 Jakub Jelinek <jakub@redhat.com>
-
- * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Use
- quick_grow_cleared method on unprom rather than quick_grow.
-
-2023-09-29 Sergei Trofimovich <siarheit@google.com>
-
- PR middle-end/111505
- * ggc-common.cc (ggc_zero_out_root_pointers, ggc_common_finalize):
- Add new helper. Use helper instead of memset() to wipe out pointers.
-
-2023-09-29 Richard Sandiford <richard.sandiford@arm.com>
-
- * builtins.h (c_readstr): Take a fixed_size_mode rather than a
- scalar_int_mode.
- * builtins.cc (c_readstr): Likewise. Build a local array of
- bytes and use native_decode_rtx to get the rtx image.
- (builtin_memcpy_read_str): Simplify accordingly.
- (builtin_strncpy_read_str): Likewise.
- (builtin_memset_read_str): Likewise.
- (builtin_memset_gen_str): Likewise.
- * expr.cc (string_cst_read_str): Likewise.
-
-2023-09-29 Jakub Jelinek <jakub@redhat.com>
-
- * tree-ssa-loop-im.cc (tree_ssa_lim_initialize): Use quick_grow_cleared
- instead of quick_grow on vec<bitmap_head> members.
- * cfganal.cc (control_dependences::control_dependences): Likewise.
- * rtl-ssa/blocks.cc (function_info::build_info::build_info): Likewise.
- (function_info::place_phis): Use safe_grow_cleared instead of safe_grow
- on auto_vec<bitmap_head> vars.
- * tree-ssa-live.cc (compute_live_vars): Use quick_grow_cleared instead
- of quick_grow on vec<bitmap_head> var.
-
-2023-09-28 Vladimir N. Makarov <vmakarov@redhat.com>
-
- Revert:
- 2023-09-14 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * ira-costs.cc (find_costs_and_classes): Decrease memory cost
- by equiv savings.
-
-2023-09-28 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- PR target/111121
- * config/aarch64/aarch64.md (aarch64_movmemdi): Add new expander.
- (movmemdi): Call aarch64_expand_cpymem_mops for correct expansion.
- * config/aarch64/aarch64.cc (aarch64_expand_cpymem_mops): Add support
- for memmove.
- * config/aarch64/aarch64-protos.h (aarch64_expand_cpymem_mops): Add new
- function.
-
-2023-09-28 Pan Li <pan2.li@intel.com>
-
- PR target/111506
- * config/riscv/autovec.md (<float_cvt><mode><vnnconvert>2):
- New pattern.
- * config/riscv/vector-iterators.md: New iterator.
-
-2023-09-28 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * rtl.h (lra_in_progress): Change type to bool.
- (ira_in_progress): Add new extern.
- * ira.cc (ira_in_progress): New global.
- (pass_ira::execute): Set up ira_in_progress.
- * lra.cc: (lra_in_progress): Change type to bool and initialize.
- (lra): Use bool values for lra_in_progress.
- * lra-eliminations.cc (init_elim_table): Ditto.
-
-2023-09-28 Richard Biener <rguenther@suse.de>
-
- PR target/111600
- * gimple-ssa-warn-access.cc (pass_waccess::check_dangling_stores):
- Use a heap allocated worklist for CFG traversal instead of
- recursion.
-
-2023-09-28 Jakub Jelinek <jakub@redhat.com>
- Jonathan Wakely <jwakely@redhat.com>
-
- * vec.h: Mention in file comment limited support for non-POD types
- in some operations.
- (vec_destruct): New function template.
- (release): Use it for non-trivially destructible T.
- (truncate): Likewise.
- (quick_push): Perform a placement new into slot
- instead of assignment.
- (pop): For non-trivially destructible T return void
- rather than T & and destruct the popped element.
- (quick_insert, ordered_remove): Note that they aren't suitable
- for non-trivially copyable types. Add static_asserts for that.
- (block_remove): Assert T is trivially copyable.
- (vec_detail::is_trivially_copyable_or_pair): New trait.
- (qsort, sort, stablesort): Assert T is trivially copyable or
- std::pair with both trivally copyable types.
- (quick_grow): Add assert T is trivially default constructible,
- for now commented out.
- (quick_grow_cleared): Don't call quick_grow, instead inline it
- by hand except for the new static_assert.
- (gt_ggc_mx): Assert T is trivially destructable.
- (auto_vec::operator=): Formatting fixes.
- (auto_vec::auto_vec): Likewise.
- (vec_safe_grow_cleared): Don't call vec_safe_grow, instead inline
- it manually and call quick_grow_cleared method rather than quick_grow.
- (safe_grow_cleared): Likewise.
- * edit-context.cc (class line_event): Move definition earlier.
- * tree-ssa-loop-im.cc (seq_entry::seq_entry): Make default ctor
- defaulted.
- * ipa-fnsummary.cc (evaluate_properties_for_edge): Use
- safe_grow_cleared instead of safe_grow followed by placement new
- constructing the elements.
-
-2023-09-28 Richard Sandiford <richard.sandiford@arm.com>
-
- * dwarf2out.cc (mem_loc_descriptor): Remove unused variables.
- * tree-affine.cc (expr_to_aff_combination): Likewise.
-
-2023-09-28 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111614
- * tree-ssa-reassoc.cc (undistribute_bitref_for_vector): Properly
- convert the first vector when required.
-
-2023-09-28 xuli <xuli1@eswincomputing.com>
-
- PR target/111533
- * config/riscv/riscv-v.cc (expand_const_vector): Fix bug.
- * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug.
-
-2023-09-27 Sandra Loosemore <sandra@codesourcery.com>
-
- * gimple.cc (gimple_copy): Add case GIMPLE_OMP_STRUCTURED_BLOCK.
-
-2023-09-27 Iain Sandoe <iain@sandoe.co.uk>
-
- PR target/111610
- * configure: Regenerate.
- * configure.ac: Rename the missing dsymutil case to "DET_UNKNOWN".
-
-2023-09-27 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
- Philipp Tomsich <philipp.tomsich@vrull.eu>
- Manolis Tsamis <manolis.tsamis@vrull.eu>
-
- * config/aarch64/aarch64-opts.h (enum aarch64_ldp_policy): New
- enum type.
- (enum aarch64_stp_policy): New enum type.
- * config/aarch64/aarch64-protos.h (struct tune_params): Add
- appropriate enums for the policies.
- (aarch64_mem_ok_with_ldpstp_policy_model): New declaration.
- * config/aarch64/aarch64-tuning-flags.def
- (AARCH64_EXTRA_TUNING_OPTION): Remove superseded tuning
- options.
- * config/aarch64/aarch64.cc (aarch64_parse_ldp_policy): New
- function to parse ldp-policy parameter.
- (aarch64_parse_stp_policy): New function to parse stp-policy parameter.
- (aarch64_override_options_internal): Call parsing functions.
- (aarch64_mem_ok_with_ldpstp_policy_model): New function.
- (aarch64_operands_ok_for_ldpstp): Add call to
- aarch64_mem_ok_with_ldpstp_policy_model for parameter-value
- check and alignment check and remove superseded ones.
- (aarch64_operands_adjust_ok_for_ldpstp): Add call to
- aarch64_mem_ok_with_ldpstp_policy_model for parameter-value
- check and alignment check and remove superseded ones.
- * config/aarch64/aarch64.opt (aarch64-ldp-policy): New param.
- (aarch64-stp-policy): New param.
- * doc/invoke.texi: Document the parameters accordingly.
-
-2023-09-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-data-ref.cc (include calls.h): Add new include.
- (get_references_in_stmt): Correctly handle IFN_MASK_CALL.
-
-2023-09-27 Richard Biener <rguenther@suse.de>
-
- * match.pd (abs (copysign (x, y)) -> abs (x)): New pattern.
-
-2023-09-27 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/105606
- * system.h (BROKEN_VALUE_INITIALIZATION): Don't define.
- * vec.h (vec_default_construct): Remove BROKEN_VALUE_INITIALIZATION
- workaround.
- * function.cc (assign_parm_find_data_types): Likewise.
-
-2023-09-27 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (roundeven<mode>2): New pattern.
- * config/riscv/riscv-protos.h (enum insn_flags): New enum type.
- (enum insn_type): Ditto.
- (expand_vec_roundeven): New func decl.
- * config/riscv/riscv-v.cc (expand_vec_roundeven): New func impl.
-
-2023-09-27 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111590
- * dse.cc (find_shift_sequence): Check the mode with access_size exist on the target.
-
-2023-09-27 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-if-conv.cc (is_cond_scalar_reduction): Fix comments.
-
-2023-09-27 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (btrunc<mode>2): New pattern.
- * config/riscv/riscv-protos.h (expand_vec_trunc): New func decl.
- * config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): New func impl.
- (expand_vec_trunc): Ditto.
-
-2023-09-26 Hans-Peter Nilsson <hp@axis.com>
-
- PR target/107567
- PR target/109166
- * builtins.cc (expand_builtin) <case BUILT_IN_ATOMIC_TEST_AND_SET>:
- Handle failure from expand_builtin_atomic_test_and_set.
- * optabs.cc (expand_atomic_test_and_set): When all attempts fail to
- generate atomic code through target support, return NULL
- instead of emitting non-atomic code. Also, for code handling
- targetm.atomic_test_and_set_trueval != 1, gcc_assert result
- from calling emit_store_flag_force instead of returning NULL.
-
-2023-09-26 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/111599
- * value-relation.cc (relation_oracle::valid_equivs): Ensure
- ssa_name is valid.
-
-2023-09-26 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/106164
- PR tree-optimization/111456
- * match.pd (`(A ==/!= B) & (A CMP C)`):
- Support an optional cast on the second A.
- (`(A ==/!= B) | (A CMP C)`): Likewise.
-
-2023-09-26 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111469
- * tree-ssa-phiopt.cc (minmax_replacement): Fix
- the assumption for the `non-diamond` handling cases
- of diamond code.
-
-2023-09-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * match.pd: Optimize COND_ADD reduction pattern.
-
-2023-09-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR tree-optimization/111594
- PR tree-optimization/110660
- * match.pd: Optimize COND_LEN_ADD reduction.
-
-2023-09-26 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (round<mode>2): New pattern.
- * config/riscv/riscv-protos.h (enum insn_flags): New enum type.
- (enum insn_type): Ditto.
- (expand_vec_round): New function decl.
- * config/riscv/riscv-v.cc (expand_vec_round): New function impl.
-
-2023-09-26 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.h (DARWIN_CC1_SPEC): Remove -dynamiclib.
-
-2023-09-26 Tobias Burnus <tobias@codesourcery.com>
-
- PR middle-end/111547
- * doc/invoke.texi (-fopenmp): Mention C++11 [[omp::decl(...)]] syntax.
- (-fopenmp-simd): Likewise. Clarify 'loop' directive semantic.
-
-2023-09-26 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (rint<mode>2): New pattern.
- * config/riscv/riscv-protos.h (expand_vec_rint): New function decl.
- * config/riscv/riscv-v.cc (expand_vec_rint): New function impl.
-
-2023-09-26 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (nearbyint<mode>2): New pattern.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- (expand_vec_nearbyint): New function decl.
- * config/riscv/riscv-v.cc (expand_vec_nearbyint): New func impl.
-
-2023-09-26 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (gen_ceil_const_fp): Remove.
- (get_fp_rounding_coefficient): Rename.
- (gen_floor_const_fp): Remove.
- (expand_vec_ceil): Take renamed func.
- (expand_vec_floor): Ditto.
-
-2023-09-25 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR middle-end/111497
- * lra-constraints.cc (lra_constraints): Copy substituted
- equivalence.
- * lra.cc (lra): Change comment for calling unshare_all_rtl_again.
-
-2023-09-25 Eric Botcazou <ebotcazou@adacore.com>
-
- * gimple-range-gori.cc (gori_compute::logical_combine): Add missing
- return statement in the varying case.
-
-2023-09-25 Xi Ruoyao <xry111@xry111.site>
-
- * doc/invoke.texi: Update -m[no-]explicit-relocs for r14-4160.
-
-2023-09-25 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110386
- * gimple-ssa-backprop.cc (strip_sign_op_1): Remove ABSU_EXPR.
-
-2023-09-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111548
- * config/riscv/riscv-vsetvl.cc (earliest_pred_can_be_fused_p): Bugfix
-
-2023-09-25 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/111366
- * config/rs6000/rs6000.cc (rs6000_update_ipa_fn_target_info): Skip
- empty inline asm.
-
-2023-09-25 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/111380
- * config/rs6000/rs6000.cc (rs6000_can_inline_p): Adopt
- target_option_default_node when the callee has no option
- attributes, also simplify the existing code accordingly.
-
-2023-09-25 Guo Jie <guojie@loongson.cn>
-
- * config/loongarch/lasx.md (lasx_vecinit_merge_<LASX:mode>): New
- pattern for vector construction.
- (vec_set<mode>_internal): Ditto.
- (lasx_xvinsgr2vr_<mode256_i_half>_internal): Ditto.
- (lasx_xvilvl_<lasxfmt_f>_internal): Ditto.
- * config/loongarch/loongarch.cc (loongarch_expand_vector_init):
- Optimized the implementation of vector construction.
- (loongarch_expand_vector_init_same): New function.
- * config/loongarch/lsx.md (lsx_vilvl_<lsxfmt_f>_internal): New
- pattern for vector construction.
- (lsx_vreplvei_mirror_<lsxfmt_f>): New pattern for vector
- construction.
- (vec_concatv2df): Ditto.
- (vec_concatv4sf): Ditto.
-
-2023-09-24 Pan Li <pan2.li@intel.com>
-
- PR target/111546
- * config/riscv/riscv-v.cc
- (expand_vector_init_merge_repeating_sequence): Bugfix
-
-2023-09-24 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111543
- * match.pd (`(X & ~Y) & Y`, `(X | ~Y) | Y`): New patterns.
-
-2023-09-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md: Extend VLS modes
- * config/riscv/vector-iterators.md: Ditto.
-
-2023-09-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md: Add VLS modes for conditional ABS/SQRT.
-
-2023-09-23 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (floor<mode>2): New pattern.
- * config/riscv/riscv-protos.h (enum insn_flags): New enum type.
- (enum insn_type): Ditto.
- (expand_vec_floor): New function decl.
- * config/riscv/riscv-v.cc (gen_floor_const_fp): New function impl.
- (expand_vec_floor): Ditto.
-
-2023-09-22 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (expand_vec_float_cmp_mask): Refactor.
- (emit_vec_float_cmp_mask): Rename.
- (expand_vec_copysign): Ditto.
- (emit_vec_copysign): Ditto.
- (emit_vec_abs): New function impl.
- (emit_vec_cvt_x_f): Ditto.
- (emit_vec_cvt_f_x): Ditto.
- (expand_vec_ceil): Ditto.
-
-2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Extend VLS modes.
-
-2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (gen_const_vector_dup): Use global expand function.
- * config/riscv/vector.md (@vec_duplicate<mode>): Remove @.
- (vec_duplicate<mode>): Ditto.
-
-2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Add VLS conditional patterns.
- * config/riscv/riscv-protos.h (expand_cond_unop): Ditto.
- (expand_cond_binop): Ditto.
- (expand_cond_ternop): Ditto.
- * config/riscv/riscv-v.cc (expand_cond_unop): Ditto.
- (expand_cond_binop): Ditto.
- (expand_cond_ternop): Ditto.
-
-2023-09-22 xuli <xuli1@eswincomputing.com>
-
- PR target/111451
- * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of vrgather.vv
- into vrgatherei16.vv.
-
-2023-09-22 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_widen_reduc_plus_scal_<mode>):
- New combine patterns.
- * config/riscv/riscv-protos.h (enum insn_type): New insn_type.
-
-2023-09-22 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum avl_type): New VLS avl_type.
- * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Move comments.
-
-2023-09-22 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (ceil<mode>2): New pattern.
- * config/riscv/riscv-protos.h (enum insn_flags): New enum type.
- (enum insn_type): Ditto.
- (expand_vec_ceil): New function decl.
- * config/riscv/riscv-v.cc (gen_ceil_const_fp): New function impl.
- (expand_vec_float_cmp_mask): Ditto.
- (expand_vec_copysign): Ditto.
- (expand_vec_ceil): Ditto.
- * config/riscv/vector.md: Add VLS mode support.
-
-2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Extend VLS modes.
-
-2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Extend VLS modes.
-
-2023-09-21 Lehua Ding <lehua.ding@rivai.ai>
- Robin Dapp <rdapp.gcc@gmail.com>
-
- * config/riscv/riscv-v.cc (emit_vlmax_insn): Adjust comments.
- (emit_nonvlmax_insn): Adjust comments.
- (emit_vlmax_insn_lra): Adjust comments.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*linux*): Set rust target_objs, and
- target_has_targetrustm,
- * config/t-linux (linux-rust.o): New rule.
- * config/linux-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (i[34567]86-*-mingw* | x86_64-*-mingw*): Set
- rust_target_objs and target_has_targetrustm.
- * config/t-winnt (winnt-rust.o): New rule.
- * config/winnt-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*-*-fuchsia): Set tmake_rule, rust_target_objs,
- and target_has_targetrustm.
- * config/fuchsia-rust.cc: New file.
- * config/t-fuchsia: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*-*-vxworks*): Set rust_target_objs and
- target_has_targetrustm.
- * config/t-vxworks (vxworks-rust.o): New rule.
- * config/vxworks-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*-*-dragonfly*): Set rust_target_objs and
- target_has_targetrustm.
- * config/t-dragonfly (dragonfly-rust.o): New rule.
- * config/dragonfly-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*-*-solaris2*): Set rust_target_objs and
- target_has_targetrustm.
- * config/t-sol2 (sol2-rust.o): New rule.
- * config/sol2-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*-*-openbsd*): Set rust_target_objs and
- target_has_targetrustm.
- * config/t-openbsd (openbsd-rust.o): New rule.
- * config/openbsd-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*-*-netbsd*): Set rust_target_objs and
- target_has_targetrustm.
- * config/t-netbsd (netbsd-rust.o): New rule.
- * config/netbsd-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*-*-freebsd*): Set rust_target_objs and
- target_has_targetrustm.
- * config/t-freebsd (freebsd-rust.o): New rule.
- * config/freebsd-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config.gcc (*-*-darwin*): Set rust_target_objs and
- target_has_targetrustm.
- * config/t-darwin (darwin-rust.o): New rule.
- * config/darwin-rust.cc: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * config/i386/t-i386 (i386-rust.o): New rule.
- * config/i386/i386-rust.cc: New file.
- * config/i386/i386-rust.h: New file.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in: Document TARGET_RUST_OS_INFO.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in: Add @node for Rust language and ABI, and document
- TARGET_RUST_CPU_INFO.
-
-2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org>
-
- * Makefile.in (tm_rust_file_list, tm_rust_include_list, TM_RUST_H,
- RUST_TARGET_DEF, RUST_TARGET_H, RUST_TARGET_OBJS): New variables.
- (tm_rust.h, cs-tm_rust.h, default-rust.o,
- rust/rust-target-hooks-def.h, s-rust-target-hooks-def-h): New rules.
- (s-tm-texi): Also check timestamp on rust-target.def.
- (generated_files): Add TM_RUST_H and rust-target-hooks-def.h.
- (build/genhooks.o): Also depend on RUST_TARGET_DEF.
- * config.gcc (tm_rust_file, rust_target_objs, target_has_targetrustm):
- New variables.
- * configure: Regenerate.
- * configure.ac (tm_rust_file_list, tm_rust_include_list,
- rust_target_objs): Add substitutes.
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in (targetrustm): Document.
- (target_has_targetrustm): Document.
- * genhooks.cc: Include rust/rust-target.def.
- * config/default-rust.cc: New file.
-
-2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110751
- * config/riscv/autovec.md: Enable scratch rtx in ELSE operand.
- * config/riscv/predicates.md (autovec_else_operand): New predicate.
- * config/riscv/riscv-v.cc (get_else_operand): New function.
- (expand_cond_len_unop): Adapt ELSE value.
- (expand_cond_len_binop): Ditto.
- (expand_cond_len_ternop): Ditto.
- * config/riscv/riscv.cc (riscv_preferred_else_value): New function.
- (TARGET_PREFERRED_ELSE_VALUE): New targethook.
-
-2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111486
- * config/riscv/riscv.cc (riscv_legitimize_move): Fix bug.
-
-2023-09-21 Jiufu Guo <guojiufu@linux.ibm.com>
-
- PR tree-optimization/111355
- * match.pd ((X + C) / N): Update pattern.
-
-2023-09-21 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * match.pd ((t * 2) / 2): Update to use overflow_free_p.
-
-2023-09-21 xuli <xuli1@eswincomputing.com>
-
- PR target/111450
- * config/riscv/constraints.md (c01): const_int 1.
- (c02): const_int 2.
- (c04): const_int 4.
- (c08): const_int 8.
- * config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for stride operand.
- (vector_eew16_stride_operand): Ditto.
- (vector_eew32_stride_operand): Ditto.
- (vector_eew64_stride_operand): Ditto.
- * config/riscv/vector-iterators.md: New iterator for stride operand.
- * config/riscv/vector.md: Add stride = element width constraint.
-
-2023-09-21 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/predicates.md (const_1_or_2_operand): Rename.
- (const_1_or_4_operand): Ditto.
- (vector_gs_scale_operand_16): Ditto.
- (vector_gs_scale_operand_32): Ditto.
- * config/riscv/vector-iterators.md: Adjust.
-
-2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Extend VLS modes.
- * config/riscv/vector-iterators.md: Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-09-20 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-cache.cc (ssa_cache::merge_range): Change meaning
- of the return value.
- (ssa_cache::dump): Don't print GLOBAL RANGE header.
- (ssa_lazy_cache::merge_range): Adjust return value meaning.
- (ranger_cache::dump): Print GLOBAL RANGE header.
-
-2023-09-20 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (foperator_unordered_ge::fold_range): Remove
- special casing.
- (foperator_unordered_gt::fold_range): Same.
- (foperator_unordered_lt::fold_range): Same.
- (foperator_unordered_le::fold_range): Same.
-
-2023-09-20 Jakub Jelinek <jakub@redhat.com>
-
- * builtins.h (type_to_class): Declare.
- * builtins.cc (type_to_class): No longer static. Return
- int rather than enum.
- * doc/extend.texi (__builtin_classify_type): Document.
-
-2023-09-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110751
- * internal-fn.cc (expand_fn_using_insn): Support undefined rtx value.
- * optabs.cc (maybe_legitimize_operand): Ditto.
- (can_reuse_operands_p): Ditto.
- * optabs.h (enum expand_operand_type): Ditto.
- (create_undefined_input_operand): Ditto.
-
-2023-09-20 Tobias Burnus <tobias@codesourcery.com>
-
- * gimplify.cc (gimplify_bind_expr): Call GOMP_alloc/free for
- 'omp allocate' variables; move stack cleanup after other
- cleanup.
- (omp_notice_variable): Process original decl when decl
- of the value-expression for a 'omp allocate' variable is passed.
- * omp-low.cc (scan_omp_1_op): Handle 'omp allocate' variables
-
-2023-09-20 Yanzhang Wang <yanzhang.wang@intel.com>
-
- * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
- support simplifying vector int not only scalar int.
-
-2023-09-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Extend VLS floating-point.
-
-2023-09-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (vector_insn_info::operator==): Fix bug.
-
-2023-09-20 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.h:
- (SUBTARGET_DRIVER_SELF_SPECS): Move handling of 'shared' into the same
- specs as 'dynamiclib'. (STARTFILE_SPEC): Handle 'shared'.
-
-2023-09-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111489
- * params.opt (-param uninit-max-chain-len=): Raise default to 8.
-
-2023-09-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111489
- * doc/invoke.texi (--param uninit-max-chain-len): Document.
- (--param uninit-max-num-chains): Likewise.
- * params.opt (-param=uninit-max-chain-len=): New.
- (-param=uninit-max-num-chains=): Likewise.
- * gimple-predicate-analysis.cc (MAX_NUM_CHAINS): Define to
- param_uninit_max_num_chains.
- (MAX_CHAIN_LEN): Define to param_uninit_max_chain_len.
- (uninit_analysis::init_use_preds): Avoid VLA.
- (uninit_analysis::init_from_phi_def): Likewise.
- (compute_control_dep_chain): Avoid using MAX_CHAIN_LEN in
- template parameter.
-
-2023-09-20 Jakub Jelinek <jakub@redhat.com>
-
- * match.pd ((x << c) >> c): Use MAX_FIXED_MODE_SIZE instead of
- GET_MODE_PRECISION of TImode or DImode depending on whether
- TImode is supported scalar mode.
- * gimple-lower-bitint.cc (bitint_precision_kind): Likewise.
- * expr.cc (expand_expr_real_1): Likewise.
- * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt): Likewise.
- * ubsan.cc (ubsan_encode_value, ubsan_type_descriptor): Likewise.
-
-2023-09-20 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*<optab>not<mode>): Move and rename.
- (*n<optab><mode>): Ditto.
- (*v<any_shiftrt:optab><any_extend:optab>trunc<mode>): Ditto.
- (*<any_shiftrt:optab>trunc<mode>): Ditto.
- (*narrow_<any_shiftrt:optab><any_extend:optab><mode>): Ditto.
- (*narrow_<any_shiftrt:optab><mode>_scalar): Ditto.
- (*single_widen_mult<any_extend:su><mode>): Ditto.
- (*single_widen_mul<any_extend:su><mode>): Ditto.
- (*single_widen_mult<mode>): Ditto.
- (*single_widen_mul<mode>): Ditto.
- (*dual_widen_fma<mode>): Ditto.
- (*dual_widen_fma<su><mode>): Ditto.
- (*single_widen_fma<mode>): Ditto.
- (*single_widen_fma<su><mode>): Ditto.
- (*dual_fma<mode>): Ditto.
- (*single_fma<mode>): Ditto.
- (*dual_fnma<mode>): Ditto.
- (*dual_widen_fnma<mode>): Ditto.
- (*single_fnma<mode>): Ditto.
- (*single_widen_fnma<mode>): Ditto.
- (*dual_fms<mode>): Ditto.
- (*dual_widen_fms<mode>): Ditto.
- (*single_fms<mode>): Ditto.
- (*single_widen_fms<mode>): Ditto.
- (*dual_fnms<mode>): Ditto.
- (*dual_widen_fnms<mode>): Ditto.
- (*single_fnms<mode>): Ditto.
- (*single_widen_fnms<mode>): Ditto.
-
-2023-09-20 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/111392
- * attribs.cc (decl_attributes): Don't warn on omp::directive attribute
- on vars or function decls if -fopenmp or -fopenmp-simd.
-
-2023-09-20 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/111488
- * config/riscv/autovec-opt.md: Add missed operand.
-
-2023-09-20 Omar Sandoval <osandov@osandov.com>
-
- PR debug/111409
- * dwarf2out.cc (output_macinfo): Don't call optimize_macinfo_range if
- dwarf_split_debug_info.
-
-2023-09-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (can_find_related_mode_p): New function.
- (vectorize_related_mode): Add VLS related modes.
- * config/riscv/vector-iterators.md: Extend VLS modes.
-
-2023-09-20 Surya Kumari Jangala <jskumari@linux.ibm.com>
-
- PR rtl-optimization/110071
- * ira-color.cc (improve_allocation): Consider cost of callee
- save registers.
-
-2023-09-20 mengqinggang <mengqinggang@loongson.cn>
- Xi Ruoyao <xry111@xry111.site>
-
- * configure: Regenerate.
- * configure.ac: Checking assembler for -mno-relax support.
- Disable relaxation when probing leb128 support.
-
-2023-09-20 Lulu Cheng <chenglulu@loongson.cn>
-
- * config.in: Regenerate.
- * config/loongarch/genopts/loongarch.opt.in: Add compilation option
- mrelax. And set the initial value of explicit-relocs according to the
- detection status.
- * config/loongarch/gnu-user.h: When compiling with -mno-relax, pass the
- --no-relax option to the linker.
- * config/loongarch/loongarch-driver.h (ASM_SPEC): When compiling with
- -mno-relax, pass the -mno-relax option to the assembler.
- * config/loongarch/loongarch-opts.h (HAVE_AS_MRELAX_OPTION): Define macro.
- * config/loongarch/loongarch.opt: Regenerate.
- * configure: Regenerate.
- * configure.ac: Add detection of support for binutils relax function.
-
-2023-09-19 Ben Boeckel <ben.boeckel@kitware.com>
-
- * doc/invoke.texi: Document -fdeps-format=, -fdeps-file=, and
- -fdeps-target= flags.
- * gcc.cc: add defaults for -fdeps-target= and -fdeps-file= when
- only -fdeps-format= is specified.
- * json.h: Add a TODO item to refactor out to share with
- `libcpp/mkdeps.cc`.
-
-2023-09-19 Ben Boeckel <ben.boeckel@kitware.com>
- Jason Merrill <jason@redhat.com>
-
- * gcc.cc (join_spec_func): Add a spec function to join all
- arguments.
-
-2023-09-19 Patrick O'Neill <patrick@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_legitimize_const_move): Eliminate
- src_op_0 var to avoid rtl check error.
-
-2023-09-19 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (frelop_early_resolve): Clean-up and remove
- special casing.
- (operator_not_equal::fold_range): Handle VREL_EQ.
- (operator_lt::fold_range): Remove special casing for VREL_EQ.
- (operator_gt::fold_range): Same.
- (foperator_unordered_equal::fold_range): Same.
-
-2023-09-19 Javier Martinez <javier.martinez.bugzilla@gmail.com>
-
- * doc/extend.texi: Document attributes hot, cold on C++ types.
-
-2023-09-19 Pat Haugen <pthaugen@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (rs6000_rtx_costs): Check whether the
- modulo instruction is disabled.
- * config/rs6000/rs6000.h (RS6000_DISABLE_SCALAR_MODULO): New.
- * config/rs6000/rs6000.md (mod<mode>3, *mod<mode>3): Check it.
- (define_expand umod<mode>3): New.
- (define_insn umod<mode>3): Rename to *umod<mode>3 and check if the modulo
- instruction is disabled.
- (umodti3, modti3): Check if the modulo instruction is disabled.
-
-2023-09-19 Gaius Mulley <gaiusmod2@gmail.com>
-
- * doc/gm2.texi (fdebug-builtins): Correct description.
-
-2023-09-19 Jeff Law <jlaw@ventanamicro.com>
-
- * config/iq2000/predicates.md (uns_arith_constant): New predicate.
- * config/iq2000/iq2000.md (rotrsi3): Use it.
-
-2023-09-19 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (operator_lt::op1_range): Remove known_isnan check.
- (operator_lt::op2_range): Same.
- (operator_le::op1_range): Same.
- (operator_le::op2_range): Same.
- (operator_gt::op1_range): Same.
- (operator_gt::op2_range): Same.
- (operator_ge::op1_range): Same.
- (operator_ge::op2_range): Same.
- (foperator_unordered_lt::op1_range): Same.
- (foperator_unordered_lt::op2_range): Same.
- (foperator_unordered_le::op1_range): Same.
- (foperator_unordered_le::op2_range): Same.
- (foperator_unordered_gt::op1_range): Same.
- (foperator_unordered_gt::op2_range): Same.
- (foperator_unordered_ge::op1_range): Same.
- (foperator_unordered_ge::op2_range): Same.
-
-2023-09-19 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (frange::update_nan): New.
-
-2023-09-19 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (operator_not_equal::op2_range): New.
- * range-op-mixed.h: Add operator_not_equal::op2_range.
-
-2023-09-19 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/110080
- PR tree-optimization/110249
- * tree-vrp.cc (remove_unreachable::final_p): New.
- (remove_unreachable::maybe_register): Rename from
- maybe_register_block and call early or final routine.
- (fully_replaceable): New.
- (remove_unreachable::handle_early): New.
- (remove_unreachable::remove_and_update_globals): Remove
- non-final processing.
- (rvrp_folder::rvrp_folder): Add final flag to constructor.
- (rvrp_folder::post_fold_bb): Remove unreachable registration.
- (rvrp_folder::pre_fold_stmt): Move unreachable processing to here.
- (execute_ranger_vrp): Adjust some call parameters.
-
-2023-09-19 Richard Biener <rguenther@suse.de>
-
- PR c/111468
- * tree-pretty-print.h (op_symbol_code): Add defaulted flags
- argument.
- * tree-pretty-print.cc (op_symbol): Likewise.
- (op_symbol_code): Print TDF_GIMPLE variant if requested.
- * gimple-pretty-print.cc (dump_binary_rhs): Pass flags to
- op_symbol_code.
- (dump_gimple_cond): Likewise.
-
-2023-09-19 Thomas Schwinge <thomas@codesourcery.com>
- Pan Li <pan2.li@intel.com>
-
- * tree-streamer.h (bp_unpack_machine_mode): If
- 'ib->file_data->mode_table' not available, apply 1-to-1 mapping.
-
-2023-09-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_can_change_mode_class): Block unordered VLA and VLS modes.
-
-2023-09-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Extend VLS modes.
- * config/riscv/vector.md: Ditto.
-
-2023-09-19 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111465
- * tree-ssa-threadupdate.cc (fwd_jt_path_registry::thread_block_1):
- Cancel the path when a EDGE_NO_COPY_SRC_BLOCK became non-empty.
-
-2023-09-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Extend VLS floating-point modes.
- * config/riscv/vector.md: Ditto.
-
-2023-09-19 Jakub Jelinek <jakub@redhat.com>
-
- * match.pd ((x << c) >> c): Don't call build_nonstandard_integer_type
- nor check type_has_mode_precision_p for width larger than [TD]Imode
- precision.
- (a ? CST1 : CST2): Don't use build_nonstandard_type, just convert
- to type. Use boolean_true_node instead of
- constant_boolean_node (true, boolean_type_node). Formatting fixes.
-
-2023-09-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Add VLS modes.
- * config/riscv/vector.md: Ditto.
-
-2023-09-19 Jakub Jelinek <jakub@redhat.com>
-
- * tree.cc (build_bitint_type): Assert precision is not 0, or
- for signed types 1.
- (signed_or_unsigned_type_for): Return INTEGER_TYPE for signed variant
- of unsigned _BitInt(1).
-
-2023-09-19 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*<optab>_fma<mode>):
- Removed old combine patterns.
- (*single_<optab>mult_plus<mode>): Ditto.
- (*double_<optab>mult_plus<mode>): Ditto.
- (*sign_zero_extend_fma): Ditto.
- (*zero_sign_extend_fma): Ditto.
- (*double_widen_fma<mode>): Ditto.
- (*single_widen_fma<mode>): Ditto.
- (*double_widen_fnma<mode>): Ditto.
- (*single_widen_fnma<mode>): Ditto.
- (*double_widen_fms<mode>): Ditto.
- (*single_widen_fms<mode>): Ditto.
- (*double_widen_fnms<mode>): Ditto.
- (*single_widen_fnms<mode>): Ditto.
- (*reduc_plus_scal_<mode>): Adjust name.
- (*widen_reduc_plus_scal_<mode>): Adjust name.
- (*dual_widen_fma<mode>): New combine pattern.
- (*dual_widen_fmasu<mode>): Ditto.
- (*dual_widen_fmaus<mode>): Ditto.
- (*dual_fma<mode>): Ditto.
- (*single_fma<mode>): Ditto.
- (*dual_fnma<mode>): Ditto.
- (*single_fnma<mode>): Ditto.
- (*dual_fms<mode>): Ditto.
- (*single_fms<mode>): Ditto.
- (*dual_fnms<mode>): Ditto.
- (*single_fnms<mode>): Ditto.
- * config/riscv/autovec.md (fma<mode>4):
- Reafctor fma pattern.
- (*fma<VI:mode><P:mode>): Removed.
- (fnma<mode>4): Reafctor.
- (*fnma<VI:mode><P:mode>): Removed.
- (*fma<VF:mode><P:mode>): Removed.
- (*fnma<VF:mode><P:mode>): Removed.
- (fms<mode>4): Reafctor.
- (*fms<VF:mode><P:mode>): Removed.
- (fnms<mode>4): Reafctor.
- (*fnms<VF:mode><P:mode>): Removed.
- * config/riscv/riscv-protos.h (prepare_ternary_operands):
- Adjust prototype.
- * config/riscv/riscv-v.cc (prepare_ternary_operands): Refactor.
- * config/riscv/vector.md (*pred_mul_plus<mode>_undef): New pattern.
- (*pred_mul_plus<mode>): Removed.
- (*pred_mul_plus<mode>_scalar): Removed.
- (*pred_mul_plus<mode>_extended_scalar): Removed.
- (*pred_minus_mul<mode>_undef): New pattern.
- (*pred_minus_mul<mode>): Removed.
- (*pred_minus_mul<mode>_scalar): Removed.
- (*pred_minus_mul<mode>_extended_scalar): Removed.
- (*pred_mul_<optab><mode>_undef): New pattern.
- (*pred_mul_<optab><mode>): Removed.
- (*pred_mul_<optab><mode>_scalar): Removed.
- (*pred_mul_neg_<optab><mode>_undef): New pattern.
- (*pred_mul_neg_<optab><mode>): Removed.
- (*pred_mul_neg_<optab><mode>_scalar): Removed.
-
-2023-09-19 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * config/riscv/riscv-vector-builtins.cc
- (builtin_decl, expand_builtin): Replace SVE with RVV.
-
-2023-09-19 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * config/riscv/t-riscv: Add dependencies for riscv-builtins.cc,
- riscv-cmo.def and riscv-scalar-crypto.def.
-
-2023-09-18 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Extend to vls mode.
-
-2023-09-18 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Bugfix.
- * config/riscv/riscv-protos.h (SCALAR_MOVE_MERGED_OP): New enum.
-
-2023-09-18 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111442
- * match.pd (zero_one_valued_p): Have the bit_and match not be
- recursive.
-
-2023-09-18 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111435
- * match.pd (zero_one_valued_p): Don't do recursion
- on converts.
-
-2023-09-18 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin-protos.h (enum darwin_external_toolchain): New.
- * config/darwin.cc (DSYMUTIL_VERSION): New.
- (darwin_override_options): Choose the default debug DWARF version
- depending on the configured dsymutil version.
-
-2023-09-18 Iain Sandoe <iain@sandoe.co.uk>
-
- * configure: Regenerate.
- * configure.ac: Handle explict disable of stdlib option, set
- defaults for Darwin.
-
-2023-09-18 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111431
- * match.pd (`(a == CST) & a`): New pattern.
-
-2023-09-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-selftests.cc (run_broadcast_selftests): Adapt selftests.
- * config/riscv/vector.md (@vec_duplicate<mode>): Remove.
-
-2023-09-18 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- PR target/105928
- * config/aarch64/aarch64.cc (aarch64_internal_mov_immediate)
- Add support for immediates using shifted ORR/BIC.
- (aarch64_split_dimode_const_store): Apply if we save one instruction.
- * config/aarch64/aarch64.md (<LOGICAL:optab>_<SHIFT:optab><mode>3):
- Make pattern global.
-
-2023-09-18 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- * config/aarch64/aarch64-cores.def (neoverse-n1): Place before ares.
- (neoverse-v1): Place before zeus.
- (neoverse-v2): Place before demeter.
- * config/aarch64/aarch64-tune.md: Regenerate.
-
-2023-09-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Add VLS modes.
- * config/riscv/vector-iterators.md: Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-09-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (vlmul_for_greatest_sew_second_ratio): New function.
- * config/riscv/riscv-vsetvl.def (DEF_SEW_LMUL_FUSE_RULE): Fix bug.
-
-2023-09-18 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111294
- * tree-ssa-threadbackward.cc (back_threader_profitability::m_name):
- Remove
- (back_threader::find_paths_to_names): Adjust.
- (back_threader::maybe_thread_block): Likewise.
- (back_threader_profitability::possibly_profitable_path_p): Remove
- code applying extra costs to copies PHIs.
-
-2023-09-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Extend VLS modes.
- * config/riscv/vector.md: Ditto.
-
-2023-09-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md (mov<mode>): New pattern.
- (*mov<mode>_mem_to_mem): Ditto.
- (*mov<mode>): Ditto.
- (@mov<VLS_AVL_REG:mode><P:mode>_lra): Ditto.
- (*mov<VLS_AVL_REG:mode><P:mode>_lra): Ditto.
- (*mov<mode>_vls): Ditto.
- (movmisalign<mode>): Ditto.
- (@vec_duplicate<mode>): Ditto.
- * config/riscv/autovec-vls.md: Removed.
-
-2023-09-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111153
- * config/riscv/autovec.md: Add VLS modes.
-
-2023-09-18 Jason Merrill <jason@redhat.com>
-
- * doc/gty.texi: Add discussion of cache vs. deletable.
-
-2023-09-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-vls.md (<optab><mode>3): Deleted.
- (copysign<mode>3): Ditto.
- (xorsign<mode>3): Ditto.
- (<optab><mode>2): Ditto.
- * config/riscv/autovec.md: Extend VLS modes.
-
-2023-09-18 Jiufu Guo <guojiufu@linux.ibm.com>
-
- PR middle-end/111303
- * match.pd ((t * 2) / 2): Update pattern.
-
-2023-09-17 Ajit Kumar Agarwal <aagarwa1@linux.ibm.com>
-
- * config/rs6000/vsx.md (*vctzlsbb_zext_<mode>): New define_insn.
-
-2023-09-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111391
- * config/riscv/autovec.md (@vec_extract<mode><vel>): Remove @.
- (vec_extract<mode><vel>): Ditto.
- * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
- (pass_vsetvl::local_eliminate_vsetvl_insn): Fix bug.
- * config/riscv/riscv.cc (riscv_legitimize_move): Expand VLS mode to scalar mode move.
-
-2023-09-16 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * config/riscv/crypto.md (riscv_sha256sig0_<mode>,
- riscv_sha256sig1_<mode>, riscv_sha256sum0_<mode>,
- riscv_sha256sum1_<mode>, riscv_sm3p0_<mode>, riscv_sm3p1_<mode>,
- riscv_sm4ed_<mode>, riscv_sm4ks_<mode>): Remove and replace with
- new insn/expansions.
- (SHA256_OP, SM3_OP, SM4_OP): New iterators.
- (sha256_op, sm3_op, sm4_op): New attributes for iteration.
- (*riscv_<sha256_op>_si): New raw instruction for RV32.
- (*riscv_<sm3_op>_si): Ditto.
- (*riscv_<sm4_op>_si): Ditto.
- (riscv_<sha256_op>_di_extended): New base instruction for RV64.
- (riscv_<sm3_op>_di_extended): Ditto.
- (riscv_<sm4_op>_di_extended): Ditto.
- (riscv_<sha256_op>_si): New common instruction expansion.
- (riscv_<sm3_op>_si): Ditto.
- (riscv_<sm4_op>_si): Ditto.
- * config/riscv/riscv-builtins.cc: Add availability "crypto_zknh",
- "crypto_zksh" and "crypto_zksed". Remove availability
- "crypto_zksh{32,64}" and "crypto_zksed{32,64}".
- * config/riscv/riscv-ftypes.def: Remove unused function type.
- * config/riscv/riscv-scalar-crypto.def: Make SHA-256, SM3 and SM4
- intrinsics to operate on uint32_t.
-
-2023-09-16 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * config/riscv/riscv-builtins.cc (RISCV_ATYPE_UQI): New for
- uint8_t. (RISCV_ATYPE_UHI): New for uint16_t.
- (RISCV_ATYPE_QI, RISCV_ATYPE_HI, RISCV_ATYPE_SI, RISCV_ATYPE_DI):
- Removed as no longer used.
- (RISCV_ATYPE_UDI): New for uint64_t.
- * config/riscv/riscv-cmo.def: Make types unsigned for not working
- "zicbop_cbo_prefetchi" and working bit manipulation clmul builtin
- argument/return types.
- * config/riscv/riscv-ftypes.def: Make bit manipulation, round
- number and shift amount types unsigned.
- * config/riscv/riscv-scalar-crypto.def: Ditto.
-
-2023-09-16 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec-vls.md (xorsign<mode>3): New pattern.
-
-2023-09-15 Fei Gao <gaofei@eswincomputing.com>
-
- * config/riscv/predicates.md: Restrict predicate
- to allow 'reg' only.
-
-2023-09-15 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (zero_one_valued_p): Match a cast from a zero_one_valued_p.
- Also match `a & zero_one_valued_p` too.
-
-2023-09-15 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111414
- * match.pd (`(1 >> X) != 0`): Check to see if
- the integer_onep was an integral type (not a vector type).
-
-2023-09-15 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-fold.cc (fold_using_range::range_of_phi): Always
- run phi analysis, and do it before loop analysis.
-
-2023-09-15 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-fold.cc (fold_using_range::range_of_phi): Fix
- indentation.
-
-2023-09-15 Qing Zhao <qing.zhao@oracle.com>
-
- PR tree-optimization/111407
- * tree-ssa-math-opts.cc (convert_mult_to_widen): Avoid the transform
- when one of the operands is subject to abnormal coalescing.
-
-2023-09-15 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum insn_flags): Change name.
- (enum insn_type): Ditto.
- * config/riscv/riscv-v.cc (get_mask_mode_from_insn_flags): Removed.
- (emit_vlmax_insn): Adjust.
- (emit_nonvlmax_insn): Adjust.
- (emit_vlmax_insn_lra): Adjust.
-
-2023-09-15 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md: Adjust.
- * config/riscv/autovec.md: Ditto.
- * config/riscv/riscv-protos.h (enum class): Delete enum reduction_type.
- (expand_reduction): Adjust expand_reduction prototype.
- * config/riscv/riscv-v.cc (need_mask_operand_p): New helper function.
- (expand_reduction): Refactor expand_reduction.
-
-2023-09-15 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/111411
- * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp): Require
- the lower memory access to a mem-pair operand.
-
-2023-09-15 Yang Yujie <yangyujie@loongson.cn>
-
- * config.gcc: Pass the default ABI via TM_MULTILIB_CONFIG.
- * config/loongarch/loongarch-driver.h: Invoke MLIB_SELF_SPECS
- before the driver canonicalization routines.
- * config/loongarch/loongarch.h: Move definitions of CC1_SPEC etc.
- to loongarch-driver.h
- * config/loongarch/t-linux: Move multilib-related definitions to
- t-multilib.
- * config/loongarch/t-multilib: New file. Inject library build
- options obtained from --with-multilib-list.
- * config/loongarch/t-loongarch: Same.
-
-2023-09-15 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/111381
- * config/riscv/autovec-opt.md (*reduc_plus_scal_<mode>):
- New combine pattern.
- (*fold_left_widen_plus_<mode>): Ditto.
- (*mask_len_fold_left_widen_plus_<mode>): Ditto.
- * config/riscv/autovec.md (reduc_plus_scal_<mode>):
- Change from define_expand to define_insn_and_split.
- (fold_left_plus_<mode>): Ditto.
- (mask_len_fold_left_plus_<mode>): Ditto.
- * config/riscv/riscv-v.cc (expand_reduction):
- Support widen reduction.
- * config/riscv/vector-iterators.md (UNSPEC_WREDUC_SUM):
- Add new iterators and attrs.
-
-2023-09-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-event-id.h (diagnostic_thread_id_t): New typedef.
- * diagnostic-format-sarif.cc (class sarif_thread_flow): New.
- (sarif_thread_flow::sarif_thread_flow): New.
- (sarif_builder::make_code_flow_object): Reimplement, creating
- per-thread threadFlow objects, populating them with the relevant
- events.
- (sarif_builder::make_thread_flow_object): Delete, moving the
- code into sarif_builder::make_code_flow_object.
- (sarif_builder::make_thread_flow_location_object): Add
- "path_event_idx" param. Use it to set "executionOrder"
- property.
- * diagnostic-path.h (diagnostic_event::get_thread_id): New
- pure-virtual vfunc.
- (class diagnostic_thread): New.
- (diagnostic_path::num_threads): New pure-virtual vfunc.
- (diagnostic_path::get_thread): New pure-virtual vfunc.
- (diagnostic_path::multithreaded_p): New decl.
- (simple_diagnostic_event::simple_diagnostic_event): Add optional
- thread_id param.
- (simple_diagnostic_event::get_thread_id): New accessor.
- (simple_diagnostic_event::m_thread_id): New.
- (class simple_diagnostic_thread): New.
- (simple_diagnostic_path::simple_diagnostic_path): Move definition
- to diagnostic.cc.
- (simple_diagnostic_path::num_threads): New.
- (simple_diagnostic_path::get_thread): New.
- (simple_diagnostic_path::add_thread): New.
- (simple_diagnostic_path::add_thread_event): New.
- (simple_diagnostic_path::m_threads): New.
- * diagnostic-show-locus.cc (layout::layout): Add pretty_printer
- param for overriding the context's printer.
- (diagnostic_show_locus): Likwise.
- * diagnostic.cc (simple_diagnostic_path::simple_diagnostic_path):
- Move here from diagnostic-path.h. Add main thread.
- (simple_diagnostic_path::num_threads): New.
- (simple_diagnostic_path::get_thread): New.
- (simple_diagnostic_path::add_thread): New.
- (simple_diagnostic_path::add_thread_event): New.
- (simple_diagnostic_event::simple_diagnostic_event): Add thread_id
- param and use it to initialize m_thread_id. Reformat.
- * diagnostic.h: Add pretty_printer param for overriding the
- context's printer.
- * tree-diagnostic-path.cc: Add #define INCLUDE_VECTOR.
- (can_consolidate_events): Compare thread ids.
- (class per_thread_summary): New.
- (event_range::event_range): Add per_thread_summary arg.
- (event_range::print): Add "pp" param and use it rather than dc's
- printer.
- (event_range::m_thread_id): New field.
- (event_range::m_per_thread_summary): New field.
- (path_summary::multithreaded_p): New.
- (path_summary::get_events_for_thread_id): New.
- (path_summary::m_per_thread_summary): New field.
- (path_summary::m_thread_id_to_events): New field.
- (path_summary::get_or_create_events_for_thread_id): New.
- (path_summary::path_summary): Create per_thread_summary instances
- as needed and associate the event_range instances with them.
- (base_indent): Move here from print_path_summary_as_text.
- (per_frame_indent): Likewise.
- (class thread_event_printer): New, adapted from parts of
- print_path_summary_as_text.
- (print_path_summary_as_text): Make static. Reimplement to
- moving most of existing code to class thread_event_printer,
- capturing state as per-thread as appropriate.
- (default_tree_diagnostic_path_printer): Add missing 'break' on
- final case.
-
-2023-09-14 David Malcolm <dmalcolm@redhat.com>
-
- * dwarf2cfi.cc (dwarf2cfi_cc_finalize): New.
- * dwarf2out.h (dwarf2cfi_cc_finalize): New decl.
- * ggc-common.cc (ggc_mark_roots): Multiply by rti->nelt when
- clearing the deletable gcc_root_tab_t.
- (ggc_common_finalize): New.
- * ggc.h (ggc_common_finalize): New decl.
- * toplev.cc (toplev::finalize): Call dwarf2cfi_cc_finalize and
- ggc_common_finalize.
-
-2023-09-14 Max Filippov <jcmvbkbc@gmail.com>
-
- * config/xtensa/predicates.md (xtensa_cstoresi_operator): Add
- unsigned comparisons.
- * config/xtensa/xtensa.cc (xtensa_expand_scc): Add code
- generation of salt/saltu instructions.
- * config/xtensa/xtensa.h (TARGET_SALT): New macro.
- * config/xtensa/xtensa.md (salt, saltu): New instruction
- patterns.
-
-2023-09-14 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * ira-costs.cc (find_costs_and_classes): Decrease memory cost
- by equiv savings.
-
-2023-09-14 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec.md: Change rtx code to unspec.
- * config/riscv/riscv-protos.h (expand_reduction): Change prototype.
- * config/riscv/riscv-v.cc (expand_reduction): Change prototype.
- * config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
- Removed.
- (class widen_freducop): Removed.
- * config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
- * config/riscv/vector.md (@pred_reduc_<reduc><mode>): Change name.
- (@pred_<reduc_op><mode>): New name.
- (@pred_widen_reduc_plus<v_su><mode>): Change name.
- (@pred_reduc_plus<order><mode>): Change name.
- (@pred_widen_reduc_plus<order><mode>): Change name.
-
-2023-09-14 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_reduction): Adjust call.
- * config/riscv/riscv-vector-builtins-bases.cc: Adjust call.
- * config/riscv/vector-iterators.md: New iterators and attrs.
- * config/riscv/vector.md (@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>):
- Removed.
- (@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>): Removed.
- (@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>): Removed.
- (@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>): Removed.
- (@pred_reduc_<reduc><mode>): Added.
- (@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): Removed.
- (@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Removed.
- (@pred_widen_reduc_plus<v_su><mode>): Added.
- (@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Removed.
- (@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>): Removed.
- (@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>): Removed.
- (@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>): Removed.
- (@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>): Removed.
- (@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>): Removed.
- (@pred_reduc_plus<order><mode>): Added.
- (@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>): Removed.
- (@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Removed.
- (@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Removed.
- (@pred_widen_reduc_plus<order><mode>): Added.
-
-2023-09-14 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_vector_costs::analyze_loop_info):
- Move WHILELO handling to...
- (aarch64_vector_costs::finish_cost): ...here. Check whether the
- vectorizer has decided to use a predicated loop.
-
-2023-09-14 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/106164
- * match.pd (`(X CMP1 CST1) AND/IOR (X CMP2 CST2)`):
- Expand to support constants that are off by one.
-
-2023-09-14 Andrew Pinski <apinski@marvell.com>
-
- * genmatch.cc (parser::parse_result): For an else clause
- of an if statement inside a switch, error out explictly.
-
-2023-09-14 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md: Add VLS mask modes.
- * config/riscv/autovec.md (@vcond_mask_<mode><vm>): Remove @.
- (vcond_mask_<mode><vm>): Add VLS mask modes.
- * config/riscv/vector.md: Ditto.
-
-2023-09-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111294
- * tree-ssa-forwprop.cc (pass_forwprop::execute): Track
- operands that eventually become dead and use simple_dce_from_worklist
- to remove their definitions if they did so.
-
-2023-09-14 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve.md (@aarch64_vec_duplicate_vq<mode>_le):
- Accept all nonimmediate_operands, but keep the existing constraints.
- If the instruction is split before RA, load invalid addresses into
- a temporary register.
- * config/aarch64/predicates.md (aarch64_sve_dup_ld1rq_operand): Delete.
-
-2023-09-14 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111395
- * config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE.
- (vector_insn_info::global_merge): Ditto.
- (vector_insn_info::get_avl_or_vl_reg): Ditto.
-
-2023-09-14 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Format it.
-
-2023-09-14 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch-def.c: Modify the default value of
- branch_cost.
-
-2023-09-14 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.cc (xtensa_expand_scc):
- Revert the changes from the last patch, as the work in the RTL
- expansion pass is too far to determine the physical registers.
- * config/xtensa/xtensa.md (*eqne_INT_MIN): Ditto.
- (eq_zero_NSA, eqne_zero, *eqne_zero_masked_bits): New patterns.
-
-2023-09-14 Lulu Cheng <chenglulu@loongson.cn>
-
- PR target/111334
- * config/loongarch/loongarch.md: Fix bug of '<optab>di3_fake'.
-
-2023-09-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (vec_extract<mode><vel>): Add VLS modes.
- (@vec_extract<mode><vel>): Ditto.
- * config/riscv/vector.md: Ditto
-
-2023-09-13 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`X <= MAX(X, Y)`):
- Move before `MIN (X, C1) < C2` pattern.
-
-2023-09-13 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111364
- * match.pd (`MIN (X, Y) == X`): Extend
- to min/lt, min/ge, max/gt, max/le.
-
-2023-09-13 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111345
- * match.pd (`Y > (X % Y)`): Merge
- into ...
- (`(X % Y) < Y`): Pattern by adding `:c`
- on the comparison.
-
-2023-09-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111387
- * tree-vect-slp.cc (vect_get_and_check_slp_defs): Check
- EDGE_DFS_BACK when doing BB vectorization.
- (vect_slp_function): Use rev_post_order_and_mark_dfs_back_seme
- to compute RPO and mark backedges.
-
-2023-09-13 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_<mulh_table><mode>3_highpart):
- New combine pattern.
- * config/riscv/autovec.md (smul<mode>3_highpart): Mrege smul and umul.
- (<mulh_table><mode>3_highpart): Merged pattern.
- (umul<mode>3_highpart): Mrege smul and umul.
- * config/riscv/vector-iterators.md (umul): New iterators.
- (UNSPEC_VMULHU): New iterators.
-
-2023-09-13 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_v<any_shiftrt:optab><any_extend:optab>trunc<mode>):
- New combine pattern.
- (*cond_<any_shiftrt:optab>trunc<mode>): Ditto.
-
-2023-09-13 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*copysign<mode>_neg): Move.
- (*cond_copysign<mode>): New combine pattern.
- * config/riscv/riscv-v.cc (needs_fp_rounding): Extend.
-
-2023-09-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111397
- * tree-ssa-propagate.cc (may_propagate_copy): Change optional
- argument to specify whether the PHI destination doesn't flow in
- from an abnormal PHI.
- (propagate_value): Adjust.
- * tree-ssa-forwprop.cc (pass_forwprop::execute): Indicate abnormal
- PHI dest.
- * tree-ssa-sccvn.cc (eliminate_dom_walker::before_dom_children):
- Likewise.
- (process_bb): Likewise.
-
-2023-09-13 Pan Li <pan2.li@intel.com>
-
- PR target/111362
- * config/riscv/riscv.cc (riscv_emit_frm_mode_set): Bugfix.
-
-2023-09-13 Jiufu Guo <guojiufu@linux.ibm.com>
-
- PR tree-optimization/111303
- * match.pd ((X - N * M) / N): Add undefined_p checking.
- ((X + N * M) / N): Likewise.
- ((X + C) div_rshift N): Likewise.
-
-2023-09-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111337
- * config/riscv/autovec.md (vcond_mask_<mode><mode>): New pattern.
-
-2023-09-12 Martin Jambor <mjambor@suse.cz>
-
- * dbgcnt.def (form_fma): New.
- * tree-ssa-math-opts.cc: Include dbgcnt.h.
- (convert_mult_to_fma): Bail out if the debug counter say so.
-
-2023-09-12 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/autovec-opt.md: Update type
- * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_save_regs_above_locals_p):
- New function.
- (aarch64_layout_frame): Use it to decide whether locals should
- go above or below the saved registers.
- (aarch64_expand_prologue): Update stack layout comment.
- Emit a stack tie after the final adjustment.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame::saved_regs_size)
- (aarch64_frame::below_hard_fp_saved_regs_size): Delete.
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Update accordingly.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame::sve_save_and_probe)
- (aarch64_frame::hard_fp_save_and_probe): New fields.
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Initialize them.
- Rather than asserting that a leaf function saves LR, instead assert
- that a leaf function saves something.
- (aarch64_get_separate_components): Prevent the chosen probe
- registers from being individually shrink-wrapped.
- (aarch64_allocate_and_probe_stack_space): Remove workaround for
- probe registers that aren't at the bottom of the previous allocation.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_allocate_and_probe_stack_space):
- Always probe the residual allocation at offset 1024, asserting
- that that is in range.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Ensure that
- the LR save slot is in the first 16 bytes of the register save area.
- Only form STP/LDP push/pop candidates if both registers are valid.
- (aarch64_allocate_and_probe_stack_space): Remove workaround for
- when LR was not in the first 16 bytes.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_allocate_and_probe_stack_space):
- Don't probe final allocations that are exactly 1KiB in size (after
- unprobed space above the final allocation has been deducted).
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Tweak
- calculation of initial_adjust for frames in which all saves
- are SVE saves.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Simplify
- the allocation of the top of the frame.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame): Add comment above
- reg_offset.
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Walk offsets
- from the bottom of the frame, rather than the bottom of the saved
- register area. Measure reg_offset from the bottom of the frame
- rather than the bottom of the saved register area.
- (aarch64_save_callee_saves): Update accordingly.
- (aarch64_restore_callee_saves): Likewise.
- (aarch64_get_separate_components): Likewise.
- (aarch64_process_components): Likewise.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame::frame_size): Tweak comment.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame::hard_fp_offset): Rename
- to...
- (aarch64_frame::bytes_above_hard_fp): ...this.
- * config/aarch64/aarch64.cc (aarch64_layout_frame)
- (aarch64_expand_prologue): Update accordingly.
- (aarch64_initial_elimination_offset): Likewise.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame::locals_offset): Rename to...
- (aarch64_frame::bytes_above_locals): ...this.
- * config/aarch64/aarch64.cc (aarch64_layout_frame)
- (aarch64_initial_elimination_offset): Update accordingly.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_expand_prologue): Move the
- calculation of chain_offset into the emit_frame_chain block.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame::callee_offset): Delete.
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Remove
- callee_offset handling.
- (aarch64_save_callee_saves): Replace the start_offset parameter
- with a bytes_below_sp parameter.
- (aarch64_restore_callee_saves): Likewise.
- (aarch64_expand_prologue): Update accordingly.
- (aarch64_expand_epilogue): Likewise.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame::bytes_below_hard_fp): New
- field.
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Initialize it.
- (aarch64_expand_epilogue): Use it instead of
- below_hard_fp_saved_regs_size.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (aarch64_frame::bytes_below_saved_regs): New
- field.
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Initialize it,
- and use it instead of crtl->outgoing_args_size.
- (aarch64_get_separate_components): Use bytes_below_saved_regs instead
- of outgoing_args_size.
- (aarch64_process_components): Likewise.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_layout_frame): Explicitly
- allocate the frame in one go if there are no saved registers.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_expand_prologue): Use
- chain_offset rather than callee_offset.
-
-2023-09-12 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
- a local shorthand for cfun->machine->frame.
- (aarch64_restore_callee_saves, aarch64_get_separate_components):
- (aarch64_process_components): Likewise.
- (aarch64_allocate_and_probe_stack_space): Likewise.
- (aarch64_expand_prologue, aarch64_expand_epilogue): Likewise.
- (aarch64_layout_frame): Use existing shorthand for one more case.
-
-2023-09-12 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/107881
- * match.pd (`(a CMP1 b) ^ (a CMP2 b)`): New pattern.
- (`(a CMP1 b) == (a CMP2 b)`): New pattern.
-
-2023-09-12 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-costs.h (struct range): Removed.
-
-2023-09-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (get_last_live_range): New function.
- (compute_nregs_for_mode): Ditto.
- (live_range_conflict_p): Ditto.
- (max_number_of_live_regs): Ditto.
- (compute_lmul): Ditto.
- (costs::prefer_new_lmul_p): Ditto.
- (costs::better_main_loop_than_p): Ditto.
- * config/riscv/riscv-vector-costs.h (struct stmt_point): New struct.
- (struct var_live_range): Ditto.
- (struct autovec_info): Ditto.
- * config/riscv/t-riscv: Update makefile for COST model.
-
-2023-09-12 Jakub Jelinek <jakub@redhat.com>
-
- * fold-const.cc (range_check_type): Handle BITINT_TYPE like
- OFFSET_TYPE.
-
-2023-09-12 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/111338
- * tree-ssa-sccvn.cc (struct vn_walk_cb_data): Add bufsize non-static
- data member.
- (vn_walk_cb_data::push_partial_def): Remove bufsize variable.
- (visit_nary_op): Avoid the BIT_AND_EXPR with constant rhs2
- optimization if type's precision is too large for
- vn_walk_cb_data::bufsize.
-
-2023-09-12 Gaius Mulley <gaiusmod2@gmail.com>
-
- * doc/gm2.texi (Compiler options): Document new option
- -Wcase-enum.
-
-2023-09-12 Thomas Schwinge <thomas@codesourcery.com>
-
- * doc/sourcebuild.texi (stack_size): Update.
-
-2023-09-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/bitmanip.md (*<optab>_not<mode>): Export INSN name.
- (<optab>_not<mode>3): Likewise.
- * config/riscv/riscv-protos.h (riscv_expand_strcmp): New
- prototype.
- * config/riscv/riscv-string.cc (GEN_EMIT_HELPER3): New helper
- macros.
- (GEN_EMIT_HELPER2): Likewise.
- (emit_strcmp_scalar_compare_byte): New function.
- (emit_strcmp_scalar_compare_subword): Likewise.
- (emit_strcmp_scalar_compare_word): Likewise.
- (emit_strcmp_scalar_load_and_compare): Likewise.
- (emit_strcmp_scalar_call_to_libc): Likewise.
- (emit_strcmp_scalar_result_calculation_nonul): Likewise.
- (emit_strcmp_scalar_result_calculation): Likewise.
- (riscv_expand_strcmp_scalar): Likewise.
- (riscv_expand_strcmp): Likewise.
- * config/riscv/riscv.md (*slt<u>_<X:mode><GPR:mode>): Export
- INSN name.
- (@slt<u>_<X:mode><GPR:mode>3): Likewise.
- (cmpstrnsi): Invoke expansion function for str(n)cmp.
- (cmpstrsi): Likewise.
- * config/riscv/riscv.opt: Add new parameter
- '-mstring-compare-inline-limit'.
- * doc/invoke.texi: Document new parameter
- '-mstring-compare-inline-limit'.
-
-2023-09-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config.gcc: Add new object riscv-string.o.
- riscv-string.cc.
- * config/riscv/riscv-protos.h (riscv_expand_strlen):
- New function.
- * config/riscv/riscv.md (strlen<mode>): New expand INSN.
- * config/riscv/riscv.opt: New flag 'minline-strlen'.
- * config/riscv/t-riscv: Add new object riscv-string.o.
- * config/riscv/thead.md (th_rev<mode>2): Export INSN name.
- (th_rev<mode>2): Likewise.
- (th_tstnbz<mode>2): New INSN.
- * doc/invoke.texi: Document '-minline-strlen'.
- * emit-rtl.cc (emit_likely_jump_insn): New helper function.
- (emit_unlikely_jump_insn): Likewise.
- * rtl.h (emit_likely_jump_insn): New prototype.
- (emit_unlikely_jump_insn): Likewise.
- * config/riscv/riscv-string.cc: New file.
-
-2023-09-12 Thomas Schwinge <thomas@codesourcery.com>
-
- * config/nvptx/nvptx.h (TARGET_USE_LOCAL_THUNK_ALIAS_P)
- (TARGET_SUPPORTS_ALIASES): Define.
-
-2023-09-12 Thomas Schwinge <thomas@codesourcery.com>
-
- * doc/sourcebuild.texi (check-function-bodies): Update.
-
-2023-09-12 Tobias Burnus <tobias@codesourcery.com>
-
- * gimplify.cc (gimplify_bind_expr): Check for
- insertion after variable cleanup. Convert 'omp allocate'
- var-decl attribute to GOMP_alloc/GOMP_free calls.
-
-2023-09-12 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: remove unused
- parameter e and replace NULL_RTX with gcc_unreachable.
-
-2023-09-12 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc (class vcreate): New class.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vcreate): Add vcreate support.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc: Add args type.
-
-2023-09-12 Fei Gao <gaofei@eswincomputing.com>
-
- * config/riscv/riscv.cc
- (riscv_avoid_shrink_wrapping_separate): wrap the condition check in
- riscv_avoid_shrink_wrapping_separate.
- (riscv_avoid_multi_push):avoid multi push if shrink_wrapping_separate
- is active.
- (riscv_get_separate_components):call riscv_avoid_shrink_wrapping_separate
-
-2023-09-12 Fei Gao <gaofei@eswincomputing.com>
-
- * shrink-wrap.cc (try_shrink_wrapping_separate):call
- use_shrink_wrapping_separate.
- (use_shrink_wrapping_separate): wrap the condition
- check in use_shrink_wrapping_separate.
- * shrink-wrap.h (use_shrink_wrapping_separate): add to extern
-
-2023-09-11 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111348
- * match.pd (`(a CMP b) ? minmax<a, c> : minmax<b, c>`): Add :c on
- the cmp part of the pattern.
-
-2023-09-11 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/111340
- * config/i386/i386.cc (output_pic_addr_const): Handle CONST_WIDE_INT.
- Call output_addr_const for CASE_CONST_SCALAR_INT.
-
-2023-09-11 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/thead.md: Update types
-
-2023-09-11 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/riscv.md: Update types
-
-2023-09-11 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/riscv.md: Add "zicond" type
- * config/riscv/zicond.md: Update types
-
-2023-09-11 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/riscv.md: Add "pushpop" and "mvpair" types
- * config/riscv/zc.md: Update types
-
-2023-09-11 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/autovec-opt.md: Update types
- * config/riscv/autovec.md: likewise
-
-2023-09-11 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtins.def (s390_vec_signed_flt): Fix
- builtin flag.
- (s390_vec_unsigned_flt): Ditto.
- (s390_vec_revb_flt): Ditto.
- (s390_vec_reve_flt): Ditto.
- (s390_vclfnhs): Fix operand flags.
- (s390_vclfnls): Ditto.
- (s390_vcrnfs): Ditto.
- (s390_vcfn): Ditto.
- (s390_vcnf): Ditto.
-
-2023-09-11 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtins.def (O_U64): New.
- (O1_U64): Ditto.
- (O2_U64): Ditto.
- (O3_U64): Ditto.
- (O4_U64): Ditto.
- (O_M12): Change bit position.
- (O_S2): Ditto.
- (O_S3): Ditto.
- (O_S4): Ditto.
- (O_S5): Ditto.
- (O_S8): Ditto.
- (O_S12): Ditto.
- (O_S16): Ditto.
- (O_S32): Ditto.
- (O_ELEM): Ditto.
- (O_LIT): Ditto.
- (OB_DEF_VAR): Add operand constraints.
- (B_DEF): Ditto.
- * config/s390/s390.cc (s390_const_operand_ok): Honour 64 bit
- operands.
-
-2023-09-11 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111349
- * match.pd (`(a CMP CST1) ? max<a,CST2> : a`): Add :c on
- the cmp part of the pattern.
-
-2023-09-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111311
- * config/riscv/riscv.opt: Set default as scalable vectorization.
-
-2023-09-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (get_all_predecessors): Remove.
- (get_all_successors): Ditto.
- * config/riscv/riscv-v.cc (get_all_predecessors): Ditto.
- (get_all_successors): Ditto.
-
-2023-09-11 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/111329
- * pretty-print.h (pp_wide_int): Rewrite from macro into inline
- function. For printing values which don't fit into digit_buffer
- use out-of-line function.
- * wide-int-print.h (pp_wide_int_large): Declare.
- * wide-int-print.cc: Include pretty-print.h.
- (pp_wide_int_large): Define.
-
-2023-09-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn):
- Use dominance analysis.
- (pass_vsetvl::init): Ditto.
- (pass_vsetvl::done): Ditto.
-
-2023-09-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111311
- * config/riscv/autovec.md: Add VLS modes.
- * config/riscv/riscv-protos.h (cmp_lmul_le_one): New function.
- (cmp_lmul_gt_one): Ditto.
- * config/riscv/riscv-v.cc (cmp_lmul_le_one): Ditto.
- (cmp_lmul_gt_one): Ditto.
- * config/riscv/riscv.cc (riscv_print_operand): Add VLS modes.
- (riscv_vectorize_vec_perm_const): Ditto.
- * config/riscv/vector-iterators.md: Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-09-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-vls.md (*mov<mode>_vls): New pattern.
- * config/riscv/vector-iterators.md: New iterator
-
-2023-09-11 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111346
- * match.pd (`X CMP MINMAX`): Add `:c` on the cmp part
- of the pattern
-
-2023-09-11 liuhongt <hongtao.liu@intel.com>
-
- PR target/111306
- PR target/111335
- * config/i386/sse.md (int_comm): New int_attr.
- (fma_<complexopname>_<mode><sdc_maskz_name><round_name>):
- Remove % for Complex conjugate operations since they're not
- commutative.
- (fma_<complexpairopname>_<mode>_pair): Ditto.
- (<avx512>_<complexopname>_<mode>_mask<round_name>): Ditto.
- (cmul<conj_op><mode>3): Ditto.
-
-2023-09-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (shuffle_generic_patterns): Expand
- fixed-vlmax/vls vector permutation.
-
-2023-09-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid unnecessary slideup.
-
-2023-09-10 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111331
- * match.pd (`(a CMP CST1) ? max<a,CST2> : a`):
- Fix the LE/GE comparison to the correct value.
- * tree-ssa-phiopt.cc (minmax_replacement):
- Fix the LE/GE comparison for the
- `(a CMP CST1) ? max<a,CST2> : a` optimization.
-
-2023-09-10 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.cc (darwin_function_section): Place unlikely
- executed global init code into the standard cold section.
-
-2023-09-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111311
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::vsetvl_fusion): Add TDF_DETAILS.
- (pass_vsetvl::pre_vsetvl): Ditto.
- (pass_vsetvl::init): Ditto.
- (pass_vsetvl::lazy_vsetvl): Ditto.
-
-2023-09-09 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch.md (mulsidi3_64bit):
- Field unsigned extension support.
- (<u>muldi3_highpart): Modify template name.
- (<u>mulsi3_highpart): Likewise.
- (<u>mulsidi3_64bit): Field unsigned extension support.
- (<su>muldi3_highpart): Modify muldi3_highpart to
- smuldi3_highpart.
- (<su>mulsi3_highpart): Modify mulsi3_highpart to
- smulsi3_highpart.
-
-2023-09-09 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc (loongarch_block_move_straight):
- Check precondition (delta must be a power of 2) and use
- popcount_hwi instead of a homebrew loop.
-
-2023-09-09 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.h (LARCH_MAX_MOVE_PER_INSN):
- Define to the maximum amount of bytes able to be loaded or
- stored with one machine instruction.
- * config/loongarch/loongarch.cc (loongarch_mode_for_move_size):
- New static function.
- (loongarch_block_move_straight): Call
- loongarch_mode_for_move_size for machine_mode to be moved.
- (loongarch_expand_block_move): Use LARCH_MAX_MOVE_PER_INSN
- instead of UNITS_PER_WORD.
-
-2023-09-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Fix floating-point operations predicate.
-
-2023-09-09 Lehua Ding <lehua.ding@rivai.ai>
-
- * fold-const.cc (can_min_p): New function.
- (poly_int_binop): Try fold MIN_EXPR.
-
-2023-09-08 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (foperator_ltgt::fold_range): Do not special
- case VREL_EQ nor call frelop_early_resolve.
-
-2023-09-08 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/thead.md (*extend<SHORT:mode><SUPERQI:mode>2_th_ext):
- Remove broken INSN.
- (*extendhi<SUPERQI:mode>2_th_ext): New INSN.
- (*extendqi<SUPERQI:mode>2_th_ext): New INSN.
-
-2023-09-08 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/thead.md: Use more appropriate mode attributes
- for extensions.
-
-2023-09-08 Guo Jie <guojie@loongson.cn>
-
- * common/config/loongarch/loongarch-common.cc:
- (default_options loongarch_option_optimization_table):
- Default to -fsched-pressure.
-
-2023-09-08 Yang Yujie <yangyujie@loongson.cn>
-
- * config.gcc: remove non-POSIX syntax "<<<".
-
-2023-09-08 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/bitmanip.md (*extend<SHORT:mode><SUPERQI:mode>2_zbb):
- Rename postfix to _bitmanip.
- (*extend<SHORT:mode><SUPERQI:mode>2_bitmanip): Renamed pattern.
- (*zero_extendhi<GPR:mode>2_zbb): Remove duplicated pattern.
-
-2023-09-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_pass_in_vector_p): Only allow RVV type.
-
-2023-09-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_hard_regno_nregs): Fix bug.
-
-2023-09-07 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md
- (<avx512>_vpermt2var<mode>3<sd_maskz_name>): New define_insn.
- (VHFBF_AVX512VL): New mode iterator.
- (VI2HFBF_AVX512VL): New mode iterator.
-
-2023-09-07 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (contains_zero_p): Return false for undefined ranges.
- * range-op-float.cc (operator_gt::op1_op2_relation): Adjust for
- contains_zero_p change above.
- (operator_ge::op1_op2_relation): Same.
- (operator_equal::op1_op2_relation): Same.
- (operator_not_equal::op1_op2_relation): Same.
- (operator_lt::op1_op2_relation): Same.
- (operator_le::op1_op2_relation): Same.
- (operator_ge::op1_op2_relation): Same.
- * range-op.cc (operator_equal::op1_op2_relation): Same.
- (operator_not_equal::op1_op2_relation): Same.
- (operator_lt::op1_op2_relation): Same.
- (operator_le::op1_op2_relation): Same.
- (operator_cast::op1_range): Same.
- (set_nonzero_range_from_mask): Same.
- (operator_bitwise_xor::op1_range): Same.
- (operator_addr_expr::fold_range): Same.
- (operator_addr_expr::op1_range): Same.
-
-2023-09-07 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/110875
- * gimple-range.cc (gimple_ranger::prefill_name): Only invoke
- cache-prefilling routine when the ssa-name has no global value.
-
-2023-09-07 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR target/111225
- * lra-constraints.cc (goal_reuse_alt_p): New global flag.
- (process_alt_operands): Set up the flag. Clear flag for chosen
- alternative with special memory constraints.
- (process_alt_operands): Set up used insn alternative depending on the flag.
-
-2023-09-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-vls.md: Add VLS mask modes mov patterns.
- * config/riscv/riscv.md: Ditto.
- * config/riscv/vector-iterators.md: Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-09-07 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-core.h (error_meta): New decl.
- * diagnostic.cc (error_meta): New.
-
-2023-09-07 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * expr.cc (expand_expr_real_1): Don't call targetm.c.bitint_type_info
- inside gcc_assert, as later code relies on it filling info variable.
- * gimple-fold.cc (clear_padding_bitint_needs_padding_p,
- clear_padding_type): Likewise.
- * varasm.cc (output_constant): Likewise.
- * fold-const.cc (native_encode_int, native_interpret_int): Likewise.
- * stor-layout.cc (finish_bitfield_representative, layout_type):
- Likewise.
- * gimple-lower-bitint.cc (bitint_precision_kind): Likewise.
-
-2023-09-07 Xi Ruoyao <xry111@xry111.site>
-
- PR target/111252
- * config/loongarch/loongarch-protos.h
- (loongarch_pre_reload_split): Declare new function.
- (loongarch_use_bstrins_for_ior_with_mask): Likewise.
- * config/loongarch/loongarch.cc
- (loongarch_pre_reload_split): Implement.
- (loongarch_use_bstrins_for_ior_with_mask): Likewise.
- * config/loongarch/predicates.md (ins_zero_bitmask_operand):
- New predicate.
- * config/loongarch/loongarch.md (bstrins_<mode>_for_mask):
- New define_insn_and_split.
- (bstrins_<mode>_for_ior_mask): Likewise.
- (define_peephole2): Further optimize code sequence produced by
- bstrins_<mode>_for_ior_mask if possible.
-
-2023-09-07 Richard Sandiford <richard.sandiford@arm.com>
-
- * lra-eliminations.cc (lra_eliminate_regs_1): Use simplify_gen_binary
- rather than gen_rtx_PLUS.
-
-2023-09-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111313
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_earliest_vsetvls): Remove.
- (pass_vsetvl::df_post_optimization): Remove incorrect function.
-
-2023-09-07 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
- Parse 'XVentanaCondOps' extension.
- * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
- (TARGET_XVENTANACONDOPS): Ditto.
- (TARGET_ZICOND_LIKE): New to represent targets with conditional
- moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
- * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
- with TARGET_ZICOND_LIKE.
- (riscv_expand_conditional_move): Ditto.
- * config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
- TARGET_ZICOND_LIKE.
- * config/riscv/riscv.opt: Add new riscv_xventana_subext.
- * config/riscv/zicond.md: Modify description.
- (eqz_ventana): New to match corresponding czero instructions.
- (nez_ventana): Ditto.
- (*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
- 'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
- (*czero.<eqz>.<GPR><X>): Ditto.
- (*czero.eqz.<GPR><X>.opt1): Ditto.
- (*czero.nez.<GPR><X>.opt2): Ditto.
-
-2023-09-06 Ian Lance Taylor <iant@golang.org>
-
- PR go/111310
- * godump.cc (go_format_type): Handle BITINT_TYPE.
-
-2023-09-06 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * tree.cc (build_one_cst, build_minus_one_cst): Handle BITINT_TYPE
- like INTEGER_TYPE.
-
-2023-09-06 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * gimple-lower-bitint.cc (bitint_large_huge::if_then_else,
- bitint_large_huge::if_then_if_then_else): Use make_single_succ_edge
- rather than make_edge, initialize bb->count.
-
-2023-09-06 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * doc/libgcc.texi (Bit-precise integer arithmetic functions):
- Document general rules for _BitInt support library functions
- and document __mulbitint3 and __divmodbitint4.
- (Conversion functions): Document __fix{s,d,x,t}fbitint,
- __floatbitint{s,d,x,t,h,b}f, __bid_fix{s,d,t}dbitint and
- __bid_floatbitint{s,d,t}d.
-
-2023-09-06 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * glimits.h (BITINT_MAXWIDTH): Define if __BITINT_MAXWIDTH__ is
- predefined.
-
-2023-09-06 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * internal-fn.cc (expand_ubsan_result_store): Add LHS, MODE and
- DO_ERROR arguments. For non-mode precision BITINT_TYPE results
- check if all padding bits up to mode precision are zeros or sign
- bit copies and if not, jump to DO_ERROR.
- (expand_addsub_overflow, expand_neg_overflow, expand_mul_overflow):
- Adjust expand_ubsan_result_store callers.
- * ubsan.cc: Include target.h and langhooks.h.
- (ubsan_encode_value): Pass BITINT_TYPE values which fit into pointer
- size converted to pointer sized integer, pass BITINT_TYPE values
- which fit into TImode (if supported) or DImode as those integer types
- or otherwise for now punt (pass 0).
- (ubsan_type_descriptor): Handle BITINT_TYPE. For pstyle of
- UBSAN_PRINT_FORCE_INT use TK_Integer (0x0000) mode with a
- TImode/DImode precision rather than TK_Unknown used otherwise for
- large/huge BITINT_TYPEs.
- (instrument_si_overflow): Instrument BITINT_TYPE operations even when
- they don't have mode precision.
- * ubsan.h (enum ubsan_print_style): New enumerator.
-
-2023-09-06 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * config/i386/i386.cc (classify_argument): Handle BITINT_TYPE.
- (ix86_bitint_type_info): New function.
- (TARGET_C_BITINT_TYPE_INFO): Redefine.
-
-2023-09-06 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * Makefile.in (OBJS): Add gimple-lower-bitint.o.
- * passes.def: Add pass_lower_bitint after pass_lower_complex and
- pass_lower_bitint_O0 after pass_lower_complex_O0.
- * tree-pass.h (PROP_gimple_lbitint): Define.
- (make_pass_lower_bitint_O0, make_pass_lower_bitint): Declare.
- * gimple-lower-bitint.h: New file.
- * tree-ssa-live.h (struct _var_map): Add bitint member.
- (init_var_map): Adjust declaration.
- (region_contains_p): Handle map->bitint like map->outofssa_p.
- * tree-ssa-live.cc (init_var_map): Add BITINT argument, initialize
- map->bitint and set map->outofssa_p to false if it is non-NULL.
- * tree-ssa-coalesce.cc: Include gimple-lower-bitint.h.
- (build_ssa_conflict_graph): Call build_bitint_stmt_ssa_conflicts if
- map->bitint.
- (create_coalesce_list_for_region): For map->bitint ignore SSA_NAMEs
- not in that bitmap, and allow res without default def.
- (compute_optimized_partition_bases): In map->bitint mode try hard to
- coalesce any SSA_NAMEs with the same size.
- (coalesce_bitint): New function.
- (coalesce_ssa_name): In map->bitint mode, or map->bitmap into
- used_in_copies and call coalesce_bitint.
- * gimple-lower-bitint.cc: New file.
-
-2023-09-06 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * tree.def (BITINT_TYPE): New type.
- * tree.h (TREE_CHECK6, TREE_NOT_CHECK6): Define.
- (NUMERICAL_TYPE_CHECK, INTEGRAL_TYPE_P): Include
- BITINT_TYPE.
- (BITINT_TYPE_P): Define.
- (CONSTRUCTOR_BITFIELD_P): Return true even for BLKmode bit-fields if
- they have BITINT_TYPE type.
- (tree_check6, tree_not_check6): New inline functions.
- (any_integral_type_check): Include BITINT_TYPE.
- (build_bitint_type): Declare.
- * tree.cc (tree_code_size, wide_int_to_tree_1, cache_integer_cst,
- build_zero_cst, type_hash_canon_hash, type_cache_hasher::equal,
- type_hash_canon): Handle BITINT_TYPE.
- (bitint_type_cache): New variable.
- (build_bitint_type): New function.
- (signed_or_unsigned_type_for, verify_type_variant, verify_type):
- Handle BITINT_TYPE.
- (tree_cc_finalize): Free bitint_type_cache.
- * builtins.cc (type_to_class): Handle BITINT_TYPE.
- (fold_builtin_unordered_cmp): Handle BITINT_TYPE like INTEGER_TYPE.
- * cfgexpand.cc (expand_debug_expr): Punt on BLKmode BITINT_TYPE
- INTEGER_CSTs.
- * convert.cc (convert_to_pointer_1, convert_to_real_1,
- convert_to_complex_1): Handle BITINT_TYPE like INTEGER_TYPE.
- (convert_to_integer_1): Likewise. For BITINT_TYPE don't check
- GET_MODE_PRECISION (TYPE_MODE (type)).
- * doc/generic.texi (BITINT_TYPE): Document.
- * doc/tm.texi.in (TARGET_C_BITINT_TYPE_INFO): New.
- * doc/tm.texi: Regenerated.
- * dwarf2out.cc (base_type_die, is_base_type, modified_type_die,
- gen_type_die_with_usage): Handle BITINT_TYPE.
- (rtl_for_decl_init): Punt on BLKmode BITINT_TYPE INTEGER_CSTs or
- handle those which fit into shwi.
- * expr.cc (expand_expr_real_1): Define EXTEND_BITINT macro, reduce
- to bitfield precision reads from BITINT_TYPE vars, parameters or
- memory locations. Expand large/huge BITINT_TYPE INTEGER_CSTs into
- memory.
- * fold-const.cc (fold_convert_loc, make_range_step): Handle
- BITINT_TYPE.
- (extract_muldiv_1): For BITINT_TYPE use TYPE_PRECISION rather than
- GET_MODE_SIZE (SCALAR_INT_TYPE_MODE).
- (native_encode_int, native_interpret_int, native_interpret_expr):
- Handle BITINT_TYPE.
- * gimple-expr.cc (useless_type_conversion_p): Make BITINT_TYPE
- to some other integral type or vice versa conversions non-useless.
- * gimple-fold.cc (gimple_fold_builtin_memset): Punt for BITINT_TYPE.
- (clear_padding_unit): Mention in comment that _BitInt types don't need
- to fit either.
- (clear_padding_bitint_needs_padding_p): New function.
- (clear_padding_type_may_have_padding_p): Handle BITINT_TYPE.
- (clear_padding_type): Likewise.
- * internal-fn.cc (expand_mul_overflow): For unsigned non-mode
- precision operands force pos_neg? to 1.
- (expand_MULBITINT, expand_DIVMODBITINT, expand_FLOATTOBITINT,
- expand_BITINTTOFLOAT): New functions.
- * internal-fn.def (MULBITINT, DIVMODBITINT, FLOATTOBITINT,
- BITINTTOFLOAT): New internal functions.
- * internal-fn.h (expand_MULBITINT, expand_DIVMODBITINT,
- expand_FLOATTOBITINT, expand_BITINTTOFLOAT): Declare.
- * match.pd (non-equality compare simplifications from fold_binary):
- Punt if TYPE_MODE (arg1_type) is BLKmode.
- * pretty-print.h (pp_wide_int): Handle printing of large precision
- wide_ints which would buffer overflow digit_buffer.
- * stor-layout.cc (finish_bitfield_representative): For bit-fields
- with BITINT_TYPE, prefer representatives with precisions in
- multiple of limb precision.
- (layout_type): Handle BITINT_TYPE. Handle COMPLEX_TYPE with BLKmode
- element type and assert it is BITINT_TYPE.
- * target.def (bitint_type_info): New C target hook.
- * target.h (struct bitint_info): New type.
- * targhooks.cc (default_bitint_type_info): New function.
- * targhooks.h (default_bitint_type_info): Declare.
- * tree-pretty-print.cc (dump_generic_node): Handle BITINT_TYPE.
- Handle printing large wide_ints which would buffer overflow
- digit_buffer.
- * tree-ssa-sccvn.cc: Include target.h.
- (eliminate_dom_walker::eliminate_stmt): Punt for large/huge
- BITINT_TYPE.
- * tree-switch-conversion.cc (jump_table_cluster::emit): For more than
- 64-bit BITINT_TYPE subtract low bound from expression and cast to
- 64-bit integer type both the controlling expression and case labels.
- * typeclass.h (enum type_class): Add bitint_type_class enumerator.
- * varasm.cc (output_constant): Handle BITINT_TYPE INTEGER_CSTs.
- * vr-values.cc (check_for_binary_op_overflow): Use widest2_int rather
- than widest_int.
- (simplify_using_ranges::simplify_internal_call_using_ranges): Use
- unsigned_type_for rather than build_nonstandard_integer_type.
-
-2023-09-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111296
- * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix incorrect mode
- tieable for RVV modes.
-
-2023-09-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111295
- * config/riscv/riscv-vsetvl.cc (insert_vsetvl): Bug fix.
-
-2023-09-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-switch.def (VLS_ENTRY): Remove TARGET_64BIT
-
-2023-09-06 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.cc (xtensa_expand_scc):
- Add code for particular constants (only 0 and INT_MIN for now)
- for EQ/NE boolean evaluation in SImode.
- * config/xtensa/xtensa.md (*eqne_INT_MIN): Remove because its
- implementation has been integrated into the above.
-
-2023-09-06 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/111232
- * config/riscv/autovec-opt.md (@pred_single_widen_mul<any_extend:su><mode>):
- Delete.
- (*pred_widen_mulsu<mode>): Delete.
- (*pred_single_widen_mul<mode>): Delete.
- (*dual_widen_<any_widen_binop:optab><any_extend:su><mode>):
- Add new combine patterns.
- (*single_widen_sub<any_extend:su><mode>): Ditto.
- (*single_widen_add<any_extend:su><mode>): Ditto.
- (*single_widen_mult<any_extend:su><mode>): Ditto.
- (*dual_widen_mulsu<mode>): Ditto.
- (*dual_widen_mulus<mode>): Ditto.
- (*dual_widen_<optab><mode>): Ditto.
- (*single_widen_add<mode>): Ditto.
- (*single_widen_sub<mode>): Ditto.
- (*single_widen_mult<mode>): Ditto.
- * config/riscv/autovec.md (<optab><mode>3):
- Change define_expand to define_insn_and_split.
- (<optab><mode>2): Ditto.
- (abs<mode>2): Ditto.
- (smul<mode>3_highpart): Ditto.
- (umul<mode>3_highpart): Ditto.
-
-2023-09-06 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-protos.h (riscv_declare_function_name): Add protos.
- (riscv_asm_output_alias): Ditto.
- (riscv_asm_output_external): Ditto.
- * config/riscv/riscv.cc (riscv_asm_output_variant_cc):
- Output .variant_cc directive for vector function.
- (riscv_declare_function_name): Ditto.
- (riscv_asm_output_alias): Ditto.
- (riscv_asm_output_external): Ditto.
- * config/riscv/riscv.h (ASM_DECLARE_FUNCTION_NAME):
- Implement ASM_DECLARE_FUNCTION_NAME.
- (ASM_OUTPUT_DEF_FROM_DECLS): Implement ASM_OUTPUT_DEF_FROM_DECLS.
- (ASM_OUTPUT_EXTERNAL): Implement ASM_OUTPUT_EXTERNAL.
-
-2023-09-06 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-sr.cc (riscv_remove_unneeded_save_restore_calls): Pass riscv_cc.
- * config/riscv/riscv.cc (struct riscv_frame_info): Add new fileds.
- (riscv_frame_info::reset): Reset new fileds.
- (riscv_call_tls_get_addr): Pass riscv_cc.
- (riscv_function_arg): Return riscv_cc for call patterm.
- (get_riscv_cc): New function return riscv_cc from rtl call_insn.
- (riscv_insn_callee_abi): Implement TARGET_INSN_CALLEE_ABI.
- (riscv_save_reg_p): Add vector callee-saved check.
- (riscv_stack_align): Add vector save area comment.
- (riscv_compute_frame_info): Ditto.
- (riscv_restore_reg): Update for type change.
- (riscv_for_each_saved_v_reg): New function save vector registers.
- (riscv_first_stack_step): Handle funciton with vector callee-saved registers.
- (riscv_expand_prologue): Ditto.
- (riscv_expand_epilogue): Ditto.
- (riscv_output_mi_thunk): Pass riscv_cc.
- (TARGET_INSN_CALLEE_ABI): Implement TARGET_INSN_CALLEE_ABI.
- * config/riscv/riscv.h (get_riscv_cc): Export get_riscv_cc function.
- * config/riscv/riscv.md: Add CALLEE_CC operand for call pattern.
-
-2023-09-06 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-protos.h (builtin_type_p): New function for checking vector type.
- * config/riscv/riscv-vector-builtins.cc (builtin_type_p): Ditto.
- * config/riscv/riscv.cc (struct riscv_arg_info): New fields.
- (riscv_init_cumulative_args): Setup variant_cc field.
- (riscv_vector_type_p): New function for checking vector type.
- (riscv_hard_regno_nregs): Hoist declare.
- (riscv_get_vector_arg): Subroutine of riscv_get_arg_info.
- (riscv_get_arg_info): Support vector cc.
- (riscv_function_arg_advance): Update cum.
- (riscv_pass_by_reference): Handle vector args.
- (riscv_v_abi): New function return vector abi.
- (riscv_return_value_is_vector_type_p): New function for check vector arguments.
- (riscv_arguments_is_vector_type_p): New function for check vector returns.
- (riscv_fntype_abi): Implement TARGET_FNTYPE_ABI.
- (TARGET_FNTYPE_ABI): Implement TARGET_FNTYPE_ABI.
- * config/riscv/riscv.h (GCC_RISCV_H): Define macros for vector abi.
- (MAX_ARGS_IN_VECTOR_REGISTERS): Ditto.
- (MAX_ARGS_IN_MASK_REGISTERS): Ditto.
- (V_ARG_FIRST): Ditto.
- (V_ARG_LAST): Ditto.
- (enum riscv_cc): Define all RISCV_CC variants.
- * config/riscv/riscv.opt: Add --param=riscv-vector-abi.
-
-2023-09-06 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_<optab><mode>):
- Add sqrt + vcond_mask combine pattern.
- * config/riscv/autovec.md (<optab><mode>2):
- Change define_expand to define_insn_and_split.
-
-2023-09-06 Jason Merrill <jason@redhat.com>
-
- * common.opt: Update -fabi-version=19.
-
-2023-09-06 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * config/riscv/zicond.md: Add closing parent to a comment.
-
-2023-09-06 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Force
- large constant cons/alt into a register.
-
-2023-09-05 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.cc (riscv_build_integer_1): Don't
- require one zero bit in the upper 32 bits for LI+RORI synthesis.
-
-2023-09-05 Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/bitmanip.md (bswapsi2): Expose for TARGET_64BIT.
-
-2023-09-05 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/98710
- * match.pd (`(x | c) & ~(y | c)`, `(x & c) | ~(y & c)`): New pattern.
- (`x & ~(y | x)`, `x | ~(y & x)`): New patterns.
-
-2023-09-05 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/103536
- * match.pd (`(x | y) & (x & z)`,
- `(x & y) | (x | z)`): New patterns.
-
-2023-09-05 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/107137
- * match.pd (`(nop_convert)-(convert)a`): New pattern.
-
-2023-09-05 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/96694
- * match.pd (`~MAX(~X, Y)`, `~MIN(~X, Y)`): New patterns.
-
-2023-09-05 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/105832
- * match.pd (`(1 >> X) != 0`): New pattern
-
-2023-09-05 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/riscv.md: Update/Add types
-
-2023-09-05 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/pic.md: Update types
-
-2023-09-05 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.cc (riscv_build_integer_1): Enable constant
- synthesis with rotate-right for XTheadBb.
-
-2023-09-05 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/zicond.md: Fix op2 pattern.
-
-2023-09-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64.h (AARCH64_ISA_RCPC): Remove dup.
-
-2023-09-05 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-opts.h (HAVE_AS_EXPLICIT_RELOCS):
- Define to 0 if not defined yet.
-
-2023-09-05 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/linux.h (TARGET_ASM_FILE_END): Move ...
- * config/riscv/riscv.cc (TARGET_ASM_FILE_END): to here.
-
-2023-09-05 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec-vls.md (copysign<mode>3): New pattern.
- * config/riscv/vector.md: Extend iterator for VLS.
-
-2023-09-05 Lulu Cheng <chenglulu@loongson.cn>
-
- * config.gcc: Export the header file lasxintrin.h.
- * config/loongarch/loongarch-builtins.cc (enum loongarch_builtin_type):
- Add Loongson ASX builtin functions support.
- (AVAIL_ALL): Ditto.
- (LASX_BUILTIN): Ditto.
- (LASX_NO_TARGET_BUILTIN): Ditto.
- (LASX_BUILTIN_TEST_BRANCH): Ditto.
- (CODE_FOR_lasx_xvsadd_b): Ditto.
- (CODE_FOR_lasx_xvsadd_h): Ditto.
- (CODE_FOR_lasx_xvsadd_w): Ditto.
- (CODE_FOR_lasx_xvsadd_d): Ditto.
- (CODE_FOR_lasx_xvsadd_bu): Ditto.
- (CODE_FOR_lasx_xvsadd_hu): Ditto.
- (CODE_FOR_lasx_xvsadd_wu): Ditto.
- (CODE_FOR_lasx_xvsadd_du): Ditto.
- (CODE_FOR_lasx_xvadd_b): Ditto.
- (CODE_FOR_lasx_xvadd_h): Ditto.
- (CODE_FOR_lasx_xvadd_w): Ditto.
- (CODE_FOR_lasx_xvadd_d): Ditto.
- (CODE_FOR_lasx_xvaddi_bu): Ditto.
- (CODE_FOR_lasx_xvaddi_hu): Ditto.
- (CODE_FOR_lasx_xvaddi_wu): Ditto.
- (CODE_FOR_lasx_xvaddi_du): Ditto.
- (CODE_FOR_lasx_xvand_v): Ditto.
- (CODE_FOR_lasx_xvandi_b): Ditto.
- (CODE_FOR_lasx_xvbitsel_v): Ditto.
- (CODE_FOR_lasx_xvseqi_b): Ditto.
- (CODE_FOR_lasx_xvseqi_h): Ditto.
- (CODE_FOR_lasx_xvseqi_w): Ditto.
- (CODE_FOR_lasx_xvseqi_d): Ditto.
- (CODE_FOR_lasx_xvslti_b): Ditto.
- (CODE_FOR_lasx_xvslti_h): Ditto.
- (CODE_FOR_lasx_xvslti_w): Ditto.
- (CODE_FOR_lasx_xvslti_d): Ditto.
- (CODE_FOR_lasx_xvslti_bu): Ditto.
- (CODE_FOR_lasx_xvslti_hu): Ditto.
- (CODE_FOR_lasx_xvslti_wu): Ditto.
- (CODE_FOR_lasx_xvslti_du): Ditto.
- (CODE_FOR_lasx_xvslei_b): Ditto.
- (CODE_FOR_lasx_xvslei_h): Ditto.
- (CODE_FOR_lasx_xvslei_w): Ditto.
- (CODE_FOR_lasx_xvslei_d): Ditto.
- (CODE_FOR_lasx_xvslei_bu): Ditto.
- (CODE_FOR_lasx_xvslei_hu): Ditto.
- (CODE_FOR_lasx_xvslei_wu): Ditto.
- (CODE_FOR_lasx_xvslei_du): Ditto.
- (CODE_FOR_lasx_xvdiv_b): Ditto.
- (CODE_FOR_lasx_xvdiv_h): Ditto.
- (CODE_FOR_lasx_xvdiv_w): Ditto.
- (CODE_FOR_lasx_xvdiv_d): Ditto.
- (CODE_FOR_lasx_xvdiv_bu): Ditto.
- (CODE_FOR_lasx_xvdiv_hu): Ditto.
- (CODE_FOR_lasx_xvdiv_wu): Ditto.
- (CODE_FOR_lasx_xvdiv_du): Ditto.
- (CODE_FOR_lasx_xvfadd_s): Ditto.
- (CODE_FOR_lasx_xvfadd_d): Ditto.
- (CODE_FOR_lasx_xvftintrz_w_s): Ditto.
- (CODE_FOR_lasx_xvftintrz_l_d): Ditto.
- (CODE_FOR_lasx_xvftintrz_wu_s): Ditto.
- (CODE_FOR_lasx_xvftintrz_lu_d): Ditto.
- (CODE_FOR_lasx_xvffint_s_w): Ditto.
- (CODE_FOR_lasx_xvffint_d_l): Ditto.
- (CODE_FOR_lasx_xvffint_s_wu): Ditto.
- (CODE_FOR_lasx_xvffint_d_lu): Ditto.
- (CODE_FOR_lasx_xvfsub_s): Ditto.
- (CODE_FOR_lasx_xvfsub_d): Ditto.
- (CODE_FOR_lasx_xvfmul_s): Ditto.
- (CODE_FOR_lasx_xvfmul_d): Ditto.
- (CODE_FOR_lasx_xvfdiv_s): Ditto.
- (CODE_FOR_lasx_xvfdiv_d): Ditto.
- (CODE_FOR_lasx_xvfmax_s): Ditto.
- (CODE_FOR_lasx_xvfmax_d): Ditto.
- (CODE_FOR_lasx_xvfmin_s): Ditto.
- (CODE_FOR_lasx_xvfmin_d): Ditto.
- (CODE_FOR_lasx_xvfsqrt_s): Ditto.
- (CODE_FOR_lasx_xvfsqrt_d): Ditto.
- (CODE_FOR_lasx_xvflogb_s): Ditto.
- (CODE_FOR_lasx_xvflogb_d): Ditto.
- (CODE_FOR_lasx_xvmax_b): Ditto.
- (CODE_FOR_lasx_xvmax_h): Ditto.
- (CODE_FOR_lasx_xvmax_w): Ditto.
- (CODE_FOR_lasx_xvmax_d): Ditto.
- (CODE_FOR_lasx_xvmaxi_b): Ditto.
- (CODE_FOR_lasx_xvmaxi_h): Ditto.
- (CODE_FOR_lasx_xvmaxi_w): Ditto.
- (CODE_FOR_lasx_xvmaxi_d): Ditto.
- (CODE_FOR_lasx_xvmax_bu): Ditto.
- (CODE_FOR_lasx_xvmax_hu): Ditto.
- (CODE_FOR_lasx_xvmax_wu): Ditto.
- (CODE_FOR_lasx_xvmax_du): Ditto.
- (CODE_FOR_lasx_xvmaxi_bu): Ditto.
- (CODE_FOR_lasx_xvmaxi_hu): Ditto.
- (CODE_FOR_lasx_xvmaxi_wu): Ditto.
- (CODE_FOR_lasx_xvmaxi_du): Ditto.
- (CODE_FOR_lasx_xvmin_b): Ditto.
- (CODE_FOR_lasx_xvmin_h): Ditto.
- (CODE_FOR_lasx_xvmin_w): Ditto.
- (CODE_FOR_lasx_xvmin_d): Ditto.
- (CODE_FOR_lasx_xvmini_b): Ditto.
- (CODE_FOR_lasx_xvmini_h): Ditto.
- (CODE_FOR_lasx_xvmini_w): Ditto.
- (CODE_FOR_lasx_xvmini_d): Ditto.
- (CODE_FOR_lasx_xvmin_bu): Ditto.
- (CODE_FOR_lasx_xvmin_hu): Ditto.
- (CODE_FOR_lasx_xvmin_wu): Ditto.
- (CODE_FOR_lasx_xvmin_du): Ditto.
- (CODE_FOR_lasx_xvmini_bu): Ditto.
- (CODE_FOR_lasx_xvmini_hu): Ditto.
- (CODE_FOR_lasx_xvmini_wu): Ditto.
- (CODE_FOR_lasx_xvmini_du): Ditto.
- (CODE_FOR_lasx_xvmod_b): Ditto.
- (CODE_FOR_lasx_xvmod_h): Ditto.
- (CODE_FOR_lasx_xvmod_w): Ditto.
- (CODE_FOR_lasx_xvmod_d): Ditto.
- (CODE_FOR_lasx_xvmod_bu): Ditto.
- (CODE_FOR_lasx_xvmod_hu): Ditto.
- (CODE_FOR_lasx_xvmod_wu): Ditto.
- (CODE_FOR_lasx_xvmod_du): Ditto.
- (CODE_FOR_lasx_xvmul_b): Ditto.
- (CODE_FOR_lasx_xvmul_h): Ditto.
- (CODE_FOR_lasx_xvmul_w): Ditto.
- (CODE_FOR_lasx_xvmul_d): Ditto.
- (CODE_FOR_lasx_xvclz_b): Ditto.
- (CODE_FOR_lasx_xvclz_h): Ditto.
- (CODE_FOR_lasx_xvclz_w): Ditto.
- (CODE_FOR_lasx_xvclz_d): Ditto.
- (CODE_FOR_lasx_xvnor_v): Ditto.
- (CODE_FOR_lasx_xvor_v): Ditto.
- (CODE_FOR_lasx_xvori_b): Ditto.
- (CODE_FOR_lasx_xvnori_b): Ditto.
- (CODE_FOR_lasx_xvpcnt_b): Ditto.
- (CODE_FOR_lasx_xvpcnt_h): Ditto.
- (CODE_FOR_lasx_xvpcnt_w): Ditto.
- (CODE_FOR_lasx_xvpcnt_d): Ditto.
- (CODE_FOR_lasx_xvxor_v): Ditto.
- (CODE_FOR_lasx_xvxori_b): Ditto.
- (CODE_FOR_lasx_xvsll_b): Ditto.
- (CODE_FOR_lasx_xvsll_h): Ditto.
- (CODE_FOR_lasx_xvsll_w): Ditto.
- (CODE_FOR_lasx_xvsll_d): Ditto.
- (CODE_FOR_lasx_xvslli_b): Ditto.
- (CODE_FOR_lasx_xvslli_h): Ditto.
- (CODE_FOR_lasx_xvslli_w): Ditto.
- (CODE_FOR_lasx_xvslli_d): Ditto.
- (CODE_FOR_lasx_xvsra_b): Ditto.
- (CODE_FOR_lasx_xvsra_h): Ditto.
- (CODE_FOR_lasx_xvsra_w): Ditto.
- (CODE_FOR_lasx_xvsra_d): Ditto.
- (CODE_FOR_lasx_xvsrai_b): Ditto.
- (CODE_FOR_lasx_xvsrai_h): Ditto.
- (CODE_FOR_lasx_xvsrai_w): Ditto.
- (CODE_FOR_lasx_xvsrai_d): Ditto.
- (CODE_FOR_lasx_xvsrl_b): Ditto.
- (CODE_FOR_lasx_xvsrl_h): Ditto.
- (CODE_FOR_lasx_xvsrl_w): Ditto.
- (CODE_FOR_lasx_xvsrl_d): Ditto.
- (CODE_FOR_lasx_xvsrli_b): Ditto.
- (CODE_FOR_lasx_xvsrli_h): Ditto.
- (CODE_FOR_lasx_xvsrli_w): Ditto.
- (CODE_FOR_lasx_xvsrli_d): Ditto.
- (CODE_FOR_lasx_xvsub_b): Ditto.
- (CODE_FOR_lasx_xvsub_h): Ditto.
- (CODE_FOR_lasx_xvsub_w): Ditto.
- (CODE_FOR_lasx_xvsub_d): Ditto.
- (CODE_FOR_lasx_xvsubi_bu): Ditto.
- (CODE_FOR_lasx_xvsubi_hu): Ditto.
- (CODE_FOR_lasx_xvsubi_wu): Ditto.
- (CODE_FOR_lasx_xvsubi_du): Ditto.
- (CODE_FOR_lasx_xvpackod_d): Ditto.
- (CODE_FOR_lasx_xvpackev_d): Ditto.
- (CODE_FOR_lasx_xvpickod_d): Ditto.
- (CODE_FOR_lasx_xvpickev_d): Ditto.
- (CODE_FOR_lasx_xvrepli_b): Ditto.
- (CODE_FOR_lasx_xvrepli_h): Ditto.
- (CODE_FOR_lasx_xvrepli_w): Ditto.
- (CODE_FOR_lasx_xvrepli_d): Ditto.
- (CODE_FOR_lasx_xvandn_v): Ditto.
- (CODE_FOR_lasx_xvorn_v): Ditto.
- (CODE_FOR_lasx_xvneg_b): Ditto.
- (CODE_FOR_lasx_xvneg_h): Ditto.
- (CODE_FOR_lasx_xvneg_w): Ditto.
- (CODE_FOR_lasx_xvneg_d): Ditto.
- (CODE_FOR_lasx_xvbsrl_v): Ditto.
- (CODE_FOR_lasx_xvbsll_v): Ditto.
- (CODE_FOR_lasx_xvfmadd_s): Ditto.
- (CODE_FOR_lasx_xvfmadd_d): Ditto.
- (CODE_FOR_lasx_xvfmsub_s): Ditto.
- (CODE_FOR_lasx_xvfmsub_d): Ditto.
- (CODE_FOR_lasx_xvfnmadd_s): Ditto.
- (CODE_FOR_lasx_xvfnmadd_d): Ditto.
- (CODE_FOR_lasx_xvfnmsub_s): Ditto.
- (CODE_FOR_lasx_xvfnmsub_d): Ditto.
- (CODE_FOR_lasx_xvpermi_q): Ditto.
- (CODE_FOR_lasx_xvpermi_d): Ditto.
- (CODE_FOR_lasx_xbnz_v): Ditto.
- (CODE_FOR_lasx_xbz_v): Ditto.
- (CODE_FOR_lasx_xvssub_b): Ditto.
- (CODE_FOR_lasx_xvssub_h): Ditto.
- (CODE_FOR_lasx_xvssub_w): Ditto.
- (CODE_FOR_lasx_xvssub_d): Ditto.
- (CODE_FOR_lasx_xvssub_bu): Ditto.
- (CODE_FOR_lasx_xvssub_hu): Ditto.
- (CODE_FOR_lasx_xvssub_wu): Ditto.
- (CODE_FOR_lasx_xvssub_du): Ditto.
- (CODE_FOR_lasx_xvabsd_b): Ditto.
- (CODE_FOR_lasx_xvabsd_h): Ditto.
- (CODE_FOR_lasx_xvabsd_w): Ditto.
- (CODE_FOR_lasx_xvabsd_d): Ditto.
- (CODE_FOR_lasx_xvabsd_bu): Ditto.
- (CODE_FOR_lasx_xvabsd_hu): Ditto.
- (CODE_FOR_lasx_xvabsd_wu): Ditto.
- (CODE_FOR_lasx_xvabsd_du): Ditto.
- (CODE_FOR_lasx_xvavg_b): Ditto.
- (CODE_FOR_lasx_xvavg_h): Ditto.
- (CODE_FOR_lasx_xvavg_w): Ditto.
- (CODE_FOR_lasx_xvavg_d): Ditto.
- (CODE_FOR_lasx_xvavg_bu): Ditto.
- (CODE_FOR_lasx_xvavg_hu): Ditto.
- (CODE_FOR_lasx_xvavg_wu): Ditto.
- (CODE_FOR_lasx_xvavg_du): Ditto.
- (CODE_FOR_lasx_xvavgr_b): Ditto.
- (CODE_FOR_lasx_xvavgr_h): Ditto.
- (CODE_FOR_lasx_xvavgr_w): Ditto.
- (CODE_FOR_lasx_xvavgr_d): Ditto.
- (CODE_FOR_lasx_xvavgr_bu): Ditto.
- (CODE_FOR_lasx_xvavgr_hu): Ditto.
- (CODE_FOR_lasx_xvavgr_wu): Ditto.
- (CODE_FOR_lasx_xvavgr_du): Ditto.
- (CODE_FOR_lasx_xvmuh_b): Ditto.
- (CODE_FOR_lasx_xvmuh_h): Ditto.
- (CODE_FOR_lasx_xvmuh_w): Ditto.
- (CODE_FOR_lasx_xvmuh_d): Ditto.
- (CODE_FOR_lasx_xvmuh_bu): Ditto.
- (CODE_FOR_lasx_xvmuh_hu): Ditto.
- (CODE_FOR_lasx_xvmuh_wu): Ditto.
- (CODE_FOR_lasx_xvmuh_du): Ditto.
- (CODE_FOR_lasx_xvssran_b_h): Ditto.
- (CODE_FOR_lasx_xvssran_h_w): Ditto.
- (CODE_FOR_lasx_xvssran_w_d): Ditto.
- (CODE_FOR_lasx_xvssran_bu_h): Ditto.
- (CODE_FOR_lasx_xvssran_hu_w): Ditto.
- (CODE_FOR_lasx_xvssran_wu_d): Ditto.
- (CODE_FOR_lasx_xvssrarn_b_h): Ditto.
- (CODE_FOR_lasx_xvssrarn_h_w): Ditto.
- (CODE_FOR_lasx_xvssrarn_w_d): Ditto.
- (CODE_FOR_lasx_xvssrarn_bu_h): Ditto.
- (CODE_FOR_lasx_xvssrarn_hu_w): Ditto.
- (CODE_FOR_lasx_xvssrarn_wu_d): Ditto.
- (CODE_FOR_lasx_xvssrln_bu_h): Ditto.
- (CODE_FOR_lasx_xvssrln_hu_w): Ditto.
- (CODE_FOR_lasx_xvssrln_wu_d): Ditto.
- (CODE_FOR_lasx_xvssrlrn_bu_h): Ditto.
- (CODE_FOR_lasx_xvssrlrn_hu_w): Ditto.
- (CODE_FOR_lasx_xvssrlrn_wu_d): Ditto.
- (CODE_FOR_lasx_xvftint_w_s): Ditto.
- (CODE_FOR_lasx_xvftint_l_d): Ditto.
- (CODE_FOR_lasx_xvftint_wu_s): Ditto.
- (CODE_FOR_lasx_xvftint_lu_d): Ditto.
- (CODE_FOR_lasx_xvsllwil_h_b): Ditto.
- (CODE_FOR_lasx_xvsllwil_w_h): Ditto.
- (CODE_FOR_lasx_xvsllwil_d_w): Ditto.
- (CODE_FOR_lasx_xvsllwil_hu_bu): Ditto.
- (CODE_FOR_lasx_xvsllwil_wu_hu): Ditto.
- (CODE_FOR_lasx_xvsllwil_du_wu): Ditto.
- (CODE_FOR_lasx_xvsat_b): Ditto.
- (CODE_FOR_lasx_xvsat_h): Ditto.
- (CODE_FOR_lasx_xvsat_w): Ditto.
- (CODE_FOR_lasx_xvsat_d): Ditto.
- (CODE_FOR_lasx_xvsat_bu): Ditto.
- (CODE_FOR_lasx_xvsat_hu): Ditto.
- (CODE_FOR_lasx_xvsat_wu): Ditto.
- (CODE_FOR_lasx_xvsat_du): Ditto.
- (loongarch_builtin_vectorized_function): Ditto.
- (loongarch_expand_builtin_insn): Ditto.
- (loongarch_expand_builtin): Ditto.
- * config/loongarch/loongarch-ftypes.def (1): Ditto.
- (2): Ditto.
- (3): Ditto.
- (4): Ditto.
- * config/loongarch/lasxintrin.h: New file.
-
-2023-09-05 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch-modes.def
- (VECTOR_MODES): Add Loongson ASX instruction support.
- * config/loongarch/loongarch-protos.h (loongarch_split_256bit_move): Ditto.
- (loongarch_split_256bit_move_p): Ditto.
- (loongarch_expand_vector_group_init): Ditto.
- (loongarch_expand_vec_perm_1): Ditto.
- * config/loongarch/loongarch.cc (loongarch_symbol_insns): Ditto.
- (loongarch_valid_offset_p): Ditto.
- (loongarch_address_insns): Ditto.
- (loongarch_const_insns): Ditto.
- (loongarch_legitimize_move): Ditto.
- (loongarch_builtin_vectorization_cost): Ditto.
- (loongarch_split_move_p): Ditto.
- (loongarch_split_move): Ditto.
- (loongarch_output_move_index_float): Ditto.
- (loongarch_split_256bit_move_p): Ditto.
- (loongarch_split_256bit_move): Ditto.
- (loongarch_output_move): Ditto.
- (loongarch_print_operand_reloc): Ditto.
- (loongarch_print_operand): Ditto.
- (loongarch_hard_regno_mode_ok_uncached): Ditto.
- (loongarch_hard_regno_nregs): Ditto.
- (loongarch_class_max_nregs): Ditto.
- (loongarch_can_change_mode_class): Ditto.
- (loongarch_mode_ok_for_mov_fmt_p): Ditto.
- (loongarch_vector_mode_supported_p): Ditto.
- (loongarch_preferred_simd_mode): Ditto.
- (loongarch_autovectorize_vector_modes): Ditto.
- (loongarch_lsx_output_division): Ditto.
- (loongarch_expand_lsx_shuffle): Ditto.
- (loongarch_expand_vec_perm): Ditto.
- (loongarch_expand_vec_perm_interleave): Ditto.
- (loongarch_try_expand_lsx_vshuf_const): Ditto.
- (loongarch_expand_vec_perm_even_odd_1): Ditto.
- (loongarch_expand_vec_perm_even_odd): Ditto.
- (loongarch_expand_vec_perm_1): Ditto.
- (loongarch_expand_vec_perm_const_2): Ditto.
- (loongarch_is_quad_duplicate): Ditto.
- (loongarch_is_double_duplicate): Ditto.
- (loongarch_is_odd_extraction): Ditto.
- (loongarch_is_even_extraction): Ditto.
- (loongarch_is_extraction_permutation): Ditto.
- (loongarch_is_center_extraction): Ditto.
- (loongarch_is_reversing_permutation): Ditto.
- (loongarch_is_di_misalign_extract): Ditto.
- (loongarch_is_si_misalign_extract): Ditto.
- (loongarch_is_lasx_lowpart_interleave): Ditto.
- (loongarch_is_lasx_lowpart_interleave_2): Ditto.
- (COMPARE_SELECTOR): Ditto.
- (loongarch_is_lasx_lowpart_extract): Ditto.
- (loongarch_is_lasx_highpart_interleave): Ditto.
- (loongarch_is_lasx_highpart_interleave_2): Ditto.
- (loongarch_is_elem_duplicate): Ditto.
- (loongarch_is_op_reverse_perm): Ditto.
- (loongarch_is_single_op_perm): Ditto.
- (loongarch_is_divisible_perm): Ditto.
- (loongarch_is_triple_stride_extract): Ditto.
- (loongarch_vectorize_vec_perm_const): Ditto.
- (loongarch_cpu_sched_reassociation_width): Ditto.
- (loongarch_expand_vector_extract): Ditto.
- (emit_reduc_half): Ditto.
- (loongarch_expand_vec_unpack): Ditto.
- (loongarch_expand_vector_group_init): Ditto.
- (loongarch_expand_vector_init): Ditto.
- (loongarch_expand_lsx_cmp): Ditto.
- (loongarch_builtin_support_vector_misalignment): Ditto.
- * config/loongarch/loongarch.h (UNITS_PER_LASX_REG): Ditto.
- (BITS_PER_LASX_REG): Ditto.
- (STRUCTURE_SIZE_BOUNDARY): Ditto.
- (LASX_REG_FIRST): Ditto.
- (LASX_REG_LAST): Ditto.
- (LASX_REG_NUM): Ditto.
- (LASX_REG_P): Ditto.
- (LASX_REG_RTX_P): Ditto.
- (LASX_SUPPORTED_MODE_P): Ditto.
- * config/loongarch/loongarch.md: Ditto.
- * config/loongarch/lasx.md: New file.
-
-2023-09-05 Lulu Cheng <chenglulu@loongson.cn>
-
- * config.gcc: Export the header file lsxintrin.h.
- * config/loongarch/loongarch-builtins.cc (LARCH_FTYPE_NAME4): Add builtin function support.
- (enum loongarch_builtin_type): Ditto.
- (AVAIL_ALL): Ditto.
- (LARCH_BUILTIN): Ditto.
- (LSX_BUILTIN): Ditto.
- (LSX_BUILTIN_TEST_BRANCH): Ditto.
- (LSX_NO_TARGET_BUILTIN): Ditto.
- (CODE_FOR_lsx_vsadd_b): Ditto.
- (CODE_FOR_lsx_vsadd_h): Ditto.
- (CODE_FOR_lsx_vsadd_w): Ditto.
- (CODE_FOR_lsx_vsadd_d): Ditto.
- (CODE_FOR_lsx_vsadd_bu): Ditto.
- (CODE_FOR_lsx_vsadd_hu): Ditto.
- (CODE_FOR_lsx_vsadd_wu): Ditto.
- (CODE_FOR_lsx_vsadd_du): Ditto.
- (CODE_FOR_lsx_vadd_b): Ditto.
- (CODE_FOR_lsx_vadd_h): Ditto.
- (CODE_FOR_lsx_vadd_w): Ditto.
- (CODE_FOR_lsx_vadd_d): Ditto.
- (CODE_FOR_lsx_vaddi_bu): Ditto.
- (CODE_FOR_lsx_vaddi_hu): Ditto.
- (CODE_FOR_lsx_vaddi_wu): Ditto.
- (CODE_FOR_lsx_vaddi_du): Ditto.
- (CODE_FOR_lsx_vand_v): Ditto.
- (CODE_FOR_lsx_vandi_b): Ditto.
- (CODE_FOR_lsx_bnz_v): Ditto.
- (CODE_FOR_lsx_bz_v): Ditto.
- (CODE_FOR_lsx_vbitsel_v): Ditto.
- (CODE_FOR_lsx_vseqi_b): Ditto.
- (CODE_FOR_lsx_vseqi_h): Ditto.
- (CODE_FOR_lsx_vseqi_w): Ditto.
- (CODE_FOR_lsx_vseqi_d): Ditto.
- (CODE_FOR_lsx_vslti_b): Ditto.
- (CODE_FOR_lsx_vslti_h): Ditto.
- (CODE_FOR_lsx_vslti_w): Ditto.
- (CODE_FOR_lsx_vslti_d): Ditto.
- (CODE_FOR_lsx_vslti_bu): Ditto.
- (CODE_FOR_lsx_vslti_hu): Ditto.
- (CODE_FOR_lsx_vslti_wu): Ditto.
- (CODE_FOR_lsx_vslti_du): Ditto.
- (CODE_FOR_lsx_vslei_b): Ditto.
- (CODE_FOR_lsx_vslei_h): Ditto.
- (CODE_FOR_lsx_vslei_w): Ditto.
- (CODE_FOR_lsx_vslei_d): Ditto.
- (CODE_FOR_lsx_vslei_bu): Ditto.
- (CODE_FOR_lsx_vslei_hu): Ditto.
- (CODE_FOR_lsx_vslei_wu): Ditto.
- (CODE_FOR_lsx_vslei_du): Ditto.
- (CODE_FOR_lsx_vdiv_b): Ditto.
- (CODE_FOR_lsx_vdiv_h): Ditto.
- (CODE_FOR_lsx_vdiv_w): Ditto.
- (CODE_FOR_lsx_vdiv_d): Ditto.
- (CODE_FOR_lsx_vdiv_bu): Ditto.
- (CODE_FOR_lsx_vdiv_hu): Ditto.
- (CODE_FOR_lsx_vdiv_wu): Ditto.
- (CODE_FOR_lsx_vdiv_du): Ditto.
- (CODE_FOR_lsx_vfadd_s): Ditto.
- (CODE_FOR_lsx_vfadd_d): Ditto.
- (CODE_FOR_lsx_vftintrz_w_s): Ditto.
- (CODE_FOR_lsx_vftintrz_l_d): Ditto.
- (CODE_FOR_lsx_vftintrz_wu_s): Ditto.
- (CODE_FOR_lsx_vftintrz_lu_d): Ditto.
- (CODE_FOR_lsx_vffint_s_w): Ditto.
- (CODE_FOR_lsx_vffint_d_l): Ditto.
- (CODE_FOR_lsx_vffint_s_wu): Ditto.
- (CODE_FOR_lsx_vffint_d_lu): Ditto.
- (CODE_FOR_lsx_vfsub_s): Ditto.
- (CODE_FOR_lsx_vfsub_d): Ditto.
- (CODE_FOR_lsx_vfmul_s): Ditto.
- (CODE_FOR_lsx_vfmul_d): Ditto.
- (CODE_FOR_lsx_vfdiv_s): Ditto.
- (CODE_FOR_lsx_vfdiv_d): Ditto.
- (CODE_FOR_lsx_vfmax_s): Ditto.
- (CODE_FOR_lsx_vfmax_d): Ditto.
- (CODE_FOR_lsx_vfmin_s): Ditto.
- (CODE_FOR_lsx_vfmin_d): Ditto.
- (CODE_FOR_lsx_vfsqrt_s): Ditto.
- (CODE_FOR_lsx_vfsqrt_d): Ditto.
- (CODE_FOR_lsx_vflogb_s): Ditto.
- (CODE_FOR_lsx_vflogb_d): Ditto.
- (CODE_FOR_lsx_vmax_b): Ditto.
- (CODE_FOR_lsx_vmax_h): Ditto.
- (CODE_FOR_lsx_vmax_w): Ditto.
- (CODE_FOR_lsx_vmax_d): Ditto.
- (CODE_FOR_lsx_vmaxi_b): Ditto.
- (CODE_FOR_lsx_vmaxi_h): Ditto.
- (CODE_FOR_lsx_vmaxi_w): Ditto.
- (CODE_FOR_lsx_vmaxi_d): Ditto.
- (CODE_FOR_lsx_vmax_bu): Ditto.
- (CODE_FOR_lsx_vmax_hu): Ditto.
- (CODE_FOR_lsx_vmax_wu): Ditto.
- (CODE_FOR_lsx_vmax_du): Ditto.
- (CODE_FOR_lsx_vmaxi_bu): Ditto.
- (CODE_FOR_lsx_vmaxi_hu): Ditto.
- (CODE_FOR_lsx_vmaxi_wu): Ditto.
- (CODE_FOR_lsx_vmaxi_du): Ditto.
- (CODE_FOR_lsx_vmin_b): Ditto.
- (CODE_FOR_lsx_vmin_h): Ditto.
- (CODE_FOR_lsx_vmin_w): Ditto.
- (CODE_FOR_lsx_vmin_d): Ditto.
- (CODE_FOR_lsx_vmini_b): Ditto.
- (CODE_FOR_lsx_vmini_h): Ditto.
- (CODE_FOR_lsx_vmini_w): Ditto.
- (CODE_FOR_lsx_vmini_d): Ditto.
- (CODE_FOR_lsx_vmin_bu): Ditto.
- (CODE_FOR_lsx_vmin_hu): Ditto.
- (CODE_FOR_lsx_vmin_wu): Ditto.
- (CODE_FOR_lsx_vmin_du): Ditto.
- (CODE_FOR_lsx_vmini_bu): Ditto.
- (CODE_FOR_lsx_vmini_hu): Ditto.
- (CODE_FOR_lsx_vmini_wu): Ditto.
- (CODE_FOR_lsx_vmini_du): Ditto.
- (CODE_FOR_lsx_vmod_b): Ditto.
- (CODE_FOR_lsx_vmod_h): Ditto.
- (CODE_FOR_lsx_vmod_w): Ditto.
- (CODE_FOR_lsx_vmod_d): Ditto.
- (CODE_FOR_lsx_vmod_bu): Ditto.
- (CODE_FOR_lsx_vmod_hu): Ditto.
- (CODE_FOR_lsx_vmod_wu): Ditto.
- (CODE_FOR_lsx_vmod_du): Ditto.
- (CODE_FOR_lsx_vmul_b): Ditto.
- (CODE_FOR_lsx_vmul_h): Ditto.
- (CODE_FOR_lsx_vmul_w): Ditto.
- (CODE_FOR_lsx_vmul_d): Ditto.
- (CODE_FOR_lsx_vclz_b): Ditto.
- (CODE_FOR_lsx_vclz_h): Ditto.
- (CODE_FOR_lsx_vclz_w): Ditto.
- (CODE_FOR_lsx_vclz_d): Ditto.
- (CODE_FOR_lsx_vnor_v): Ditto.
- (CODE_FOR_lsx_vor_v): Ditto.
- (CODE_FOR_lsx_vori_b): Ditto.
- (CODE_FOR_lsx_vnori_b): Ditto.
- (CODE_FOR_lsx_vpcnt_b): Ditto.
- (CODE_FOR_lsx_vpcnt_h): Ditto.
- (CODE_FOR_lsx_vpcnt_w): Ditto.
- (CODE_FOR_lsx_vpcnt_d): Ditto.
- (CODE_FOR_lsx_vxor_v): Ditto.
- (CODE_FOR_lsx_vxori_b): Ditto.
- (CODE_FOR_lsx_vsll_b): Ditto.
- (CODE_FOR_lsx_vsll_h): Ditto.
- (CODE_FOR_lsx_vsll_w): Ditto.
- (CODE_FOR_lsx_vsll_d): Ditto.
- (CODE_FOR_lsx_vslli_b): Ditto.
- (CODE_FOR_lsx_vslli_h): Ditto.
- (CODE_FOR_lsx_vslli_w): Ditto.
- (CODE_FOR_lsx_vslli_d): Ditto.
- (CODE_FOR_lsx_vsra_b): Ditto.
- (CODE_FOR_lsx_vsra_h): Ditto.
- (CODE_FOR_lsx_vsra_w): Ditto.
- (CODE_FOR_lsx_vsra_d): Ditto.
- (CODE_FOR_lsx_vsrai_b): Ditto.
- (CODE_FOR_lsx_vsrai_h): Ditto.
- (CODE_FOR_lsx_vsrai_w): Ditto.
- (CODE_FOR_lsx_vsrai_d): Ditto.
- (CODE_FOR_lsx_vsrl_b): Ditto.
- (CODE_FOR_lsx_vsrl_h): Ditto.
- (CODE_FOR_lsx_vsrl_w): Ditto.
- (CODE_FOR_lsx_vsrl_d): Ditto.
- (CODE_FOR_lsx_vsrli_b): Ditto.
- (CODE_FOR_lsx_vsrli_h): Ditto.
- (CODE_FOR_lsx_vsrli_w): Ditto.
- (CODE_FOR_lsx_vsrli_d): Ditto.
- (CODE_FOR_lsx_vsub_b): Ditto.
- (CODE_FOR_lsx_vsub_h): Ditto.
- (CODE_FOR_lsx_vsub_w): Ditto.
- (CODE_FOR_lsx_vsub_d): Ditto.
- (CODE_FOR_lsx_vsubi_bu): Ditto.
- (CODE_FOR_lsx_vsubi_hu): Ditto.
- (CODE_FOR_lsx_vsubi_wu): Ditto.
- (CODE_FOR_lsx_vsubi_du): Ditto.
- (CODE_FOR_lsx_vpackod_d): Ditto.
- (CODE_FOR_lsx_vpackev_d): Ditto.
- (CODE_FOR_lsx_vpickod_d): Ditto.
- (CODE_FOR_lsx_vpickev_d): Ditto.
- (CODE_FOR_lsx_vrepli_b): Ditto.
- (CODE_FOR_lsx_vrepli_h): Ditto.
- (CODE_FOR_lsx_vrepli_w): Ditto.
- (CODE_FOR_lsx_vrepli_d): Ditto.
- (CODE_FOR_lsx_vsat_b): Ditto.
- (CODE_FOR_lsx_vsat_h): Ditto.
- (CODE_FOR_lsx_vsat_w): Ditto.
- (CODE_FOR_lsx_vsat_d): Ditto.
- (CODE_FOR_lsx_vsat_bu): Ditto.
- (CODE_FOR_lsx_vsat_hu): Ditto.
- (CODE_FOR_lsx_vsat_wu): Ditto.
- (CODE_FOR_lsx_vsat_du): Ditto.
- (CODE_FOR_lsx_vavg_b): Ditto.
- (CODE_FOR_lsx_vavg_h): Ditto.
- (CODE_FOR_lsx_vavg_w): Ditto.
- (CODE_FOR_lsx_vavg_d): Ditto.
- (CODE_FOR_lsx_vavg_bu): Ditto.
- (CODE_FOR_lsx_vavg_hu): Ditto.
- (CODE_FOR_lsx_vavg_wu): Ditto.
- (CODE_FOR_lsx_vavg_du): Ditto.
- (CODE_FOR_lsx_vavgr_b): Ditto.
- (CODE_FOR_lsx_vavgr_h): Ditto.
- (CODE_FOR_lsx_vavgr_w): Ditto.
- (CODE_FOR_lsx_vavgr_d): Ditto.
- (CODE_FOR_lsx_vavgr_bu): Ditto.
- (CODE_FOR_lsx_vavgr_hu): Ditto.
- (CODE_FOR_lsx_vavgr_wu): Ditto.
- (CODE_FOR_lsx_vavgr_du): Ditto.
- (CODE_FOR_lsx_vssub_b): Ditto.
- (CODE_FOR_lsx_vssub_h): Ditto.
- (CODE_FOR_lsx_vssub_w): Ditto.
- (CODE_FOR_lsx_vssub_d): Ditto.
- (CODE_FOR_lsx_vssub_bu): Ditto.
- (CODE_FOR_lsx_vssub_hu): Ditto.
- (CODE_FOR_lsx_vssub_wu): Ditto.
- (CODE_FOR_lsx_vssub_du): Ditto.
- (CODE_FOR_lsx_vabsd_b): Ditto.
- (CODE_FOR_lsx_vabsd_h): Ditto.
- (CODE_FOR_lsx_vabsd_w): Ditto.
- (CODE_FOR_lsx_vabsd_d): Ditto.
- (CODE_FOR_lsx_vabsd_bu): Ditto.
- (CODE_FOR_lsx_vabsd_hu): Ditto.
- (CODE_FOR_lsx_vabsd_wu): Ditto.
- (CODE_FOR_lsx_vabsd_du): Ditto.
- (CODE_FOR_lsx_vftint_w_s): Ditto.
- (CODE_FOR_lsx_vftint_l_d): Ditto.
- (CODE_FOR_lsx_vftint_wu_s): Ditto.
- (CODE_FOR_lsx_vftint_lu_d): Ditto.
- (CODE_FOR_lsx_vandn_v): Ditto.
- (CODE_FOR_lsx_vorn_v): Ditto.
- (CODE_FOR_lsx_vneg_b): Ditto.
- (CODE_FOR_lsx_vneg_h): Ditto.
- (CODE_FOR_lsx_vneg_w): Ditto.
- (CODE_FOR_lsx_vneg_d): Ditto.
- (CODE_FOR_lsx_vshuf4i_d): Ditto.
- (CODE_FOR_lsx_vbsrl_v): Ditto.
- (CODE_FOR_lsx_vbsll_v): Ditto.
- (CODE_FOR_lsx_vfmadd_s): Ditto.
- (CODE_FOR_lsx_vfmadd_d): Ditto.
- (CODE_FOR_lsx_vfmsub_s): Ditto.
- (CODE_FOR_lsx_vfmsub_d): Ditto.
- (CODE_FOR_lsx_vfnmadd_s): Ditto.
- (CODE_FOR_lsx_vfnmadd_d): Ditto.
- (CODE_FOR_lsx_vfnmsub_s): Ditto.
- (CODE_FOR_lsx_vfnmsub_d): Ditto.
- (CODE_FOR_lsx_vmuh_b): Ditto.
- (CODE_FOR_lsx_vmuh_h): Ditto.
- (CODE_FOR_lsx_vmuh_w): Ditto.
- (CODE_FOR_lsx_vmuh_d): Ditto.
- (CODE_FOR_lsx_vmuh_bu): Ditto.
- (CODE_FOR_lsx_vmuh_hu): Ditto.
- (CODE_FOR_lsx_vmuh_wu): Ditto.
- (CODE_FOR_lsx_vmuh_du): Ditto.
- (CODE_FOR_lsx_vsllwil_h_b): Ditto.
- (CODE_FOR_lsx_vsllwil_w_h): Ditto.
- (CODE_FOR_lsx_vsllwil_d_w): Ditto.
- (CODE_FOR_lsx_vsllwil_hu_bu): Ditto.
- (CODE_FOR_lsx_vsllwil_wu_hu): Ditto.
- (CODE_FOR_lsx_vsllwil_du_wu): Ditto.
- (CODE_FOR_lsx_vssran_b_h): Ditto.
- (CODE_FOR_lsx_vssran_h_w): Ditto.
- (CODE_FOR_lsx_vssran_w_d): Ditto.
- (CODE_FOR_lsx_vssran_bu_h): Ditto.
- (CODE_FOR_lsx_vssran_hu_w): Ditto.
- (CODE_FOR_lsx_vssran_wu_d): Ditto.
- (CODE_FOR_lsx_vssrarn_b_h): Ditto.
- (CODE_FOR_lsx_vssrarn_h_w): Ditto.
- (CODE_FOR_lsx_vssrarn_w_d): Ditto.
- (CODE_FOR_lsx_vssrarn_bu_h): Ditto.
- (CODE_FOR_lsx_vssrarn_hu_w): Ditto.
- (CODE_FOR_lsx_vssrarn_wu_d): Ditto.
- (CODE_FOR_lsx_vssrln_bu_h): Ditto.
- (CODE_FOR_lsx_vssrln_hu_w): Ditto.
- (CODE_FOR_lsx_vssrln_wu_d): Ditto.
- (CODE_FOR_lsx_vssrlrn_bu_h): Ditto.
- (CODE_FOR_lsx_vssrlrn_hu_w): Ditto.
- (CODE_FOR_lsx_vssrlrn_wu_d): Ditto.
- (loongarch_builtin_vector_type): Ditto.
- (loongarch_build_cvpointer_type): Ditto.
- (LARCH_ATYPE_CVPOINTER): Ditto.
- (LARCH_ATYPE_BOOLEAN): Ditto.
- (LARCH_ATYPE_V2SF): Ditto.
- (LARCH_ATYPE_V2HI): Ditto.
- (LARCH_ATYPE_V2SI): Ditto.
- (LARCH_ATYPE_V4QI): Ditto.
- (LARCH_ATYPE_V4HI): Ditto.
- (LARCH_ATYPE_V8QI): Ditto.
- (LARCH_ATYPE_V2DI): Ditto.
- (LARCH_ATYPE_V4SI): Ditto.
- (LARCH_ATYPE_V8HI): Ditto.
- (LARCH_ATYPE_V16QI): Ditto.
- (LARCH_ATYPE_V2DF): Ditto.
- (LARCH_ATYPE_V4SF): Ditto.
- (LARCH_ATYPE_V4DI): Ditto.
- (LARCH_ATYPE_V8SI): Ditto.
- (LARCH_ATYPE_V16HI): Ditto.
- (LARCH_ATYPE_V32QI): Ditto.
- (LARCH_ATYPE_V4DF): Ditto.
- (LARCH_ATYPE_V8SF): Ditto.
- (LARCH_ATYPE_UV2DI): Ditto.
- (LARCH_ATYPE_UV4SI): Ditto.
- (LARCH_ATYPE_UV8HI): Ditto.
- (LARCH_ATYPE_UV16QI): Ditto.
- (LARCH_ATYPE_UV4DI): Ditto.
- (LARCH_ATYPE_UV8SI): Ditto.
- (LARCH_ATYPE_UV16HI): Ditto.
- (LARCH_ATYPE_UV32QI): Ditto.
- (LARCH_ATYPE_UV2SI): Ditto.
- (LARCH_ATYPE_UV4HI): Ditto.
- (LARCH_ATYPE_UV8QI): Ditto.
- (loongarch_builtin_vectorized_function): Ditto.
- (LARCH_GET_BUILTIN): Ditto.
- (loongarch_expand_builtin_insn): Ditto.
- (loongarch_expand_builtin_lsx_test_branch): Ditto.
- (loongarch_expand_builtin): Ditto.
- * config/loongarch/loongarch-ftypes.def (1): Ditto.
- (2): Ditto.
- (3): Ditto.
- (4): Ditto.
- * config/loongarch/lsxintrin.h: New file.
-
-2023-09-05 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/constraints.md (M): Add Loongson LSX base instruction support.
- (N): Ditto.
- (O): Ditto.
- (P): Ditto.
- (R): Ditto.
- (S): Ditto.
- (YG): Ditto.
- (YA): Ditto.
- (YB): Ditto.
- (Yb): Ditto.
- (Yh): Ditto.
- (Yw): Ditto.
- (YI): Ditto.
- (YC): Ditto.
- (YZ): Ditto.
- (Unv5): Ditto.
- (Uuv5): Ditto.
- (Usv5): Ditto.
- (Uuv6): Ditto.
- (Urv8): Ditto.
- * config/loongarch/genopts/loongarch.opt.in: Ditto.
- * config/loongarch/loongarch-builtins.cc (loongarch_gen_const_int_vector): Ditto.
- * config/loongarch/loongarch-modes.def (VECTOR_MODES): Ditto.
- (VECTOR_MODE): Ditto.
- (INT_MODE): Ditto.
- * config/loongarch/loongarch-protos.h (loongarch_split_move_insn_p): Ditto.
- (loongarch_split_move_insn): Ditto.
- (loongarch_split_128bit_move): Ditto.
- (loongarch_split_128bit_move_p): Ditto.
- (loongarch_split_lsx_copy_d): Ditto.
- (loongarch_split_lsx_insert_d): Ditto.
- (loongarch_split_lsx_fill_d): Ditto.
- (loongarch_expand_vec_cmp): Ditto.
- (loongarch_const_vector_same_val_p): Ditto.
- (loongarch_const_vector_same_bytes_p): Ditto.
- (loongarch_const_vector_same_int_p): Ditto.
- (loongarch_const_vector_shuffle_set_p): Ditto.
- (loongarch_const_vector_bitimm_set_p): Ditto.
- (loongarch_const_vector_bitimm_clr_p): Ditto.
- (loongarch_lsx_vec_parallel_const_half): Ditto.
- (loongarch_gen_const_int_vector): Ditto.
- (loongarch_lsx_output_division): Ditto.
- (loongarch_expand_vector_init): Ditto.
- (loongarch_expand_vec_unpack): Ditto.
- (loongarch_expand_vec_perm): Ditto.
- (loongarch_expand_vector_extract): Ditto.
- (loongarch_expand_vector_reduc): Ditto.
- (loongarch_ldst_scaled_shift): Ditto.
- (loongarch_expand_vec_cond_expr): Ditto.
- (loongarch_expand_vec_cond_mask_expr): Ditto.
- (loongarch_builtin_vectorized_function): Ditto.
- (loongarch_gen_const_int_vector_shuffle): Ditto.
- (loongarch_build_signbit_mask): Ditto.
- * config/loongarch/loongarch.cc (loongarch_pass_aggregate_num_fpr): Ditto.
- (loongarch_setup_incoming_varargs): Ditto.
- (loongarch_emit_move): Ditto.
- (loongarch_const_vector_bitimm_set_p): Ditto.
- (loongarch_const_vector_bitimm_clr_p): Ditto.
- (loongarch_const_vector_same_val_p): Ditto.
- (loongarch_const_vector_same_bytes_p): Ditto.
- (loongarch_const_vector_same_int_p): Ditto.
- (loongarch_const_vector_shuffle_set_p): Ditto.
- (loongarch_symbol_insns): Ditto.
- (loongarch_cannot_force_const_mem): Ditto.
- (loongarch_valid_offset_p): Ditto.
- (loongarch_valid_index_p): Ditto.
- (loongarch_classify_address): Ditto.
- (loongarch_address_insns): Ditto.
- (loongarch_ldst_scaled_shift): Ditto.
- (loongarch_const_insns): Ditto.
- (loongarch_split_move_insn_p): Ditto.
- (loongarch_subword_at_byte): Ditto.
- (loongarch_legitimize_move): Ditto.
- (loongarch_builtin_vectorization_cost): Ditto.
- (loongarch_split_move_p): Ditto.
- (loongarch_split_move): Ditto.
- (loongarch_split_move_insn): Ditto.
- (loongarch_output_move_index_float): Ditto.
- (loongarch_split_128bit_move_p): Ditto.
- (loongarch_split_128bit_move): Ditto.
- (loongarch_split_lsx_copy_d): Ditto.
- (loongarch_split_lsx_insert_d): Ditto.
- (loongarch_split_lsx_fill_d): Ditto.
- (loongarch_output_move): Ditto.
- (loongarch_extend_comparands): Ditto.
- (loongarch_print_operand_reloc): Ditto.
- (loongarch_print_operand): Ditto.
- (loongarch_hard_regno_mode_ok_uncached): Ditto.
- (loongarch_hard_regno_call_part_clobbered): Ditto.
- (loongarch_hard_regno_nregs): Ditto.
- (loongarch_class_max_nregs): Ditto.
- (loongarch_can_change_mode_class): Ditto.
- (loongarch_mode_ok_for_mov_fmt_p): Ditto.
- (loongarch_secondary_reload): Ditto.
- (loongarch_vector_mode_supported_p): Ditto.
- (loongarch_preferred_simd_mode): Ditto.
- (loongarch_autovectorize_vector_modes): Ditto.
- (loongarch_lsx_output_division): Ditto.
- (loongarch_option_override_internal): Ditto.
- (loongarch_hard_regno_caller_save_mode): Ditto.
- (MAX_VECT_LEN): Ditto.
- (loongarch_spill_class): Ditto.
- (struct expand_vec_perm_d): Ditto.
- (loongarch_promote_function_mode): Ditto.
- (loongarch_expand_vselect): Ditto.
- (loongarch_starting_frame_offset): Ditto.
- (loongarch_expand_vselect_vconcat): Ditto.
- (TARGET_ASM_ALIGNED_DI_OP): Ditto.
- (TARGET_OPTION_OVERRIDE): Ditto.
- (TARGET_LEGITIMIZE_ADDRESS): Ditto.
- (TARGET_ASM_SELECT_RTX_SECTION): Ditto.
- (TARGET_ASM_FUNCTION_RODATA_SECTION): Ditto.
- (loongarch_expand_lsx_shuffle): Ditto.
- (TARGET_SCHED_INIT): Ditto.
- (TARGET_SCHED_REORDER): Ditto.
- (TARGET_SCHED_REORDER2): Ditto.
- (TARGET_SCHED_VARIABLE_ISSUE): Ditto.
- (TARGET_SCHED_ADJUST_COST): Ditto.
- (TARGET_SCHED_ISSUE_RATE): Ditto.
- (TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Ditto.
- (TARGET_FUNCTION_OK_FOR_SIBCALL): Ditto.
- (TARGET_VALID_POINTER_MODE): Ditto.
- (TARGET_REGISTER_MOVE_COST): Ditto.
- (TARGET_MEMORY_MOVE_COST): Ditto.
- (TARGET_RTX_COSTS): Ditto.
- (TARGET_ADDRESS_COST): Ditto.
- (TARGET_IN_SMALL_DATA_P): Ditto.
- (TARGET_PREFERRED_RELOAD_CLASS): Ditto.
- (TARGET_ASM_FILE_START_FILE_DIRECTIVE): Ditto.
- (TARGET_EXPAND_BUILTIN_VA_START): Ditto.
- (loongarch_expand_vec_perm): Ditto.
- (TARGET_PROMOTE_FUNCTION_MODE): Ditto.
- (TARGET_RETURN_IN_MEMORY): Ditto.
- (TARGET_FUNCTION_VALUE): Ditto.
- (TARGET_LIBCALL_VALUE): Ditto.
- (loongarch_try_expand_lsx_vshuf_const): Ditto.
- (TARGET_ASM_OUTPUT_MI_THUNK): Ditto.
- (TARGET_ASM_CAN_OUTPUT_MI_THUNK): Ditto.
- (TARGET_PRINT_OPERAND): Ditto.
- (TARGET_PRINT_OPERAND_ADDRESS): Ditto.
- (TARGET_PRINT_OPERAND_PUNCT_VALID_P): Ditto.
- (TARGET_SETUP_INCOMING_VARARGS): Ditto.
- (TARGET_STRICT_ARGUMENT_NAMING): Ditto.
- (TARGET_MUST_PASS_IN_STACK): Ditto.
- (TARGET_PASS_BY_REFERENCE): Ditto.
- (TARGET_ARG_PARTIAL_BYTES): Ditto.
- (TARGET_FUNCTION_ARG): Ditto.
- (TARGET_FUNCTION_ARG_ADVANCE): Ditto.
- (TARGET_FUNCTION_ARG_BOUNDARY): Ditto.
- (TARGET_SCALAR_MODE_SUPPORTED_P): Ditto.
- (TARGET_INIT_BUILTINS): Ditto.
- (loongarch_expand_vec_perm_const_1): Ditto.
- (loongarch_expand_vec_perm_const_2): Ditto.
- (loongarch_vectorize_vec_perm_const): Ditto.
- (loongarch_cpu_sched_reassociation_width): Ditto.
- (loongarch_sched_reassociation_width): Ditto.
- (loongarch_expand_vector_extract): Ditto.
- (emit_reduc_half): Ditto.
- (loongarch_expand_vector_reduc): Ditto.
- (loongarch_expand_vec_unpack): Ditto.
- (loongarch_lsx_vec_parallel_const_half): Ditto.
- (loongarch_constant_elt_p): Ditto.
- (loongarch_gen_const_int_vector_shuffle): Ditto.
- (loongarch_expand_vector_init): Ditto.
- (loongarch_expand_lsx_cmp): Ditto.
- (loongarch_expand_vec_cond_expr): Ditto.
- (loongarch_expand_vec_cond_mask_expr): Ditto.
- (loongarch_expand_vec_cmp): Ditto.
- (loongarch_case_values_threshold): Ditto.
- (loongarch_build_const_vector): Ditto.
- (loongarch_build_signbit_mask): Ditto.
- (loongarch_builtin_support_vector_misalignment): Ditto.
- (TARGET_ASM_ALIGNED_HI_OP): Ditto.
- (TARGET_ASM_ALIGNED_SI_OP): Ditto.
- (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): Ditto.
- (TARGET_VECTOR_MODE_SUPPORTED_P): Ditto.
- (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): Ditto.
- (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Ditto.
- (TARGET_VECTORIZE_VEC_PERM_CONST): Ditto.
- (TARGET_SCHED_REASSOCIATION_WIDTH): Ditto.
- (TARGET_CASE_VALUES_THRESHOLD): Ditto.
- (TARGET_HARD_REGNO_CALL_PART_CLOBBERED): Ditto.
- (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto.
- * config/loongarch/loongarch.h (TARGET_SUPPORTS_WIDE_INT): Ditto.
- (UNITS_PER_LSX_REG): Ditto.
- (BITS_PER_LSX_REG): Ditto.
- (BIGGEST_ALIGNMENT): Ditto.
- (LSX_REG_FIRST): Ditto.
- (LSX_REG_LAST): Ditto.
- (LSX_REG_NUM): Ditto.
- (LSX_REG_P): Ditto.
- (LSX_REG_RTX_P): Ditto.
- (IMM13_OPERAND): Ditto.
- (LSX_SUPPORTED_MODE_P): Ditto.
- * config/loongarch/loongarch.md (unknown,add,sub,not,nor,and,or,xor): Ditto.
- (unknown,add,sub,not,nor,and,or,xor,simd_add): Ditto.
- (unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FCC): Ditto.
- (mode" ): Ditto.
- (DF): Ditto.
- (SF): Ditto.
- (sf): Ditto.
- (DI): Ditto.
- (SI): Ditto.
- * config/loongarch/loongarch.opt: Ditto.
- * config/loongarch/predicates.md (const_lsx_branch_operand): Ditto.
- (const_uimm3_operand): Ditto.
- (const_8_to_11_operand): Ditto.
- (const_12_to_15_operand): Ditto.
- (const_uimm4_operand): Ditto.
- (const_uimm6_operand): Ditto.
- (const_uimm7_operand): Ditto.
- (const_uimm8_operand): Ditto.
- (const_imm5_operand): Ditto.
- (const_imm10_operand): Ditto.
- (const_imm13_operand): Ditto.
- (reg_imm10_operand): Ditto.
- (aq8b_operand): Ditto.
- (aq8h_operand): Ditto.
- (aq8w_operand): Ditto.
- (aq8d_operand): Ditto.
- (aq10b_operand): Ditto.
- (aq10h_operand): Ditto.
- (aq10w_operand): Ditto.
- (aq10d_operand): Ditto.
- (aq12b_operand): Ditto.
- (aq12h_operand): Ditto.
- (aq12w_operand): Ditto.
- (aq12d_operand): Ditto.
- (const_m1_operand): Ditto.
- (reg_or_m1_operand): Ditto.
- (const_exp_2_operand): Ditto.
- (const_exp_4_operand): Ditto.
- (const_exp_8_operand): Ditto.
- (const_exp_16_operand): Ditto.
- (const_exp_32_operand): Ditto.
- (const_0_or_1_operand): Ditto.
- (const_0_to_3_operand): Ditto.
- (const_0_to_7_operand): Ditto.
- (const_2_or_3_operand): Ditto.
- (const_4_to_7_operand): Ditto.
- (const_8_to_15_operand): Ditto.
- (const_16_to_31_operand): Ditto.
- (qi_mask_operand): Ditto.
- (hi_mask_operand): Ditto.
- (si_mask_operand): Ditto.
- (d_operand): Ditto.
- (db4_operand): Ditto.
- (db7_operand): Ditto.
- (db8_operand): Ditto.
- (ib3_operand): Ditto.
- (sb4_operand): Ditto.
- (sb5_operand): Ditto.
- (sb8_operand): Ditto.
- (sd8_operand): Ditto.
- (ub4_operand): Ditto.
- (ub8_operand): Ditto.
- (uh4_operand): Ditto.
- (uw4_operand): Ditto.
- (uw5_operand): Ditto.
- (uw6_operand): Ditto.
- (uw8_operand): Ditto.
- (addiur2_operand): Ditto.
- (addiusp_operand): Ditto.
- (andi16_operand): Ditto.
- (movep_src_register): Ditto.
- (movep_src_operand): Ditto.
- (fcc_reload_operand): Ditto.
- (muldiv_target_operand): Ditto.
- (const_vector_same_val_operand): Ditto.
- (const_vector_same_simm5_operand): Ditto.
- (const_vector_same_uimm5_operand): Ditto.
- (const_vector_same_ximm5_operand): Ditto.
- (const_vector_same_uimm6_operand): Ditto.
- (par_const_vector_shf_set_operand): Ditto.
- (reg_or_vector_same_val_operand): Ditto.
- (reg_or_vector_same_simm5_operand): Ditto.
- (reg_or_vector_same_uimm5_operand): Ditto.
- (reg_or_vector_same_ximm5_operand): Ditto.
- (reg_or_vector_same_uimm6_operand): Ditto.
- * doc/md.texi: Ditto.
- * config/loongarch/lsx.md: New file.
-
-2023-09-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (lookup_vector_type_attribute): Export global.
- (get_all_predecessors): New function.
- (get_all_successors): Ditto.
- * config/riscv/riscv-v.cc (get_all_predecessors): Ditto.
- (get_all_successors): Ditto.
- * config/riscv/riscv-vector-builtins.cc (sizeless_type_p): Export global.
- * config/riscv/riscv-vsetvl.cc (get_all_predecessors): Remove it.
-
-2023-09-05 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc-protos.h (arc_output_addsi): Remove declaration.
- (split_addsi): Likewise.
- * config/arc/arc.cc (arc_print_operand): Add/repurpose 's', 'S',
- 'N', 'x', and 'J' code letters.
- (arc_output_addsi): Make it static.
- (split_addsi): Remove it.
- * config/arc/arc.h (UNSIGNED_INT*): New defines.
- (SINNED_INT*): Likewise.
- * config/arc/arc.md (type): Add add, sub, bxor types.
- (tst_movb): Change code letter from 's' to 'x'.
- (andsi3_i): Likewise.
- (addsi3_mixed): Refurbish the pattern.
- (call_i): Change code letter from 'S' to 'J'.
- * config/arc/arc700.md: Add newly introduced types.
- * config/arc/arcHS.md: Likewsie.
- * config/arc/arcHS4x.md: Likewise.
- * config/arc/constraints.md (Cca, CL2, Csp, C2a): Remove it.
- (CM4): Update description.
- (CP4, C6u, C6n, CIs, C4p): New constraint.
-
-2023-09-05 Claudiu Zissulescu <claziss@gmail.com>
-
- * common/config/arc/arc-common.cc (arc_option_optimization_table):
- Remove mbbit_peephole.
- * config/arc/arc.md (UNSPEC_ARC_DIRECT): Remove.
- (store_direct): Likewise.
- (BBIT peephole2): Likewise.
- * config/arc/arc.opt (mbbit-peephole): Ignore option.
- * doc/invoke.texi (mbbit-peephole): Update document.
-
-2023-09-05 Jakub Jelinek <jakub@redhat.com>
-
- * tree-ssa-tail-merge.cc (replace_block_by): Fix a comment typo:
- avreage -> average.
-
-2023-09-05 Yang Yujie <yangyujie@loongson.cn>
-
- * config/loongarch/loongarch.h (CC1_SPEC): Mark normalized
- options passed from driver to gnat1 as explicit for multilib.
-
-2023-09-05 Yang Yujie <yangyujie@loongson.cn>
-
- * config.gcc: add loongarch*-elf target.
- * config/loongarch/elf.h: New file.
- Link against newlib by default.
-
-2023-09-05 Yang Yujie <yangyujie@loongson.cn>
-
- * config.gcc: use -mstrict-align for building libraries
- if --with-strict-align-lib is given.
- * doc/install.texi: likewise.
-
-2023-09-05 Yang Yujie <yangyujie@loongson.cn>
-
- * config/loongarch/loongarch-c.cc: Export macros
- "__loongarch_{arch,tune}" in the preprocessor.
-
-2023-09-05 Yang Yujie <yangyujie@loongson.cn>
-
- * config.gcc: Make --with-abi= obsolete, decide the default ABI
- with target triplet. Allow specifying multilib library build
- options with --with-multilib-list and --with-multilib-default.
- * config/loongarch/t-linux: Likewise.
- * config/loongarch/genopts/loongarch-strings: Likewise.
- * config/loongarch/loongarch-str.h: Likewise.
- * doc/install.texi: Likewise.
- * config/loongarch/genopts/loongarch.opt.in: Introduce
- -m[no-]l[a]sx options. Only process -m*-float and
- -m[no-]l[a]sx in the GCC driver.
- * config/loongarch/loongarch.opt: Likewise.
- * config/loongarch/la464.md: Likewise.
- * config/loongarch/loongarch-c.cc: Likewise.
- * config/loongarch/loongarch-cpu.cc: Likewise.
- * config/loongarch/loongarch-cpu.h: Likewise.
- * config/loongarch/loongarch-def.c: Likewise.
- * config/loongarch/loongarch-def.h: Likewise.
- * config/loongarch/loongarch-driver.cc: Likewise.
- * config/loongarch/loongarch-driver.h: Likewise.
- * config/loongarch/loongarch-opts.cc: Likewise.
- * config/loongarch/loongarch-opts.h: Likewise.
- * config/loongarch/loongarch.cc: Likewise.
- * doc/invoke.texi: Likewise.
-
-2023-09-05 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md: (V8BFH_128): Renamed to ..
- (VHFBF_128): .. this.
- (V16BFH_256): Renamed to ..
- (VHFBF_256): .. this.
- (avx512f_mov<mode>): Extend to V_128.
- (vcvtnee<bf16_ph>2ps_<mode>): Changed to VHFBF_128.
- (vcvtneo<bf16_ph>2ps_<mode>): Ditto.
- (vcvtnee<bf16_ph>2ps_<mode>): Changed to VHFBF_256.
- (vcvtneo<bf16_ph>2ps_<mode>): Ditto.
- * config/i386/i386-expand.cc (expand_vec_perm_blend):
- Canonicalize vec_merge.
-
-2023-09-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Fix Dynamic status.
- * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto.
- (autovectorize_vector_modes): Ditto.
- (vectorize_related_mode): Ditto.
-
-2023-09-04 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/rs6000/darwin.h (LIB_SPEC): Include libSystemStubs for
- all 32b Darwin PowerPC cases.
-
-2023-09-04 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin-sections.def (static_init_section): Add the
- __TEXT,__StaticInit section.
- * config/darwin.cc (darwin_function_section): Use the static init
- section for global initializers, to match other platform toolchains.
-
-2023-09-04 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin-sections.def (darwin_exception_section): Move to
- the __TEXT segment.
- * config/darwin.cc (darwin_emit_except_table_label): Align before
- the exception table label.
- * config/darwin.h (ASM_PREFERRED_EH_DATA_FORMAT): Use indirect PC-
- relative 4byte relocs.
-
-2023-09-04 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.cc (dump_machopic_symref_flags): New.
- (debug_machopic_symref_flags): New.
-
-2023-09-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-types.def
- (vfloat16mf4_t): Add FP16 intrinsic def.
- (vfloat16mf2_t): Ditto.
- (vfloat16m1_t): Ditto.
- (vfloat16m2_t): Ditto.
- (vfloat16m4_t): Ditto.
- (vfloat16m8_t): Ditto.
-
-2023-09-04 Jiufu Guo <guojiufu@linux.ibm.com>
-
- PR tree-optimization/108757
- * match.pd ((X - N * M) / N): New pattern.
- ((X + N * M) / N): New pattern.
- ((X + C) div_rshift N): New pattern.
-
-2023-09-04 Guo Jie <guojie@loongson.cn>
-
- * config/loongarch/loongarch.md: Support 'G' -> 'k' in
- movsf_hardfloat and movdf_hardfloat.
-
-2023-09-04 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_extend_comparands):
- In unsigned QImode test, check for sign extended subreg and/or
- constant operands, and do a sign extension in that case.
- * config/loongarch/loongarch.md (TARGET_64BIT): Define
- template cbranchqi4.
-
-2023-09-04 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch.md: Allows fixed-point values to be loaded
- from memory into floating-point registers.
-
-2023-09-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec-vls.md (<optab><mode>3): New pattern for
- fmax/fmin
- * config/riscv/vector.md: Add VLS modes to vfmax/vfmin.
-
-2023-09-02 Mikael Morin <mikael@gcc.gnu.org>
-
- * tree-diagnostic.cc (tree_diagnostics_defaults): Delete allocated
- pointer before overwriting it.
-
-2023-09-02 chenxiaolong <chenxiaolong@loongson.cn>
-
- * config/loongarch/loongarch-builtins.cc (loongarch_init_builtins):
- Associate the __float128 type to float128_type_node so that it can
- be recognized by the compiler.
- * config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins):
- Add the flag "FLOAT128_TYPE" to gcc and associate a function
- with the suffix "q" to "f128".
- * doc/extend.texi:Added support for 128-bit floating-point functions on
- the LoongArch architecture.
-
-2023-09-01 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/111069
- * common.opt (fabi-version=): Document version 19.
- * doc/invoke.texi (-fabi-version=): Likewise.
-
-2023-09-01 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_<optab><mode><vconvert>):
- New combine pattern.
- (*cond_<float_cvt><vconvert><mode>): Ditto.
- (*cond_<optab><vnconvert><mode>): Ditto.
- (*cond_<float_cvt><vnconvert><mode>): Ditto.
- (*cond_<optab><mode><vnconvert>): Ditto.
- (*cond_<float_cvt><mode><vnconvert>2): Ditto.
- * config/riscv/autovec.md (<optab><mode><vconvert>2): Adjust.
- (<float_cvt><vconvert><mode>2): Adjust.
- (<optab><vnconvert><mode>2): Adjust.
- (<float_cvt><vnconvert><mode>2): Adjust.
- (<optab><mode><vnconvert>2): Adjust.
- (<float_cvt><mode><vnconvert>2): Adjust.
- * config/riscv/riscv-v.cc (needs_fp_rounding): Add INT->FP extend.
-
-2023-09-01 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_extend<v_double_trunc><mode>):
- New combine pattern.
- (*cond_trunc<mode><v_double_trunc>): Ditto.
- * config/riscv/autovec.md: Adjust.
- * config/riscv/riscv-v.cc (needs_fp_rounding): Add FP extend.
-
-2023-09-01 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_<optab><v_double_trunc><mode>):
- New combine pattern.
- (*cond_<optab><v_quad_trunc><mode>): Ditto.
- (*cond_<optab><v_oct_trunc><mode>): Ditto.
- (*cond_trunc<mode><v_double_trunc>): Ditto.
- * config/riscv/autovec.md (<optab><v_quad_trunc><mode>2): Adjust.
- (<optab><v_oct_trunc><mode>2): Ditto.
-
-2023-09-01 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec.md: Adjust.
- * config/riscv/riscv-protos.h (expand_cond_len_unop): Ditto.
- (expand_cond_len_binop): Ditto.
- * config/riscv/riscv-v.cc (needs_fp_rounding): Ditto.
- (expand_cond_len_op): Ditto.
- (expand_cond_len_unop): Ditto.
- (expand_cond_len_binop): Ditto.
- (expand_cond_len_ternop): Ditto.
-
-2023-09-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (autovectorize_vector_modes): Enable
- VECT_COMPARE_COSTS by default.
-
-2023-09-01 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (vec_extract<mode>qi): New expander.
-
-2023-09-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Add
- dynamic enum.
- * config/riscv/riscv.opt: Add dynamic compile option.
-
-2023-09-01 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec-vls.md (<optab><mode>3): New pattern for
- vls floating-point autovec.
- * config/riscv/vector-iterators.md: New iterator for
- floating-point V and VLS.
- * config/riscv/vector.md: Add VLS to floating-point binop.
-
-2023-09-01 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/19832
- * match.pd: Add pattern to optimize
- `(a != b) ? a OP b : c`.
-
-2023-09-01 Lulu Cheng <chenglulu@loongson.cn>
- Guo Jie <guojie@loongson.cn>
-
- PR target/110484
- * config/loongarch/loongarch.cc (loongarch_emit_stack_tie): Use the
- frame_pointer_needed to determine whether to use the $fp register.
-
-2023-08-31 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110915
- * match.pd (min_value, max_value): Extend to vector constants.
-
-2023-08-31 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-
- * config.in: Regenerate.
- * config/darwin-c.cc: Change spelling to macOS.
- * config/darwin-driver.cc: Likewise.
- * config/darwin.h: Likewise.
- * configure.ac: Likewise.
- * doc/contrib.texi: Likewise.
- * doc/extend.texi: Likewise.
- * doc/invoke.texi: Likewise.
- * doc/plugins.texi: Likewise.
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in: Change spelling to macOS.
- * plugin.cc: Likewise.
-
-2023-08-31 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmadd/vfnmacc.
- * config/riscv/autovec.md: Ditto.
-
-2023-08-31 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmsac/vfnmsub
- * config/riscv/autovec.md: Ditto.
-
-2023-08-31 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.md (untyped_call): Emit a call_value
- rather than a call. List each possible destination register
- in the call pattern.
-
-2023-08-31 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmsac/vfmsub
- * config/riscv/autovec.md: Ditto.
-
-2023-08-31 Pan Li <pan2.li@intel.com>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmadd/vfmacc.
- * config/riscv/autovec.md: Ditto.
- * config/riscv/vector-iterators.md: Add UNSPEC_VFFMA.
-
-2023-08-31 Palmer Dabbelt <palmer@rivosinc.com>
-
- * config/riscv/autovec.md (shifts): Use
- vector_scalar_shift_operand.
- * config/riscv/predicates.md (vector_scalar_shift_operand): New
- predicate.
-
-2023-08-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config.gcc: Add vector cost model framework for RVV.
- * config/riscv/riscv.cc (riscv_vectorize_create_costs): Ditto.
- (TARGET_VECTORIZE_CREATE_COSTS): Ditto.
- * config/riscv/t-riscv: Ditto.
- * config/riscv/riscv-vector-costs.cc: New file.
- * config/riscv/riscv-vector-costs.h: New file.
-
-2023-08-31 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
-
- PR target/110411
- * config/rs6000/mma.md (define_insn_and_split movoo): Disallow
- AltiVec address operands.
- (define_insn_and_split movxo): Likewise.
- * config/rs6000/predicates.md (vsx_quad_dform_memory_operand): Remove
- redundant mode size check.
-
-2023-08-31 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-protos.h (IS_AGNOSTIC): Move to here.
- * config/riscv/riscv-v.cc (gen_no_side_effects_vsetvl_rtx):
- Change to default policy.
- * config/riscv/riscv-vector-builtins-bases.cc: Change to default policy.
- * config/riscv/riscv-vsetvl.h (IS_AGNOSTIC): Delete.
- * config/riscv/riscv.cc (riscv_print_operand): Use IS_AGNOSTIC to test.
-
-2023-08-31 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md: Adjust.
- * config/riscv/autovec-vls.md: Ditto.
- * config/riscv/autovec.md: Ditto.
- * config/riscv/riscv-protos.h (enum insn_type): Add insn_type.
- (enum insn_flags): Add insn flags.
- (emit_vlmax_insn): Adjust.
- (emit_vlmax_fp_insn): Delete.
- (emit_vlmax_ternary_insn): Delete.
- (emit_vlmax_fp_ternary_insn): Delete.
- (emit_nonvlmax_insn): Adjust.
- (emit_vlmax_slide_insn): Delete.
- (emit_nonvlmax_slide_tu_insn): Delete.
- (emit_vlmax_merge_insn): Delete.
- (emit_vlmax_cmp_insn): Delete.
- (emit_vlmax_cmp_mu_insn): Delete.
- (emit_vlmax_masked_mu_insn): Delete.
- (emit_scalar_move_insn): Delete.
- (emit_nonvlmax_integer_move_insn): Delete.
- (emit_vlmax_insn_lra): Add.
- * config/riscv/riscv-v.cc (get_mask_mode_from_insn_flags): New.
- (emit_vlmax_insn): Adjust.
- (emit_nonvlmax_insn): Adjust.
- (emit_vlmax_insn_lra): Add.
- (emit_vlmax_fp_insn): Delete.
- (emit_vlmax_ternary_insn): Delete.
- (emit_vlmax_fp_ternary_insn): Delete.
- (emit_vlmax_slide_insn): Delete.
- (emit_nonvlmax_slide_tu_insn): Delete.
- (emit_nonvlmax_slide_insn): Delete.
- (emit_vlmax_merge_insn): Delete.
- (emit_vlmax_cmp_insn): Delete.
- (emit_vlmax_cmp_mu_insn): Delete.
- (emit_vlmax_masked_insn): Delete.
- (emit_nonvlmax_masked_insn): Delete.
- (emit_vlmax_masked_store_insn): Delete.
- (emit_nonvlmax_masked_store_insn): Delete.
- (emit_vlmax_masked_mu_insn): Delete.
- (emit_vlmax_masked_fp_mu_insn): Delete.
- (emit_nonvlmax_tu_insn): Delete.
- (emit_nonvlmax_fp_tu_insn): Delete.
- (emit_nonvlmax_tumu_insn): Delete.
- (emit_nonvlmax_fp_tumu_insn): Delete.
- (emit_scalar_move_insn): Delete.
- (emit_cpop_insn): Delete.
- (emit_vlmax_integer_move_insn): Delete.
- (emit_nonvlmax_integer_move_insn): Delete.
- (emit_vlmax_gather_insn): Delete.
- (emit_vlmax_masked_gather_mu_insn): Delete.
- (emit_vlmax_compress_insn): Delete.
- (emit_nonvlmax_compress_insn): Delete.
- (emit_vlmax_reduction_insn): Delete.
- (emit_vlmax_fp_reduction_insn): Delete.
- (emit_nonvlmax_fp_reduction_insn): Delete.
- (expand_vec_series): Adjust.
- (expand_const_vector): Adjust.
- (legitimize_move): Adjust.
- (sew64_scalar_helper): Adjust.
- (expand_tuple_move): Adjust.
- (expand_vector_init_insert_elems): Adjust.
- (expand_vector_init_merge_repeating_sequence): Adjust.
- (expand_vec_cmp): Adjust.
- (expand_vec_cmp_float): Adjust.
- (expand_vec_perm): Adjust.
- (shuffle_merge_patterns): Adjust.
- (shuffle_compress_patterns): Adjust.
- (shuffle_decompress_patterns): Adjust.
- (expand_load_store): Adjust.
- (expand_cond_len_op): Adjust.
- (expand_cond_len_unop): Adjust.
- (expand_cond_len_binop): Adjust.
- (expand_gather_scatter): Adjust.
- (expand_cond_len_ternop): Adjust.
- (expand_reduction): Adjust.
- (expand_lanes_load_store): Adjust.
- (expand_fold_extract_last): Adjust.
- * config/riscv/riscv.cc (vector_zero_call_used_regs): Adjust.
- * config/riscv/vector.md: Adjust.
-
-2023-08-31 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/96762
- * config/rs6000/rs6000-string.cc (expand_block_move): Call vector
- load/store with length only on 64-bit Power10.
-
-2023-08-31 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc.cc (arc_split_mov_const): Use LSL16 only when
- SWAP option is enabled.
- * config/arc/arc.md (ashlsi2_cnt16): Likewise.
-
-2023-08-31 Stamatis Markianos-Wright <stam.markianos-wright@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vcaddq_rot90, vcaddq_rot270):
- Use common insn for signed and unsigned front-end definitions.
- * config/arm/arm_mve_builtins.def
- (vcaddq_rot90_m_u, vcaddq_rot270_m_u): Make common.
- (vcaddq_rot90_m_s, vcaddq_rot270_m_s): Remove.
- * config/arm/iterators.md (mve_insn): Merge signed and unsigned defs.
- (isu): Likewise.
- (rot): Likewise.
- (mve_rot): Likewise.
- (supf): Likewise.
- (VxCADDQ_M): Likewise.
- * config/arm/unspecs.md (unspec): Likewise.
- * config/arm/mve.md: Fix minor typo.
-
-2023-08-31 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (<avx512>_blendm<mode>): Merge
- VF_AVX512HFBFVL into VI12HFBF_AVX512VL.
- (VF_AVX512HFBF16): Renamed to VHFBF.
- (VF_AVX512FP16VL): Renamed to VHF_AVX512VL.
- (VF_AVX512FP16): Removed.
- (div<mode>3): Adjust VF_AVX512FP16VL to VHF_AVX512VL.
- (avx512fp16_rcp<mode>2<mask_name>): Ditto.
- (rsqrt<mode>2): Ditto.
- (<sse>_rsqrt<mode>2<mask_name>): Ditto.
- (vcond<mode><code>): Ditto.
- (vcond<sseintvecmodelower><mode>): Ditto.
- (<avx512>_fmaddc_<mode>_mask1<round_expand_name>): Ditto.
- (<avx512>_fmaddc_<mode>_maskz<round_expand_name>): Ditto.
- (<avx512>_fcmaddc_<mode>_mask1<round_expand_name>): Ditto.
- (<avx512>_fcmaddc_<mode>_maskz<round_expand_name>): Ditto.
- (cmla<conj_op><mode>4): Ditto.
- (fma_<mode>_fadd_fmul): Ditto.
- (fma_<mode>_fadd_fcmul): Ditto.
- (fma_<complexopname>_<mode>_fma_zero): Ditto.
- (fma_<mode>_fmaddc_bcst): Ditto.
- (fma_<mode>_fcmaddc_bcst): Ditto.
- (<avx512>_<complexopname>_<mode>_mask<round_name>): Ditto.
- (cmul<conj_op><mode>3): Ditto.
- (<avx512>_<complexopname>_<mode><maskc_name><round_name>):
- Ditto.
- (vec_unpacks_lo_<mode>): Ditto.
- (vec_unpacks_hi_<mode>): Ditto.
- (vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Ditto.
- (vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Ditto.
- (*vec_extract<mode>_0): Ditto.
- (*<avx512>_cmp<mode>3): Extend to V48H_AVX512VL.
-
-2023-08-31 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/111234
- * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
-
-2023-08-31 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * range-op-mixed.h (operator_plus::overflow_free_p): New declare.
- (operator_minus::overflow_free_p): New declare.
- (operator_mult::overflow_free_p): New declare.
- * range-op.cc (range_op_handler::overflow_free_p): New function.
- (range_operator::overflow_free_p): New default function.
- (operator_plus::overflow_free_p): New function.
- (operator_minus::overflow_free_p): New function.
- (operator_mult::overflow_free_p): New function.
- * range-op.h (range_op_handler::overflow_free_p): New declare.
- (range_operator::overflow_free_p): New declare.
- * value-range.cc (irange::nonnegative_p): New function.
- (irange::nonpositive_p): New function.
- * value-range.h (irange::nonnegative_p): New declare.
- (irange::nonpositive_p): New declare.
-
-2023-08-30 Dimitar Dimitrov <dimitar@dinux.eu>
-
- PR target/106562
- * config/pru/predicates.md (const_0_operand): New predicate.
- (pru_cstore_comparison_operator): Ditto.
- * config/pru/pru.md (cstore<mode>4): New pattern.
- (cstoredi4): Ditto.
-
-2023-08-30 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111228
- * match.pd ((vec_perm (vec_perm ..) @5 ..) -> (vec_perm @x @5 ..)):
- New simplifications.
-
-2023-08-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (movmisalign<mode>): Delete.
-
-2023-08-30 Die Li <lidie@eswincomputing.com>
- Fei Gao <gaofei@eswincomputing.com>
-
- * config/riscv/peephole.md: New pattern.
- * config/riscv/predicates.md (a0a1_reg_operand): New predicate.
- (zcmp_mv_sreg_operand): New predicate.
- * config/riscv/riscv.md: New predicate.
- * config/riscv/zc.md (*mva01s<X:mode>): New pattern.
- (*mvsa01<X:mode>): New pattern.
-
-2023-08-30 Fei Gao <gaofei@eswincomputing.com>
-
- * config/riscv/riscv.cc
- (riscv_zcmp_can_use_popretz): true if popretz can be used
- (riscv_gen_multi_pop_insn): interface to generate cm.pop[ret][z]
- (riscv_expand_epilogue): expand cm.pop[ret][z] in epilogue
- * config/riscv/riscv.md: define A0_REGNUM
- * config/riscv/zc.md
- (@gpr_multi_popretz_up_to_ra_<mode>): md for popretz ra
- (@gpr_multi_popretz_up_to_s0_<mode>): md for popretz ra, s0
- (@gpr_multi_popretz_up_to_s1_<mode>): likewise
- (@gpr_multi_popretz_up_to_s2_<mode>): likewise
- (@gpr_multi_popretz_up_to_s3_<mode>): likewise
- (@gpr_multi_popretz_up_to_s4_<mode>): likewise
- (@gpr_multi_popretz_up_to_s5_<mode>): likewise
- (@gpr_multi_popretz_up_to_s6_<mode>): likewise
- (@gpr_multi_popretz_up_to_s7_<mode>): likewise
- (@gpr_multi_popretz_up_to_s8_<mode>): likewise
- (@gpr_multi_popretz_up_to_s9_<mode>): likewise
- (@gpr_multi_popretz_up_to_s11_<mode>): likewise
-
-2023-08-30 Fei Gao <gaofei@eswincomputing.com>
-
- * config/riscv/iterators.md
- (slot0_offset): slot 0 offset in stack GPRs area in bytes
- (slot1_offset): slot 1 offset in stack GPRs area in bytes
- (slot2_offset): likewise
- (slot3_offset): likewise
- (slot4_offset): likewise
- (slot5_offset): likewise
- (slot6_offset): likewise
- (slot7_offset): likewise
- (slot8_offset): likewise
- (slot9_offset): likewise
- (slot10_offset): likewise
- (slot11_offset): likewise
- (slot12_offset): likewise
- * config/riscv/predicates.md
- (stack_push_up_to_ra_operand): predicates of stack adjust pushing ra
- (stack_push_up_to_s0_operand): predicates of stack adjust pushing ra, s0
- (stack_push_up_to_s1_operand): likewise
- (stack_push_up_to_s2_operand): likewise
- (stack_push_up_to_s3_operand): likewise
- (stack_push_up_to_s4_operand): likewise
- (stack_push_up_to_s5_operand): likewise
- (stack_push_up_to_s6_operand): likewise
- (stack_push_up_to_s7_operand): likewise
- (stack_push_up_to_s8_operand): likewise
- (stack_push_up_to_s9_operand): likewise
- (stack_push_up_to_s11_operand): likewise
- (stack_pop_up_to_ra_operand): predicates of stack adjust poping ra
- (stack_pop_up_to_s0_operand): predicates of stack adjust poping ra, s0
- (stack_pop_up_to_s1_operand): likewise
- (stack_pop_up_to_s2_operand): likewise
- (stack_pop_up_to_s3_operand): likewise
- (stack_pop_up_to_s4_operand): likewise
- (stack_pop_up_to_s5_operand): likewise
- (stack_pop_up_to_s6_operand): likewise
- (stack_pop_up_to_s7_operand): likewise
- (stack_pop_up_to_s8_operand): likewise
- (stack_pop_up_to_s9_operand): likewise
- (stack_pop_up_to_s11_operand): likewise
- * config/riscv/riscv-protos.h
- (riscv_zcmp_valid_stack_adj_bytes_p):declaration
- * config/riscv/riscv.cc (struct riscv_frame_info): comment change
- (riscv_avoid_multi_push): helper function of riscv_use_multi_push
- (riscv_use_multi_push): true if multi push is used
- (riscv_multi_push_sregs_count): num of sregs in multi-push
- (riscv_multi_push_regs_count): num of regs in multi-push
- (riscv_16bytes_align): align to 16 bytes
- (riscv_stack_align): moved to a better place
- (riscv_save_libcall_count): no functional change
- (riscv_compute_frame_info): add zcmp frame info
- (riscv_for_each_saved_reg): save or restore fprs in specified slot for zcmp
- (riscv_adjust_multi_push_cfi_prologue): adjust cfi for cm.push
- (riscv_gen_multi_push_pop_insn): gen function for multi push and pop
- (get_multi_push_fpr_mask): get mask for the fprs pushed by cm.push
- (riscv_expand_prologue): allocate stack by cm.push
- (riscv_adjust_multi_pop_cfi_epilogue): adjust cfi for cm.pop[ret]
- (riscv_expand_epilogue): allocate stack by cm.pop[ret]
- (zcmp_base_adj): calculate stack adjustment base size
- (zcmp_additional_adj): calculate stack adjustment additional size
- (riscv_zcmp_valid_stack_adj_bytes_p): check if stack adjustment valid
- * config/riscv/riscv.h (RETURN_ADDR_MASK): mask of ra
- (S0_MASK): likewise
- (S1_MASK): likewise
- (S2_MASK): likewise
- (S3_MASK): likewise
- (S4_MASK): likewise
- (S5_MASK): likewise
- (S6_MASK): likewise
- (S7_MASK): likewise
- (S8_MASK): likewise
- (S9_MASK): likewise
- (S10_MASK): likewise
- (S11_MASK): likewise
- (MULTI_PUSH_GPR_MASK): GPR_MASK that cm.push can cover at most
- (ZCMP_MAX_SPIMM): max spimm value
- (ZCMP_SP_INC_STEP): zcmp sp increment step
- (ZCMP_INVALID_S0S10_SREGS_COUNTS): num of s0-s10
- (ZCMP_S0S11_SREGS_COUNTS): num of s0-s11
- (ZCMP_MAX_GRP_SLOTS): max slots of pushing and poping in zcmp
- (CALLEE_SAVED_FREG_NUMBER): get x of fsx(fs0 ~ fs11)
- * config/riscv/riscv.md: include zc.md
- * config/riscv/zc.md: New file. machine description for zcmp
-
-2023-08-30 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/110914
- * tree-ssa-strlen.cc (strlen_pass::handle_builtin_memcpy): Don't call
- adjust_last_stmt unless len is known constant.
-
-2023-08-30 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/111015
- * gimple-ssa-store-merging.cc
- (imm_store_chain_info::output_merged_store): Use wi::mask and
- wide_int_to_tree instead of unsigned HOST_WIDE_INT shift and
- build_int_cst to build BIT_AND_EXPR mask.
-
-2023-08-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): Add MASK_LEN_ variant.
- (call_may_clobber_ref_p_1): Ditto.
- * tree-ssa-loop-ivopts.cc (get_mem_type_for_internal_fn): Ditto.
- (get_alias_ptr_type_for_ptr_address): Ditto.
-
-2023-08-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc
- (vector_insn_info::get_avl_or_vl_reg): Fix bug.
-
-2023-08-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-vls.md (movmisalign<mode>): New pattern.
- * config/riscv/riscv.cc (riscv_support_vector_misalignment): Support
- VLS misalign.
-
-2023-08-29 Philipp Tomsich <philipp.tomsich@vrull.eu>
-
- * config/riscv/zicond.md: New splitters to rewrite single bit
- sign extension as the condition to a czero in the desired form.
-
-2023-08-29 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/99860
- * doc/invoke.texi: Add -Wanalyzer-overlapping-buffers.
-
-2023-08-29 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/99860
- * Makefile.in (ANALYZER_OBJS): Add analyzer/ranges.o.
-
-2023-08-29 Jin Ma <jinma@linux.alibaba.com>
-
- * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli):
- zvfh can generate zfa extended instruction fli.h, just like zfh.
-
-2023-08-29 Edwin Lu <ewlu@rivosinc.com>
- Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Generate
- __riscv_unaligned_avoid with value 1 or
- __riscv_unaligned_slow with value 1 or
- __riscv_unaligned_fast with value 1
- * config/riscv/riscv.cc (riscv_option_override): Define
- riscv_user_wants_strict_align. Set
- riscv_user_wants_strict_align to TARGET_STRICT_ALIGN
- * config/riscv/riscv.h: Declare riscv_user_wants_strict_align
-
-2023-08-29 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/autovec-vls.md: Update types
- * config/riscv/riscv.md: Add vector placeholder type
- * config/riscv/vector.md: Update types
-
-2023-08-29 Carl Love <cel@us.ibm.com>
-
- * config/rs6000/dfp.md (UNSPEC_DQUAN): New unspec.
- (dfp_dqua_<mode>, dfp_dquai_<mode>): New define_insn.
- * config/rs6000/rs6000-builtins.def (__builtin_dfp_dqua,
- __builtin_dfp_dquai, __builtin_dfp_dquaq, __builtin_dfp_dquaqi):
- New buit-in definitions.
- * config/rs6000/rs6000-overload.def (__builtin_dfp_quantize): New
- overloaded definition.
- * doc/extend.texi: Add documentation for __builtin_dfp_quantize.
-
-2023-08-29 Pan Li <pan2.li@intel.com>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_legitimize_poly_move): New declaration.
- (riscv_legitimize_const_move): Handle ref plus const poly.
-
-2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_implied_info): Add implications from unprivileged extensions.
- (riscv_ext_version_table): Add stub support for all unprivileged
- extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'.
-
-2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc (riscv_ext_version_table):
- Add stub support for all vendor extensions supported by Binutils.
-
-2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_implied_info): Add implications from privileged extensions.
- (riscv_ext_version_table): Add stub support for all privileged
- extensions supported by Binutils.
-
-2023-08-29 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec.md: Adjust
- * config/riscv/riscv-protos.h (RVV_VUNDEF): Clean.
- (get_vlmax_rtx): Exported.
- * config/riscv/riscv-v.cc (emit_nonvlmax_fp_ternary_tu_insn): Deleted.
- (emit_vlmax_masked_gather_mu_insn): Adjust.
- (get_vlmax_rtx): New func.
- (expand_load_store): Adjust.
- (expand_cond_len_unop): Call expand_cond_len_op.
- (expand_cond_len_op): New subroutine.
- (expand_cond_len_binop): Call expand_cond_len_op.
- (expand_cond_len_ternop): Call expand_cond_len_op.
- (expand_lanes_load_store): Adjust.
-
-2023-08-29 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/79173
- PR middle-end/111209
- * tree-ssa-math-opts.cc (match_uaddc_usubc): Match also
- just 2 limb uaddc/usubc with 0 carry-in on lower limb and ignored
- carry-out on higher limb. Don't match it though if it could be
- matched later on 4 argument addition/subtraction.
-
-2023-08-29 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111147
- * match.pd (`(x | y) & (~x ^ y)`) Use bitwise_inverted_equal_p
- instead of matching bit_not.
-
-2023-08-29 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins.cc (type_suffixes): Add missing
- initializer.
-
-2023-08-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (vector_insn_info::get_avl_or_vl_reg): New function.
- (pass_vsetvl::compute_local_properties): Fix bug.
- (pass_vsetvl::commit_vsetvls): Ditto.
- * config/riscv/riscv-vsetvl.h: New function.
-
-2023-08-29 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/110943
- * config/riscv/predicates.md (vector_const_int_or_double_0_operand):
- New predicate.
- * config/riscv/riscv-vector-builtins.cc (function_expander::function_expander):
- force_reg mem target operand.
- * config/riscv/vector.md (@pred_mov<mode>): Wrapper.
- (*pred_mov<mode>): Remove imm -> reg pattern.
- (*pred_broadcast<mode>_imm): Add imm -> reg pattern.
-
-2023-08-29 Lulu Cheng <chenglulu@loongson.cn>
-
- * common/config/loongarch/loongarch-common.cc:
- Enable '-free' on O2 and above.
- * doc/invoke.texi: Modify the description information
- of the '-free' compilation option and add the LoongArch
- description.
-
-2023-08-28 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * doc/extend.texi: Fix the description of __builtin_riscv_pause.
-
-2023-08-28 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc (riscv_ext_version_table):
- Implement the 'Zihintpause' extension, version 2.0.
- (riscv_ext_flag_table) Add 'Zihintpause' handling.
- * config/riscv/riscv-builtins.cc: Remove availability predicate
- "always" and add "hint_pause".
- (riscv_builtins) : Add "pause" extension.
- * config/riscv/riscv-opts.h (MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New.
- * config/riscv/riscv.md (riscv_pause): Adjust output based on
- TARGET_ZIHINTPAUSE.
-
-2023-08-28 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`(X & ~Y) | (~X & Y)`): Use bitwise_inverted_equal_p
- instead of specifically checking for ~X.
-
-2023-08-28 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111146
- * match.pd (`(x | y) & ~x`, `(x & y) | ~x`): Remove
- redundant pattern.
-
-2023-08-28 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (gimple_simplify_phiopt): Add dump information
- when resimplify returns true.
- (match_simplify_replacement): Print only if accepted the match-and-simplify
- result rather than the full sequence.
-
-2023-08-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::earliest_fusion): Skip
- never probability.
- (pass_vsetvl::compute_probabilities): Fix unitialized probability.
-
-2023-08-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::earliest_fusion): Fix bug.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-base.cc (vmullbq_poly)
- (vmulltq_poly): New.
- * config/arm/arm-mve-builtins-base.def (vmullbq_poly)
- (vmulltq_poly): New.
- * config/arm/arm-mve-builtins-base.h (vmullbq_poly)
- (vmulltq_poly): New.
- * config/arm/arm_mve.h (vmulltq_poly): Remove.
- (vmullbq_poly): Remove.
- (vmullbq_poly_m): Remove.
- (vmulltq_poly_m): Remove.
- (vmullbq_poly_x): Remove.
- (vmulltq_poly_x): Remove.
- (vmulltq_poly_p8): Remove.
- (vmullbq_poly_p8): Remove.
- (vmulltq_poly_p16): Remove.
- (vmullbq_poly_p16): Remove.
- (vmullbq_poly_m_p8): Remove.
- (vmullbq_poly_m_p16): Remove.
- (vmulltq_poly_m_p8): Remove.
- (vmulltq_poly_m_p16): Remove.
- (vmullbq_poly_x_p8): Remove.
- (vmullbq_poly_x_p16): Remove.
- (vmulltq_poly_x_p8): Remove.
- (vmulltq_poly_x_p16): Remove.
- (__arm_vmulltq_poly_p8): Remove.
- (__arm_vmullbq_poly_p8): Remove.
- (__arm_vmulltq_poly_p16): Remove.
- (__arm_vmullbq_poly_p16): Remove.
- (__arm_vmullbq_poly_m_p8): Remove.
- (__arm_vmullbq_poly_m_p16): Remove.
- (__arm_vmulltq_poly_m_p8): Remove.
- (__arm_vmulltq_poly_m_p16): Remove.
- (__arm_vmullbq_poly_x_p8): Remove.
- (__arm_vmullbq_poly_x_p16): Remove.
- (__arm_vmulltq_poly_x_p8): Remove.
- (__arm_vmulltq_poly_x_p16): Remove.
- (__arm_vmulltq_poly): Remove.
- (__arm_vmullbq_poly): Remove.
- (__arm_vmullbq_poly_m): Remove.
- (__arm_vmulltq_poly_m): Remove.
- (__arm_vmullbq_poly_x): Remove.
- (__arm_vmulltq_poly_x): Remove.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-functions.h (class
- unspec_mve_function_exact_insn_vmull_poly): New.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_widen_poly): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_widen_poly): New.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (parse_element_type): Add
- support for 'U' and 'p' format specifiers.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins.cc (type_suffixes): Handle poly_p
- field..
- (TYPES_poly_8_16): New.
- (poly_8_16): New.
- * config/arm/arm-mve-builtins.def (p8): New type suffix.
- (p16): Likewise.
- * config/arm/arm-mve-builtins.h (enum type_class_index): Add
- TYPE_poly.
- (struct type_suffix_info): Add poly_p field.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-base.cc (vmullbq_int, vmulltq_int):
- New.
- * config/arm/arm-mve-builtins-base.def (vmullbq_int, vmulltq_int):
- New.
- * config/arm/arm-mve-builtins-base.h (vmullbq_int, vmulltq_int):
- New.
- * config/arm/arm_mve.h (vmulltq_int): Remove.
- (vmullbq_int): Remove.
- (vmullbq_int_m): Remove.
- (vmulltq_int_m): Remove.
- (vmullbq_int_x): Remove.
- (vmulltq_int_x): Remove.
- (vmulltq_int_u8): Remove.
- (vmullbq_int_u8): Remove.
- (vmulltq_int_s8): Remove.
- (vmullbq_int_s8): Remove.
- (vmulltq_int_u16): Remove.
- (vmullbq_int_u16): Remove.
- (vmulltq_int_s16): Remove.
- (vmullbq_int_s16): Remove.
- (vmulltq_int_u32): Remove.
- (vmullbq_int_u32): Remove.
- (vmulltq_int_s32): Remove.
- (vmullbq_int_s32): Remove.
- (vmullbq_int_m_s8): Remove.
- (vmullbq_int_m_s32): Remove.
- (vmullbq_int_m_s16): Remove.
- (vmullbq_int_m_u8): Remove.
- (vmullbq_int_m_u32): Remove.
- (vmullbq_int_m_u16): Remove.
- (vmulltq_int_m_s8): Remove.
- (vmulltq_int_m_s32): Remove.
- (vmulltq_int_m_s16): Remove.
- (vmulltq_int_m_u8): Remove.
- (vmulltq_int_m_u32): Remove.
- (vmulltq_int_m_u16): Remove.
- (vmullbq_int_x_s8): Remove.
- (vmullbq_int_x_s16): Remove.
- (vmullbq_int_x_s32): Remove.
- (vmullbq_int_x_u8): Remove.
- (vmullbq_int_x_u16): Remove.
- (vmullbq_int_x_u32): Remove.
- (vmulltq_int_x_s8): Remove.
- (vmulltq_int_x_s16): Remove.
- (vmulltq_int_x_s32): Remove.
- (vmulltq_int_x_u8): Remove.
- (vmulltq_int_x_u16): Remove.
- (vmulltq_int_x_u32): Remove.
- (__arm_vmulltq_int_u8): Remove.
- (__arm_vmullbq_int_u8): Remove.
- (__arm_vmulltq_int_s8): Remove.
- (__arm_vmullbq_int_s8): Remove.
- (__arm_vmulltq_int_u16): Remove.
- (__arm_vmullbq_int_u16): Remove.
- (__arm_vmulltq_int_s16): Remove.
- (__arm_vmullbq_int_s16): Remove.
- (__arm_vmulltq_int_u32): Remove.
- (__arm_vmullbq_int_u32): Remove.
- (__arm_vmulltq_int_s32): Remove.
- (__arm_vmullbq_int_s32): Remove.
- (__arm_vmullbq_int_m_s8): Remove.
- (__arm_vmullbq_int_m_s32): Remove.
- (__arm_vmullbq_int_m_s16): Remove.
- (__arm_vmullbq_int_m_u8): Remove.
- (__arm_vmullbq_int_m_u32): Remove.
- (__arm_vmullbq_int_m_u16): Remove.
- (__arm_vmulltq_int_m_s8): Remove.
- (__arm_vmulltq_int_m_s32): Remove.
- (__arm_vmulltq_int_m_s16): Remove.
- (__arm_vmulltq_int_m_u8): Remove.
- (__arm_vmulltq_int_m_u32): Remove.
- (__arm_vmulltq_int_m_u16): Remove.
- (__arm_vmullbq_int_x_s8): Remove.
- (__arm_vmullbq_int_x_s16): Remove.
- (__arm_vmullbq_int_x_s32): Remove.
- (__arm_vmullbq_int_x_u8): Remove.
- (__arm_vmullbq_int_x_u16): Remove.
- (__arm_vmullbq_int_x_u32): Remove.
- (__arm_vmulltq_int_x_s8): Remove.
- (__arm_vmulltq_int_x_s16): Remove.
- (__arm_vmulltq_int_x_s32): Remove.
- (__arm_vmulltq_int_x_u8): Remove.
- (__arm_vmulltq_int_x_u16): Remove.
- (__arm_vmulltq_int_x_u32): Remove.
- (__arm_vmulltq_int): Remove.
- (__arm_vmullbq_int): Remove.
- (__arm_vmullbq_int_m): Remove.
- (__arm_vmulltq_int_m): Remove.
- (__arm_vmullbq_int_x): Remove.
- (__arm_vmulltq_int_x): Remove.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_widen): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_widen): New.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-functions.h (class
- unspec_mve_function_exact_insn_vmull): New.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/iterators.md (mve_insn): Add vmullb, vmullt.
- (isu): Add VMULLBQ_INT_S, VMULLBQ_INT_U, VMULLTQ_INT_S,
- VMULLTQ_INT_U.
- (supf): Add VMULLBQ_POLY_P, VMULLTQ_POLY_P, VMULLBQ_POLY_M_P,
- VMULLTQ_POLY_M_P.
- (VMULLBQ_INT, VMULLTQ_INT, VMULLBQ_INT_M, VMULLTQ_INT_M): Delete.
- (VMULLxQ_INT, VMULLxQ_POLY, VMULLxQ_INT_M, VMULLxQ_POLY_M): New.
- * config/arm/mve.md (mve_vmullbq_int_<supf><mode>)
- (mve_vmulltq_int_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_int_<supf><mode>) ... this.
- (mve_vmulltq_poly_p<mode>, mve_vmullbq_poly_p<mode>): Merge into ...
- (@mve_<mve_insn>q_poly_<supf><mode>): ... this.
- (mve_vmullbq_int_m_<supf><mode>, mve_vmulltq_int_m_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_int_m_<supf><mode>): ... this.
- (mve_vmullbq_poly_m_p<mode>, mve_vmulltq_poly_m_p<mode>): Merge into ...
- (@mve_<mve_insn>q_poly_m_<supf><mode>): ... this.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (parse_element_type):
- Remove dead check.
-
-2023-08-28 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_acca_int32): Fix loop bound.
- (binary_acca_int64): Likewise.
-
-2023-08-28 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (fold_range): Handle relations.
-
-2023-08-28 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
- Optimize the function implementation.
-
-2023-08-28 liuhongt <hongtao.liu@intel.com>
-
- PR target/111119
- * config/i386/sse.md (V48_AVX2): Rename to ..
- (V48_128_256): .. this.
- (ssefltmodesuffix): Extend to V4SF/V8SF/V2DF/V4DF.
- (<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Change
- V48_AVX2 to V48_128_256, also generate vmaskmov{ps,pd} for
- integral modes when TARGET_AVX2 is not available.
- (<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>): Ditto.
- (maskload<mode><sseintvecmodelower>): Change V48_AVX2 to
- V48_128_256.
- (maskstore<mode><sseintvecmodelower>): Ditto.
-
-2023-08-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (vsetvl_vtype_change_only_p):
- New function.
- (after_or_same_p): Ditto.
- (find_reg_killed_by): Delete.
- (has_vsetvl_killed_avl_p): Ditto.
- (anticipatable_occurrence_p): Refactor.
- (any_set_in_bb_p): Delete.
- (count_regno_occurrences): Ditto.
- (backward_propagate_worthwhile_p): Ditto.
- (demands_can_be_fused_p): Ditto.
- (earliest_pred_can_be_fused_p): New function.
- (vsetvl_dominated_by_p): Ditto.
- (vector_insn_info::parse_insn): Refactor.
- (vector_insn_info::merge): Refactor.
- (vector_insn_info::dump): Refactor.
- (vector_infos_manager::vector_infos_manager): Refactor.
- (vector_infos_manager::all_empty_predecessor_p): Delete.
- (vector_infos_manager::all_same_avl_p): Ditto.
- (vector_infos_manager::create_bitmap_vectors): Refactor.
- (vector_infos_manager::free_bitmap_vectors): Refactor.
- (vector_infos_manager::dump): Refactor.
- (pass_vsetvl::update_block_info): New function.
- (enum fusion_type): Ditto.
- (pass_vsetvl::get_backward_fusion_type): Delete.
- (pass_vsetvl::hard_empty_block_p): Ditto.
- (pass_vsetvl::backward_demand_fusion): Ditto.
- (pass_vsetvl::forward_demand_fusion): Ditto.
- (pass_vsetvl::demand_fusion): Ditto.
- (pass_vsetvl::cleanup_illegal_dirty_blocks): Ditto.
- (pass_vsetvl::compute_local_properties): Ditto.
- (pass_vsetvl::earliest_fusion): New function.
- (pass_vsetvl::vsetvl_fusion): Ditto.
- (pass_vsetvl::commit_vsetvls): Refactor.
- (get_first_vsetvl_before_rvv_insns): Ditto.
- (pass_vsetvl::global_eliminate_vsetvl_insn): Ditto.
- (pass_vsetvl::cleanup_earliest_vsetvls): New function.
- (pass_vsetvl::df_post_optimization): Refactor.
- (pass_vsetvl::lazy_vsetvl): Ditto.
- * config/riscv/riscv-vsetvl.h: Ditto.
-
-2023-08-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (len_fold_extract_last_<mode>): New pattern.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- (expand_fold_extract_last): New function.
- * config/riscv/riscv-v.cc (emit_nonvlmax_slide_insn): Ditto.
- (emit_cpop_insn): Ditto.
- (emit_nonvlmax_compress_insn): Ditto.
- (expand_fold_extract_last): Ditto.
- * config/riscv/vector.md: Fix vcpop.m ratio demand.
-
-2023-08-25 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/sync-rvwmo.md: updated types to "multi" or
- "atomic" based on number of assembly lines generated
- * config/riscv/sync-ztso.md: likewise
- * config/riscv/sync.md: likewise
-
-2023-08-25 Jin Ma <jinma@linux.alibaba.com>
-
- * common/config/riscv/riscv-common.cc: Add zfa extension version, which depends on
- the F extension.
- * config/riscv/constraints.md (zfli): Constrain the floating point number that the
- instructions FLI.H/S/D can load.
- * config/riscv/iterators.md (ceil): New.
- * config/riscv/riscv-opts.h (MASK_ZFA): New.
- (TARGET_ZFA): New.
- * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): New.
- * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli): New.
- (riscv_cannot_force_const_mem): If instruction FLI.H/S/D can be used, memory is
- not applicable.
- (riscv_const_insns): Likewise.
- (riscv_legitimize_const_move): Likewise.
- (riscv_split_64bit_move_p): If instruction FLI.H/S/D can be used, no split is
- required.
- (riscv_split_doubleword_move): Likewise.
- (riscv_output_move): Output the mov instructions in zfa extension.
- (riscv_print_operand): Output the floating-point value of the FLI.H/S/D immediate
- in assembly.
- (riscv_secondary_memory_needed): Likewise.
- * config/riscv/riscv.md (fminm<mode>3): New.
- (fmaxm<mode>3): New.
- (movsidf2_low_rv32): New.
- (movsidf2_high_rv32): New.
- (movdfsisi3_rv32): New.
- (f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_zfa): New.
- * config/riscv/riscv.opt: New.
-
-2023-08-25 Sandra Loosemore <sandra@codesourcery.com>
-
- * omp-api.h: New.
- * omp-general.cc (omp_runtime_api_procname): New.
- (omp_runtime_api_call): Moved here from omp-low.cc, and make
- non-static.
- * omp-general.h: Include omp-api.h.
- * omp-low.cc (omp_runtime_api_call): Delete this copy.
-
-2023-08-25 Sandra Loosemore <sandra@codesourcery.com>
-
- * doc/generic.texi (OpenMP): Document OMP_STRUCTURED_BLOCK.
- * doc/gimple.texi (GIMPLE instruction set): Add
- GIMPLE_OMP_STRUCTURED_BLOCK.
- (GIMPLE_OMP_STRUCTURED_BLOCK): New subsection.
- * gimple-low.cc (lower_stmt): Error on GIMPLE_OMP_STRUCTURED_BLOCK.
- * gimple-pretty-print.cc (dump_gimple_omp_block): Handle
- GIMPLE_OMP_STRUCTURED_BLOCK.
- (pp_gimple_stmt_1): Likewise.
- * gimple-walk.cc (walk_gimple_stmt): Likewise.
- * gimple.cc (gimple_build_omp_structured_block): New.
- * gimple.def (GIMPLE_OMP_STRUCTURED_BLOCK): New.
- * gimple.h (gimple_build_omp_structured_block): Declare.
- (gimple_has_substatements): Handle GIMPLE_OMP_STRUCTURED_BLOCK.
- (CASE_GIMPLE_OMP): Likewise.
- * gimplify.cc (is_gimple_stmt): Handle OMP_STRUCTURED_BLOCK.
- (gimplify_expr): Likewise.
- * omp-expand.cc (GIMPLE_OMP_STRUCTURED_BLOCK): Error on
- GIMPLE_OMP_STRUCTURED_BLOCK.
- * omp-low.cc (scan_omp_1_stmt): Handle GIMPLE_OMP_STRUCTURED_BLOCK.
- (lower_omp_1): Likewise.
- (diagnose_sb_1): Likewise.
- (diagnose_sb_2): Likewise.
- * tree-inline.cc (remap_gimple_stmt): Handle
- GIMPLE_OMP_STRUCTURED_BLOCK.
- (estimate_num_insns): Likewise.
- * tree-nested.cc (convert_nonlocal_reference_stmt): Likewise.
- (convert_local_reference_stmt): Likewise.
- (convert_gimple_call): Likewise.
- * tree-pretty-print.cc (dump_generic_node): Handle
- OMP_STRUCTURED_BLOCK.
- * tree.def (OMP_STRUCTURED_BLOCK): New.
- * tree.h (OMP_STRUCTURED_BLOCK_BODY): New.
-
-2023-08-25 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_rtx_costs): Adjust const_int
- cost. Add some comments about different constants handling.
-
-2023-08-25 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`a ? one_zero : one_zero`): Move
- below detection of minmax.
-
-2023-08-25 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`a | C -> C`): New pattern.
-
-2023-08-25 Uros Bizjak <ubizjak@gmail.com>
-
- * caller-save.cc (new_saved_hard_reg):
- Rename TRUE/FALSE to true/false.
- (setup_save_areas): Ditto.
- * gcc.cc (set_collect_gcc_options): Ditto.
- (driver::build_multilib_strings): Ditto.
- (print_multilib_info): Ditto.
- * genautomata.cc (gen_cpu_unit): Ditto.
- (gen_query_cpu_unit): Ditto.
- (gen_bypass): Ditto.
- (gen_excl_set): Ditto.
- (gen_presence_absence_set): Ditto.
- (gen_presence_set): Ditto.
- (gen_final_presence_set): Ditto.
- (gen_absence_set): Ditto.
- (gen_final_absence_set): Ditto.
- (gen_automaton): Ditto.
- (gen_regexp_repeat): Ditto.
- (gen_regexp_allof): Ditto.
- (gen_regexp_oneof): Ditto.
- (gen_regexp_sequence): Ditto.
- (process_decls): Ditto.
- (reserv_sets_are_intersected): Ditto.
- (initiate_excl_sets): Ditto.
- (form_reserv_sets_list): Ditto.
- (check_presence_pattern_sets): Ditto.
- (check_absence_pattern_sets): Ditto.
- (check_regexp_units_distribution): Ditto.
- (check_unit_distributions_to_automata): Ditto.
- (create_ainsns): Ditto.
- (output_insn_code_cases): Ditto.
- (output_internal_dead_lock_func): Ditto.
- (form_important_insn_automata_lists): Ditto.
- * gengtype-state.cc (read_state_files_list): Ditto.
- * gengtype.cc (main): Ditto.
- * gimple-array-bounds.cc (array_bounds_checker::check_array_bounds):
- Ditto.
- * gimple.cc (gimple_build_call_from_tree): Ditto.
- (preprocess_case_label_vec_for_gimple): Ditto.
- * gimplify.cc (gimplify_call_expr): Ditto.
- * ordered-hash-map-tests.cc (test_map_of_int_to_strings): Ditto.
-
-2023-08-25 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111137
- * tree-vect-data-refs.cc (vect_slp_analyze_load_dependences):
- Properly handle grouped stores from other SLP instances.
-
-2023-08-25 Richard Biener <rguenther@suse.de>
-
- * tree-vect-data-refs.cc (vect_slp_analyze_store_dependences):
- Split out from vect_slp_analyze_node_dependences, remove
- dead code.
- (vect_slp_analyze_load_dependences): Split out from
- vect_slp_analyze_node_dependences, adjust comments. Process
- queued stores before any disambiguation.
- (vect_slp_analyze_node_dependences): Remove.
- (vect_slp_analyze_instance_dependence): Adjust.
-
-2023-08-25 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (frelop_early_resolve): Rewrite for better NAN
- handling.
- (operator_not_equal::fold_range): Adjust for relations.
- (operator_lt::fold_range): Same.
- (operator_gt::fold_range): Same.
- (foperator_unordered_equal::fold_range): Same.
- (foperator_unordered_lt::fold_range): Same.
- (foperator_unordered_le::fold_range): Same.
- (foperator_unordered_gt::fold_range): Same.
- (foperator_unordered_ge::fold_range): Same.
-
-2023-08-25 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111136
- * tree-vect-loop.cc (vect_dissolve_slp_only_groups): For
- stores force STMT_VINFO_STRIDED_P and also duplicate that
- to all elements.
-
-2023-08-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::compute_local_properties):
- Add early continue.
-
-2023-08-25 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (vec_set<mode>): Removed.
- (V_128H): Merge into ..
- (V_128): .. this.
- (V_256H): Merge into ..
- (V_256): .. this.
- (V_512): Add V32HF, V32BF.
- (*ssse3_palignr<mode>_perm): Adjust mode iterator from V_128H
- to V_128.
- (vcond<mode><sseintvecmodelower>): Removed
- (vcondu<mode><sseintvecmodelower>): Removed.
- (avx_vbroadcastf128_<mode>): Refator from V_256H to V_256.
-
-2023-08-25 Hongyu Wang <hongyu.wang@intel.com>
-
- PR target/111127
- * config/i386/sse.md (avx512f_cvtne2ps2bf16_<mode>_maskz):
- Adjust paramter order.
-
-2023-08-24 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/94866
- * config/i386/sse.md (*sse2_movq128_<mode>_1): New insn pattern.
-
-2023-08-24 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/105899
- * doc/invoke.texi (Static Analyzer Options): Add "strcat" to the
- list of functions known to the analyzer.
-
-2023-08-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111123
- * tree-ssa-ccp.cc (pass_fold_builtins::execute): Do not
- remove indirect clobbers here ...
- * tree-outof-ssa.cc (rewrite_out_of_ssa): ... but here.
- (remove_indirect_clobbers): New function.
-
-2023-08-24 Jan Hubicka <jh@suse.cz>
-
- * cfg.h (struct control_flow_graph): New field full_profile.
- * auto-profile.cc (afdo_annotate_cfg): Set full_profile to true.
- * cfg.cc (init_flow): Set full_profile to false.
- * graphite.cc (graphite_transform_loops): Set full_profile to false.
- * lto-streamer-in.cc (input_cfg): Initialize full_profile flag.
- * predict.cc (pass_profile::execute): Set full_profile to true.
- * symtab-thunks.cc (expand_thunk): Set full_profile to true.
- * tree-cfg.cc (gimple_verify_flow_info): Verify that profile is full
- if full_profile is set.
- * tree-inline.cc (initialize_cfun): Initialize full_profile.
- (expand_call_inline): Combine full_profile.
-
-2023-08-24 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_build_slp_tree_1): Rename
- load_p to ldst_p, fix mistakes and rely on
- STMT_VINFO_DATA_REF.
-
-2023-08-24 Jan Hubicka <jh@suse.cz>
-
- * gimple-harden-conditionals.cc (insert_check_and_trap): Set count
- of newly build trap bb.
-
-2023-08-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_preferred_else_value): Remove it since
- it forbid COND_LEN_FMS/COND_LEN_FNMS STMT fold.
- (TARGET_PREFERRED_ELSE_VALUE): Ditto.
-
-2023-08-24 Robin Dapp <rdapp.gcc@gmail.com>
-
- * common/config/riscv/riscv-common.cc: Add -fsched-pressure.
- * config/riscv/riscv.cc (riscv_option_override): Set sched
- pressure algorithm.
-
-2023-08-24 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_print_operand): Allow vk operand.
-
-2023-08-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111125
- * tree-vect-slp.cc (vect_slp_function): Split at novector
- loop entry, do not push blocks in novector loops.
-
-2023-08-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/extend.texi: Document the C [[__extension__ ...]] construct.
-
-2023-08-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * genmatch.cc (decision_tree::gen): Support
- COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS gimple fold.
- * gimple-match-exports.cc (gimple_simplify): Ditto.
- (gimple_resimplify6): New function.
- (gimple_resimplify7): New function.
- (gimple_match_op::resimplify): Support
- COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS gimple fold.
- (convert_conditional_op): Ditto.
- (build_call_internal): Ditto.
- (try_conditional_simplification): Ditto.
- (gimple_extract): Ditto.
- * gimple-match.h (gimple_match_cond::gimple_match_cond): Ditto.
- * internal-fn.cc (CASE): Ditto.
-
-2023-08-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111115
- * tree-vectorizer.h (vect_slp_child_index_for_operand): New.
- * tree-vect-data-refs.cc (can_group_stmts_p): Also group
- .MASK_STORE.
- * tree-vect-slp.cc (arg3_arg2_map): New.
- (vect_get_operand_map): Handle IFN_MASK_STORE.
- (vect_slp_child_index_for_operand): New function.
- (vect_build_slp_tree_1): Handle statements with no LHS,
- masked store ifns.
- (vect_remove_slp_scalar_calls): Likewise.
- * tree-vect-stmts.cc (vect_check_store_rhs): Lookup the
- SLP child corresponding to the ifn value index.
- (vectorizable_store): Likewise for the mask index. Support
- masked stores.
- (vectorizable_load): Lookup the SLP child corresponding to the
- ifn mask index.
-
-2023-08-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111125
- * tree-vect-slp.cc (vectorizable_bb_reduc_epilogue): Account
- for the remain_defs processing.
-
-2023-08-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc: Include ssa.h.
- (aarch64_multiply_add_p): Require the second operand of an
- Advanced SIMD subtraction to be a multiplication. Assume that
- such an operation won't be fused if the second operand is used
- multiple times and if the first operand is also a multiplication.
-
-2023-08-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-loop.cc (vectorizable_reduction): Apply
- LEN_FOLD_EXTRACT_LAST.
- * tree-vect-stmts.cc (vectorizable_condition): Ditto.
-
-2023-08-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111128
- * tree-vect-patterns.cc (vect_recog_over_widening_pattern):
- Emit external shift operand inline if we promoted it with
- another pattern stmt.
-
-2023-08-24 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Fix typo.
-
-2023-08-24 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class binop_frm): Removed.
- (class reverse_binop_frm): Ditto.
- (class widen_binop_frm): Ditto.
- (class vfmacc_frm): Ditto.
- (class vfnmacc_frm): Ditto.
- (class vfmsac_frm): Ditto.
- (class vfnmsac_frm): Ditto.
- (class vfmadd_frm): Ditto.
- (class vfnmadd_frm): Ditto.
- (class vfmsub_frm): Ditto.
- (class vfnmsub_frm): Ditto.
- (class vfwmacc_frm): Ditto.
- (class vfwnmacc_frm): Ditto.
- (class vfwmsac_frm): Ditto.
- (class vfwnmsac_frm): Ditto.
- (class unop_frm): Ditto.
- (class vfrec7_frm): Ditto.
- (class binop): Add frm_op_type template arg.
- (class unop): Ditto.
- (class widen_binop): Ditto.
- (class widen_binop_fp): Ditto.
- (class reverse_binop): Ditto.
- (class vfmacc): Ditto.
- (class vfnmsac): Ditto.
- (class vfmadd): Ditto.
- (class vfnmsub): Ditto.
- (class vfnmacc): Ditto.
- (class vfmsac): Ditto.
- (class vfnmadd): Ditto.
- (class vfmsub): Ditto.
- (class vfwmacc): Ditto.
- (class vfwnmacc): Ditto.
- (class vfwmsac): Ditto.
- (class vfwnmsac): Ditto.
- (class float_misc): Ditto.
-
-2023-08-24 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111109
- * match.pd (ior(cond,cond), ior(vec_cond,vec_cond)):
- Add check to make sure cmp and icmp are inverse.
-
-2023-08-24 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/95929
- * match.pd (convert?(-a)): New pattern
- for 1bit integer types.
-
-2023-08-24 Haochen Jiang <haochen.jiang@intel.com>
-
- Revert:
- 2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Add avx10_set and version and detect avx10.1.
- (cpu_indicator_init): Handle avx10.1-512.
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA2_AVX10_512BIT_SET): New.
- (OPTION_MASK_ISA2_AVX10_1_SET): Ditto.
- (OPTION_MASK_ISA2_AVX10_512BIT_UNSET): Ditto.
- (OPTION_MASK_ISA2_AVX10_1_UNSET): Ditto.
- (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10_1.
- (ix86_handle_option): Handle -mavx10.1, -mavx10.1-256 and
- -mavx10.1-512.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_AVX10_512BIT, FEATURE_AVX10_1 and
- FEATURE_AVX10_512BIT.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- AVX10_512BIT, AVX10_1 and AVX10_1_512.
- * config/i386/constraints.md (Yk): Add AVX10_1.
- (Yv): Ditto.
- (k): Ditto.
- * config/i386/cpuid.h (bit_AVX10): New.
- (bit_AVX10_256): Ditto.
- (bit_AVX10_512): Ditto.
- * config/i386/i386-c.cc (ix86_target_macros_internal):
- Define AVX10_512BIT and AVX10_1.
- * config/i386/i386-isa.def
- (AVX10_512BIT): Add DEF_PTA(AVX10_512BIT).
- (AVX10_1): Add DEF_PTA(AVX10_1).
- * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1.
- (ix86_valid_target_attribute_inner_p): Handle avx10-512bit, avx10.1
- and avx10.1-512.
- (ix86_option_override_internal): Enable AVX512{F,VL,BW,DQ,CD,BF16,
- FP16,VBMI,VBMI2,VNNI,IFMA,BITALG,VPOPCNTDQ} features for avx10.1-512.
- (ix86_valid_target_attribute_inner_p): Handle AVX10_1.
- * config/i386/i386.cc (ix86_get_ssemov): Add AVX10_1.
- (ix86_conditional_register_usage): Ditto.
- (ix86_hard_regno_mode_ok): Ditto.
- (ix86_rtx_costs): Ditto.
- * config/i386/i386.h (VALID_MASK_AVX10_MODE): New macro.
- * config/i386/i386.opt: Add option -mavx10.1, -mavx10.1-256 and
- -mavx10.1-512.
- * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
- * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
- * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
- and avx10.1-512.
-
-2023-08-24 Haochen Jiang <haochen.jiang@intel.com>
-
- Revert:
- 2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (ix86_check_avx10): New function to check isa_flags and
- isa_flags_explicit to emit warning when AVX10 is enabled
- by "-m" option.
- (ix86_check_avx512): New function to check isa_flags and
- isa_flags_explicit to emit warning when AVX512 is enabled
- by "-m" option.
- (ix86_handle_option): Do not change the flags when warning
- is emitted.
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Do not append -mno-avx10.1 for -march=native.
-
-2023-08-24 Haochen Jiang <haochen.jiang@intel.com>
-
- Revert:
- 2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (ix86_check_avx10_vector_width): New function to check isa_flags
- to emit a warning when there is a conflict in AVX10 options for
- vector width.
- (ix86_handle_option): Add check for avx10.1-256 and avx10.1-512.
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Do not append -mno-avx10-max-512bit for -march=native.
-
-2023-08-24 Haochen Jiang <haochen.jiang@intel.com>
-
- Revert:
- 2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512vldqintrin.h: Remove target attribute.
- * config/i386/i386-builtin.def (BDESC):
- Add OPTION_MASK_ISA2_AVX10_1.
- * config/i386/i386-builtins.cc (def_builtin): Handle AVX10_1.
- * config/i386/i386-expand.cc
- (ix86_check_builtin_isa_match): Ditto.
- (ix86_expand_sse2_mulvxdi3): Add TARGET_AVX10_1.
- * config/i386/i386.md: Add new isa attribute avx10_1_or_avx512dq
- and avx10_1_or_avx512vl.
- * config/i386/sse.md: (VF2_AVX512VLDQ_AVX10_1): New.
- (VF1_128_256VLDQ_AVX10_1): Ditto.
- (VI8_AVX512VLDQ_AVX10_1): Ditto.
- (<sse>_andnot<mode>3<mask_name>):
- Add TARGET_AVX10_1 and change isa attr from avx512dq to
- avx10_1_or_avx512dq.
- (*andnot<mode>3): Add TARGET_AVX10_1 and change isa attr from
- avx512vl to avx10_1_or_avx512vl.
- (fix<fixunssuffix>_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
- Change iterator to VF2_AVX512VLDQ_AVX10_1. Remove target check.
- (fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
- Ditto.
- (ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
- Ditto.
- (fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
- Change iterator to VF1_128_256VLDQ_AVX10_1. Remove target check.
- (avx512dq_fix<fixunssuffix>_truncv2sfv2di2<mask_name>):
- Add TARGET_AVX10_1.
- (fix<fixunssuffix>_truncv2sfv2di2): Ditto.
- (cond_mul<mode>): Change iterator to VI8_AVX10_1_AVX512DQVL.
- Remove target check.
- (avx512dq_mul<mode>3<mask_name>): Ditto.
- (*avx512dq_mul<mode>3<mask_name>): Ditto.
- (VI4F_BRCST32x2): Add TARGET_AVX512DQ and TARGET_AVX10_1.
- (<mask_codefor>avx512dq_broadcast<mode><mask_name>):
- Remove target check.
- (VI8F_BRCST64x2): Add TARGET_AVX512DQ and TARGET_AVX10_1.
- (<mask_codefor>avx512dq_broadcast<mode><mask_name>_1):
- Remove target check.
- * config/i386/subst.md (mask_mode512bit_condition): Add TARGET_AVX10_1.
- (mask_avx512vl_condition): Ditto.
- (mask): Ditto.
-
-2023-08-24 Haochen Jiang <haochen.jiang@intel.com>
-
- Revert:
- 2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512vldqintrin.h: Remove target attribute.
- * config/i386/i386-builtin.def (BDESC):
- Add OPTION_MASK_ISA2_AVX10_1.
- * config/i386/i386.cc (standard_sse_constant_opcode): Add TARGET_AVX10_1.
- * config/i386/sse.md: (VI48_AVX512VL_AVX10_1): New.
- (VI48_AVX512VLDQ_AVX10_1): Ditto.
- (VF2_AVX512VL): Remove.
- (VI8_256_512VLDQ_AVX10_1): Rename from VI8_256_512.
- Add TARGET_AVX10_1.
- (*<code><mode>3<mask_name>): Change isa attribute to
- avx10_1_or_avx512dq. Add TARGET_AVX10_1.
- (<code><mode>3): Add TARGET_AVX10_1. Change isa attr
- to avx10_1_or_avx512vl.
- (<mask_codefor>avx512dq_cvtps2qq<mode><mask_name><round_name>):
- Change iterator to VI8_256_512VLDQ_AVX10_1. Remove target check.
- (<mask_codefor>avx512dq_cvtps2qqv2di<mask_name>):
- Add TARGET_AVX10_1.
- (<mask_codefor>avx512dq_cvtps2uqq<mode><mask_name><round_name>):
- Change iterator to VI8_256_512VLDQ_AVX10_1. Remove target check.
- (<mask_codefor>avx512dq_cvtps2uqqv2di<mask_name>):
- Add TARGET_AVX10_1.
- (float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>):
- Change iterator to VF2_AVX512VLDQ_AVX10_1. Remove target check.
- (float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>):
- Change iterator to VF1_128_256VLDQ_AVX10_1. Remove target check.
- (float<floatunssuffix>v4div4sf2<mask_name>):
- Add TARGET_AVX10_1.
- (avx512dq_float<floatunssuffix>v2div2sf2): Ditto.
- (*avx512dq_float<floatunssuffix>v2div2sf2): Ditto.
- (float<floatunssuffix>v2div2sf2): Ditto.
- (float<floatunssuffix>v2div2sf2_mask): Ditto.
- (*float<floatunssuffix>v2div2sf2_mask): Ditto.
- (*float<floatunssuffix>v2div2sf2_mask_1): Ditto.
- (<avx512>_cvt<ssemodesuffix>2mask<mode>):
- Change iterator to VI48_AVX512VLDQ_AVX10_1. Remove target check.
- (<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto.
- (*<avx512>_cvtmask2<ssemodesuffix><mode>):
- Change iterator to VI48_AVX512VL_AVX10_1. Remove target check.
- Change when constraint is enabled.
-
-2023-08-24 Haochen Jiang <haochen.jiang@intel.com>
-
- Revert:
- 2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512vldqintrin.h: Remove target attribute.
- * config/i386/i386-builtin.def (BDESC):
- Add OPTION_MASK_ISA2_AVX10_1.
- * config/i386/sse.md (VF_AVX512VLDQ_AVX10_1): New.
- (VFH_AVX512VLDQ_AVX10_1): Ditto.
- (VF1_AVX512VLDQ_AVX10_1): Ditto.
- (<mask_codefor>reducep<mode><mask_name><round_saeonly_name>):
- Change iterator to VFH_AVX512VLDQ_AVX10_1. Remove target check.
- (vec_pack<floatprefix>_float_<mode>): Change iterator to
- VI8_AVX512VLDQ_AVX10_1. Remove target check.
- (vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Change iterator to
- VF1_AVX512VLDQ_AVX10_1. Remove target check.
- (vec_unpack_<fixprefix>fix_trunc_hi_<mode>): Ditto.
- (VI48F_256_DQVL_AVX10_1): Rename from VI48F_256_DQ.
- (avx512vl_vextractf128<mode>): Change iterator to
- VI48F_256_DQVL_AVX10_1. Remove target check.
- (vec_extract_hi_<mode>_mask): Add TARGET_AVX10_1.
- (vec_extract_hi_<mode>): Ditto.
- (avx512vl_vinsert<mode>): Ditto.
- (vec_set_lo_<mode><mask_name>): Ditto.
- (vec_set_hi_<mode><mask_name>): Ditto.
- (avx512dq_rangep<mode><mask_name><round_saeonly_name>): Change
- iterator to VF_AVX512VLDQ_AVX10_1. Remove target check.
- (avx512dq_fpclass<mode><mask_scalar_merge_name>): Change
- iterator to VFH_AVX512VLDQ_AVX10_1. Remove target check.
- * config/i386/subst.md (mask_avx512dq_condition): Add
- TARGET_AVX10_1.
- (mask_scalar_merge): Ditto.
-
-2023-08-24 Haochen Jiang <haochen.jiang@intel.com>
-
- Revert:
- 2023-08-18 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/111051
- * config/i386/avx512vldqintrin.h: Push AVX2 when AVX2 is
- disabled.
-
-2023-08-24 Richard Biener <rguenther@suse.de>
-
- PR debug/111080
- * dwarf2out.cc (prune_unused_types_walk): Handle
- DW_TAG_restrict_type, DW_TAG_shared_type, DW_TAG_atomic_type,
- DW_TAG_immutable_type, DW_TAG_coarray_type, DW_TAG_unspecified_type
- and DW_TAG_dynamic_type as to only output them when referenced.
-
-2023-08-24 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386.cc (ix86_invalid_conversion): Adjust GCC
- V13 to GCC 13.1.
-
-2023-08-24 liuhongt <hongtao.liu@intel.com>
-
- * common/config/i386/i386-common.cc (processor_names): Add new
- member graniterapids-s and arrowlake-s.
- * config/i386/i386-options.cc (processor_alias_table): Update
- table with PROCESSOR_ARROWLAKE_S and
- PROCESSOR_GRANITERAPIDS_D.
- (m_GRANITERAPID_D): New macro.
- (m_ARROWLAKE_S): Ditto.
- (m_CORE_AVX512): Add m_GRANITERAPIDS_D.
- (processor_cost_table): Add icelake_cost for
- PROCESSOR_GRANITERAPIDS_D and alderlake_cost for
- PROCESSOR_ARROWLAKE_S.
- * config/i386/x86-tune.def: Hanlde m_ARROWLAKE_S same as
- m_ARROWLAKE.
- * config/i386/i386.h (enum processor_type): Add new member
- PROCESSOR_GRANITERAPIDS_D and PROCESSOR_ARROWLAKE_S.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Handle
- PROCESSOR_GRANITERAPIDS_D and PROCESSOR_ARROWLAKE_S
-
-2023-08-23 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * lra-eliminations.cc (eliminate_regs_in_insn): Use equivalences to
- to help simplify code further.
-
-2023-08-23 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-fold.cc (fold_using_range::range_of_phi): Tweak output.
- * gimple-range-phi.cc (phi_group::phi_group): Remove unused members.
- Initialize using a range instead of value and edge.
- (phi_group::calculate_using_modifier): Use initializer value and
- process for relations after trying for iteration convergence.
- (phi_group::refine_using_relation): Use initializer range.
- (phi_group::dump): Rework the dump output.
- (phi_analyzer::process_phi): Allow multiple constant initilizers.
- Dump groups immediately as created.
- (phi_analyzer::dump): Tweak output.
- * gimple-range-phi.h (phi_group::phi_group): Adjust prototype.
- (phi_group::initial_value): Delete.
- (phi_group::refine_using_relation): Adjust prototype.
- (phi_group::m_initial_value): Delete.
- (phi_group::m_initial_edge): Delete.
- (phi_group::m_vr): Use int_range_max.
- * tree-vrp.cc (execute_ranger_vrp): Don't dump phi groups.
-
-2023-08-23 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-phi.cc (phi_analyzer::operator[]): Return NULL if
- no group was created.
- (phi_analyzer::process_phi): Do not create groups of one phi node.
-
-2023-08-23 Richard Earnshaw <rearnsha@arm.com>
-
- * target.def (gen_ccmp_first, gen_ccmp_next): Use rtx_code for
- CODE, CMP_CODE and BIT_CODE arguments.
- * config/aarch64/aarch64.cc (aarch64_gen_ccmp_first): Likewise.
- (aarch64_gen_ccmp_next): Likewise.
- * doc/tm.texi: Regenerated.
-
-2023-08-23 Richard Earnshaw <rearnsha@arm.com>
-
- * coretypes.h (rtx_code): Add forward declaration.
- * rtl.h (rtx_code): Make compatible with forward declaration.
-
-2023-08-23 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/111010
- * config/i386/i386.md (*concat<any_or_plus:mode><dwi>3_3):
- Merge pattern from *concatditi3_3 and *concatsidi3_3 using
- DWIH mode iterator. Disable (=&r,m,m) alternative for
- 32-bit targets.
- (*concat<any_or_plus:mode><dwi>3_3): Disable (=&r,m,m)
- alternative for 32-bit targets.
-
-2023-08-23 Zhangjin Liao <liaozhangjin@eswincomputing.com>
-
- * config/riscv/bitmanip.md (*<bitmanip_optab>disi2_sext): Add a more
- appropriate type attribute.
-
-2023-08-23 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_abs<mode>): New combine pattern.
- (*copysign<mode>_neg): Ditto.
- * config/riscv/autovec.md (@vcond_mask_<mode><vm>): Adjust.
- (<optab><mode>2): Ditto.
- (cond_<optab><mode>): New.
- (cond_len_<optab><mode>): Ditto.
- * config/riscv/riscv-protos.h (enum insn_type): New.
- (expand_cond_len_unop): New helper func.
- * config/riscv/riscv-v.cc (shuffle_merge_patterns): Adjust.
- (expand_cond_len_unop): New helper func.
-
-2023-08-23 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-ch.cc (enum ch_decision): Fix comment.
- (should_duplicate_loop_header_p): Fix return value for static exits.
- (ch_base::copy_headers): Improve handling of ch_possible_zero_cost.
-
-2023-08-23 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_store): Move the handlings on
- VMAT_GATHER_SCATTER in the final loop nest to its own loop,
- and update the final nest accordingly.
-
-2023-08-23 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_store): Move the handlings on
- VMAT_LOAD_STORE_LANES in the final loop nest to its own loop,
- and update the final nest accordingly.
-
-2023-08-23 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_store): Remove vec oprnds,
- adjust vec result_chain, vec_oprnd with auto_vec, and adjust
- gvec_oprnds with auto_delete_vec.
-
-2023-08-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc
- (pass_vsetvl::global_eliminate_vsetvl_insn): Fix potential ICE.
-
-2023-08-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (ge_sew_ratio_unavailable_p):
- Fix fuse rule bug.
- * config/riscv/riscv-vsetvl.def (DEF_SEW_LMUL_FUSE_RULE): Ditto.
-
-2023-08-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Add attribute.
-
-2023-08-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (change_insn): Clang format.
- (vector_infos_manager::all_same_ratio_p): Ditto.
- (vector_infos_manager::all_same_avl_p): Ditto.
- (pass_vsetvl::refine_vsetvls): Ditto.
- (pass_vsetvl::cleanup_vsetvls): Ditto.
- (pass_vsetvl::commit_vsetvls): Ditto.
- (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
- (pass_vsetvl::global_eliminate_vsetvl_insn): Ditto.
- (pass_vsetvl::compute_probabilities): Ditto.
-
-2023-08-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/t-riscv: Add riscv-vsetvl.def
-
-2023-08-22 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.opt: Add --param names
- riscv-autovec-preference and riscv-autovec-lmul
-
-2023-08-22 Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
-
- * config/riscv/t-linux: Add MULTIARCH_DIRNAME.
-
-2023-08-22 Tobias Burnus <tobias@codesourcery.com>
-
- * tree-core.h (enum omp_clause_defaultmap_kind): Add
- OMP_CLAUSE_DEFAULTMAP_CATEGORY_ALL.
- * gimplify.cc (gimplify_scan_omp_clauses): Handle it.
- * tree-pretty-print.cc (dump_omp_clause): Likewise.
-
-2023-08-22 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/106652
- * doc/extend.texi (_Float<n>): Drop obsolete sentence that the
- types aren't supported in C++.
-
-2023-08-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * doc/md.texi: Add LEN_FOLD_EXTRACT_LAST pattern.
- * internal-fn.cc (fold_len_extract_direct): Ditto.
- (expand_fold_len_extract_optab_fn): Ditto.
- (direct_fold_len_extract_optab_supported_p): Ditto.
- * internal-fn.def (LEN_FOLD_EXTRACT_LAST): Ditto.
- * optabs.def (OPTAB_D): Ditto.
-
-2023-08-22 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_store): Do not bump
- DR_GROUP_STORE_COUNT here. Remove early out.
- (vect_transform_stmt): Only call vectorizable_store on
- the last element of an interleaving chain.
-
-2023-08-22 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/94864
- PR tree-optimization/94865
- PR tree-optimization/93080
- * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): New pattern
- for vector insertion from vector extraction.
-
-2023-08-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- Kewen.Lin <linkw@linux.ibm.com>
-
- * tree-vect-loop.cc (vect_verify_loop_lens): Add exists check.
- (vectorizable_live_operation): Add live vectorization for length loop
- control.
-
-2023-08-22 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/105899
- * doc/invoke.texi: Remove -Wanalyzer-unterminated-string.
-
-2023-08-22 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (vfwredusum_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwredusum_frm): New intrinsic function def.
-
-2023-08-21 David Faust <david.faust@oracle.com>
-
- * config/bpf/bpf.md (neg): Second operand must be a register.
-
-2023-08-21 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/bitmanip.md: Added bitmanip type to insns
- that are missing types.
-
-2023-08-21 Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Avoid extraenous
- newline.
-
-2023-08-21 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-
- * config/aarch64/falkor-tag-collision-avoidance.cc (dump_insn_list):
- Fix format specifier.
-
-2023-08-21 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (frange::union_nans): Return false if nothing
- changed.
- (range_tests_floats): New test.
-
-2023-08-21 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- PR tree-optimization/111048
- * fold-const.cc (valid_mask_for_fold_vec_perm_cst_p): Set arg_npatterns
- correctly.
- (fold_vec_perm_cst): Remove workaround and again call
- valid_mask_fold_vec_perm_cst_p for both VLS and VLA vectors.
- (test_fold_vec_perm_cst::test_nunits_min_4): Add test-case.
-
-2023-08-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111082
- * tree-vect-slp.cc (vectorize_slp_instance_root_stmt): Only
- pun operations that can overflow.
-
-2023-08-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * lcm.cc (compute_antinout_edge): Export as global use.
- (compute_earliest): Ditto.
- (compute_rev_insert_delete): Ditto.
- * lcm.h (compute_antinout_edge): Ditto.
- (compute_earliest): Ditto.
-
-2023-08-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111070
- * tree-ssa-ifcombine.cc (ifcombine_ifandif): Check we have
- an SSA name before checking SSA_NAME_OCCURS_IN_ABNORMAL_PHI.
-
-2023-08-21 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111002
- * match.pd (view_convert(vec_cond(a,b,c))): New pattern.
-
-2023-08-21 liuhongt <hongtao.liu@intel.com>
-
- * common/config/i386/cpuinfo.h (get_intel_cpu): Detect
- Alderlake-N.
- * common/config/i386/i386-common.cc (alias_table): Support
- -march=gracemont as an alias of -march=alderlake.
-
-2023-08-20 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_sse_extend): Use ops[1]
- instead of src in the call to ix86_expand_sse_cmp.
- * config/i386/sse.md (<any_extend:insn>v8qiv8hi2): Do not
- force operands[1] to a register.
- (<any_extend:insn>v4hiv4si2): Ditto.
- (<any_extend:insn>v2siv2di2): Ditto.
-
-2023-08-20 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/111006
- PR tree-optimization/110986
- * match.pd: (op(vec_cond(a,b,c))): Handle convert for op.
-
-2023-08-20 Eric Gallager <egallager@gcc.gnu.org>
-
- PR target/90835
- * Makefile.in: improve error message when /usr/include is
- missing
-
-2023-08-19 Tobias Burnus <tobias@codesourcery.com>
-
- PR middle-end/111017
- * omp-expand.cc (expand_omp_for_init_vars): Pass after=true
- to expand_omp_build_cond for 'factor != 0' condition, resulting
- in pre-r12-5295-g47de0b56ee455e code for the gimple insert.
-
-2023-08-19 Guo Jie <guojie@loongson.cn>
- Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/t-loongarch: Add loongarch-driver.h into
- TM_H. Add loongarch-def.h and loongarch-tune.h into
- OPTIONS_H_EXTRA.
-
-2023-08-18 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/111023
- * config/i386/i386-expand.cc (ix86_split_mmx_punpck):
- Also handle V2QImode.
- (ix86_expand_sse_extend): New function.
- * config/i386/i386-protos.h (ix86_expand_sse_extend): New prototype.
- * config/i386/mmx.md (<any_extend:insn>v4qiv4hi2): Enable for
- TARGET_SSE2. Expand through ix86_expand_sse_extend for !TARGET_SSE4_1.
- (<any_extend:insn>v2hiv2si2): Ditto.
- (<any_extend:insn>v2qiv2hi2): Ditto.
- * config/i386/sse.md (<any_extend:insn>v8qiv8hi2): Ditto.
- (<any_extend:insn>v4hiv4si2): Ditto.
- (<any_extend:insn>v2siv2di2): Ditto.
-
-2023-08-18 Aldy Hernandez <aldyh@redhat.com>
-
- PR ipa/110753
- * value-range.cc (irange::union_bitmask): Return FALSE if updated
- bitmask is semantically equivalent to the original mask.
- (irange::intersect_bitmask): Same.
- (irange::get_bitmask): Add comment.
-
-2023-08-18 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111019
- * tree-ssa-loop-im.cc (gather_mem_refs_stmt): When canonicalizing
- also scrap base and offset in case the ref is indirect.
-
-2023-08-18 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.opt (mframe-limit): Set default to 32767.
-
-2023-08-18 Kewen Lin <linkw@linux.ibm.com>
-
- PR bootstrap/111021
- * Makefile.in (TM_P_H): Add $(TREE_H) as dependence.
-
-2023-08-18 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_build_scatter_store_calls): New, factor
- out from ...
- (vectorizable_store): ... here.
-
-2023-08-18 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111048
- * fold-const.cc (fold_vec_perm_cst): Check for non-VLA
- vectors first.
-
-2023-08-18 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/111051
- * config/i386/avx512vldqintrin.h: Push AVX2 when AVX2 is
- disabled.
-
-2023-08-18 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_load): Move the handlings on
- VMAT_GATHER_SCATTER in the final loop nest to its own loop,
- and update the final nest accordingly.
-
-2023-08-18 Andrew Pinski <apinski@marvell.com>
-
- * doc/md.texi (Standard patterns): Document cond_neg, cond_one_cmpl,
- cond_len_neg and cond_len_one_cmpl.
-
-2023-08-18 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/iterators.md (TARGET_HARD_FLOAT || TARGET_ZFINX): New.
- * config/riscv/pic.md (*local_pic_load<ANYF:mode>): Change ANYF.
- (*local_pic_load<ANYLSF:mode>): To ANYLSF.
- (*local_pic_load_32d<ANYF:mode>): Ditto.
- (*local_pic_load_32d<ANYLSF:mode>): Ditto.
- (*local_pic_store<ANYF:mode>): Ditto.
- (*local_pic_store<ANYLSF:mode>): Ditto.
- (*local_pic_store_32d<ANYF:mode>): Ditto.
- (*local_pic_store_32d<ANYLSF:mode>): Ditto.
-
-2023-08-18 Lehua Ding <lehua.ding@rivai.ai>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/predicates.md (vector_const_0_operand): New.
- * config/riscv/vector.md (*pred_broadcast<mode>_zero): Ditto.
-
-2023-08-18 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::backward_demand_fusion):
- Forbidden.
-
-2023-08-17 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/111009
- * range-op.cc (operator_addr_expr::op1_range): Be more restrictive.
-
-2023-08-17 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Moving
- slots_num initialization from here ...
- (lra_spill): ... to here before the 1st call of
- assign_stack_slot_num_and_sort_pseudos. Add the 2nd call after
- fp->sp elimination.
-
-2023-08-17 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- PR c/106537
- * doc/invoke.texi (Option Summary): Mention
- -Wcompare-distinct-pointer-types under `Warning Options'.
- (Warning Options): Document -Wcompare-distinct-pointer-types.
-
-2023-08-17 Jan-Benedict Glaw <jbglaw@lug-owl.de>
-
- * recog.cc (memory_address_addr_space_p): Mark possibly unused
- argument as unused.
-
-2023-08-17 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111039
- * tree-ssa-ifcombine.cc (ifcombine_ifandif): Check for
- SSA_NAME_OCCURS_IN_ABNORMAL_PHI.
-
-2023-08-17 Alex Coplan <alex.coplan@arm.com>
-
- * doc/rtl.texi: Fix up sample code for RTL-SSA insn changes.
-
-2023-08-17 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- PR target/111046
- * config/bpf/bpf.cc (bpf_attribute_table): Add entry for the
- `naked' function attribute.
- (bpf_warn_func_return): New function.
- (TARGET_WARN_FUNC_RETURN): Define.
- (bpf_expand_prologue): Add preventive comment.
- (bpf_expand_epilogue): Likewise.
- * doc/extend.texi (BPF Function Attributes): Document the `naked'
- function attribute.
-
-2023-08-17 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_slp_check_for_roots): Use
- !needs_fold_left_reduction_p to decide whether we can
- handle the reduction with association.
- (vectorize_slp_instance_root_stmt): For TYPE_OVERFLOW_UNDEFINED
- reductions perform all arithmetic in an unsigned type.
-
-2023-08-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
-
- * configure.ac (gcc_cv_ld64_version): Allow for dyld in ld -v
- output.
- * configure: Regenerate.
-
-2023-08-17 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (widen_freducop): Add frm_opt_type template arg.
- (vfwredosum_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwredosum_frm): New intrinsic function def.
-
-2023-08-17 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (vfredosum_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfredosum_frm): New intrinsic function def.
-
-2023-08-17 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class freducop): Add frm_op_type template arg.
- (vfredusum_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfredusum_frm): New intrinsic function def.
- * config/riscv/riscv-vector-builtins-shapes.cc
- (struct reduc_alu_frm_def): New class for frm shape.
- (SHAPE): New declaration.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
-
-2023-08-17 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfncvt_f): Add frm_op_type template arg.
- (vfncvt_f_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfncvt_f_frm): New intrinsic function def.
-
-2023-08-17 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (vfncvt_xu_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfncvt_xu_frm): New intrinsic function def.
-
-2023-08-17 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfncvt_x): Add frm_op_type template arg.
- (BASE): New declaration.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfncvt_x_frm): New intrinsic function def.
- * config/riscv/riscv-vector-builtins-shapes.cc
- (struct narrow_alu_frm_def): New shape function for frm.
- (SHAPE): New declaration.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
-
-2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512vldqintrin.h: Remove target attribute.
- * config/i386/i386-builtin.def (BDESC):
- Add OPTION_MASK_ISA2_AVX10_1.
- * config/i386/sse.md (VF_AVX512VLDQ_AVX10_1): New.
- (VFH_AVX512VLDQ_AVX10_1): Ditto.
- (VF1_AVX512VLDQ_AVX10_1): Ditto.
- (<mask_codefor>reducep<mode><mask_name><round_saeonly_name>):
- Change iterator to VFH_AVX512VLDQ_AVX10_1. Remove target check.
- (vec_pack<floatprefix>_float_<mode>): Change iterator to
- VI8_AVX512VLDQ_AVX10_1. Remove target check.
- (vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Change iterator to
- VF1_AVX512VLDQ_AVX10_1. Remove target check.
- (vec_unpack_<fixprefix>fix_trunc_hi_<mode>): Ditto.
- (VI48F_256_DQVL_AVX10_1): Rename from VI48F_256_DQ.
- (avx512vl_vextractf128<mode>): Change iterator to
- VI48F_256_DQVL_AVX10_1. Remove target check.
- (vec_extract_hi_<mode>_mask): Add TARGET_AVX10_1.
- (vec_extract_hi_<mode>): Ditto.
- (avx512vl_vinsert<mode>): Ditto.
- (vec_set_lo_<mode><mask_name>): Ditto.
- (vec_set_hi_<mode><mask_name>): Ditto.
- (avx512dq_rangep<mode><mask_name><round_saeonly_name>): Change
- iterator to VF_AVX512VLDQ_AVX10_1. Remove target check.
- (avx512dq_fpclass<mode><mask_scalar_merge_name>): Change
- iterator to VFH_AVX512VLDQ_AVX10_1. Remove target check.
- * config/i386/subst.md (mask_avx512dq_condition): Add
- TARGET_AVX10_1.
- (mask_scalar_merge): Ditto.
-
-2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512vldqintrin.h: Remove target attribute.
- * config/i386/i386-builtin.def (BDESC):
- Add OPTION_MASK_ISA2_AVX10_1.
- * config/i386/i386.cc (standard_sse_constant_opcode): Add TARGET_AVX10_1.
- * config/i386/sse.md: (VI48_AVX512VL_AVX10_1): New.
- (VI48_AVX512VLDQ_AVX10_1): Ditto.
- (VF2_AVX512VL): Remove.
- (VI8_256_512VLDQ_AVX10_1): Rename from VI8_256_512.
- Add TARGET_AVX10_1.
- (*<code><mode>3<mask_name>): Change isa attribute to
- avx10_1_or_avx512dq. Add TARGET_AVX10_1.
- (<code><mode>3): Add TARGET_AVX10_1. Change isa attr
- to avx10_1_or_avx512vl.
- (<mask_codefor>avx512dq_cvtps2qq<mode><mask_name><round_name>):
- Change iterator to VI8_256_512VLDQ_AVX10_1. Remove target check.
- (<mask_codefor>avx512dq_cvtps2qqv2di<mask_name>):
- Add TARGET_AVX10_1.
- (<mask_codefor>avx512dq_cvtps2uqq<mode><mask_name><round_name>):
- Change iterator to VI8_256_512VLDQ_AVX10_1. Remove target check.
- (<mask_codefor>avx512dq_cvtps2uqqv2di<mask_name>):
- Add TARGET_AVX10_1.
- (float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>):
- Change iterator to VF2_AVX512VLDQ_AVX10_1. Remove target check.
- (float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>):
- Change iterator to VF1_128_256VLDQ_AVX10_1. Remove target check.
- (float<floatunssuffix>v4div4sf2<mask_name>):
- Add TARGET_AVX10_1.
- (avx512dq_float<floatunssuffix>v2div2sf2): Ditto.
- (*avx512dq_float<floatunssuffix>v2div2sf2): Ditto.
- (float<floatunssuffix>v2div2sf2): Ditto.
- (float<floatunssuffix>v2div2sf2_mask): Ditto.
- (*float<floatunssuffix>v2div2sf2_mask): Ditto.
- (*float<floatunssuffix>v2div2sf2_mask_1): Ditto.
- (<avx512>_cvt<ssemodesuffix>2mask<mode>):
- Change iterator to VI48_AVX512VLDQ_AVX10_1. Remove target check.
- (<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto.
- (*<avx512>_cvtmask2<ssemodesuffix><mode>):
- Change iterator to VI48_AVX512VL_AVX10_1. Remove target check.
- Change when constraint is enabled.
-
-2023-08-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111037
- * config/riscv/riscv-vsetvl.cc (float_insn_valid_sew_p): New function.
- (second_sew_less_than_first_sew_p): Fix bug.
- (first_sew_less_than_second_sew_p): Ditto.
-
-2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512vldqintrin.h: Remove target attribute.
- * config/i386/i386-builtin.def (BDESC):
- Add OPTION_MASK_ISA2_AVX10_1.
- * config/i386/i386-builtins.cc (def_builtin): Handle AVX10_1.
- * config/i386/i386-expand.cc
- (ix86_check_builtin_isa_match): Ditto.
- (ix86_expand_sse2_mulvxdi3): Add TARGET_AVX10_1.
- * config/i386/i386.md: Add new isa attribute avx10_1_or_avx512dq
- and avx10_1_or_avx512vl.
- * config/i386/sse.md: (VF2_AVX512VLDQ_AVX10_1): New.
- (VF1_128_256VLDQ_AVX10_1): Ditto.
- (VI8_AVX512VLDQ_AVX10_1): Ditto.
- (<sse>_andnot<mode>3<mask_name>):
- Add TARGET_AVX10_1 and change isa attr from avx512dq to
- avx10_1_or_avx512dq.
- (*andnot<mode>3): Add TARGET_AVX10_1 and change isa attr from
- avx512vl to avx10_1_or_avx512vl.
- (fix<fixunssuffix>_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
- Change iterator to VF2_AVX512VLDQ_AVX10_1. Remove target check.
- (fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
- Ditto.
- (ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
- Ditto.
- (fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
- Change iterator to VF1_128_256VLDQ_AVX10_1. Remove target check.
- (avx512dq_fix<fixunssuffix>_truncv2sfv2di2<mask_name>):
- Add TARGET_AVX10_1.
- (fix<fixunssuffix>_truncv2sfv2di2): Ditto.
- (cond_mul<mode>): Change iterator to VI8_AVX10_1_AVX512DQVL.
- Remove target check.
- (avx512dq_mul<mode>3<mask_name>): Ditto.
- (*avx512dq_mul<mode>3<mask_name>): Ditto.
- (VI4F_BRCST32x2): Add TARGET_AVX512DQ and TARGET_AVX10_1.
- (<mask_codefor>avx512dq_broadcast<mode><mask_name>):
- Remove target check.
- (VI8F_BRCST64x2): Add TARGET_AVX512DQ and TARGET_AVX10_1.
- (<mask_codefor>avx512dq_broadcast<mode><mask_name>_1):
- Remove target check.
- * config/i386/subst.md (mask_mode512bit_condition): Add TARGET_AVX10_1.
- (mask_avx512vl_condition): Ditto.
- (mask): Ditto.
-
-2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (ix86_check_avx10_vector_width): New function to check isa_flags
- to emit a warning when there is a conflict in AVX10 options for
- vector width.
- (ix86_handle_option): Add check for avx10.1-256 and avx10.1-512.
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Do not append -mno-avx10-max-512bit for -march=native.
-
-2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (ix86_check_avx10): New function to check isa_flags and
- isa_flags_explicit to emit warning when AVX10 is enabled
- by "-m" option.
- (ix86_check_avx512): New function to check isa_flags and
- isa_flags_explicit to emit warning when AVX512 is enabled
- by "-m" option.
- (ix86_handle_option): Do not change the flags when warning
- is emitted.
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Do not append -mno-avx10.1 for -march=native.
-
-2023-08-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Add avx10_set and version and detect avx10.1.
- (cpu_indicator_init): Handle avx10.1-512.
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA2_AVX10_512BIT_SET): New.
- (OPTION_MASK_ISA2_AVX10_1_SET): Ditto.
- (OPTION_MASK_ISA2_AVX10_512BIT_UNSET): Ditto.
- (OPTION_MASK_ISA2_AVX10_1_UNSET): Ditto.
- (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10_1.
- (ix86_handle_option): Handle -mavx10.1, -mavx10.1-256 and
- -mavx10.1-512.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_AVX10_512BIT, FEATURE_AVX10_1 and
- FEATURE_AVX10_512BIT.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- AVX10_512BIT, AVX10_1 and AVX10_1_512.
- * config/i386/constraints.md (Yk): Add AVX10_1.
- (Yv): Ditto.
- (k): Ditto.
- * config/i386/cpuid.h (bit_AVX10): New.
- (bit_AVX10_256): Ditto.
- (bit_AVX10_512): Ditto.
- * config/i386/i386-c.cc (ix86_target_macros_internal):
- Define AVX10_512BIT and AVX10_1.
- * config/i386/i386-isa.def
- (AVX10_512BIT): Add DEF_PTA(AVX10_512BIT).
- (AVX10_1): Add DEF_PTA(AVX10_1).
- * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1.
- (ix86_valid_target_attribute_inner_p): Handle avx10-512bit, avx10.1
- and avx10.1-512.
- (ix86_option_override_internal): Enable AVX512{F,VL,BW,DQ,CD,BF16,
- FP16,VBMI,VBMI2,VNNI,IFMA,BITALG,VPOPCNTDQ} features for avx10.1-512.
- (ix86_valid_target_attribute_inner_p): Handle AVX10_1.
- * config/i386/i386.cc (ix86_get_ssemov): Add AVX10_1.
- (ix86_conditional_register_usage): Ditto.
- (ix86_hard_regno_mode_ok): Ditto.
- (ix86_rtx_costs): Ditto.
- * config/i386/i386.h (VALID_MASK_AVX10_MODE): New macro.
- * config/i386/i386.opt: Add option -mavx10.1, -mavx10.1-256 and
- -mavx10.1-512.
- * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
- * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
- * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
- and avx10.1-512.
-
-2023-08-17 Sergei Trofimovich <siarheit@google.com>
-
- * flag-types.h (vrp_mode): Remove unused.
-
-2023-08-17 Yanzhang Wang <yanzhang.wang@intel.com>
-
- * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): Use
- CONSTM1_RTX.
-
-2023-08-17 Andrew Pinski <apinski@marvell.com>
-
- * internal-fn.def (COND_NOT): New internal function.
- * match.pd (UNCOND_UNARY, COND_UNARY): Add bit_not/not
- to the lists.
- (`vec (a ? -1 : 0) ^ b`): New pattern to convert
- into conditional not.
- * optabs.def (cond_one_cmpl): New optab.
- (cond_len_one_cmpl): Likewise.
-
-2023-08-16 Surya Kumari Jangala <jskumari@linux.ibm.com>
-
- PR rtl-optimization/110254
- * ira-color.cc (improve_allocation): Update array
- allocated_hard_reg_p.
-
-2023-08-16 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-int.h (lra_update_fp2sp_elimination): Change the prototype.
- * lra-eliminations.cc (spill_pseudos): Record spilled pseudos.
- (lra_update_fp2sp_elimination): Ditto.
- (update_reg_eliminate): Adjust spill_pseudos call.
- * lra-spills.cc (lra_spill): Assign stack slots to pseudos spilled
- in lra_update_fp2sp_elimination.
-
-2023-08-16 Richard Ball <richard.ball@arm.com>
-
- * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A720 CPU.
- * config/aarch64/aarch64-tune.md: Regenerate.
- * doc/invoke.texi: Document Cortex-A720 CPU.
-
-2023-08-16 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor):
- Implement expander.
- (<u>avg<v_double_trunc>3_ceil): Ditto.
- * config/riscv/vector-iterators.md (ashiftrt): New iterator.
- (ASHIFTRT): Ditto.
-
-2023-08-16 Robin Dapp <rdapp@ventanamicro.com>
-
- * internal-fn.cc (vec_extract_direct): Change type argument
- numbers.
- (expand_vec_extract_optab_fn): Call convert_optab_fn.
- (direct_vec_extract_optab_supported_p): Use
- convert_optab_supported_p.
-
-2023-08-16 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
- Richard Sandiford <richard.sandiford@arm.com>
-
- * fold-const.cc (INCLUDE_ALGORITHM): Add Include.
- (valid_mask_for_fold_vec_perm_cst_p): New function.
- (fold_vec_perm_cst): Likewise.
- (fold_vec_perm): Adjust assert and call fold_vec_perm_cst.
- (test_fold_vec_perm_cst): New namespace.
- (test_fold_vec_perm_cst::build_vec_cst_rand): New function.
- (test_fold_vec_perm_cst::validate_res): Likewise.
- (test_fold_vec_perm_cst::validate_res_vls): Likewise.
- (test_fold_vec_perm_cst::builder_push_elems): Likewise.
- (test_fold_vec_perm_cst::test_vnx4si_v4si): Likewise.
- (test_fold_vec_perm_cst::test_v4si_vnx4si): Likewise.
- (test_fold_vec_perm_cst::test_all_nunits): Likewise.
- (test_fold_vec_perm_cst::test_nunits_min_2): Likewise.
- (test_fold_vec_perm_cst::test_nunits_min_4): Likewise.
- (test_fold_vec_perm_cst::test_nunits_min_8): Likewise.
- (test_fold_vec_perm_cst::test_nunits_max_4): Likewise.
- (test_fold_vec_perm_cst::is_simple_vla_size): Likewise.
- (test_fold_vec_perm_cst::test): Likewise.
- (fold_const_cc_tests): Call test_fold_vec_perm_cst::test.
-
-2023-08-16 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (BASE): New declaration.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwcvt_xu_frm): New intrinsic function def.
-
-2023-08-16 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Use explicit argument.
-
-2023-08-16 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (BASE): New declaration.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwcvt_x_frm): New intrinsic function def.
-
-2023-08-16 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc (BASE): New declaration.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfcvt_f_frm): New intrinsic function def.
-
-2023-08-16 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (BASE): New declaration.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfcvt_xu_frm): New intrinsic function def..
-
-2023-08-16 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/110429
- * config/rs6000/vsx.md (*vsx_extract_<mode>_store_p9): Skip vector
- extract when the element is 7 on BE while 8 on LE for byte or 3 on
- BE while 4 on LE for halfword.
-
-2023-08-16 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/106769
- * config/rs6000/vsx.md (expand vsx_extract_<mode>): Set it only
- for V8HI and V16QI.
- (vsx_extract_v4si): New expand for V4SI extraction.
- (vsx_extract_v4si_w1): New insn pattern for V4SI extraction on
- word 1 from BE order.
- (*mfvsrwz): New insn pattern for mfvsrwz.
- (*vsx_extract_<mode>_di_p9): Assert that it won't be generated on
- word 1 from BE order.
- (*vsx_extract_si): Remove.
- (*vsx_extract_v4si_w023): New insn and split pattern on word 0, 2,
- 3 from BE order.
-
-2023-08-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (vec_mask_len_load_lanes<mode><vsingle>):
- New pattern.
- (vec_mask_len_store_lanes<mode><vsingle>): Ditto.
- * config/riscv/riscv-protos.h (expand_lanes_load_store): New function.
- * config/riscv/riscv-v.cc (get_mask_mode): Add tuple mask mode.
- (expand_lanes_load_store): New function.
- * config/riscv/vector-iterators.md: New iterator.
-
-2023-08-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * internal-fn.cc (internal_load_fn_p): Apply
- MASK_LEN_{LOAD_LANES,STORE_LANES} into vectorizer.
- (internal_store_fn_p): Ditto.
- (internal_fn_len_index): Ditto.
- (internal_fn_mask_index): Ditto.
- (internal_fn_stored_value_index): Ditto.
- * tree-vect-data-refs.cc (vect_store_lanes_supported): Ditto.
- (vect_load_lanes_supported): Ditto.
- * tree-vect-loop.cc: Ditto.
- * tree-vect-slp.cc (vect_slp_prefer_store_lanes_p): Ditto.
- * tree-vect-stmts.cc (check_load_store_for_partial_vectors): Ditto.
- (get_group_load_store_type): Ditto.
- (vectorizable_store): Ditto.
- (vectorizable_load): Ditto.
- * tree-vectorizer.h (vect_store_lanes_supported): Ditto.
- (vect_load_lanes_supported): Ditto.
-
-2023-08-16 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (enum frm_op_type): New type for frm.
- (BASE): New declaration.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfcvt_x_frm): New intrinsic function def.
-
-2023-08-16 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386-builtins.cc
- (ix86_vectorize_builtin_gather): Adjust for use_gather_8parts.
- * config/i386/i386-options.cc (parse_mtune_ctrl_str):
- Set/Clear tune features use_{gather,scatter}_{2parts, 4parts,
- 8parts} for -mtune-crtl={,^}{use_gather,use_scatter}.
- * config/i386/i386.cc (ix86_vectorize_builtin_scatter): Adjust
- for use_scatter_8parts
- * config/i386/i386.h (TARGET_USE_GATHER): Rename to ..
- (TARGET_USE_GATHER_8PARTS): .. this.
- (TARGET_USE_SCATTER): Rename to ..
- (TARGET_USE_SCATTER_8PARTS): .. this.
- * config/i386/x86-tune.def (X86_TUNE_USE_GATHER): Rename to
- (X86_TUNE_USE_GATHER_8PARTS): .. this.
- (X86_TUNE_USE_SCATTER): Rename to
- (X86_TUNE_USE_SCATTER_8PARTS): .. this.
- * config/i386/i386.opt: Add new options mgather, mscatter.
-
-2023-08-16 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386-options.cc (m_GDS): New macro.
- * config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Don't
- enable for m_GDS.
- (X86_TUNE_USE_GATHER_4PARTS): Ditto.
- (X86_TUNE_USE_GATHER): Ditto.
-
-2023-08-16 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386.md (movdf_internal): Generate vmovapd instead of
- vmovsd when moving DFmode between SSE_REGS.
- (movhi_internal): Generate vmovdqa instead of vmovsh when
- moving HImode between SSE_REGS.
- (mov<mode>_internal): Use vmovaps instead of vmovsh when
- moving HF/BFmode between SSE_REGS.
-
-2023-08-15 David Faust <david.faust@oracle.com>
-
- * config/bpf/bpf.md (extendsisi2): Delete useless define_insn.
-
-2023-08-15 David Faust <david.faust@oracle.com>
-
- PR target/111029
- * config/bpf/bpf.cc (bpf_print_register): Print 'w' registers
- for any mode 32-bits or smaller, not just SImode.
-
-2023-08-15 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/68930
- PR ipa/92497
- * ipa-prop.h (ipcp_get_aggregate_const): Declare.
- * ipa-prop.cc (ipcp_get_aggregate_const): New function.
- (ipcp_transform_function): Do not deallocate transformation info.
- * tree-ssa-sccvn.cc: Include alloc-pool.h, symbol-summary.h and
- ipa-prop.h.
- (vn_reference_lookup_2): When hitting default-def vuse, query
- IPA-CP transformation info for any known constants.
-
-2023-08-15 Chung-Lin Tang <cltang@codesourcery.com>
- Thomas Schwinge <thomas@codesourcery.com>
-
- * gimplify.cc (oacc_region_type_name): New function.
- (oacc_default_clause): If no 'default' clause appears on this
- compute construct, see if one appears on a lexically containing
- 'data' construct.
- (gimplify_scan_omp_clauses): Upon OMP_CLAUSE_DEFAULT case, set
- ctx->oacc_default_clause_ctx to current context.
-
-2023-08-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110989
- * config/riscv/predicates.md: Fix predicate.
-
-2023-08-15 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_analyze_slp_instance): Remove
- slp_inst_kind_ctor handling.
- (vect_analyze_slp): Simplify.
- (vect_build_slp_instance): Dump when we analyze a CTOR.
- (vect_slp_check_for_constructors): Rename to ...
- (vect_slp_check_for_roots): ... this. Register a
- slp_root for CONSTRUCTORs instead of shoving them to
- the set of grouped stores.
- (vect_slp_analyze_bb_1): Adjust.
-
-2023-08-15 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (_slp_instance::remain_stmts): Change
- to ...
- (_slp_instance::remain_defs): ... this.
- (SLP_INSTANCE_REMAIN_STMTS): Rename to ...
- (SLP_INSTANCE_REMAIN_DEFS): ... this.
- (slp_root::remain): New.
- (slp_root::slp_root): Adjust.
- * tree-vect-slp.cc (vect_free_slp_instance): Adjust.
- (vect_build_slp_instance): Get extra remain parameter,
- adjust former handling of a cut off stmt.
- (vect_analyze_slp_instance): Adjust.
- (vect_analyze_slp): Likewise.
- (_bb_vec_info::~_bb_vec_info): Likewise.
- (vectorizable_bb_reduc_epilogue): Dump something if we fail.
- (vect_slp_check_for_constructors): Handle non-internal
- defs as remain defs of a reduction.
- (vectorize_slp_instance_root_stmt): Adjust.
-
-2023-08-15 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-loop-ivcanon.cc: Include tree-vectorizer.h
- (canonicalize_loop_induction_variables): Use find_loop_location.
-
-2023-08-15 Hans-Peter Nilsson <hp@axis.com>
-
- PR bootstrap/111021
- * config/cris/cris-protos.h: Revert recent change.
- * config/cris/cris.cc (cris_legitimate_address_p): Remove
- code_helper unused parameter.
- (cris_legitimate_address_p_hook): New wrapper function.
- (TARGET_LEGITIMATE_ADDRESS_P): Change to
- cris_legitimate_address_p_hook.
-
-2023-08-15 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110963
- * tree-ssa-pre.cc (do_pre_regular_insertion): Also insert
- a PHI node when the expression is available on all edges
- and we insert at most one copy from a constant.
-
-2023-08-15 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110991
- * tree-ssa-loop-ivcanon.cc (constant_after_peeling): Handle
- VIEW_CONVERT_EXPR <op>, handle more simple IV-like SSA cycles
- that will end up constant.
-
-2023-08-15 Kewen Lin <linkw@linux.ibm.com>
-
- PR bootstrap/111021
- * Makefile.in (RECOG_H): Add $(TREE_H) as dependence.
-
-2023-08-15 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_load): Move the handlings on
- VMAT_LOAD_STORE_LANES in the final loop nest to its own loop,
- and update the final nest accordingly.
-
-2023-08-15 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_load): Remove some useless checks
- on VMAT_INVARIANT.
-
-2023-08-15 Pan Li <pan2.li@intel.com>
-
- * mode-switching.cc (create_pre_exit): Add SET insn check.
-
-2023-08-15 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfrec7_frm): New class for frm.
- (vfrec7_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfrec7_frm): New intrinsic function definition.
- * config/riscv/vector-iterators.md
- (VFMISC): Remove VFREC7.
- (misc_op): Ditto.
- (float_insn_type): Ditto.
- (VFMISC_FRM): New int iterator.
- (misc_frm_op): New op for frm.
- (float_frm_insn_type): New type for frm.
- * config/riscv/vector.md (@pred_<misc_frm_op><mode>):
- New pattern for misc frm.
-
-2023-08-14 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-constraints.cc (curr_insn_transform): Process output stack
- pointer reloads before emitting reload insns.
-
-2023-08-14 benjamin priour <vultkayn@gcc.gnu.org>
-
- PR analyzer/110543
- * doc/invoke.texi: Add documentation of
- fanalyzer-show-events-in-system-headers
-
-2023-08-14 Jan Hubicka <jh@suse.cz>
-
- PR gcov-profile/110988
- * tree-cfg.cc (fold_loop_internal_call): Avoid division by zero.
-
-2023-08-14 Jiawei <jiawei@iscas.ac.cn>
-
- * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
- Enable compressed builtins when ZC* extensions enabled.
- * config/riscv/riscv-shorten-memrefs.cc:
- Enable shorten_memrefs pass when ZC* extensions enabled.
- * config/riscv/riscv.cc (riscv_compressed_reg_p):
- Enable compressible registers when ZC* extensions enabled.
- (riscv_rtx_costs): Allow adjusting rtx costs when ZC* extensions enabled.
- (riscv_address_cost): Allow adjusting address cost when ZC* extensions enabled.
- (riscv_first_stack_step): Allow compression of the register saves
- without adding extra instructions.
- * config/riscv/riscv.h (FUNCTION_BOUNDARY): Adjusts function boundary
- to 16 bits when ZC* extensions enabled.
-
-2023-08-14 Jiawei <jiawei@iscas.ac.cn>
-
- * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New extensions.
- * config/riscv/riscv-opts.h (MASK_ZCA): New mask.
- (MASK_ZCB): Ditto.
- (MASK_ZCE): Ditto.
- (MASK_ZCF): Ditto.
- (MASK_ZCD): Ditto.
- (MASK_ZCMP): Ditto.
- (MASK_ZCMT): Ditto.
- (TARGET_ZCA): New target.
- (TARGET_ZCB): Ditto.
- (TARGET_ZCE): Ditto.
- (TARGET_ZCF): Ditto.
- (TARGET_ZCD): Ditto.
- (TARGET_ZCMP): Ditto.
- (TARGET_ZCMT): Ditto.
- * config/riscv/riscv.opt: New target variable.
-
-2023-08-14 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- Revert:
- 2023-05-17 Jin Ma <jinma@linux.alibaba.com>
-
- * genrecog.cc (print_nonbool_test): Fix type error of
- switch (SUBREG_BYTE (op))'.
-
-2023-08-14 Richard Biener <rguenther@suse.de>
-
- * tree-cfg.cc (print_loop_info): Dump to 'file', not 'dump_file'.
-
-2023-08-14 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class unop_frm): New class for frm.
- (vfsqrt_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfsqrt_frm): New intrinsic function definition.
-
-2023-08-14 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfwnmsac_frm): New class for frm.
- (vfwnmsac_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwnmsac_frm): New intrinsic function definition.
-
-2023-08-14 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfwmsac_frm): New class for frm.
- (vfwmsac_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwmsac_frm): New intrinsic function definition.
-
-2023-08-14 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfwnmacc_frm): New class for frm.
- (vfwnmacc_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwnmacc_frm): New intrinsic function definition.
-
-2023-08-14 Cui, Lili <lili.cui@intel.com>
-
- * common/config/i386/cpuinfo.h (get_intel_cpu): Add model value 0xba
- to Raptorlake.
-
-2023-08-14 Hans-Peter Nilsson <hp@axis.com>
-
- * config/mmix/predicates.md (mmix_address_operand): Use
- lra_in_progress, not reload_in_progress.
-
-2023-08-14 Hans-Peter Nilsson <hp@axis.com>
-
- * config/mmix/mmix.cc: Re-enable LRA.
-
-2023-08-14 Hans-Peter Nilsson <hp@axis.com>
-
- * config/mmix/predicates.md (frame_pointer_operand): Handle FP+offset
- when lra_in_progress.
-
-2023-08-14 Hans-Peter Nilsson <hp@axis.com>
-
- * config/mmix/mmix.cc: Disable LRA for MMIX.
-
-2023-08-14 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfwmacc_frm): New class for vfwmacc frm.
- (vfwmacc_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwmacc_frm): Function definition for vfwmacc.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_widen_ternop_insn): Add frm support.
-
-2023-08-14 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfnmsub_frm): New class for vfnmsub frm.
- (vfnmsub_frm): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfnmsub_frm): New function declaration.
-
-2023-08-14 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-constraints.cc (curr_insn_transform): Set done_p up and
- check it on true after processing output stack pointer reload.
-
-2023-08-12 Jakub Jelinek <jakub@redhat.com>
-
- * Makefile.in (USER_H): Add stdckdint.h.
- * ginclude/stdckdint.h: New file.
-
-2023-08-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110994
- * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR.
-
-2023-08-12 Patrick Palka <ppalka@redhat.com>
-
- * tree-pretty-print.cc (dump_generic_node) <case TREE_VEC>:
- Delimit output with braces.
-
-2023-08-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110985
- * config/riscv/riscv-v.cc (expand_vec_series): Refactor the expander.
-
-2023-08-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Add VLS CONST_VECTOR.
- * config/riscv/riscv.cc (riscv_const_insns): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-08-11 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/105899
- * doc/analyzer.texi (__analyzer_get_strlen): New.
- * doc/invoke.texi: Add -Wanalyzer-unterminated-string.
-
-2023-08-11 Jeff Law <jlaw@ventanamicro.com>
-
- * config/rx/rx.md (subdi3): Fix test for borrow.
-
-2023-08-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR middle-end/110989
- * tree-vect-stmts.cc (vectorizable_store): Replace iv_type with sizetype.
- (vectorizable_load): Ditto.
-
-2023-08-11 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.md (allocate_stack): Define.
- * config/bpf/bpf.h (FIRST_PSEUDO_REGISTER): Make room for fake
- stack pointer register.
- (FIXED_REGISTERS): Adjust accordingly.
- (CALL_USED_REGISTERS): Likewise.
- (REG_CLASS_CONTENTS): Likewise.
- (REGISTER_NAMES): Likewise.
- * config/bpf/bpf.cc (bpf_compute_frame_layout): Do not reserve
- space for callee-saved registers.
- (bpf_expand_prologue): Do not save callee-saved registers in xbpf.
- (bpf_expand_epilogue): Do not restore callee-saved registers in
- xbpf.
-
-2023-08-11 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.cc (bpf_function_arg_advance): Do not complain
- about too many arguments if function is always inlined.
-
-2023-08-11 Patrick Palka <ppalka@redhat.com>
-
- * tree-pretty-print.cc (dump_generic_node) <case COMPONENT_REF>:
- Don't call component_ref_field_offset if the RHS isn't a decl.
-
-2023-08-11 John David Anglin <danglin@gcc.gnu.org>
-
- PR bootstrap/110646
- * gensupport.cc(class conlist): Use strtol instead of std::stoi.
-
-2023-08-11 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-constraints.cc (goal_alt_out_sp_reload_p): New flag.
- (process_alt_operands): Set the flag.
- (curr_insn_transform): Modify stack pointer offsets if output
- stack pointer reload is generated.
-
-2023-08-11 Joseph Myers <joseph@codesourcery.com>
-
- * configure: Regenerate.
-
-2023-08-11 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110979
- * tree-vect-loop.cc (vectorizable_reduction): For
- FOLD_LEFT_REDUCTION without target support make sure
- we don't need to honor signed zeros and sign dependent rounding.
-
-2023-08-11 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_slp_region): Provide opt-info for all SLP
- subgraph entries. Dump the used vector size based on the
- SLP subgraph entry root vector type.
-
-2023-08-11 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfmsub_frm): New class for vfmsub frm.
- (vfmsub_frm): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmsub_frm): New function declaration.
-
-2023-08-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * doc/md.texi: Add vec_mask_len_{load_lanes,store_lanes} patterns.
- * internal-fn.cc (expand_partial_load_optab_fn): Ditto.
- (expand_partial_store_optab_fn): Ditto.
- * internal-fn.def (MASK_LEN_LOAD_LANES): Ditto.
- (MASK_LEN_STORE_LANES): Ditto.
- * optabs.def (OPTAB_CD): Ditto.
-
-2023-08-11 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfnmadd_frm): New class for vfnmadd frm.
- (vfnmadd_frm): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfnmadd_frm): New function declaration.
-
-2023-08-11 Drew Ross <drross@redhat.com>
- Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109938
- * match.pd (((x ^ y) & z) | x -> (z & y) | x): New simplification.
-
-2023-08-11 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfmadd_frm): New class for vfmadd frm.
- (vfmadd_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmadd_frm): New function definition.
-
-2023-08-11 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfnmsac_frm): New class for vfnmsac frm.
- (vfnmsac_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfnmsac_frm): New function definition.
-
-2023-08-11 Jakub Jelinek <jakub@redhat.com>
-
- * doc/extend.texi (Typeof): Document typeof_unqual
- and __typeof_unqual__.
-
-2023-08-11 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110954
- * generic-match-head.cc (bitwise_inverted_equal_p): Add
- wascmp argument and set it accordingly.
- * gimple-match-head.cc (bitwise_inverted_equal_p): Add
- wascmp argument to the macro.
- (gimple_bitwise_inverted_equal_p): Add
- wascmp argument and set it accordingly.
- * match.pd (`a & ~a`, `a ^| ~a`): Update call
- to bitwise_inverted_equal_p and handle wascmp case.
- (`(~x | y) & x`, `(~x | y) & x`, `a?~t:t`): Update
- call to bitwise_inverted_equal_p and check to see
- if was !wascmp or if precision was 1.
-
-2023-08-11 Martin Uecker <uecker@tugraz.at>
-
- PR c/84510
- * doc/invoke.texi: Update.
-
-2023-08-11 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfmsac_frm): New class for vfmsac frm.
- (vfmsac_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmsac_frm): New function definition
-
-2023-08-10 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/110923
- * tree-ssa-loop-split.cc (split_loop): Watch for division by zero.
-
-2023-08-10 Patrick O'Neill <patrick@rivosinc.com>
-
- * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
- dependent on 'a' extension.
- * config/riscv/riscv-opts.h (MASK_ZTSO): New mask.
- (TARGET_ZTSO): New target.
- * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add
- Ztso case.
- (riscv_memmodel_needs_amo_release): Add Ztso case.
- (riscv_print_operand): Add Ztso case for LR/SC annotations.
- * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md.
- * config/riscv/riscv.opt: Add Ztso target variable.
- * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or
- Ztso specific insn.
- (atomic_load<mode>): Expand to RVWMO or Ztso specific insn.
- (atomic_store<mode>): Expand to RVWMO or Ztso specific insn.
- * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO
- specific load/store/fence mappings.
- * config/riscv/sync-ztso.md: New file. Seperate out Ztso
- specific load/store/fence mappings.
-
-2023-08-10 Jan Hubicka <jh@suse.cz>
-
- * cfgloopmanip.cc (duplicate_loop_body_to_header_edge): Special case loops with
- 0 iteration count.
-
-2023-08-10 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-threadupdate.cc (ssa_fix_duplicate_block_edges): Fix profile update.
-
-2023-08-10 Jan Hubicka <jh@suse.cz>
-
- * profile-count.cc (profile_count::differs_from_p): Fix overflow and
- handling of undefined values.
-
-2023-08-10 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * tree-ssa-phiopt.cc (single_non_singleton_phi_for_edges): Never
- return virtual phis and return NULL if there is a virtual phi
- where the arguments from E0 and E1 edges aren't equal.
-
-2023-08-10 Richard Biener <rguenther@suse.de>
-
- * internal-fn.def (VCOND, VCONDU, VCONDEQ, VCOND_MASK,
- VEC_SET, VEC_EXTRACT): Make ECF_CONST | ECF_NOTHROW.
-
-2023-08-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110962
- * config/riscv/autovec.md (vec_duplicate<mode>): New pattern.
-
-2023-08-10 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfnmacc_frm): New class for vfnmacc.
- (vfnmacc_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfnmacc_frm): New function definition.
-
-2023-08-10 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfmacc_frm): New class for vfmacc frm.
- (vfmacc_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmacc_frm): New function definition.
-
-2023-08-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110964
- * config/riscv/riscv-v.cc (expand_cond_len_ternop): Add integer ternary.
-
-2023-08-10 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (vectorizable_live_operation): Remove
- gimple_stmt_iterator * argument.
- * tree-vect-loop.cc (vectorizable_live_operation): Likewise.
- Adjust plumbing around vect_get_loop_mask.
- (vect_analyze_loop_operations): Adjust.
- * tree-vect-slp.cc (vect_slp_analyze_node_operations_1): Likewise.
- (vect_bb_slp_mark_live_stmts): Likewise.
- (vect_schedule_slp_node): Likewise.
- * tree-vect-stmts.cc (can_vectorize_live_stmts): Likewise.
- Remove gimple_stmt_iterator * argument.
- (vect_transform_stmt): Adjust.
-
-2023-08-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Add missing modes.
-
-2023-08-10 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * lto-streamer-in.cc (lto_input_tree_1): Assert TYPE_PRECISION
- is up to WIDE_INT_MAX_PRECISION rather than MAX_BITSIZE_MODE_ANY_INT.
-
-2023-08-10 Jakub Jelinek <jakub@redhat.com>
-
- PR c/102989
- * expr.cc (expand_expr_real_1) <case MEM_REF>: Add an early return for
- EXPAND_WRITE or EXPAND_MEMORY modifiers to avoid testing it multiple
- times.
-
-2023-08-10 liuhongt <hongtao.liu@intel.com>
-
- PR target/110832
- * config/i386/mmx.md: (movq_<mode>_to_sse): Also do not
- sanitize upper part of V4HFmode register with
- -fno-trapping-math.
- (<insn>v4hf3): Enable for ix86_partial_vec_fp_math.
- (<divv4hf3): Ditto.
- (<insn>v2hf3): Ditto.
- (divv2hf3): Ditto.
- (movd_v2hf_to_sse): Do not sanitize upper part of V2HFmode
- register with -fno-trapping-math.
-
-2023-08-10 Pan Li <pan2.li@intel.com>
- Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-protos.h
- (enum floating_point_rounding_mode): Add NONE, DYN_EXIT and DYN_CALL.
- (get_frm_mode): New declaration.
- * config/riscv/riscv-v.cc (get_frm_mode): New function to get frm mode.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_ternop_insn): Take care of frm reg.
- * config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to FRM_XXX.
- (riscv_emit_frm_mode_set): Ditto.
- (riscv_emit_mode_set): Ditto.
- (riscv_frm_adjust_mode_after_call): Ditto.
- (riscv_frm_mode_needed): Ditto.
- (riscv_frm_mode_after): Ditto.
- (riscv_mode_entry): Ditto.
- (riscv_mode_exit): Ditto.
- * config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
- * config/riscv/vector.md
- (rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed
- (symbol_ref): * config/riscv/vector.md: Set frm_mode attr explicitly.
-
-2023-08-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix
- incorrect anticipate info.
-
-2023-08-09 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc (riscv_ext_version_table):
- Remove 'Zve32d' from the version list.
-
-2023-08-09 Jin Ma <jinma@linux.alibaba.com>
-
- * config/riscv/riscv.cc (riscv_sched_variable_issue): New function.
- (TARGET_SCHED_VARIABLE_ISSUE): New macro.
- Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
- Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
-
-2023-08-09 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * config/riscv/riscv.cc (riscv_legitimize_address): Handle folding.
- (mem_shadd_or_shadd_rtx_p): New function.
-
-2023-08-09 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110937
- PR tree-optimization/100798
- * match.pd (`a ? ~b : b`): Handle this
- case.
-
-2023-08-09 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.opt (mpartial-vector-fp-math): Add dot.
-
-2023-08-09 Richard Ball <richard.ball@arm.com>
-
- * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A520 CPU.
- * config/aarch64/aarch64-tune.md: Regenerate.
- * doc/invoke.texi: Document Cortex-A520 CPU.
-
-2023-08-09 Carl Love <cel@us.ibm.com>
-
- * config/rs6000/rs6000-builtins.def (vcmpneb, vcmpneh, vcmpnew):
- Move definitions to Altivec stanza.
- * config/rs6000/altivec.md (vcmpneb, vcmpneh, vcmpnew): New
- define_expand.
-
-2023-08-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110950
- * config/riscv/riscv-v.cc (expand_const_vector): Add NPATTERNS = 1
- stepped vector support.
-
-2023-08-09 liuhongt <hongtao.liu@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Rename local variable subleaf_level to max_subleaf_level.
-
-2023-08-09 Richard Biener <rguenther@suse.de>
-
- PR rtl-optimization/110587
- * lra-assigns.cc (find_hard_regno_for_1): Re-order checks.
-
-2023-08-09 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/110248
- * config/rs6000/rs6000.cc (rs6000_legitimate_address_p): Check if
- the given code is for ifn LEN_{LOAD,STORE}, if yes then make it not
- legitimate when outer code is PLUS.
-
-2023-08-09 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/110248
- * recog.cc (memory_address_addr_space_p): Add one more argument ch of
- type code_helper and pass it to targetm.addr_space.legitimate_address_p
- instead of ERROR_MARK.
- (offsettable_address_addr_space_p): Update one function pointer with
- one more argument of type code_helper as its assignees
- memory_address_addr_space_p and strict_memory_address_addr_space_p
- have been adjusted, and adjust some call sites with ERROR_MARK.
- * recog.h (tree.h): New include header file for tree_code ERROR_MARK.
- (memory_address_addr_space_p): Adjust with one more unnamed argument
- of type code_helper with default ERROR_MARK.
- (strict_memory_address_addr_space_p): Likewise.
- * reload.cc (strict_memory_address_addr_space_p): Add one unnamed
- argument of type code_helper.
- * tree-ssa-address.cc (valid_mem_ref_p): Add one more argument ch of
- type code_helper and pass it to memory_address_addr_space_p.
- * tree-ssa-address.h (valid_mem_ref_p): Adjust the declaration with
- one more unnamed argument of type code_helper with default value
- ERROR_MARK.
- * tree-ssa-loop-ivopts.cc (get_address_cost): Use ERROR_MARK as code
- by default, change it with ifn code for USE_PTR_ADDRESS type use, and
- pass it to all valid_mem_ref_p calls.
-
-2023-08-09 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/110248
- * coretypes.h (class code_helper): Add forward declaration.
- * doc/tm.texi: Regenerate.
- * lra-constraints.cc (valid_address_p): Call target hook
- targetm.addr_space.legitimate_address_p with an extra parameter
- ERROR_MARK as its prototype changes.
- * recog.cc (memory_address_addr_space_p): Likewise.
- * reload.cc (strict_memory_address_addr_space_p): Likewise.
- * target.def (legitimate_address_p, addr_space.legitimate_address_p):
- Extend with one more argument of type code_helper, update the
- documentation accordingly.
- * targhooks.cc (default_legitimate_address_p): Adjust for the
- new code_helper argument.
- (default_addr_space_legitimate_address_p): Likewise.
- * targhooks.h (default_legitimate_address_p): Likewise.
- (default_addr_space_legitimate_address_p): Likewise.
- * config/aarch64/aarch64.cc (aarch64_legitimate_address_hook_p): Adjust
- with extra unnamed code_helper argument with default ERROR_MARK.
- * config/alpha/alpha.cc (alpha_legitimate_address_p): Likewise.
- * config/arc/arc.cc (arc_legitimate_address_p): Likewise.
- * config/arm/arm-protos.h (arm_legitimate_address_p): Likewise.
- (tree.h): New include for tree_code ERROR_MARK.
- * config/arm/arm.cc (arm_legitimate_address_p): Adjust with extra
- unnamed code_helper argument with default ERROR_MARK.
- * config/avr/avr.cc (avr_addr_space_legitimate_address_p): Likewise.
- * config/bfin/bfin.cc (bfin_legitimate_address_p): Likewise.
- * config/bpf/bpf.cc (bpf_legitimate_address_p): Likewise.
- * config/c6x/c6x.cc (c6x_legitimate_address_p): Likewise.
- * config/cris/cris-protos.h (cris_legitimate_address_p): Likewise.
- (tree.h): New include for tree_code ERROR_MARK.
- * config/cris/cris.cc (cris_legitimate_address_p): Adjust with extra
- unnamed code_helper argument with default ERROR_MARK.
- * config/csky/csky.cc (csky_legitimate_address_p): Likewise.
- * config/epiphany/epiphany.cc (epiphany_legitimate_address_p):
- Likewise.
- * config/frv/frv.cc (frv_legitimate_address_p): Likewise.
- * config/ft32/ft32.cc (ft32_addr_space_legitimate_address_p): Likewise.
- * config/gcn/gcn.cc (gcn_addr_space_legitimate_address_p): Likewise.
- * config/h8300/h8300.cc (h8300_legitimate_address_p): Likewise.
- * config/i386/i386.cc (ix86_legitimate_address_p): Likewise.
- * config/ia64/ia64.cc (ia64_legitimate_address_p): Likewise.
- * config/iq2000/iq2000.cc (iq2000_legitimate_address_p): Likewise.
- * config/lm32/lm32.cc (lm32_legitimate_address_p): Likewise.
- * config/loongarch/loongarch.cc (loongarch_legitimate_address_p):
- Likewise.
- * config/m32c/m32c.cc (m32c_legitimate_address_p): Likewise.
- (m32c_addr_space_legitimate_address_p): Likewise.
- * config/m32r/m32r.cc (m32r_legitimate_address_p): Likewise.
- * config/m68k/m68k.cc (m68k_legitimate_address_p): Likewise.
- * config/mcore/mcore.cc (mcore_legitimate_address_p): Likewise.
- * config/microblaze/microblaze-protos.h (tree.h): New include for
- tree_code ERROR_MARK.
- (microblaze_legitimate_address_p): Adjust with extra unnamed
- code_helper argument with default ERROR_MARK.
- * config/microblaze/microblaze.cc (microblaze_legitimate_address_p):
- Likewise.
- * config/mips/mips.cc (mips_legitimate_address_p): Likewise.
- * config/mmix/mmix.cc (mmix_legitimate_address_p): Likewise.
- * config/mn10300/mn10300.cc (mn10300_legitimate_address_p): Likewise.
- * config/moxie/moxie.cc (moxie_legitimate_address_p): Likewise.
- * config/msp430/msp430.cc (msp430_legitimate_address_p): Likewise.
- (msp430_addr_space_legitimate_address_p): Adjust with extra code_helper
- argument with default ERROR_MARK and adjust the call to function
- msp430_legitimate_address_p.
- * config/nds32/nds32.cc (nds32_legitimate_address_p): Adjust with extra
- unnamed code_helper argument with default ERROR_MARK.
- * config/nios2/nios2.cc (nios2_legitimate_address_p): Likewise.
- * config/nvptx/nvptx.cc (nvptx_legitimate_address_p): Likewise.
- * config/or1k/or1k.cc (or1k_legitimate_address_p): Likewise.
- * config/pa/pa.cc (pa_legitimate_address_p): Likewise.
- * config/pdp11/pdp11.cc (pdp11_legitimate_address_p): Likewise.
- * config/pru/pru.cc (pru_addr_space_legitimate_address_p): Likewise.
- * config/riscv/riscv.cc (riscv_legitimate_address_p): Likewise.
- * config/rl78/rl78-protos.h (rl78_as_legitimate_address): Likewise.
- (tree.h): New include for tree_code ERROR_MARK.
- * config/rl78/rl78.cc (rl78_as_legitimate_address): Adjust with
- extra unnamed code_helper argument with default ERROR_MARK.
- * config/rs6000/rs6000.cc (rs6000_legitimate_address_p): Likewise.
- (rs6000_debug_legitimate_address_p): Adjust with extra code_helper
- argument and adjust the call to function rs6000_legitimate_address_p.
- * config/rx/rx.cc (rx_is_legitimate_address): Adjust with extra
- unnamed code_helper argument with default ERROR_MARK.
- * config/s390/s390.cc (s390_legitimate_address_p): Likewise.
- * config/sh/sh.cc (sh_legitimate_address_p): Likewise.
- * config/sparc/sparc.cc (sparc_legitimate_address_p): Likewise.
- * config/v850/v850.cc (v850_legitimate_address_p): Likewise.
- * config/vax/vax.cc (vax_legitimate_address_p): Likewise.
- * config/visium/visium.cc (visium_legitimate_address_p): Likewise.
- * config/xtensa/xtensa.cc (xtensa_legitimate_address_p): Likewise.
- * config/stormy16/stormy16-protos.h (xstormy16_legitimate_address_p):
- Likewise.
- (tree.h): New include for tree_code ERROR_MARK.
- * config/stormy16/stormy16.cc (xstormy16_legitimate_address_p):
- Adjust with extra unnamed code_helper argument with default
- ERROR_MARK.
-
-2023-08-09 liuhongt <hongtao.liu@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features): Check
- EAX for valid subleaf before use CPUID.
-
-2023-08-08 Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Use word_mode
- for the temporary when canonicalizing the condition.
-
-2023-08-08 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/core-builtins.cc: Cleaned include headers.
- (struct cr_builtins): Added GTY.
- (cr_builtins_ref): Created.
- (builtins_data) Changed to GC root.
- (allocate_builtin_data): Changed.
- Included gt-core-builtins.h.
- * config/bpf/coreout.cc: (bpf_core_extra) Added GTY.
- (bpf_core_extra_ref): Created.
- (bpf_comment_info): Changed to GC root.
- (bpf_core_reloc_add, output_btfext_header, btf_ext_init): Changed.
-
-2023-08-08 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/110832
- * config/i386/i386.opt (mpartial-vector-fp-math): New option.
- * config/i386/mmx.md (movq_<mode>_to_sse): Do not sanitize
- upper part of V2SFmode register with -fno-trapping-math.
- (<plusminusmult:insn>v2sf3): Enable for ix86_partial_vec_fp_math.
- (divv2sf3): Ditto.
- (<smaxmin:code>v2sf3): Ditto.
- (sqrtv2sf2): Ditto.
- (*mmx_haddv2sf3_low): Ditto.
- (*mmx_hsubv2sf3_low): Ditto.
- (vec_addsubv2sf3): Ditto.
- (vec_cmpv2sfv2si): Ditto.
- (vcond<V2FI:mode>v2sf): Ditto.
- (fmav2sf4): Ditto.
- (fmsv2sf4): Ditto.
- (fnmav2sf4): Ditto.
- (fnmsv2sf4): Ditto.
- (fix_truncv2sfv2si2): Ditto.
- (fixuns_truncv2sfv2si2): Ditto.
- (floatv2siv2sf2): Ditto.
- (floatunsv2siv2sf2): Ditto.
- (nearbyintv2sf2): Ditto.
- (rintv2sf2): Ditto.
- (lrintv2sfv2si2): Ditto.
- (ceilv2sf2): Ditto.
- (lceilv2sfv2si2): Ditto.
- (floorv2sf2): Ditto.
- (lfloorv2sfv2si2): Ditto.
- (btruncv2sf2): Ditto.
- (roundv2sf2): Ditto.
- (lroundv2sfv2si2): Ditto.
- * doc/invoke.texi (x86 Options): Document
- -mpartial-vector-fp-math option.
-
-2023-08-08 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/103281
- PR tree-optimization/28794
- * vr-values.cc (simplify_using_ranges::simplify_cond_using_ranges_1): Split out
- majority to ...
- (simplify_using_ranges::simplify_compare_using_ranges_1): Here.
- (simplify_using_ranges::simplify_casted_cond): Rename to ...
- (simplify_using_ranges::simplify_casted_compare): This
- and change arguments to take op0 and op1.
- (simplify_using_ranges::simplify_compare_assign_using_ranges_1): New method.
- (simplify_using_ranges::simplify): For tcc_comparison assignments call
- simplify_compare_assign_using_ranges_1.
- * vr-values.h (simplify_using_ranges): Add
- new methods, simplify_compare_using_ranges_1 and simplify_compare_assign_using_ranges_1.
- Rename simplify_casted_cond and simplify_casted_compare and
- update argument types.
-
-2023-08-08 Andrzej Turko <andrzej.turko@gmail.com>
-
- * genmatch.cc: Log line numbers indirectly.
-
-2023-08-08 Andrzej Turko <andrzej.turko@gmail.com>
-
- * genmatch.cc: Make sinfo map ordered.
- * Makefile.in: Require the ordered map header for genmatch.o.
-
-2023-08-08 Andrzej Turko <andrzej.turko@gmail.com>
-
- * ordered-hash-map.h: Add get_or_insert.
- * ordered-hash-map-tests.cc: Use get_or_insert in tests.
-
-2023-08-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (cond_<optab><mode>): New pattern.
- (cond_len_<optab><mode>): Ditto.
- (cond_fma<mode>): Ditto.
- (cond_len_fma<mode>): Ditto.
- (cond_fnma<mode>): Ditto.
- (cond_len_fnma<mode>): Ditto.
- (cond_fms<mode>): Ditto.
- (cond_len_fms<mode>): Ditto.
- (cond_fnms<mode>): Ditto.
- (cond_len_fnms<mode>): Ditto.
- * config/riscv/riscv-protos.h (riscv_get_v_regno_alignment): Export
- global.
- (enum insn_type): Add new enum type.
- (prepare_ternary_operands): New function.
- * config/riscv/riscv-v.cc (emit_vlmax_masked_fp_mu_insn): Ditto.
- (emit_nonvlmax_tumu_insn): Ditto.
- (emit_nonvlmax_fp_tumu_insn): Ditto.
- (expand_cond_len_binop): Add condtional operations.
- (expand_cond_len_ternop): Ditto.
- (prepare_ternary_operands): New function.
- * config/riscv/riscv.cc (riscv_memmodel_needs_amo_release): Export
- riscv_get_v_regno_alignment as global scope.
- * config/riscv/vector.md: Fix ternary bugs.
-
-2023-08-08 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/49955
- * tree-vectorizer.h (_slp_instance::remain_stmts): New.
- (SLP_INSTANCE_REMAIN_STMTS): Likewise.
- * tree-vect-slp.cc (vect_free_slp_instance): Release
- SLP_INSTANCE_REMAIN_STMTS.
- (vect_build_slp_instance): Make the number of lanes of
- a BB reduction even.
- (vectorize_slp_instance_root_stmt): Handle unvectorized
- defs of a BB reduction.
-
-2023-08-08 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * internal-fn.cc (get_len_internal_fn): New function.
- (DEF_INTERNAL_COND_FN): Ditto.
- (DEF_INTERNAL_SIGNED_COND_FN): Ditto.
- * internal-fn.h (get_len_internal_fn): Ditto.
- * tree-vect-stmts.cc (vectorizable_call): Add CALL auto-vectorization.
-
-2023-08-08 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110924
- * tree-ssa-live.h (virtual_operand_live): Update comment.
- * tree-ssa-live.cc (virtual_operand_live::get_live_in): Remove
- optimization, look at each predecessor.
- * tree-ssa-sink.cc (pass_sink_code::execute): Mark backedges.
-
-2023-08-08 yulong <shiyulong@iscas.ac.cn>
-
- * config/riscv/riscv-v.cc (slide1_sew64_helper): Modify.
-
-2023-08-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-vls.md (<optab><mode>2): Add VLS neg.
- * config/riscv/vector.md: Ditto.
-
-2023-08-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Add VLS shift.
-
-2023-08-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-vls.md (<optab><mode>3): Add VLS modes.
- * config/riscv/vector-iterators.md: Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-08-07 Jonathan Wakely <jwakely@redhat.com>
-
- * config/i386/i386.cc (ix86_invalid_conversion): Fix grammar.
-
-2023-08-07 Nick Alcock <nick.alcock@oracle.com>
-
- * configure: Regenerate.
-
-2023-08-07 John Ericson <git@JohnEricson.me>
-
- * configure: Regenerate.
-
-2023-08-07 Alan Modra <amodra@gmail.com>
-
- * configure: Regenerate.
-
-2023-08-07 Alexander von Gluck IV <kallisti5@unixzen.com>
-
- * configure: Regenerate.
-
-2023-08-07 Nick Alcock <nick.alcock@oracle.com>
-
- * configure: Regenerate.
-
-2023-08-07 Nick Alcock <nick.alcock@oracle.com>
-
- * configure: Regenerate.
-
-2023-08-07 H.J. Lu <hjl.tools@gmail.com>
-
- * configure: Regenerate.
-
-2023-08-07 H.J. Lu <hjl.tools@gmail.com>
-
- * configure: Regenerate.
-
-2023-08-07 Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Allow
- VOIDmode operands to conditional before canonicalization.
-
-2023-08-07 Manolis Tsamis <manolis.tsamis@vrull.eu>
-
- * regcprop.cc (maybe_copy_reg_attrs): Remove unnecessary function.
- (find_oldest_value_reg): Inline stack_pointer_rtx check.
- (copyprop_hardreg_forward_1): Inline stack_pointer_rtx check.
-
-2023-08-07 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/110378
- * ipa-param-manipulation.h (class ipa_param_body_adjustments): New
- members get_ddef_if_exists_and_is_used and mark_clobbers_dead.
- * ipa-sra.cc (isra_track_scalar_value_uses): Ignore clobbers.
- (ptr_parm_has_nonarg_uses): Likewise.
- * ipa-param-manipulation.cc
- (ipa_param_body_adjustments::get_ddef_if_exists_and_is_used): New.
- (ipa_param_body_adjustments::mark_dead_statements): Move initial
- checks to get_ddef_if_exists_and_is_used.
- (ipa_param_body_adjustments::mark_clobbers_dead): New.
- (ipa_param_body_adjustments::common_initialization): Call
- mark_clobbers_dead when splitting.
-
-2023-08-07 Raphael Zinsly <rzinsly@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_expand_int_scc): Add invert_ptr
- as an argument and pass it to riscv_emit_int_order_test.
- (riscv_expand_conditional_move): Handle cases where the condition
- is not EQ/NE or the second argument to the conditional is not
- (const_int 0).
- * config/riscv/riscv-protos.h (riscv_expand_int_scc): Update prototype.
- Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
-
-2023-08-07 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109959
- * match.pd (`(a > 1) ? 0 : (cast)a`, `(a <= 1) & (cast)a`):
- New patterns.
-
-2023-08-07 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-sink.cc (pass_sink_code::execute): Do not
- calculate post-dominators. Calculate RPO on the inverted
- graph and process blocks in that order.
-
-2023-08-07 liuhongt <hongtao.liu@intel.com>
-
- PR target/110926
- * config/i386/i386-protos.h
- (vpternlog_redundant_operand_mask): Adjust parameter type.
- * config/i386/i386.cc (vpternlog_redundant_operand_mask): Use
- INTVAL instead of XINT, also adjust parameter type from rtx*
- to rtx since the function only needs operands[4] in vpternlog
- pattern.
- (substitute_vpternlog_operands): Pass operands[4] instead of
- operands to vpternlog_redundant_operand_mask.
- * config/i386/sse.md: Ditto.
-
-2023-08-07 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_slp_region): Save/restore vect_location
- around dumping code.
-
-2023-08-07 liuhongt <hongtao.liu@intel.com>
-
- PR target/110762
- * config/i386/mmx.md (<insn><mode>3): Changed from define_insn
- to define_expand and break into ..
- (<insn>v4hf3): .. this.
- (divv4hf3): .. this.
- (<insn>v2hf3): .. this.
- (divv2hf3): .. this.
- (movd_v2hf_to_sse): New define_expand.
- (movq_<mode>_to_sse): Extend to V4HFmode.
- (mmxdoublevecmode): Ditto.
- (V2FI_V4HF): New mode iterator.
- * config/i386/sse.md (*vec_concatv4sf): Extend to hanlde V8HF
- by using mode iterator V4SF_V8HF, renamed to ..
- (*vec_concat<mode>): .. this.
- (*vec_concatv4sf_0): Extend to handle V8HF by using mode
- iterator V4SF_V8HF, renamed to ..
- (*vec_concat<mode>_0): .. this.
- (*vec_concatv8hf_movss): New define_insn.
- (V4SF_V8HF): New mode iterator.
-
-2023-08-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Add op vectype.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/mmx.md (*mmx_pinsrd): Drop "prefix_data16".
- (*mmx_pinsrb): Likewise.
- (*mmx_pextrb): Likewise.
- (*mmx_pextrb_zext): Likewise.
- (mmx_pshufbv8qi3): Likewise.
- (mmx_pshufbv4qi3): Likewise.
- (mmx_pswapdv2si2): Likewise.
- (*pinsrb): Likewise.
- (*pextrb): Likewise.
- (*pextrb_zext): Likewise.
- * config/i386/sse.md (*sse4_1_mulv2siv2di3<mask_name>): Likewise.
- (*sse2_eq<mode>3): Likewise.
- (*sse2_gt<mode>3): Likewise.
- (<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
- (*vec_extract<mode>): Likewise.
- (*vec_extract<PEXTR_MODE12:mode>_zext): Likewise.
- (*vec_extractv16qi_zext): Likewise.
- (ssse3_ph<plusminus_mnemonic>wv8hi3): Likewise.
- (ssse3_pmaddubsw128): Likewise.
- (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Likewise.
- (<ssse3_avx2>_pshufb<mode>3<mask_name>): Likewise.
- (<ssse3_avx2>_psign<mode>3): Likewise.
- (<ssse3_avx2>_palignr<mode>): Likewise.
- (*abs<mode>2): Likewise.
- (sse4_2_pcmpestr): Likewise.
- (sse4_2_pcmpestri): Likewise.
- (sse4_2_pcmpestrm): Likewise.
- (sse4_2_pcmpestr_cconly): Likewise.
- (sse4_2_pcmpistr): Likewise.
- (sse4_2_pcmpistri): Likewise.
- (sse4_2_pcmpistrm): Likewise.
- (sse4_2_pcmpistr_cconly): Likewise.
- (vgf2p8affineinvqb_<mode><mask_name>): Likewise.
- (vgf2p8affineqb_<mode><mask_name>): Likewise.
- (vgf2p8mulb_<mode><mask_name>): Likewise.
- (*<code>v8hi3 [smaxmin]): Drop "prefix_data16" and
- "prefix_extra".
- (*<code>v16qi3 [umaxmin]): Likewise.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386.md (sse4_1_round<mode>2): Make
- "length_immediate" uniformly 1.
- * config/i386/mmx.md (mmx_pblendvb_v8qi): Likewise.
- (mmx_pblendvb_<mode>): Likewise.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md
- (<avx512>_<complexopname>_<mode><maskc_name><round_name>): Add
- "prefix" attribute.
- (avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>):
- Likewise.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md (xop_phadd<u>bw): Add "prefix",
- "prefix_extra", and "mode" attributes.
- (xop_phadd<u>bd): Likewise.
- (xop_phadd<u>bq): Likewise.
- (xop_phadd<u>wd): Likewise.
- (xop_phadd<u>wq): Likewise.
- (xop_phadd<u>dq): Likewise.
- (xop_phsubbw): Likewise.
- (xop_phsubwd): Likewise.
- (xop_phsubdq): Likewise.
- (xop_rotl<mode>3): Add "prefix" and "prefix_extra" attributes.
- (xop_rotr<mode>3): Likewise.
- (xop_frcz<mode>2): Likewise.
- (*xop_vmfrcz<mode>2): Likewise.
- (xop_vrotl<mode>3): Add "prefix" attribute. Change
- "prefix_extra" to 1.
- (xop_sha<mode>3): Likewise.
- (xop_shl<mode>3): Likewise.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md
- (*<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Drop
- "prefix_extra".
- (avx512dq_vextract<shuffletype>64x2_1_mask): Likewise.
- (*avx512dq_vextract<shuffletype>64x2_1): Likewise.
- (avx512f_vextract<shuffletype>32x4_1_mask): Likewise.
- (*avx512f_vextract<shuffletype>32x4_1): Likewise.
- (vec_extract_lo_<mode>_mask [AVX512 forms]): Likewise.
- (vec_extract_lo_<mode> [AVX512 forms]): Likewise.
- (vec_extract_hi_<mode>_mask [AVX512 forms]): Likewise.
- (vec_extract_hi_<mode> [AVX512 forms]): Likewise.
- (@vec_extract_lo_<mode> [AVX512 forms]): Likewise.
- (@vec_extract_hi_<mode> [AVX512 forms]): Likewise.
- (vec_extract_lo_v64qi): Likewise.
- (vec_extract_hi_v64qi): Likewise.
- (*vec_widen_umult_even_v16si<mask_name>): Likewise.
- (*vec_widen_smult_even_v16si<mask_name>): Likewise.
- (*avx512f_<code><mode>3<mask_name>): Likewise.
- (*vec_extractv4ti): Likewise.
- (avx512bw_<code>v32qiv32hi2<mask_name>): Likewise.
- (<mask_codefor>avx512dq_broadcast<mode><mask_name>_1): Likewise.
- Add "length_immediate".
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386.md (@rdrand<mode>): Add "prefix_0f". Drop
- "prefix_extra".
- (@rdseed<mode>): Likewise.
- * config/i386/mmx.md (<code><mode>3 [smaxmin and umaxmin cases]):
- Adjust "prefix_extra".
- * config/i386/sse.md (@vec_set<mode>_0): Likewise.
- (*sse4_1_<code><mode>3<mask_name>): Likewise.
- (*avx2_eq<mode>3): Likewise.
- (avx2_gt<mode>3): Likewise.
- (<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
- (*vec_extract<mode>): Likewise.
- (<vi8_sse4_1_avx2_avx512>_movntdqa): Likewise.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386.md (rd<fsgs>base<mode>): Add "prefix_0f" and
- "prefix_rep". Drop "prefix_extra".
- (wr<fsgs>base<mode>): Likewise.
- (ptwrite<mode>): Likewise.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386.md (isa): Move up.
- (length_immediate): Handle "fma4".
- (prefix): Handle "ssemuladd".
- * config/i386/sse.md (*fma_fmadd_<mode>): Add "prefix" attribute.
- (<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>):
- Likewise.
- (<avx512>_fmadd_<mode>_mask<round_name>): Likewise.
- (<avx512>_fmadd_<mode>_mask3<round_name>): Likewise.
- (<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>):
- Likewise.
- (<avx512>_fmsub_<mode>_mask<round_name>): Likewise.
- (<avx512>_fmsub_<mode>_mask3<round_name>): Likewise.
- (*fma_fnmadd_<mode>): Likewise.
- (<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>):
- Likewise.
- (<avx512>_fnmadd_<mode>_mask<round_name>): Likewise.
- (<avx512>_fnmadd_<mode>_mask3<round_name>): Likewise.
- (<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>):
- Likewise.
- (<avx512>_fnmsub_<mode>_mask<round_name>): Likewise.
- (<avx512>_fnmsub_<mode>_mask3<round_name>): Likewise.
- (<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>):
- Likewise.
- (<avx512>_fmaddsub_<mode>_mask<round_name>): Likewise.
- (<avx512>_fmaddsub_<mode>_mask3<round_name>): Likewise.
- (<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>):
- Likewise.
- (<avx512>_fmsubadd_<mode>_mask<round_name>): Likewise.
- (<avx512>_fmsubadd_<mode>_mask3<round_name>): Likewise.
- (*fmai_fmadd_<mode>): Likewise.
- (*fmai_fmsub_<mode>): Likewise.
- (*fmai_fnmadd_<mode><round_name>): Likewise.
- (*fmai_fnmsub_<mode><round_name>): Likewise.
- (avx512f_vmfmadd_<mode>_mask<round_name>): Likewise.
- (avx512f_vmfmadd_<mode>_mask3<round_name>): Likewise.
- (avx512f_vmfmadd_<mode>_maskz_1<round_name>): Likewise.
- (*avx512f_vmfmsub_<mode>_mask<round_name>): Likewise.
- (avx512f_vmfmsub_<mode>_mask3<round_name>): Likewise.
- (*avx512f_vmfmsub_<mode>_maskz_1<round_name>): Likewise.
- (avx512f_vmfnmadd_<mode>_mask<round_name>): Likewise.
- (avx512f_vmfnmadd_<mode>_mask3<round_name>): Likewise.
- (avx512f_vmfnmadd_<mode>_maskz_1<round_name>): Likewise.
- (*avx512f_vmfnmsub_<mode>_mask<round_name>): Likewise.
- (*avx512f_vmfnmsub_<mode>_mask3<round_name>): Likewise.
- (*avx512f_vmfnmsub_<mode>_maskz_1<round_name>): Likewise.
- (*fma4i_vmfmadd_<mode>): Likewise.
- (*fma4i_vmfmsub_<mode>): Likewise.
- (*fma4i_vmfnmadd_<mode>): Likewise.
- (*fma4i_vmfnmsub_<mode>): Likewise.
- (fma_<complexopname>_<mode><sdc_maskz_name><round_name>): Likewise.
- (<avx512>_<complexopname>_<mode>_mask<round_name>): Likewise.
- (avx512fp16_fma_<complexopname>sh_v8hf<mask_scalarcz_name><round_scalarcz_name>):
- Likewise.
- (avx512fp16_<complexopname>sh_v8hf_mask<round_name>): Likewise.
- (xop_p<macs><ssemodesuffix><ssemodesuffix>): Likewise.
- (xop_p<macs>dql): Likewise.
- (xop_p<macs>dqh): Likewise.
- (xop_p<macs>wd): Likewise.
- (xop_p<madcs>wd): Likewise.
- (fma_<complexpairopname>_<mode>_pair): Likewise. Add "mode" attribute.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386.md (length_immediate): Handle "sse4arg".
- (prefix): Likewise.
- (*xop_pcmov_<mode>): Add "mode" attribute.
- * config/i386/mmx.md (*xop_maskcmp<mode>3): Drop "prefix_data16",
- "prefix_rep", "prefix_extra", and "length_immediate" attributes.
- (*xop_maskcmp_uns<mode>3): Likewise. Switch "type" to "sse4arg".
- (*xop_pcmov_<mode>): Add "mode" attribute.
- * config/i386/sse.md (xop_pcmov_<mode><avxsizesuffix>): Add "mode"
- attribute.
- (xop_maskcmp<mode>3): Drop "prefix_data16", "prefix_rep",
- "prefix_extra", and "length_immediate" attributes.
- (xop_maskcmp_uns<mode>3): Likewise. Switch "type" to "sse4arg".
- (xop_maskcmp_uns2<mode>3): Drop "prefix_data16", "prefix_extra",
- and "length_immediate" attributes. Switch "type" to "sse4arg".
- (xop_pcom_tf<mode>3): Likewise.
- (xop_vpermil2<mode>3): Drop "length_immediate" attribute.
-
-2023-08-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386.md (prefix_extra): Correct comment. Fold
- cases yielding 2 into ones yielding 1.
-
-2023-08-07 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/106293
- * tree-vect-loop-manip.cc (vect_loop_versioning): Fix profile update.
- * tree-vect-loop.cc (vect_transform_loop): Likewise.
-
-2023-08-07 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/96695
- * match.pd (min_value, max_value): Extend to
- pointer types too.
-
-2023-08-06 Jan Hubicka <jh@suse.cz>
-
- * config/i386/cpuid.h (__get_cpuid_count, __get_cpuid_max): Add
- __builtin_expect that CPU likely supports cpuid.
-
-2023-08-06 Jan Hubicka <jh@suse.cz>
-
- * tree-loop-distribution.cc (loop_distribution::execute): Disable
- distribution for loops with estimated iterations 0.
-
-2023-08-06 Jan Hubicka <jh@suse.cz>
-
- * tree-vect-loop-manip.cc (vect_do_peeling): Fix profile update of peeled epilogues.
-
-2023-08-04 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
- more Zicond patterns. Fix whitespace typo.
- (riscv_rtx_costs): Remove accidental code duplication.
- Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
-
-2023-08-04 Yan Simonaytes <simonaytes.yan@ispras.ru>
-
- PR target/110202
- * config/i386/i386-protos.h
- (vpternlog_redundant_operand_mask): Declare.
- (substitute_vpternlog_operands): Declare.
- * config/i386/i386.cc
- (vpternlog_redundant_operand_mask): New helper.
- (substitute_vpternlog_operands): New function. Use them...
- * config/i386/sse.md: ... here in new VPTERNLOG define_splits.
-
-2023-08-04 Roger Sayle <roger@nextmovesoftware.com>
-
- * expmed.cc (extract_bit_field_1): Document that an UNSIGNEDP
- value of -1 is equivalent to don't care.
- (extract_integral_bit_field): Indicate that we don't require
- the most significant word to be zero extended, if we're about
- to sign extend it.
- (extract_fixed_bit_field_1): Document that an UNSIGNEDP value
- of -1 is equivalent to don't care. Don't clear the most
- significant bits with AND mask when UNSIGNEDP is -1.
-
-2023-08-04 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/sse.md (define_split): Convert highpart:DF extract
- from V2DFmode register into a sse2_storehpd instruction.
- (define_split): Likewise, convert lowpart:DF extract from V2DF
- register into a sse2_storelpd instruction.
-
-2023-08-04 Qing Zhao <qing.zhao@oracle.com>
-
- * doc/invoke.texi (-Wflex-array-member-not-at-end): Document
- new option.
-
-2023-08-04 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-lives.cc (process_bb_lives): Check input insn pattern hard regs
- against early clobber hard regs.
-
-2023-08-04 Tamar Christina <tamar.christina@arm.com>
-
- * doc/extend.texi: Document it.
-
-2023-08-04 Tamar Christina <tamar.christina@arm.com>
-
- PR target/106346
- * config/aarch64/aarch64-simd.md (vec_widen_<sur>shiftl_lo_<mode>,
- vec_widen_<sur>shiftl_hi_<mode>): Remove.
- (aarch64_<sur>shll<mode>_internal): Renamed to...
- (aarch64_<su>shll<mode>): .. This.
- (aarch64_<sur>shll2<mode>_internal): Renamed to...
- (aarch64_<su>shll2<mode>): .. This.
- (aarch64_<sur>shll_n<mode>, aarch64_<sur>shll2_n<mode>): Re-use new
- optabs.
- * config/aarch64/constraints.md (D2, DL): New.
- * config/aarch64/predicates.md (aarch64_simd_shll_imm_vec): New.
-
-2023-08-04 Tamar Christina <tamar.christina@arm.com>
-
- * gensupport.cc (conlist): Support length 0 attribute.
-
-2023-08-04 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_bool_compound_p): New.
- (aarch64_adjust_stmt_cost, aarch64_vector_costs::count_ops): Use it.
-
-2023-08-04 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_multiply_add_p): Update handling
- of constants.
- (aarch64_adjust_stmt_cost): Use it.
- (aarch64_vector_costs::count_ops): Likewise.
- (aarch64_vector_costs::add_stmt_cost): Pass vinfo to
- aarch64_adjust_stmt_cost.
-
-2023-08-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110838
- * tree-vect-patterns.cc (vect_recog_over_widening_pattern):
- Fix right-shift value sanitizing. Properly emit external
- def mangling in the preheader rather than in the pattern
- def sequence where it will fail vectorizing.
-
-2023-08-04 Matthew Malcomson <matthew.malcomson@arm.com>
-
- PR middle-end/110316
- PR middle-end/9903
- * timevar.cc (NANOSEC_PER_SEC, TICKS_TO_NANOSEC,
- CLOCKS_TO_NANOSEC, nanosec_to_floating_sec, percent_of): New.
- (TICKS_TO_MSEC, CLOCKS_TO_MSEC): Remove these macros.
- (timer::validate_phases): Use integral arithmetic to check
- validity.
- (timer::print_row, timer::print): Convert from integral
- nanoseconds to floating point seconds before printing.
- (timer::all_zero): Change limit to nanosec count instead of
- fractional count of seconds.
- (make_json_for_timevar_time_def): Convert from integral
- nanoseconds to floating point seconds before recording.
- * timevar.h (struct timevar_time_def): Update all measurements
- to use uint64_t nanoseconds rather than seconds stored in a
- double.
-
-2023-08-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110838
- * match.pd (([rl]shift @0 out-of-bounds) -> zero): Restrict
- the arithmetic right-shift case to non-negative operands.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfmacc_frm): New class for vfmacc frm.
- (vfmacc_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmacc_frm): New function definition.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_ternop_insn): Add frm operand support.
- * config/riscv/vector.md: Add vfmuladd to frm_mode.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfnmacc_frm): New class for vfnmacc.
- (vfnmacc_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfnmacc_frm): New function definition.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfmsac_frm): New class for vfmsac frm.
- (vfmsac_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmsac_frm): New function definition.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfnmsac_frm): New class for vfnmsac frm.
- (vfnmsac_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfnmsac_frm): New function definition.
-
-2023-08-04 Georg-Johann Lay <avr@gjlay.de>
-
- * config/avr/avr-mcus.def (avr64dd14, avr64dd20, avr64dd28, avr64dd32)
- (avr64ea28, avr64ea32, avr64ea48, attiny424, attiny426, attiny427)
- (attiny824, attiny826, attiny827, attiny1624, attiny1626, attiny1627)
- (attiny3224, attiny3226, attiny3227, avr16dd14, avr16dd20, avr16dd28)
- (avr16dd32, avr32dd14, avr32dd20, avr32dd28, avr32dd32)
- (attiny102, attiny104): New devices.
- * doc/avr-mmcu.texi: Regenerate.
-
-2023-08-04 Georg-Johann Lay <avr@gjlay.de>
-
- * config/avr/avr-mcus.def (avr128d*, avr64d*): Fix their FLASH_SIZE
- and PM_OFFSET entries.
-
-2023-08-04 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110874
- * gimple-match-head.cc (gimple_bit_not_with_nop): New declaration.
- (gimple_maybe_cmp): Likewise.
- (gimple_bitwise_inverted_equal_p): Rewrite to use gimple_bit_not_with_nop
- and gimple_maybe_cmp instead of being recursive.
- * match.pd (bit_not_with_nop): New match pattern.
- (maybe_cmp): Likewise.
-
-2023-08-04 Drew Ross <drross@redhat.com>
-
- PR middle-end/101955
- * match.pd ((signed x << c) >> c): New canonicalization.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfnmsac_frm): New class for vfnmsac frm.
- (vfnmsac_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfnmsac_frm): New function definition.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfmsac_frm): New class for vfmsac frm.
- (vfmsac_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmsac_frm): New function definition.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfnmacc_frm): New class for vfnmacc.
- (vfnmacc_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfnmacc_frm): New function definition.
-
-2023-08-04 Hao Liu <hliu@os.amperecomputing.com>
-
- PR target/110625
- * config/aarch64/aarch64.cc (aarch64_force_single_cycle): check
- STMT_VINFO_REDUC_DEF to avoid failures in info_for_reduction.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class vfmacc_frm): New class for vfmacc frm.
- (vfmacc_frm_obj): New declaration.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmacc_frm): New function definition.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_ternop_insn): Add frm operand support.
- * config/riscv/vector.md: Add vfmuladd to frm_mode.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (vfwmul_frm_obj): New declaration.
- (vfwmul_frm): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h:
- (vfwmul_frm): Ditto.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwmul_frm): New function definition.
- * config/riscv/vector.md: (frm_mode) Add vfwmul to frm_mode.
-
-2023-08-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (binop_frm): New declaration.
- (reverse_binop_frm): Likewise.
- (BASE): Likewise.
- * config/riscv/riscv-vector-builtins-bases.h:
- (vfdiv_frm): New extern declaration.
- (vfrdiv_frm): Likewise.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfdiv_frm): New function definition.
- (vfrdiv_frm): Likewise.
- * config/riscv/vector.md: Add vfdiv to frm_mode.
-
-2023-08-03 Jan Hubicka <jh@suse.cz>
-
- * tree-cfg.cc (print_loop_info): Print entry count.
-
-2023-08-03 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-split.cc (split_loop): Update estimated iteration counts.
-
-2023-08-03 Jan Hubicka <jh@suse.cz>
-
- PR bootstrap/110857
- * cfgloopmanip.cc (scale_loop_profile): (Un)initialize
- unadjusted_exit_count.
-
-2023-08-03 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-prop.cc (ipa_compute_jump_functions_for_edge): Read global
- value/mask.
-
-2023-08-03 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
- various Zicond patterns.
- * config/riscv/riscv.md (mov<mode>cc): Allow TARGET_ZICOND. Use
- sfb_alu_operand for both arms of the conditional move.
- Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
-
-2023-08-03 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- PR target/107844
- PR target/107479
- PR target/107480
- PR target/107481
- * config.gcc: Added core-builtins.cc and .o files.
- * config/bpf/bpf-passes.def: Removed file.
- * config/bpf/bpf-protos.h (bpf_add_core_reloc,
- bpf_replace_core_move_operands): New prototypes.
- * config/bpf/bpf.cc (enum bpf_builtins, is_attr_preserve_access,
- maybe_make_core_relo, bpf_core_field_info, bpf_core_compute,
- bpf_core_get_index, bpf_core_new_decl, bpf_core_walk,
- bpf_is_valid_preserve_field_info_arg, is_attr_preserve_access,
- handle_attr_preserve, pass_data_bpf_core_attr, pass_bpf_core_attr):
- Removed.
- (def_builtin, bpf_expand_builtin, bpf_resolve_overloaded_builtin): Changed.
- * config/bpf/bpf.md (define_expand mov<MM:mode>): Changed.
- (mov_reloc_core<mode>): Added.
- * config/bpf/core-builtins.cc (struct cr_builtin, enum
- cr_decision struct cr_local, struct cr_final, struct
- core_builtin_helpers, enum bpf_plugin_states): Added types.
- (builtins_data, core_builtin_helpers, core_builtin_type_defs):
- Added variables.
- (allocate_builtin_data, get_builtin-data, search_builtin_data,
- remove_parser_plugin, compare_same_kind, compare_same_ptr_expr,
- compare_same_ptr_type, is_attr_preserve_access, core_field_info,
- bpf_core_get_index, compute_field_expr,
- pack_field_expr_for_access_index, pack_field_expr_for_preserve_field,
- process_field_expr, pack_enum_value, process_enum_value, pack_type,
- process_type, bpf_require_core_support, make_core_relo, read_kind,
- kind_access_index, kind_preserve_field_info, kind_enum_value,
- kind_type_id, kind_preserve_type_info, get_core_builtin_fndecl_for_type,
- bpf_handle_plugin_finish_type, bpf_init_core_builtins,
- construct_builtin_core_reloc, bpf_resolve_overloaded_core_builtin,
- bpf_expand_core_builtin, bpf_add_core_reloc,
- bpf_replace_core_move_operands): Added functions.
- * config/bpf/core-builtins.h (enum bpf_builtins): Added.
- (bpf_init_core_builtins, bpf_expand_core_builtin,
- bpf_resolve_overloaded_core_builtin): Added functions.
- * config/bpf/coreout.cc (struct bpf_core_extra): Added.
- (bpf_core_reloc_add, output_asm_btfext_core_reloc): Changed.
- * config/bpf/coreout.h (bpf_core_reloc_add) Changed prototype.
- * config/bpf/t-bpf: Added core-builtins.o.
- * doc/extend.texi: Added documentation for new BPF builtins.
-
-2023-08-03 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-fold.cc (fold_using_range::range_of_range_op): Add
- ranges to the call to relation_fold_and_or.
- (fold_using_range::relation_fold_and_or): Add op1 and op2 ranges.
- (fur_source::register_outgoing_edges): Add op1 and op2 ranges.
- * gimple-range-fold.h (relation_fold_and_or): Adjust params.
- * gimple-range-gori.cc (gori_compute::compute_operand_range): Add
- a varying op1 and op2 to call.
- * range-op-float.cc (range_operator::op1_op2_relation): New dafaults.
- (operator_equal::op1_op2_relation): New float version.
- (operator_not_equal::op1_op2_relation): Ditto.
- (operator_lt::op1_op2_relation): Ditto.
- (operator_le::op1_op2_relation): Ditto.
- (operator_gt::op1_op2_relation): Ditto.
- (operator_ge::op1_op2_relation) Ditto.
- * range-op-mixed.h (operator_equal::op1_op2_relation): New float
- prototype.
- (operator_not_equal::op1_op2_relation): Ditto.
- (operator_lt::op1_op2_relation): Ditto.
- (operator_le::op1_op2_relation): Ditto.
- (operator_gt::op1_op2_relation): Ditto.
- (operator_ge::op1_op2_relation): Ditto.
- * range-op.cc (range_op_handler::op1_op2_relation): Dispatch new
- variations.
- (range_operator::op1_op2_relation): Add extra params.
- (operator_equal::op1_op2_relation): Ditto.
- (operator_not_equal::op1_op2_relation): Ditto.
- (operator_lt::op1_op2_relation): Ditto.
- (operator_le::op1_op2_relation): Ditto.
- (operator_gt::op1_op2_relation): Ditto.
- (operator_ge::op1_op2_relation): Ditto.
- * range-op.h (range_operator): New prototypes.
- (range_op_handler): Ditto.
-
-2023-08-03 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (gori_compute::compute_operand1_range):
- Use identity relation.
- (gori_compute::compute_operand2_range): Ditto.
- * value-relation.cc (get_identity_relation): New.
- * value-relation.h (get_identity_relation): New prototype.
-
-2023-08-03 Andrew MacLeod <amacleod@redhat.com>
-
- * value-range.h (Value_Range::set_varying): Set the type.
- (Value_Range::set_zero): Ditto.
- (Value_Range::set_nonzero): Ditto.
-
-2023-08-03 Jeff Law <jeffreyalaw@gmail.com>
-
- * config/riscv/riscv.cc (riscv_rtx_costs): Remove errant hunk from
- recent commit.
-
-2023-08-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Add vfsub.
-
-2023-08-03 Richard Sandiford <richard.sandiford@arm.com>
-
- * poly-int.h (can_div_trunc_p): Succeed for more boundary conditions.
-
-2023-08-03 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110838
- * tree-vect-patterns.cc (vect_recog_over_widening_pattern):
- Adjust the shift operand of RSHIFT_EXPRs.
-
-2023-08-03 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110702
- * tree-ssa-loop-ivopts.cc (rewrite_use_address): When
- we created a NULL pointer based access rewrite that to
- a LEA.
-
-2023-08-03 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-sink.cc: Include tree-ssa-live.h.
- (pass_sink_code::execute): Instantiate virtual_operand_live
- and pass it down.
- (sink_code_in_bb): Pass down virtual_operand_live.
- (statement_sink_location): Get virtual_operand_live and
- verify we are not sinking loads across stores by looking up
- the live virtual operand at the sink location.
-
-2023-08-03 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-live.h (class virtual_operand_live): New.
- * tree-ssa-live.cc (virtual_operand_live::init): New.
- (virtual_operand_live::get_live_in): Likewise.
- (virtual_operand_live::get_live_out): Likewise.
-
-2023-08-03 Richard Biener <rguenther@suse.de>
-
- * passes.def: Exchange loop splitting and final value
- replacement passes.
-
-2023-08-03 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
- New function which handles bswap patterns for vec_perm_const.
- (vectorize_vec_perm_const_1): Call new function.
- * config/s390/vector.md (*bswap<mode>): Fix operands in output
- template.
- (*vstbr<mode>): New insn.
-
-2023-08-03 Alexandre Oliva <oliva@adacore.com>
-
- * config/vxworks-smp.opt: New. Introduce -msmp.
- * config.gcc: Enable it on powerpc* vxworks prior to 7r*.
- * config/rs6000/vxworks.h (STARTFILE_PREFIX_SPEC): Choose
- lib_smp when -msmp is present in the command line.
- * doc/invoke.texi: Document it.
-
-2023-08-03 Yanzhang Wang <yanzhang.wang@intel.com>
-
- * config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf
- when enabling -mno-omit-leaf-frame-pointer
- (riscv_option_override): Override omit-frame-pointer.
- (riscv_frame_pointer_required): Save s0 for non-leaf function
- (TARGET_FRAME_POINTER_REQUIRED): Override defination
- * config/riscv/riscv.opt: Add option support.
-
-2023-08-03 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110792
- * config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
- place operand in a register before gen_<insn>64ti2_doubleword.
- (<any_rotate>di3): Likewise, for rotations by 32 bits, place
- operand in a register before gen_<insn>32di2_doubleword.
- (<any_rotate>32di2_doubleword): Constrain operand to be in register.
- (<any_rotate>64ti2_doubleword): Likewise.
-
-2023-08-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (vfmul_frm_obj): New declaration.
- (Base): Likewise.
- * config/riscv/riscv-vector-builtins-bases.h: Likewise.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfmul_frm): New function definition.
- * config/riscv/vector.md: Add vfmul to frm_mode.
-
-2023-08-03 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`~X & X`): Check that the types match.
- (`~x | x`, `~x ^ x`): Likewise.
-
-2023-08-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.h: Remove
- redudant declaration.
-
-2023-08-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc (BASE): Add
- vfwsub frm.
- * config/riscv/riscv-vector-builtins-bases.h: Add declaration.
- * config/riscv/riscv-vector-builtins-functions.def (vfwsub_frm):
- Add vfwsub function definitions.
-
-2023-08-02 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- PR rtl-optimization/110867
- * combine.cc (simplify_compare_const): Try the optimization only
- in case the constant fits into the comparison mode.
-
-2023-08-02 Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/zicond.md: Remove incorrect zicond patterns and
- renumber/rename them.
- (zero.nez.<GPR:MODE><X:mode>.opt2): Fix output string.
-
-2023-08-02 Richard Biener <rguenther@suse.de>
-
- * tree-phinodes.h (add_phi_node_to_bb): Remove.
- * tree-phinodes.cc (add_phi_node_to_bb): Make static.
-
-2023-08-02 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md (vec_dupv2df<mask_name>): Fold the middle
- two of the alternatives.
-
-2023-08-02 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/92335
- * tree-ssa-sink.cc (select_best_block): Before loop
- optimizations avoid sinking unconditional loads/stores
- in innermost loops to conditional executed places.
-
-2023-08-02 Andrew Pinski <apinski@marvell.com>
-
- * gimple-match-head.cc (gimple_bitwise_inverted_equal_p): Valueize
- the comparison operands before comparing them.
-
-2023-08-02 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`~X & X`, `~X | X`): Move over to
- use bitwise_inverted_equal_p, removing :c as bitwise_inverted_equal_p
- handles that already.
- Remove range test simplifications to true/false as they
- are now handled by these patterns.
-
-2023-08-02 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (match_simplify_replacement): Mark's cond
- statement's lhs and rhs to check if trivial dead.
- Rename inserted_exprs to exprs_maybe_dce; also move it so
- bitmap is not allocated if not needed.
-
-2023-08-02 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class widen_binop_frm): New class for binop frm.
- (BASE): Add vfwadd_frm.
- * config/riscv/riscv-vector-builtins-bases.h: New declaration.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfwadd_frm): New function definition.
- * config/riscv/riscv-vector-builtins-shapes.cc
- (BASE_NAME_MAX_LEN): New macro.
- (struct alu_frm_def): Leverage new base class.
- (struct build_frm_base): New build base for frm.
- (struct widen_alu_frm_def): New struct for widen alu frm.
- (SHAPE): Add widen_alu_frm shape.
- * config/riscv/riscv-vector-builtins-shapes.h: New declaration.
- * config/riscv/vector.md (frm_mode): Add vfwalu type.
-
-2023-08-02 Jan Hubicka <jh@suse.cz>
-
- * cfgloop.h (loop_count_in): Declare.
- * cfgloopanal.cc (expected_loop_iterations_by_profile): Use count_in.
- (loop_count_in): Move here from ...
- * cfgloopmanip.cc (loop_count_in): ... here.
- (scale_loop_profile): Improve dumping; cast iteration bound to sreal.
-
-2023-08-02 Jan Hubicka <jh@suse.cz>
-
- * cfg.cc (scale_strictly_dominated_blocks): New function.
- * cfg.h (scale_strictly_dominated_blocks): Declare.
- * tree-cfg.cc (fold_loop_internal_call): Fixup CFG profile.
-
-2023-08-02 Richard Biener <rguenther@suse.de>
-
- PR rtl-optimization/110587
- * lra-spills.cc (return_regno_p): Remove.
- (regno_in_use_p): Likewise.
- (lra_final_code_change): Do not remove noop moves
- between hard registers.
-
-2023-08-02 liuhongt <hongtao.liu@intel.com>
-
- PR target/81904
- * config/i386/sse.md (vec_fmaddsub<mode>4): Extend to vector
- HFmode, use mode iterator VFH instead.
- (vec_fmsubadd<mode>4): Ditto.
- (<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>):
- Remove scalar mode from iterator, use VFH_AVX512VL instead.
- (<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>):
- Ditto.
-
-2023-08-02 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (*avx2_lddqu_inserti_to_bcasti): New
- pre_reload define_insn_and_split.
-
-2023-08-02 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_rtx_costs): Add costing for
- using Zicond to implement some conditional moves.
-
-2023-08-02 Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/zicond.md: Use the X iterator instead of ANYI
- on the comparison input operands.
-
-2023-08-02 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_rtx_costs, case IF_THEN_ELSE): Add
- Zicond costing.
- (case SET): For INSNs that just set a REG, take the cost from the
- SET_SRC.
- Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
-
-2023-08-02 Hu, Lin1 <lin1.hu@intel.com>
-
- * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_INT8_SET):
- Change OPTION_MASK_ISA2_AMX_TILE to OPTION_MASK_ISA2_AMX_TILE_SET.
- (OPTION_MASK_ISA2_AMX_BF16_SET): Ditto
- (OPTION_MASK_ISA2_AMX_FP16_SET): Ditto
- (OPTION_MASK_ISA2_AMX_COMPLEX_SET): Ditto
- (OPTION_MASK_ISA_ABM_SET):
- Change OPTION_MASK_ISA_POPCNT to OPTION_MASK_ISA_POPCNT_SET.
-
-2023-08-01 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config/s390/s390.cc (s390_encode_section_info): Assume external
- symbols without explicit alignment to be unaligned if
- -munaligned-symbols has been specified.
- * config/s390/s390.opt (-munaligned-symbols): New option.
-
-2023-08-01 Richard Ball <richard.ball@arm.com>
-
- * gimple-fold.cc (fold_ctor_reference):
- Add support for poly_int.
-
-2023-08-01 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/110220
- * config/avr/avr.cc (avr_optimize_casesi): Set JUMP_LABEL and
- LABEL_NUSES of new conditional branch instruction.
-
-2023-08-01 Jan Hubicka <jh@suse.cz>
-
- * tree-vect-loop-manip.cc (vect_do_peeling): Fix profile update after
- constant prologue peeling.
-
-2023-08-01 Christophe Lyon <christophe.lyon@linaro.org>
-
- * doc/sourcebuild.texi (arm_v8_1m_main_cde_mve_fp): Fix spelling.
-
-2023-08-01 Pan Li <pan2.li@intel.com>
- Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (DYNAMIC_FRM_RTL): New macro.
- (STATIC_FRM_P): Ditto.
- (struct mode_switching_info): New struct for mode switching.
- (struct machine_function): Add new field mode switching.
- (riscv_emit_frm_mode_set): Add DYN_CALL emit.
- (riscv_frm_adjust_mode_after_call): New function for call mode.
- (riscv_frm_emit_after_call_in_bb_end): New function for emit
- insn when call as the end of bb.
- (riscv_frm_mode_needed): New function for frm mode needed.
- (frm_unknown_dynamic_p): Remove call check.
- (riscv_mode_needed): Extrac function for frm.
- (riscv_frm_mode_after): Add DYN_CALL after.
- (riscv_mode_entry): Remove backup rtl initialization.
- * config/riscv/vector.md (frm_mode): Add dyn_call.
- (fsrmsi_restore_exit): Rename to _volatile.
- (fsrmsi_restore_volatile): Likewise.
-
-2023-08-01 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc
- (class reverse_binop_frm): Add new template for reversed frm.
- (vfsub_frm_obj): New obj.
- (vfrsub_frm_obj): Likewise.
- * config/riscv/riscv-vector-builtins-bases.h:
- (vfsub_frm): New declaration.
- (vfrsub_frm): Likewise.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfsub_frm): New function define.
- (vfrsub_frm): Likewise.
-
-2023-08-01 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/93044
- * match.pd (nested int casts): A truncation (to the same size or smaller)
- can always remove the inner cast.
-
-2023-07-31 Hamza Mahfooz <someguy@effective-light.com>
-
- PR c/65213
- * doc/invoke.texi (-Wmissing-variable-declarations): Document
- new option.
-
-2023-07-31 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/106164
- * match.pd (`a != b & a <= b`, `a != b & a >= b`,
- `a == b | a < b`, `a == b | a > b`): Handle these cases
- too.
-
-2023-07-31 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/106164
- * match.pd: Extend the `(X CMP1 CST1) AND/IOR (X CMP2 CST2)`
- patterns to support `(X CMP1 Y) AND/IOR (X CMP2 Y)`.
-
-2023-07-31 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/100864
- * generic-match-head.cc (bitwise_inverted_equal_p): New function.
- * gimple-match-head.cc (bitwise_inverted_equal_p): New macro.
- (gimple_bitwise_inverted_equal_p): New function.
- * match.pd ((~x | y) & x): Use bitwise_inverted_equal_p
- instead of direct matching bit_not.
-
-2023-07-31 Costas Argyris <costas.argyris@gmail.com>
-
- PR driver/77576
- * gcc-ar.cc (main): Expand argv and use
- temporary response file to call ar if any
- expansions were made.
-
-2023-07-31 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/110582
- * gimple-range-fold.cc (fur_list::get_operand): Do not use the
- range vector for non-ssa names.
-
-2023-07-31 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/109361
- * diagnostic-client-data-hooks.h (class sarif_object): New forward
- decl.
- (diagnostic_client_data_hooks::add_sarif_invocation_properties):
- New vfunc.
- * diagnostic-format-sarif.cc: Include "diagnostic-format-sarif.h".
- (class sarif_invocation): Inherit from sarif_object rather than
- json::object.
- (class sarif_result): Likewise.
- (class sarif_ice_notification): Likewise.
- (sarif_object::get_or_create_properties): New.
- (sarif_invocation::prepare_to_flush): Add "context" param. Use it
- to call the context's add_sarif_invocation_properties hook.
- (sarif_builder::flush_to_file): Pass m_context to
- sarif_invocation::prepare_to_flush.
- * diagnostic-format-sarif.h: New header.
- * doc/invoke.texi (Developer Options): Clarify that -ftime-report
- writes to stderr. Document that if SARIF diagnostic output is
- requested then any timing information is written in JSON form as
- part of the SARIF output, rather than to stderr.
- * timevar.cc: Include "json.h".
- (timer::named_items::m_hash_map): Split out type into...
- (timer::named_items::hash_map_t): ...this new typedef.
- (timer::named_items::make_json): New function.
- (timevar_diff): New function.
- (make_json_for_timevar_time_def): New function.
- (timer::timevar_def::make_json): New function.
- (timer::make_json): New function.
- * timevar.h (class json::value): New forward decl.
- (timer::make_json): New decl.
- (timer::timevar_def::make_json): New decl.
- * tree-diagnostic-client-data-hooks.cc: Include
- "diagnostic-format-sarif.h" and "timevar.h".
- (compiler_data_hooks::add_sarif_invocation_properties): New vfunc
- implementation.
-
-2023-07-31 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * combine.cc (simplify_compare_const): Narrow comparison of
- memory and constant.
- (try_combine): Adapt new function signature.
- (simplify_comparison): Adapt new function signature.
-
-2023-07-31 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-v.cc (expand_vec_series): Drop unused
- variable.
- (expand_vector_init_insert_elems): Ditto.
-
-2023-07-31 Hao Liu <hliu@os.amperecomputing.com>
-
- PR target/110625
- * config/aarch64/aarch64.cc (count_ops): Only '* count' for
- single_defuse_cycle while counting reduction_latency.
-
-2023-07-31 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * internal-fn.def (DEF_INTERNAL_COND_FN): New macro.
- (DEF_INTERNAL_SIGNED_COND_FN): Ditto.
- (COND_ADD): Remove.
- (COND_SUB): Ditto.
- (COND_MUL): Ditto.
- (COND_DIV): Ditto.
- (COND_MOD): Ditto.
- (COND_RDIV): Ditto.
- (COND_MIN): Ditto.
- (COND_MAX): Ditto.
- (COND_FMIN): Ditto.
- (COND_FMAX): Ditto.
- (COND_AND): Ditto.
- (COND_IOR): Ditto.
- (COND_XOR): Ditto.
- (COND_SHL): Ditto.
- (COND_SHR): Ditto.
- (COND_FMA): Ditto.
- (COND_FMS): Ditto.
- (COND_FNMA): Ditto.
- (COND_FNMS): Ditto.
- (COND_NEG): Ditto.
- (COND_LEN_ADD): Ditto.
- (COND_LEN_SUB): Ditto.
- (COND_LEN_MUL): Ditto.
- (COND_LEN_DIV): Ditto.
- (COND_LEN_MOD): Ditto.
- (COND_LEN_RDIV): Ditto.
- (COND_LEN_MIN): Ditto.
- (COND_LEN_MAX): Ditto.
- (COND_LEN_FMIN): Ditto.
- (COND_LEN_FMAX): Ditto.
- (COND_LEN_AND): Ditto.
- (COND_LEN_IOR): Ditto.
- (COND_LEN_XOR): Ditto.
- (COND_LEN_SHL): Ditto.
- (COND_LEN_SHR): Ditto.
- (COND_LEN_FMA): Ditto.
- (COND_LEN_FMS): Ditto.
- (COND_LEN_FNMA): Ditto.
- (COND_LEN_FNMS): Ditto.
- (COND_LEN_NEG): Ditto.
- (ADD): New macro define.
- (SUB): Ditto.
- (MUL): Ditto.
- (DIV): Ditto.
- (MOD): Ditto.
- (RDIV): Ditto.
- (MIN): Ditto.
- (MAX): Ditto.
- (FMIN): Ditto.
- (FMAX): Ditto.
- (AND): Ditto.
- (IOR): Ditto.
- (XOR): Ditto.
- (SHL): Ditto.
- (SHR): Ditto.
- (FMA): Ditto.
- (FMS): Ditto.
- (FNMA): Ditto.
- (FNMS): Ditto.
- (NEG): Ditto.
-
-2023-07-31 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110843
- * config/i386/i386-features.cc (compute_convert_gain): Check
- TARGET_AVX512VL (not TARGET_AVX512F) when considering V2DImode
- and V4SImode rotates in STV.
- (general_scalar_chain::convert_rotate): Likewise.
-
-2023-07-31 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/autovec.md (abs<mode>2): Remove `.require ()`.
- * config/riscv/riscv-protos.h (get_mask_mode): Update return
- type.
- * config/riscv/riscv-v.cc (rvv_builder::rvv_builder): Remove
- `.require ()`.
- (emit_vlmax_insn): Ditto.
- (emit_vlmax_fp_insn): Ditto.
- (emit_vlmax_ternary_insn): Ditto.
- (emit_vlmax_fp_ternary_insn): Ditto.
- (emit_nonvlmax_fp_ternary_tu_insn): Ditto.
- (emit_nonvlmax_insn): Ditto.
- (emit_vlmax_slide_insn): Ditto.
- (emit_nonvlmax_slide_tu_insn): Ditto.
- (emit_vlmax_merge_insn): Ditto.
- (emit_vlmax_masked_insn): Ditto.
- (emit_nonvlmax_masked_insn): Ditto.
- (emit_vlmax_masked_store_insn): Ditto.
- (emit_nonvlmax_masked_store_insn): Ditto.
- (emit_vlmax_masked_mu_insn): Ditto.
- (emit_nonvlmax_tu_insn): Ditto.
- (emit_nonvlmax_fp_tu_insn): Ditto.
- (emit_scalar_move_insn): Ditto.
- (emit_vlmax_compress_insn): Ditto.
- (emit_vlmax_reduction_insn): Ditto.
- (emit_vlmax_fp_reduction_insn): Ditto.
- (emit_nonvlmax_fp_reduction_insn): Ditto.
- (expand_vec_series): Ditto.
- (expand_vector_init_merge_repeating_sequence): Ditto.
- (expand_vec_perm): Ditto.
- (shuffle_merge_patterns): Ditto.
- (shuffle_compress_patterns): Ditto.
- (shuffle_decompress_patterns): Ditto.
- (expand_reduction): Ditto.
- (get_mask_mode): Update return type.
- * config/riscv/riscv.cc (riscv_get_mask_mode): Check vector type
- is valid, and use new get_mask_mode interface.
-
-2023-07-31 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_frm_def):
- Move rm suffix before mask.
-
-2023-07-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-vls.md (@vec_duplicate<mode>): New pattern.
- * config/riscv/riscv-v.cc (autovectorize_vector_modes): Add VLS autovec
- support.
-
-2023-07-29 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110790
- * config/i386/i386.md (extv<mode>): Use QImode for offsets.
- (extzv<mode>): Likewise.
- (insv<mode>): Likewise.
- (*testqi_ext_3): Likewise.
- (*btr<mode>_2): Likewise.
- (define_split): Likewise.
- (*btsq_imm): Likewise.
- (*btrq_imm): Likewise.
- (*btcq_imm): Likewise.
- (define_peephole2 x3): Likewise.
- (*bt<mode>): Likewise
- (*bt<mode>_mask): New define_insn_and_split.
- (*jcc_bt<mode>): Use QImode for offsets.
- (*jcc_bt<mode>_1): Delete obsolete pattern.
- (*jcc_bt<mode>_mask): Use QImode offsets.
- (*jcc_bt<mode>_mask_1): Likewise.
- (define_split): Likewise.
- (*bt<mode>_setcqi): Likewise.
- (*bt<mode>_setncqi): Likewise.
- (*bt<mode>_setnc<mode>): Likewise.
- (*bt<mode>_setncqi_2): Likewise.
- (*bt<mode>_setc<mode>_mask): New define_insn_and_split.
- (bmi2_bzhi_<mode>3): Use QImode offsets.
- (*bmi2_bzhi_<mode>3): Likewise.
- (*bmi2_bzhi_<mode>3_1): Likewise.
- (*bmi2_bzhi_<mode>3_1_ccz): Likewise.
- (@tbm_bextri_<mode>): Likewise.
-
-2023-07-29 Jan Hubicka <jh@suse.cz>
-
- * profile-count.cc (profile_probability::sqrt): New member function.
- (profile_probability::pow): Likewise.
- * profile-count.h: (profile_probability::sqrt): Declare
- (profile_probability::pow): Likewise.
- * tree-vect-loop-manip.cc (vect_loop_versioning): Fix profile update.
-
-2023-07-28 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-cache.cc (ssa_cache::merge_range): New.
- (ssa_lazy_cache::merge_range): New.
- * gimple-range-cache.h (class ssa_cache): Adjust protoypes.
- (class ssa_lazy_cache): Ditto.
- * gimple-range.cc (assume_query::calculate_op): Use merge_range.
-
-2023-07-28 Andrew MacLeod <amacleod@redhat.com>
-
- * tree-ssa-propagate.cc (substitute_and_fold_engine::value_on_edge):
- Move from value-query.cc.
- (substitute_and_fold_engine::value_of_stmt): Ditto.
- (substitute_and_fold_engine::range_of_expr): New.
- * tree-ssa-propagate.h (substitute_and_fold_engine): Inherit from
- range_query. New prototypes.
- * value-query.cc (value_query::value_on_edge): Relocate.
- (value_query::value_of_stmt): Ditto.
- * value-query.h (class value_query): Remove.
- (class range_query): Remove base class. Adjust prototypes.
-
-2023-07-28 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/110205
- * gimple-range-cache.h (ranger_cache::m_estimate): Delete.
- * range-op-mixed.h (operator_bitwise_xor::op1_op2_relation_effect):
- Add final override.
- * range-op.cc (operator_lshift): Add missing final overrides.
- (operator_rshift): Ditto.
-
-2023-07-28 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.cc (bpf_option_override): Disable tail-call
- optimizations in BPF target.
-
-2023-07-28 Honza <jh@ryzen4.suse.cz>
-
- * cfgloopmanip.cc (loop_count_in): Break out from ...
- (loop_exit_for_scaling): Break out from ...
- (update_loop_exit_probability_scale_dom_bbs): Break out from ...;
- add more sanity check and debug info.
- (scale_loop_profile): ... here.
- (create_empty_loop_on_edge): Fix whitespac.
- * cfgloopmanip.h (update_loop_exit_probability_scale_dom_bbs): Declare.
- * loop-unroll.cc (unroll_loop_constant_iterations): Use
- update_loop_exit_probability_scale_dom_bbs.
- * tree-ssa-loop-manip.cc (update_exit_probability_after_unrolling): Remove.
- (tree_transform_and_unroll_loop): Use
- update_loop_exit_probability_scale_dom_bbs.
- * tree-ssa-loop-split.cc (split_loop): Use
- update_loop_exit_probability_scale_dom_bbs.
-
-2023-07-28 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/77689
- * tree-ssa-loop-split.cc: Include value-query.h.
- (split_at_bb_p): Analyze cases where EQ/NE can be turned
- into LT/LE/GT/GE; return updated guard code.
- (split_loop): Use guard code.
-
-2023-07-28 Roger Sayle <roger@nextmovesoftware.com>
- Richard Biener <rguenther@suse.de>
-
- PR middle-end/28071
- PR rtl-optimization/110587
- * expr.cc (emit_group_load_1): Simplify logic for calling
- force_reg on ORIG_SRC, to avoid making a copy if the source
- is already in a pseudo register.
-
-2023-07-28 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/106923
- * tree-ssa-loop-split.cc (connect_loops): Change probability
- of the test preconditioning second loop to very_likely.
- (fix_loop_bb_probability): Handle correctly case where
- on of the arms of the conditional is empty.
- (split_loop): Fold the test guarding first condition to
- see if it is constant true; Set correct entry block
- probabilities of the split loops; determine correct loop
- eixt probabilities.
-
-2023-07-28 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: remove rounding mode of
- vsadd[u] and vssub[u].
- * config/riscv/vector.md: Ditto.
-
-2023-07-28 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-split.cc (split_loop): Also support NE driven
- loops when IV test is not overflowing.
-
-2023-07-28 liuhongt <hongtao.liu@intel.com>
-
- PR target/110788
- * config/i386/sse.md (avx512cd_maskb_vec_dup<mode>): Add
- UNSPEC_MASKOP.
- (avx512cd_maskw_vec_dup<mode>): Ditto.
-
-2023-07-27 David Faust <david.faust@oracle.com>
-
- PR target/110782
- PR target/110784
- * config/bpf/bpf.opt (msmov): New option.
- * config/bpf/bpf.cc (bpf_option_override): Handle it here.
- * config/bpf/bpf.md (*extendsidi2): New.
- (extendhidi2): New.
- (extendqidi2): New.
- (extendsisi2): New.
- (extendhisi2): New.
- (extendqisi2): New.
- * doc/invoke.texi (Option Summary): Add -msmov eBPF option.
- (eBPF Options): Add -m[no-]smov. Document that -mcpu=v4
- also enables -msmov.
-
-2023-07-27 David Faust <david.faust@oracle.com>
-
- * doc/invoke.texi (Option Summary): Remove -mkernel eBPF option.
- Add -mbswap and -msdiv eBPF options.
- (eBPF Options): Remove -mkernel. Add -mno-{jmpext, jmp32,
- alu32, v3-atomics, bswap, sdiv}. Document that -mcpu=v4 also
- enables -msdiv.
-
-2023-07-27 David Faust <david.faust@oracle.com>
-
- * config/bpf/bpf.md (add<AM:mode>3): Use %w2 instead of %w1
- in pseudo-C dialect output template.
- (sub<AM:mode>3): Likewise.
-
-2023-07-27 Jan Hubicka <jh@suse.cz>
-
- * tree-vect-loop.cc (optimize_mask_stores): Make store
- likely.
-
-2023-07-27 Jan Hubicka <jh@suse.cz>
-
- * cfgloop.h (single_dom_exit): Declare.
- * cfgloopmanip.h (update_exit_probability_after_unrolling): Declare.
- * cfgrtl.cc (struct cfg_hooks): Fix comment.
- * loop-unroll.cc (unroll_loop_constant_iterations): Update exit edge.
- * tree-ssa-loop-ivopts.h (single_dom_exit): Do not declare it here.
- * tree-ssa-loop-manip.cc (update_exit_probability_after_unrolling):
- Break out from ...
- (tree_transform_and_unroll_loop): ... here;
-
-2023-07-27 Jan Hubicka <jh@suse.cz>
-
- * cfgloopmanip.cc (scale_dominated_blocks_in_loop): Move here from
- tree-ssa-loop-manip.cc and avoid recursion.
- (scale_loop_profile): Use scale_dominated_blocks_in_loop.
- (duplicate_loop_body_to_header_edge): Add DLTHE_FLAG_FLAT_PROFILE
- flag.
- * cfgloopmanip.h (DLTHE_FLAG_FLAT_PROFILE): Define.
- (scale_dominated_blocks_in_loop): Declare.
- * predict.cc (dump_prediction): Do not ICE on uninitialized probability.
- (change_edge_frequency): Remove.
- * predict.h (change_edge_frequency): Remove.
- * tree-ssa-loop-manip.cc (scale_dominated_blocks_in_loop): Move to
- cfgloopmanip.cc.
- (niter_for_unrolled_loop): Remove.
- (tree_transform_and_unroll_loop): Fix profile update.
-
-2023-07-27 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-im.cc (execute_sm_if_changed): Turn cap probability
- to guessed; fix count of new_bb.
-
-2023-07-27 Jan Hubicka <jh@suse.cz>
-
- * profile-count.h (profile_count::apply_probability): Fix
- handling of uninitialized probabilities, optimize scaling
- by probability 1.
-
-2023-07-27 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/91838
- * gimple-match-head.cc: Include attribs.h and asan.h.
- * generic-match-head.cc: Likewise.
- * match.pd (([rl]shift @0 out-of-bounds) -> zero): New pattern.
-
-2023-07-27 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add VLS modes.
- (ADJUST_ALIGNMENT): Ditto.
- (ADJUST_PRECISION): Ditto.
- (VLS_MODES): Ditto.
- (VECTOR_MODE_WITH_PREFIX): Ditto.
- * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): New macro.
- * config/riscv/riscv-protos.h (riscv_v_ext_vls_mode_p): New function.
- * config/riscv/riscv-v.cc (INCLUDE_ALGORITHM): Add include.
- (legitimize_move): Enable basic VLS modes support.
- (get_vlmul): Ditto.
- (get_ratio): Ditto.
- (get_vector_mode): Ditto.
- * config/riscv/riscv-vector-switch.def (VLS_ENTRY): Add vls modes.
- * config/riscv/riscv.cc (riscv_v_ext_vls_mode_p): New function.
- (VLS_ENTRY): New macro.
- (riscv_v_ext_mode_p): Add vls modes.
- (riscv_get_v_regno_alignment): New function.
- (riscv_print_operand): Add vls modes.
- (riscv_hard_regno_nregs): Ditto.
- (riscv_hard_regno_mode_ok): Ditto.
- (riscv_regmode_natural_size): Ditto.
- (riscv_vectorize_preferred_vector_alignment): Ditto.
- * config/riscv/riscv.md: Ditto.
- * config/riscv/vector-iterators.md: Ditto.
- * config/riscv/vector.md: Ditto.
- * config/riscv/autovec-vls.md: New file.
-
-2023-07-27 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv_vector.h (enum RVV_CSR): Removed.
- (vread_csr): Ditto.
- (vwrite_csr): Ditto.
-
-2023-07-27 demin.han <demin.han@starfivetech.com>
-
- * config/riscv/autovec.md: Delete which_alternative use in split
-
-2023-07-27 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-sink.cc (sink_code_in_bb): Remove recursion, instead
- use a worklist ...
- (pass_sink_code::execute): ... in the caller.
-
-2023-07-27 Kewen Lin <linkw@linux.ibm.com>
- Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110776
- * tree-vect-stmts.cc (vectorizable_load): Always cost VMAT_ELEMENTWISE
- as scalar load.
-
-2023-07-26 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * config/riscv/riscv.md: Include zicond.md
- * config/riscv/zicond.md: New file.
-
-2023-07-26 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * common/config/riscv/riscv-common.cc: New extension.
- * config/riscv/riscv-opts.h (MASK_ZICOND): New mask.
- (TARGET_ZICOND): New target.
-
-2023-07-26 Carl Love <cel@us.ibm.com>
-
- * config/rs6000/rs6000-c.cc (find_instance): Add new parameter that
- specifies the number of built-in arguments to check.
- (altivec_resolve_overloaded_builtin): Update calls to find_instance
- to pass the number of built-in arguments to be checked.
-
-2023-07-26 David Faust <david.faust@oracle.com>
-
- * config/bpf/bpf.opt (mv3-atomics): New option.
- * config/bpf/bpf.cc (bpf_option_override): Handle it here.
- * config/bpf/bpf.h (enum_reg_class): Add R0 class.
- (REG_CLASS_NAMES): Likewise.
- (REG_CLASS_CONTENTS): Likewise.
- (REGNO_REG_CLASS): Handle R0.
- * config/bpf/bpf.md (UNSPEC_XADD): Rename to UNSPEC_AADD.
- (UNSPEC_AAND): New unspec.
- (UNSPEC_AOR): Likewise.
- (UNSPEC_AXOR): Likewise.
- (UNSPEC_AFADD): Likewise.
- (UNSPEC_AFAND): Likewise.
- (UNSPEC_AFOR): Likewise.
- (UNSPEC_AFXOR): Likewise.
- (UNSPEC_AXCHG): Likewise.
- (UNSPEC_ACMPX): Likewise.
- (atomic_add<mode>): Use UNSPEC_AADD and atomic type attribute.
- Move to...
- * config/bpf/atomic.md: ...Here. New file.
- * config/bpf/constraints.md (t): New constraint for R0.
- * doc/invoke.texi (eBPF Options): Document -mv3-atomics.
-
-2023-07-26 Matthew Malcomson <matthew.malcomson@arm.com>
-
- * tree-vect-stmts.cc (get_group_load_store_type): Reformat
- comment.
-
-2023-07-26 Carl Love <cel@us.ibm.com>
-
- * config/rs6000/rs6000-builtins.def: Rename
- __builtin_altivec_vreplace_un_uv2di as __builtin_altivec_vreplace_un_udi
- __builtin_altivec_vreplace_un_uv4si as __builtin_altivec_vreplace_un_usi
- __builtin_altivec_vreplace_un_v2df as __builtin_altivec_vreplace_un_df
- __builtin_altivec_vreplace_un_v2di as __builtin_altivec_vreplace_un_di
- __builtin_altivec_vreplace_un_v4sf as __builtin_altivec_vreplace_un_sf
- __builtin_altivec_vreplace_un_v4si as __builtin_altivec_vreplace_un_si.
- Rename VREPLACE_UN_UV2DI as VREPLACE_UN_UDI, VREPLACE_UN_UV4SI as
- VREPLACE_UN_USI, VREPLACE_UN_V2DF as VREPLACE_UN_DF,
- VREPLACE_UN_V2DI as VREPLACE_UN_DI, VREPLACE_UN_V4SF as
- VREPLACE_UN_SF, VREPLACE_UN_V4SI as VREPLACE_UN_SI.
- Rename vreplace_un_v2di as vreplace_un_di, vreplace_un_v4si as
- vreplace_un_si, vreplace_un_v2df as vreplace_un_df,
- vreplace_un_v2di as vreplace_un_di, vreplace_un_v4sf as
- vreplace_un_sf, vreplace_un_v4si as vreplace_un_si.
- * config/rs6000/rs6000-c.cc (find_instance): Add case
- RS6000_OVLD_VEC_REPLACE_UN.
- * config/rs6000/rs6000-overload.def (__builtin_vec_replace_un):
- Fix first argument type. Rename VREPLACE_UN_UV4SI as
- VREPLACE_UN_USI, VREPLACE_UN_V4SI as VREPLACE_UN_SI,
- VREPLACE_UN_UV2DI as VREPLACE_UN_UDI, VREPLACE_UN_V2DI as
- VREPLACE_UN_DI, VREPLACE_UN_V4SF as VREPLACE_UN_SF,
- VREPLACE_UN_V2DF as VREPLACE_UN_DF.
- * config/rs6000/vsx.md (REPLACE_ELT): Rename the mode_iterator
- REPLACE_ELT_V for vector modes.
- (REPLACE_ELT): New scalar mode iterator.
- (REPLACE_ELT_char): Add scalar attributes.
- (vreplace_un_<mode>): Change iterator and mode attribute.
-
-2023-07-26 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/104940
- * Makefile.in (ANALYZER_OBJS): Add analyzer/symbol.o.
-
-2023-07-26 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/106081
- * tree-vect-slp.cc (vect_optimize_slp_pass::start_choosing_layouts):
- Assign layout -1 to splats.
-
-2023-07-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-mixed.h (class operator_cast): Add update_bitmask.
- * range-op.cc (operator_cast::update_bitmask): New.
- (operator_cast::fold_range): Call update_bitmask.
-
-2023-07-26 Li Xu <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Change
- scalar type to float16, eliminate warning.
- (vfloat16mf4x3_t): Ditto.
- (vfloat16mf4x4_t): Ditto.
- (vfloat16mf4x5_t): Ditto.
- (vfloat16mf4x6_t): Ditto.
- (vfloat16mf4x7_t): Ditto.
- (vfloat16mf4x8_t): Ditto.
- (vfloat16mf2x2_t): Ditto.
- (vfloat16mf2x3_t): Ditto.
- (vfloat16mf2x4_t): Ditto.
- (vfloat16mf2x5_t): Ditto.
- (vfloat16mf2x6_t): Ditto.
- (vfloat16mf2x7_t): Ditto.
- (vfloat16mf2x8_t): Ditto.
- (vfloat16m1x2_t): Ditto.
- (vfloat16m1x3_t): Ditto.
- (vfloat16m1x4_t): Ditto.
- (vfloat16m1x5_t): Ditto.
- (vfloat16m1x6_t): Ditto.
- (vfloat16m1x7_t): Ditto.
- (vfloat16m1x8_t): Ditto.
- (vfloat16m2x2_t): Ditto.
- (vfloat16m2x3_t): Ditto.
- (vfloat16m2x4_t): Ditto.
- (vfloat16m4x2_t): Ditto.
- * config/riscv/vector-iterators.md: add RVVM4x2DF in iterator V4T.
- * config/riscv/vector.md: add tuple mode in attr sew.
-
-2023-07-26 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/110762
- * config/i386/i386.md (plusminusmult): New code iterator.
- * config/i386/mmx.md (mmxdoublevecmode): New mode attribute.
- (movq_<mode>_to_sse): New expander.
- (<plusminusmult:insn>v2sf3): Macroize expander from addv2sf3,
- subv2sf3 and mulv2sf3 using plusminusmult code iterator. Rewrite
- as a wrapper around V4SFmode operation.
- (mmx_addv2sf3): Change operand 1 and operand 2 predicates to
- nonimmediate_operand.
- (*mmx_addv2sf3): Remove SSE alternatives. Change operand 1 and
- operand 2 predicates to nonimmediate_operand.
- (mmx_subv2sf3): Change operand 2 predicate to nonimmediate_operand.
- (mmx_subrv2sf3): Change operand 1 predicate to nonimmediate_operand.
- (*mmx_subv2sf3): Remove SSE alternatives. Change operand 1 and
- operand 2 predicates to nonimmediate_operand.
- (mmx_mulv2sf3): Change operand 1 and operand 2 predicates to
- nonimmediate_operand.
- (*mmx_mulv2sf3): Remove SSE alternatives. Change operand 1 and
- operand 2 predicates to nonimmediate_operand.
- (divv2sf3): Rewrite as a wrapper around V4SFmode operation.
- (<smaxmin:code>v2sf3): Ditto.
- (mmx_<smaxmin:code>v2sf3): Change operand 1 and operand 2
- predicates to nonimmediate_operand.
- (*mmx_<smaxmin:code>v2sf3): Remove SSE alternatives. Change
- operand 1 and operand 2 predicates to nonimmediate_operand.
- (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
- (sqrtv2sf2): Rewrite as a wrapper around V4SFmode operation.
- (*mmx_haddv2sf3_low): Ditto.
- (*mmx_hsubv2sf3_low): Ditto.
- (vec_addsubv2sf3): Ditto.
- (*mmx_maskcmpv2sf3_comm): Remove.
- (*mmx_maskcmpv2sf3): Remove.
- (vec_cmpv2sfv2si): Rewrite as a wrapper around V4SFmode operation.
- (vcond<V2FI:mode>v2sf): Ditto.
- (fmav2sf4): Ditto.
- (fmsv2sf4): Ditto.
- (fnmav2sf4): Ditto.
- (fnmsv2sf4): Ditto.
- (fix_truncv2sfv2si2): Ditto.
- (fixuns_truncv2sfv2si2): Ditto.
- (mmx_fix_truncv2sfv2si2): Remove SSE alternatives.
- Change operand 1 predicate to nonimmediate_operand.
- (floatv2siv2sf2): Rewrite as a wrapper around V4SFmode operation.
- (floatunsv2siv2sf2): Ditto.
- (mmx_floatv2siv2sf2): Remove SSE alternatives.
- Change operand 1 predicate to nonimmediate_operand.
- (nearbyintv2sf2): Rewrite as a wrapper around V4SFmode operation.
- (rintv2sf2): Ditto.
- (lrintv2sfv2si2): Ditto.
- (ceilv2sf2): Ditto.
- (lceilv2sfv2si2): Ditto.
- (floorv2sf2): Ditto.
- (lfloorv2sfv2si2): Ditto.
- (btruncv2sf2): Ditto.
- (roundv2sf2): Ditto.
- (lroundv2sfv2si2): Ditto.
- (*mmx_roundv2sf2): Remove.
-
-2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.md: Fix neg{SI,DI}2 insn.
-
-2023-07-26 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110799
- * tree-ssa-pre.cc (compute_avail): More thoroughly match
- up TBAA behavior of redundant loads.
-
-2023-07-26 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/110755
- * range-op-float.cc (frange_arithmetic): Change +0 result to -0
- for PLUS_EXPR or MINUS_EXPR if -frounding-math, inf is negative and
- it is exact op1 + (-op1) or op1 - op1.
-
-2023-07-26 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/110741
- * config/rs6000/vsx.md (define_insn xxeval): Correct vsx
- operands output with "x".
-
-2023-07-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op.cc (class operator_absu): Add update_bitmask.
- (operator_absu::update_bitmask): New.
-
-2023-07-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-mixed.h (class operator_abs): Add update_bitmask.
- * range-op.cc (operator_abs::update_bitmask): New.
-
-2023-07-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-mixed.h (class operator_bitwise_not): Add update_bitmask.
- * range-op.cc (operator_bitwise_not::update_bitmask): New.
-
-2023-07-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op.cc (update_known_bitmask): Handle unary operators.
-
-2023-07-26 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-ssa-ccp.cc (bit_value_unop): Initialize val when appropriate.
-
-2023-07-26 Jin Ma <jinma@linux.alibaba.com>
-
- * config/riscv/riscv.md: Likewise.
-
-2023-07-26 Jan Hubicka <jh@suse.cz>
-
- * profile-count.cc (profile_count::to_sreal_scale): Value is not know
- if we divide by zero.
-
-2023-07-25 David Faust <david.faust@oracle.com>
-
- * config/bpf/bpf.cc (bpf_print_operand_address): Don't print
- enclosing parentheses for pseudo-C dialect.
- * config/bpf/bpf.md (zero_exdendhidi2): Add parentheses around
- operands of pseudo-C dialect output templates where needed.
- (zero_extendqidi2): Likewise.
- (zero_extendsidi2): Likewise.
- (*mov<MM:mode>): Likewise.
-
-2023-07-25 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-ssa-ccp.cc (value_mask_to_min_max): Make static.
- (bit_value_mult_const): Same.
- (get_individual_bits): Same.
-
-2023-07-25 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/103605
- * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Gimple
- fold RS6000_BIF_XSMINDP and RS6000_BIF_XSMAXDP when fast-math is set.
- * config/rs6000/rs6000.md (FMINMAX): New int iterator.
- (minmax_op): New int attribute.
- (UNSPEC_FMAX, UNSPEC_FMIN): New unspecs.
- (f<minmax_op><mode>3): New pattern by UNSPEC_FMAX and UNSPEC_FMIN.
- * config/rs6000/rs6000-builtins.def (__builtin_vsx_xsmaxdp): Set
- pattern to fmaxdf3.
- (__builtin_vsx_xsmindp): Set pattern to fmindf3.
-
-2023-07-24 David Faust <david.faust@oracle.com>
-
- * config/bpf/bpf.md (nop): Add pseudo-c asm dialect template.
-
-2023-07-24 Drew Ross <drross@redhat.com>
- Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/109986
- * generic-match-head.cc (bitwise_equal_p): New macro.
- * gimple-match-head.cc (bitwise_equal_p): New macro.
- (gimple_nop_convert): Declare.
- (gimple_bitwise_equal_p): Helper for bitwise_equal_p.
- * match.pd ((~X | Y) ^ X -> ~(X & Y)): New simplification.
-
-2023-07-24 Jeff Law <jlaw@ventanamicro.com>
-
- * common/config/riscv/riscv-common.cc (riscv_subset_list::add): Use
- single quote rather than backquote in diagnostic.
-
-2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- PR target/110783
- * config/bpf/bpf.opt: New command-line option -msdiv.
- * config/bpf/bpf.md: Conditionalize sdiv/smod on bpf_has_sdiv.
- * config/bpf/bpf.cc (bpf_option_override): Initialize
- bpf_has_sdiv.
- * doc/invoke.texi (eBPF Options): Document -msdiv.
-
-2023-07-24 Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_option_override): Spell out
- greater than and use cannot in diagnostic string.
-
-2023-07-24 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (_slp_tree::push_vec_def): Add.
- (_slp_tree::vec_stmts): Remove.
- (SLP_TREE_VEC_STMTS): Remove.
- * tree-vect-slp.cc (_slp_tree::push_vec_def): Define.
- (_slp_tree::_slp_tree): Adjust.
- (_slp_tree::~_slp_tree): Likewise.
- (vect_get_slp_vect_def): Simplify.
- (vect_get_slp_defs): Likewise.
- (vect_transform_slp_perm_load_1): Adjust.
- (vect_add_slp_permutation): Likewise.
- (vect_schedule_slp_node): Likewise.
- (vectorize_slp_instance_root_stmt): Likewise.
- (vect_schedule_scc): Likewise.
- * tree-vect-stmts.cc (vectorizable_bswap): Use push_vec_def.
- (vectorizable_call): Likewise.
- (vectorizable_call): Likewise.
- (vect_create_vectorized_demotion_stmts): Likewise.
- (vectorizable_conversion): Likewise.
- (vectorizable_assignment): Likewise.
- (vectorizable_shift): Likewise.
- (vectorizable_operation): Likewise.
- (vectorizable_load): Likewise.
- (vectorizable_condition): Likewise.
- (vectorizable_comparison): Likewise.
- * tree-vect-loop.cc (vect_create_epilog_for_reduction): Adjust.
- (vectorize_fold_left_reduction): Use push_vec_def.
- (vect_transform_reduction): Likewise.
- (vect_transform_cycle_phi): Likewise.
- (vectorizable_lc_phi): Likewise.
- (vectorizable_phi): Likewise.
- (vectorizable_recurr): Likewise.
- (vectorizable_induction): Likewise.
- (vectorizable_live_operation): Likewise.
-
-2023-07-24 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-loop.cc: Remove unused tree-vectorizer.h include.
-
-2023-07-24 Richard Biener <rguenther@suse.de>
-
- * config/i386/i386-builtins.cc: Remove tree-vectorizer.h include.
- * config/i386/i386-expand.cc: Likewise.
- * config/i386/i386-features.cc: Likewise.
- * config/i386/i386-options.cc: Likewise.
-
-2023-07-24 Robin Dapp <rdapp@ventanamicro.com>
-
- * tree-vect-stmts.cc (vectorizable_conversion): Handle
- more demotion/promotion for modifier == NONE.
-
-2023-07-24 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110787
- PR target/110790
- Revert patch.
- * config/i386/i386.md (extv<mode>): Use QImode for offsets.
- (extzv<mode>): Likewise.
- (insv<mode>): Likewise.
- (*testqi_ext_3): Likewise.
- (*btr<mode>_2): Likewise.
- (define_split): Likewise.
- (*btsq_imm): Likewise.
- (*btrq_imm): Likewise.
- (*btcq_imm): Likewise.
- (define_peephole2 x3): Likewise.
- (*bt<mode>): Likewise
- (*bt<mode>_mask): New define_insn_and_split.
- (*jcc_bt<mode>): Use QImode for offsets.
- (*jcc_bt<mode>_1): Delete obsolete pattern.
- (*jcc_bt<mode>_mask): Use QImode offsets.
- (*jcc_bt<mode>_mask_1): Likewise.
- (define_split): Likewise.
- (*bt<mode>_setcqi): Likewise.
- (*bt<mode>_setncqi): Likewise.
- (*bt<mode>_setnc<mode>): Likewise.
- (*bt<mode>_setncqi_2): Likewise.
- (*bt<mode>_setc<mode>_mask): New define_insn_and_split.
- (bmi2_bzhi_<mode>3): Use QImode offsets.
- (*bmi2_bzhi_<mode>3): Likewise.
- (*bmi2_bzhi_<mode>3_1): Likewise.
- (*bmi2_bzhi_<mode>3_1_ccz): Likewise.
- (@tbm_bextri_<mode>): Likewise.
-
-2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf-opts.h (enum bpf_kernel_version): Remove enum.
- * config/bpf/bpf.opt (mkernel): Remove option.
- * config/bpf/bpf.cc (bpf_target_macros): Do not define
- BPF_KERNEL_VERSION_CODE.
-
-2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- PR target/110786
- * config/bpf/bpf.opt (mcpu): Add ISA_V4 and make it the default.
- (mbswap): New option.
- * config/bpf/bpf-opts.h (enum bpf_isa_version): New value ISA_V4.
- * config/bpf/bpf.cc (bpf_option_override): Set bpf_has_bswap.
- * config/bpf/bpf.md: Use bswap instructions if available for
- bswap* insn, and fix constraint.
- * doc/invoke.texi (eBPF Options): Document -mcpu=v4 and -mbswap.
-
-2023-07-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (fold_left_plus_<mode>): New pattern.
- (mask_len_fold_left_plus_<mode>): Ditto.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- (enum reduction_type): Ditto.
- (expand_reduction): Add in-order reduction.
- * config/riscv/riscv-v.cc (emit_nonvlmax_fp_reduction_insn): New function.
- (expand_reduction): Add in-order reduction.
-
-2023-07-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-loop.cc (get_masked_reduction_fn): Add mask_len_fold_left_plus.
- (vectorize_fold_left_reduction): Ditto.
- (vectorizable_reduction): Ditto.
- (vect_transform_reduction): Ditto.
-
-2023-07-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110777
- * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_avail):
- Avoid propagating abnormals.
-
-2023-07-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110766
- * tree-scalar-evolution.cc
- (analyze_and_compute_bitwise_induction_effect): Check the PHI
- is defined in the loop header.
-
-2023-07-24 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/110740
- * tree-vect-loop.cc (vect_analyze_loop_costing): Do not vectorize a
- loop with a single scalar iteration.
-
-2023-07-24 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-shapes.cc
- (struct alu_frm_def): Take range check.
-
-2023-07-22 Vineet Gupta <vineetg@rivosinc.com>
-
- PR target/110748
- * config/riscv/predicates.md (const_0_operand): Add back
- const_double.
-
-2023-07-22 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_expand_move): Disable the
- 64-bit insertions into TImode optimizations with -O0, unless
- the function has the "naked" attribute (for PR target/110533).
-
-2023-07-22 Andrew Pinski <apinski@marvell.com>
-
- PR target/110778
- * rtl.h (extended_count): Change last argument type
- to bool.
-
-2023-07-22 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386.md (extv<mode>): Use QImode for offsets.
- (extzv<mode>): Likewise.
- (insv<mode>): Likewise.
- (*testqi_ext_3): Likewise.
- (*btr<mode>_2): Likewise.
- (define_split): Likewise.
- (*btsq_imm): Likewise.
- (*btrq_imm): Likewise.
- (*btcq_imm): Likewise.
- (define_peephole2 x3): Likewise.
- (*bt<mode>): Likewise
- (*bt<mode>_mask): New define_insn_and_split.
- (*jcc_bt<mode>): Use QImode for offsets.
- (*jcc_bt<mode>_1): Delete obsolete pattern.
- (*jcc_bt<mode>_mask): Use QImode offsets.
- (*jcc_bt<mode>_mask_1): Likewise.
- (define_split): Likewise.
- (*bt<mode>_setcqi): Likewise.
- (*bt<mode>_setncqi): Likewise.
- (*bt<mode>_setnc<mode>): Likewise.
- (*bt<mode>_setncqi_2): Likewise.
- (*bt<mode>_setc<mode>_mask): New define_insn_and_split.
- (bmi2_bzhi_<mode>3): Use QImode offsets.
- (*bmi2_bzhi_<mode>3): Likewise.
- (*bmi2_bzhi_<mode>3_1): Likewise.
- (*bmi2_bzhi_<mode>3_1_ccz): Likewise.
- (@tbm_bextri_<mode>): Likewise.
-
-2023-07-22 Jeff Law <jlaw@ventanamicro.com>
-
- * config/bfin/bfin.md (ones): Fix length computation.
-
-2023-07-22 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-eliminations.cc (update_reg_eliminate): Fix the assert.
- (lra_update_fp2sp_elimination): Use HARD_FRAME_POINTER_REGNUM
- instead of FRAME_POINTER_REGNUM to spill pseudos.
-
-2023-07-21 Roger Sayle <roger@nextmovesoftware.com>
- Richard Biener <rguenther@suse.de>
-
- PR c/110699
- * gimplify.cc (gimplify_compound_lval): If the array's type
- is error_mark_node then return GS_ERROR.
-
-2023-07-21 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- PR target/110770
- * config/bpf/bpf.opt: Added option -masm=<dialect>.
- * config/bpf/bpf-opts.h (enum bpf_asm_dialect): New type.
- * config/bpf/bpf.cc (bpf_print_register): New function.
- (bpf_print_register): Support pseudo-c syntax for registers.
- (bpf_print_operand_address): Likewise.
- * config/bpf/bpf.h (ASM_SPEC): handle -msasm.
- (ASSEMBLER_DIALECT): Define.
- * config/bpf/bpf.md: Added pseudo-c templates.
- * doc/invoke.texi (-masm=): New eBPF option item.
-
-2023-07-21 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf.md: fixed template for neg instruction.
-
-2023-07-21 Jan Hubicka <jh@suse.cz>
-
- PR target/110727
- * tree-vect-loop.cc (scale_profile_for_vect_loop): Avoid scaling flat
- profiles by vectorization factor.
- (vect_transform_loop): Check for flat profiles.
-
-2023-07-21 Jan Hubicka <jh@suse.cz>
-
- * cfgloop.h (maybe_flat_loop_profile): Declare
- * cfgloopanal.cc (maybe_flat_loop_profile): New function.
- * tree-cfg.cc (print_loop_info): Print info about flat profiles.
-
-2023-07-21 Jan Hubicka <jh@suse.cz>
-
- * cfgloop.cc (get_estimated_loop_iterations): Use sreal::to_nearest_int
- * cfgloopanal.cc (expected_loop_iterations_unbounded): Likewise.
- * predict.cc (estimate_bb_frequencies): Likewise.
- * profile.cc (branch_prob): Likewise.
- * tree-ssa-loop-niter.cc (estimate_numbers_of_iterations): Likewise
-
-2023-07-21 Iain Sandoe <iain@sandoe.co.uk>
-
- * config.in: Regenerate.
- * config/darwin.h (DARWIN_LD_DEMANGLE): New.
- (LINK_COMMAND_SPEC_A): Add demangle handling.
- * configure: Regenerate.
- * configure.ac: Detect linker support for '-demangle'.
-
-2023-07-21 Jan Hubicka <jh@suse.cz>
-
- * sreal.cc (sreal::to_nearest_int): New.
- (sreal_verify_basics): Verify also to_nearest_int.
- (verify_aritmetics): Likewise.
- (sreal_verify_conversions): New.
- (sreal_cc_tests): Call sreal_verify_conversions.
- * sreal.h: (sreal::to_nearest_int): Declare
-
-2023-07-21 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-ch.cc (enum ch_decision): New enum.
- (should_duplicate_loop_header_p): Return info on profitability.
- (do_while_loop_p): Watch for constant conditionals.
- (update_profile_after_ch): Do not sanity check that all
- static exits are taken.
- (ch_base::copy_headers): Run on all loops.
- (pass_ch::process_loop_p): Improve heuristics by handling also
- do_while loop and duplicating shortest sequence containing all
- winning blocks.
-
-2023-07-21 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-niter.cc (finite_loop_p): Reorder to do cheap
- tests first; update finite_p flag.
-
-2023-07-21 Jan Hubicka <jh@suse.cz>
-
- * cfgloop.cc (flow_loop_dump): Use print_loop_info.
- * cfgloop.h (print_loop_info): Declare.
- * tree-cfg.cc (print_loop_info): Break out from ...; add
- printing of missing fields and profile
- (print_loop): ... here.
-
-2023-07-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_gather_scatter): Remove redundant variables.
-
-2023-07-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-stmts.cc (check_load_store_for_partial_vectors): Change condition order.
- (vectorizable_operation): Ditto.
-
-2023-07-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Align order of mask and len.
- * config/riscv/riscv-v.cc (expand_load_store): Ditto.
- (expand_gather_scatter): Ditto.
- * doc/md.texi: Ditto.
- * internal-fn.cc (add_len_and_mask_args): Ditto.
- (add_mask_and_len_args): Ditto.
- (expand_partial_load_optab_fn): Ditto.
- (expand_partial_store_optab_fn): Ditto.
- (expand_scatter_store_optab_fn): Ditto.
- (expand_gather_load_optab_fn): Ditto.
- (internal_fn_len_index): Ditto.
- (internal_fn_mask_index): Ditto.
- (internal_len_load_store_bias): Ditto.
- * tree-vect-stmts.cc (vectorizable_store): Ditto.
- (vectorizable_load): Ditto.
-
-2023-07-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (len_maskload<mode><vm>): Change LEN_MASK into MASK_LEN.
- (mask_len_load<mode><vm>): Ditto.
- (len_maskstore<mode><vm>): Ditto.
- (mask_len_store<mode><vm>): Ditto.
- (len_mask_gather_load<RATIO64:mode><RATIO64I:mode>): Ditto.
- (mask_len_gather_load<RATIO64:mode><RATIO64I:mode>): Ditto.
- (len_mask_gather_load<RATIO32:mode><RATIO32I:mode>): Ditto.
- (mask_len_gather_load<RATIO32:mode><RATIO32I:mode>): Ditto.
- (len_mask_gather_load<RATIO16:mode><RATIO16I:mode>): Ditto.
- (mask_len_gather_load<RATIO16:mode><RATIO16I:mode>): Ditto.
- (len_mask_gather_load<RATIO8:mode><RATIO8I:mode>): Ditto.
- (mask_len_gather_load<RATIO8:mode><RATIO8I:mode>): Ditto.
- (len_mask_gather_load<RATIO4:mode><RATIO4I:mode>): Ditto.
- (mask_len_gather_load<RATIO4:mode><RATIO4I:mode>): Ditto.
- (len_mask_gather_load<RATIO2:mode><RATIO2I:mode>): Ditto.
- (mask_len_gather_load<RATIO2:mode><RATIO2I:mode>): Ditto.
- (len_mask_gather_load<RATIO1:mode><RATIO1:mode>): Ditto.
- (mask_len_gather_load<RATIO1:mode><RATIO1:mode>): Ditto.
- (len_mask_scatter_store<RATIO64:mode><RATIO64I:mode>): Ditto.
- (mask_len_scatter_store<RATIO64:mode><RATIO64I:mode>): Ditto.
- (len_mask_scatter_store<RATIO32:mode><RATIO32I:mode>): Ditto.
- (mask_len_scatter_store<RATIO32:mode><RATIO32I:mode>): Ditto.
- (len_mask_scatter_store<RATIO16:mode><RATIO16I:mode>): Ditto.
- (mask_len_scatter_store<RATIO16:mode><RATIO16I:mode>): Ditto.
- (len_mask_scatter_store<RATIO8:mode><RATIO8I:mode>): Ditto.
- (mask_len_scatter_store<RATIO8:mode><RATIO8I:mode>): Ditto.
- (len_mask_scatter_store<RATIO4:mode><RATIO4I:mode>): Ditto.
- (mask_len_scatter_store<RATIO4:mode><RATIO4I:mode>): Ditto.
- (len_mask_scatter_store<RATIO2:mode><RATIO2I:mode>): Ditto.
- (mask_len_scatter_store<RATIO2:mode><RATIO2I:mode>): Ditto.
- (len_mask_scatter_store<RATIO1:mode><RATIO1:mode>): Ditto.
- (mask_len_scatter_store<RATIO1:mode><RATIO1:mode>): Ditto.
- * doc/md.texi: Ditto.
- * genopinit.cc (main): Ditto.
- (CMP_NAME): Ditto. Ditto.
- * gimple-fold.cc (arith_overflowed_p): Ditto.
- (gimple_fold_partial_load_store_mem_ref): Ditto.
- (gimple_fold_call): Ditto.
- * internal-fn.cc (len_maskload_direct): Ditto.
- (mask_len_load_direct): Ditto.
- (len_maskstore_direct): Ditto.
- (mask_len_store_direct): Ditto.
- (expand_call_mem_ref): Ditto.
- (expand_len_maskload_optab_fn): Ditto.
- (expand_mask_len_load_optab_fn): Ditto.
- (expand_len_maskstore_optab_fn): Ditto.
- (expand_mask_len_store_optab_fn): Ditto.
- (direct_len_maskload_optab_supported_p): Ditto.
- (direct_mask_len_load_optab_supported_p): Ditto.
- (direct_len_maskstore_optab_supported_p): Ditto.
- (direct_mask_len_store_optab_supported_p): Ditto.
- (internal_load_fn_p): Ditto.
- (internal_store_fn_p): Ditto.
- (internal_gather_scatter_fn_p): Ditto.
- (internal_fn_len_index): Ditto.
- (internal_fn_mask_index): Ditto.
- (internal_fn_stored_value_index): Ditto.
- (internal_len_load_store_bias): Ditto.
- * internal-fn.def (LEN_MASK_GATHER_LOAD): Ditto.
- (MASK_LEN_GATHER_LOAD): Ditto.
- (LEN_MASK_LOAD): Ditto.
- (MASK_LEN_LOAD): Ditto.
- (LEN_MASK_SCATTER_STORE): Ditto.
- (MASK_LEN_SCATTER_STORE): Ditto.
- (LEN_MASK_STORE): Ditto.
- (MASK_LEN_STORE): Ditto.
- * optabs-query.cc (supports_vec_gather_load_p): Ditto.
- (supports_vec_scatter_store_p): Ditto.
- * optabs-tree.cc (target_supports_mask_load_store_p): Ditto.
- (target_supports_len_load_store_p): Ditto.
- * optabs.def (OPTAB_CD): Ditto.
- * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): Ditto.
- (call_may_clobber_ref_p_1): Ditto.
- * tree-ssa-dse.cc (initialize_ao_ref_for_dse): Ditto.
- (dse_optimize_stmt): Ditto.
- * tree-ssa-loop-ivopts.cc (get_mem_type_for_internal_fn): Ditto.
- (get_alias_ptr_type_for_ptr_address): Ditto.
- * tree-vect-data-refs.cc (vect_gather_scatter_fn_p): Ditto.
- * tree-vect-patterns.cc (vect_recog_gather_scatter_pattern): Ditto.
- * tree-vect-stmts.cc (check_load_store_for_partial_vectors): Ditto.
- (vect_get_strided_load_store_ops): Ditto.
- (vectorizable_store): Ditto.
- (vectorizable_load): Ditto.
-
-2023-07-21 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386.opt: Fix a typo.
-
-2023-07-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/88540
- * tree-ssa-phiopt.cc (minmax_replacement): Do not give up
- with NaNs but handle the simple case by if-converting to a
- COND_EXPR.
-
-2023-07-21 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (minmax<minmax<a,b>,a>->minmax<a,b>): New
- transformation.
-
-2023-07-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110742
- * tree-vect-slp.cc (vect_optimize_slp_pass::get_result_with_layout):
- Do not materialize an edge permutation in an external node with
- vector defs.
- (vect_slp_analyze_node_operations_1): Guard purely internal
- nodes better.
-
-2023-07-21 Jan Hubicka <jh@suse.cz>
-
- * cfgloop.cc: Include sreal.h.
- (flow_loop_dump): Dump sreal iteration exsitmate.
- (get_estimated_loop_iterations): Update.
- * cfgloop.h (expected_loop_iterations_by_profile): Declare.
- * cfgloopanal.cc (expected_loop_iterations_by_profile): New function.
- (expected_loop_iterations_unbounded): Use new API.
- * cfgloopmanip.cc (scale_loop_profile): Use
- expected_loop_iterations_by_profile
- * predict.cc (pass_profile::execute): Likewise.
- * profile.cc (branch_prob): Likewise.
- * tree-ssa-loop-niter.cc: Include sreal.h.
- (estimate_numbers_of_iterations): Likewise
-
-2023-07-21 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/110744
- * tree-ssa-sccvn.cc (vn_reference_lookup_3): Correct the index of bias
- operand for ifn IFN_LEN_STORE.
-
-2023-07-21 liuhongt <hongtao.liu@intel.com>
-
- PR target/89701
- * common.opt: (fcf-protection=): Add EnumSet attribute to
- support combination of params.
-
-2023-07-21 David Malcolm <dmalcolm@redhat.com>
-
- PR middle-end/110612
- * text-art/table.cc (table_geometry::table_geometry): Drop m_table
- field.
- (table_geometry::table_x_to_canvas_x): Add cast to comparison.
- (table_geometry::table_y_to_canvas_y): Likewise.
- * text-art/table.h (table_geometry::m_table): Drop unused field.
- * text-art/widget.h (wrapper_widget::update_child_alloc_rects):
- Add "override".
-
-2023-07-20 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/110717
- * config/i386/i386-features.cc
- (general_scalar_chain::compute_convert_gain): Calculate gain
- for extend higpart case.
- (general_scalar_chain::convert_op): Handle
- ASHIFTRT/ASHIFT combined RTX.
- (general_scalar_to_vector_candidate_p): Enable ASHIFTRT for
- SImode for SSE2 targets. Handle ASHIFTRT/ASHIFT combined RTX.
- * config/i386/i386.md (*extend<dwi>2_doubleword_highpart):
- New define_insn_and_split pattern.
- (*extendv2di2_highpart_stv): Ditto.
-
-2023-07-20 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-constraints.cc (simplify_operand_subreg): Check frame pointer
- simplification.
-
-2023-07-20 Andrew Pinski <apinski@marvell.com>
-
- * combine.cc (dump_combine_stats): Remove.
- (dump_combine_total_stats): Remove.
- (total_attempts, total_merges, total_extras,
- total_successes): Remove.
- (combine_instructions): Don't increment total stats
- instead use statistics_counter_event.
- * dumpfile.cc (print_combine_total_stats): Remove.
- * dumpfile.h (print_combine_total_stats): Remove.
- (dump_combine_total_stats): Remove.
- * passes.cc (finish_optimization_passes):
- Don't call print_combine_total_stats.
- * rtl.h (dump_combine_total_stats): Remove.
- (dump_combine_stats): Remove.
-
-2023-07-20 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-ch.cc (should_duplicate_loop_header_p): Use BIT instead of TRUTH
- logical ops.
-
-2023-07-20 Martin Jambor <mjambor@suse.cz>
-
- * doc/invoke.texi (analyzer-text-art-string-ellipsis-threshold): New.
- (analyzer-text-art-ideal-canvas-width): Likewise.
- (analyzer-text-art-string-ellipsis-head-len): Likewise.
- (analyzer-text-art-string-ellipsis-tail-len): Likewise.
-
-2023-07-20 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-stmts.cc (check_load_store_for_partial_vectors):
- Refine code structure.
-
-2023-07-20 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-ch.cc (edge_range_query): Rename to ...
- (get_range_query): ... this one; do
- (static_loop_exit): Add query parametr, turn ranger to reference.
- (loop_static_stmt_p): New function.
- (loop_static_op_p): New function.
- (loop_iv_derived_p): Remove.
- (loop_combined_static_and_iv_p): New function.
- (should_duplicate_loop_header_p): Discover combined onditionals;
- do not track iv derived; improve dumps.
- (pass_ch::execute): Fix whitespace.
-
-2023-07-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110204
- * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_avail):
- Look through copies generated by PRE.
-
-2023-07-20 Matthew Malcomson <matthew.malcomson@arm.com>
-
- * tree-vect-stmts.cc (get_group_load_store_type): Account for
- `gap` when checking if need to peel twice.
-
-2023-07-20 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-
- PR middle-end/77928
- * doc/extend.texi: Document iseqsig builtin.
- * builtins.cc (fold_builtin_iseqsig): New function.
- (fold_builtin_2): Handle BUILT_IN_ISEQSIG.
- (is_inexpensive_builtin): Handle BUILT_IN_ISEQSIG.
- * builtins.def (BUILT_IN_ISEQSIG): New built-in.
-
-2023-07-20 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector.md: Fix incorrect match_operand.
-
-2023-07-20 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_expand_move): Don't call
- force_reg, to use SUBREG rather than create a new pseudo when
- inserting DFmode fields into TImode with insvti_{high,low}part.
- * config/i386/i386.md (*concat<mode><dwi>3_3): Split into two
- define_insn_and_split...
- (*concatditi3_3): 64-bit implementation. Provide alternative
- that allows register allocation to use SSE registers that is
- split into vec_concatv2di after reload.
- (*concatsidi3_3): 32-bit implementation.
-
-2023-07-20 Richard Biener <rguenther@suse.de>
-
- PR middle-end/61747
- * internal-fn.cc (expand_vec_cond_optab_fn): When the
- value operands are equal to the original comparison operands
- preserve that equality by re-using the comparison expansion.
- * optabs.cc (emit_conditional_move): When the value operands
- are equal to the comparison operands and would be forced to
- a register by prepare_cmp_insn do so earlier, preserving the
- equality.
-
-2023-07-20 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector.md: Align pattern format.
-
-2023-07-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * doc/invoke.texi: Remove AVX512VP2INTERSECT in
- Granite Rapids{, D} from documentation.
-
-2023-07-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md
- (len_mask_gather_load<VNX16_QHSD:mode><VNX16_QHSDI:mode>):
- Refactor RVV machine modes.
- (len_mask_gather_load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
- (len_mask_gather_load<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
- (len_mask_gather_load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
- (len_mask_gather_load<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
- (len_mask_gather_load<mode><mode>): Ditto.
- (len_mask_gather_load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
- (len_mask_scatter_store<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
- (len_mask_scatter_store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
- (len_mask_scatter_store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
- (len_mask_scatter_store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
- (len_mask_scatter_store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
- (len_mask_scatter_store<mode><mode>): Ditto.
- (len_mask_scatter_store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
- * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Ditto.
- (ADJUST_NUNITS): Ditto.
- (ADJUST_ALIGNMENT): Ditto.
- (ADJUST_BYTESIZE): Ditto.
- (ADJUST_PRECISION): Ditto.
- (RVV_MODES): Ditto.
- (RVV_WHOLE_MODES): Ditto.
- (RVV_FRACT_MODE): Ditto.
- (RVV_NF8_MODES): Ditto.
- (RVV_NF4_MODES): Ditto.
- (VECTOR_MODES_WITH_PREFIX): Ditto.
- (VECTOR_MODE_WITH_PREFIX): Ditto.
- (RVV_TUPLE_MODES): Ditto.
- (RVV_NF2_MODES): Ditto.
- (RVV_TUPLE_PARTIAL_MODES): Ditto.
- * config/riscv/riscv-v.cc (struct mode_vtype_group): Ditto.
- (ENTRY): Ditto.
- (TUPLE_ENTRY): Ditto.
- (get_vlmul): Ditto.
- (get_nf): Ditto.
- (get_ratio): Ditto.
- (preferred_simd_mode): Ditto.
- (autovectorize_vector_modes): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Ditto.
- * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Ditto.
- (vbool64_t): Ditto.
- (vbool32_t): Ditto.
- (vbool16_t): Ditto.
- (vbool8_t): Ditto.
- (vbool4_t): Ditto.
- (vbool2_t): Ditto.
- (vbool1_t): Ditto.
- (vint8mf8_t): Ditto.
- (vuint8mf8_t): Ditto.
- (vint8mf4_t): Ditto.
- (vuint8mf4_t): Ditto.
- (vint8mf2_t): Ditto.
- (vuint8mf2_t): Ditto.
- (vint8m1_t): Ditto.
- (vuint8m1_t): Ditto.
- (vint8m2_t): Ditto.
- (vuint8m2_t): Ditto.
- (vint8m4_t): Ditto.
- (vuint8m4_t): Ditto.
- (vint8m8_t): Ditto.
- (vuint8m8_t): Ditto.
- (vint16mf4_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vuint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vuint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vuint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vuint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vuint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vuint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vuint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vuint32m8_t): Ditto.
- (vint64m1_t): Ditto.
- (vuint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vuint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vuint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint64m8_t): Ditto.
- (vfloat16mf4_t): Ditto.
- (vfloat16mf2_t): Ditto.
- (vfloat16m1_t): Ditto.
- (vfloat16m2_t): Ditto.
- (vfloat16m4_t): Ditto.
- (vfloat16m8_t): Ditto.
- (vfloat32mf2_t): Ditto.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat32m8_t): Ditto.
- (vfloat64m1_t): Ditto.
- (vfloat64m2_t): Ditto.
- (vfloat64m4_t): Ditto.
- (vfloat64m8_t): Ditto.
- * config/riscv/riscv-vector-switch.def (ENTRY): Ditto.
- (TUPLE_ENTRY): Ditto.
- * config/riscv/riscv-vsetvl.cc (change_insn): Ditto.
- * config/riscv/riscv.cc (riscv_valid_lo_sum_p): Ditto.
- (riscv_v_adjust_nunits): Ditto.
- (riscv_v_adjust_bytesize): Ditto.
- (riscv_v_adjust_precision): Ditto.
- (riscv_convert_vector_bits): Ditto.
- * config/riscv/riscv.h (riscv_v_adjust_nunits): Ditto.
- * config/riscv/riscv.md: Ditto.
- * config/riscv/vector-iterators.md: Ditto.
- * config/riscv/vector.md
- (@pred_indexed_<order>store<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
- (@pred_indexed_<order>store<VNX128_Q:mode><VNX128_Q:mode>): Ditto.
- (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto.
- (@pred_indexed_<order>load<V1T:mode><VNX1_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto.
- (@pred_indexed_<order>load<V2T:mode><VNX2_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto.
- (@pred_indexed_<order>load<V4T:mode><VNX4_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto.
- (@pred_indexed_<order>load<V8T:mode><VNX8_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto.
- (@pred_indexed_<order>load<V16T:mode><VNX16_QHSI:mode>): Ditto.
- (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto.
- (@pred_indexed_<order>load<V32T:mode><VNX32_QHI:mode>): Ditto.
- (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto.
- (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto.
- (@pred_indexed_<order>store<V1T:mode><VNX1_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto.
- (@pred_indexed_<order>store<V2T:mode><VNX2_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto.
- (@pred_indexed_<order>store<V4T:mode><VNX4_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto.
- (@pred_indexed_<order>store<V8T:mode><VNX8_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto.
- (@pred_indexed_<order>store<V16T:mode><VNX16_QHSI:mode>): Ditto.
- (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto.
- (@pred_indexed_<order>store<V32T:mode><VNX32_QHI:mode>): Ditto.
- (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto.
-
-2023-07-19 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-int.h (lra_update_fp2sp_elimination): New prototype.
- (lra_asm_insn_error): New prototype.
- * lra-spills.cc (remove_pseudos): Add check for pseudo slot memory
- existence.
- (lra_spill): Call lra_update_fp2sp_elimination.
- * lra-eliminations.cc: Remove trailing spaces.
- (elimination_fp2sp_occured_p): New static flag.
- (lra_eliminate_regs_1): Set the flag up.
- (update_reg_eliminate): Modify the assert for stack to frame
- pointer elimination.
- (lra_update_fp2sp_elimination): New function.
- (lra_eliminate): Clear flag elimination_fp2sp_occured_p.
-
-2023-07-19 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * config/aarch64/aarch64.h (TARGET_MEMTAG): Remove armv8.5
- dependency.
- * config/aarch64/arm_acle.h: Remove unnecessary armv8.x
- dependencies from target pragmas.
- * config/aarch64/arm_fp16.h (target): Likewise.
- * config/aarch64/arm_neon.h (target): Likewise.
-
-2023-07-19 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110252
- * tree-ssa-phiopt.cc (class auto_flow_sensitive): New class.
- (auto_flow_sensitive::auto_flow_sensitive): New constructor.
- (auto_flow_sensitive::~auto_flow_sensitive): New deconstructor.
- (match_simplify_replacement): Temporarily
- remove the flow sensitive info on the two statements that might
- be moved.
-
-2023-07-19 Andrew Pinski <apinski@marvell.com>
-
- * gimple-fold.cc (fosa_unwind): Replace `vrange_storage *`
- with flow_sensitive_info_storage.
- (follow_outer_ssa_edges): Update how to save off the flow
- sensitive info.
- (maybe_fold_comparisons_from_match_pd): Update restoring
- of flow sensitive info.
- * tree-ssanames.cc (flow_sensitive_info_storage::save): New method.
- (flow_sensitive_info_storage::restore): New method.
- (flow_sensitive_info_storage::save_and_clear): New method.
- (flow_sensitive_info_storage::clear_storage): New method.
- * tree-ssanames.h (class flow_sensitive_info_storage): New class.
-
-2023-07-19 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110726
- * match.pd ((a|b)&(a==b),a|(a==b),(a&b)|(a==b)):
- Add checks to make sure the type was one bit precision
- intergal type.
-
-2023-07-19 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * doc/md.texi: Add mask_len_fold_left_plus.
- * internal-fn.cc (mask_len_fold_left_direct): Ditto.
- (expand_mask_len_fold_left_optab_fn): Ditto.
- (direct_mask_len_fold_left_optab_supported_p): Ditto.
- * internal-fn.def (MASK_LEN_FOLD_LEFT_PLUS): Ditto.
- * optabs.def (OPTAB_D): Ditto.
-
-2023-07-19 Jakub Jelinek <jakub@redhat.com>
-
- * tree-switch-conversion.h (class bit_test_cluster): Fix comment typo.
-
-2023-07-19 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/110731
- * wide-int.cc (wi::divmod_internal): Always unpack dividend and
- divisor as UNSIGNED regardless of sgn.
-
-2023-07-19 Lehua Ding <lehua.ding@rivai.ai>
-
- * common/config/riscv/riscv-common.cc (riscv_supported_std_ext): Init.
- (standard_extensions_p): Add check.
- (riscv_subset_list::add): Just return NULL if it failed before.
- (riscv_subset_list::parse_std_ext): Continue parse when find a error
- (riscv_subset_list::parse): Just return NULL if it failed before.
- * config/riscv/riscv-subset.h (class riscv_subset_list): Add field.
-
-2023-07-19 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate):
- Use gen_vec_set_0.
- (ix86_expand_vector_extract): Use gen_vec_extract_lo /
- gen_vec_extract_hi.
- (expand_vec_perm_broadcast_1): Use gen_vec_interleave_high /
- gen_vec_interleave_low. Rename local variable.
-
-2023-07-19 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md (vec_dupv2df<mask_name>): Add new AVX512F
- alternative. Move AVX512VL part of condition to new "enabled"
- attribute.
-
-2023-07-19 liuhongt <hongtao.liu@intel.com>
-
- PR target/109504
- * config/i386/i386-builtins.cc
- (ix86_register_float16_builtin_type): Remove TARGET_SSE2.
- (ix86_register_bf16_builtin_type): Ditto.
- * config/i386/i386-c.cc (ix86_target_macros): When TARGET_SSE2
- isn't available, undef the macros which are used to check the
- backend support of the _Float16/__bf16 types when building
- libstdc++ and libgcc.
- * config/i386/i386.cc (construct_container): Issue errors for
- HFmode/BFmode when TARGET_SSE2 is not available.
- (function_value_32): Ditto.
- (ix86_scalar_mode_supported_p): Remove TARGET_SSE2 for HFmode/BFmode.
- (ix86_libgcc_floating_mode_supported_p): Ditto.
- (ix86_emit_support_tinfos): Adjust codes.
- (ix86_invalid_conversion): Return diagnostic message string
- when there's conversion from/to BF/HFmode w/o TARGET_SSE2.
- (ix86_invalid_unary_op): New function.
- (ix86_invalid_binary_op): Ditto.
- (TARGET_INVALID_UNARY_OP): Define.
- (TARGET_INVALID_BINARY_OP): Define.
- * config/i386/immintrin.h [__SSE2__]: Remove for fp16/bf16
- related instrinsics header files.
- * config/i386/i386.h (VALID_SSE2_TYPE_MODE): New macro.
-
-2023-07-18 Uros Bizjak <ubizjak@gmail.com>
-
- * dwarf2asm.cc: Change FALSE to false.
- * dwarf2cfi.cc (execute_dwarf2_frame): Change return type to void.
- * dwarf2out.cc (matches_main_base): Change return type from
- int to bool. Change "last_match" variable to bool.
- (dump_struct_debug): Change return type from int to bool.
- Change "matches" and "result" function arguments to bool.
- (is_pseudo_reg): Change return type from int to bool.
- (is_tagged_type): Ditto.
- (same_loc_p): Ditto.
- (same_dw_val_p): Change return type from int to bool and adjust
- function body accordingly.
- (same_attr_p): Ditto.
- (same_die_p): Ditto.
- (is_type_die): Ditto.
- (is_declaration_die): Ditto.
- (should_move_die_to_comdat): Ditto.
- (is_base_type): Ditto.
- (is_based_loc): Ditto.
- (local_scope_p): Ditto.
- (class_scope_p): Ditto.
- (class_or_namespace_scope_p): Ditto.
- (is_tagged_type): Ditto.
- (is_rust): Use void argument.
- (is_nested_in_subprogram): Change return type from int to bool.
- (contains_subprogram_definition): Ditto.
- (gen_struct_or_union_type_die): Change "nested", "complete"
- and "ns_decl" variables to bool.
- (is_naming_typedef_decl): Change FALSE to false.
-
-2023-07-18 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-ch.cc (edge_range_query): Take loop argument; be ready
- for queries not in headers.
- (static_loop_exit): Add basic blck parameter; update use of
- edge_range_query
- (should_duplicate_loop_header_p): Add ranger and static_exits
- parameter. Do not account statements that will be optimized
- out after duplicaiton in overall size. Add ranger query to
- find static exits.
- (update_profile_after_ch): Take static_exits has set instead of
- single eliminated_edge.
- (ch_base::copy_headers): Do all analysis in the first pass;
- remember invariant_exits and static_exits.
-
-2023-07-18 Jason Merrill <jason@redhat.com>
-
- * fold-const.cc (native_interpret_aggregate): Skip empty fields.
-
-2023-07-18 Gaius Mulley <gaiusmod2@gmail.com>
-
- * doc/gm2.texi (Semantic checking): Change example testwithptr
- to testnew6.
-
-2023-07-18 Richard Biener <rguenther@suse.de>
-
- PR middle-end/105715
- * gimple-isel.cc (gimple_expand_vec_exprs): Merge into...
- (pass_gimple_isel::execute): ... this. Duplicate
- comparison defs of COND_EXPRs.
-
-2023-07-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-selftests.cc (run_poly_int_selftests): Add more selftests.
- * config/riscv/riscv.cc (riscv_legitimize_poly_move): Dynamic adjust size of VLA vectors.
- (riscv_convert_vector_bits): Ditto.
-
-2023-07-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (vec_shl_insert_<mode>): New patterns.
- * config/riscv/riscv-v.cc (shuffle_compress_patterns): Fix bugs.
-
-2023-07-18 Juergen Christ <jchrist@linux.ibm.com>
-
- * config/s390/vx-builtins.md: New vsel pattern.
-
-2023-07-18 liuhongt <hongtao.liu@intel.com>
-
- PR target/110438
- * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>):
- Remove # from assemble output.
-
-2023-07-18 liuhongt <hongtao.liu@intel.com>
-
- PR target/110591
- * config/i386/sync.md (cmpccxadd_<mode>): Adjust the pattern
- to explicitly set FLAGS_REG like *cmp<mode>_1, also add extra
- 3 define_peephole2 after the pattern.
-
-2023-07-18 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * rtl-ssa/internals.inl: Fix when mode1 and mode2 are not ordred.
-
-2023-07-18 Pan Li <pan2.li@intel.com>
- Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (struct machine_function): Add new field.
- (riscv_static_frm_mode_p): New function.
- (riscv_emit_frm_mode_set): New function for emit FRM.
- (riscv_emit_mode_set): Extract function for FRM.
- (riscv_mode_needed): Fix the TODO.
- (riscv_mode_entry): Initial dynamic frm RTL.
- (riscv_mode_exit): Return DYN_EXIT.
- * config/riscv/riscv.md: Add rdfrm.
- * config/riscv/vector-iterators.md (unspecv): Add DYN_EXIT unspecv.
- * config/riscv/vector.md (frm_modee): Add new mode dyn_exit.
- (fsrm): Removed.
- (fsrmsi_backup): New pattern for swap.
- (fsrmsi_restore): New pattern for restore.
- (fsrmsi_restore_exit): New pattern for restore exit.
- (frrmsi): New pattern for backup.
-
-2023-07-17 Arsen Arsenović <arsen@aarsen.me>
-
- * doc/extend.texi: Add @cindex on __auto_type.
-
-2023-07-17 Uros Bizjak <ubizjak@gmail.com>
-
- * combine-stack-adj.cc (stack_memref_p): Change return type from
- int to bool and adjust function body accordingly.
- (rest_of_handle_stack_adjustments): Change return type to void.
-
-2023-07-17 Uros Bizjak <ubizjak@gmail.com>
-
- * combine.cc (struct reg_stat_type): Change last_set_invalid to bool.
- (cant_combine_insn_p): Change return type from int to bool and adjust
- function body accordingly.
- (can_combine_p): Ditto.
- (combinable_i3pat): Ditto. Change "i1_not_in_src" and "i0_not_in_src"
- function arguments from int to bool.
- (contains_muldiv): Change return type from int to bool and adjust
- function body accordingly.
- (try_combine): Ditto. Change "new_direct_jump" pointer function
- argument from int to bool. Change "substed_i2", "substed_i1",
- "substed_i0", "added_sets_0", "added_sets_1", "added_sets_2",
- "i2dest_in_i2src", "i1dest_in_i1src", "i2dest_in_i1src",
- "i0dest_in_i0src", "i1dest_in_i0src", "i2dest_in_i0src",
- "i2dest_killed", "i1dest_killed", "i0dest_killed", "i1_feeds_i2_n",
- "i0_feeds_i2_n", "i0_feeds_i1_n", "i3_subst_into_i2", "have_mult",
- "swap_i2i3", "split_i2i3" and "changed_i3_dest" variables
- from int to bool.
- (subst): Change "in_dest", "in_cond" and "unique_copy" function
- arguments from int to bool.
- (combine_simplify_rtx): Change "in_dest" and "in_cond" function
- arguments from int to bool.
- (make_extraction): Change "unsignedp", "in_dest" and "in_compare"
- function argument from int to bool.
- (force_int_to_mode): Change "just_select" function argument
- from int to bool. Change "next_select" variable to bool.
- (rtx_equal_for_field_assignment_p): Change return type from
- int to bool and adjust function body accordingly.
- (merge_outer_ops): Ditto. Change "pcomp_p" pointer function
- argument from int to bool.
- (get_last_value_validate): Change return type from int to bool
- and adjust function body accordingly.
- (reg_dead_at_p): Ditto.
- (reg_bitfield_target_p): Ditto.
- (combine_instructions): Ditto. Change "new_direct_jump"
- variable to bool.
- (can_combine_p): Change return type from int to bool
- and adjust function body accordingly.
- (likely_spilled_retval_p): Ditto.
- (can_change_dest_mode): Change "added_sets" function argument
- from int to bool.
- (find_split_point): Change "unsignedp" variable to bool.
- (simplify_if_then_else): Change "comparison_p" and "swapped"
- variables to bool.
- (simplify_set): Change "other_changed" variable to bool.
- (expand_compound_operation): Change "unsignedp" variable to bool.
- (force_to_mode): Change "just_select" function argument
- from int to bool. Change "next_select" variable to bool.
- (extended_count): Change "unsignedp" function argument to bool.
- (simplify_shift_const_1): Change "complement_p" variable to bool.
- (simplify_comparison): Change "changed" variable to bool.
- (rest_of_handle_combine): Change return type to void.
-
-2023-07-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR plugins/110610
- * Makefile.in (INTERNAL_FN_H): Add insn-opinit.h.
-
-2023-07-17 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
-
- * ira.cc (setup_reg_class_relations): Continue
- if regclass cl3 is hard_reg_set_empty_p.
-
-2023-07-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_option_override): Add sorry check.
-
-2023-07-17 Martin Jambor <mjambor@suse.cz>
-
- * tree-ssa-loop-ivcanon.cc (try_peel_loop): Remove unused variable
- entry_count.
-
-2023-07-17 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-ssa-ccp.cc (ccp_finalize): Export value/mask known bits.
-
-2023-07-17 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/110696
- * common/config/riscv/riscv-common.cc (riscv_subset_list::handle_implied_ext):
- recur add all implied extensions.
- (riscv_subset_list::check_implied_ext): Add new method.
- (riscv_subset_list::parse): Call checker check_implied_ext.
- * config/riscv/riscv-subset.h: Add new method.
-
-2023-07-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (reduc_plus_scal_<mode>): New pattern.
- (reduc_smax_scal_<mode>): Ditto.
- (reduc_umax_scal_<mode>): Ditto.
- (reduc_smin_scal_<mode>): Ditto.
- (reduc_umin_scal_<mode>): Ditto.
- (reduc_and_scal_<mode>): Ditto.
- (reduc_ior_scal_<mode>): Ditto.
- (reduc_xor_scal_<mode>): Ditto.
- * config/riscv/riscv-protos.h (enum insn_type): Add reduction.
- (expand_reduction): New function.
- * config/riscv/riscv-v.cc (emit_vlmax_reduction_insn): Ditto.
- (emit_vlmax_fp_reduction_insn): Ditto.
- (get_m1_mode): Ditto.
- (expand_cond_len_binop): Fix name.
- (expand_reduction): New function
- * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Fix VSETVL BUG.
- (validate_change_or_fail): New function.
- (change_insn): Fix VSETVL BUG.
- (change_vsetvl_insn): Ditto.
- (pass_vsetvl::backward_demand_fusion): Ditto.
- (pass_vsetvl::df_post_optimization): Ditto.
-
-2023-07-17 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-prop.cc (ipcp_update_bits): Export value/mask known bits.
-
-2023-07-17 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.cc (riscv_regno_ok_for_index_p):
- Remove parameter name from declaration of unused parameter.
-
-2023-07-17 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/110652
- * tree-vect-stmts.cc (vectorizable_load): Initialize new_temp as
- NULL_TREE.
-
-2023-07-17 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110669
- * tree-scalar-evolution.cc (analyze_and_compute_bitop_with_inv_effect):
- Check we matched a header PHI.
-
-2023-07-17 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-ssanames.cc (set_bitmask): New.
- * tree-ssanames.h (set_bitmask): New.
-
-2023-07-17 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (irange_bitmask::verify_mask): Mask need not be
- normalized.
- * value-range.h (irange_bitmask::union_): Normalize beforehand.
- (irange_bitmask::intersect): Same.
-
-2023-07-17 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/95923
- * match.pd ((a|b)&(a==b),a|(a==b),(a&b)|(a==b)): New transformation.
-
-2023-07-17 Roger Sayle <roger@nextmovesoftware.com>
-
- * tree-if-conv.cc (predicate_scalar_phi): Make the arguments
- to the std::sort comparison lambda function const.
-
-2023-07-17 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110666
- * match.pd (A NEEQ (A NEEQ CST)): Fix Outer EQ case.
-
-2023-07-17 Mo, Zewei <zewei.mo@intel.com>
-
- * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Lunar Lake,
- Arrow Lake and Arrow Lake S.
- * common/config/i386/i386-common.cc:
- (processor_name): Add arrowlake.
- (processor_alias_table): Add arrow lake, arrow lake s and lunar
- lake.
- * common/config/i386/i386-cpuinfo.h (enum processor_subtypes):
- Add INTEL_COREI7_ARROWLAKE and INTEL_COREI7_ARROWLAKE_S.
- * config.gcc: Add -march=arrowlake and -march=arrowlake-s.
- * config/i386/driver-i386.cc (host_detect_local_cpu): Handle
- arrowlake-s.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Add
- arrowlake.
- * config/i386/i386-options.cc (m_ARROWLAKE): New.
- (processor_cost_table): Add arrowlake.
- * config/i386/i386.h (enum processor_type):
- Add PROCESSOR_ARROWLAKE.
- * config/i386/x86-tune.def: Add m_ARROWLAKE.
- * doc/extend.texi: Add arrowlake and arrowlake-s.
- * doc/invoke.texi: Ditto.
-
-2023-07-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/sse.md (VI2_AVX2): Delete V32HI since we actually
- have the same iterator. Also renaming all the occurence to
- VI2_AVX2_AVX512BW.
- (usdot_prod<mode>): New define_expand.
- (udot_prod<mode>): Ditto.
-
-2023-07-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Detech SM4.
- * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET,
- OPTION_MASK_ISA2_SM4_UNSET): New.
- (OPTION_MASK_ISA2_AVX_UNSET): Add SM4.
- (ix86_handle_option): Handle -msm4.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_SM4.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- sm4.
- * config.gcc: Add sm4intrin.h.
- * config/i386/cpuid.h (bit_SM4): New.
- * config/i386/i386-builtin.def (BDESC): Add new builtins.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Define
- __SM4__.
- * config/i386/i386-isa.def (SM4): Add DEF_PTA(SM4).
- * config/i386/i386-options.cc (isa2_opts): Add -msm4.
- (ix86_valid_target_attribute_inner_p): Handle sm4.
- * config/i386/i386.opt: Add option -msm4.
- * config/i386/immintrin.h: Include sm4intrin.h
- * config/i386/sse.md (vsm4key4_<mode>): New define insn.
- (vsm4rnds4_<mode>): Ditto.
- * doc/extend.texi: Document sm4.
- * doc/invoke.texi: Document -msm4.
- * doc/sourcebuild.texi: Document target sm4.
- * config/i386/sm4intrin.h: New file.
-
-2023-07-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Detect SHA512.
- * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET,
- OPTION_MASK_ISA2_SHA512_UNSET): New.
- (OPTION_MASK_ISA2_AVX_UNSET): Add SHA512.
- (ix86_handle_option): Handle -msha512.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_SHA512.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- sha512.
- * config.gcc: Add sha512intrin.h.
- * config/i386/cpuid.h (bit_SHA512): New.
- * config/i386/i386-builtin-types.def:
- Add DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI).
- * config/i386/i386-builtin.def (BDESC): Add new builtins.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Define
- __SHA512__.
- * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle
- V4DI_FTYPE_V4DI_V4DI_V2DI and V4DI_FTYPE_V4DI_V2DI.
- * config/i386/i386-isa.def (SHA512): Add DEF_PTA(SHA512).
- * config/i386/i386-options.cc (isa2_opts): Add -msha512.
- (ix86_valid_target_attribute_inner_p): Handle sha512.
- * config/i386/i386.opt: Add option -msha512.
- * config/i386/immintrin.h: Include sha512intrin.h.
- * config/i386/sse.md (vsha512msg1): New define insn.
- (vsha512msg2): Ditto.
- (vsha512rnds2): Ditto.
- * doc/extend.texi: Document sha512.
- * doc/invoke.texi: Document -msha512.
- * doc/sourcebuild.texi: Document target sha512.
- * config/i386/sha512intrin.h: New file.
-
-2023-07-17 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Detect SM3.
- * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET,
- OPTION_MASK_ISA2_SM3_UNSET): New.
- (OPTION_MASK_ISA2_AVX_UNSET): Add SM3.
- (ix86_handle_option): Handle -msm3.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_SM3.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- SM3.
- * config.gcc: Add sm3intrin.h
- * config/i386/cpuid.h (bit_SM3): New.
- * config/i386/i386-builtin-types.def:
- Add DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT).
- * config/i386/i386-builtin.def (BDESC): Add new builtins.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Define
- __SM3__.
- * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle
- V4SI_FTYPE_V4SI_V4SI_V4SI_INT.
- * config/i386/i386-isa.def (SM3): Add DEF_PTA(SM3).
- * config/i386/i386-options.cc (isa2_opts): Add -msm3.
- (ix86_valid_target_attribute_inner_p): Handle sm3.
- * config/i386/i386.opt: Add option -msm3.
- * config/i386/immintrin.h: Include sm3intrin.h.
- * config/i386/sse.md (vsm3msg1): New define insn.
- (vsm3msg2): Ditto.
- (vsm3rnds2): Ditto.
- * doc/extend.texi: Document sm3.
- * doc/invoke.texi: Document -msm3.
- * doc/sourcebuild.texi: Document target sm3.
- * config/i386/sm3intrin.h: New file.
-
-2023-07-17 Kong Lingling <lingling.kong@intel.com>
- Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features): Detect
- avxvnniint16.
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA2_AVXVNNIINT16_SET): New.
- (OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto.
- (ix86_handle_option): Handle -mavxvnniint16.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_AVXVNNIINT16.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- avxvnniint16.
- * config.gcc: Add avxvnniint16.h.
- * config/i386/avxvnniint16intrin.h: New file.
- * config/i386/cpuid.h (bit_AVXVNNIINT16): New.
- * config/i386/i386-builtin.def: Add new builtins.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Define
- __AVXVNNIINT16__.
- * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint16.
- (ix86_valid_target_attribute_inner_p): Handle avxvnniint16intrin.h.
- * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT16).
- * config/i386/i386.opt: Add option -mavxvnniint16.
- * config/i386/immintrin.h: Include avxvnniint16.h.
- * config/i386/sse.md
- (vpdp<vpdpwprodtype>_<mode>): New define_insn.
- * doc/extend.texi: Document avxvnniint16.
- * doc/invoke.texi: Document -mavxvnniint16.
- * doc/sourcebuild.texi: Document target avxvnniint16.
-
-2023-07-16 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/110649
- * tree-vect-loop.cc (scale_profile_for_vect_loop): Rewrite.
- (vect_transform_loop): Move scale_profile_for_vect_loop after
- upper bound updates.
-
-2023-07-16 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/110649
- * tree-vect-loop.cc (optimize_mask_stores): Set correctly
- probability of the if-then-else construct.
-
-2023-07-16 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/110649
- * tree-ssa-loop-ivcanon.cc (try_peel_loop): Avoid double profile update.
-
-2023-07-15 Andrew Pinski <apinski@marvell.com>
-
- * doc/contrib.texi: Update my entry.
-
-2023-07-15 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa.md: Define constants R1_REGNUM, R19_REGNUM and
- R27_REGNUM.
- (tgd_load): Restrict to !TARGET_64BIT. Use register constants.
- (tld_load): Likewise.
- (tgd_load_pic): Change to expander.
- (tld_load_pic, tld_offset_load, tp_load): Likewise.
- (tie_load_pic, tle_load): Likewise.
- (tgd_load_picsi, tgd_load_picdi): New.
- (tld_load_picsi, tld_load_picdi): New.
- (tld_offset_load<P:mode>): New.
- (tp_load<P:mode>): New.
- (tie_load_picsi, tie_load_picdi): New.
- (tle_load<P:mode>): New.
-
-2023-07-14 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-base.cc (vcmlaq, vcmlaq_rot90)
- (vcmlaq_rot180, vcmlaq_rot270): New.
- * config/arm/arm-mve-builtins-base.def (vcmlaq, vcmlaq_rot90)
- (vcmlaq_rot180, vcmlaq_rot270): New.
- * config/arm/arm-mve-builtins-base.h: (vcmlaq, vcmlaq_rot90)
- (vcmlaq_rot180, vcmlaq_rot270): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vcmlaq,
- vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270.
- * config/arm/arm_mve.h (vcmlaq): Delete.
- (vcmlaq_rot180): Delete.
- (vcmlaq_rot270): Delete.
- (vcmlaq_rot90): Delete.
- (vcmlaq_m): Delete.
- (vcmlaq_rot180_m): Delete.
- (vcmlaq_rot270_m): Delete.
- (vcmlaq_rot90_m): Delete.
- (vcmlaq_f16): Delete.
- (vcmlaq_rot180_f16): Delete.
- (vcmlaq_rot270_f16): Delete.
- (vcmlaq_rot90_f16): Delete.
- (vcmlaq_f32): Delete.
- (vcmlaq_rot180_f32): Delete.
- (vcmlaq_rot270_f32): Delete.
- (vcmlaq_rot90_f32): Delete.
- (vcmlaq_m_f32): Delete.
- (vcmlaq_m_f16): Delete.
- (vcmlaq_rot180_m_f32): Delete.
- (vcmlaq_rot180_m_f16): Delete.
- (vcmlaq_rot270_m_f32): Delete.
- (vcmlaq_rot270_m_f16): Delete.
- (vcmlaq_rot90_m_f32): Delete.
- (vcmlaq_rot90_m_f16): Delete.
- (__arm_vcmlaq_f16): Delete.
- (__arm_vcmlaq_rot180_f16): Delete.
- (__arm_vcmlaq_rot270_f16): Delete.
- (__arm_vcmlaq_rot90_f16): Delete.
- (__arm_vcmlaq_f32): Delete.
- (__arm_vcmlaq_rot180_f32): Delete.
- (__arm_vcmlaq_rot270_f32): Delete.
- (__arm_vcmlaq_rot90_f32): Delete.
- (__arm_vcmlaq_m_f32): Delete.
- (__arm_vcmlaq_m_f16): Delete.
- (__arm_vcmlaq_rot180_m_f32): Delete.
- (__arm_vcmlaq_rot180_m_f16): Delete.
- (__arm_vcmlaq_rot270_m_f32): Delete.
- (__arm_vcmlaq_rot270_m_f16): Delete.
- (__arm_vcmlaq_rot90_m_f32): Delete.
- (__arm_vcmlaq_rot90_m_f16): Delete.
- (__arm_vcmlaq): Delete.
- (__arm_vcmlaq_rot180): Delete.
- (__arm_vcmlaq_rot270): Delete.
- (__arm_vcmlaq_rot90): Delete.
- (__arm_vcmlaq_m): Delete.
- (__arm_vcmlaq_rot180_m): Delete.
- (__arm_vcmlaq_rot270_m): Delete.
- (__arm_vcmlaq_rot90_m): Delete.
-
-2023-07-14 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm_mve_builtins.def (vcmlaq_rot90_f)
- (vcmlaq_rot270_f, vcmlaq_rot180_f, vcmlaq_f): Add "_f" suffix.
- * config/arm/iterators.md (MVE_VCMLAQ_M): New.
- (mve_insn): Add vcmla.
- (rot): Add VCMLAQ_M_F, VCMLAQ_ROT90_M_F, VCMLAQ_ROT180_M_F,
- VCMLAQ_ROT270_M_F.
- (mve_rot): Add VCMLAQ_M_F, VCMLAQ_ROT90_M_F, VCMLAQ_ROT180_M_F,
- VCMLAQ_ROT270_M_F.
- * config/arm/mve.md (mve_vcmlaq<mve_rot><mode>): Rename into ...
- (@mve_<mve_insn>q<mve_rot>_f<mode>): ... this.
- (mve_vcmlaq_m_f<mode>, mve_vcmlaq_rot180_m_f<mode>)
- (mve_vcmlaq_rot270_m_f<mode>, mve_vcmlaq_rot90_m_f<mode>): Merge
- into ...
- (@mve_<mve_insn>q<mve_rot>_m_f<mode>): ... this.
-
-2023-07-14 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-base.cc (vcmulq, vcmulq_rot90)
- (vcmulq_rot180, vcmulq_rot270): New.
- * config/arm/arm-mve-builtins-base.def (vcmulq, vcmulq_rot90)
- (vcmulq_rot180, vcmulq_rot270): New.
- * config/arm/arm-mve-builtins-base.h: (vcmulq, vcmulq_rot90)
- (vcmulq_rot180, vcmulq_rot270): New.
- * config/arm/arm_mve.h (vcmulq_rot90): Delete.
- (vcmulq_rot270): Delete.
- (vcmulq_rot180): Delete.
- (vcmulq): Delete.
- (vcmulq_m): Delete.
- (vcmulq_rot180_m): Delete.
- (vcmulq_rot270_m): Delete.
- (vcmulq_rot90_m): Delete.
- (vcmulq_x): Delete.
- (vcmulq_rot90_x): Delete.
- (vcmulq_rot180_x): Delete.
- (vcmulq_rot270_x): Delete.
- (vcmulq_rot90_f16): Delete.
- (vcmulq_rot270_f16): Delete.
- (vcmulq_rot180_f16): Delete.
- (vcmulq_f16): Delete.
- (vcmulq_rot90_f32): Delete.
- (vcmulq_rot270_f32): Delete.
- (vcmulq_rot180_f32): Delete.
- (vcmulq_f32): Delete.
- (vcmulq_m_f32): Delete.
- (vcmulq_m_f16): Delete.
- (vcmulq_rot180_m_f32): Delete.
- (vcmulq_rot180_m_f16): Delete.
- (vcmulq_rot270_m_f32): Delete.
- (vcmulq_rot270_m_f16): Delete.
- (vcmulq_rot90_m_f32): Delete.
- (vcmulq_rot90_m_f16): Delete.
- (vcmulq_x_f16): Delete.
- (vcmulq_x_f32): Delete.
- (vcmulq_rot90_x_f16): Delete.
- (vcmulq_rot90_x_f32): Delete.
- (vcmulq_rot180_x_f16): Delete.
- (vcmulq_rot180_x_f32): Delete.
- (vcmulq_rot270_x_f16): Delete.
- (vcmulq_rot270_x_f32): Delete.
- (__arm_vcmulq_rot90_f16): Delete.
- (__arm_vcmulq_rot270_f16): Delete.
- (__arm_vcmulq_rot180_f16): Delete.
- (__arm_vcmulq_f16): Delete.
- (__arm_vcmulq_rot90_f32): Delete.
- (__arm_vcmulq_rot270_f32): Delete.
- (__arm_vcmulq_rot180_f32): Delete.
- (__arm_vcmulq_f32): Delete.
- (__arm_vcmulq_m_f32): Delete.
- (__arm_vcmulq_m_f16): Delete.
- (__arm_vcmulq_rot180_m_f32): Delete.
- (__arm_vcmulq_rot180_m_f16): Delete.
- (__arm_vcmulq_rot270_m_f32): Delete.
- (__arm_vcmulq_rot270_m_f16): Delete.
- (__arm_vcmulq_rot90_m_f32): Delete.
- (__arm_vcmulq_rot90_m_f16): Delete.
- (__arm_vcmulq_x_f16): Delete.
- (__arm_vcmulq_x_f32): Delete.
- (__arm_vcmulq_rot90_x_f16): Delete.
- (__arm_vcmulq_rot90_x_f32): Delete.
- (__arm_vcmulq_rot180_x_f16): Delete.
- (__arm_vcmulq_rot180_x_f32): Delete.
- (__arm_vcmulq_rot270_x_f16): Delete.
- (__arm_vcmulq_rot270_x_f32): Delete.
- (__arm_vcmulq_rot90): Delete.
- (__arm_vcmulq_rot270): Delete.
- (__arm_vcmulq_rot180): Delete.
- (__arm_vcmulq): Delete.
- (__arm_vcmulq_m): Delete.
- (__arm_vcmulq_rot180_m): Delete.
- (__arm_vcmulq_rot270_m): Delete.
- (__arm_vcmulq_rot90_m): Delete.
- (__arm_vcmulq_x): Delete.
- (__arm_vcmulq_rot90_x): Delete.
- (__arm_vcmulq_rot180_x): Delete.
- (__arm_vcmulq_rot270_x): Delete.
-
-2023-07-14 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm_mve_builtins.def (vcmulq_rot90_f)
- (vcmulq_rot270_f, vcmulq_rot180_f, vcmulq_f): Add "_f" suffix.
- * config/arm/iterators.md (MVE_VCADDQ_VCMULQ)
- (MVE_VCADDQ_VCMULQ_M): New.
- (mve_insn): Add vcmul.
- (rot): Add VCMULQ_M_F, VCMULQ_ROT90_M_F, VCMULQ_ROT180_M_F,
- VCMULQ_ROT270_M_F.
- (VCMUL): Delete.
- (mve_rot): Add VCMULQ_M_F, VCMULQ_ROT90_M_F, VCMULQ_ROT180_M_F,
- VCMULQ_ROT270_M_F.
- * config/arm/mve.md (mve_vcmulq<mve_rot><mode>): Merge into
- @mve_<mve_insn>q<mve_rot>_f<mode>.
- (mve_vcmulq_m_f<mode>, mve_vcmulq_rot180_m_f<mode>)
- (mve_vcmulq_rot270_m_f<mode>, mve_vcmulq_rot90_m_f<mode>): Merge
- into @mve_<mve_insn>q<mve_rot>_m_f<mode>.
-
-2023-07-14 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-base.cc (vcaddq_rot90)
- (vcaddq_rot270, vhcaddq_rot90, vhcaddq_rot270): New.
- * config/arm/arm-mve-builtins-base.def (vcaddq_rot90)
- (vcaddq_rot270, vhcaddq_rot90, vhcaddq_rot270): New.
- * config/arm/arm-mve-builtins-base.h: (vcaddq_rot90)
- (vcaddq_rot270, vhcaddq_rot90, vhcaddq_rot270): New.
- * config/arm/arm-mve-builtins-functions.h (class
- unspec_mve_function_exact_insn_rot): New.
- * config/arm/arm_mve.h (vcaddq_rot90): Delete.
- (vcaddq_rot270): Delete.
- (vhcaddq_rot90): Delete.
- (vhcaddq_rot270): Delete.
- (vcaddq_rot270_m): Delete.
- (vcaddq_rot90_m): Delete.
- (vhcaddq_rot270_m): Delete.
- (vhcaddq_rot90_m): Delete.
- (vcaddq_rot90_x): Delete.
- (vcaddq_rot270_x): Delete.
- (vhcaddq_rot90_x): Delete.
- (vhcaddq_rot270_x): Delete.
- (vcaddq_rot90_u8): Delete.
- (vcaddq_rot270_u8): Delete.
- (vhcaddq_rot90_s8): Delete.
- (vhcaddq_rot270_s8): Delete.
- (vcaddq_rot90_s8): Delete.
- (vcaddq_rot270_s8): Delete.
- (vcaddq_rot90_u16): Delete.
- (vcaddq_rot270_u16): Delete.
- (vhcaddq_rot90_s16): Delete.
- (vhcaddq_rot270_s16): Delete.
- (vcaddq_rot90_s16): Delete.
- (vcaddq_rot270_s16): Delete.
- (vcaddq_rot90_u32): Delete.
- (vcaddq_rot270_u32): Delete.
- (vhcaddq_rot90_s32): Delete.
- (vhcaddq_rot270_s32): Delete.
- (vcaddq_rot90_s32): Delete.
- (vcaddq_rot270_s32): Delete.
- (vcaddq_rot90_f16): Delete.
- (vcaddq_rot270_f16): Delete.
- (vcaddq_rot90_f32): Delete.
- (vcaddq_rot270_f32): Delete.
- (vcaddq_rot270_m_s8): Delete.
- (vcaddq_rot270_m_s32): Delete.
- (vcaddq_rot270_m_s16): Delete.
- (vcaddq_rot270_m_u8): Delete.
- (vcaddq_rot270_m_u32): Delete.
- (vcaddq_rot270_m_u16): Delete.
- (vcaddq_rot90_m_s8): Delete.
- (vcaddq_rot90_m_s32): Delete.
- (vcaddq_rot90_m_s16): Delete.
- (vcaddq_rot90_m_u8): Delete.
- (vcaddq_rot90_m_u32): Delete.
- (vcaddq_rot90_m_u16): Delete.
- (vhcaddq_rot270_m_s8): Delete.
- (vhcaddq_rot270_m_s32): Delete.
- (vhcaddq_rot270_m_s16): Delete.
- (vhcaddq_rot90_m_s8): Delete.
- (vhcaddq_rot90_m_s32): Delete.
- (vhcaddq_rot90_m_s16): Delete.
- (vcaddq_rot270_m_f32): Delete.
- (vcaddq_rot270_m_f16): Delete.
- (vcaddq_rot90_m_f32): Delete.
- (vcaddq_rot90_m_f16): Delete.
- (vcaddq_rot90_x_s8): Delete.
- (vcaddq_rot90_x_s16): Delete.
- (vcaddq_rot90_x_s32): Delete.
- (vcaddq_rot90_x_u8): Delete.
- (vcaddq_rot90_x_u16): Delete.
- (vcaddq_rot90_x_u32): Delete.
- (vcaddq_rot270_x_s8): Delete.
- (vcaddq_rot270_x_s16): Delete.
- (vcaddq_rot270_x_s32): Delete.
- (vcaddq_rot270_x_u8): Delete.
- (vcaddq_rot270_x_u16): Delete.
- (vcaddq_rot270_x_u32): Delete.
- (vhcaddq_rot90_x_s8): Delete.
- (vhcaddq_rot90_x_s16): Delete.
- (vhcaddq_rot90_x_s32): Delete.
- (vhcaddq_rot270_x_s8): Delete.
- (vhcaddq_rot270_x_s16): Delete.
- (vhcaddq_rot270_x_s32): Delete.
- (vcaddq_rot90_x_f16): Delete.
- (vcaddq_rot90_x_f32): Delete.
- (vcaddq_rot270_x_f16): Delete.
- (vcaddq_rot270_x_f32): Delete.
- (__arm_vcaddq_rot90_u8): Delete.
- (__arm_vcaddq_rot270_u8): Delete.
- (__arm_vhcaddq_rot90_s8): Delete.
- (__arm_vhcaddq_rot270_s8): Delete.
- (__arm_vcaddq_rot90_s8): Delete.
- (__arm_vcaddq_rot270_s8): Delete.
- (__arm_vcaddq_rot90_u16): Delete.
- (__arm_vcaddq_rot270_u16): Delete.
- (__arm_vhcaddq_rot90_s16): Delete.
- (__arm_vhcaddq_rot270_s16): Delete.
- (__arm_vcaddq_rot90_s16): Delete.
- (__arm_vcaddq_rot270_s16): Delete.
- (__arm_vcaddq_rot90_u32): Delete.
- (__arm_vcaddq_rot270_u32): Delete.
- (__arm_vhcaddq_rot90_s32): Delete.
- (__arm_vhcaddq_rot270_s32): Delete.
- (__arm_vcaddq_rot90_s32): Delete.
- (__arm_vcaddq_rot270_s32): Delete.
- (__arm_vcaddq_rot270_m_s8): Delete.
- (__arm_vcaddq_rot270_m_s32): Delete.
- (__arm_vcaddq_rot270_m_s16): Delete.
- (__arm_vcaddq_rot270_m_u8): Delete.
- (__arm_vcaddq_rot270_m_u32): Delete.
- (__arm_vcaddq_rot270_m_u16): Delete.
- (__arm_vcaddq_rot90_m_s8): Delete.
- (__arm_vcaddq_rot90_m_s32): Delete.
- (__arm_vcaddq_rot90_m_s16): Delete.
- (__arm_vcaddq_rot90_m_u8): Delete.
- (__arm_vcaddq_rot90_m_u32): Delete.
- (__arm_vcaddq_rot90_m_u16): Delete.
- (__arm_vhcaddq_rot270_m_s8): Delete.
- (__arm_vhcaddq_rot270_m_s32): Delete.
- (__arm_vhcaddq_rot270_m_s16): Delete.
- (__arm_vhcaddq_rot90_m_s8): Delete.
- (__arm_vhcaddq_rot90_m_s32): Delete.
- (__arm_vhcaddq_rot90_m_s16): Delete.
- (__arm_vcaddq_rot90_x_s8): Delete.
- (__arm_vcaddq_rot90_x_s16): Delete.
- (__arm_vcaddq_rot90_x_s32): Delete.
- (__arm_vcaddq_rot90_x_u8): Delete.
- (__arm_vcaddq_rot90_x_u16): Delete.
- (__arm_vcaddq_rot90_x_u32): Delete.
- (__arm_vcaddq_rot270_x_s8): Delete.
- (__arm_vcaddq_rot270_x_s16): Delete.
- (__arm_vcaddq_rot270_x_s32): Delete.
- (__arm_vcaddq_rot270_x_u8): Delete.
- (__arm_vcaddq_rot270_x_u16): Delete.
- (__arm_vcaddq_rot270_x_u32): Delete.
- (__arm_vhcaddq_rot90_x_s8): Delete.
- (__arm_vhcaddq_rot90_x_s16): Delete.
- (__arm_vhcaddq_rot90_x_s32): Delete.
- (__arm_vhcaddq_rot270_x_s8): Delete.
- (__arm_vhcaddq_rot270_x_s16): Delete.
- (__arm_vhcaddq_rot270_x_s32): Delete.
- (__arm_vcaddq_rot90_f16): Delete.
- (__arm_vcaddq_rot270_f16): Delete.
- (__arm_vcaddq_rot90_f32): Delete.
- (__arm_vcaddq_rot270_f32): Delete.
- (__arm_vcaddq_rot270_m_f32): Delete.
- (__arm_vcaddq_rot270_m_f16): Delete.
- (__arm_vcaddq_rot90_m_f32): Delete.
- (__arm_vcaddq_rot90_m_f16): Delete.
- (__arm_vcaddq_rot90_x_f16): Delete.
- (__arm_vcaddq_rot90_x_f32): Delete.
- (__arm_vcaddq_rot270_x_f16): Delete.
- (__arm_vcaddq_rot270_x_f32): Delete.
- (__arm_vcaddq_rot90): Delete.
- (__arm_vcaddq_rot270): Delete.
- (__arm_vhcaddq_rot90): Delete.
- (__arm_vhcaddq_rot270): Delete.
- (__arm_vcaddq_rot270_m): Delete.
- (__arm_vcaddq_rot90_m): Delete.
- (__arm_vhcaddq_rot270_m): Delete.
- (__arm_vhcaddq_rot90_m): Delete.
- (__arm_vcaddq_rot90_x): Delete.
- (__arm_vcaddq_rot270_x): Delete.
- (__arm_vhcaddq_rot90_x): Delete.
- (__arm_vhcaddq_rot270_x): Delete.
-
-2023-07-14 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm_mve_builtins.def (vcaddq_rot90_, vcaddq_rot270_)
- (vcaddq_rot90_f, vcaddq_rot90_f): Add "_" or "_f" suffix.
- * config/arm/iterators.md (mve_insn): Add vcadd, vhcadd.
- (isu): Add UNSPEC_VCADD90, UNSPEC_VCADD270, VCADDQ_ROT270_M_U,
- VCADDQ_ROT270_M_S, VCADDQ_ROT90_M_U, VCADDQ_ROT90_M_S,
- VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S, VHCADDQ_ROT90_S,
- VHCADDQ_ROT270_S.
- (rot): Add VCADDQ_ROT90_M_F, VCADDQ_ROT90_M_S, VCADDQ_ROT90_M_U,
- VCADDQ_ROT270_M_F, VCADDQ_ROT270_M_S, VCADDQ_ROT270_M_U,
- VHCADDQ_ROT90_S, VHCADDQ_ROT270_S, VHCADDQ_ROT90_M_S,
- VHCADDQ_ROT270_M_S.
- (mve_rot): Add VCADDQ_ROT90_M_F, VCADDQ_ROT90_M_S,
- VCADDQ_ROT90_M_U, VCADDQ_ROT270_M_F, VCADDQ_ROT270_M_S,
- VCADDQ_ROT270_M_U, VHCADDQ_ROT90_S, VHCADDQ_ROT270_S,
- VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S.
- (supf): Add VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S,
- VHCADDQ_ROT90_S, VHCADDQ_ROT270_S, UNSPEC_VCADD90,
- UNSPEC_VCADD270.
- (VCADDQ_ROT270_M): Delete.
- (VCADDQ_M_F VxCADDQ VxCADDQ_M): New.
- (VCADDQ_ROT90_M): Delete.
- * config/arm/mve.md (mve_vcaddq<mve_rot><mode>)
- (mve_vhcaddq_rot270_s<mode>, mve_vhcaddq_rot90_s<mode>): Merge
- into ...
- (@mve_<mve_insn>q<mve_rot>_<supf><mode>): ... this.
- (mve_vcaddq<mve_rot><mode>): Rename into ...
- (@mve_<mve_insn>q<mve_rot>_f<mode>): ... this
- (mve_vcaddq_rot270_m_<supf><mode>)
- (mve_vcaddq_rot90_m_<supf><mode>, mve_vhcaddq_rot270_m_s<mode>)
- (mve_vhcaddq_rot90_m_s<mode>): Merge into ...
- (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): ... this.
- (mve_vcaddq_rot270_m_f<mode>, mve_vcaddq_rot90_m_f<mode>): Merge
- into ...
- (@mve_<mve_insn>q<mve_rot>_m_f<mode>): ... this.
-
-2023-07-14 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110588
- * config/i386/i386.md (*bt<mode>_setcqi): Prefer string form
- preparation statement over braces for a single statement.
- (*bt<mode>_setncqi): Likewise.
- (*bt<mode>_setncqi_2): New define_insn_and_split.
-
-2023-07-14 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_expand_move): Generalize special
- case inserting of 64-bit values into a TImode register, to handle
- both DImode and DFmode using either *insvti_lowpart_1
- or *isnvti_highpart_1.
-
-2023-07-14 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/110206
- * fwprop.cc (contains_paradoxical_subreg_p): Move to ...
- * rtlanal.cc (contains_paradoxical_subreg_p): ... here.
- * rtlanal.h (contains_paradoxical_subreg_p): Add prototype.
- * cprop.cc (try_replace_reg): Do not set REG_EQUAL note
- when the original source contains a paradoxical subreg.
-
-2023-07-14 Jan Hubicka <jh@suse.cz>
-
- * passes.cc (execute_function_todo): Remove
- TODO_rebuild_frequencies
- * passes.def: Add rebuild_frequencies pass.
- * predict.cc (estimate_bb_frequencies): Drop
- force parameter.
- (tree_estimate_probability): Update call of
- estimate_bb_frequencies.
- (rebuild_frequencies): Turn into a pass; verify CFG profile consistency
- first and do not rebuild if not necessary.
- (class pass_rebuild_frequencies): New.
- (make_pass_rebuild_frequencies): New.
- * profile-count.h: Add profile_count::very_large_p.
- * tree-inline.cc (optimize_inline_calls): Do not return
- TODO_rebuild_frequencies
- * tree-pass.h (TODO_rebuild_frequencies): Remove.
- (make_pass_rebuild_frequencies): Declare.
-
-2023-07-14 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (cond_len_fma<mode>): New pattern.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- (expand_cond_len_ternop): New function.
- * config/riscv/riscv-v.cc (emit_nonvlmax_fp_ternary_tu_insn): Ditto.
- (expand_cond_len_ternop): Ditto.
-
-2023-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- PR target/110657
- * config/bpf/bpf.md: Enable instruction scheduling.
-
-2023-07-14 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * tree-if-conv.cc (INCLUDE_ALGORITHM): Include.
- (struct bb_predicate): Add no_predicate_stmts.
- (set_bb_predicate): Increase predicate count.
- (set_bb_predicate_gimplified_stmts): Conditionally initialize
- no_predicate_stmts.
- (get_bb_num_predicate_stmts): New.
- (init_bb_predicate): Initialzie no_predicate_stmts.
- (release_bb_predicate): Cleanup no_predicate_stmts.
- (insert_gimplified_predicates): Preserve no_predicate_stmts.
-
-2023-07-14 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * tree-if-conv.cc (gen_simplified_condition,
- gen_phi_nest_statement): New.
- (gen_phi_arg_condition, predicate_scalar_phi): Use it.
-
-2023-07-14 Richard Biener <rguenther@suse.de>
-
- * gimple.h (gimple_phi_arg): New const overload.
- (gimple_phi_arg_def): Make gimple arg const.
- (gimple_phi_arg_def_from_edge): New inline function.
- * tree-phinodes.h (gimple_phi_arg_imm_use_ptr_from_edge):
- Likewise.
- * tree-ssa-operands.h (PHI_ARG_DEF_FROM_EDGE): Direct to
- new inline function.
- (PHI_ARG_DEF_PTR_FROM_EDGE): Likewise.
-
-2023-07-14 Monk Chiang <monk.chiang@sifive.com>
-
- * common/config/riscv/riscv-common.cc:
- (riscv_implied_info): Add zihintntl item.
- (riscv_ext_version_table): Ditto.
- (riscv_ext_flag_table): Ditto.
- * config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro.
- (TARGET_ZIHINTNTL): Ditto.
-
-2023-07-14 Die Li <lidie@eswincomputing.com>
-
- * config/riscv/riscv.md: Remove redundant portion in and<mode>3.
-
-2023-07-14 Oleg Endo <olegendo@gcc.gnu.org>
-
- PR target/101469
- * config/sh/sh.md (peephole2): Handle case where eliminated reg is also
- used by the address of the following memory operand.
-
-2023-07-13 Mikael Pettersson <mikpelinux@gmail.com>
-
- PR target/107841
- * config/pdp11/pdp11.cc (pdp11_expand_epilogue): Also
- deallocate alloca-only frame.
-
-2023-07-13 Iain Sandoe <iain@sandoe.co.uk>
-
- PR target/110624
- * config/darwin.h (DARWIN_PLATFORM_ID): New.
- (LINK_COMMAND_A): Use DARWIN_PLATFORM_ID to pass OS, OS version
- and SDK data to the static linker.
-
-2023-07-13 Carl Love <cel@us.ibm.com>
-
- * config/rs6000/rs6000-builtins.def (__builtin_set_fpscr_rn): Update
- built-in definition return type.
- * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Add check,
- define __SET_FPSCR_RN_RETURNS_FPSCR__ macro.
- * config/rs6000/rs6000.md (rs6000_set_fpscr_rn): Add return
- argument to return FPSCR fields.
- * doc/extend.texi (__builtin_set_fpscr_rn): Update description for
- the return value. Add description for
- __SET_FPSCR_RN_RETURNS_FPSCR__ macro.
-
-2023-07-13 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/106966
- * config/alpha/alpha.cc (alpha_emit_set_long_const):
- Always use DImode when constructing long const.
-
-2023-07-13 Uros Bizjak <ubizjak@gmail.com>
-
- * haifa-sched.cc: Change TRUE/FALSE to true/false.
- * ira.cc: Ditto.
- * lra-assigns.cc: Ditto.
- * lra-constraints.cc: Ditto.
- * sel-sched.cc: Ditto.
-
-2023-07-13 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110293
- PR tree-optimization/110539
- * match.pd: Expand the `x != (typeof x)(x == 0)`
- pattern to handle where the inner and outer comparsions
- are either `!=` or `==` and handle other constants
- than 0.
-
-2023-07-13 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR middle-end/109520
- * lra-int.h (lra_insn_recog_data): Add member asm_reloads_num.
- (lra_asm_insn_error): New prototype.
- * lra.cc: Include rtl_error.h.
- (lra_set_insn_recog_data): Initialize asm_reloads_num.
- (lra_asm_insn_error): New func whose code is taken from ...
- * lra-assigns.cc (lra_split_hard_reg_for): ... here. Use lra_asm_insn_error.
- * lra-constraints.cc (curr_insn_transform): Check reloads nummber for asm.
-
-2023-07-13 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * genmatch.cc (commutative_op): Add COND_LEN_*
- * internal-fn.cc (first_commutative_argument): Ditto.
- (CASE): Ditto.
- (get_unconditional_internal_fn): Ditto.
- (can_interpret_as_conditional_op_p): Ditto.
- (internal_fn_len_index): Ditto.
- * internal-fn.h (can_interpret_as_conditional_op_p): Ditt.
- * tree-ssa-math-opts.cc (convert_mult_to_fma_1): Ditto.
- (convert_mult_to_fma): Ditto.
- (math_opts_dom_walker::after_dom_children): Ditto.
-
-2023-07-13 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv.cc (vxrm_rtx): New static var.
- (frm_rtx): Ditto.
- (global_state_unknown_p): Removed.
- (riscv_entity_mode_after): Removed.
- (asm_insn_p): New function.
- (vxrm_unknown_p): New function for fixed-point.
- (riscv_vxrm_mode_after): Ditto.
- (frm_unknown_dynamic_p): New function for floating-point.
- (riscv_frm_mode_after): Ditto.
- (riscv_mode_after): Leverage new functions.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_model_load_cost): Remove.
- (vectorizable_load): Adjust the cost handling on VMAT_CONTIGUOUS without
- calling vect_model_load_cost.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_model_load_cost): Assert this function only
- handle memory_access_type VMAT_CONTIGUOUS, remove some
- VMAT_CONTIGUOUS_PERMUTE related handlings.
- (vectorizable_load): Adjust the cost handling on VMAT_CONTIGUOUS_PERMUTE
- without calling vect_model_load_cost.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_model_load_cost): Assert it won't get
- VMAT_CONTIGUOUS_REVERSE any more.
- (vectorizable_load): Adjust the costing handling on
- VMAT_CONTIGUOUS_REVERSE without calling vect_model_load_cost.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_load): Adjust the cost handling on
- VMAT_LOAD_STORE_LANES without calling vect_model_load_cost.
- (vectorizable_load): Remove VMAT_LOAD_STORE_LANES related handling and
- assert it will never get VMAT_LOAD_STORE_LANES.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_load): Adjust the cost handling on
- VMAT_GATHER_SCATTER without calling vect_model_load_cost.
- (vect_model_load_cost): Adjut the assertion on VMAT_GATHER_SCATTER,
- remove VMAT_GATHER_SCATTER related handlings and the related parameter
- gs_info.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_load): Adjust the cost handling
- on VMAT_ELEMENTWISE and VMAT_STRIDED_SLP without calling
- vect_model_load_cost.
- (vect_model_load_cost): Assert it won't get VMAT_ELEMENTWISE and
- VMAT_STRIDED_SLP any more, and remove their related handlings.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (hoist_defs_of_uses): Add one argument HOIST_P.
- (vectorizable_load): Adjust the handling on VMAT_INVARIANT to respect
- hoisting decision and without calling vect_model_load_cost.
- (vect_model_load_cost): Assert it won't get VMAT_INVARIANT any more
- and remove VMAT_INVARIANT related handlings.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vect_build_gather_load_calls): Add the handlings
- on costing with one extra argument cost_vec.
- (vectorizable_load): Adjust the call to vect_build_gather_load_calls.
- (vect_model_load_cost): Assert it won't get VMAT_GATHER_SCATTER with
- gs_info.decl set any more.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-stmts.cc (vectorizable_load): Move and duplicate the call
- to vect_model_load_cost down to some different transform paths
- according to the handlings of different vect_memory_access_types.
-
-2023-07-13 Kewen Lin <linkw@linux.ibm.com>
-
- * tree.h (wi::from_mpz): Hide from GENERATOR_FILE.
-
-2023-07-13 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md
- (len_mask_gather_load<VNX1_QHSD:mode><VNX1_QHSDI:mode>): New pattern.
- (len_mask_gather_load<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Ditto.
- (len_mask_gather_load<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
- (len_mask_gather_load<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
- (len_mask_gather_load<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
- (len_mask_gather_load<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
- (len_mask_gather_load<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
- (len_mask_gather_load<mode><mode>): Ditto.
- (len_mask_scatter_store<VNX1_QHSD:mode><VNX1_QHSDI:mode>): Ditto.
- (len_mask_scatter_store<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Ditto.
- (len_mask_scatter_store<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
- (len_mask_scatter_store<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
- (len_mask_scatter_store<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
- (len_mask_scatter_store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
- (len_mask_scatter_store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
- (len_mask_scatter_store<mode><mode>): Ditto.
- * config/riscv/predicates.md (const_1_operand): New predicate.
- (vector_gs_scale_operand_16): Ditto.
- (vector_gs_scale_operand_32): Ditto.
- (vector_gs_scale_operand_64): Ditto.
- (vector_gs_extension_operand): Ditto.
- (vector_gs_scale_operand_16_rv32): Ditto.
- (vector_gs_scale_operand_32_rv32): Ditto.
- * config/riscv/riscv-protos.h (enum insn_type): Add gather/scatter.
- (expand_gather_scatter): New function.
- * config/riscv/riscv-v.cc (gen_const_vector_dup): Add gather/scatter.
- (emit_vlmax_masked_store_insn): New function.
- (emit_nonvlmax_masked_store_insn): Ditto.
- (modulo_sel_indices): Ditto.
- (expand_vec_perm): Fix SLP for gather/scatter.
- (prepare_gather_scatter): New function.
- (expand_gather_scatter): Ditto.
- * config/riscv/riscv.cc (riscv_legitimize_move): Fix bug of
- (subreg:SI (DI CONST_POLY_INT)).
- * config/riscv/vector-iterators.md: Add gather/scatter.
- * config/riscv/vector.md (vec_duplicate<mode>): Use "@" instead.
- (@vec_duplicate<mode>): Ditto.
- (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>):
- Fix name.
- (@pred_indexed_<order>store<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
-
-2023-07-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (cond_len_<optab><mode>): New pattern.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- (expand_cond_len_binop): New function.
- * config/riscv/riscv-v.cc (emit_nonvlmax_tu_insn): Ditto.
- (emit_nonvlmax_fp_tu_insn): Ditto.
- (need_fp_rounding_p): Ditto.
- (expand_cond_len_binop): Ditto.
- * config/riscv/riscv.cc (riscv_preferred_else_value): Ditto.
- (TARGET_PREFERRED_ELSE_VALUE): New target hook.
-
-2023-07-12 Jan Hubicka <jh@suse.cz>
-
- * tree-cfg.cc (gimple_duplicate_sese_region): Rename to ...
- (gimple_duplicate_seme_region): ... this; break out profile updating
- code to ...
- * tree-ssa-loop-ch.cc (update_profile_after_ch): ... here.
- (ch_base::copy_headers): Update.
- * tree-cfg.h (gimple_duplicate_sese_region): Rename to ...
- (gimple_duplicate_seme_region): ... this.
-
-2023-07-12 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/107043
- * range-op.cc (operator_bitwise_and::op1_range): Update bitmask.
-
-2023-07-12 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/107053
- * gimple-range-op.cc (cfn_popcount): Use known set bits.
-
-2023-07-12 Uros Bizjak <ubizjak@gmail.com>
-
- * ira.cc (equiv_init_varies_p): Change return type from int to bool
- and adjust function body accordingly.
- (equiv_init_movable_p): Ditto.
- (memref_used_between_p): Ditto.
- * lra-constraints.cc (valid_address_p): Ditto.
-
-2023-07-12 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op.cc (irange_to_masked_value): Remove.
- (update_known_bitmask): Update irange value/mask pair instead of
- only updating nonzero bits.
-
-2023-07-12 Jan Hubicka <jh@suse.cz>
-
- * tree-cfg.cc (gimple_duplicate_sese_region): Add ORIG_ELIMINATED_EDGES
- parameter and rewrite profile updating code to handle edges elimination.
- * tree-cfg.h (gimple_duplicate_sese_region): Update prototpe.
- * tree-ssa-loop-ch.cc (loop_invariant_op_p): New function.
- (loop_iv_derived_p): New function.
- (should_duplicate_loop_header_p): Track invariant exit edges; fix handling
- of PHIs and propagation of IV derived variables.
- (ch_base::copy_headers): Pass around the invariant edges hash set.
-
-2023-07-12 Uros Bizjak <ubizjak@gmail.com>
-
- * ifcvt.cc (cond_exec_changed_p): Change variable to bool.
- (last_active_insn): Change "skip_use_p" function argument to bool.
- (noce_operand_ok): Change return type from int to bool.
- (find_cond_trap): Ditto.
- (block_jumps_and_fallthru_p): Change "fallthru_p" and
- "jump_p" variables to bool.
- (noce_find_if_block): Change return type from int to bool.
- (cond_exec_find_if_block): Ditto.
- (find_if_case_1): Ditto.
- (find_if_case_2): Ditto.
- (dead_or_predicable): Ditto. Change "reversep" function arg to bool.
- (block_jumps_and_fallthru): Rename from block_jumps_and_fallthru_p.
- (cond_exec_process_insns): Change return type from int to bool.
- Change "mod_ok" function arg to bool.
- (cond_exec_process_if_block): Change return type from int to bool.
- Change "do_multiple_p" function arg to bool. Change "then_mod_ok"
- variable to bool.
- (noce_emit_store_flag): Change return type from int to bool.
- Change "reversep" function arg to bool. Change "cond_complex"
- variable to bool.
- (noce_try_move): Change return type from int to bool.
- (noce_try_ifelse_collapse): Ditto.
- (noce_try_store_flag): Ditto. Change "reversep" variable to bool.
- (noce_try_addcc): Change return type from int to bool. Change
- "subtract" variable to bool.
- (noce_try_store_flag_constants): Change return type from int to bool.
- (noce_try_store_flag_mask): Ditto. Change "reversep" variable to bool.
- (noce_try_cmove): Change return type from int to bool.
- (noce_try_cmove_arith): Ditto. Change "is_mem" variable to bool.
- (noce_try_minmax): Change return type from int to bool. Change
- "unsignedp" variable to bool.
- (noce_try_abs): Change return type from int to bool. Change
- "negate" variable to bool.
- (noce_try_sign_mask): Change return type from int to bool.
- (noce_try_move): Ditto.
- (noce_try_store_flag_constants): Ditto.
- (noce_try_cmove): Ditto.
- (noce_try_cmove_arith): Ditto.
- (noce_try_minmax): Ditto. Change "unsignedp" variable to bool.
- (noce_try_bitop): Change return type from int to bool.
- (noce_operand_ok): Ditto.
- (noce_convert_multiple_sets): Ditto.
- (noce_convert_multiple_sets_1): Ditto.
- (noce_process_if_block): Ditto.
- (check_cond_move_block): Ditto.
- (cond_move_process_if_block): Ditto. Change "success_p"
- variable to bool.
- (rest_of_handle_if_conversion): Change return type to void.
-
-2023-07-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * internal-fn.cc (FOR_EACH_CODE_MAPPING): Adapt for COND_LEN_* support.
- (CASE): Ditto.
- (get_conditional_len_internal_fn): New function.
- * internal-fn.h (get_conditional_len_internal_fn): Ditto.
- * tree-vect-stmts.cc (vectorizable_operation): Adapt for COND_LEN_*
- support.
-
-2023-07-12 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/91681
- * config/i386/i386.md (*add<dwi>3_doubleword_concat_zext): Typo.
-
-2023-07-12 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/91681
- * config/i386/i386.md (*add<dwi>3_doubleword_concat_zext): New
- define_insn_and_split derived from *add<dwi>3_doubleword_concat
- and *add<dwi>3_doubleword_zext.
-
-2023-07-12 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110598
- * config/i386/i386.md (peephole2): Check !reg_mentioned_p when
- optimizing rega = 0; rega op= regb for op in [XOR,IOR,PLUS].
- (peephole2): Simplify rega = 0; rega op= rega cases.
-
-2023-07-12 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_expand_int_compare): If
- testing a TImode SUBREG of a 128-bit vector register against
- zero, use a PTEST instruction instead of first moving it to
- a pair of scalar registers.
-
-2023-07-12 Robin Dapp <rdapp@ventanamicro.com>
-
- * genopinit.cc (main): Adjust maximal number of optabs and
- machine modes.
- * gensupport.cc (find_optab): Shift optab by 20 and mode by
- 10 bits.
- * optabs-query.h (optab_handler): Ditto.
- (convert_optab_handler): Ditto.
-
-2023-07-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110630
- * tree-vect-slp.cc (vect_add_slp_permutation): New
- offset parameter, honor that for the extract code generation.
- (vectorizable_slp_permutation_1): Handle offsetted identities.
-
-2023-07-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (smul<mode>3_highpart): New pattern.
- (umul<mode>3_highpart): Ditto.
-
-2023-07-12 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386.md (extendbfsf2_1): Add new AVX512F
- alternative. Adjust original last alternative's "prefix"
- attribute to maybe_evex.
-
-2023-07-12 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md (vec_dupv4sf): Make first alternative use
- vbroadcastss for AVX2. New AVX512F alternative.
- (*vec_dupv4si): New AVX2 and AVX512F alternatives using
- vpbroadcastd. Replace sselog1 by sseshuf1 in "type" attribute.
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/peephole.md: Remove XThead* peephole passes.
- * config/riscv/thead.md: Include thead-peephole.md.
- * config/riscv/thead-peephole.md: New file.
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv-protos.h (riscv_regno_ok_for_index_p):
- New prototype.
- (riscv_index_reg_class): Likewise.
- * config/riscv/riscv.cc (riscv_regno_ok_for_index_p): New function.
- (riscv_index_reg_class): New function.
- * config/riscv/riscv.h (INDEX_REG_CLASS): Call new function
- riscv_index_reg_class().
- (REGNO_OK_FOR_INDEX_P): Call new function
- riscv_regno_ok_for_index_p().
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv-protos.h (enum riscv_address_type):
- New location of type definition.
- (struct riscv_address_info): Likewise.
- * config/riscv/riscv.cc (enum riscv_address_type):
- Old location of type definition.
- (struct riscv_address_info): Likewise.
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.h (Xmode): New macro.
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.cc (riscv_print_operand_address): Use
- output_addr_const rather than riscv_print_operand.
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/thead.md: Adjust constraints of th_addsl.
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/thead.cc (th_mempair_operands_p):
- Fix documentation of th_mempair_order_operands().
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/thead.cc (th_mempair_save_regs):
- Emit REG_FRAME_RELATED_EXPR notes in prologue.
-
-2023-07-12 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.md: No base-ISA extension splitter for XThead*.
- * config/riscv/thead.md (*extend<SHORT:mode><SUPERQI:mode>2_th_ext):
- New XThead extension INSN.
- (*zero_extendsidi2_th_extu): New XThead extension INSN.
- (*zero_extendhi<GPR:mode>2_th_extu): New XThead extension INSN.
-
-2023-07-12 liuhongt <hongtao.liu@intel.com>
-
- PR target/110438
- PR target/110202
- * config/i386/predicates.md
- (int_float_vector_all_ones_operand): New predicate.
- * config/i386/sse.md (*vmov<mode>_constm1_pternlog_false_dep): New
- define_insn.
- (*<avx512>_cvtmask2<ssemodesuffix><mode>_pternlog_false_dep):
- Ditto.
- (*<avx512>_cvtmask2<ssemodesuffix><mode>_pternlog_false_dep):
- Ditto.
- (*<avx512>_cvtmask2<ssemodesuffix><mode>): Adjust to
- define_insn_and_split to avoid false dependence.
- (*<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto.
- (<mask_codefor>one_cmpl<mode>2<mask_name>): Adjust constraint
- of operands 1 to '0' to avoid false dependence.
- (*andnot<mode>3): Ditto.
- (iornot<mode>3): Ditto.
- (*<nlogic><mode>3): Ditto.
-
-2023-07-12 Mo, Zewei <zewei.mo@intel.com>
-
- * common/config/i386/cpuinfo.h
- (get_intel_cpu): Handle Granite Rapids D.
- * common/config/i386/i386-common.cc:
- (processor_alias_table): Add graniterapids-d.
- * common/config/i386/i386-cpuinfo.h
- (enum processor_subtypes): Add INTEL_COREI7_GRANITERAPIDS_D.
- * config.gcc: Add -march=graniterapids-d.
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Handle graniterapids-d.
- * config/i386/i386.h: (PTA_GRANITERAPIDS_D): New.
- * doc/extend.texi: Add graniterapids-d.
- * doc/invoke.texi: Ditto.
-
-2023-07-12 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins):
- Add OPTION_MASK_ISA_AVX512VL.
- * config/i386/i386-expand.cc (ix86_check_builtin_isa_match):
- Ditto.
-
-2023-07-11 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum insn_type): Add vcompress optimization.
- * config/riscv/riscv-v.cc (emit_vlmax_compress_insn): Ditto.
- (shuffle_compress_patterns): Ditto.
- (expand_vec_perm_const_1): Ditto.
-
-2023-07-11 Uros Bizjak <ubizjak@gmail.com>
-
- * cfghooks.cc (verify_flow_info): Change "err" variable to bool.
- * cfghooks.h (struct cfg_hooks): Change return type of
- verify_flow_info from integer to bool.
- * cfgrtl.cc (can_delete_note_p): Change return type from int to bool.
- (can_delete_label_p): Ditto.
- (rtl_verify_flow_info): Change return type from int to bool
- and adjust function body accordingly. Change "err" variable to bool.
- (rtl_verify_flow_info_1): Ditto.
- (free_bb_for_insn): Change return type to void.
- (rtl_merge_blocks): Change "b_empty" variable to bool.
- (try_redirect_by_replacing_jump): Change "fallthru" variable to bool.
- (verify_hot_cold_block_grouping): Change return type from int to bool.
- Change "err" variable to bool.
- (rtl_verify_edges): Ditto.
- (rtl_verify_bb_insns): Ditto.
- (rtl_verify_bb_pointers): Ditto.
- (rtl_verify_bb_insn_chain): Ditto.
- (rtl_verify_fallthru): Ditto.
- (rtl_verify_bb_layout): Ditto.
- (purge_all_dead_edges): Change "purged" variable to bool.
- * cfgrtl.h (free_bb_for_insn): Change return type from int to void.
- * postreload-gcse.cc (expr_hasher::equal): Change "equiv_p" to bool.
- (load_killed_in_block_p): Change return type from int to bool
- and adjust function body accordingly.
- (oprs_unchanged_p): Return true/false.
- (rest_of_handle_gcse2): Change return type to void.
- * tree-cfg.cc (gimple_verify_flow_info): Change return type from
- int to bool. Change "err" variable to bool.
-
-2023-07-11 Gaius Mulley <gaiusmod2@gmail.com>
-
- * doc/gm2.texi (-Wuninit-variable-checking=) New item.
-
-2023-07-11 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * doc/md.texi: Add COND_LEN_* operations for loop control with length.
- * internal-fn.cc (cond_len_unary_direct): Ditto.
- (cond_len_binary_direct): Ditto.
- (cond_len_ternary_direct): Ditto.
- (expand_cond_len_unary_optab_fn): Ditto.
- (expand_cond_len_binary_optab_fn): Ditto.
- (expand_cond_len_ternary_optab_fn): Ditto.
- (direct_cond_len_unary_optab_supported_p): Ditto.
- (direct_cond_len_binary_optab_supported_p): Ditto.
- (direct_cond_len_ternary_optab_supported_p): Ditto.
- * internal-fn.def (COND_LEN_ADD): Ditto.
- (COND_LEN_SUB): Ditto.
- (COND_LEN_MUL): Ditto.
- (COND_LEN_DIV): Ditto.
- (COND_LEN_MOD): Ditto.
- (COND_LEN_RDIV): Ditto.
- (COND_LEN_MIN): Ditto.
- (COND_LEN_MAX): Ditto.
- (COND_LEN_FMIN): Ditto.
- (COND_LEN_FMAX): Ditto.
- (COND_LEN_AND): Ditto.
- (COND_LEN_IOR): Ditto.
- (COND_LEN_XOR): Ditto.
- (COND_LEN_SHL): Ditto.
- (COND_LEN_SHR): Ditto.
- (COND_LEN_FMA): Ditto.
- (COND_LEN_FMS): Ditto.
- (COND_LEN_FNMA): Ditto.
- (COND_LEN_FNMS): Ditto.
- (COND_LEN_NEG): Ditto.
- * optabs.def (OPTAB_D): Ditto.
-
-2023-07-11 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110614
- * tree-vect-data-refs.cc (vect_supportable_dr_alignment):
- SLP splats are not suitable for re-align ops.
-
-2023-07-10 Peter Bergner <bergner@linux.ibm.com>
-
- * config/rs6000/predicates.md (quad_memory_operand): Remove redundant
- MEM_P usage.
- (vsx_quad_dform_memory_operand): Likewise.
-
-2023-07-10 Uros Bizjak <ubizjak@gmail.com>
-
- * reorg.cc (stop_search_p): Change return type from int to bool
- and adjust function body accordingly.
- (resource_conflicts_p): Ditto.
- (insn_references_resource_p): Change return type from int to bool.
- (insn_sets_resource_p): Ditto.
- (redirect_with_delay_slots_safe_p): Ditto.
- (condition_dominates_p): Change return type from int to bool
- and adjust function body accordingly.
- (redirect_with_delay_list_safe_p): Ditto.
- (check_annul_list_true_false): Ditto. Change "annul_true_p"
- function argument to bool.
- (steal_delay_list_from_target): Change "pannul_p" function
- argument to bool pointer. Change "must_annul" and "used_annul"
- variables from int to bool.
- (steal_delay_list_from_fallthrough): Ditto.
- (own_thread_p): Change return type from int to bool and adjust
- function body accordingly. Change "allow_fallthrough" function
- argument to bool.
- (reorg_redirect_jump): Change return type from int to bool.
- (fill_simple_delay_slots): Change "non_jumps_p" function
- argument from int to bool. Change "maybe_never" varible to bool.
- (fill_slots_from_thread): Change "likely", "thread_if_true" and
- "own_thread" function arguments to bool. Change "lose" and
- "must_annul" variables to bool.
- (delete_from_delay_slot): Change "had_barrier" variable to bool.
- (try_merge_delay_insns): Change "annul_p" variable to bool.
- (fill_eager_delay_slots): Change "own_target" and "own_fallthrouhg"
- variables to bool.
- (rest_of_handle_delay_slots): Change return type from int to void
- and adjust function body accordingly.
-
-2023-07-10 Kito Cheng <kito.cheng@sifive.com>
-
- * doc/extend.texi (RISC-V Operand Modifiers): New.
-
-2023-07-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (add_label_notes): Remove it.
- (insert_insn_end_basic_block): Ditto.
- (pass_vsetvl::commit_vsetvls): Adapt for new helper function.
- * gcse.cc (insert_insn_end_basic_block): Export as global function.
- * gcse.h (insert_insn_end_basic_block): Ditto.
-
-2023-07-10 Christophe Lyon <christophe.lyon@linaro.org>
-
- PR target/110268
- * config/arm/arm-builtins.cc (arm_init_mve_builtins): Handle LTO.
- (arm_builtin_decl): Hahndle MVE builtins.
- * config/arm/arm-mve-builtins.cc (builtin_decl): New function.
- (add_unique_function): Fix handling of
- __ARM_MVE_PRESERVE_USER_NAMESPACE.
- (add_overloaded_function): Likewise.
- * config/arm/arm-protos.h (builtin_decl): New declaration.
-
-2023-07-10 Christophe Lyon <christophe.lyon@linaro.org>
-
- * doc/sourcebuild.texi (arm_v8_1m_main_cde_mve_fp): Document.
-
-2023-07-10 Xi Ruoyao <xry111@xry111.site>
-
- PR tree-optimization/110557
- * tree-vect-patterns.cc (vect_recog_bitfield_ref_pattern):
- Ensure the output sign-extended if necessary.
-
-2023-07-10 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386.md (peephole2): Transform xchg insn with a
- REG_UNUSED note to a (simple) move.
- (*insvti_lowpart_1): New define_insn_and_split.
- (*insvdi_lowpart_1): Likewise.
-
-2023-07-10 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-features.cc (compute_convert_gain): Tweak
- gains/costs for ROTATE/ROTATERT by integer constant on AVX512VL.
- (general_scalar_chain::convert_rotate): On TARGET_AVX512F generate
- avx512vl_rolv2di or avx412vl_rolv4si when appropriate.
-
-2023-07-10 liuhongt <hongtao.liu@intel.com>
-
- PR target/110170
- * config/i386/i386.md (*ieee_max<mode>3_1): New pre_reload
- splitter to detect fp max pattern.
- (*ieee_min<mode>3_1): Ditto, but for fp min pattern.
-
-2023-07-09 Jan Hubicka <jh@suse.cz>
-
- * cfg.cc (check_bb_profile): Dump counts with relative frequency.
- (dump_edge_info): Likewise.
- (dump_bb_info): Likewise.
- * profile-count.cc (profile_count::dump): Add comma between quality and
- freq.
-
-2023-07-08 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/110600
- * cfgloopmanip.cc (scale_loop_profile): Add mising profile_dump check.
-
-2023-07-08 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/110590
- * cfgloopmanip.cc (scale_loop_profile): Avoid scaling exits within
- inner loops and be more careful about inconsistent profiles.
- (duplicate_loop_body_to_header_edge): Fix profile update when eliminated
- exit is followed by other exit.
-
-2023-07-08 Uros Bizjak <ubizjak@gmail.com>
-
- * cprop.cc (reg_available_p): Change return type from int to bool.
- (reg_not_set_p): Ditto.
- (try_replace_reg): Ditto. Change "success" variable to bool.
- (cprop_jump): Change return type from int to void
- and adjust function body accordingly.
- (constprop_register): Ditto.
- (cprop_insn): Ditto. Change "changed" variable to bool.
- (local_cprop_pass): Change return type from int to void
- and adjust function body accordingly.
- (bypass_block): Ditto. Change "change", "may_be_loop_header"
- and "removed_p" variables to bool.
- (bypass_conditional_jumps): Change return type from int to void
- and adjust function body accordingly. Change "changed"
- variable to bool.
- (one_cprop_pass): Ditto.
-
-2023-07-08 Uros Bizjak <ubizjak@gmail.com>
-
- * gcse.cc (expr_equiv_p): Change return type from int to bool.
- (oprs_unchanged_p): Change return type from int to void
- and adjust function body accordingly.
- (oprs_anticipatable_p): Ditto.
- (oprs_available_p): Ditto.
- (insert_expr_in_table): Ditto. Change "antic_p" and "avail_p"
- arguments to bool. Change "found" variable to bool.
- (load_killed_in_block_p): Change return type from int to void and
- adjust function body accordingly. Change "avail_p" argument to bool.
- (pre_expr_reaches_here_p): Change return type from int to void
- and adjust function body accordingly.
- (pre_delete): Ditto. Change "changed" variable to bool.
- (pre_gcse): Change return type from int to void
- and adjust function body accordingly. Change "did_insert" and
- "changed" variables to bool.
- (one_pre_gcse_pass): Change return type from int to void
- and adjust function body accordingly. Change "changed" variable
- to bool.
- (should_hoist_expr_to_dom): Change return type from int to void
- and adjust function body accordingly. Change
- "visited_allocated_locally" variable to bool.
- (hoist_code): Change return type from int to void and adjust
- function body accordingly. Change "changed" variable to bool.
- (one_code_hoisting_pass): Ditto.
- (pre_edge_insert): Change return type from int to void and adjust
- function body accordingly. Change "did_insert" variable to bool.
- (pre_expr_reaches_here_p_work): Change return type from int to void
- and adjust function body accordingly.
- (simple_mem): Ditto.
- (want_to_gcse_p): Change return type from int to void
- and adjust function body accordingly.
- (can_assign_to_reg_without_clobbers_p): Update function body
- for bool return type.
- (hash_scan_set): Change "antic_p" and "avail_p" variables to bool.
- (pre_insert_copies): Change "added_copy" variable to bool.
-
-2023-07-08 Jonathan Wakely <jwakely@redhat.com>
-
- PR c++/110595
- PR c++/110596
- * doc/invoke.texi (Warning Options): Fix typos.
-
-2023-07-07 Jan Hubicka <jh@suse.cz>
-
- * profile-count.cc (profile_count::dump): Add FUN
- parameter; print relative frequency.
- (profile_count::debug): Update.
- * profile-count.h (profile_count::dump): Update
- prototype.
-
-2023-07-07 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/43644
- PR target/110533
- * config/i386/i386-expand.cc (ix86_expand_move): Convert SETs of
- TImode destinations from paradoxical SUBREGs (setting the lowpart)
- into explicit zero extensions. Use *insvti_highpart_1 instruction
- to set the highpart of a TImode destination.
-
-2023-07-07 Jan Hubicka <jh@suse.cz>
-
- * predict.cc (force_edge_cold): Use
- set_edge_probability_and_rescale_others; improve dumps.
-
-2023-07-07 Jan Hubicka <jh@suse.cz>
-
- * cfgloopmanip.cc (scale_loop_profile): Fix computation of count_in and scaling blocks
- after exit.
- * tree-vect-loop-manip.cc (vect_do_peeling): Scale loop profile of the epilogue if bound
- is known.
-
-2023-07-07 Juergen Christ <jchrist@linux.ibm.com>
-
- * config/s390/s390.cc (vec_init): Fix default case
-
-2023-07-07 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-assigns.cc (assign_by_spills): Add reload insns involving
- reload pseudos with non-refined class to be processed on the next
- sub-pass.
- * lra-constraints.cc (enough_allocatable_hard_regs_p): New func.
- (in_class_p): Use it.
- (print_curr_insn_alt): New func.
- (process_alt_operands): Use it. Improve debug info.
- (curr_insn_transform): Use print_curr_insn_alt. Refine reload
- pseudo class if it is not refined yet.
-
-2023-07-07 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (irange::get_bitmask_from_range): Return all the
- known bits for a singleton.
- (irange::set_range_from_bitmask): Set a range of a singleton when
- all bits are known.
-
-2023-07-07 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (irange::intersect): Leave normalization to
- caller.
-
-2023-07-07 Aldy Hernandez <aldyh@redhat.com>
-
- * data-streamer-in.cc (streamer_read_value_range): Adjust for
- value/mask.
- * data-streamer-out.cc (streamer_write_vrange): Same.
- * range-op.cc (operator_cast::fold_range): Same.
- * value-range-pretty-print.cc
- (vrange_printer::print_irange_bitmasks): Same.
- * value-range-storage.cc (irange_storage::write_lengths_address):
- Same.
- (irange_storage::set_irange): Same.
- (irange_storage::get_irange): Same.
- (irange_storage::size): Same.
- (irange_storage::dump): Same.
- * value-range-storage.h: Same.
- * value-range.cc (debug): New.
- (irange_bitmask::dump): New.
- (add_vrange): Adjust for value/mask.
- (irange::operator=): Same.
- (irange::set): Same.
- (irange::verify_range): Same.
- (irange::operator==): Same.
- (irange::contains_p): Same.
- (irange::irange_single_pair_union): Same.
- (irange::union_): Same.
- (irange::intersect): Same.
- (irange::invert): Same.
- (irange::get_nonzero_bits_from_range): Rename to...
- (irange::get_bitmask_from_range): ...this.
- (irange::set_range_from_nonzero_bits): Rename to...
- (irange::set_range_from_bitmask): ...this.
- (irange::set_nonzero_bits): Rename to...
- (irange::update_bitmask): ...this.
- (irange::get_nonzero_bits): Rename to...
- (irange::get_bitmask): ...this.
- (irange::intersect_nonzero_bits): Rename to...
- (irange::intersect_bitmask): ...this.
- (irange::union_nonzero_bits): Rename to...
- (irange::union_bitmask): ...this.
- (irange_bitmask::verify_mask): New.
- * value-range.h (class irange_bitmask): New.
- (irange_bitmask::set_unknown): New.
- (irange_bitmask::unknown_p): New.
- (irange_bitmask::irange_bitmask): New.
- (irange_bitmask::get_precision): New.
- (irange_bitmask::get_nonzero_bits): New.
- (irange_bitmask::set_nonzero_bits): New.
- (irange_bitmask::operator==): New.
- (irange_bitmask::union_): New.
- (irange_bitmask::intersect): New.
- (class irange): Friend vrange_printer.
- (irange::varying_compatible_p): Adjust for bitmask.
- (irange::set_varying): Same.
- (irange::set_nonzero): Same.
-
-2023-07-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md (*vec_extractv2ti): Drop g modifiers.
-
-2023-07-07 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md (@vec_extract_hi_<mode>): Drop last
- alternative. Switch new last alternative's "isa" attribute to
- "avx512vl".
- (vec_extract_hi_v32qi): Likewise.
-
-2023-07-07 Pan Li <pan2.li@intel.com>
- Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
- when FRM_MODE_DYN.
- (riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
- (riscv_mode_exit): Likewise for exit mode.
- (riscv_mode_needed): Likewise for needed mode.
- (riscv_mode_after): Likewise for after mode.
-
-2023-07-07 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector.md: Fix typo.
-
-2023-07-06 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/25623
- * tree-ssa-loop-ch.cc (ch_base::copy_headers): Scale loop frequency to maximal number
- of iterations determined.
- * tree-ssa-loop-ivcanon.cc (try_unroll_loop_completely): Likewise.
-
-2023-07-06 Jan Hubicka <jh@suse.cz>
-
- * cfgloopmanip.cc (scale_loop_profile): Rewrite exit edge
- probability update to be safe on loops with subloops.
- Make bound parameter to be iteration bound.
- * tree-ssa-loop-ivcanon.cc (try_peel_loop): Update call
- of scale_loop_profile.
- * tree-vect-loop-manip.cc (vect_do_peeling): Likewise.
-
-2023-07-06 Hao Liu OS <hliu@os.amperecomputing.com>
-
- PR tree-optimization/110449
- * tree-vect-loop.cc (vectorizable_induction): use vec_n to replace
- vec_loop for the unrolled loop.
-
-2023-07-06 Jan Hubicka <jh@suse.cz>
-
- * cfg.cc (set_edge_probability_and_rescale_others): New function.
- (update_bb_profile_for_threading): Use it; simplify the rest.
- * cfg.h (set_edge_probability_and_rescale_others): Declare.
- * profile-count.h (profile_probability::apply_scale): New.
-
-2023-07-06 Claudiu Zissulescu <claziss@gmail.com>
-
- * doc/extend.texi (ARC Built-in Functions): Update documentation
- with missing builtins.
-
-2023-07-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110556
- * tree-ssa-tail-merge.cc (gimple_equal_p): Check
- assign code and all operands of non-stores.
-
-2023-07-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110563
- * tree-vectorizer.h (vect_determine_partial_vectors_and_peeling):
- Remove second argument.
- * tree-vect-loop.cc (vect_determine_partial_vectors_and_peeling):
- Remove for_epilogue_p argument. Merge assert ...
- (vect_analyze_loop_2): ... with check done before determining
- partial vectors by moving it after.
- * tree-vect-loop-manip.cc (vect_do_peeling): Adjust.
-
-2023-07-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * ggc-common.cc (gt_pch_note_reorder, gt_pch_save): Tighten up a
- few things re 'reorder' option and strings.
- * stringpool.cc (gt_pch_p_S): This is now 'gcc_unreachable'.
-
-2023-07-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * gengtype-parse.cc: Clean up obsolete parametrized structs
- remnants.
- * gengtype.cc: Likewise.
- * gengtype.h: Likewise.
-
-2023-07-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * gengtype.cc (struct walk_type_data): Remove 'needs_cast_p'.
- Adjust all users.
-
-2023-07-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * gengtype-parse.cc (token_names): Add '"user"'.
- * gengtype.h (gty_token): Add 'UNUSED_PARAM_IS' for use with
- 'FIRST_TOKEN_WITH_VALUE'.
-
-2023-07-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * doc/gty.texi (GTY Options) <string_length>: Enhance.
-
-2023-07-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * gengtype.cc (write_root, write_roots): Explicitly reject
- 'string_length' option.
- * doc/gty.texi (GTY Options) <string_length>: Document.
-
-2023-07-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * ggc-internal.h (ggc_pch_count_object, ggc_pch_alloc_object)
- (ggc_pch_write_object): Remove 'bool is_string' argument.
- * ggc-common.cc: Adjust.
- * ggc-page.cc: Likewise.
-
-2023-07-06 Roger Sayle <roger@nextmovesoftware.com>
-
- * dwarf2out.cc (mem_loc_descriptor): Handle COPYSIGN.
-
-2023-07-06 Hongyu Wang <hongyu.wang@intel.com>
-
- * doc/extend.texi: Move x86 inlining rule to a new subsubsection
- and add description for inling of function with arch and tune
- attributes.
-
-2023-07-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110515
- * tree-ssa-pre.cc (compute_avail): Make code dealing
- with hoisting loads with different alias-sets more
- robust.
-
-2023-07-06 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-stmts.cc (vect_get_strided_load_store_ops): Fix ICE.
-
-2023-07-06 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.cc (ix86_can_inline_p): If callee has
- default arch=x86-64 and tune=generic, do not block the
- inlining to its caller. Also allow callee with different
- arch= to be inlined if it has always_inline attribute and
- it's ISA is subset of caller's.
-
-2023-07-06 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386.cc (ix86_rtx_costs): Adjust rtx_cost for
- DF/SFmode AND/IOR/XOR/ANDN operations.
-
-2023-07-06 Andrew Pinski <apinski@marvell.com>
-
- PR middle-end/110554
- * tree-vect-generic.cc (expand_vector_condition): For comparisons,
- just build using boolean_type_node instead of the cond_type.
- For non-comparisons/non-scalar-bitmask, build a ` != 0` gimple
- that will feed into the COND_EXPR.
-
-2023-07-06 liuhongt <hongtao.liu@intel.com>
-
- PR target/110170
- * config/i386/i386.md (movdf_internal): Disparage slightly for
- 2 alternatives (r,v) and (v,r) by adding constraint modifier
- '?'.
-
-2023-07-06 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
-
- PR target/106907
- * config/rs6000/rs6000.cc (rs6000_expand_vector_extract): Remove redundant
- initialization of new_addr.
-
-2023-07-06 Hao Liu <hliu@os.amperecomputing.com>
-
- PR tree-optimization/110474
- * tree-vect-loop.cc (vect_analyze_loop_2): unscale the VF by suggested
- unroll factor while selecting the epilog vect loop VF.
-
-2023-07-05 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (compute_operand_range): Convert to a tail
- call.
-
-2023-07-05 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (compute_operand_range): After calling
- compute_operand2_range, recursively call self if needed.
- (compute_operand2_range): Turn into a leaf function.
- (gori_compute::compute_operand1_and_operand2_range): Finish
- operand2 calculation.
- * gimple-range-gori.h (compute_operand2_range): Remove name param.
-
-2023-07-05 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (compute_operand_range): After calling
- compute_operand1_range, recursively call self if needed.
- (compute_operand1_range): Turn into a leaf function.
- (gori_compute::compute_operand1_and_operand2_range): Finish
- operand1 calculation.
- * gimple-range-gori.h (compute_operand1_range): Remove name param.
-
-2023-07-05 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (compute_operand_range): Check for
- operand interdependence when both op1 and op2 are computed.
- (compute_operand1_and_operand2_range): No checks required now.
-
-2023-07-05 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (compute_operand_range): Check for
- a relation between op1 and op2 and use that instead.
- (compute_operand1_range): Don't look for a relation override.
- (compute_operand2_range): Ditto.
-
-2023-07-05 Jonathan Wakely <jwakely@redhat.com>
-
- * doc/contrib.texi (Contributors): Update my entry.
-
-2023-07-05 Filip Kastl <filip.kastl@gmail.com>
-
- * value-prof.cc (gimple_mod_subtract_transform): Correct edge
- prob calculation.
-
-2023-07-05 Uros Bizjak <ubizjak@gmail.com>
-
- * sched-int.h (struct haifa_sched_info): Change can_schedule_ready_p,
- scehdule_more_p and contributes_to_priority indirect frunction
- type from int to bool.
- (no_real_insns_p): Change return type from int to bool.
- (contributes_to_priority): Ditto.
- * haifa-sched.cc (no_real_insns_p): Change return type from
- int to bool and adjust function body accordingly.
- * modulo-sched.cc (try_scheduling_node_in_cycle): Change "success"
- variable type from int to bool.
- (ps_insn_advance_column): Change return type from int to bool.
- (ps_has_conflicts): Ditto. Change "has_conflicts"
- variable type from int to bool.
- * sched-deps.cc (deps_may_trap_p): Change return type from int to bool.
- (conditions_mutex_p): Ditto.
- * sched-ebb.cc (schedule_more_p): Ditto.
- (ebb_contributes_to_priority): Change return type from
- int to bool and adjust function body accordingly.
- * sched-rgn.cc (is_cfg_nonregular): Ditto.
- (check_live_1): Ditto.
- (is_pfree): Ditto.
- (find_conditional_protection): Ditto.
- (is_conditionally_protected): Ditto.
- (is_prisky): Ditto.
- (is_exception_free): Ditto.
- (haifa_find_rgns): Change "unreachable" and "too_large_failure"
- variables from int to bool.
- (extend_rgns): Change "rescan" variable from int to bool.
- (check_live): Change return type from
- int to bool and adjust function body accordingly.
- (can_schedule_ready_p): Ditto.
- (schedule_more_p): Ditto.
- (contributes_to_priority): Ditto.
-
-2023-07-05 Robin Dapp <rdapp@ventanamicro.com>
-
- * doc/md.texi: Document that vec_set and vec_extract must not
- fail.
- * gimple-isel.cc (gimple_expand_vec_set_expr): Rename this...
- (gimple_expand_vec_set_extract_expr): ...to this.
- (gimple_expand_vec_exprs): Call renamed function.
- * internal-fn.cc (vec_extract_direct): Add.
- (expand_vec_extract_optab_fn): New function to expand
- vec_extract optab.
- (direct_vec_extract_optab_supported_p): Add.
- * internal-fn.def (VEC_EXTRACT): Add.
- * optabs.cc (can_vec_extract_var_idx_p): New function.
- * optabs.h (can_vec_extract_var_idx_p): Declare.
-
-2023-07-05 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md: Add gen_lowpart.
-
-2023-07-05 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md: Allow register index operand.
-
-2023-07-05 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_exact_insn): Use FRM_DYN instead of const0.
-
-2023-07-05 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md: Use float_truncate.
-
-2023-07-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * internal-fn.cc (internal_fn_len_index): Apply
- LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer.
- (internal_fn_mask_index): Ditto.
- * optabs-query.cc (supports_vec_gather_load_p): Ditto.
- (supports_vec_scatter_store_p): Ditto.
- * tree-vect-data-refs.cc (vect_gather_scatter_fn_p): Ditto.
- * tree-vect-patterns.cc (vect_recog_gather_scatter_pattern): Ditto.
- * tree-vect-stmts.cc (check_load_store_for_partial_vectors): Ditto.
- (vect_get_strided_load_store_ops): Ditto.
- (vectorizable_store): Ditto.
- (vectorizable_load): Ditto.
-
-2023-07-05 Robin Dapp <rdapp@ventanamicro.com>
- Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * simplify-rtx.cc (native_encode_rtx): Ditto.
- (native_decode_vector_rtx): Ditto.
- (simplify_const_vector_byte_offset): Ditto.
- (simplify_const_vector_subreg): Ditto.
- * tree.cc (build_truth_vector_type_for_mode): Ditto.
- * varasm.cc (output_constant_pool_2): Ditto.
-
-2023-07-05 YunQiang Su <yunqiang.su@cipunited.com>
-
- * config/mips/mips.cc (mips_expand_block_move): don't expand for
- r6 with -mno-unaligned-access option if one or both of src and
- dest are unaligned. restruct: return directly if length is not const.
- (mips_block_move_straight): emit_move if ISA_HAS_UNALIGNED_ACCESS.
-
-2023-07-05 Jan Beulich <jbeulich@suse.com>
-
- PR target/100711
- * config/i386/sse.md: New splitters to simplify
- not;vec_duplicate as a singular vpternlog.
- (one_cmpl<mode>2): Allow broadcast for operand 1.
- (<mask_codefor>one_cmpl<mode>2<mask_name>): Likewise.
-
-2023-07-05 Jan Beulich <jbeulich@suse.com>
-
- PR target/100711
- * config/i386/sse.md: New splitters to simplify
- not;vec_duplicate;{ior,xor} as vec_duplicate;{iornot,xnor}.
-
-2023-07-05 Jan Beulich <jbeulich@suse.com>
-
- PR target/100711
- * config/i386/sse.md: Permit non-immediate operand 1 in AVX2
- form of splitter for PR target/100711.
-
-2023-07-05 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110541
- * tree.def (VEC_PERM_EXPR): Adjust documentation to reflect
- reality.
-
-2023-07-05 Jan Beulich <jbeulich@suse.com>
-
- PR target/93768
- * config/i386/sse.md (*andnot<mode>3): Add new alternatives
- for memory form operand 1.
-
-2023-07-05 Jan Beulich <jbeulich@suse.com>
-
- PR target/93768
- * config/i386/i386.cc (ix86_rtx_costs): Further special-case
- bitwise vector operations.
- * config/i386/sse.md (*iornot<mode>3): New insn.
- (*xnor<mode>3): Likewise.
- (*<nlogic><mode>3): Likewise.
- (andor): New code iterator.
- (nlogic): New code attribute.
- (ternlog_nlogic): Likewise.
-
-2023-07-05 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vect_mark_relevant): Fix typo.
-
-2023-07-05 yulong <shiyulong@iscas.ac.cn>
-
- * config/riscv/vector.md: Add float16 attr at sew、vlmul and ratio.
-
-2023-07-05 yulong <shiyulong@iscas.ac.cn>
-
- * config/riscv/genrvv-type-indexer.cc (valid_type): Enable FP16 tuple.
- * config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro.
- (ADJUST_ALIGNMENT): Ditto.
- (RVV_TUPLE_PARTIAL_MODES): Ditto.
- (ADJUST_NUNITS): Ditto.
- * config/riscv/riscv-vector-builtins-types.def (vfloat16mf4x2_t):
- New types.
- (vfloat16mf4x3_t): Ditto.
- (vfloat16mf4x4_t): Ditto.
- (vfloat16mf4x5_t): Ditto.
- (vfloat16mf4x6_t): Ditto.
- (vfloat16mf4x7_t): Ditto.
- (vfloat16mf4x8_t): Ditto.
- (vfloat16mf2x2_t): Ditto.
- (vfloat16mf2x3_t): Ditto.
- (vfloat16mf2x4_t): Ditto.
- (vfloat16mf2x5_t): Ditto.
- (vfloat16mf2x6_t): Ditto.
- (vfloat16mf2x7_t): Ditto.
- (vfloat16mf2x8_t): Ditto.
- (vfloat16m1x2_t): Ditto.
- (vfloat16m1x3_t): Ditto.
- (vfloat16m1x4_t): Ditto.
- (vfloat16m1x5_t): Ditto.
- (vfloat16m1x6_t): Ditto.
- (vfloat16m1x7_t): Ditto.
- (vfloat16m1x8_t): Ditto.
- (vfloat16m2x2_t): Ditto.
- (vfloat16m2x3_t): Ditto.
- (vfloat16m2x4_t): Ditto.
- (vfloat16m4x2_t): Ditto.
- * config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): New macro.
- (vfloat16mf4x3_t): Ditto.
- (vfloat16mf4x4_t): Ditto.
- (vfloat16mf4x5_t): Ditto.
- (vfloat16mf4x6_t): Ditto.
- (vfloat16mf4x7_t): Ditto.
- (vfloat16mf4x8_t): Ditto.
- (vfloat16mf2x2_t): Ditto.
- (vfloat16mf2x3_t): Ditto.
- (vfloat16mf2x4_t): Ditto.
- (vfloat16mf2x5_t): Ditto.
- (vfloat16mf2x6_t): Ditto.
- (vfloat16mf2x7_t): Ditto.
- (vfloat16mf2x8_t): Ditto.
- (vfloat16m1x2_t): Ditto.
- (vfloat16m1x3_t): Ditto.
- (vfloat16m1x4_t): Ditto.
- (vfloat16m1x5_t): Ditto.
- (vfloat16m1x6_t): Ditto.
- (vfloat16m1x7_t): Ditto.
- (vfloat16m1x8_t): Ditto.
- (vfloat16m2x2_t): Ditto.
- (vfloat16m2x3_t): Ditto.
- (vfloat16m2x4_t): Ditto.
- (vfloat16m4x2_t): Ditto.
- * config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): New.
- * config/riscv/riscv.md: New.
- * config/riscv/vector-iterators.md: New.
-
-2023-07-04 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110487
- * match.pd (a !=/== CST1 ? CST2 : CST3): Always
- build a nonstandard integer and use that.
-
-2023-07-04 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (a?-1:0): Cast type an integer type
- rather the type before the negative.
- (a?0:-1): Likewise.
-
-2023-07-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.cc (machine_function, xtensa_expand_prologue):
- Change to use HARD_REG_BIT and its macros.
- * config/xtensa/xtensa.md
- (peephole2: regmove elimination during DFmode input reload):
- Likewise.
-
-2023-07-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110491
- * tree-ssa-phiopt.cc (match_simplify_replacement): Check
- whether the PHI args are possibly undefined before folding
- the COND_EXPR.
-
-2023-07-04 Pan Li <pan2.li@intel.com>
- Thomas Schwinge <thomas@codesourcery.com>
-
- * lto-streamer-in.cc (lto_input_mode_table): Stream in the mode
- bits for machine mode table.
- * lto-streamer-out.cc (lto_write_mode_table): Stream out the
- HOST machine mode bits.
- * lto-streamer.h (struct lto_file_decl_data): New fields mode_bits.
- * tree-streamer.cc (streamer_mode_table): Take MAX_MACHINE_MODE
- as the table size.
- * tree-streamer.h (streamer_mode_table): Ditto.
- (bp_pack_machine_mode): Take 1 << ceil_log2 (MAX_MACHINE_MODE)
- as the packing limit.
- (bp_unpack_machine_mode): Ditto with 'file_data->mode_bits'.
-
-2023-07-04 Thomas Schwinge <thomas@codesourcery.com>
-
- * lto-streamer.h (class lto_input_block): Capture
- 'lto_file_decl_data *file_data' instead of just
- 'unsigned char *mode_table'.
- * ipa-devirt.cc (ipa_odr_read_section): Adjust.
- * ipa-fnsummary.cc (inline_read_section): Likewise.
- * ipa-icf.cc (sem_item_optimizer::read_section): Likewise.
- * ipa-modref.cc (read_section): Likewise.
- * ipa-prop.cc (ipa_prop_read_section, read_replacements_section):
- Likewise.
- * ipa-sra.cc (isra_read_summary_section): Likewise.
- * lto-cgraph.cc (input_cgraph_opt_section): Likewise.
- * lto-section-in.cc (lto_create_simple_input_block): Likewise.
- * lto-streamer-in.cc (lto_read_body_or_constructor)
- (lto_input_toplevel_asms): Likewise.
- * tree-streamer.h (bp_unpack_machine_mode): Likewise.
-
-2023-07-04 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-phiopt.cc (pass_phiopt::execute): Mark SSA undefs.
- (empty_bb_or_one_feeding_into_p): Check for them.
- * tree-ssa.h (gimple_uses_undefined_value_p): Remove.
- * tree-ssa.cc (gimple_uses_undefined_value_p): Likewise.
-
-2023-07-04 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (vect_analyze_loop_costing): Remove
- check guarding scalar_niter underflow.
-
-2023-07-04 Hao Liu <hliu@os.amperecomputing.com>
-
- PR tree-optimization/110531
- * tree-vect-loop.cc (vect_analyze_loop_1): initialize
- slp_done_for_suggested_uf to false.
-
-2023-07-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110228
- * tree-ssa-ifcombine.cc (pass_tree_ifcombine::execute):
- Mark SSA may-undefs.
- (bb_no_side_effects_p): Check stmt uses for undefs.
-
-2023-07-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110436
- * tree-vect-stmts.cc (vect_mark_relevant): Expand dumping,
- force live but not relevant pattern stmts relevant.
-
-2023-07-04 Lili Cui <lili.cui@intel.com>
-
- * config/i386/i386.h: Add PTA_ENQCMD and PTA_UINTR to PTA_SIERRAFOREST.
- * doc/invoke.texi: Update new isa to march=sierraforest and grandridge.
-
-2023-07-04 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110495
- * tree.h (TREE_OVERFLOW): Do not mention VECTOR_CSTs
- since we do not set TREE_OVERFLOW on those since the
- introduction of VL vectors.
- * match.pd (x +- CST +- CST): For VECTOR_CST do not look
- at TREE_OVERFLOW to determine validity of association.
-
-2023-07-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110310
- * tree-vect-loop.cc (vect_determine_partial_vectors_and_peeling):
- Move costing part ...
- (vect_analyze_loop_costing): ... here. Integrate better
- estimate for epilogues from ...
- (vect_analyze_loop_2): Call vect_determine_partial_vectors_and_peeling
- with actual epilogue status.
- * tree-vect-loop-manip.cc (vect_do_peeling): ... here and
- avoid cancelling epilogue vectorization.
- (vect_update_epilogue_niters): Remove. No longer update
- epilogue LOOP_VINFO_NITERS.
-
-2023-07-04 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-07-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector.md: Fix typo.
-
-2023-07-04 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * doc/md.texi: Add len_mask_gather_load/len_mask_scatter_store.
- * internal-fn.cc (expand_scatter_store_optab_fn): Ditto.
- (expand_gather_load_optab_fn): Ditto.
- (internal_load_fn_p): Ditto.
- (internal_store_fn_p): Ditto.
- (internal_gather_scatter_fn_p): Ditto.
- (internal_fn_len_index): Ditto.
- (internal_fn_mask_index): Ditto.
- (internal_fn_stored_value_index): Ditto.
- * internal-fn.def (LEN_MASK_GATHER_LOAD): Ditto.
- (LEN_MASK_SCATTER_STORE): Ditto.
- * optabs.def (OPTAB_CD): Ditto.
-
-2023-07-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc
- (vector_insn_info::parse_insn): Add early break.
-
-2023-07-04 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.md (CRIS_UNSPEC_SWAP_BITS): Remove.
- ("cris_swap_bits", "ctzsi2"): Use bitreverse instead.
-
-2023-07-04 Hans-Peter Nilsson <hp@axis.com>
-
- * dwarf2out.cc (mem_loc_descriptor): Handle BITREVERSE.
-
-2023-07-03 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * common/config/riscv/riscv-common.cc: Add support for zvbb,
- zvbc, zvkg, zvkned, zvknha, zvknhb, zvksed, zvksh, zvkn,
- zvknc, zvkng, zvks, zvksc, zvksg, zvkt and the implied subsets.
- * config/riscv/arch-canonicalize: Add canonicalization info for
- zvkn, zvknc, zvkng, zvks, zvksc, zvksg.
- * config/riscv/riscv-opts.h (MASK_ZVBB): New macro.
- (MASK_ZVBC): Likewise.
- (TARGET_ZVBB): Likewise.
- (TARGET_ZVBC): Likewise.
- (MASK_ZVKG): Likewise.
- (MASK_ZVKNED): Likewise.
- (MASK_ZVKNHA): Likewise.
- (MASK_ZVKNHB): Likewise.
- (MASK_ZVKSED): Likewise.
- (MASK_ZVKSH): Likewise.
- (MASK_ZVKN): Likewise.
- (MASK_ZVKNC): Likewise.
- (MASK_ZVKNG): Likewise.
- (MASK_ZVKS): Likewise.
- (MASK_ZVKSC): Likewise.
- (MASK_ZVKSG): Likewise.
- (MASK_ZVKT): Likewise.
- (TARGET_ZVKG): Likewise.
- (TARGET_ZVKNED): Likewise.
- (TARGET_ZVKNHA): Likewise.
- (TARGET_ZVKNHB): Likewise.
- (TARGET_ZVKSED): Likewise.
- (TARGET_ZVKSH): Likewise.
- (TARGET_ZVKN): Likewise.
- (TARGET_ZVKNC): Likewise.
- (TARGET_ZVKNG): Likewise.
- (TARGET_ZVKS): Likewise.
- (TARGET_ZVKSC): Likewise.
- (TARGET_ZVKSG): Likewise.
- (TARGET_ZVKT): Likewise.
- * config/riscv/riscv.opt: Introduction of riscv_zv{b,k}_subext.
-
-2023-07-03 Andrew Pinski <apinski@marvell.com>
-
- PR middle-end/110510
- * except.h (struct eh_landing_pad_d): Add chain_next GTY.
-
-2023-07-03 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.h: Avoid duplicate multiply_defined specs on
- earlier Darwin versions with shared libgcc.
-
-2023-07-03 Uros Bizjak <ubizjak@gmail.com>
-
- * tree.h (tree_int_cst_equal): Change return type from int to bool.
- (operand_equal_for_phi_arg_p): Ditto.
- (tree_map_base_marked_p): Ditto.
- * tree.cc (contains_placeholder_p): Update function body
- for bool return type.
- (type_cache_hasher::equal): Ditto.
- (tree_map_base_hash): Change return type
- from int to void and adjust function body accordingly.
- (tree_int_cst_equal): Ditto.
- (operand_equal_for_phi_arg_p): Ditto.
- (get_narrower): Change "first" variable to bool.
- (cl_option_hasher::equal): Update function body for bool return type.
- * ggc.h (ggc_set_mark): Change return type from int to bool.
- (ggc_marked_p): Ditto.
- * ggc-page.cc (gt_ggc_mx): Change return type
- from int to void and adjust function body accordingly.
- (ggc_set_mark): Ditto.
-
-2023-07-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Change order of
- LEN_MASK_LOAD/LEN_MASK_STORE/LEN_LOAD/LEN_STORE arguments.
- * config/riscv/riscv-v.cc (expand_load_store): Ditto.
- * doc/md.texi: Ditto.
- * gimple-fold.cc (gimple_fold_partial_load_store_mem_ref): Ditto.
- * internal-fn.cc (len_maskload_direct): Ditto.
- (len_maskstore_direct): Ditto.
- (add_len_and_mask_args): New function.
- (expand_partial_load_optab_fn): Change order of
- LEN_MASK_LOAD/LEN_MASK_STORE/LEN_LOAD/LEN_STORE arguments.
- (expand_partial_store_optab_fn): Ditto.
- (internal_fn_len_index): New function.
- (internal_fn_mask_index): Change order of
- LEN_MASK_LOAD/LEN_MASK_STORE/LEN_LOAD/LEN_STORE arguments.
- (internal_fn_stored_value_index): Ditto.
- (internal_len_load_store_bias): Ditto.
- * internal-fn.h (internal_fn_len_index): New function.
- * tree-ssa-dse.cc (initialize_ao_ref_for_dse): Change order of
- LEN_MASK_LOAD/LEN_MASK_STORE/LEN_LOAD/LEN_STORE arguments.
- * tree-vect-stmts.cc (vectorizable_store): Ditto.
- (vectorizable_load): Ditto.
-
-2023-07-03 Gaius Mulley <gaiusmod2@gmail.com>
-
- PR modula2/110125
- * doc/gm2.texi (Semantic checking): Include examples using
- -Wuninit-variable-checking.
-
-2023-07-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
- (*single_widen_fnma<mode>): Ditto.
- (*double_widen_fms<mode>): Ditto.
- (*single_widen_fms<mode>): Ditto.
- (*double_widen_fnms<mode>): Ditto.
- (*single_widen_fnms<mode>): Ditto.
-
-2023-07-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (@pred_single_widen_mul<any_extend:su><mode>): Change "@"
- into "*" in pattern name which simplifies build files.
- (*pred_single_widen_mul<any_extend:su><mode>): Ditto.
- (*pred_single_widen_mul<mode>): New pattern.
-
-2023-07-03 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-simd.md (vec_extract<mode><Vhalf>): Expect
- the index to be 0 or 1.
-
-2023-07-03 Lehua Ding <lehua.ding@rivai.ai>
-
- Revert:
- 2023-07-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
- (*single_widen_fnma<mode>): Ditto.
- (*double_widen_fms<mode>): Ditto.
- (*single_widen_fms<mode>): Ditto.
- (*double_widen_fnms<mode>): Ditto.
- (*single_widen_fnms<mode>): Ditto.
-
-2023-07-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
- (*single_widen_fnma<mode>): Ditto.
- (*double_widen_fms<mode>): Ditto.
- (*single_widen_fms<mode>): Ditto.
- (*double_widen_fnms<mode>): Ditto.
- (*single_widen_fnms<mode>): Ditto.
-
-2023-07-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector.md: Fix typo.
-
-2023-07-03 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110506
- * tree-vect-patterns.cc (vect_recog_rotate_pattern): Re-order
- TYPE_PRECISION access with INTEGRAL_TYPE_P check.
-
-2023-07-03 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110506
- * tree-ssa-ccp.cc (get_value_for_expr): Check for integral
- type before relying on TYPE_PRECISION to produce a nonzero mask.
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/mips.md(*and<mode>3_mips16): Generates
- ZEB/ZEH instructions.
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/mips.cc(mips_9bit_offset_address_p): Restrict the
- address register to M16_REGS for MIPS16.
- (BUILTIN_AVAIL_MIPS16E2): Defined a new macro.
- (AVAIL_MIPS16E2_OR_NON_MIPS16): Same as above.
- (AVAIL_NON_MIPS16 (cache..)): Update to
- AVAIL_MIPS16E2_OR_NON_MIPS16.
- * config/mips/mips.h (ISA_HAS_CACHE): Add clause for ISA_HAS_MIPS16E2.
- * config/mips/mips.md (mips_cache): Mark as extended MIPS16.
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause
- for ISA_HAS_MIPS16E2.
- (ISA_HAS_SYNC): Same as above.
- (ISA_HAS_LL_SC): Same as above.
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/mips.cc(mips_expand_ins_as_unaligned_store):
- Add logics for generating instruction.
- * config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2.
- * config/mips/mips.md(mov_<load>l): Generates instructions.
- (mov_<load>r): Same as above.
- (mov_<store>l): Adjusted for the conditions above.
- (mov_<store>r): Same as above.
- (mov_<store>l_mips16e2): Add machine description for `define_insn mov_<store>l_mips16e2`.
- (mov_<store>r_mips16e2): Add machine description for `define_insn mov_<store>r_mips16e2`.
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction.
- (mips_const_insns): Same as above.
- (mips_output_move): Same as above.
- (mips_output_function_prologue): Same as above.
- * config/mips/mips.md: Same as above
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/constraints.md(Yz): New constraints for mips16e2.
- * config/mips/mips-protos.h(mips_bit_clear_p): Declared new function.
- (mips_bit_clear_info): Same as above.
- * config/mips/mips.cc(mips_bit_clear_info): New function for
- generating instructions.
- (mips_bit_clear_p): Same as above.
- * config/mips/mips.h(ISA_HAS_EXT_INS): Add clause for ISA_HAS_MIPS16E2.
- * config/mips/mips.md(extended_mips16): Generates EXT and INS instructions.
- (*and<mode>3): Generates INS instruction.
- (*and<mode>3_mips16): Generates EXT, INS and ANDI instructions.
- (ior<mode>3): Add logics for ORI instruction.
- (*ior<mode>3_mips16_asmacro): Generates ORI instrucion.
- (*ior<mode>3_mips16): Add logics for XORI instruction.
- (*xor<mode>3_mips16): Generates XORI instrucion.
- (*extzv<mode>): Add logics for EXT instruction.
- (*insv<mode>): Add logics for INS instruction.
- * config/mips/predicates.md(bit_clear_operand): New predicate for
- generating bitwise instructions.
- (and_reg_operand): Add logics for generating bitwise instructions.
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/mips.cc(mips_regno_mode_ok_for_base_p): Generate instructions
- that uses global pointer register.
- (mips16_unextended_reference_p): Same as above.
- (mips_pic_base_register): Same as above.
- (mips_init_relocs): Same as above.
- * config/mips/mips.h(MIPS16_GP_LOADS): Defined a new macro.
- (GLOBAL_POINTER_REGNUM): Moved to machine description `mips.md`.
- * config/mips/mips.md(GLOBAL_POINTER_REGNUM): Moved to here from above.
- (*lowsi_mips16_gp):New `define_insn *low<mode>_mips16`.
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2.
- * config/mips/mips.md(*mov<GPR:mode>_on_<MOVECC:mode>): Add logics for MOVx insts.
- (*mov<GPR:mode>_on_<MOVECC:mode>_mips16e2): Generate MOVx instruction.
- (*mov<GPR:mode>_on_<GPR2:mode>_ne): Add logics for MOVx insts.
- (*mov<GPR:mode>_on_<GPR2:mode>_ne_mips16e2): Generate MOVx instruction.
- * config/mips/predicates.md(reg_or_0_operand_mips16e2): New predicate for MOVx insts.
-
-2023-07-03 Jie Mei <jie.mei@oss.cipunited.com>
-
- * config/mips/mips.cc(mips_file_start): Add mips16e2 info
- for output file.
- * config/mips/mips.h(__mips_mips16e2): Defined a new
- predefine macro.
- (ISA_HAS_MIPS16E2): Defined a new macro.
- (ASM_SPEC): Pass mmips16e2 to the assembler.
- * config/mips/mips.opt: Add -m(no-)mips16e2 option.
- * config/mips/predicates.md: Add clause for TARGET_MIPS16E2.
- * doc/invoke.texi: Add -m(no-)mips16e2 option..
-
-2023-07-02 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/110508
- * tree-ssa-math-opts.cc (match_uaddc_usubc): Only replace re2 with
- REALPART_EXPR opf nlhs if re2 is non-NULL.
-
-2023-07-02 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.cc (xtensa_match_CLAMPS_imms_p):
- Simplify.
- * config/xtensa/xtensa.md (*xtensa_clamps):
- Add TARGET_MINMAX to the condition.
-
-2023-07-02 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.md (*eqne_INT_MIN):
- Add missing ":SI" to the match_operator.
-
-2023-07-02 Iain Sandoe <iain@sandoe.co.uk>
-
- PR target/108743
- * config/darwin.opt: Add fconstant-cfstrings alias to
- mconstant-cfstrings.
- * doc/invoke.texi: Amend invocation descriptions to reflect
- that the fconstant-cfstrings is a target-option alias and to
- add the missing mconstant-cfstrings option description to the
- Darwin section.
-
-2023-07-01 Jan Hubicka <jh@suse.cz>
-
- * tree-cfg.cc (gimple_duplicate_sese_region): Add elliminated_edge
- parmaeter; update profile.
- * tree-cfg.h (gimple_duplicate_sese_region): Update prototype.
- * tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Rename to ...
- (static_loop_exit): ... this; return the edge to be elliminated.
- (ch_base::copy_headers): Handle profile updating for eliminated exits.
-
-2023-07-01 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-features.cc (compute_convert_gain): Provide
- gains/costs for ROTATE and ROTATERT (by an integer constant).
- (general_scalar_chain::convert_rotate): New helper function to
- convert a DImode or SImode rotation by an integer constant into
- SSE vector form.
- (general_scalar_chain::convert_insn): Call the new convert_rotate
- for ROTATE and ROTATERT.
- (general_scalar_to_vector_candidate_p): Consider ROTATE and
- ROTATERT to be candidates if the second operand is an integer
- constant, valid for a rotation (or shift) in the given mode.
- * config/i386/i386-features.h (general_scalar_chain): Add new
- helper method convert_rotate.
-
-2023-07-01 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/103680
- * cfg.cc (update_bb_profile_for_threading): Fix profile update;
- make message clearer.
-
-2023-06-30 Qing Zhao <qing.zhao@oracle.com>
-
- PR tree-optimization/101832
- * tree-object-size.cc (addr_object_size): Handle structure/union type
- when it has flexible size.
-
-2023-06-30 Eric Botcazou <ebotcazou@adacore.com>
-
- * gimple-fold.cc (fold_array_ctor_reference): Fix head comment.
- (fold_nonarray_ctor_reference): Likewise. Specifically deal
- with integral bit-fields.
- (fold_ctor_reference): Make sure that the constructor uses the
- native storage order.
-
-2023-06-30 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/109849
- * predict.cc (estimate_bb_frequencies): Turn to static function.
- (expr_expected_value_1): Fix handling of binary expressions with
- predicted values.
- * predict.def (PRED_MALLOC_NONNULL): Move later in the priority queue.
- (PRED_BUILTIN_EXPECT_WITH_PROBABILITY): Move to almost top of the priority
- queue.
- * predict.h (estimate_bb_frequencies): No longer declare it.
-
-2023-06-30 Uros Bizjak <ubizjak@gmail.com>
-
- * fold-const.h (multiple_of_p): Change return type from int to bool.
- * fold-const.cc (split_tree): Change negl_p, neg_litp_p,
- neg_conp_p and neg_var_p variables to bool.
- (const_binop): Change sat_p variable to bool.
- (merge_ranges): Change no_overlap variable to bool.
- (extract_muldiv_1): Change same_p variable to bool.
- (tree_swap_operands_p): Update function body for bool return type.
- (fold_truth_andor): Change commutative variable to bool.
- (multiple_of_p): Change return type
- from int to void and adjust function body accordingly.
- * optabs.h (expand_twoval_unop): Change return type from int to bool.
- (expand_twoval_binop): Ditto.
- (can_compare_p): Ditto.
- (have_add2_insn): Ditto.
- (have_addptr3_insn): Ditto.
- (have_sub2_insn): Ditto.
- (have_insn_for): Ditto.
- * optabs.cc (add_equal_note): Ditto.
- (widen_operand): Change no_extend argument from int to bool.
- (expand_binop): Ditto.
- (expand_twoval_unop): Change return type
- from int to void and adjust function body accordingly.
- (expand_twoval_binop): Ditto.
- (can_compare_p): Ditto.
- (have_add2_insn): Ditto.
- (have_addptr3_insn): Ditto.
- (have_sub2_insn): Ditto.
- (have_insn_for): Ditto.
-
-2023-06-30 Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com>
-
- * config/aarch64/aarch64-simd.md
- (vec_widen_<su>abdl_lo_<mode>, vec_widen_<su>abdl_hi_<mode>):
- Expansions for abd vec widen optabs.
- (aarch64_<su>abdl<mode>_insn): VQW based abdl RTL.
- * config/aarch64/iterators.md (USMAX_EXT): Code attributes
- that give the appropriate extend RTL for the max RTL.
-
-2023-06-30 Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com>
-
- * internal-fn.def (VEC_WIDEN_ABD): New internal hilo optab.
- * optabs.def (vec_widen_sabd_optab,
- vec_widen_sabd_hi_optab, vec_widen_sabd_lo_optab,
- vec_widen_sabd_odd_even, vec_widen_sabd_even_optab,
- vec_widen_uabd_optab,
- vec_widen_uabd_hi_optab, vec_widen_uabd_lo_optab,
- vec_widen_uabd_odd_even, vec_widen_uabd_even_optab):
- New optabs.
- * doc/md.texi: Document them.
- * tree-vect-patterns.cc (vect_recog_abd_pattern): Update to
- to build a VEC_WIDEN_ABD call if the input precision is smaller
- than the precision of the output.
- (vect_recog_widen_abd_pattern): Should an ABD expression be
- found preceeding an extension, replace the two with a
- VEC_WIDEN_ABD.
-
-2023-06-30 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector.md: Refactor the common condition.
-
-2023-06-30 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110496
- * gimple-ssa-store-merging.cc (find_bswap_or_nop_1): Re-order
- verifying and TYPE_PRECISION query for the BIT_FIELD_REF case.
-
-2023-06-30 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110489
- * statistics.cc (curr_statistics_hash): Add argument
- indicating whether we should allocate the hash.
- (statistics_fini_pass): If the hash isn't allocated
- only print the summary header.
-
-2023-06-30 Segher Boessenkool <segher@kernel.crashing.org>
- Thomas Schwinge <thomas@codesourcery.com>
-
- * config/nvptx/nvptx.cc (TARGET_LRA_P): Remove.
-
-2023-06-30 Jovan Dmitrović <jovan.dmitrovic@syrmia.com>
-
- PR target/109435
- * config/mips/mips.cc (mips_function_arg_alignment): Returns
- the alignment of function argument. In case of typedef type,
- it returns the aligment of the aliased type.
- (mips_function_arg_boundary): Relocated calculation of the
- aligment of function arguments.
-
-2023-06-29 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/109849
- * ipa-fnsummary.cc (decompose_param_expr): Skip
- functions returning its parameter.
- (set_cond_stmt_execution_predicate): Return early
- if predicate was constructed.
-
-2023-06-29 Qing Zhao <qing.zhao@oracle.com>
-
- PR c/77650
- * doc/extend.texi: Document GCC extension on a structure containing
- a flexible array member to be a member of another structure.
-
-2023-06-29 Qing Zhao <qing.zhao@oracle.com>
-
- * print-tree.cc (print_node): Print new bit type_include_flexarray.
- * tree-core.h (struct tree_type_common): Use bit no_named_args_stdarg_p
- as type_include_flexarray for RECORD_TYPE or UNION_TYPE.
- * tree-streamer-in.cc (unpack_ts_type_common_value_fields): Stream
- in bit no_named_args_stdarg_p properly for its corresponding type.
- * tree-streamer-out.cc (pack_ts_type_common_value_fields): Stream
- out bit no_named_args_stdarg_p properly for its corresponding type.
- * tree.h (TYPE_INCLUDES_FLEXARRAY): New macro TYPE_INCLUDES_FLEXARRAY.
-
-2023-06-29 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-vrp.cc (maybe_set_nonzero_bits): Move from here...
- * tree-ssa-dom.cc (maybe_set_nonzero_bits): ...to here.
- * tree-vrp.h (maybe_set_nonzero_bits): Remove.
-
-2023-06-29 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (frange::set): Do not call verify_range.
- (frange::normalize_kind): Verify range.
- (frange::union_nans): Do not call verify_range.
- (frange::union_): Same.
- (frange::intersect): Same.
- (irange::irange_single_pair_union): Call normalize_kind if
- necessary.
- (irange::union_): Same.
- (irange::intersect): Same.
- (irange::set_range_from_nonzero_bits): Verify range.
- (irange::set_nonzero_bits): Call normalize_kind if necessary.
- (irange::get_nonzero_bits): Tweak comment.
- (irange::intersect_nonzero_bits): Call normalize_kind if
- necessary.
- (irange::union_nonzero_bits): Same.
- * value-range.h (irange::normalize_kind): Verify range.
-
-2023-06-29 Uros Bizjak <ubizjak@gmail.com>
-
- * cselib.h (rtx_equal_for_cselib_1):
- Change return type from int to bool.
- (references_value_p): Ditto.
- (rtx_equal_for_cselib_p): Ditto.
- * expr.h (can_store_by_pieces): Ditto.
- (try_casesi): Ditto.
- (try_tablejump): Ditto.
- (safe_from_p): Ditto.
- * sbitmap.h (bitmap_equal_p): Ditto.
- * cselib.cc (references_value_p): Change return type
- from int to void and adjust function body accordingly.
- (rtx_equal_for_cselib_1): Ditto.
- * expr.cc (is_aligning_offset): Ditto.
- (can_store_by_pieces): Ditto.
- (mostly_zeros_p): Ditto.
- (all_zeros_p): Ditto.
- (safe_from_p): Ditto.
- (is_aligning_offset): Ditto.
- (try_casesi): Ditto.
- (try_tablejump): Ditto.
- (store_constructor): Change "need_to_clear" and
- "const_bounds_p" variables to bool.
- * sbitmap.cc (bitmap_equal_p): Change return type from int to bool.
-
-2023-06-29 Robin Dapp <rdapp@ventanamicro.com>
-
- * tree-ssa-math-opts.cc (divmod_candidate_p): Use
- element_precision.
-
-2023-06-29 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110460
- * tree-vect-stmts.cc (get_related_vectype_for_scalar_type):
- Only allow integral, pointer and scalar float type scalar_type.
-
-2023-06-29 Lili Cui <lili.cui@intel.com>
-
- PR tree-optimization/110148
- * tree-ssa-reassoc.cc (rewrite_expr_tree_parallel): Handle loop-carried
- ops in this function.
-
-2023-06-29 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110452
- * expr.cc (store_constructor): Handle uniform boolean
- vectors with integer mode specially.
-
-2023-06-29 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110461
- * match.pd (bitop (convert@2 @0) (convert?@3 @1)): Disable
- for VECTOR_TYPE_P.
-
-2023-06-29 Richard Sandiford <richard.sandiford@arm.com>
-
- * vec.h (gt_pch_nx): Add overloads for va_gc_atomic.
- (array_slice): Relax va_gc constructor to handle all vectors
- with a vl_embed layout.
-
-2023-06-29 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv.cc (riscv_emit_mode_set): Add emit for FRM.
- (riscv_mode_needed): Likewise.
- (riscv_entity_mode_after): Likewise.
- (riscv_mode_after): Likewise.
- (riscv_mode_entry): Likewise.
- (riscv_mode_exit): Likewise.
- * config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Add number
- for FRM.
- * config/riscv/riscv.md: Add FRM register.
- * config/riscv/vector-iterators.md: Add FRM type.
- * config/riscv/vector.md (frm_mode): Define new attr for FRM mode.
- (fsrm): Define new insn for fsrm instruction.
-
-2023-06-29 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-protos.h (enum floating_point_rounding_mode):
- Add macro for static frm min and max.
- * config/riscv/riscv-vector-builtins-bases.cc
- (class binop_frm): New class for floating-point with frm.
- (BASE): Add vfadd for frm.
- * config/riscv/riscv-vector-builtins-bases.h: Likewise.
- * config/riscv/riscv-vector-builtins-functions.def
- (vfadd_frm): Likewise.
- * config/riscv/riscv-vector-builtins-shapes.cc
- (struct alu_frm_def): New struct for alu with frm.
- (SHAPE): Add alu with frm.
- * config/riscv/riscv-vector-builtins-shapes.h: Likewise.
- * config/riscv/riscv-vector-builtins.cc
- (function_checker::report_out_of_range_and_not): New function
- for report out of range and not val.
- (function_checker::require_immediate_range_or): New function
- for checking in range or one val.
- * config/riscv/riscv-vector-builtins.h: Add function decl.
-
-2023-06-29 Cui, Lili <lili.cui@intel.com>
-
- * common/config/i386/cpuinfo.h (get_intel_cpu): Remove model value 0xa8
- from Rocketlake, move model value 0xbf from Alderlake to Raptorlake.
-
-2023-06-28 Hans-Peter Nilsson <hp@axis.com>
-
- PR target/110144
- * config/cris/cris.cc (cris_postdbr_cmpelim): Don't apply PATTERN
- to insn before validating it.
-
-2023-06-28 Jan Hubicka <jh@suse.cz>
-
- PR middle-end/110334
- * ipa-fnsummary.h (ipa_fn_summary): Add
- safe_to_inline_to_always_inline.
- * ipa-inline.cc (can_early_inline_edge_p): ICE
- if SSA is not built; do cycle checking for
- always_inline functions.
- (inline_always_inline_functions): Be recrusive;
- watch for cycles; do not updat overall summary.
- (early_inliner): Do not give up on always_inlines.
- * ipa-utils.cc (ipa_reverse_postorder): Do not skip
- always inlines.
-
-2023-06-28 Uros Bizjak <ubizjak@gmail.com>
-
- * output.h (leaf_function_p): Change return type from int to bool.
- (final_forward_branch_p): Ditto.
- (only_leaf_regs_used): Ditto.
- (maybe_assemble_visibility): Ditto.
- * varasm.h (supports_one_only): Ditto.
- * rtl.h (compute_alignments): Change return type from int to void.
- * final.cc (app_on): Change return type from int to bool.
- (compute_alignments): Change return type from int to void
- and adjust function body accordingly.
- (shorten_branches): Change "something_changed" variable
- type from int to bool.
- (leaf_function_p): Change return type from int to bool
- and adjust function body accordingly.
- (final_forward_branch_p): Ditto.
- (only_leaf_regs_used): Ditto.
- * varasm.cc (contains_pointers_p): Change return type from
- int to bool and adjust function body accordingly.
- (compare_constant): Ditto.
- (maybe_assemble_visibility): Ditto.
- (supports_one_only): Ditto.
-
-2023-06-28 Manolis Tsamis <manolis.tsamis@vrull.eu>
-
- PR debug/110308
- * regcprop.cc (maybe_mode_change): Check stack_pointer_rtx mode.
- (maybe_copy_reg_attrs): New function.
- (find_oldest_value_reg): Use maybe_copy_reg_attrs.
- (copyprop_hardreg_forward_1): Ditto.
-
-2023-06-28 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110434
- * tree-nrv.cc (pass_nrv::execute): Remove CLOBBERs of
- VAR we replace with <retval>.
-
-2023-06-28 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110451
- * tree-ssa-loop-im.cc (stmt_cost): [VEC_]COND_EXPR and
- tcc_comparison are expensive.
-
-2023-06-28 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_expand_branch): Also use ptest
- for TImode comparisons on 32-bit architectures.
- * config/i386/i386.md (cbranch<mode>4): Change from SDWIM to
- SWIM1248x to exclude/avoid TImode being conditional on -m64.
- (cbranchti4): New define_expand for TImode on both TARGET_64BIT
- and/or with TARGET_SSE4_1.
- * config/i386/predicates.md (ix86_timode_comparison_operator):
- New predicate that depends upon TARGET_64BIT.
- (ix86_timode_comparison_operand): Likewise.
-
-2023-06-28 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/78794
- * config/i386/i386-features.cc (compute_convert_gain): Provide
- more accurate gains for conversion of scalar comparisons to
- PTEST.
-
-2023-06-28 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110443
- * tree-vect-slp.cc (vect_build_slp_tree_1): Reject non-grouped
- gather loads.
-
-2023-06-28 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * config/rs6000/rs6000.md (peephole2 for compare_and_move): New.
- (peephole2 for move_and_compare): New.
- (mode_iterator WORD): New. Set the mode to SI/DImode by
- TARGET_POWERPC64.
- (*mov<mode>_internal2): Change the mode iterator from P to WORD.
- (split pattern for compare_and_move): Likewise.
-
-2023-06-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (*double_widen_fma<mode>): New pattern.
- (*single_widen_fma<mode>): Ditto.
-
-2023-06-28 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/104124
- * config/rs6000/altivec.md (*altivec_vupkhs<VU_char>_direct): Rename
- to...
- (altivec_vupkhs<VU_char>_direct): ...this.
- * config/rs6000/predicates.md (vspltisw_vupkhsw_constant_split): New
- predicate to test if a constant can be loaded with vspltisw and
- vupkhsw.
- (easy_vector_constant): Call vspltisw_vupkhsw_constant_p to Check if
- a vector constant can be synthesized with a vspltisw and a vupkhsw.
- * config/rs6000/rs6000-protos.h (vspltisw_vupkhsw_constant_p):
- Declare.
- * config/rs6000/rs6000.cc (vspltisw_vupkhsw_constant_p): New
- function to return true if OP mode is V2DI and can be synthesized
- with vupkhsw and vspltisw.
- * config/rs6000/vsx.md (*vspltisw_v2di_split): New insn to load up
- constants with vspltisw and vupkhsw.
-
-2023-06-28 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/110377
- * ipa-prop.cc (ipa_compute_jump_functions_for_edge): Pass statement to
- the ranger query.
- (ipa_analyze_node): Enable ranger.
-
-2023-06-28 Richard Biener <rguenther@suse.de>
-
- * tree.h (TYPE_PRECISION): Check for non-VECTOR_TYPE.
- (TYPE_PRECISION_RAW): Provide raw access to the precision
- field.
- * tree.cc (verify_type_variant): Compare TYPE_PRECISION_RAW.
- (gimple_canonical_types_compatible_p): Likewise.
- * tree-streamer-out.cc (pack_ts_type_common_value_fields):
- Stream TYPE_PRECISION_RAW.
- * tree-streamer-in.cc (unpack_ts_type_common_value_fields):
- Likewise.
- * lto-streamer-out.cc (hash_tree): Hash TYPE_PRECISION_RAW.
-
-2023-06-28 Alexandre Oliva <oliva@adacore.com>
-
- * doc/extend.texi (zero-call-used-regs): Document leafy and
- variants thereof.
- * flag-types.h (zero_regs_flags): Add LEAFY_MODE, as well as
- LEAFY and variants.
- * function.cc (gen_call_ued_regs_seq): Set only_used for leaf
- functions in leafy mode.
- * opts.cc (zero_call_used_regs_opts): Add leafy and variants.
-
-2023-06-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Adapt expand.
- * config/riscv/vector.md (@pred_single_widen_<plus_minus:optab><mode>):
- Remove.
- (@pred_single_widen_add<mode>): New pattern.
- (@pred_single_widen_sub<mode>): New pattern.
-
-2023-06-28 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386.cc (ix86_invalid_conversion): New function.
- (TARGET_INVALID_CONVERSION): Define as
- ix86_invalid_conversion.
-
-2023-06-27 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<optab><vnconvert><mode>2): New
- expander.
- (<float_cvt><vnconvert><mode>2): Ditto.
- (<optab><mode><vnconvert>2): Ditto.
- (<float_cvt><mode><vnconvert>2): Ditto.
- * config/riscv/vector-iterators.md: Add vnconvert.
-
-2023-06-27 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (extend<v_double_trunc><mode>2): New
- expander.
- (extend<v_quad_trunc><mode>2): Ditto.
- (trunc<mode><v_double_trunc>2): Ditto.
- (trunc<mode><v_quad_trunc>2): Ditto.
- * config/riscv/vector-iterators.md: Add VQEXTF and HF to
- V_QUAD_TRUNC and v_quad_trunc.
-
-2023-06-27 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<float_cvt><vconvert><mode>2): New
- expander.
-
-2023-06-27 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (copysign<mode>3): Add expander.
- (xorsign<mode>3): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc (class vfsgnjn):
- New class.
- * config/riscv/vector-iterators.md (copysign): Remove ncopysign.
- (xorsign): Ditto.
- (n): Ditto.
- (x): Ditto.
- * config/riscv/vector.md (@pred_ncopysign<mode>): Split off.
- (@pred_ncopysign<mode>_scalar): Ditto.
-
-2023-06-27 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md: VF_AUTO -> VF.
- * config/riscv/vector-iterators.md: Introduce VF_ZVFHMIN,
- VWEXTF_ZVFHMIN and use TARGET_ZVFH in VWCONVERTI, VHF and
- VHF_LMUL1.
- * config/riscv/vector.md: Use new iterators.
-
-2023-06-27 Robin Dapp <rdapp@ventanamicro.com>
-
- * match.pd: Use element_mode and check if target supports
- operation with new type.
-
-2023-06-27 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svdupq_impl::fold_nonconst_dupq): New method.
- (svdupq_impl::fold): Call fold_nonconst_dupq.
-
-2023-06-27 Andrew Pinski <apinski@marvell.com>
-
- PR middle-end/110420
- PR middle-end/103979
- PR middle-end/98619
- * gimplify.cc (gimplify_asm_expr): Mark asm with labels as volatile.
-
-2023-06-27 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-cp.cc (decide_whether_version_node): Adjust comment.
- * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Adjust
- for Value_Range.
- (set_switch_stmt_execution_predicate): Same.
- * ipa-prop.cc (ipa_compute_jump_functions_for_edge): Same.
-
-2023-06-27 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Adjust for use with
- ipa_vr instead of value_range.
- (gt_pch_nx): Same.
- (gt_ggc_mx): Same.
- (ipa_get_value_range): Same.
- * value-range.cc (gt_pch_nx): Move to ipa-prop.cc and adjust for
- ipa_vr.
- (gt_ggc_mx): Same.
-
-2023-06-27 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-cp.cc (ipa_vr_operation_and_type_effects): New.
- * ipa-prop.cc (ipa_get_value_range): Adjust for ipa_vr.
- (ipa_set_jfunc_vr): Take a range.
- (ipa_compute_jump_functions_for_edge): Pass range to
- ipa_set_jfunc_vr.
- (ipa_write_jump_function): Call streamer write helper.
- (ipa_read_jump_function): Call streamer read helper.
- * ipa-prop.h (class ipa_vr): Change m_vr to an ipa_vr.
-
-2023-06-27 Richard Sandiford <richard.sandiford@arm.com>
-
- * gengtype-parse.cc (consume_until_comma_or_eos): Parse "= { ... }"
- as a probable initializer rather than a probable complete statement.
-
-2023-06-27 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/96208
- * tree-vect-slp.cc (vect_build_slp_tree_1): Allow
- a non-grouped load if it is the same for all lanes.
- (vect_build_slp_tree_2): Handle not grouped loads.
- (vect_optimize_slp_pass::remove_redundant_permutations):
- Likewise.
- (vect_transform_slp_perm_load_1): Likewise.
- * tree-vect-stmts.cc (vect_model_load_cost): Likewise.
- (get_group_load_store_type): Likewise. Handle
- invariant accesses.
- (vectorizable_load): Likewise.
-
-2023-06-27 liuhongt <hongtao.liu@intel.com>
-
- PR rtl-optimization/110237
- * config/i386/sse.md (<avx512>_store<mode>_mask): Refine with
- UNSPEC_MASKMOV.
- (maskstore<mode><avx512fmaskmodelower): Ditto.
- (*<avx512>_store<mode>_mask): New define_insn, it's renamed
- from original <avx512>_store<mode>_mask.
-
-2023-06-27 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386-features.cc (pass_insert_vzeroupper:gate):
- Move flag_expensive_optimizations && !optimize_size to ..
- * config/i386/i386-options.cc (ix86_option_override_internal):
- .. this, it makes -mvzeroupper independent of optimization
- level, but still keeps the behavior of architecture
- tuning(emit_vzeroupper) unchanged.
-
-2023-06-27 liuhongt <hongtao.liu@intel.com>
-
- PR target/82735
- * config/i386/i386.cc (ix86_avx_u127_mode_needed): Don't emit
- vzeroupper for vzeroupper call_insn.
-
-2023-06-27 Andrew Pinski <apinski@marvell.com>
-
- * doc/extend.texi (__builtin_alloca_with_align_and_max): Fix
- defbuiltin usage.
-
-2023-06-27 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_const_vector): Fix stepped vector
- with base != 0.
-
-2023-06-26 Andrew Pinski <apinski@marvell.com>
-
- * doc/extend.texi (access attribute): Add
- cindex for it.
- (interrupt/interrupt_handler attribute):
- Likewise.
-
-2023-06-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_sqrshrun_n<mode>_insn):
- Use <DWI> instead of <V2XWIDE>.
- (aarch64_sqrshrun_n<mode>): Likewise.
-
-2023-06-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_const_vec_rsra_rnd_imm_p):
- Rename to...
- (aarch64_rnd_imm_p): ... This.
- * config/aarch64/predicates.md (aarch64_simd_rsra_rnd_imm_vec):
- Rename to...
- (aarch64_int_rnd_operand): ... This.
- (aarch64_simd_rshrn_imm_vec): Delete.
- * config/aarch64/aarch64-simd.md (aarch64_<sra_op>rsra_n<mode>_insn):
- Adjust for the above.
- (aarch64_<sra_op>rshr_n<mode><vczle><vczbe>_insn): Likewise.
- (*aarch64_<shrn_op>rshrn_n<mode>_insn): Likewise.
- (*aarch64_sqrshrun_n<mode>_insn<vczle><vczbe>): Likewise.
- (aarch64_sqrshrun_n<mode>_insn): Likewise.
- (aarch64_<shrn_op>rshrn2_n<mode>_insn_le): Likewise.
- (aarch64_<shrn_op>rshrn2_n<mode>_insn_be): Likewise.
- (aarch64_sqrshrun2_n<mode>_insn_le): Likewise.
- (aarch64_sqrshrun2_n<mode>_insn_be): Likewise.
- * config/aarch64/aarch64.cc (aarch64_const_vec_rsra_rnd_imm_p):
- Rename to...
- (aarch64_rnd_imm_p): ... This.
-
-2023-06-26 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config/s390/s390.cc (s390_encode_section_info): Set
- SYMBOL_FLAG_SET_NOTALIGN2 only if the symbol has explicitely been
- misaligned.
-
-2023-06-26 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/109849
- * tree-ssa-dce.cc (make_forwarders_with_degenerate_phis): Fix profile
- count of newly constructed forwarder block.
-
-2023-06-26 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * doc/optinfo.texi: Fix "steam" -> "stream".
-
-2023-06-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-ssa-dse.cc (initialize_ao_ref_for_dse): Add LEN_MASK_STORE and
- fix LEN_STORE.
- (dse_optimize_stmt): Add LEN_MASK_STORE.
-
-2023-06-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * gimple-fold.cc (gimple_fold_partial_load_store_mem_ref): Fix gimple
- fold of LOAD/STORE with length.
-
-2023-06-26 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (compute_operand1_and_operand2_range):
- Check for interdependence between operands 1 and 2.
-
-2023-06-26 Richard Sandiford <richard.sandiford@arm.com>
-
- * tree-vect-stmts.cc (vectorizable_conversion): Take multi_step_cvt
- into account when costing non-widening/truncating conversions.
-
-2023-06-26 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110381
- * tree-vect-slp.cc (vect_optimize_slp_pass::start_choosing_layouts):
- Materialize permutes before fold-left reductions.
-
-2023-06-26 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.h: Remove duplicated decl.
-
-2023-06-26 Richard Biener <rguenther@suse.de>
-
- * varasm.cc (initializer_constant_valid_p_1): Also
- constrain the type of value to be scalar integral
- before dispatching to narrowing_initializer_constant_valid_p.
-
-2023-06-26 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-scopedtables.cc (hashable_expr_equal_p):
- Use element_precision.
-
-2023-06-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (vcond<V:mode><VI:mode>): Remove redundant
- vcond patterns.
- (vcondu<V:mode><VI:mode>): Ditto.
- * config/riscv/riscv-protos.h (expand_vcond): Ditto.
- * config/riscv/riscv-v.cc (expand_vcond): Ditto.
-
-2023-06-26 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110392
- * gimple-predicate-analysis.cc (uninit_analysis::is_use_guarded):
- Do early exits on true/false predicate only after normalization.
-
-2023-06-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-ssa-sccvn.cc (vn_reference_lookup_3): Change name "len" into
- "length".
-
-2023-06-26 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386.md (peephole2): Simplify zeroing a register
- followed by an IOR, XOR or PLUS operation on it, into a move.
- (*ashl<dwi>3_doubleword_highpart): New define_insn_and_split to
- eliminate (and hide from reload) unnecessary word to doubleword
- extensions that are followed by left shifts by sufficiently large,
- but valid, bit counts.
-
-2023-06-26 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/110371
- PR tree-optimization/110018
- * tree-vect-stmts.cc (vectorizable_conversion): Use cvt_op to
- save intermediate type operand instead of "subtle" vec_dest
- for case NONE.
-
-2023-06-26 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/110371
- PR tree-optimization/110018
- * tree-vect-stmts.cc (vectorizable_conversion): Don't use
- intermiediate type for FIX_TRUNC_EXPR when ftrapping-math.
-
-2023-06-26 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386-options.cc (ix86_valid_target_attribute_tree):
- Override tune_string with arch_string if tune_string is not
- explicitly specified.
-
-2023-06-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (vector_insn_info::parse_insn): Ehance
- AVL propagation.
- * config/riscv/riscv-vsetvl.h: New function.
-
-2023-06-25 Li Xu <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: change emit_insn to
- emit_move_insn
-
-2023-06-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (len_load_<mode>): Remove.
- (len_maskload<mode><vm>): Remove.
- (len_store_<mode>): New pattern.
- (len_maskstore<mode><vm>): New pattern.
- * config/riscv/predicates.md (autovec_length_operand): New predicate.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- (expand_load_store): New function.
- * config/riscv/riscv-v.cc (emit_vlmax_masked_insn): Ditto.
- (emit_nonvlmax_masked_insn): Ditto.
- (expand_load_store): Ditto.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_contiguous_store_insn): Add avl_type operand
- into pred_store.
- * config/riscv/vector.md: Ditto.
-
-2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * internal-fn.cc (expand_partial_store_optab_fn): Fix bug of BIAS
- argument index.
-
-2023-06-25 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector.md: Revert.
-
-2023-06-25 Pan Li <pan2.li@intel.com>
-
- * config/riscv/genrvv-type-indexer.cc (valid_type): Revert changes.
- * config/riscv/riscv-modes.def (RVV_TUPLE_MODES): Ditto.
- (ADJUST_ALIGNMENT): Ditto.
- (RVV_TUPLE_PARTIAL_MODES): Ditto.
- (ADJUST_NUNITS): Ditto.
- * config/riscv/riscv-vector-builtins-types.def (vfloat16mf4x2_t): Ditto.
- (vfloat16mf4x3_t): Ditto.
- (vfloat16mf4x4_t): Ditto.
- (vfloat16mf4x5_t): Ditto.
- (vfloat16mf4x6_t): Ditto.
- (vfloat16mf4x7_t): Ditto.
- (vfloat16mf4x8_t): Ditto.
- (vfloat16mf2x2_t): Ditto.
- (vfloat16mf2x3_t): Ditto.
- (vfloat16mf2x4_t): Ditto.
- (vfloat16mf2x5_t): Ditto.
- (vfloat16mf2x6_t): Ditto.
- (vfloat16mf2x7_t): Ditto.
- (vfloat16mf2x8_t): Ditto.
- (vfloat16m1x2_t): Ditto.
- (vfloat16m1x3_t): Ditto.
- (vfloat16m1x4_t): Ditto.
- (vfloat16m1x5_t): Ditto.
- (vfloat16m1x6_t): Ditto.
- (vfloat16m1x7_t): Ditto.
- (vfloat16m1x8_t): Ditto.
- (vfloat16m2x2_t): Ditto.
- (vfloat16m2x3_t): Diito.
- (vfloat16m2x4_t): Diito.
- (vfloat16m4x2_t): Diito.
- * config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Ditto.
- (vfloat16mf4x3_t): Ditto.
- (vfloat16mf4x4_t): Ditto.
- (vfloat16mf4x5_t): Ditto.
- (vfloat16mf4x6_t): Ditto.
- (vfloat16mf4x7_t): Ditto.
- (vfloat16mf4x8_t): Ditto.
- (vfloat16mf2x2_t): Ditto.
- (vfloat16mf2x3_t): Ditto.
- (vfloat16mf2x4_t): Ditto.
- (vfloat16mf2x5_t): Ditto.
- (vfloat16mf2x6_t): Ditto.
- (vfloat16mf2x7_t): Ditto.
- (vfloat16mf2x8_t): Ditto.
- (vfloat16m1x2_t): Ditto.
- (vfloat16m1x3_t): Ditto.
- (vfloat16m1x4_t): Ditto.
- (vfloat16m1x5_t): Ditto.
- (vfloat16m1x6_t): Ditto.
- (vfloat16m1x7_t): Ditto.
- (vfloat16m1x8_t): Ditto.
- (vfloat16m2x2_t): Ditto.
- (vfloat16m2x3_t): Ditto.
- (vfloat16m2x4_t): Ditto.
- (vfloat16m4x2_t): Ditto.
- * config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): Ditto.
- * config/riscv/riscv.md: Ditto.
- * config/riscv/vector-iterators.md: Ditto.
-
-2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * gimple-fold.cc (arith_overflowed_p): Apply LEN_MASK_{LOAD,STORE}.
- (gimple_fold_partial_load_store_mem_ref): Ditto.
- (gimple_fold_partial_store): Ditto.
- (gimple_fold_call): Ditto.
-
-2023-06-25 liuhongt <hongtao.liu@intel.com>
-
- PR target/110309
- * config/i386/sse.md (maskload<mode><avx512fmaskmodelower>):
- Refine pattern with UNSPEC_MASKLOAD.
- (maskload<mode><avx512fmaskmodelower>): Ditto.
- (*<avx512>_load<mode>_mask): Extend mode iterator to
- VI12HFBF_AVX512VL.
- (*<avx512>_load<mode>): Ditto.
-
-2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-ssa-alias.cc (call_may_clobber_ref_p_1): Add LEN_MASK_STORE.
-
-2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): Apply
- LEN_MASK_{LOAD,STORE}
-
-2023-06-25 yulong <shiyulong@iscas.ac.cn>
-
- * config/riscv/vector.md: Add float16 attr at sew、vlmul and ratio.
-
-2023-06-24 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386.md (*<code>qi_ext<mode>_3): New define_insn.
-
-2023-06-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (*fma<mode>): set clobber to Pmode in expand stage.
- (*fma<VI:mode><P:mode>): Ditto.
- (*fnma<mode>): Ditto.
- (*fnma<VI:mode><P:mode>): Ditto.
-
-2023-06-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (fma<mode>4): New pattern.
- (*fma<mode>): Ditto.
- (fnma<mode>4): Ditto.
- (*fnma<mode>): Ditto.
- (fms<mode>4): Ditto.
- (*fms<mode>): Ditto.
- (fnms<mode>4): Ditto.
- (*fnms<mode>): Ditto.
- * config/riscv/riscv-protos.h (emit_vlmax_fp_ternary_insn):
- New function.
- * config/riscv/riscv-v.cc (emit_vlmax_fp_ternary_insn): Ditto.
- * config/riscv/vector.md: Fix attribute bug.
-
-2023-06-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-ssa-loop-ivopts.cc (get_mem_type_for_internal_fn):
- Apply LEN_MASK_{LOAD,STORE}.
-
-2023-06-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-ssa-loop-ivopts.cc (get_alias_ptr_type_for_ptr_address):
- Add LEN_MASK_{LOAD,STORE}.
-
-2023-06-24 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-sarif.cc: Add #define INCLUDE_VECTOR.
- * diagnostic.cc: Likewise.
- * text-art/box-drawing.cc: Likewise.
- * text-art/canvas.cc: Likewise.
- * text-art/ruler.cc: Likewise.
- * text-art/selftests.cc: Likewise.
- * text-art/selftests.h (text_art::canvas): New forward decl.
- * text-art/style.cc: Add #define INCLUDE_VECTOR.
- * text-art/styled-string.cc: Likewise.
- * text-art/table.cc: Likewise.
- * text-art/table.h: Remove #include <vector>.
- * text-art/theme.cc: Add #define INCLUDE_VECTOR.
- * text-art/types.h: Check that INCLUDE_VECTOR is defined.
- Remove #include of <vector> and <string>.
- * text-art/widget.cc: Add #define INCLUDE_VECTOR.
- * text-art/widget.h: Remove #include <vector>.
-
-2023-06-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * internal-fn.cc (expand_partial_store_optab_fn): Adapt for LEN_MASK_STORE.
- (internal_load_fn_p): Add LEN_MASK_LOAD.
- (internal_store_fn_p): Add LEN_MASK_STORE.
- (internal_fn_mask_index): Add LEN_MASK_{LOAD,STORE}.
- (internal_fn_stored_value_index): Add LEN_MASK_STORE.
- (internal_len_load_store_bias): Add LEN_MASK_{LOAD,STORE}.
- * optabs-tree.cc (can_vec_mask_load_store_p): Adapt for LEN_MASK_{LOAD,STORE}.
- (get_len_load_store_mode): Ditto.
- * optabs-tree.h (can_vec_mask_load_store_p): Ditto.
- (get_len_load_store_mode): Ditto.
- * tree-vect-stmts.cc (check_load_store_for_partial_vectors): Ditto.
- (get_all_ones_mask): New function.
- (vectorizable_store): Apply LEN_MASK_{LOAD,STORE} into vectorizer.
- (vectorizable_load): Ditto.
-
-2023-06-23 Marek Polacek <polacek@redhat.com>
-
- * doc/cpp.texi (__cplusplus): Document value for -std=c++26 and
- -std=gnu++26. Document that for C++23, its value is 202302L.
- * doc/invoke.texi: Document -std=c++26 and -std=gnu++26.
- * dwarf2out.cc (highest_c_language): Handle GNU C++26.
- (gen_compile_unit_die): Likewise.
-
-2023-06-23 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-phiprop.cc (propagate_with_phi): Compute post dominators on
- demand.
- (pass_phiprop::execute): Do not compute it here; return
- update_ssa_only_virtuals if something changed.
- (pass_data_phiprop): Remove TODO_update_ssa from todos.
-
-2023-06-23 Michael Meissner <meissner@linux.ibm.com>
- Aaron Sawdey <acsawdey@linux.ibm.com>
-
- PR target/105325
- * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
- allowed prefixed lwa to be generated.
- * config/rs6000/fusion.md: Regenerate.
- * config/rs6000/predicates.md (ds_form_mem_operand): Delete.
- * config/rs6000/rs6000.md (prefixed attribute): Add support for load
- plus compare immediate fused insns.
- (maybe_prefixed): Likewise.
-
-2023-06-23 Roger Sayle <roger@nextmovesoftware.com>
-
- * simplify-rtx.cc (simplify_subreg): Optimize lowpart SUBREGs
- of ASHIFT to const0_rtx with sufficiently large shift count.
- Optimize highpart SUBREGs of ASHIFT as the shift operand when
- the shift count is the correct offset. Optimize SUBREGs of
- multi-word logic operations if the SUBREGs of both operands
- can be simplified.
-
-2023-06-23 Richard Biener <rguenther@suse.de>
-
- * varasm.cc (initializer_constant_valid_p_1): Only
- allow conversions between scalar floating point types.
-
-2023-06-23 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_assignment):
- Properly handle non-integral operands when analyzing
- conversions.
-
-2023-06-23 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- PR tree-optimization/110280
- * match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
- using build_vector_from_val with the element of input operand, and
- mask's type if operand and mask's types don't match.
-
-2023-06-23 Richard Biener <rguenther@suse.de>
-
- * fold-const.cc (tree_simple_nonnegative_warnv_p): Guard
- the truth_value_p case with !VECTOR_TYPE_P.
-
-2023-06-23 Richard Biener <rguenther@suse.de>
-
- * tree-vect-patterns.cc (vect_look_through_possible_promotion):
- Exit early when the type isn't scalar integral.
-
-2023-06-23 Richard Biener <rguenther@suse.de>
-
- * match.pd ((outertype)((innertype0)a+(innertype1)b)
- -> ((newtype)a+(newtype)b)): Use element_precision
- where appropriate.
-
-2023-06-23 Richard Biener <rguenther@suse.de>
-
- * fold-const.cc (fold_binary_loc): Use element_precision
- when trying (double)float1 CMP (double)float2 to
- float1 CMP float2 simplification.
- * match.pd: Likewise.
-
-2023-06-23 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_load): Avoid useless
- copies of VMAT_INVARIANT vectorized stmts, fix SLP support.
-
-2023-06-23 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vector_vector_composition_type):
- Handle composition of a vector from a number of elements that
- happens to match its number of lanes.
-
-2023-06-22 Marek Polacek <polacek@redhat.com>
-
- * configure.ac (--enable-host-bind-now): New check. Add
- -Wl,-z,now to LD_PICFLAG if --enable-host-bind-now.
- * configure: Regenerate.
- * doc/install.texi: Document --enable-host-bind-now.
-
-2023-06-22 Di Zhao OS <dizhao@os.amperecomputing.com>
-
- * config/aarch64/aarch64.cc: Change fma_reassoc_width for ampere1.
-
-2023-06-22 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110332
- * tree-ssa-phiprop.cc (propagate_with_phi): Always
- check aliasing with edge inserted loads.
-
-2023-06-22 Roger Sayle <roger@nextmovesoftware.com>
- Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_sse_ptest): Recognize
- expansion of ptestc with equal operands as producing const1_rtx.
- * config/i386/i386.cc (ix86_rtx_costs): Provide accurate cost
- estimates of UNSPEC_PTEST, where the ptest performs the PAND
- or PAND of its operands.
- * config/i386/sse.md (define_split): Transform CCCmode UNSPEC_PTEST
- of reg_equal_p operands into an x86_stc instruction.
- (define_split): Split pandn/ptestz/set{n?}e into ptestc/set{n?}c.
- (define_split): Similar to above for strict_low_part destinations.
- (define_split): Split pandn/ptestz/j{n?}e into ptestc/j{n?}c.
-
-2023-06-22 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/106626
- * Makefile.in (ANALYZER_OBJS): Add analyzer/access-diagram.o.
- * doc/invoke.texi (Wanalyzer-out-of-bounds): Add description of
- text art.
- (fanalyzer-debug-text-art): New.
-
-2023-06-22 David Malcolm <dmalcolm@redhat.com>
-
- * Makefile.in (OBJS-libcommon): Add text-art/box-drawing.o,
- text-art/canvas.o, text-art/ruler.o, text-art/selftests.o,
- text-art/style.o, text-art/styled-string.o, text-art/table.o,
- text-art/theme.o, and text-art/widget.o.
- * color-macros.h (COLOR_FG_BRIGHT_BLACK): New.
- (COLOR_FG_BRIGHT_RED): New.
- (COLOR_FG_BRIGHT_GREEN): New.
- (COLOR_FG_BRIGHT_YELLOW): New.
- (COLOR_FG_BRIGHT_BLUE): New.
- (COLOR_FG_BRIGHT_MAGENTA): New.
- (COLOR_FG_BRIGHT_CYAN): New.
- (COLOR_FG_BRIGHT_WHITE): New.
- (COLOR_BG_BRIGHT_BLACK): New.
- (COLOR_BG_BRIGHT_RED): New.
- (COLOR_BG_BRIGHT_GREEN): New.
- (COLOR_BG_BRIGHT_YELLOW): New.
- (COLOR_BG_BRIGHT_BLUE): New.
- (COLOR_BG_BRIGHT_MAGENTA): New.
- (COLOR_BG_BRIGHT_CYAN): New.
- (COLOR_BG_BRIGHT_WHITE): New.
- * common.opt (fdiagnostics-text-art-charset=): New option.
- (diagnostic-text-art.h): New SourceInclude.
- (diagnostic_text_art_charset) New Enum and EnumValues.
- * configure: Regenerate.
- * configure.ac (gccdepdir): Add text-art to loop.
- * diagnostic-diagram.h: New file.
- * diagnostic-format-json.cc (json_emit_diagram): New.
- (diagnostic_output_format_init_json): Wire it up to
- context->m_diagrams.m_emission_cb.
- * diagnostic-format-sarif.cc: Include "diagnostic-diagram.h" and
- "text-art/canvas.h".
- (sarif_result::on_nested_diagnostic): Move code to...
- (sarif_result::add_related_location): ...this new function.
- (sarif_result::on_diagram): New.
- (sarif_builder::emit_diagram): New.
- (sarif_builder::make_message_object_for_diagram): New.
- (sarif_emit_diagram): New.
- (diagnostic_output_format_init_sarif): Set
- context->m_diagrams.m_emission_cb to sarif_emit_diagram.
- * diagnostic-text-art.h: New file.
- * diagnostic.cc: Include "diagnostic-text-art.h",
- "diagnostic-diagram.h", and "text-art/theme.h".
- (diagnostic_initialize): Initialize context->m_diagrams and
- call diagnostics_text_art_charset_init.
- (diagnostic_finish): Clean up context->m_diagrams.m_theme.
- (diagnostic_emit_diagram): New.
- (diagnostics_text_art_charset_init): New.
- * diagnostic.h (text_art::theme): New forward decl.
- (class diagnostic_diagram): Likewise.
- (diagnostic_context::m_diagrams): New field.
- (diagnostic_emit_diagram): New decl.
- * doc/invoke.texi (Diagnostic Message Formatting Options): Add
- -fdiagnostics-text-art-charset=.
- (-fdiagnostics-plain-output): Add
- -fdiagnostics-text-art-charset=none.
- * gcc.cc: Include "diagnostic-text-art.h".
- (driver_handle_option): Handle OPT_fdiagnostics_text_art_charset_.
- * opts-common.cc (decode_cmdline_options_to_array): Add
- "-fdiagnostics-text-art-charset=none" to expanded_args for
- -fdiagnostics-plain-output.
- * opts.cc: Include "diagnostic-text-art.h".
- (common_handle_option): Handle OPT_fdiagnostics_text_art_charset_.
- * pretty-print.cc (pp_unicode_character): New.
- * pretty-print.h (pp_unicode_character): New decl.
- * selftest-run-tests.cc: Include "text-art/selftests.h".
- (selftest::run_tests): Call text_art_tests.
- * text-art/box-drawing-chars.inc: New file, generated by
- contrib/unicode/gen-box-drawing-chars.py.
- * text-art/box-drawing.cc: New file.
- * text-art/box-drawing.h: New file.
- * text-art/canvas.cc: New file.
- * text-art/canvas.h: New file.
- * text-art/ruler.cc: New file.
- * text-art/ruler.h: New file.
- * text-art/selftests.cc: New file.
- * text-art/selftests.h: New file.
- * text-art/style.cc: New file.
- * text-art/styled-string.cc: New file.
- * text-art/table.cc: New file.
- * text-art/table.h: New file.
- * text-art/theme.cc: New file.
- * text-art/theme.h: New file.
- * text-art/types.h: New file.
- * text-art/widget.cc: New file.
- * text-art/widget.h: New file.
-
-2023-06-21 Uros Bizjak <ubizjak@gmail.com>
-
- * function.h (emit_initial_value_sets):
- Change return type from int to void.
- (aggregate_value_p): Change return type from int to bool.
- (prologue_contains): Ditto.
- (epilogue_contains): Ditto.
- (prologue_epilogue_contains): Ditto.
- * function.cc (temp_slot): Make "in_use" variable bool.
- (make_slot_available): Update for changed "in_use" variable.
- (assign_stack_temp_for_type): Ditto.
- (emit_initial_value_sets): Change return type from int to void
- and update function body accordingly.
- (instantiate_virtual_regs): Ditto.
- (rest_of_handle_thread_prologue_and_epilogue): Ditto.
- (safe_insn_predicate): Change return type from int to bool.
- (aggregate_value_p): Change return type from int to bool
- and update function body accordingly.
- (prologue_contains): Change return type from int to bool.
- (prologue_epilogue_contains): Ditto.
-
-2023-06-21 Alexander Monakov <amonakov@ispras.ru>
-
- * common.opt (fp_contract_mode) [on]: Remove fallback.
- * config/sh/sh.md (*fmasf4): Correct flag_fp_contract_mode test.
- * doc/invoke.texi (-ffp-contract): Update.
- * trans-mem.cc (diagnose_tm_1): Skip internal function calls.
-
-2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
- Add alternatives to prefer to avoid same input and output Z register.
- (mask_gather_load<mode><v_int_container>): Likewise.
- (*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
- (*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
- (*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
- Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
- Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_sxtw): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather<mode>): Likewise.
- (@aarch64_ldff1_gather<mode>): Likewise.
- (*aarch64_ldff1_gather<mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather<mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
- <VNx4_NARROW:mode>): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_uxtw): Likewise.
- * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
- (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
- <SVE_PARTIAL_I:mode>): Likewise.
-
-2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
- Convert to compact alternatives syntax.
- (mask_gather_load<mode><v_int_container>): Likewise.
- (*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
- (*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
- (*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
- Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
- Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_sxtw): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather<mode>): Likewise.
- (@aarch64_ldff1_gather<mode>): Likewise.
- (*aarch64_ldff1_gather<mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather<mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
- <VNx4_NARROW:mode>): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_uxtw): Likewise.
- * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
- (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
- <SVE_PARTIAL_I:mode>): Likewise.
-
-2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- Revert:
- 2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
- Convert to compact alternatives syntax.
- (mask_gather_load<mode><v_int_container>): Likewise.
- (*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
- (*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
- (*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
- Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
- Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_sxtw): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather<mode>): Likewise.
- (@aarch64_ldff1_gather<mode>): Likewise.
- (*aarch64_ldff1_gather<mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather<mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
- <VNx4_NARROW:mode>): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_uxtw): Likewise.
- * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
- (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
- <SVE_PARTIAL_I:mode>): Likewise.
-
-2023-06-21 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * optabs-query.cc (can_vec_mask_load_store_p): Move to optabs-tree.cc.
- (get_len_load_store_mode): Ditto.
- * optabs-query.h (can_vec_mask_load_store_p): Move to optabs-tree.h.
- (get_len_load_store_mode): Ditto.
- * optabs-tree.cc (can_vec_mask_load_store_p): New function.
- (get_len_load_store_mode): Ditto.
- * optabs-tree.h (can_vec_mask_load_store_p): Ditto.
- (get_len_load_store_mode): Ditto.
- * tree-if-conv.cc: include optabs-tree instead of optabs-query
-
-2023-06-21 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-loop-ivopts.cc (add_iv_candidate_for_use): Use
- split_constant_offset for the POINTER_PLUS_EXPR case.
-
-2023-06-21 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-loop-ivopts.cc (record_group_use): Use
- split_constant_offset.
-
-2023-06-21 Richard Biener <rguenther@suse.de>
-
- * tree-loop-distribution.cc (classify_builtin_st): Use
- split_constant_offset.
- * tree-ssa-loop-ivopts.h (strip_offset): Remove.
- * tree-ssa-loop-ivopts.cc (strip_offset): Make static.
-
-2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
- Convert to compact alternatives syntax.
- (mask_gather_load<mode><v_int_container>): Likewise.
- (*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
- (*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
- (*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
- Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
- Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_sxtw): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather<mode>): Likewise.
- (@aarch64_ldff1_gather<mode>): Likewise.
- (*aarch64_ldff1_gather<mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather<mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
- <VNx4_NARROW:mode>): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_uxtw): Likewise.
- * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
- (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
- <SVE_PARTIAL_I:mode>): Likewise.
-
-2023-06-21 Tamar Christina <tamar.christina@arm.com>
-
- PR other/110329
- * doc/md.texi: Replace backslashchar.
-
-2023-06-21 Richard Biener <rguenther@suse.de>
-
- * config/i386/i386.cc (ix86_vector_costs::finish_cost):
- Overload. For masked main loops make sure the vectorization
- factor isn't more than double the number of iterations.
-
-2023-06-21 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/i386-expand.cc (ix86_expand_copysign): Request
- value duplication by ix86_build_signbit_mask() when AVX512F and
- not HFmode.
- * config/i386/sse.md (*<avx512>_vternlog<mode>_all): Convert to
- 2-alternative form. Adjust "mode" attribute. Add "enabled"
- attribute.
- (*<avx512>_vpternlog<mode>_1): Also permit when TARGET_AVX512F
- && !TARGET_PREFER_AVX256.
- (*<avx512>_vpternlog<mode>_2): Likewise.
- (*<avx512>_vpternlog<mode>_3): Likewise.
-
-2023-06-21 liuhongt <hongtao.liu@intel.com>
-
- PR target/110018
- * tree-vect-stmts.cc (vectorizable_conversion): Use
- intermiediate integer type for float_expr/fix_trunc_expr when
- direct optab is not existed.
-
-2023-06-20 Tamar Christina <tamar.christina@arm.com>
-
- PR bootstrap/110324
- * gensupport.cc (convert_syntax): Explicitly check for RTX code.
-
-2023-06-20 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.md (stack_tie): Hard-code the first
- register operand to the stack pointer. Require the second register
- operand to have the number specified in a separate const_int operand.
- * config/aarch64/aarch64.cc (aarch64_emit_stack_tie): New function.
- (aarch64_allocate_and_probe_stack_space): Use it.
- (aarch64_expand_prologue, aarch64_expand_epilogue): Likewise.
- (aarch64_expand_epilogue): Likewise.
-
-2023-06-20 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/79173
- * tree-ssa-math-opts.cc (match_uaddc_usubc): Remember lhs of
- IMAGPART_EXPR of arg2/arg3 and use that as arg3 if it has the right
- type.
-
-2023-06-20 Uros Bizjak <ubizjak@gmail.com>
-
- * calls.h (setjmp_call_p): Change return type from int to bool.
- * calls.cc (struct arg_data): Change "pass_on_stack" to bool.
- (store_one_arg): Change return type from int to bool
- and adjust function body accordingly. Change "sibcall_failure"
- variable to bool.
- (finalize_must_preallocate): Ditto. Change *must_preallocate pointer
- argument to bool. Change "partial_seen" variable to bool.
- (load_register_parameters): Change *sibcall_failure
- pointer argument to bool.
- (check_sibcall_argument_overlap_1): Change return type from int to bool
- and adjust function body accordingly.
- (check_sibcall_argument_overlap): Ditto. Change
- "mark_stored_args_map" argument to bool.
- (emit_call_1): Change "already_popped" variable to bool.
- (setjmp_call_p): Change return type from int to bool
- and adjust function body accordingly.
- (initialize_argument_information): Change *must_preallocate
- pointer argument to bool.
- (expand_call): Change "pcc_struct_value", "must_preallocate"
- and "sibcall_failure" variables to bool.
- (emit_library_call_value_1): Change "pcc_struct_value"
- variable to bool.
-
-2023-06-20 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/110276
- * ipa-sra.cc (struct caller_issues): New field there_is_one.
- (check_for_caller_issues): Set it.
- (check_all_callers_for_issues): Check it.
-
-2023-06-20 Martin Jambor <mjambor@suse.cz>
-
- * ipa-prop.h (ipa_uid_to_idx_map_elt): New type.
- (struct ipcp_transformation): Rearrange members according to
- C++ class coding convention, add m_uid_to_idx,
- get_param_index and maybe_create_parm_idx_map.
- * ipa-cp.cc (ipcp_transformation::get_param_index): New function.
- (compare_uids): Likewise.
- (ipcp_transformation::maype_create_parm_idx_map): Likewise.
- * ipa-prop.cc (ipcp_get_parm_bits): Use get_param_index.
- (ipcp_update_bits): Accept TS as a parameter, assume it is not NULL.
- (ipcp_update_vr): Likewise.
- (ipcp_transform_function): Call, maybe_create_parm_idx_map of TS, bail
- out quickly if empty, pass it to ipcp_update_bits and ipcp_update_vr.
-
-2023-06-20 Carl Love <cel@us.ibm.com>
-
- * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin):
- Rename CODE_FOR_xsxsigqp_tf to CODE_FOR_xsxsigqp_tf_ti.
- Rename CODE_FOR_xsxsigqp_kf to CODE_FOR_xsxsigqp_kf_ti.
- Rename CCDE_FOR_xsxexpqp_tf to CODE_FOR_xsxexpqp_tf_di.
- Rename CODE_FOR_xsxexpqp_kf to CODE_FOR_xsxexpqp_kf_di.
- (CODE_FOR_xsxexpqp_kf_v2di, CODE_FOR_xsxsigqp_kf_v1ti,
- CODE_FOR_xsiexpqp_kf_v2di): Add case statements.
- * config/rs6000/rs6000-builtins.def
- (__builtin_vsx_scalar_extract_exp_to_vec,
- __builtin_vsx_scalar_extract_sig_to_vec,
- __builtin_vsx_scalar_insert_exp_vqp): Add new builtin definitions.
- Rename xsxexpqp_kf, xsxsigqp_kf, xsiexpqp_kf to xsexpqp_kf_di,
- xsxsigqp_kf_ti, xsiexpqp_kf_di respectively.
- * config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
- Update case RS6000_OVLD_VEC_VSIE to handle MODE_VECTOR_INT for new
- overloaded instance. Update comments.
- * config/rs6000/rs6000-overload.def
- (__builtin_vec_scalar_insert_exp): Add new overload definition with
- vector arguments.
- (scalar_extract_exp_to_vec, scalar_extract_sig_to_vec): New
- overloaded definitions.
- * config/rs6000/vsx.md (V2DI_DI): New mode iterator.
- (DI_to_TI): New mode attribute.
- Rename xsxexpqp_<mode> to sxexpqp_<IEEE128:mode>_<V2DI_DI:mode>.
- Rename xsxsigqp_<mode> to xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>.
- Rename xsiexpqp_<mode> to xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>.
- * doc/extend.texi (scalar_extract_exp_to_vec,
- scalar_extract_sig_to_vec): Add documentation for new builtins.
- (scalar_insert_exp): Add new overloaded builtin definition.
-
-2023-06-20 Li Xu <xuli1@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_regmode_natural_size): set the natural
- size of vector mask mode to one rvv register.
-
-2023-06-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_const_vector): Optimize codegen.
-
-2023-06-20 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_arg_has_vector): Add default
- switch handler.
-
-2023-06-20 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-dse.cc (dse_classify_store): When we found
- no defs and the basic-block with the original definition
- ends in __builtin_unreachable[_trap] the store is dead.
-
-2023-06-20 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-phiprop.cc (phiprop_insert_phi): For simple loads
- keep the virtual SSA form up-to-date.
-
-2023-06-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (*aarch64_addp_same_reg<mode>):
- New define_insn_and_split.
-
-2023-06-20 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.md (*mov<mode>_aarch64): Drop test comment.
-
-2023-06-20 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md (vec_dupv2di): Correct %vmovddup input
- constraint. Add new AVX512F alternative.
-
-2023-06-20 Richard Biener <rguenther@suse.de>
-
- PR debug/110295
- * dwarf2out.cc (process_scope_var): Continue processing
- the decl after setting a parent in case the existing DIE
- was in limbo.
-
-2023-06-20 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_scalable_vector_type_p): Delete.
- (riscv_arg_has_vector): Simplify.
- (riscv_pass_in_vector_p): Adjust warning message.
-
-2023-06-19 Jin Ma <jinma@linux.alibaba.com>
-
- * config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR.
- (riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions.
- * config/riscv/riscv.md (riscv_frcsr): New patterns.
- (riscv_fscsr): Likewise.
-
-2023-06-19 Toru Kisuki <tkisuki@tachyum.com>
-
- PR rtl-optimization/110305
- * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
- Handle HONOR_SNANS for x + 0.0.
-
-2023-06-19 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/109811
- PR tree-optimization/109849
- * passes.def: Add phiprop to early optimization passes.
- * tree-ssa-phiprop.cc: Allow clonning.
-
-2023-06-19 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.md (arches): Add nosimd.
- (*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64): Rewrite to
- compact syntax.
-
-2023-06-19 Tamar Christina <tamar.christina@arm.com>
- Omar Tahir <Omar.Tahir2@arm.com>
-
- * gensupport.cc (class conlist, add_constraints, add_attributes,
- skip_spaces, expect_char, preprocess_compact_syntax,
- parse_section_layout, parse_section, convert_syntax): New.
- (process_rtx): Check for conversion.
- * genoutput.cc (process_template): Check for unresolved iterators.
- (class data): Add compact_syntax_p.
- (gen_insn): Use it.
- * gensupport.h (compact_syntax): New.
- (hash-set.h): Include.
- * doc/md.texi: Document it.
-
-2023-06-19 Uros Bizjak <ubizjak@gmail.com>
-
- * recog.h (check_asm_operands): Change return type from int to bool.
- (insn_invalid_p): Ditto.
- (verify_changes): Ditto.
- (apply_change_group): Ditto.
- (constrain_operands): Ditto.
- (constrain_operands_cached): Ditto.
- (validate_replace_rtx_subexp): Ditto.
- (validate_replace_rtx): Ditto.
- (validate_replace_rtx_part): Ditto.
- (validate_replace_rtx_part_nosimplify): Ditto.
- (added_clobbers_hard_reg_p): Ditto.
- (peep2_regno_dead_p): Ditto.
- (peep2_reg_dead_p): Ditto.
- (store_data_bypass_p): Ditto.
- (if_test_bypass_p): Ditto.
- * rtl.h (split_all_insns_noflow): Change
- return type from unsigned int to void.
- * genemit.cc (output_added_clobbers_hard_reg_p): Change return type
- of generated added_clobbers_hard_reg_p from int to bool and adjust
- function body accordingly. Change "used" variable type from
- int to bool.
- * recog.cc (check_asm_operands): Change return type
- from int to bool and adjust function body accordingly.
- (insn_invalid_p): Ditto. Change "is_asm" variable to bool.
- (verify_changes): Change return type from int to bool.
- (apply_change_group): Change return type from int to bool
- and adjust function body accordingly.
- (validate_replace_rtx_subexp): Change return type from int to bool.
- (validate_replace_rtx): Ditto.
- (validate_replace_rtx_part): Ditto.
- (validate_replace_rtx_part_nosimplify): Ditto.
- (constrain_operands_cached): Ditto.
- (constrain_operands): Ditto. Change "lose" and "win"
- variables type from int to bool.
- (split_all_insns_noflow): Change return type from unsigned int
- to void and adjust function body accordingly.
- (peep2_regno_dead_p): Change return type from int to bool.
- (peep2_reg_dead_p): Ditto.
- (peep2_find_free_register): Change "success"
- variable type from int to bool
- (store_data_bypass_p_1): Change return type from int to bool.
- (store_data_bypass_p): Ditto.
-
-2023-06-19 Li Xu <xuli1@eswincomputing.com>
-
- * config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the
- Zve32f extension.
-
-2023-06-19 Pan Li <pan2.li@intel.com>
-
- PR target/110299
- * config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
- modes.
- * config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
- VWLMUL1_ZVE32, VI_ZVE64, VI_ZVE32, VWI, VWI_ZVE64, VWI_ZVE32,
- VF_ZVE63 and VF_ZVE32.
- * config/riscv/vector.md
- (@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Removed.
- (@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>): Ditto.
- (@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>): Ditto.
- (@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
- (@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>): Ditto.
- (@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): New pattern.
- (@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Ditto.
- (@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Ditto.
- (@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Ditto.
- (@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Ditto.
-
-2023-06-19 Pan Li <pan2.li@intel.com>
-
- PR target/110277
- * config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
- ret_mode.
- * config/riscv/vector-iterators.md: Add VHF, VSF, VDF,
- VHF_LMUL1, VSF_LMUL1, VDF_LMUL1, and remove unused attr.
- * config/riscv/vector.md (@pred_reduc_<reduc><mode><vlmul1>): Removed.
- (@pred_reduc_<reduc><mode><vlmul1_zve64>): Ditto.
- (@pred_reduc_<reduc><mode><vlmul1_zve32>): Ditto.
- (@pred_reduc_plus<order><mode><vlmul1>): Ditto.
- (@pred_reduc_plus<order><mode><vlmul1_zve32>): Ditto.
- (@pred_reduc_plus<order><mode><vlmul1_zve64>): Ditto.
- (@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>): New pattern.
- (@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>): Ditto.
- (@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>): Ditto.
- (@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>): Ditto.
- (@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>): Ditto.
- (@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>): Ditto.
-
-2023-06-19 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn.cc (gcn_expand_divmod_libfunc): New function.
- (gcn_init_libfuncs): Add div and mod functions for all modes.
- Add placeholders for divmod functions.
- (TARGET_EXPAND_DIVMOD_LIBFUNC): Define.
-
-2023-06-19 Andrew Stubbs <ams@codesourcery.com>
-
- * tree-vect-generic.cc: Include optabs-libfuncs.h.
- (get_compute_type): Check optab_libfunc.
- * tree-vect-stmts.cc: Include optabs-libfuncs.h.
- (vectorizable_operation): Check optab_libfunc.
-
-2023-06-19 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-protos.h (vgpr_4reg_mode_p): New function.
- * config/gcn/gcn-valu.md (V_4REG, V_4REG_ALT): New iterators.
- (V_MOV, V_MOV_ALT): Likewise.
- (scalar_mode, SCALAR_MODE): Add TImode.
- (vnsi, VnSI, vndi, VnDI): Likewise.
- (vec_merge, vec_merge_with_clobber, vec_merge_with_vcc): Use V_MOV.
- (mov<mode>, mov<mode>_unspec): Use V_MOV.
- (*mov<mode>_4reg): New insn.
- (mov<mode>_exec): New 4reg variant.
- (mov<mode>_sgprbase): Likewise.
- (reload_in<mode>, reload_out<mode>): Use V_MOV.
- (vec_set<mode>): Likewise.
- (vec_duplicate<mode><exec>): New 4reg variant.
- (vec_extract<mode><scalar_mode>): Likewise.
- (vec_extract<V_ALL:mode><V_ALL_ALT:mode>): Rename to ...
- (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): ... this, and use V_MOV.
- (vec_extract<V_4REG:mode><V_4REG_ALT:mode>_nop): New 4reg variant.
- (fold_extract_last_<mode>): Use V_MOV.
- (vec_init<V_ALL:mode><V_ALL_ALT:mode>): Rename to ...
- (vec_init<V_MOV:mode><V_MOV_ALT:mode>): ... this, and use V_MOV.
- (gather_load<mode><vnsi>, gather<mode>_expr<exec>,
- gather<mode>_insn_1offset<exec>, gather<mode>_insn_1offset_ds<exec>,
- gather<mode>_insn_2offsets<exec>): Use V_MOV.
- (scatter_store<mode><vnsi>, scatter<mode>_expr<exec_scatter>,
- scatter<mode>_insn_1offset<exec_scatter>,
- scatter<mode>_insn_1offset_ds<exec_scatter>,
- scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
- (maskload<mode>di, maskstore<mode>di, mask_gather_load<mode><vnsi>,
- mask_scatter_store<mode><vnsi>): Likewise.
- * config/gcn/gcn.cc (gcn_class_max_nregs): Use vgpr_4reg_mode_p.
- (gcn_hard_regno_mode_ok): Likewise.
- (GEN_VNM): Add TImode support.
- (USE_TI): New macro. Separate TImode operations from non-TImode ones.
- (gcn_vector_mode_supported_p): Add V64TImode, V32TImode, V16TImode,
- V8TImode, and V2TImode.
- (print_operand): Add 'J' and 'K' print codes.
-
-2023-06-19 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110298
- * tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely):
- Clear number of iterations info before cleaning up the CFG.
-
-2023-06-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
- Simplify vec_concat of lowpart subreg and high part vec_select.
-
-2023-06-19 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/invoke.texi (-foffload-options): Remove '-O3' from the examples.
-
-2023-06-19 Richard Sandiford <richard.sandiford@arm.com>
-
- * tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors):
- Handle null niters_skip.
-
-2023-06-19 Richard Biener <rguenther@suse.de>
-
- * config/aarch64/aarch64.cc
- (aarch64_vector_costs::analyze_loop_vinfo): Fix reference
- to LOOP_VINFO_MASKS.
-
-2023-06-19 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
-
- PR target/105523
- * common/config/avr/avr-common.cc: Remove setting
- of OPT_fdelete_null_pointer_checks.
- * config/avr/avr.cc (avr_option_override): Clear
- flag_delete_null_pointer_checks if zero_address_valid.
- (avr_addr_space_zero_address_valid): New function.
- (TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): Provide target
- hook.
-
-2023-06-19 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- Robin Dapp <rdapp.gcc@gmail.com>
-
- * doc/md.texi: Add len_mask{load,store}.
- * genopinit.cc (main): Ditto.
- (CMP_NAME): Ditto.
- * internal-fn.cc (len_maskload_direct): Ditto.
- (len_maskstore_direct): Ditto.
- (expand_call_mem_ref): Ditto.
- (expand_partial_load_optab_fn): Ditto.
- (expand_len_maskload_optab_fn): Ditto.
- (expand_partial_store_optab_fn): Ditto.
- (expand_len_maskstore_optab_fn): Ditto.
- (direct_len_maskload_optab_supported_p): Ditto.
- (direct_len_maskstore_optab_supported_p): Ditto.
- * internal-fn.def (LEN_MASK_LOAD): Ditto.
- (LEN_MASK_STORE): Ditto.
- * optabs.def (OPTAB_CD): Ditto.
-
-2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<optab><mode>2): Add unop expanders.
-
-2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<optab><mode>3): Implement binop
- expander.
- * config/riscv/riscv-protos.h (emit_vlmax_fp_insn): Declare.
- (enum vxrm_field_enum): Rename this...
- (enum fixed_point_rounding_mode): ...to this.
- (enum frm_field_enum): Rename this...
- (enum floating_point_rounding_mode): ...to this.
- * config/riscv/riscv-v.cc (emit_vlmax_fp_insn): New function
- * config/riscv/riscv.cc (riscv_const_insns): Clarify const
- vector handling.
- (riscv_libgcc_floating_mode_supported_p): Adjust comment.
- (riscv_excess_precision): Do not convert to float for ZVFH.
- * config/riscv/vector-iterators.md: Add VF_AUTO iterator.
-
-2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/vector-iterators.md: Add VI_QH iterator.
- * config/riscv/autovec-opt.md
- (@pred_extract_first_sextdi<mode>): New vmv.x.s pattern
- that includes sign extension.
- (@pred_extract_first_sextsi<mode>): Dito for SImode.
-
-2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (vec_set<mode>): Implement.
- (vec_extract<mode><vel>): Implement.
- * config/riscv/riscv-protos.h (enum insn_type): Add slide insn.
- (emit_vlmax_slide_insn): Declare.
- (emit_nonvlmax_slide_tu_insn): Declare.
- (emit_scalar_move_insn): Export.
- (emit_nonvlmax_integer_move_insn): Export.
- * config/riscv/riscv-v.cc (emit_vlmax_slide_insn): New function.
- (emit_nonvlmax_slide_tu_insn): New function.
- (emit_vlmax_masked_mu_insn): No change.
- (emit_vlmax_integer_move_insn): Export.
-
-2023-06-19 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (enum vect_partial_vector_style): New.
- (_loop_vec_info::partial_vector_style): Likewise.
- (LOOP_VINFO_PARTIAL_VECTORS_STYLE): Likewise.
- (rgroup_controls::compare_type): Add.
- (vec_loop_masks): Change from a typedef to auto_vec<>
- to a structure.
- * tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors):
- Adjust. Convert niters_skip to compare_type.
- (vect_set_loop_condition_partial_vectors_avx512): New function
- implementing the AVX512 partial vector codegen.
- (vect_set_loop_condition): Dispatch to the correct
- vect_set_loop_condition_partial_vectors_* function based on
- LOOP_VINFO_PARTIAL_VECTORS_STYLE.
- (vect_prepare_for_masked_peels): Compute LOOP_VINFO_MASK_SKIP_NITERS
- in the original niter type.
- * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize
- partial_vector_style.
- (can_produce_all_loop_masks_p): Adjust.
- (vect_verify_full_masking): Produce the rgroup_controls vector
- here. Set LOOP_VINFO_PARTIAL_VECTORS_STYLE on success.
- (vect_verify_full_masking_avx512): New function implementing
- verification of AVX512 style masking.
- (vect_verify_loop_lens): Set LOOP_VINFO_PARTIAL_VECTORS_STYLE.
- (vect_analyze_loop_2): Also try AVX512 style masking.
- Adjust condition.
- (vect_estimate_min_profitable_iters): Implement AVX512 style
- mask producing cost.
- (vect_record_loop_mask): Do not build the rgroup_controls
- vector here but record masks in a hash-set.
- (vect_get_loop_mask): Implement AVX512 style mask query,
- complementing the existing while_ult style.
-
-2023-06-19 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (vect_get_loop_mask): Add loop_vec_info
- argument.
- * tree-vect-loop.cc (vect_get_loop_mask): Likewise.
- (vectorize_fold_left_reduction): Adjust.
- (vect_transform_reduction): Likewise.
- (vectorizable_live_operation): Likewise.
- * tree-vect-stmts.cc (vectorizable_call): Likewise.
- (vectorizable_operation): Likewise.
- (vectorizable_store): Likewise.
- (vectorizable_load): Likewise.
- (vectorizable_condition): Likewise.
-
-2023-06-19 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
-
- PR target/110086
- * config/avr/avr.opt (mgas-isr-prologues, mmain-is-OS_task):
- Add Optimization option property.
-
-2023-06-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.cc (xtensa_constantsynth_2insn):
- Add new pattern for the abovementioned case.
-
-2023-06-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.cc
- (TARGET_MEMORY_MOVE_COST, xtensa_memory_move_cost): Remove.
-
-2023-06-19 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (TARGET_CONST_ANCHOR): New define.
-
-2023-06-19 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * cse.cc (try_const_anchors): Check SCALAR_INT_MODE.
-
-2023-06-19 liuhongt <hongtao.liu@intel.com>
-
- PR target/110235
- * config/i386/sse.md (<sse2_avx2>_packsswb<mask_name>):
- Substitute with ..
- (sse2_packsswb<mask_name>): .. this, ..
- (avx2_packsswb<mask_name>): .. this and ..
- (avx512bw_packsswb<mask_name>): .. this.
- (<sse2_avx2>_packssdw<mask_name>): Substitute with ..
- (sse2_packssdw<mask_name>): .. this, ..
- (avx2_packssdw<mask_name>): .. this and ..
- (avx512bw_packssdw<mask_name>): .. this.
-
-2023-06-19 liuhongt <hongtao.liu@intel.com>
-
- PR target/110235
- * config/i386/i386-expand.cc (ix86_split_mmx_pack): Use
- UNSPEC_US_TRUNCATE instead of original us_truncate for
- packusdw/packuswb.
- * config/i386/mmx.md (mmx_pack<s_trunsuffix>swb): Substitute
- with ..
- (mmx_packsswb): .. this and ..
- (mmx_packuswb): .. this.
- (mmx_packusdw): Use UNSPEC_US_TRUNCATE instead of original
- us_truncate.
- (s_trunsuffix): Removed code iterator.
- (any_s_truncate): Ditto.
- * config/i386/sse.md (<sse2_avx2>_packuswb<mask_name>): Use
- UNSPEC_US_TRUNCATE instead of original us_truncate.
- (<sse4_1_avx2>_packusdw<mask_name>): Ditto.
- * config/i386/i386.md (UNSPEC_US_TRUNCATE): New unspec_c_enum.
-
-2023-06-18 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Fix one typo.
-
-2023-06-18 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (*rtx_equal_p_callback_function):
- Change return type from int to bool.
- (rtx_equal_p): Ditto.
- (*hash_rtx_callback_function): Ditto.
- * rtl.cc (rtx_equal_p): Change return type from int to bool
- and adjust function body accordingly.
- * early-remat.cc (scratch_equal): Ditto.
- * sel-sched-ir.cc (skip_unspecs_callback): Ditto.
- (hash_with_unspec_callback): Ditto.
-
-2023-06-18 Jeff Law <jlaw@ventanamicro.com>
-
- * config/arc/arc.md (movqi_insn): Allow certain constants to
- be stored into memory in the pattern's condition.
- (movsf_insn): Similarly.
-
-2023-06-18 Honza <jh@ryzen3.suse.cz>
-
- PR tree-optimization/109849
- * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Add new parameter
- ES; handle ipa_predicate::not_sra_candidate.
- (evaluate_properties_for_edge): Pass es to
- evaluate_conditions_for_known_args.
- (ipa_fn_summary_t::duplicate): Handle sra candidates.
- (dump_ipa_call_summary): Dump points_to_possible_sra_candidate.
- (load_or_store_of_ptr_parameter): New function.
- (points_to_possible_sra_candidate_p): New function.
- (analyze_function_body): Initialize points_to_possible_sra_candidate;
- determine sra predicates.
- (estimate_ipcp_clone_size_and_time): Update call of
- evaluate_conditions_for_known_args.
- (remap_edge_params): Update points_to_possible_sra_candidate.
- (read_ipa_call_summary): Stream points_to_possible_sra_candidate
- (write_ipa_call_summary): Likewise.
- * ipa-predicate.cc (ipa_predicate::add_clause): Handle not_sra_candidate.
- (dump_condition): Dump it.
- * ipa-predicate.h (struct inline_param_summary): Add
- points_to_possible_sra_candidate.
-
-2023-06-18 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_expand_carry): New helper
- function for setting the carry flag.
- (ix86_expand_builtin) <handlecarry>: Use it here.
- * config/i386/i386-protos.h (ix86_expand_carry): Prototype here.
- * config/i386/i386.md (uaddc<mode>5): Use ix86_expand_carry.
- (usubc<mode>5): Likewise.
-
-2023-06-18 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386.md (*concat<mode><dwi>3_1): Use QImode
- for the immediate constant shift count.
- (*concat<mode><dwi>3_2): Likewise.
- (*concat<mode><dwi>3_3): Likewise.
- (*concat<mode><dwi>3_4): Likewise.
- (*concat<mode><dwi>3_5): Likewise.
- (*concat<mode><dwi>3_6): Likewise.
-
-2023-06-18 Uros Bizjak <ubizjak@gmail.com>
-
- * cse.cc (hash_rtx_cb): Rename to hash_rtx.
- (hash_rtx): Remove.
- * early-remat.cc (remat_candidate_hasher::equal): Update
- to call rtx_equal_p with rtx_equal_p_callback_function argument.
- * rtl.cc (rtx_equal_p_cb): Rename to rtx_equal_p.
- (rtx_equal_p): Remove.
- * rtl.h (rtx_equal_p): Add rtx_equal_p_callback_function
- argument with NULL default value.
- (rtx_equal_p_cb): Remove function declaration.
- (hash_rtx_cb): Ditto.
- (hash_rtx): Add hash_rtx_callback_function argument
- with NULL default value.
- * sel-sched-ir.cc (free_nop_pool): Update function comment.
- (skip_unspecs_callback): Ditto.
- (vinsn_init): Update to call hash_rtx with
- hash_rtx_callback_function argument.
- (vinsn_equal_p): Ditto.
-
-2023-06-18 yulong <shiyulong@iscas.ac.cn>
-
- * config/riscv/genrvv-type-indexer.cc (valid_type): Enable FP16 tuple.
- * config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro.
- (ADJUST_ALIGNMENT): Ditto.
- (RVV_TUPLE_PARTIAL_MODES): Ditto.
- (ADJUST_NUNITS): Ditto.
- * config/riscv/riscv-vector-builtins-types.def (vfloat16mf4x2_t):
- New types.
- (vfloat16mf4x3_t): Ditto.
- (vfloat16mf4x4_t): Ditto.
- (vfloat16mf4x5_t): Ditto.
- (vfloat16mf4x6_t): Ditto.
- (vfloat16mf4x7_t): Ditto.
- (vfloat16mf4x8_t): Ditto.
- (vfloat16mf2x2_t): Ditto.
- (vfloat16mf2x3_t): Ditto.
- (vfloat16mf2x4_t): Ditto.
- (vfloat16mf2x5_t): Ditto.
- (vfloat16mf2x6_t): Ditto.
- (vfloat16mf2x7_t): Ditto.
- (vfloat16mf2x8_t): Ditto.
- (vfloat16m1x2_t): Ditto.
- (vfloat16m1x3_t): Ditto.
- (vfloat16m1x4_t): Ditto.
- (vfloat16m1x5_t): Ditto.
- (vfloat16m1x6_t): Ditto.
- (vfloat16m1x7_t): Ditto.
- (vfloat16m1x8_t): Ditto.
- (vfloat16m2x2_t): Ditto.
- (vfloat16m2x3_t): Ditto.
- (vfloat16m2x4_t): Ditto.
- (vfloat16m4x2_t): Ditto.
- * config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): New macro.
- (vfloat16mf4x3_t): Ditto.
- (vfloat16mf4x4_t): Ditto.
- (vfloat16mf4x5_t): Ditto.
- (vfloat16mf4x6_t): Ditto.
- (vfloat16mf4x7_t): Ditto.
- (vfloat16mf4x8_t): Ditto.
- (vfloat16mf2x2_t): Ditto.
- (vfloat16mf2x3_t): Ditto.
- (vfloat16mf2x4_t): Ditto.
- (vfloat16mf2x5_t): Ditto.
- (vfloat16mf2x6_t): Ditto.
- (vfloat16mf2x7_t): Ditto.
- (vfloat16mf2x8_t): Ditto.
- (vfloat16m1x2_t): Ditto.
- (vfloat16m1x3_t): Ditto.
- (vfloat16m1x4_t): Ditto.
- (vfloat16m1x5_t): Ditto.
- (vfloat16m1x6_t): Ditto.
- (vfloat16m1x7_t): Ditto.
- (vfloat16m1x8_t): Ditto.
- (vfloat16m2x2_t): Ditto.
- (vfloat16m2x3_t): Ditto.
- (vfloat16m2x4_t): Ditto.
- (vfloat16m4x2_t): Ditto.
- * config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): New.
- * config/riscv/riscv.md: New.
- * config/riscv/vector-iterators.md: New.
-
-2023-06-17 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_expand_move): Check that OP1 is
- CONST_WIDE_INT_P before calling ix86_convert_wide_int_to_broadcast.
- Generalize special case for converting TImode to V1TImode to handle
- all 128-bit vector conversions.
-
-2023-06-17 Costas Argyris <costas.argyris@gmail.com>
-
- * gcc-ar.cc (main): Refactor to slightly reduce code
- duplication. Avoid unnecessary elements in nargv.
-
-2023-06-16 Pan Li <pan2.li@intel.com>
-
- PR target/110265
- * config/riscv/riscv-vector-builtins-bases.cc: Add ret_mode for
- integer reduction expand.
- * config/riscv/vector-iterators.md: Add VQI, VHI, VSI and VDI,
- and the LMUL1 attr respectively.
- * config/riscv/vector.md
- (@pred_reduc_<reduc><mode><vlmul1>): Removed.
- (@pred_reduc_<reduc><mode><vlmul1_zve64>): Likewise.
- (@pred_reduc_<reduc><mode><vlmul1_zve32>): Likewise.
- (@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>): New pattern.
- (@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>): Likewise.
- (@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>): Likewise.
- (@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>): Likewise.
-
-2023-06-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110264
- * config/riscv/riscv-vsetvl.cc (insert_vsetvl): Fix bug.
-
-2023-06-16 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/79173
- * builtin-types.def (BT_FN_UINT_UINT_UINT_UINT_UINTPTR,
- BT_FN_ULONG_ULONG_ULONG_ULONG_ULONGPTR,
- BT_FN_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONGPTR): New
- types.
- * builtins.def (BUILT_IN_ADDC, BUILT_IN_ADDCL, BUILT_IN_ADDCLL,
- BUILT_IN_SUBC, BUILT_IN_SUBCL, BUILT_IN_SUBCLL): New builtins.
- * builtins.cc (fold_builtin_addc_subc): New function.
- (fold_builtin_varargs): Handle BUILT_IN_{ADD,SUB}C{,L,LL}.
- * doc/extend.texi (__builtin_addc, __builtin_subc): Document.
-
-2023-06-16 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/110271
- * tree-ssa-math-opts.cc (math_opts_dom_walker::after_dom_children)
- <case PLUS_EXPR>: Ignore return value from match_arith_overflow,
- instead call match_uaddc_usubc only if gsi_stmt (gsi) is still stmt.
-
-2023-06-16 Martin Jambor <mjambor@suse.cz>
-
- * configure: Regenerate.
-
-2023-06-16 Roger Sayle <roger@nextmovesoftware.com>
- Uros Bizjak <ubizjak@gmail.com>
-
- PR target/31985
- * config/i386/i386.md (*add<dwi>3_doubleword_concat): New
- define_insn_and_split combine *add<dwi>3_doubleword with
- a *concat<mode><dwi>3 for more efficient lowering after reload.
-
-2023-06-16 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * ira-lives.cc: Include except.h.
- (process_bb_node_lives): Ignore conflicts from cleanup exceptions
- when the pseudo does not live at the exception landing pad.
-
-2023-06-16 Alex Coplan <alex.coplan@arm.com>
-
- * doc/invoke.texi: Document -Welaborated-enum-base.
-
-2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd-builtins.def (shrn2_n): Rename builtins to...
- (ushrn2_n): ... This.
- (sqshrn2_n): Rename builtins to...
- (ssqshrn2_n): ... This.
- (uqshrn2_n): Rename builtins to...
- (uqushrn2_n): ... This.
- * config/aarch64/arm_neon.h (vqshrn_high_n_s16): Adjust for the above.
- (vqshrn_high_n_s32): Likewise.
- (vqshrn_high_n_s64): Likewise.
- (vqshrn_high_n_u16): Likewise.
- (vqshrn_high_n_u32): Likewise.
- (vqshrn_high_n_u64): Likewise.
- (vshrn_high_n_s16): Likewise.
- (vshrn_high_n_s32): Likewise.
- (vshrn_high_n_s64): Likewise.
- (vshrn_high_n_u16): Likewise.
- (vshrn_high_n_u32): Likewise.
- (vshrn_high_n_u64): Likewise.
- * config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn2_n<mode>_insn_le):
- Rename to...
- (aarch64_<shrn_op><sra_op>shrn2_n<mode>_insn_le): ... This.
- Use SHIFTRT iterator and AARCH64_VALID_SHRN_OP check.
- (aarch64_<shrn_op>shrn2_n<mode>_insn_be): Rename to...
- (aarch64_<shrn_op><sra_op>shrn2_n<mode>_insn_be): ... This.
- Use SHIFTRT iterator and AARCH64_VALID_SHRN_OP check.
- (aarch64_<shrn_op>shrn2_n<mode>): Rename to...
- (aarch64_<shrn_op><sra_op>shrn2_n<mode>): ... This.
- Update expander for the above.
-
-2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd-builtins.def (shrn2): Rename builtins to...
- (shrn2_n): ... This.
- (rshrn2): Rename builtins to...
- (rshrn2_n): ... This.
- * config/aarch64/arm_neon.h (vrshrn_high_n_s16): Adjust for the above.
- (vrshrn_high_n_s32): Likewise.
- (vrshrn_high_n_s64): Likewise.
- (vrshrn_high_n_u16): Likewise.
- (vrshrn_high_n_u32): Likewise.
- (vrshrn_high_n_u64): Likewise.
- (vshrn_high_n_s16): Likewise.
- (vshrn_high_n_s32): Likewise.
- (vshrn_high_n_s64): Likewise.
- (vshrn_high_n_u16): Likewise.
- (vshrn_high_n_u32): Likewise.
- (vshrn_high_n_u64): Likewise.
- * config/aarch64/aarch64-simd.md (*aarch64_<srn_op>shrn<mode>2_vect_le):
- Delete.
- (*aarch64_<srn_op>shrn<mode>2_vect_be): Likewise.
- (aarch64_shrn2<mode>_insn_le): Likewise.
- (aarch64_shrn2<mode>_insn_be): Likewise.
- (aarch64_shrn2<mode>): Likewise.
- (aarch64_rshrn2<mode>_insn_le): Likewise.
- (aarch64_rshrn2<mode>_insn_be): Likewise.
- (aarch64_rshrn2<mode>): Likewise.
- (aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_le): Likewise.
- (aarch64_<shrn_op>shrn2_n<mode>_insn_le): New define_insn.
- (aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_be): Delete.
- (aarch64_<shrn_op>shrn2_n<mode>_insn_be): New define_insn.
- (aarch64_<sur>q<r>shr<u>n2_n<mode>): Delete.
- (aarch64_<shrn_op>shrn2_n<mode>): New define_expand.
- (aarch64_<shrn_op>rshrn2_n<mode>_insn_le): New define_insn.
- (aarch64_<shrn_op>rshrn2_n<mode>_insn_be): New define_insn.
- (aarch64_<shrn_op>rshrn2_n<mode>): New define_expand.
- (aarch64_sqshrun2_n<mode>_insn_le): New define_insn.
- (aarch64_sqshrun2_n<mode>_insn_be): New define_insn.
- (aarch64_sqshrun2_n<mode>): New define_expand.
- (aarch64_sqrshrun2_n<mode>_insn_le): New define_insn.
- (aarch64_sqrshrun2_n<mode>_insn_be): New define_insn.
- (aarch64_sqrshrun2_n<mode>): New define_expand.
- * config/aarch64/iterators.md (UNSPEC_SQSHRUN, UNSPEC_SQRSHRUN,
- UNSPEC_SQSHRN, UNSPEC_UQSHRN, UNSPEC_SQRSHRN, UNSPEC_UQRSHRN):
- Delete unspec values.
- (VQSHRN_N): Delete int iterator.
-
-2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64.h (AARCH64_VALID_SHRN_OP): Define.
- * config/aarch64/aarch64-simd.md
- (*aarch64_<shrn_op>shrn_n<mode>_insn<vczle><vczbe>): Rename to...
- (*aarch64_<shrn_op><shrn_s>shrn_n<mode>_insn<vczle><vczbe>): ... This.
- Use SHIFTRT iterator and add AARCH64_VALID_SHRN_OP to condition.
- * config/aarch64/iterators.md (shrn_s): New code attribute.
-
-2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n_n<mode>):
- Rename to...
- (aarch64_<shrn_op>shrn_n<mode>): ... This. Reimplement with RTL codes.
- (*aarch64_<shrn_op>rshrn_n<mode>_insn): New define_insn.
- (aarch64_sqrshrun_n<mode>_insn): Likewise.
- (aarch64_sqshrun_n<mode>_insn): Likewise.
- (aarch64_<shrn_op>rshrn_n<mode>): New define_expand.
- (aarch64_sqshrun_n<mode>): Likewise.
- (aarch64_sqrshrun_n<mode>): Likewise.
- * config/aarch64/iterators.md (V2XWIDE): Add HI and SI modes.
-
-2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd-builtins.def (shrn): Rename builtins to...
- (shrn_n): ... This.
- (rshrn): Rename builtins to...
- (rshrn_n): ... This.
- * config/aarch64/arm_neon.h (vshrn_n_s16): Adjust for the above.
- (vshrn_n_s32): Likewise.
- (vshrn_n_s64): Likewise.
- (vshrn_n_u16): Likewise.
- (vshrn_n_u32): Likewise.
- (vshrn_n_u64): Likewise.
- (vrshrn_n_s16): Likewise.
- (vrshrn_n_s32): Likewise.
- (vrshrn_n_s64): Likewise.
- (vrshrn_n_u16): Likewise.
- (vrshrn_n_u32): Likewise.
- (vrshrn_n_u64): Likewise.
- * config/aarch64/aarch64-simd.md
- (*aarch64_<srn_op>shrn<mode><vczle><vczbe>): Delete.
- (aarch64_shrn<mode>): Likewise.
- (aarch64_rshrn<mode><vczle><vczbe>_insn): Likewise.
- (aarch64_rshrn<mode>): Likewise.
- (aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): Likewise.
- (aarch64_<sur>q<r>shr<u>n_n<mode>): Likewise.
- (*aarch64_<shrn_op>shrn_n<mode>_insn<vczle><vczbe>): New define_insn.
- (*aarch64_<shrn_op>rshrn_n<mode>_insn<vczle><vczbe>): Likewise.
- (*aarch64_sqshrun_n<mode>_insn<vczle><vczbe>): Likewise.
- (*aarch64_sqrshrun_n<mode>_insn<vczle><vczbe>): Likewise.
- (aarch64_<shrn_op>shrn_n<mode>): New define_expand.
- (aarch64_<shrn_op>rshrn_n<mode>): Likewise.
- (aarch64_sqshrun_n<mode>): Likewise.
- (aarch64_sqrshrun_n<mode>): Likewise.
- * config/aarch64/iterators.md (ALL_TRUNC): New code iterator.
- (TRUNCEXTEND): New code attribute.
- (TRUNC_SHIFT): Likewise.
- (shrn_op): Likewise.
- * config/aarch64/predicates.md (aarch64_simd_umax_quarter_mode):
- New predicate.
-
-2023-06-16 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vsetvl.cc
- (pass_vsetvl::global_eliminate_vsetvl_insn): Initialize var by NULL.
-
-2023-06-16 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110278
- * match.pd (uns < (typeof uns)(uns != 0) -> false): New.
- (x != (typeof x)(x == 0) -> true): Likewise.
-
-2023-06-16 Pali Rohár <pali@kernel.org>
-
- * config/i386/mingw-w64.h (CPP_SPEC): Adjust for -mcrtdll=.
- (REAL_LIBGCC_SPEC): New define.
- * config/i386/mingw.opt: Add mcrtdll=
- * config/i386/mingw32.h (CPP_SPEC): Adjust for -mcrtdll=.
- (REAL_LIBGCC_SPEC): Adjust for -mcrtdll=.
- (STARTFILE_SPEC): Adjust for -mcrtdll=.
- * doc/invoke.texi: Add mcrtdll= documentation.
-
-2023-06-16 Simon Dardis <simon.dardis@imgtec.com>
-
- * config/mips/mips.cc (enum mips_code_readable_setting):New enmu.
- (mips_handle_code_readable_attr):New static function.
- (mips_get_code_readable_attr):New static enum function.
- (mips_set_current_function):Set the code_readable mode.
- (mips_option_override):Same as above.
- * doc/extend.texi:Document code_readable.
-
-2023-06-16 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110269
- * fold-const.cc (fold_binary_loc): Merge x != 0 folding
- with tree_expr_nonzero_p ...
- * match.pd (cmp (convert? addr@0) integer_zerop): With this
- pattern.
-
-2023-06-15 Marek Polacek <polacek@redhat.com>
-
- * Makefile.in: Set LD_PICFLAG. Use it. Set enable_host_pie.
- Remove NO_PIE_CFLAGS and NO_PIE_FLAG. Pass LD_PICFLAG to
- ALL_LINKERFLAGS. Use the "pic" build of libiberty if --enable-host-pie.
- * configure.ac (--enable-host-shared): Don't set PICFLAG here.
- (--enable-host-pie): New check. Set PICFLAG and LD_PICFLAG after this
- check.
- * configure: Regenerate.
- * doc/install.texi: Document --enable-host-pie.
-
-2023-06-15 Manolis Tsamis <manolis.tsamis@vrull.eu>
-
- * regcprop.cc (maybe_mode_change): Enable stack pointer
- propagation.
-
-2023-06-15 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/110266
- * gimple-range-fold.cc (adjust_imagpart_expr): Check for integer
- complex type.
- (adjust_realpart_expr): Ditto.
-
-2023-06-15 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/sse.md (<avx512>_vec_dup<mode><mask_name>): Use
- vmovddup.
-
-2023-06-15 Jan Beulich <jbeulich@suse.com>
-
- * config/i386/constraints.md: Mention k and r for B.
-
-2023-06-15 Lulu Cheng <chenglulu@loongson.cn>
- Andrew Pinski <apinski@marvell.com>
-
- PR target/110136
- * config/loongarch/loongarch.md: Modify the register constraints for template
- "jumptable" and "indirect_jump" from "r" to "e".
-
-2023-06-15 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-tune.h (loongarch_align): New
- struct.
- * config/loongarch/loongarch-def.h (loongarch_cpu_align): New
- array.
- * config/loongarch/loongarch-def.c (loongarch_cpu_align): Define
- the array.
- * config/loongarch/loongarch.cc
- (loongarch_option_override_internal): Set the value of
- -falign-functions= if -falign-functions is enabled but no value
- is given. Likewise for -falign-labels=.
-
-2023-06-15 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/79173
- * internal-fn.def (UADDC, USUBC): New internal functions.
- * internal-fn.cc (expand_UADDC, expand_USUBC): New functions.
- (commutative_ternary_fn_p): Return true also for IFN_UADDC.
- * optabs.def (uaddc5_optab, usubc5_optab): New optabs.
- * tree-ssa-math-opts.cc (uaddc_cast, uaddc_ne0, uaddc_is_cplxpart,
- match_uaddc_usubc): New functions.
- (math_opts_dom_walker::after_dom_children): Call match_uaddc_usubc
- for PLUS_EXPR, MINUS_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR unless
- other optimizations have been successful for those.
- * gimple-fold.cc (gimple_fold_call): Handle IFN_UADDC and IFN_USUBC.
- * fold-const-call.cc (fold_const_call): Likewise.
- * gimple-range-fold.cc (adjust_imagpart_expr): Likewise.
- * tree-ssa-dce.cc (eliminate_unnecessary_stmts): Likewise.
- * doc/md.texi (uaddc<mode>5, usubc<mode>5): Document new named
- patterns.
- * config/i386/i386.md (uaddc<mode>5, usubc<mode>5): New
- define_expand patterns.
- (*setcc_qi_addqi3_cconly_overflow_1_<mode>, *setccc): Split
- into NOTE_INSN_DELETED note rather than nop instruction.
- (*setcc_qi_negqi_ccc_1_<mode>, *setcc_qi_negqi_ccc_2_<mode>):
- Likewise.
-
-2023-06-15 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/79173
- * config/i386/i386.md (subborrow<mode>): Add alternative with
- memory destination and add for it define_peephole2
- TARGET_READ_MODIFY_WRITE/-Os patterns to prefer using memory
- destination in these patterns.
-
-2023-06-15 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/79173
- * config/i386/i386.md (*sub<mode>_3, @add<mode>3_carry,
- addcarry<mode>, @sub<mode>3_carry, *add<mode>3_cc_overflow_1): Add
- define_peephole2 TARGET_READ_MODIFY_WRITE/-Os patterns to prefer
- using memory destination in these patterns.
-
-2023-06-15 Jakub Jelinek <jakub@redhat.com>
-
- * gimple-fold.cc (gimple_fold_call): Move handling of arg0
- as well as arg1 INTEGER_CSTs for .UBSAN_CHECK_{ADD,SUB,MUL}
- and .{ADD,SUB,MUL}_OVERFLOW calls from here...
- * fold-const-call.cc (fold_const_call): ... here.
-
-2023-06-15 Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>):
- Rename to <su>abd<mode>3.
- * config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Rename
- to <su>abd<mode>3.
-
-2023-06-15 Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com>
-
- * doc/md.texi (sabd, uabd): Document them.
- * internal-fn.def (ABD): Use new optab.
- * optabs.def (sabd_optab, uabd_optab): New optabs,
- * tree-vect-patterns.cc (vect_recog_absolute_difference):
- Recognize the following idiom abs (a - b).
- (vect_recog_sad_pattern): Refactor to use
- vect_recog_absolute_difference.
- (vect_recog_abd_pattern): Use patterns found by
- vect_recog_absolute_difference to build a new ABD
- internal call.
-
-2023-06-15 chenxiaolong <chenxl04200420@163.com>
-
- * config/loongarch/loongarch.h (LARCH_CALL_RATIO): Modify the value
- of macro LARCH_CALL_RATIO on LoongArch to make it perform optimally.
-
-2023-06-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (shuffle_merge_patterns): New pattern.
- (expand_vec_perm_const_1): Add merge optmization.
-
-2023-06-15 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/110119
- * config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for vector mode
- (riscv_pass_by_reference): Return true for vector mode
-
-2023-06-15 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec-opt.md: Align the predictor sytle.
- * config/riscv/autovec.md: Ditto.
-
-2023-06-15 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (rvv_builder::get_merge_scalar_mask):
- Take elen instead of scalar BITS_PER_WORD.
- (expand_vector_init_merge_repeating_sequence): Use inner_bits_size
- instead of scaler BITS_PER_WORD.
-
-2023-06-14 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * config/moxie/uclinux.h (MFWRAP_SPEC): Remove
-
-2023-06-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-base.cc (svlast_impl::fold):
- Fix signed comparison warning in loop from npats to enelts.
-
-2023-06-14 Thomas Schwinge <thomas@codesourcery.com>
-
- * gcc.cc (driver_handle_option): Forward host '-lgfortran', '-lm'
- to offloading compilation.
- * config/gcn/mkoffload.cc (main): Adjust.
- * config/nvptx/mkoffload.cc (main): Likewise.
- * doc/invoke.texi (foffload-options): Update example.
-
-2023-06-14 liuhongt <hongtao.liu@intel.com>
-
- PR target/110227
- * config/i386/sse.md (mov<mode>_internal>): Use x instead of v
- for alternative 2 since there's no evex version for vpcmpeqd
- ymm, ymm, ymm.
-
-2023-06-13 Jeff Law <jlaw@ventanamicro.com>
-
- * gcc.cc (LINK_COMMAND_SPEC): Remove mudflap spec handling.
-
-2023-06-13 Jeff Law <jlaw@ventanamicro.com>
-
- * config/sh/divtab.cc: Remove.
-
-2023-06-13 Jakub Jelinek <jakub@redhat.com>
-
- * config/i386/i386.cc (standard_sse_constant_opcode): Remove
- superfluous spaces around \t for vpcmpeqd.
-
-2023-06-13 Roger Sayle <roger@nextmovesoftware.com>
-
- * expr.cc (store_constructor) <case VECTOR_TYPE>: Don't bother
- clearing vectors with only a single element. Set CLEARED if the
- vector was initialized to zero.
-
-2023-06-13 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/riscv-v.cc (struct mode_vtype_group): Remove duplicate
- #include.
- (ENTRY): Undef.
- (TUPLE_ENTRY): Undef.
-
-2023-06-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (rvv_builder::single_step_npatterns_p): Add comment.
- (shuffle_generic_patterns): Ditto.
- (expand_vec_perm_const_1): Ditto.
-
-2023-06-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (emit_vlmax_decompress_insn): Fix bug.
- (shuffle_decompress_patterns): Ditto.
-
-2023-06-13 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-loop-ch.cc (ch_base::copy_headers): Free loop BBs.
-
-2023-06-13 Yanzhang Wang <yanzhang.wang@intel.com>
- Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
- warning flag if func is not builtin
- * config/riscv/riscv.cc
- (riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
- (riscv_arg_has_vector): Determine whether the arg is vector type.
- (riscv_pass_in_vector_p): Check the vector type param is passed by value.
- (riscv_init_cumulative_args): The same as header.
- (riscv_get_arg_info): Add the checking.
- (riscv_function_value): Check the func return and set warning flag
- * config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
- determine whether warning psabi or not.
-
-2023-06-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/arm/arm-opts.h (enum arm_tp_type): Remove TP_CP15.
- Add TP_TPIDRURW, TP_TPIDRURO, TP_TPIDRPRW values.
- * config/arm/arm-protos.h (arm_output_load_tpidr): Declare prototype.
- * config/arm/arm.cc (arm_option_reconfigure_globals): Replace TP_CP15
- with TP_TPIDRURO.
- (arm_output_load_tpidr): Define.
- * config/arm/arm.h (TARGET_HARD_TP): Define in terms of TARGET_SOFT_TP.
- * config/arm/arm.md (load_tp_hard): Call arm_output_load_tpidr to output
- assembly.
- (reload_tp_hard): Likewise.
- * config/arm/arm.opt (tpidrurw, tpidruro, tpidrprw): New values for
- arm_tp_type.
- * doc/invoke.texi (Arm Options, mtp): Document new values.
-
-2023-06-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/108779
- * config/aarch64/aarch64-opts.h (enum aarch64_tp_reg): Add
- AARCH64_TPIDRRO_EL0 value.
- * config/aarch64/aarch64.cc (aarch64_output_load_tp): Define.
- * config/aarch64/aarch64.opt (tpidr_el0, tpidr_el1, tpidr_el2,
- tpidr_el3, tpidrro_el3): New accepted values to -mtp=.
- * doc/invoke.texi (AArch64 Options): Document new -mtp= options.
-
-2023-06-13 Alexandre Oliva <oliva@adacore.com>
-
- * range-op-float.cc (frange_nextafter): Drop inline.
- (frelop_early_resolve): Add static.
- (frange_float): Likewise.
-
-2023-06-13 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110232
- * fold-const.cc (native_interpret_vector): Use TYPE_SIZE_UNIT
- to check whether the buffer covers the whole vector.
-
-2023-06-13 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): For
- .MASK_LOAD and friends set the size of the access to unknown.
-
-2023-06-13 Tejas Belagod <tbelagod@arm.com>
-
- PR target/96339
- * config/aarch64/aarch64-sve-builtins-base.cc (svlast_impl::fold): Fold sve
- calls that have a constant input predicate vector.
- (svlast_impl::is_lasta): Query to check if intrinsic is svlasta.
- (svlast_impl::is_lastb): Query to check if intrinsic is svlastb.
- (svlast_impl::vect_all_same): Check if all vector elements are equal.
-
-2023-06-13 Andi Kleen <ak@linux.intel.com>
-
- * config/i386/gcc-auto-profile: Regenerate.
-
-2023-06-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Fix requirement.
-
-2023-06-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (emit_vlmax_decompress_insn): New function.
- (shuffle_decompress_patterns): New function.
- (expand_vec_perm_const_1): Add decompress optimization.
-
-2023-06-12 Jeff Law <jlaw@ventanamicro.com>
-
- PR rtl-optimization/101188
- * postreload.cc (reload_cse_move2add_invalidate): New function,
- extracted from...
- (reload_cse_move2add): Call reload_cse_move2add_invalidate.
-
-2023-06-12 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- * config/aarch64/aarch64.cc (aarch64_expand_vector_init): Tweak condition
- if (n_var == n_elts && n_elts <= 16) to allow a single constant,
- and if maxv == 1, use constant element for duplicating into register.
-
-2023-06-12 Tobias Burnus <tobias@codesourcery.com>
-
- * gimplify.cc (gimplify_adjust_omp_clauses_1): Use
- GOMP_MAP_FORCE_PRESENT for 'present alloc' implicit mapping.
- (gimplify_adjust_omp_clauses): Change
- GOMP_MAP_PRESENT_{TO,TOFROM,FROM,ALLOC} to the equivalent
- GOMP_MAP_FORCE_PRESENT.
- * omp-low.cc (lower_omp_target): Remove handling of no-longer valid
- GOMP_MAP_PRESENT_{TO,TOFROM,FROM,ALLOC}; update map kinds used for
- to/from clauses with present modifier.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/110205
- * range-op-float.cc (range_operator::fold_range): Add default FII
- fold routine.
- * range-op-mixed.h (class operator_gt): Add missing final overrides.
- * range-op.cc (range_op_handler::fold_range): Add RO_FII case.
- (operator_lshift ::update_bitmask): Add final override.
- (operator_rshift ::update_bitmask): Add final override.
- * range-op.h (range_operator::fold_range): Add FII prototype.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-op.cc (gimple_range_op_handler::maybe_non_standard):
- Use range_op_handler directly.
- * range-op.cc (range_op_handler::range_op_handler): Unsigned
- param instead of tree-code.
- (ptr_op_widen_plus_signed): Delete.
- (ptr_op_widen_plus_unsigned): Delete.
- (ptr_op_widen_mult_signed): Delete.
- (ptr_op_widen_mult_unsigned): Delete.
- (range_op_table::initialize_integral_ops): Add new opcodes.
- * range-op.h (range_op_handler): Use unsigned.
- (OP_WIDEN_MULT_SIGNED): New.
- (OP_WIDEN_MULT_UNSIGNED): New.
- (OP_WIDEN_PLUS_SIGNED): New.
- (OP_WIDEN_PLUS_UNSIGNED): New.
- (RANGE_OP_TABLE_SIZE): New.
- (range_op_table::operator []): Use unsigned.
- (range_op_table::set): Use unsigned.
- (m_range_tree): Make unsigned.
- (ptr_op_widen_mult_signed): Remove.
- (ptr_op_widen_mult_unsigned): Remove.
- (ptr_op_widen_plus_signed): Remove.
- (ptr_op_widen_plus_unsigned): Remove.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-op.cc (gimple_range_op_handler): Set m_operator
- manually as there is no access to the default operator.
- (cfn_copysign::fold_range): Don't check for validity.
- (cfn_ubsan::fold_range): Ditto.
- (gimple_range_op_handler::maybe_builtin_call): Don't set to NULL.
- * range-op.cc (default_operator): New.
- (range_op_handler::range_op_handler): Use default_operator
- instead of NULL.
- (range_op_handler::operator bool): Move from header, compare
- against default operator.
- (range_op_handler::range_op): New.
- * range-op.h (range_op_handler::operator bool): Move.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op.cc (unified_table): Delete.
- (range_op_table operator_table): Instantiate.
- (range_op_table::range_op_table): Rename from unified_table.
- (range_op_handler::range_op_handler): Use range_op_table.
- * range-op.h (range_op_table::operator []): Inline.
- (range_op_table::set): Inline.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (gori_compute::condexpr_adjust): Do not
- pass type.
- * gimple-range-op.cc (get_code): Rename from get_code_and_type
- and simplify.
- (gimple_range_op_handler::supported_p): No need for type.
- (gimple_range_op_handler::gimple_range_op_handler): Ditto.
- (cfn_copysign::fold_range): Ditto.
- (cfn_ubsan::fold_range): Ditto.
- * ipa-cp.cc (ipa_vr_operation_and_type_effects): Ditto.
- * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Ditto.
- * range-op-float.cc (operator_plus::op1_range): Ditto.
- (operator_mult::op1_range): Ditto.
- (range_op_float_tests): Ditto.
- * range-op.cc (get_op_handler): Remove.
- (range_op_handler::set_op_handler): Remove.
- (operator_plus::op1_range): No need for type.
- (operator_minus::op1_range): Ditto.
- (operator_mult::op1_range): Ditto.
- (operator_exact_divide::op1_range): Ditto.
- (operator_cast::op1_range): Ditto.
- (perator_bitwise_not::fold_range): Ditto.
- (operator_negate::fold_range): Ditto.
- * range-op.h (range_op_handler::range_op_handler): Remove type param.
- (range_cast): No need for type.
- (range_op_table::operator[]): Check for enum_code >= 0.
- * tree-data-ref.cc (compute_distributive_range): No need for type.
- * tree-ssa-loop-unswitch.cc (unswitch_predicate): Ditto.
- * value-query.cc (range_query::get_tree_range): Ditto.
- * value-relation.cc (relation_oracle::validate_relation): Ditto.
- * vr-values.cc (range_of_var_in_loop): Ditto.
- (simplify_using_ranges::fold_cond_with_ops): Ditto.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (operator_max): Remove final.
- * range-op-ptr.cc (pointer_table::pointer_table): Remove MAX_EXPR.
- (pointer_table::pointer_table): Remove.
- (class hybrid_max_operator): New.
- (range_op_table::initialize_pointer_ops): Add hybrid_max_operator.
- * range-op.cc (pointer_tree_table): Remove.
- (unified_table::unified_table): Comment out MAX_EXPR.
- (get_op_handler): Remove check of pointer table.
- * range-op.h (class pointer_table): Remove.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (operator_min): Remove final.
- * range-op-ptr.cc (pointer_table::pointer_table): Remove MIN_EXPR.
- (class hybrid_min_operator): New.
- (range_op_table::initialize_pointer_ops): Add hybrid_min_operator.
- * range-op.cc (unified_table::unified_table): Comment out MIN_EXPR.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (operator_bitwise_or): Remove final.
- * range-op-ptr.cc (pointer_table::pointer_table): Remove BIT_IOR_EXPR.
- (class hybrid_or_operator): New.
- (range_op_table::initialize_pointer_ops): Add hybrid_or_operator.
- * range-op.cc (unified_table::unified_table): Comment out BIT_IOR_EXPR.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (operator_bitwise_and): Remove final.
- * range-op-ptr.cc (pointer_table::pointer_table): Remove BIT_AND_EXPR.
- (class hybrid_and_operator): New.
- (range_op_table::initialize_pointer_ops): Add hybrid_and_operator.
- * range-op.cc (unified_table::unified_table): Comment out BIT_AND_EXPR.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * Makefile.in (OBJS): Add range-op-ptr.o.
- * range-op-mixed.h (update_known_bitmask): Move prototype here.
- (minus_op1_op2_relation_effect): Move prototype here.
- (wi_includes_zero_p): Move function to here.
- (wi_zero_p): Ditto.
- * range-op.cc (update_known_bitmask): Remove static.
- (wi_includes_zero_p): Move to header.
- (wi_zero_p): Move to header.
- (minus_op1_op2_relation_effect): Remove static.
- (operator_pointer_diff): Move class and routines to range-op-ptr.cc.
- (pointer_plus_operator): Ditto.
- (pointer_min_max_operator): Ditto.
- (pointer_and_operator): Ditto.
- (pointer_or_operator): Ditto.
- (pointer_table): Ditto.
- (range_op_table::initialize_pointer_ops): Ditto.
- * range-op-ptr.cc: New.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (class operator_max): Move from...
- * range-op.cc (unified_table::unified_table): Add MAX_EXPR.
- (get_op_handler): Remove the integral table.
- (class operator_max): Move from here.
- (integral_table::integral_table): Delete.
- * range-op.h (class integral_table): Delete.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (class operator_min): Move from...
- * range-op.cc (unified_table::unified_table): Add MIN_EXPR.
- (class operator_min): Move from here.
- (integral_table::integral_table): Remove MIN_EXPR.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (class operator_bitwise_or): Move from...
- * range-op.cc (unified_table::unified_table): Add BIT_IOR_EXPR.
- (class operator_bitwise_or): Move from here.
- (integral_table::integral_table): Remove BIT_IOR_EXPR.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (class operator_bitwise_and): Move from...
- * range-op.cc (unified_table::unified_table): Add BIT_AND_EXPR.
- (get_op_handler): Check for a pointer table entry first.
- (class operator_bitwise_and): Move from here.
- (integral_table::integral_table): Remove BIT_AND_EXPR.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (class operator_bitwise_xor): Move from...
- * range-op.cc (unified_table::unified_table): Add BIT_XOR_EXPR.
- (class operator_bitwise_xor): Move from here.
- (integral_table::integral_table): Remove BIT_XOR_EXPR.
- (pointer_table::pointer_table): Remove BIT_XOR_EXPR.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (class operator_bitwise_not): Move from...
- * range-op.cc (unified_table::unified_table): Add BIT_NOT_EXPR.
- (class operator_bitwise_not): Move from here.
- (integral_table::integral_table): Remove BIT_NOT_EXPR.
- (pointer_table::pointer_table): Remove BIT_NOT_EXPR.
-
-2023-06-12 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (class operator_addr_expr): Move from...
- * range-op.cc (unified_table::unified_table): Add ADDR_EXPR.
- (class operator_addr_expr): Move from here.
- (integral_table::integral_table): Remove ADDR_EXPR.
- (pointer_table::pointer_table): Remove ADDR_EXPR.
-
-2023-06-12 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-types.def
- (vfloat16m1_t): Add type to lmul1 ops.
- (vfloat16m2_t): Likewise.
- (vfloat16m4_t): Likewise.
-
-2023-06-12 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-alias.cc (call_may_clobber_ref_p_1): For
- .MASK_STORE and friend set the size of the access to
- unknown.
-
-2023-06-12 Tamar Christina <tamar.christina@arm.com>
-
- * config.in: Regenerate.
- * configure: Regenerate.
- * configure.ac: Remove DEFAULT_MATCHPD_PARTITIONS.
-
-2023-06-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md
- (*v<any_shiftrt:optab><any_extend:optab>trunc<mode>): New pattern.
- (*<any_shiftrt:optab>trunc<mode>): Ditto.
- * config/riscv/autovec.md (<optab><mode>3): Change to
- define_insn_and_split.
- (v<optab><mode>3): Ditto.
- (trunc<mode><v_double_trunc>2): Ditto.
-
-2023-06-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * simplify-rtx.cc (simplify_const_unary_operation):
- Handle US_TRUNCATE, SS_TRUNCATE.
-
-2023-06-12 Eric Botcazou <ebotcazou@adacore.com>
-
- PR modula2/109952
- * doc/gm2.texi (Standard procedures): Fix Next link.
-
-2023-06-12 Tamar Christina <tamar.christina@arm.com>
-
- * config.in: Regenerate.
-
-2023-06-12 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR middle-end/110142
- * tree-vect-patterns.cc (vect_recog_widen_op_pattern): Don't pass
- subtype to vect_widened_op_tree and remove subtype parameter, also
- remove superfluous overloaded function definition.
- (vect_recog_widen_plus_pattern): Remove subtype parameter and dont pass
- to call to vect_recog_widen_op_pattern.
- (vect_recog_widen_minus_pattern): Likewise.
-
-2023-06-12 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (vec_pack<floatprefix>_float_<mode>): New expander.
- (vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Ditto.
- (vec_unpack_<fixprefix>fix_trunc_hi_<mode>): Ditto.
- (vec_unpacks_lo_<mode>): Ditto.
- (vec_unpacks_hi_<mode>): Ditto.
- (sse_movlhps_<mode>): New define_insn.
- (ssse3_palignr<mode>_perm): Extend to V_128H.
- (V_128H): New mode iterator.
- (ssepackPHmode): New mode attribute.
- (vunpck_extract_mode): Ditto.
- (vpckfloat_concat_mode): Extend to VxSI/VxSF for _Float16.
- (vpckfloat_temp_mode): Ditto.
- (vpckfloat_op_mode): Ditto.
- (vunpckfixt_mode): Extend to VxHF.
- (vunpckfixt_model): Ditto.
- (vunpckfixt_extract_mode): Ditto.
-
-2023-06-12 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110200
- * genmatch.cc (expr::gen_transform): Put braces around
- the if arm for the (convert ...) short-cut.
-
-2023-06-12 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/109932
- * config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
- __builtin_unpack_vector_int128): Move from stanza power7 to vsx.
-
-2023-06-12 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/110011
- * config/rs6000/rs6000.cc (output_toc): Use the mode of the 128-bit
- floating constant itself for real_to_target call.
-
-2023-06-12 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-types.def
- (vfloat16mf4_t): Add type to X2/X4/X8/X16/X32 vlmul ext ops.
- (vfloat16mf2_t): Ditto.
- (vfloat16m1_t): Ditto.
- (vfloat16m2_t): Ditto.
- (vfloat16m4_t): Ditto.
-
-2023-06-12 David Edelsohn <dje.gcc@gmail.com>
-
- * config/rs6000/rs6000-logue.cc (rs6000_stack_info):
- Do not require a stack frame when debugging is enabled for AIX.
-
-2023-06-11 Georg-Johann Lay <avr@gjlay.de>
-
- * config/avr/avr.md (adjust_len) [insv_notbit_0, insv_notbit_7]:
- Remove attribute values.
- (insv_notbit): New post-reload insn.
- (*insv.not-shiftrt_split, *insv.xor1-bit.0_split)
- (*insv.not-bit.0_split, *insv.not-bit.7_split)
- (*insv.xor-extract_split): Split to insv_notbit.
- (*insv.not-shiftrt, *insv.xor1-bit.0, *insv.not-bit.0, *insv.not-bit.7)
- (*insv.xor-extract): Remove post-reload insns.
- * config/avr/avr.cc (avr_out_insert_notbit) [bitno]: Remove parameter.
- (avr_adjust_insn_length): Adjust call of avr_out_insert_notbit.
- [ADJUST_LEN_INSV_NOTBIT_0, ADJUST_LEN_INSV_NOTBIT_7]: Remove cases.
- * config/avr/avr-protos.h (avr_out_insert_notbit): Adjust prototype.
-
-2023-06-11 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/109907
- * config/avr/avr.md (adjust_len) [extr, extr_not]: New elements.
- (MSB, SIZE): New mode attributes.
- (any_shift): New code iterator.
- (*lshr<mode>3_split, *lshr<mode>3, lshr<mode>3)
- (*lshr<mode>3_const_split): Add constraint alternative for
- the case of shift-offset = MSB. Ditch "length" attribute.
- (extzv<mode): New. replaces extzv. Adjust following patterns.
- Use avr_out_extr, avr_out_extr_not to print asm.
- (*extzv.subreg.<mode>, *extzv.<mode>.subreg, *extzv.xor)
- (*extzv<mode>.ge, *neg.ashiftrt<mode>.msb, *extzv.io.lsr7): New.
- * config/avr/constraints.md (C15, C23, C31, Yil): New
- * config/avr/predicates.md (reg_or_low_io_operand)
- (const7_operand, reg_or_low_io_operand)
- (const15_operand, const_0_to_15_operand)
- (const23_operand, const_0_to_23_operand)
- (const31_operand, const_0_to_31_operand): New.
- * config/avr/avr-protos.h (avr_out_extr, avr_out_extr_not): New.
- * config/avr/avr.cc (avr_out_extr, avr_out_extr_not): New funcs.
- (lshrqi3_out, lshrhi3_out, lshrpsi3_out, lshrsi3_out): Adjust
- MSB case to new insn constraint "r" for operands[1].
- (avr_adjust_insn_length) [ADJUST_LEN_EXTR_NOT, ADJUST_LEN_EXTR]:
- Handle these cases.
- (avr_rtx_costs_1): Adjust cost for a new pattern.
-
-2023-06-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (available_occurrence_p): Enhance user vsetvl optimization.
- (vector_insn_info::parse_insn): Add rtx_insn parse.
- (pass_vsetvl::local_eliminate_vsetvl_insn): Enhance user vsetvl optimization.
- (get_first_vsetvl): New function.
- (pass_vsetvl::global_eliminate_vsetvl_insn): Ditto.
- (pass_vsetvl::cleanup_insns): Remove it.
- (pass_vsetvl::ssa_post_optimization): New function.
- (has_no_uses): Ditto.
- (pass_vsetvl::propagate_avl): Remove it.
- (pass_vsetvl::df_post_optimization): New function.
- (pass_vsetvl::lazy_vsetvl): Rework Phase 5 && Phase 6.
- * config/riscv/riscv-vsetvl.h: Adapt declaration.
-
-2023-06-10 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-cp.cc (ipcp_vr_lattice::init): Take type argument.
- (ipcp_vr_lattice::print): Call dump method.
- (ipcp_vr_lattice::meet_with): Adjust for m_vr being a
- Value_Range.
- (ipcp_vr_lattice::meet_with_1): Make argument a reference.
- (ipcp_vr_lattice::set_to_bottom): Set varying for an unsupported
- range.
- (initialize_node_lattices): Pass type when appropriate.
- (ipa_vr_operation_and_type_effects): Make type agnostic.
- (ipa_value_range_from_jfunc): Same.
- (propagate_vr_across_jump_function): Same.
- * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same.
- (evaluate_properties_for_edge): Same.
- * ipa-prop.cc (ipa_vr::get_vrange): Same.
- (ipcp_update_vr): Same.
- * ipa-prop.h (ipa_value_range_from_jfunc): Same.
- (ipa_range_set_and_normalize): Same.
-
-2023-06-10 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/109650
- PR target/92729
- * config/avr/avr-passes.def (avr_pass_ifelse): Insert new pass.
- * config/avr/avr.cc (avr_pass_ifelse): New RTL pass.
- (avr_pass_data_ifelse): New pass_data for it.
- (make_avr_pass_ifelse, avr_redundant_compare, avr_cbranch_cost)
- (avr_canonicalize_comparison, avr_out_plus_set_ZN)
- (avr_out_cmp_ext): New functions.
- (compare_condtition): Make sure REG_CC dies in the branch insn.
- (avr_rtx_costs_1): Add computation of cbranch costs.
- (avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_ZN, ADJUST_LEN_CMP_ZEXT]:
- [ADJUST_LEN_CMP_SEXT]Handle them.
- (TARGET_CANONICALIZE_COMPARISON): New define.
- (avr_simplify_comparison_p, compare_diff_p, avr_compare_pattern)
- (avr_reorg_remove_redundant_compare, avr_reorg): Remove functions.
- (TARGET_MACHINE_DEPENDENT_REORG): Remove define.
- * config/avr/avr-protos.h (avr_simplify_comparison_p): Remove proto.
- (make_avr_pass_ifelse, avr_out_plus_set_ZN, cc_reg_rtx)
- (avr_out_cmp_zext): New Protos
- * config/avr/avr.md (branch, difficult_branch): Don't split insns.
- (*cbranchhi.zero-extend.0", *cbranchhi.zero-extend.1")
- (*swapped_tst<mode>, *add.for.eqne.<mode>): New insns.
- (*cbranch<mode>4): Rename to cbranch<mode>4_insn.
- (define_peephole): Add dead_or_set_regno_p(insn,REG_CC) as needed.
- (define_deephole2): Add peep2_regno_dead_p(*,REG_CC) as needed.
- Add new RTL peepholes for decrement-and-branch and *swapped_tst<mode>.
- Rework signtest-and-branch peepholes for *sbrx_branch<mode>.
- (adjust_len) [add_set_ZN, cmp_zext]: New.
- (QIPSI): New mode iterator.
- (ALLs1, ALLs2, ALLs4, ALLs234): New mode iterators.
- (gelt): New code iterator.
- (gelt_eqne): New code attribute.
- (rvbranch, *rvbranch, difficult_rvbranch, *difficult_rvbranch)
- (branch_unspec, *negated_tst<mode>, *reversed_tst<mode>)
- (*cmpqi_sign_extend): Remove insns.
- (define_c_enum "unspec") [UNSPEC_IDENTITY]: Remove.
- * config/avr/avr-dimode.md (cbranch<mode>4): Canonicalize comparisons.
- * config/avr/predicates.md (scratch_or_d_register_operand): New.
- * config/avr/constraints.md (Yxx): New constraint.
-
-2023-06-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (select_vl<mode>): New pattern.
- * config/riscv/riscv-protos.h (expand_select_vl): New function.
- * config/riscv/riscv-v.cc (expand_select_vl): Ditto.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_mult_div_base): Delete.
- (foperator_mult_div_base::find_range): Make static local function.
- (foperator_mult): Remove. Move prototypes to range-op-mixed.h
- (operator_mult::op1_range): Rename from foperator_mult.
- (operator_mult::op2_range): Ditto.
- (operator_mult::rv_fold): Ditto.
- (float_table::float_table): Remove MULT_EXPR.
- (class foperator_div): Inherit from range_operator.
- (float_table::float_table): Delete.
- * range-op-mixed.h (class operator_mult): Combined from integer
- and float files.
- * range-op.cc (float_tree_table): Delete.
- (op_mult): New object.
- (unified_table::unified_table): Add MULT_EXPR.
- (get_op_handler): Do not check float table any longer.
- (class cross_product_operator): Move to range-op-mixed.h.
- (class operator_mult): Move to range-op-mixed.h.
- (integral_table::integral_table): Remove MULT_EXPR.
- (pointer_table::pointer_table): Remove MULT_EXPR.
- * range-op.h (float_table): Remove.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_negate): Remove. Move prototypes
- to range-op-mixed.h
- (operator_negate::fold_range): Rename from foperator_negate.
- (operator_negate::op1_range): Ditto.
- (float_table::float_table): Remove NEGATE_EXPR.
- * range-op-mixed.h (class operator_negate): Combined from integer
- and float files.
- * range-op.cc (op_negate): New object.
- (unified_table::unified_table): Add NEGATE_EXPR.
- (class operator_negate): Move to range-op-mixed.h.
- (integral_table::integral_table): Remove NEGATE_EXPR.
- (pointer_table::pointer_table): Remove NEGATE_EXPR.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_minus): Remove. Move prototypes
- to range-op-mixed.h
- (operator_minus::fold_range): Rename from foperator_minus.
- (operator_minus::op1_range): Ditto.
- (operator_minus::op2_range): Ditto.
- (operator_minus::rv_fold): Ditto.
- (float_table::float_table): Remove MINUS_EXPR.
- * range-op-mixed.h (class operator_minus): Combined from integer
- and float files.
- * range-op.cc (op_minus): New object.
- (unified_table::unified_table): Add MINUS_EXPR.
- (class operator_minus): Move to range-op-mixed.h.
- (integral_table::integral_table): Remove MINUS_EXPR.
- (pointer_table::pointer_table): Remove MINUS_EXPR.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_abs): Remove. Move prototypes
- to range-op-mixed.h
- (operator_abs::fold_range): Rename from foperator_abs.
- (operator_abs::op1_range): Ditto.
- (float_table::float_table): Remove ABS_EXPR.
- * range-op-mixed.h (class operator_abs): Combined from integer
- and float files.
- * range-op.cc (op_abs): New object.
- (unified_table::unified_table): Add ABS_EXPR.
- (class operator_abs): Move to range-op-mixed.h.
- (integral_table::integral_table): Remove ABS_EXPR.
- (pointer_table::pointer_table): Remove ABS_EXPR.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_plus): Remove. Move prototypes
- to range-op-mixed.h
- (operator_plus::fold_range): Rename from foperator_plus.
- (operator_plus::op1_range): Ditto.
- (operator_plus::op2_range): Ditto.
- (operator_plus::rv_fold): Ditto.
- (float_table::float_table): Remove PLUS_EXPR.
- * range-op-mixed.h (class operator_plus): Combined from integer
- and float files.
- * range-op.cc (op_plus): New object.
- (unified_table::unified_table): Add PLUS_EXPR.
- (class operator_plus): Move to range-op-mixed.h.
- (integral_table::integral_table): Remove PLUS_EXPR.
- (pointer_table::pointer_table): Remove PLUS_EXPR.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (class operator_cast): Combined from integer
- and float files.
- * range-op.cc (op_cast): New object.
- (unified_table::unified_table): Add op_cast
- (class operator_cast): Move to range-op-mixed.h.
- (integral_table::integral_table): Remove op_cast
- (pointer_table::pointer_table): Remove op_cast.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (operator_cst::fold_range): New.
- * range-op-mixed.h (class operator_cst): Move from integer file.
- * range-op.cc (op_cst): New object.
- (unified_table::unified_table): Add op_cst. Also use for REAL_CST.
- (class operator_cst): Move to range-op-mixed.h.
- (integral_table::integral_table): Remove op_cst.
- (pointer_table::pointer_table): Remove op_cst.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_identity): Remove. Move prototypes
- to range-op-mixed.h
- (operator_identity::fold_range): Rename from foperator_identity.
- (operator_identity::op1_range): Ditto.
- (float_table::float_table): Remove fop_identity.
- * range-op-mixed.h (class operator_identity): Combined from integer
- and float files.
- * range-op.cc (op_identity): New object.
- (unified_table::unified_table): Add op_identity.
- (class operator_identity): Move to range-op-mixed.h.
- (integral_table::integral_table): Remove identity.
- (pointer_table::pointer_table): Remove identity.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_ge): Remove. Move prototypes
- to range-op-mixed.h
- (operator_ge::fold_range): Rename from foperator_ge.
- (operator_ge::op1_range): Ditto.
- (float_table::float_table): Remove GE_EXPR.
- * range-op-mixed.h (class operator_ge): Combined from integer
- and float files.
- * range-op.cc (op_ge): New object.
- (unified_table::unified_table): Add GE_EXPR.
- (class operator_ge): Move to range-op-mixed.h.
- (ge_op1_op2_relation): Fold into
- operator_ge::op1_op2_relation.
- (integral_table::integral_table): Remove GE_EXPR.
- (pointer_table::pointer_table): Remove GE_EXPR.
- * range-op.h (ge_op1_op2_relation): Delete.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_gt): Remove. Move prototypes
- to range-op-mixed.h
- (operator_gt::fold_range): Rename from foperator_gt.
- (operator_gt::op1_range): Ditto.
- (float_table::float_table): Remove GT_EXPR.
- * range-op-mixed.h (class operator_gt): Combined from integer
- and float files.
- * range-op.cc (op_gt): New object.
- (unified_table::unified_table): Add GT_EXPR.
- (class operator_gt): Move to range-op-mixed.h.
- (gt_op1_op2_relation): Fold into
- operator_gt::op1_op2_relation.
- (integral_table::integral_table): Remove GT_EXPR.
- (pointer_table::pointer_table): Remove GT_EXPR.
- * range-op.h (gt_op1_op2_relation): Delete.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_le): Remove. Move prototypes
- to range-op-mixed.h
- (operator_le::fold_range): Rename from foperator_le.
- (operator_le::op1_range): Ditto.
- (float_table::float_table): Remove LE_EXPR.
- * range-op-mixed.h (class operator_le): Combined from integer
- and float files.
- * range-op.cc (op_le): New object.
- (unified_table::unified_table): Add LE_EXPR.
- (class operator_le): Move to range-op-mixed.h.
- (le_op1_op2_relation): Fold into
- operator_le::op1_op2_relation.
- (integral_table::integral_table): Remove LE_EXPR.
- (pointer_table::pointer_table): Remove LE_EXPR.
- * range-op.h (le_op1_op2_relation): Delete.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_lt): Remove. Move prototypes
- to range-op-mixed.h
- (operator_lt::fold_range): Rename from foperator_lt.
- (operator_lt::op1_range): Ditto.
- (float_table::float_table): Remove LT_EXPR.
- * range-op-mixed.h (class operator_lt): Combined from integer
- and float files.
- * range-op.cc (op_lt): New object.
- (unified_table::unified_table): Add LT_EXPR.
- (class operator_lt): Move to range-op-mixed.h.
- (lt_op1_op2_relation): Fold into
- operator_lt::op1_op2_relation.
- (integral_table::integral_table): Remove LT_EXPR.
- (pointer_table::pointer_table): Remove LT_EXPR.
- * range-op.h (lt_op1_op2_relation): Delete.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_not_equal): Remove. Move prototypes
- to range-op-mixed.h
- (operator_equal::fold_range): Rename from foperator_not_equal.
- (operator_equal::op1_range): Ditto.
- (float_table::float_table): Remove NE_EXPR.
- * range-op-mixed.h (class operator_not_equal): Combined from integer
- and float files.
- * range-op.cc (op_equal): New object.
- (unified_table::unified_table): Add NE_EXPR.
- (class operator_not_equal): Move to range-op-mixed.h.
- (not_equal_op1_op2_relation): Fold into
- operator_not_equal::op1_op2_relation.
- (integral_table::integral_table): Remove NE_EXPR.
- (pointer_table::pointer_table): Remove NE_EXPR.
- * range-op.h (not_equal_op1_op2_relation): Delete.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (foperator_equal): Remove. Move prototypes
- to range-op-mixed.h
- (operator_equal::fold_range): Rename from foperator_equal.
- (operator_equal::op1_range): Ditto.
- (float_table::float_table): Remove EQ_EXPR.
- * range-op-mixed.h (class operator_equal): Combined from integer
- and float files.
- * range-op.cc (op_equal): New object.
- (unified_table::unified_table): Add EQ_EXPR.
- (class operator_equal): Move to range-op-mixed.h.
- (equal_op1_op2_relation): Fold into
- operator_equal::op1_op2_relation.
- (integral_table::integral_table): Remove EQ_EXPR.
- (pointer_table::pointer_table): Remove EQ_EXPR.
- * range-op.h (equal_op1_op2_relation): Delete.
-
-2023-06-10 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (class float_table): Move to header.
- (float_table::float_table): Move float only operators to...
- (range_op_table::initialize_float_ops): Here.
- * range-op-mixed.h: New.
- * range-op.cc (integral_tree_table, pointer_tree_table): Moved
- to top of file.
- (float_tree_table): Moved from range-op-float.cc.
- (unified_tree_table): New.
- (unified_table::unified_table): New. Call initialize routines.
- (get_op_handler): Check unified table first.
- (range_op_handler::range_op_handler): Handle no type constructor.
- (integral_table::integral_table): Move integral only operators to...
- (range_op_table::initialize_integral_ops): Here.
- (pointer_table::pointer_table): Move pointer only operators to...
- (range_op_table::initialize_pointer_ops): Here.
- * range-op.h (enum bool_range_state): Move to range-op-mixed.h.
- (get_bool_state): Ditto.
- (empty_range_varying): Ditto.
- (relop_early_resolve): Ditto.
- (class range_op_table): Add new init methods for range types.
- (class integral_table): Move declaration to here.
- (class pointer_table): Move declaration to here.
- (class float_table): Move declaration to here.
-
-2023-06-09 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- Richard Sandiford <richard.sandiford@arm.com>
- Richard Biener <rguenther@suse.de>
-
- * doc/md.texi: Add SELECT_VL support.
- * internal-fn.def (SELECT_VL): Ditto.
- * optabs.def (OPTAB_D): Ditto.
- * tree-vect-loop-manip.cc (vect_set_loop_controls_directly): Ditto.
- * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Ditto.
- * tree-vect-stmts.cc (get_select_vl_data_ref_ptr): Ditto.
- (vectorizable_store): Ditto.
- (vectorizable_load): Ditto.
- * tree-vectorizer.h (LOOP_VINFO_USING_SELECT_VL_P): Ditto.
-
-2023-06-09 Andrew MacLeod <amacleod@redhat.com>
-
- PR ipa/109886
- * ipa-prop.cc (ipa_compute_jump_functions_for_edge): Check param
- type as well.
-
-2023-06-09 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op.cc (range_cast): Move to...
- * range-op.h (range_cast): Here and add generic a version.
-
-2023-06-09 Marek Polacek <polacek@redhat.com>
-
- PR c/39589
- PR c++/96868
- * doc/invoke.texi: Clarify that -Wmissing-field-initializers doesn't
- warn about designated initializers in C only.
-
-2023-06-09 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/97711
- PR tree-optimization/110155
- * match.pd ((zero_one == 0) ? y : z <op> y): Add plus to the op.
- ((zero_one != 0) ? z <op> y : y): Likewise.
-
-2023-06-09 Andrew Pinski <apinski@marvell.com>
-
- * match.pd ((zero_one ==/!= 0) ? y : z <op> y): Use
- multiply rather than negation/bit_and.
-
-2023-06-09 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`X & -Y -> X * Y`): Allow for truncation
- and the same type for unsigned types.
-
-2023-06-09 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110165
- PR tree-optimization/110166
- * match.pd (zero_one_valued_p): Don't accept
- signed 1-bit integers.
-
-2023-06-09 Richard Biener <rguenther@suse.de>
-
- * match.pd (two conversions in a row): Use element_precision
- to DTRT for VECTOR_TYPE.
-
-2023-06-09 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv.md (enabled): Move to another place, and
- add fp_vector_disabled to the cond.
- (fp_vector_disabled): New attr defined for disabling fp.
- * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
-
-2023-06-09 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-protos.h (enum frm_field_enum): Adjust
- literal to int.
-
-2023-06-09 liuhongt <hongtao.liu@intel.com>
-
- PR target/110108
- * config/i386/i386.cc (ix86_gimple_fold_builtin): Explicitly
- view_convert_expr mask to signed type when folding pblendvb
- builtins.
-
-2023-06-09 liuhongt <hongtao.liu@intel.com>
-
- PR target/110108
- * config/i386/i386.cc (ix86_gimple_fold_builtin): Fold
- _mm{,256,512}_abs_{epi8,epi16,epi32,epi64} into gimple
- ABSU_EXPR + VCE, don't fold _mm_abs_{pi8,pi16,pi32} w/o
- TARGET_64BIT.
- * config/i386/i386-builtin.def: Replace CODE_FOR_nothing with
- real codename for __builtin_ia32_pabs{b,w,d}.
-
-2023-06-08 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-op.cc
- (gimple_range_op_handler::gimple_range_op_handler): Adjust.
- (gimple_range_op_handler::maybe_builtin_call): Adjust.
- * gimple-range-op.h (operand1, operand2): Use m_operator.
- * range-op.cc (integral_table, pointer_table): Relocate.
- (get_op_handler): Rename from get_handler and handle all types.
- (range_op_handler::range_op_handler): Relocate.
- (range_op_handler::set_op_handler): Relocate and adjust.
- (range_op_handler::range_op_handler): Relocate.
- (dispatch_trio): New.
- (RO_III, RO_IFI, RO_IFF, RO_FFF, RO_FIF, RO_FII): New consts.
- (range_op_handler::dispatch_kind): New.
- (range_op_handler::fold_range): Relocate and Use new dispatch value.
- (range_op_handler::op1_range): Ditto.
- (range_op_handler::op2_range): Ditto.
- (range_op_handler::lhs_op1_relation): Ditto.
- (range_op_handler::lhs_op2_relation): Ditto.
- (range_op_handler::op1_op2_relation): Ditto.
- (range_op_handler::set_op_handler): Use m_operator member.
- * range-op.h (range_op_handler::operator bool): Use m_operator.
- (range_op_handler::dispatch_kind): New.
- (range_op_handler::m_valid): Delete.
- (range_op_handler::m_int): Delete
- (range_op_handler::m_float): Delete
- (range_op_handler::m_operator): New.
- (range_op_table::operator[]): Relocate from .cc file.
- (range_op_table::set): Ditto.
- * value-range.h (class vrange): Make range_op_handler a friend.
-
-2023-06-08 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-op.cc (cfn_constant_float_p): Change base class.
- (cfn_pass_through_arg1): Adjust using statemenmt.
- (cfn_signbit): Change base class, adjust using statement.
- (cfn_copysign): Ditto.
- (cfn_sqrt): Ditto.
- (cfn_sincos): Ditto.
- * range-op-float.cc (fold_range): Change class to range_operator.
- (rv_fold): Ditto.
- (op1_range): Ditto
- (op2_range): Ditto
- (lhs_op1_relation): Ditto.
- (lhs_op2_relation): Ditto.
- (op1_op2_relation): Ditto.
- (foperator_*): Ditto.
- (class float_table): New. Inherit from range_op_table.
- (floating_tree_table) Change to range_op_table pointer.
- (class floating_op_table): Delete.
- * range-op.cc (operator_equal): Adjust using statement.
- (operator_not_equal): Ditto.
- (operator_lt, operator_le, operator_gt, operator_ge): Ditto.
- (operator_minus, operator_cast): Ditto.
- (operator_bitwise_and, pointer_plus_operator): Ditto.
- (get_float_handle): Change return type.
- * range-op.h (range_operator_float): Delete. Relocate all methods
- into class range_operator.
- (range_op_handler::m_float): Change type to range_operator.
- (floating_op_table): Delete.
- (floating_tree_table): Change type.
-
-2023-06-08 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op.cc (range_operator::fold_range): Call virtual routine.
- (range_operator::update_bitmask): New.
- (operator_equal::update_bitmask): New.
- (operator_not_equal::update_bitmask): New.
- (operator_lt::update_bitmask): New.
- (operator_le::update_bitmask): New.
- (operator_gt::update_bitmask): New.
- (operator_ge::update_bitmask): New.
- (operator_ge::update_bitmask): New.
- (operator_plus::update_bitmask): New.
- (operator_minus::update_bitmask): New.
- (operator_pointer_diff::update_bitmask): New.
- (operator_min::update_bitmask): New.
- (operator_max::update_bitmask): New.
- (operator_mult::update_bitmask): New.
- (operator_div:operator_div):New.
- (operator_div::update_bitmask): New.
- (operator_div::m_code): New member.
- (operator_exact_divide::operator_exact_divide): New constructor.
- (operator_lshift::update_bitmask): New.
- (operator_rshift::update_bitmask): New.
- (operator_bitwise_and::update_bitmask): New.
- (operator_bitwise_or::update_bitmask): New.
- (operator_bitwise_xor::update_bitmask): New.
- (operator_trunc_mod::update_bitmask): New.
- (op_ident, op_unknown, op_ptr_min_max): New.
- (op_nop, op_convert): Delete.
- (op_ssa, op_paren, op_obj_type): Delete.
- (op_realpart, op_imagpart): Delete.
- (op_ptr_min, op_ptr_max): Delete.
- (pointer_plus_operator:update_bitmask): New.
- (range_op_table::set): Do not use m_code.
- (integral_table::integral_table): Adjust to single instances.
- * range-op.h (range_operator::range_operator): Delete.
- (range_operator::m_code): Delete.
- (range_operator::update_bitmask): New.
-
-2023-06-08 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-float.cc (range_operator_float::fold_range): Return
- NAN of the result type.
-
-2023-06-08 Jakub Jelinek <jakub@redhat.com>
-
- * optabs.cc (expand_ffs): Add forward declaration.
- (expand_doubleword_clz): Rename to ...
- (expand_doubleword_clz_ctz_ffs): ... this. Add UNOPTAB argument,
- handle also doubleword CTZ and FFS in addition to CLZ.
- (expand_unop): Adjust caller. Also call it for doubleword
- ctz_optab and ffs_optab.
-
-2023-06-08 Jakub Jelinek <jakub@redhat.com>
-
- PR target/110152
- * config/i386/i386-expand.cc (ix86_expand_vector_init_general): For
- n_words == 2 recurse with mmx_ok as first argument rather than false.
-
-2023-06-07 Roger Sayle <roger@nextmovesoftware.com>
-
- * wide-int.cc (wi::bitreverse_large): Use HOST_WIDE_INT_1U to
- avoid sign extension/undefined behaviour when setting each bit.
-
-2023-06-07 Roger Sayle <roger@nextmovesoftware.com>
- Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_builtin) <handlecarry>:
- Use new x86_stc instruction when the carry flag must be set.
- * config/i386/i386.cc (ix86_cc_mode): Use CCCmode for *x86_cmc.
- (ix86_rtx_costs): Provide accurate rtx_costs for *x86_cmc.
- * config/i386/i386.h (TARGET_SLOW_STC): New define.
- * config/i386/i386.md (UNSPEC_STC): New UNSPEC for stc.
- (x86_stc): New define_insn.
- (define_peephole2): Convert x86_stc into alternate implementation
- on pentium4 without -Os when a QImode register is available.
- (*x86_cmc): New define_insn.
- (define_peephole2): Convert *x86_cmc into alternate implementation
- on pentium4 without -Os when a QImode register is available.
- (*setccc): New define_insn_and_split for a no-op CCCmode move.
- (*setcc_qi_negqi_ccc_1_<mode>): New define_insn_and_split to
- recognize (and eliminate) the carry flag being copied to itself.
- (*setcc_qi_negqi_ccc_2_<mode>): Likewise.
- * config/i386/x86-tune.def (X86_TUNE_SLOW_STC): New tuning flag.
-
-2023-06-07 Andrew Pinski <apinski@marvell.com>
-
- * match.pd: Fix comment for the
- `(zero_one ==/!= 0) ? y : z <op> y` patterns.
-
-2023-06-07 Jeff Law <jlaw@ventanamicro.com>
- Jeff Law <jlaw@ventanamicro.com>
-
- * config/riscv/bitmanip.md (rotrdi3, rotrsi3, rotlsi3): New expanders.
- (rotrsi3_sext): Expose generator.
- (rotlsi3 pattern): Hide generator.
- * config/riscv/riscv-protos.h (riscv_emit_binary): New function
- declaration.
- * config/riscv/riscv.cc (riscv_emit_binary): Removed static
- * config/riscv/riscv.md (addsi3, subsi3, negsi2): Hide generator.
- (mulsi3, <optab>si3): Likewise.
- (addsi3, subsi3, negsi2, mulsi3, <optab>si3): New expanders.
- (addv<mode>4, subv<mode>4, mulv<mode>4): Use riscv_emit_binary.
- (<u>mulsidi3): Likewise.
- (addsi3_extended, subsi3_extended, negsi2_extended): Expose generator.
- (mulsi3_extended, <optab>si3_extended): Likewise.
- (splitter for shadd feeding divison): Update RTL pattern to account
- for changes in how 32 bit ops are expanded for TARGET_64BIT.
- * loop-iv.cc (get_biv_step_1): Process src of extension when it PLUS.
-
-2023-06-07 Dimitar Dimitrov <dimitar@dinux.eu>
-
- PR target/109725
- * config/riscv/riscv.cc (riscv_print_operand): Calculate
- memmodel only when it is valid.
-
-2023-06-07 Dimitar Dimitrov <dimitar@dinux.eu>
-
- * config/riscv/riscv.cc (riscv_const_insns): Recursively call
- for constant element of a vector.
-
-2023-06-07 Jakub Jelinek <jakub@redhat.com>
-
- * match.pd (zero_one_valued_p): Don't handle integer_zerop specially,
- instead compare tree_nonzero_bits <= 1U rather than just == 1.
-
-2023-06-07 Alex Coplan <alex.coplan@arm.com>
-
- PR target/110132
- * config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin):
- New. Use it ...
- (aarch64_init_ls64_builtins): ... here. Switch to declaring public ACLE
- names for builtins.
- (aarch64_general_init_builtins): Ensure we invoke the arm_acle.h
- setup if in_lto_p, just like we do for SVE.
- * config/aarch64/arm_acle.h: (__arm_ld64b): Delete.
- (__arm_st64b): Delete.
- (__arm_st64bv): Delete.
- (__arm_st64bv0): Delete.
-
-2023-06-07 Alex Coplan <alex.coplan@arm.com>
-
- PR target/110100
- * config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64):
- Use input operand for the destination address.
- * config/aarch64/aarch64.md (st64b): Fix constraint on address
- operand.
-
-2023-06-07 Alex Coplan <alex.coplan@arm.com>
-
- PR target/110100
- * config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types):
- Replace eight consecutive spaces with tabs.
- (aarch64_init_ls64_builtins): Likewise.
- (aarch64_expand_builtin_ls64): Likewise.
- * config/aarch64/aarch64.md (ld64b): Likewise.
- (st64b): Likewise.
- (st64bv): Likewise
- (st64bv0): Likewise.
-
-2023-06-07 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * ira-costs.cc: (find_costs_and_classes): Constrain classes of pic
- offset table pseudo to a general reg subset.
-
-2023-06-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode><vczle><vczbe>):
- Rename to...
- (*aarch64_sqmovun<mode>_insn<vczle><vczbe>): ... This. Reimplement
- with RTL codes.
- (aarch64_sqmovun<mode> [SD_HSDI]): Reimplement with RTL codes.
- (aarch64_sqxtun2<mode>_le): Likewise.
- (aarch64_sqxtun2<mode>_be): Likewise.
- (aarch64_sqxtun2<mode>): Adjust for the above.
- (aarch64_sqmovun<mode>): New define_expand.
- * config/aarch64/iterators.md (UNSPEC_SQXTUN): Delete.
- (half_mask): New mode attribute.
- * config/aarch64/predicates.md (aarch64_simd_umax_half_mode):
- New predicate.
-
-2023-06-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_addp<mode><vczle><vczbe>):
- Reimplement as...
- (aarch64_addp<mode>_insn): ... This...
- (aarch64_addp<mode><vczle><vczbe>_insn): ... And this.
- (aarch64_addp<mode>): New define_expand.
-
-2023-06-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (expand_vec_perm_const): New function.
- * config/riscv/riscv-v.cc
- (rvv_builder::can_duplicate_repeating_sequence_p): Support POLY
- handling.
- (rvv_builder::single_step_npatterns_p): New function.
- (rvv_builder::npatterns_all_equal_p): Ditto.
- (const_vec_all_in_range_p): Support POLY handling.
- (gen_const_vector_dup): Ditto.
- (emit_vlmax_gather_insn): Add vrgatherei16.
- (emit_vlmax_masked_gather_mu_insn): Ditto.
- (expand_const_vector): Add VLA SLP const vector support.
- (expand_vec_perm): Support POLY.
- (struct expand_vec_perm_d): New struct.
- (shuffle_generic_patterns): New function.
- (expand_vec_perm_const_1): Ditto.
- (expand_vec_perm_const): Ditto.
- * config/riscv/riscv.cc (riscv_vectorize_vec_perm_const): Ditto.
- (TARGET_VECTORIZE_VEC_PERM_CONST): New targethook.
-
-2023-06-07 Andrew Pinski <apinski@marvell.com>
-
- PR middle-end/110117
- * expr.cc (expand_single_bit_test): Handle
- const_int from expand_expr.
-
-2023-06-07 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (do_store_flag): Rearrange the
- TER code so that it overrides the nonzero bits
- info if we had `a & POW2`.
-
-2023-06-07 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/110134
- * match.pd (-A CMP -B -> B CMP A): Allow EQ/NE for all integer
- types.
- (-A CMP CST -> B CMP (-CST)): Likewise.
-
-2023-06-07 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/89263
- PR tree-optimization/99069
- PR tree-optimization/20083
- PR tree-optimization/94898
- * match.pd: Add patterns to optimize `a ? onezero : onezero` with
- one of the operands are constant.
-
-2023-06-07 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (zero_one_valued_p): Match 0 integer constant
- too.
-
-2023-06-07 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-types.def
- (vfloat32mf2_t): Take RVV_REQUIRE_ELEN_FP_16 as requirement.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat32m8_t): Ditto.
- (vint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint16m2_t): Ditto.
- (vuint16m4_t): Ditto.
- (vuint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
-
-2023-06-07 Jason Merrill <jason@redhat.com>
-
- PR c++/58487
- * doc/invoke.texi: Document it.
-
-2023-06-06 Roger Sayle <roger@nextmovesoftware.com>
-
- * doc/rtl.texi (bitreverse, copysign): Document new RTX codes.
- * rtl.def (BITREVERSE, COPYSIGN): Define new RTX codes.
- * simplify-rtx.cc (simplify_unary_operation_1): Optimize
- NOT (BITREVERSE x) as BITREVERSE (NOT x).
- Optimize POPCOUNT (BITREVERSE x) as POPCOUNT x.
- Optimize PARITY (BITREVERSE x) as PARITY x.
- Optimize BITREVERSE (BITREVERSE x) as x.
- (simplify_const_unary_operation) <case BITREVERSE>: Evaluate
- BITREVERSE of a constant integer at compile-time.
- (simplify_binary_operation_1) <case COPYSIGN>: Optimize
- COPY_SIGN (x, x) as x. Optimize COPYSIGN (x, C) as ABS x
- or NEG (ABS x) for constant C. Optimize COPYSIGN (ABS x, y)
- and COPYSIGN (NEG x, y) as COPYSIGN (x, y).
- Optimize COPYSIGN (x, ABS y) as ABS x.
- Optimize COPYSIGN (COPYSIGN (x, y), z) as COPYSIGN (x, z).
- Optimize COPYSIGN (x, COPYSIGN (y, z)) as COPYSIGN (x, z).
- (simplify_const_binary_operation): Evaluate COPYSIGN of constant
- arguments at compile-time.
-
-2023-06-06 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (function_invariant_p): Change return type from int to bool.
- * reload1.cc (function_invariant_p): Change return type from
- int to bool and adjust function body accordingly.
-
-2023-06-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (*<optab>_fma<mode>): New pattern.
- (*single_<optab>mult_plus<mode>): Ditto.
- (*double_<optab>mult_plus<mode>): Ditto.
- (*sign_zero_extend_fma): Ditto.
- (*zero_sign_extend_fma): Ditto.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
-
-2023-06-06 Kwok Cheung Yeung <kcy@codesourcery.com>
- Tobias Burnus <tobias@codesourcery.com>
-
- * gimplify.cc (omp_notice_variable): Apply GOVD_MAP_ALLOC_ONLY flag
- and defaultmap flags if the defaultmap has GOVD_MAP_FORCE_PRESENT flag
- set.
- (omp_get_attachment): Handle map clauses with 'present' modifier.
- (omp_group_base): Likewise.
- (gimplify_scan_omp_clauses): Reorder present maps to come first.
- Set GOVD flags for present defaultmaps.
- (gimplify_adjust_omp_clauses_1): Set map kind for present defaultmaps.
- * omp-low.cc (scan_sharing_clauses): Handle 'always, present' map
- clauses.
- (lower_omp_target): Handle map clauses with 'present' modifier.
- Handle 'to' and 'from' clauses with 'present'.
- * tree-core.h (enum omp_clause_defaultmap_kind): Add
- OMP_CLAUSE_DEFAULTMAP_PRESENT defaultmap kind.
- * tree-pretty-print.cc (dump_omp_clause): Handle 'map', 'to' and
- 'from' clauses with 'present' modifier. Handle present defaultmap.
- * tree.h (OMP_CLAUSE_MOTION_PRESENT): New #define.
-
-2023-06-06 Segher Boessenkool <segher@kernel.crashing.org>
-
- * config/rs6000/genfusion.pl: Delete some dead code.
-
-2023-06-06 Segher Boessenkool <segher@kernel.crashing.org>
-
- * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): New, rewritten and
- split out from...
- (gen_ld_cmpi_p10): ... this.
-
-2023-06-06 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
-
- PR target/106907
- * config/rs6000/rs6000.cc (vec_const_128bit_to_bytes): Remove
- duplicate expression.
-
-2023-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (aarch64_general_gimple_fold_builtin):
- Handle unsigned reduc_plus_scal_ builtins.
- * config/aarch64/aarch64-simd-builtins.def (addp): Delete DImode instances.
- * config/aarch64/aarch64-simd.md (aarch64_addpdi): Delete.
- * config/aarch64/arm_neon.h (vpaddd_s64): Reimplement with
- __builtin_aarch64_reduc_plus_scal_v2di.
- (vpaddd_u64): Reimplement with __builtin_aarch64_reduc_plus_scal_v2di_uu.
-
-2023-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur>shr_n<mode>): Delete.
- (aarch64_<sra_op>rshr_n<mode><vczle><vczbe>_insn): New define_insn.
- (aarch64_<sra_op>rshr_n<mode>): New define_expand.
-
-2023-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_shrn<mode>_insn_le): Delete.
- (aarch64_shrn<mode>_insn_be): Delete.
- (*aarch64_<srn_op>shrn<mode>_vect): Rename to...
- (*aarch64_<srn_op>shrn<mode><vczle><vczbe>): ... This.
- (aarch64_shrn<mode>): Remove reference to the above deleted patterns.
- (aarch64_rshrn<mode>_insn_le): Delete.
- (aarch64_rshrn<mode>_insn_be): Delete.
- (aarch64_rshrn<mode><vczle><vczbe>_insn): New define_insn.
- (aarch64_rshrn<mode>): Remove references to the above deleted patterns.
-
-2023-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_parallel_select_half_p):
- Define prototype.
- (aarch64_pars_overlap_p): Likewise.
- * config/aarch64/aarch64-simd.md (aarch64_<su>addlv<mode>):
- Express in terms of UNSPEC_ADDV.
- (*aarch64_<su>addlv<VDQV_L:mode>_ze<GPI:mode>): Likewise.
- (*aarch64_<su>addlv<mode>_reduction): Define.
- (*aarch64_uaddlv<mode>_reduction_2): Likewise.
- * config/aarch64/aarch64.cc (aarch64_parallel_select_half_p): Define.
- (aarch64_pars_overlap_p): Likewise.
- * config/aarch64/iterators.md (UNSPEC_SADDLV, UNSPEC_UADDLV): Delete.
- (VQUADW): New mode attribute.
- (VWIDE2X_S): Likewise.
- (USADDLV): Delete.
- (su): Delete handling of UNSPEC_SADDLV, UNSPEC_UADDLV.
- * config/aarch64/predicates.md (vect_par_cnst_select_half): Define.
-
-2023-06-06 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110055
- * gimplify.cc (gimplify_target_expr): Do not emit
- CLOBBERs for variables which have static storage duration
- after gimplifying their initializers.
-
-2023-06-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109143
- * tree-ssa-structalias.cc (solution_set_expand): Avoid
- one bitmap iteration and optimize bit range setting.
-
-2023-06-06 Hans-Peter Nilsson <hp@axis.com>
-
- PR bootstrap/110120
- * postreload.cc (reload_cse_move2add, move2add_use_add2_insn): Use
- XVECEXP, not XEXP, to access first item of a PARALLEL.
-
-2023-06-06 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-types.def
- (vfloat16mf4_t): Add vfloat16mf4_t to WF operations.
- (vfloat16mf2_t): Likewise.
- (vfloat16m1_t): Likewise.
- (vfloat16m2_t): Likewise.
- (vfloat16m4_t): Likewise.
- (vfloat16m8_t): Likewise.
- * config/riscv/vector-iterators.md: Add FP=16 to VWF, VWF_ZVE64,
- VWLMUL1, VWLMUL1_ZVE64, vwlmul1 and vwlmul1_zve64.
-
-2023-06-06 Fei Gao <gaofei@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Use Pmode
- for cfi reg/mem machmode
- (riscv_adjust_libcall_cfi_epilogue): Use Pmode for cfi reg machmode
-
-2023-06-06 Li Xu <xuli1@eswincomputing.com>
-
- * config/riscv/vector-iterators.md:
- Fix 'REQUIREMENT' for machine_mode 'MODE'.
- * config/riscv/vector.md (@pred_indexed_<order>store<VNX16_QHS:mode>
- <VNX16_QHSI:mode>): change VNX16_QHSI to VNX16_QHSDI.
- (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>): Ditto.
-
-2023-06-06 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector-iterators.md: Fix typo in mode attr.
-
-2023-06-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
- Joel Hutton <joel.hutton@arm.com>
-
- * doc/generic.texi: Remove old tree codes.
- * expr.cc (expand_expr_real_2): Remove old tree code cases.
- * gimple-pretty-print.cc (dump_binary_rhs): Likewise.
- * optabs-tree.cc (optab_for_tree_code): Likewise.
- (supportable_half_widening_operation): Likewise.
- * tree-cfg.cc (verify_gimple_assign_binary): Likewise.
- * tree-inline.cc (estimate_operator_cost): Likewise.
- (op_symbol_code): Likewise.
- * tree-vect-data-refs.cc (vect_get_smallest_scalar_type): Likewise.
- (vect_analyze_data_ref_accesses): Likewise.
- * tree-vect-generic.cc (expand_vector_operations_1): Likewise.
- * cfgexpand.cc (expand_debug_expr): Likewise.
- * tree-vect-stmts.cc (vectorizable_conversion): Likewise.
- (supportable_widening_operation): Likewise.
- * gimple-range-op.cc (gimple_range_op_handler::maybe_non_standard):
- Likewise.
- * optabs.def (vec_widen_ssubl_hi_optab, vec_widen_ssubl_lo_optab,
- vec_widen_saddl_hi_optab, vec_widen_saddl_lo_optab,
- vec_widen_usubl_hi_optab, vec_widen_usubl_lo_optab,
- vec_widen_uaddl_hi_optab, vec_widen_uaddl_lo_optab): Remove optabs.
- * tree-pretty-print.cc (dump_generic_node): Remove tree code definition.
- * tree.def (WIDEN_PLUS_EXPR, WIDEN_MINUS_EXPR, VEC_WIDEN_PLUS_HI_EXPR,
- VEC_WIDEN_PLUS_LO_EXPR, VEC_WIDEN_MINUS_HI_EXPR,
- VEC_WIDEN_MINUS_LO_EXPR): Likewise.
-
-2023-06-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
- Joel Hutton <joel.hutton@arm.com>
- Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-simd.md (vec_widen_<su>addl_lo_<mode>): Rename
- this ...
- (vec_widen_<su>add_lo_<mode>): ... to this.
- (vec_widen_<su>addl_hi_<mode>): Rename this ...
- (vec_widen_<su>add_hi_<mode>): ... to this.
- (vec_widen_<su>subl_lo_<mode>): Rename this ...
- (vec_widen_<su>sub_lo_<mode>): ... to this.
- (vec_widen_<su>subl_hi_<mode>): Rename this ...
- (vec_widen_<su>sub_hi_<mode>): ...to this.
- * doc/generic.texi: Document new IFN codes.
- * internal-fn.cc (lookup_hilo_internal_fn): Add lookup function.
- (commutative_binary_fn_p): Add widen_plus fn's.
- (widening_fn_p): New function.
- (narrowing_fn_p): New function.
- (direct_internal_fn_optab): Change visibility.
- * internal-fn.def (DEF_INTERNAL_WIDENING_OPTAB_FN): Macro to define an
- internal_fn that expands into multiple internal_fns for widening.
- (IFN_VEC_WIDEN_PLUS, IFN_VEC_WIDEN_PLUS_HI, IFN_VEC_WIDEN_PLUS_LO,
- IFN_VEC_WIDEN_PLUS_EVEN, IFN_VEC_WIDEN_PLUS_ODD,
- IFN_VEC_WIDEN_MINUS, IFN_VEC_WIDEN_MINUS_HI,
- IFN_VEC_WIDEN_MINUS_LO, IFN_VEC_WIDEN_MINUS_ODD,
- IFN_VEC_WIDEN_MINUS_EVEN): Define widening plus,minus functions.
- * internal-fn.h (direct_internal_fn_optab): Declare new prototype.
- (lookup_hilo_internal_fn): Likewise.
- (widening_fn_p): Likewise.
- (Narrowing_fn_p): Likewise.
- * optabs.cc (commutative_optab_p): Add widening plus optabs.
- * optabs.def (OPTAB_D): Define widen add, sub optabs.
- * tree-vect-patterns.cc (vect_recog_widen_op_pattern): Support
- patterns with a hi/lo or even/odd split.
- (vect_recog_sad_pattern): Refactor to use new IFN codes.
- (vect_recog_widen_plus_pattern): Likewise.
- (vect_recog_widen_minus_pattern): Likewise.
- (vect_recog_average_pattern): Likewise.
- * tree-vect-stmts.cc (vectorizable_conversion): Add support for
- _HILO IFNs.
- (supportable_widening_operation): Likewise.
- * tree.def (WIDEN_SUM_EXPR): Update example to use new IFNs.
-
-2023-06-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
- Joel Hutton <joel.hutton@arm.com>
-
- * tree-vect-patterns.cc: Add include for gimple-iterator.
- (vect_recog_widen_op_pattern): Refactor to use code_helper.
- (vect_gimple_build): New function.
- * tree-vect-stmts.cc (simple_integer_narrowing): Refactor to use
- code_helper.
- (vectorizable_call): Likewise.
- (vect_gen_widened_results_half): Likewise.
- (vect_create_vectorized_demotion_stmts): Likewise.
- (vect_create_vectorized_promotion_stmts): Likewise.
- (vect_create_half_widening_stmts): Likewise.
- (vectorizable_conversion): Likewise.
- (supportable_widening_operation): Likewise.
- (supportable_narrowing_operation): Likewise.
- * tree-vectorizer.h (supportable_widening_operation): Change
- prototype to use code_helper.
- (supportable_narrowing_operation): Likewise.
- (vect_gimple_build): New function prototype.
- * tree.h (code_helper::safe_as_tree_code): New function.
- (code_helper::safe_as_fn_code): New function.
-
-2023-06-05 Roger Sayle <roger@nextmovesoftware.com>
-
- * wide-int.cc (wi::bitreverse_large): New function implementing
- bit reversal of an integer.
- * wide-int.h (wi::bitreverse): New (template) function prototype.
- (bitreverse_large): Prototype helper function/implementation.
- (wi::bitreverse): New template wrapper around bitreverse_large.
-
-2023-06-05 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (print_rtl_single): Change return type from int to void.
- (print_rtl_single_with_indent): Ditto.
- * print-rtl.h (class rtx_writer): Ditto. Change m_sawclose to bool.
- * print-rtl.cc (rtx_writer::rtx_writer): Update for m_sawclose change.
- (rtx_writer::print_rtx_operand_code_0): Ditto.
- (rtx_writer::print_rtx_operand_codes_E_and_V): Ditto.
- (rtx_writer::print_rtx_operand_code_i): Ditto.
- (rtx_writer::print_rtx_operand_code_u): Ditto.
- (rtx_writer::print_rtx_operand): Ditto.
- (rtx_writer::print_rtx): Ditto.
- (rtx_writer::finish_directive): Ditto.
- (print_rtl_single): Change return type from int to void
- and adjust function body accordingly.
- (rtx_writer::print_rtl_single_with_indent): Ditto.
-
-2023-06-05 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (reg_classes_intersect_p): Change return type from int to bool.
- (reg_class_subset_p): Ditto.
- * reginfo.cc (reg_classes_intersect_p): Ditto.
- (reg_class_subset_p): Ditto.
-
-2023-06-05 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-types.def
- (vfloat32mf2_t): New type for DEF_RVV_WEXTF_OPS.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat32m8_t): Ditto.
- (vint16mf4_t): New type for DEF_RVV_CONVERT_I_OPS.
- (vint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vuint16mf4_t): New type for DEF_RVV_CONVERT_U_OPS.
- (vuint16mf2_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint16m2_t): Ditto.
- (vuint16m4_t): Ditto.
- (vuint16m8_t): Ditto.
- (vint32mf2_t): New type for DEF_RVV_WCONVERT_I_OPS.
- (vint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vuint32mf2_t): New type for DEF_RVV_WCONVERT_U_OPS.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
- * config/riscv/vector-iterators.md: Add FP=16 support for V,
- VWCONVERTI, VCONVERT, VNCONVERT, VMUL1 and vlmul1.
-
-2023-06-05 Andrew Pinski <apinski@marvell.com>
-
- PR bootstrap/110085
- * Makefile.in (clean): Remove the removing of
- MULTILIB_DIR/MULTILIB_OPTIONS directories.
-
-2023-06-05 YunQiang Su <yunqiang.su@cipunited.com>
-
- * config/mips/mips-protos.h (mips_emit_speculation_barrier): New
- prototype.
- * config/mips/mips.cc (speculation_barrier_libfunc): New static
- variable.
- (mips_init_libfuncs): Initialize it.
- (mips_emit_speculation_barrier): New function.
- * config/mips/mips.md (speculation_barrier): Call
- mips_emit_speculation_barrier.
-
-2023-06-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (class rvv_builder): Reorganize functions.
- (rvv_builder::can_duplicate_repeating_sequence_p): Ditto.
- (rvv_builder::repeating_sequence_use_merge_profitable_p): Ditto.
- (rvv_builder::get_merged_repeating_sequence): Ditto.
- (rvv_builder::get_merge_scalar_mask): Ditto.
- (emit_scalar_move_insn): Ditto.
- (emit_vlmax_integer_move_insn): Ditto.
- (emit_nonvlmax_integer_move_insn): Ditto.
- (emit_vlmax_gather_insn): Ditto.
- (emit_vlmax_masked_gather_mu_insn): Ditto.
- (get_repeating_sequence_dup_machine_mode): Ditto.
-
-2023-06-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Split arguments.
- * config/riscv/riscv-protos.h (expand_vec_perm): Ditto.
- * config/riscv/riscv-v.cc (expand_vec_perm): Ditto.
-
-2023-06-04 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (do_store_flag): Improve for single bit testing
- not against zero but against that single bit.
-
-2023-06-04 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (do_store_flag): Extend the one bit checking case
- to handle the case where we don't have an and but rather still
- one bit is known to be non-zero.
-
-2023-06-04 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/constraints.md (Zz): Make this a normal
- constraint.
- * config/h8300/h8300.cc (TARGET_LRA_P): Remove.
- * config/h8300/logical.md (H8/SX bit patterns): Remove.
-
-2023-06-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.md (*btrue_INT_MIN, *eqne_INT_MIN):
- New insn_and_split patterns.
-
-2023-06-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/110109
- * config/riscv/riscv-vector-builtins-bases.cc: Change expand approach.
- * config/riscv/vector.md (@vlmul_extx2<mode>): Remove it.
- (@vlmul_extx4<mode>): Ditto.
- (@vlmul_extx8<mode>): Ditto.
- (@vlmul_extx16<mode>): Ditto.
- (@vlmul_extx32<mode>): Ditto.
- (@vlmul_extx64<mode>): Ditto.
- (*vlmul_extx2<mode>): Ditto.
- (*vlmul_extx4<mode>): Ditto.
- (*vlmul_extx8<mode>): Ditto.
- (*vlmul_extx16<mode>): Ditto.
- (*vlmul_extx32<mode>): Ditto.
- (*vlmul_extx64<mode>): Ditto.
-
-2023-06-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-types.def
- (vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
- (vfloat32m1_t): Likewise.
- (vfloat32m2_t): Likewise.
- (vfloat32m4_t): Likewise.
- (vfloat32m8_t): Likewise.
- * config/riscv/riscv-vector-builtins.def: Fix typo in comments.
- * config/riscv/vector-iterators.md: Add single to half machine
- mode conversion.
-
-2023-06-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (*<optab>not<mode>): Move to autovec-opt.md.
- (*n<optab><mode>): Ditto.
- * config/riscv/autovec.md (*<optab>not<mode>): Ditto.
- (*n<optab><mode>): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-06-04 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110083
- * config/i386/i386-features.cc (scalar_chain::convert_compare):
- Update or delete REG_EQUAL notes, converting CONST_INT and
- CONST_WIDE_INT immediate operands to a suitable CONST_VECTOR.
-
-2023-06-04 Jason Merrill <jason@redhat.com>
-
- PR c++/97720
- * tree-eh.cc (lower_resx): Pass the exception pointer to the
- failure_decl.
- * except.h: Tweak comment.
-
-2023-06-04 Hans-Peter Nilsson <hp@axis.com>
-
- * postreload.cc (move2add_use_add2_insn): Handle
- trivial single_sets. Rename variable PAT to SET.
- (move2add_use_add3_insn, reload_cse_move2add): Similar.
-
-2023-06-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins-types.def
- (vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
- (vfloat16mf2_t): Likewise.
- (vfloat16m1_t): Likewise.
- (vfloat16m2_t): Likewise.
- (vfloat16m4_t): Likewise.
- (vfloat16m8_t): Likewise.
- * config/riscv/riscv.md: Add vfloat16*_t to attr mode.
- * config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
- to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
- * config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
- vlmul and ratio.
-
-2023-06-03 Fei Gao <gaofei@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_expand_epilogue): fix cfi issue with
- correct offset.
-
-2023-06-03 Die Li <lidie@eswincomputing.com>
-
- * config/riscv/thead.md (*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Delete.
-
-2023-06-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/predicates.md: Change INTVAL into UINTVAL.
-
-2023-06-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Add vector-opt.md.
- * config/riscv/autovec-opt.md: New file.
-
-2023-06-03 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/110067
- * gimple-ssa-store-merging.cc (find_bswap_or_nop): Don't try
- bswap + rotate when TYPE_PRECISION(n->type) > n->range.
-
-2023-06-03 liuhongt <hongtao.liu@intel.com>
-
- PR target/92658
- * config/i386/mmx.md (truncv2hiv2qi2): New define_insn.
- (truncv2si<mode>2): Ditto.
-
-2023-06-02 Andrew Pinski <apinski@marvell.com>
-
- PR rtl-optimization/102733
- * dse.cc (store_info): Add addrspace field.
- (record_store): Record the address space
- and check to make sure they are the same.
-
-2023-06-02 Andrew Pinski <apinski@marvell.com>
-
- PR rtl-optimization/110042
- * ifcvt.cc (bbs_ok_for_cmove_arith): Allow paradoxical subregs.
- (bb_valid_for_noce_process_p): Strip the subreg for the SET_DEST.
-
-2023-06-02 Iain Sandoe <iain@sandoe.co.uk>
-
- PR target/110044
- * config/rs6000/rs6000.cc (darwin_rs6000_special_round_type_align):
- Make sure that we do not have a cap on field alignment before altering
- the struct layout based on the type alignment of the first entry.
-
-2023-06-02 David Faust <david.faust@oracle.com>
-
- PR debug/110073
- * btfout.cc (btf_absolute_func_id): New function.
- (btf_asm_func_type): Call it here. Change index parameter from
- size_t to ctf_id_t. Use PRIu64 formatter.
-
-2023-06-02 Alex Coplan <alex.coplan@arm.com>
-
- * btfout.cc (btf_asm_type): Use PRIu64 instead of %lu for uint64_t.
- (btf_asm_datasec_type): Likewise.
-
-2023-06-02 Carl Love <cel@us.ibm.com>
-
- * config/rs6000/rs6000-builtins.def (__builtin_altivec_tr_stxvrhx,
- __builtin_altivec_tr_stxvrwx): Fix type of third argument.
-
-2023-06-02 Jason Merrill <jason@redhat.com>
-
- PR c++/110070
- PR c++/105838
- * tree.h (DECL_MERGEABLE): New.
- * tree-core.h (struct tree_decl_common): Mention it.
- * gimplify.cc (gimplify_init_constructor): Check it.
- * cgraph.cc (symtab_node::address_can_be_compared_p): Likewise.
- * varasm.cc (categorize_decl_for_section): Likewise.
-
-2023-06-02 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (stack_regs_mentioned): Change return type from int to bool.
- * reg-stack.cc (struct_block_info_def): Change "done" to bool.
- (stack_regs_mentioned_p): Change return type from int to bool
- and adjust function body accordingly.
- (stack_regs_mentioned): Ditto.
- (check_asm_stack_operands): Ditto. Change "malformed_asm"
- variable to bool.
- (move_for_stack_reg): Recode handling of control_flow_insn_deleted.
- (swap_rtx_condition_1): Change return type from int to bool
- and adjust function body accordingly. Change "r" variable to bool.
- (swap_rtx_condition): Change return type from int to bool
- and adjust function body accordingly.
- (subst_stack_regs_pat): Recode handling of control_flow_insn_deleted.
- (subst_stack_regs): Ditto.
- (convert_regs_entry): Change return type from int to bool and adjust
- function body accordingly. Change "inserted" variable to bool.
- (convert_regs_1): Recode handling of control_flow_insn_deleted.
- (convert_regs_2): Recode handling of cfg_altered.
- (convert_regs): Ditto. Change "inserted" variable to bool.
-
-2023-06-02 Jason Merrill <jason@redhat.com>
-
- PR c++/95226
- * varasm.cc (output_constant) [REAL_TYPE]: Check that sizes match.
- (initializer_constant_valid_p_1): Compare float precision.
-
-2023-06-02 Alexander Monakov <amonakov@ispras.ru>
-
- * doc/extend.texi (Vector Extensions): Clarify bitwise shift
- semantics.
-
-2023-06-02 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-loop-manip.cc (vect_set_loop_controls_directly): Change decrement IV flow.
- (vect_set_loop_condition_partial_vectors): Ditto.
-
-2023-06-02 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/110088
- * config/avr/avr.md: Add an RTL peephole to optimize operations on
- non-LD_REGS after a move from LD_REGS.
- (piaop): New code iterator.
-
-2023-06-02 Thomas Schwinge <thomas@codesourcery.com>
-
- PR testsuite/66005
- * doc/install.texi: Document (optional) Perl usage for parallel
- testing of libgomp.
-
-2023-06-02 Thomas Schwinge <thomas@codesourcery.com>
-
- PR bootstrap/82856
- * doc/install.texi (Perl): Back to requiring "Perl version 5.6.1 (or
- later)".
-
-2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- KuanLin Chen <best124612@gmail.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Add _mu overloaded intrinsics.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct fault_load_def): Ditto.
-
-2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_vec_series): Optimize reverse series index vector.
-
-2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/predicates.md: Change INTVAL into UINTVAL.
-
-2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_VXRM_ENUM): Add
- __RISCV_ prefix.
- (DEF_RVV_FRM_ENUM): Ditto.
-
-2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Change vwadd.wv/vwsub.wv
- intrinsic API expander
- * config/riscv/vector.md
- (@pred_single_widen_<plus_minus:optab><any_extend:su><mode>): Remove it.
- (@pred_single_widen_sub<any_extend:su><mode>): New pattern.
- (@pred_single_widen_add<any_extend:su><mode>): New pattern.
-
-2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (vec_perm<mode>): New pattern.
- * config/riscv/predicates.md (vector_perm_operand): New predicate.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- (expand_vec_perm): New function.
- * config/riscv/riscv-v.cc (const_vec_all_in_range_p): Ditto.
- (gen_const_vector_dup): Ditto.
- (emit_vlmax_gather_insn): Ditto.
- (emit_vlmax_masked_gather_mu_insn): Ditto.
- (expand_vec_perm): Ditto.
-
-2023-06-01 Jason Merrill <jason@redhat.com>
-
- * doc/invoke.texi (-Wpedantic): Improve clarity.
-
-2023-06-01 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (exp_equiv_p): Change return type from int to bool.
- * cse.cc (mention_regs): Change return type from int to bool
- and adjust function body accordingly.
- (exp_equiv_p): Ditto.
- (insert_regs): Ditto. Change "modified" function argument to bool
- and update usage accordingly.
- (record_jump_cond): Remove always zero "reversed_nonequality"
- function argument and update usage accordingly.
- (fold_rtx): Change "changed" variable to bool.
- (record_jump_equiv): Remove unneeded "reversed_nonequality" variable.
- (is_dead_reg): Change return type from int to bool.
-
-2023-06-01 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.md (adddi3, subdi3):
- New RTL generation patterns implemented according to the instruc-
- tion idioms described in the Xtensa ISA reference manual (p. 600).
-
-2023-06-01 Roger Sayle <roger@nextmovesoftware.com>
- Uros Bizjak <ubizjak@gmail.com>
-
- PR target/109973
- * config/i386/i386-builtin.def (__builtin_ia32_ptestz128): Use new
- CODE_for_sse4_1_ptestzv2di.
- (__builtin_ia32_ptestc128): Use new CODE_for_sse4_1_ptestcv2di.
- (__builtin_ia32_ptestz256): Use new CODE_for_avx_ptestzv4di.
- (__builtin_ia32_ptestc256): Use new CODE_for_avx_ptestcv4di.
- * config/i386/i386-expand.cc (ix86_expand_branch): Use CCZmode
- when expanding UNSPEC_PTEST to compare against zero.
- * config/i386/i386-features.cc (scalar_chain::convert_compare):
- Likewise generate CCZmode UNSPEC_PTESTs when converting comparisons.
- (general_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
- (timode_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
- * config/i386/i386-protos.h (ix86_match_ptest_ccmode): Prototype.
- * config/i386/i386.cc (ix86_match_ptest_ccmode): New predicate to
- check for suitable matching modes for the UNSPEC_PTEST pattern.
- * config/i386/sse.md (define_split): When splitting UNSPEC_MOVMSK
- to UNSPEC_PTEST, preserve the FLAG_REG mode as CCZ.
- (*<sse4_1>_ptest<mode>): Add asterisk to hide define_insn. Remove
- ":CC" mode of FLAGS_REG, instead use ix86_match_ptest_ccmode.
- (<sse4_1>_ptestz<mode>): New define_expand to specify CCZ.
- (<sse4_1>_ptestc<mode>): New define_expand to specify CCC.
- (<sse4_1>_ptest<mode>): A define_expand using CC to preserve the
- current behavior.
- (*ptest<mode>_and): Specify CCZ to only perform this optimization
- when only the Z flag is required.
-
-2023-06-01 Jonathan Wakely <jwakely@redhat.com>
-
- PR target/109954
- * doc/invoke.texi (x86 Options): Fix description of -m32 option.
-
-2023-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
- Add =r,m and =r,m alternatives.
- (load_pair<DREG:mode><DREG2:mode>): Likewise.
- (vec_store_pair<DREG:mode><DREG2:mode>): Likewise.
-
-2023-06-01 Pan Li <pan2.li@intel.com>
-
- * common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin
- and zvfh.
- * config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16.
- (main): Disable FP16 tuple.
- * config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro.
- (TARGET_VECTOR_ELEN_FP_16): Ditto.
- * config/riscv/riscv-vector-builtins.cc (check_required_extensions):
- Add FP16.
- * config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type.
- (vfloat16mf2_t): Ditto.
- (vfloat16m1_t): Ditto.
- (vfloat16m2_t): Ditto.
- (vfloat16m4_t): Ditto.
- (vfloat16m8_t): Ditto.
- * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16):
- New macro.
- * config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16
- machine mode based on TARGET_VECTOR_ELEN_FP_16.
-
-2023-06-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins.cc (register_frm): New function.
- (DEF_RVV_FRM_ENUM): New macro.
- (handle_pragma_vector): Add FRM enum
- * config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro.
- (RNE): Ditto.
- (RTZ): Ditto.
- (RDN): Ditto.
- (RUP): Ditto.
- (RMM): Ditto.
-
-2023-05-31 Roger Sayle <roger@nextmovesoftware.com>
- Richard Sandiford <richard.sandiford@arm.com>
-
- * fold-const-call.cc (fold_const_call_ss) <CFN_BUILT_IN_BSWAP*>:
- Update call to wi::bswap.
- * simplify-rtx.cc (simplify_const_unary_operation) <case BSWAP>:
- Update call to wi::bswap.
- * tree-ssa-ccp.cc (evaluate_stmt) <case BUILT_IN_BSWAP*>:
- Update calls to wi::bswap.
- * wide-int.cc (wide_int_storage::bswap): Remove/rename to...
- (wi::bswap_large): New function, with revised API.
- * wide-int.h (wi::bswap): New (template) function prototype.
- (wide_int_storage::bswap): Remove method.
- (sext_large, zext_large): Consistent indentation/line wrapping.
- (bswap_large): Prototype helper function containing implementation.
- (wi::bswap): New template wrapper around bswap_large.
-
-2023-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (<sur>dot_prod<vsi2qi>): Rename to...
- (<sur>dot_prod<vsi2qi><vczle><vczbe>): ... This.
- (usdot_prod<vsi2qi>): Rename to...
- (usdot_prod<vsi2qi><vczle><vczbe>): ... This.
- (aarch64_<sur>dot_lane<vsi2qi>): Rename to...
- (aarch64_<sur>dot_lane<vsi2qi><vczle><vczbe>): ... This.
- (aarch64_<sur>dot_laneq<vsi2qi>): Rename to...
- (aarch64_<sur>dot_laneq<vsi2qi><vczle><vczbe>): ... This.
- (aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi>): Rename to...
- (aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi><vczle><vczbe>):
- ... This.
-
-2023-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh<mode>): Rename to...
- (aarch64_sq<r>dmulh<mode><vczle><vczbe>): ... This.
- (aarch64_sq<r>dmulh_n<mode>): Rename to...
- (aarch64_sq<r>dmulh_n<mode><vczle><vczbe>): ... This.
- (aarch64_sq<r>dmulh_lane<mode>): Rename to...
- (aarch64_sq<r>dmulh_lane<mode><vczle><vczbe>): ... This.
- (aarch64_sq<r>dmulh_laneq<mode>): Rename to...
- (aarch64_sq<r>dmulh_laneq<mode><vczle><vczbe>): ... This.
- (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>): Rename to...
- (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode><vczle><vczbe>): ... This.
- (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Rename to...
- (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>): ... This.
- (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Rename to...
- (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>): ... This.
-
-2023-05-31 David Faust <david.faust@oracle.com>
-
- * btfout.cc (btf_kind_names): New.
- (btf_kind_name): New.
- (btf_absolute_var_id): New utility function.
- (btf_relative_var_id): Likewise.
- (btf_relative_func_id): Likewise.
- (btf_absolute_datasec_id): Likewise.
- (btf_asm_type_ref): New.
- (btf_asm_type): Update asm comments and use btf_asm_type_ref ().
- (btf_asm_array): Likewise. Accept ctf_container_ref parameter.
- (btf_asm_varent): Likewise.
- (btf_asm_func_arg): Likewise.
- (btf_asm_datasec_entry): Likewise.
- (btf_asm_datasec_type): Likewise.
- (btf_asm_func_type): Likewise. Add index parameter.
- (btf_asm_enum_const): Likewise.
- (btf_asm_sou_member): Likewise.
- (output_btf_vars): Update btf_asm_* call accordingly.
- (output_asm_btf_sou_fields): Likewise.
- (output_asm_btf_enum_list): Likewise.
- (output_asm_btf_func_args_list): Likewise.
- (output_asm_btf_vlen_bytes): Likewise.
- (output_btf_func_types): Add ctf_container_ref parameter.
- Pass it to btf_asm_func_type.
- (output_btf_datasec_types): Update btf_asm_datsec_type call similarly.
- (btf_output): Update output_btf_func_types call similarly.
-
-2023-05-31 David Faust <david.faust@oracle.com>
-
- * btfout.cc (btf_asm_type): Add dedicated cases for BTF_KIND_ARRAY
- and BTF_KIND_FWD which do not use the size/type field at all.
-
-2023-05-31 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (subreg_lowpart_p): Change return type from int to bool.
- (active_insn_p): Ditto.
- (in_sequence_p): Ditto.
- (unshare_all_rtl): Change return type from int to void.
- * emit-rtl.h (mem_expr_equal_p): Change return type from int to bool.
- * emit-rtl.cc (subreg_lowpart_p): Change return type from int to bool
- and adjust function body accordingly.
- (mem_expr_equal_p): Ditto.
- (unshare_all_rtl): Change return type from int to void
- and adjust function body accordingly.
- (verify_rtx_sharing): Remove unneeded return.
- (active_insn_p): Change return type from int to bool
- and adjust function body accordingly.
- (in_sequence_p): Ditto.
-
-2023-05-31 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (true_dependence): Change return type from int to bool.
- (canon_true_dependence): Ditto.
- (read_dependence): Ditto.
- (anti_dependence): Ditto.
- (canon_anti_dependence): Ditto.
- (output_dependence): Ditto.
- (canon_output_dependence): Ditto.
- (may_alias_p): Ditto.
- * alias.h (alias_sets_conflict_p): Ditto.
- (alias_sets_must_conflict_p): Ditto.
- (objects_must_conflict_p): Ditto.
- (nonoverlapping_memrefs_p): Ditto.
- * alias.cc (rtx_equal_for_memref_p): Remove forward declaration.
- (record_set): Ditto.
- (base_alias_check): Ditto.
- (find_base_value): Ditto.
- (mems_in_disjoint_alias_sets_p): Ditto.
- (get_alias_set_entry): Ditto.
- (decl_for_component_ref): Ditto.
- (write_dependence_p): Ditto.
- (memory_modified_1): Ditto.
- (mems_in_disjoint_alias_set_p): Change return type from int to bool
- and adjust function body accordingly.
- (alias_sets_conflict_p): Ditto.
- (alias_sets_must_conflict_p): Ditto.
- (objects_must_conflict_p): Ditto.
- (rtx_equal_for_memref_p): Ditto.
- (base_alias_check): Ditto.
- (read_dependence): Ditto.
- (nonoverlapping_memrefs_p): Ditto.
- (true_dependence_1): Ditto.
- (true_dependence): Ditto.
- (canon_true_dependence): Ditto.
- (write_dependence_p): Ditto.
- (anti_dependence): Ditto.
- (canon_anti_dependence): Ditto.
- (output_dependence): Ditto.
- (canon_output_dependence): Ditto.
- (may_alias_p): Ditto.
- (init_alias_analysis): Change "changed" variable to bool.
-
-2023-05-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (<optab><v_double_trunc><mode>2): Change
- expand into define_insn_and_split.
-
-2023-05-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Remove FRM.
-
-2023-05-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Remove FRM.
-
-2023-05-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Remove FRM.
-
-2023-05-31 Christophe Lyon <christophe.lyon@linaro.org>
-
- PR target/110039
- * config/aarch64/aarch64.md (aarch64_rev16si2_alt3): New
- pattern.
-
-2023-05-31 Richard Biener <rguenther@suse.de>
-
- PR ipa/109983
- PR tree-optimization/109143
- * tree-ssa-structalias.cc (struct topo_info): Remove.
- (init_topo_info): Likewise.
- (free_topo_info): Likewise.
- (compute_topo_order): Simplify API, put the component
- with ESCAPED last so it's processed first.
- (topo_visit): Adjust.
- (solve_graph): Likewise.
-
-2023-05-31 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-structalias.cc (constraint_stats::num_avoided_edges):
- New.
- (add_graph_edge): Count redundant edges we avoid to create.
- (dump_sa_stats): Dump them.
- (ipa_pta_execute): Do not dump generating constraints when
- we are not dumping them.
-
-2023-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>): Rewrite
- output template to avoid explicit switch on which_alternative.
- (*aarch64_simd_mov<VQMOV:mode>): Likewise.
- (and<mode>3): Likewise.
- (ior<mode>3): Likewise.
- * config/aarch64/aarch64.md (*mov<mode>_aarch64): Likewise.
-
-2023-05-31 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/predicates.md (xtensa_bit_join_operator):
- New predicate.
- * config/xtensa/xtensa.md (ior_op): Remove.
- (*shlrd_reg): Rename from "*shlrd_reg_<code>", and add the
- insn_and_split pattern of the same name to express and capture
- the bit-combining operation with both sides swapped.
- In addition, replace use of code iterator with new operator
- predicate.
- (*shlrd_const, *shlrd_per_byte):
- Likewise regarding the code iterator.
-
-2023-05-31 Cui, Lili <lili.cui@intel.com>
-
- PR tree-optimization/110038
- * params.opt: Add a limit on tree-reassoc-width.
- * tree-ssa-reassoc.cc
- (rewrite_expr_tree_parallel): Add width limit.
-
-2023-05-31 Pan Li <pan2.li@intel.com>
-
- * common/config/riscv/riscv-common.cc:
- (riscv_implied_info): Add zvfh item.
- (riscv_ext_version_table): Ditto.
- (riscv_ext_flag_table): Ditto.
- * config/riscv/riscv-opts.h (MASK_ZVFH): New macro.
- (TARGET_ZVFH): Ditto.
-
-2023-05-30 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/108804
- * tree-vect-patterns.cc (vect_get_range_info): Remove static.
- * tree-vect-stmts.cc (vect_create_vectorized_demotion_stmts):
- Add new parameter narrow_src_p.
- (vectorizable_conversion): Enhance NARROW FLOAT_EXPR
- vectorization by truncating to lower precision.
- * tree-vectorizer.h (vect_get_range_info): New declare.
-
-2023-05-30 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-int.h (lra_update_sp_offset): Add the prototype.
- * lra.cc (setup_sp_offset): Change the return type. Use
- lra_update_sp_offset.
- * lra-eliminations.cc (lra_update_sp_offset): New function.
- (lra_process_new_insns): Push the current insn to reprocess if the
- input reload changes sp offset.
-
-2023-05-30 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/110041
- * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
- Fix misleading identation.
-
-2023-05-30 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (comparison_dominates_p): Change return type from int to bool.
- (condjump_p): Ditto.
- (any_condjump_p): Ditto.
- (any_uncondjump_p): Ditto.
- (simplejump_p): Ditto.
- (returnjump_p): Ditto.
- (eh_returnjump_p): Ditto.
- (onlyjump_p): Ditto.
- (invert_jump_1): Ditto.
- (invert_jump): Ditto.
- (rtx_renumbered_equal_p): Ditto.
- (redirect_jump_1): Ditto.
- (redirect_jump): Ditto.
- (condjump_in_parallel_p): Ditto.
- * jump.cc (invert_exp_1): Adjust forward declaration.
- (comparison_dominates_p): Change return type from int to bool
- and adjust function body accordingly.
- (simplejump_p): Ditto.
- (condjump_p): Ditto.
- (condjump_in_parallel_p): Ditto.
- (any_uncondjump_p): Ditto.
- (any_condjump_p): Ditto.
- (returnjump_p): Ditto.
- (eh_returnjump_p): Ditto.
- (onlyjump_p): Ditto.
- (redirect_jump_1): Ditto.
- (redirect_jump): Ditto.
- (invert_exp_1): Ditto.
- (invert_jump_1): Ditto.
- (invert_jump): Ditto.
- (rtx_renumbered_equal_p): Ditto.
-
-2023-05-30 Andrew Pinski <apinski@marvell.com>
-
- * fold-const.cc (minmax_from_comparison): Add support for NE_EXPR.
- * match.pd ((cond (cmp (convert1? x) c1) (convert2? x) c2) pattern):
- Add ne as a possible cmp.
- ((a CMP b) ? minmax<a, c> : minmax<b, c> pattern): Likewise.
-
-2023-05-30 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`(a CMP CST1) ? max<a,CST2> : a`): New
- pattern.
-
-2023-05-30 Roger Sayle <roger@nextmovesoftware.com>
-
- * simplify-rtx.cc (simplify_binary_operation_1) <AND>: Use wide-int
- instead of HWI_COMPUTABLE_MODE_P and UINTVAL in transformation of
- (and (extend X) C) as (zero_extend (and X C)), to also optimize
- modes wider than HOST_WIDE_INT.
-
-2023-05-30 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/107172
- * simplify-rtx.cc (simplify_const_relational_operation): Return
- early if we have a MODE_CC comparison that isn't a COMPARE against
- const0_rtx.
-
-2023-05-30 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_const_insns): Allow
- const_vec_duplicates.
-
-2023-05-30 liuhongt <hongtao.liu@intel.com>
-
- PR middle-end/108938
- * gimple-ssa-store-merging.cc (is_bswap_or_nop_p): New
- function, cut from original find_bswap_or_nop function.
- (find_bswap_or_nop): Add a new parameter, detect bswap +
- rotate and save rotate result in the new parameter.
- (bswap_replace): Add a new parameter to indicate rotate and
- generate rotate stmt if needed.
- (maybe_optimize_vector_constructor): Adjust for new rotate
- parameter in the upper 2 functions.
- (pass_optimize_bswap::execute): Ditto.
- (imm_store_chain_info::output_merged_store): Ditto.
-
-2023-05-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur>adalp<mode>): Delete.
- (aarch64_<su>adalp<mode>): New define_expand.
- (*aarch64_<su>adalp<mode><vczle><vczbe>_insn): New define_insn.
- (aarch64_<su>addlp<mode>): Convert to define_expand.
- (*aarch64_<su>addlp<mode><vczle><vczbe>_insn): New define_insn.
- * config/aarch64/iterators.md (UNSPEC_SADDLP, UNSPEC_UADDLP): Delete.
- (ADALP): Likewise.
- (USADDLP): Likewise.
- * config/aarch64/predicates.md (vect_par_cnst_even_or_odd_half): Define.
-
-2023-05-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (VAR1): Move to after inclusion of
- aarch64-builtin-iterators.h. Add definition to remap shadd, uhadd,
- srhadd, urhadd builtin codes for standard optab ones.
- * config/aarch64/aarch64-simd.md (<u>avg<mode>3_floor): Rename to...
- (<su_optab>avg<mode>3_floor): ... This. Expand to RTL codes rather than
- unspec.
- (<u>avg<mode>3_ceil): Rename to...
- (<su_optab>avg<mode>3_ceil): ... This. Expand to RTL codes rather than
- unspec.
- (aarch64_<su>hsub<mode>): New define_expand.
- (aarch64_<sur>h<addsub><mode><vczle><vczbe>): Split into...
- (*aarch64_<su>h<ADDSUB:optab><mode><vczle><vczbe>_insn): ... This...
- (*aarch64_<su>rhadd<mode><vczle><vczbe>_insn): ... And this.
-
-2023-05-30 Andreas Schwab <schwab@suse.de>
-
- PR target/110036
- * config/riscv/riscv.cc (riscv_asan_shadow_offset): Update to
- match libsanitizer.
-
-2023-05-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-modes.def (V16HI, V8SI, V4DI, V2TI): New modes.
- * config/aarch64/aarch64-protos.h (aarch64_const_vec_rnd_cst_p):
- Declare prototype.
- (aarch64_const_vec_rsra_rnd_imm_p): Likewise.
- * config/aarch64/aarch64-simd.md (*aarch64_simd_sra<mode>): Rename to...
- (aarch64_<sra_op>sra_n<mode>_insn): ... This.
- (aarch64_<sra_op>rsra_n<mode>_insn): New define_insn.
- (aarch64_<sra_op>sra_n<mode>): New define_expand.
- (aarch64_<sra_op>rsra_n<mode>): Likewise.
- (aarch64_<sur>sra_n<mode>): Rename to...
- (aarch64_<sur>sra_ndi): ... This.
- * config/aarch64/aarch64.cc (aarch64_classify_vector_mode): Add
- any_target_p argument.
- (aarch64_extract_vec_duplicate_wide_int): Define.
- (aarch64_const_vec_rsra_rnd_imm_p): Likewise.
- (aarch64_const_vec_rnd_cst_p): Likewise.
- (aarch64_vector_mode_supported_any_target_p): Likewise.
- (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
- * config/aarch64/iterators.md (UNSPEC_SRSRA, UNSPEC_URSRA): Delete.
- (VSRA): Adjust for the above.
- (sur): Likewise.
- (V2XWIDE): New mode_attr.
- (vec_or_offset): Likewise.
- (SHIFTEXTEND): Likewise.
- * config/aarch64/predicates.md (aarch64_simd_rsra_rnd_imm_vec): New
- predicate.
- * doc/tm.texi (TARGET_VECTOR_MODE_SUPPORTED_P): Adjust description to
- clarify that it applies to current target options.
- (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Document.
- * doc/tm.texi.in: Regenerate.
- * stor-layout.cc (mode_for_vector): Check
- vector_mode_supported_any_target_p when iterating through vector modes.
- * target.def (TARGET_VECTOR_MODE_SUPPORTED_P): Adjust description to
- clarify that it applies to current target options.
- (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Define.
-
-2023-05-30 Lili Cui <lili.cui@intel.com>
-
- PR tree-optimization/98350
- * tree-ssa-reassoc.cc
- (rewrite_expr_tree_parallel): Rewrite this function.
- (rank_ops_for_fma): New.
- (reassociate_bb): Handle new function.
-
-2023-05-30 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (rtx_addr_can_trap_p): Change return type from int to bool.
- (rtx_unstable_p): Ditto.
- (reg_mentioned_p): Ditto.
- (reg_referenced_p): Ditto.
- (reg_used_between_p): Ditto.
- (reg_set_between_p): Ditto.
- (modified_between_p): Ditto.
- (no_labels_between_p): Ditto.
- (modified_in_p): Ditto.
- (reg_set_p): Ditto.
- (multiple_sets): Ditto.
- (set_noop_p): Ditto.
- (noop_move_p): Ditto.
- (reg_overlap_mentioned_p): Ditto.
- (dead_or_set_p): Ditto.
- (dead_or_set_regno_p): Ditto.
- (find_reg_fusage): Ditto.
- (find_regno_fusage): Ditto.
- (side_effects_p): Ditto.
- (volatile_refs_p): Ditto.
- (volatile_insn_p): Ditto.
- (may_trap_p_1): Ditto.
- (may_trap_p): Ditto.
- (may_trap_or_fault_p): Ditto.
- (computed_jump_p): Ditto.
- (auto_inc_p): Ditto.
- (loc_mentioned_in_p): Ditto.
- * rtlanal.cc (computed_jump_p_1): Adjust forward declaration.
- (rtx_unstable_p): Change return type from int to bool
- and adjust function body accordingly.
- (rtx_addr_can_trap_p): Ditto.
- (reg_mentioned_p): Ditto.
- (no_labels_between_p): Ditto.
- (reg_used_between_p): Ditto.
- (reg_referenced_p): Ditto.
- (reg_set_between_p): Ditto.
- (reg_set_p): Ditto.
- (modified_between_p): Ditto.
- (modified_in_p): Ditto.
- (multiple_sets): Ditto.
- (set_noop_p): Ditto.
- (noop_move_p): Ditto.
- (reg_overlap_mentioned_p): Ditto.
- (dead_or_set_p): Ditto.
- (dead_or_set_regno_p): Ditto.
- (find_reg_fusage): Ditto.
- (find_regno_fusage): Ditto.
- (remove_node_from_insn_list): Ditto.
- (volatile_insn_p): Ditto.
- (volatile_refs_p): Ditto.
- (side_effects_p): Ditto.
- (may_trap_p_1): Ditto.
- (may_trap_p): Ditto.
- (may_trap_or_fault_p): Ditto.
- (computed_jump_p): Ditto.
- (auto_inc_p): Ditto.
- (loc_mentioned_in_p): Ditto.
- * combine.cc (can_combine_p): Update indirect function.
-
-2023-05-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (<optab><mode><vconvert>2): New pattern.
- * config/riscv/iterators.md: New attribute.
- * config/riscv/vector-iterators.md: New attribute.
-
-2023-05-30 From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.md: Fix signed and unsigned comparison
- warning.
-
-2023-05-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (fnma<mode>4): New pattern.
- (*fnma<mode>): Ditto.
-
-2023-05-29 Die Li <lidie@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move_onesided):
- Delete.
- (riscv_expand_conditional_move): Reuse the TARGET_SFB_ALU expand
- process for TARGET_XTHEADCONDMOV
-
-2023-05-29 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/110021
- * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also require
- TARGET_AVX512BW to generate truncv16hiv16qi2.
-
-2023-05-29 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * config/riscv/riscv.md (and<mode>3): New expander.
- (*and<mode>3) New pattern.
- * config/riscv/predicates.md (arith_operand_or_mode_mask): New
- predicate.
-
-2023-05-29 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary
- comments and rename local variables.
- (emit_nonvlmax_insn): Diito.
- (emit_vlmax_merge_insn): Ditto.
- (emit_vlmax_cmp_insn): Ditto.
- (emit_vlmax_cmp_mu_insn): Ditto.
- (emit_scalar_move_insn): Ditto.
-
-2023-05-29 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (emit_vlmax_insn): Eliminate the
- magic number.
- (emit_nonvlmax_insn): Ditto.
- (emit_vlmax_merge_insn): Ditto.
- (emit_vlmax_cmp_insn): Ditto.
- (emit_vlmax_cmp_mu_insn): Ditto.
- (expand_vec_series): Ditto.
-
-2023-05-29 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-protos.h (enum insn_type): New type.
- * config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
- (rvv_builder::can_duplicate_repeating_sequence_p): Align the referenced
- class member.
- (rvv_builder::get_merged_repeating_sequence): Ditto.
- (rvv_builder::repeating_sequence_use_merge_profitable_p): New function
- to evaluate the optimization cost.
- (rvv_builder::get_merge_scalar_mask): New function to get the merge
- mask.
- (emit_scalar_move_insn): New function to emit vmv.s.x.
- (emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
- (emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
- vmv.v.x.
- (get_repeating_sequence_dup_machine_mode): New function to get the dup
- machine mode.
- (expand_vector_init_merge_repeating_sequence): New function to perform
- the optimization.
- (expand_vec_init): Add this vector init optimization.
- * config/riscv/riscv.h (BITS_PER_WORD): New macro.
-
-2023-05-29 Eric Botcazou <ebotcazou@adacore.com>
-
- * tree-ssa-loop-manip.cc (create_iv): Try harder to find a SLOC to
- put onto the increment when it is inserted after the position.
-
-2023-05-29 Eric Botcazou <ebotcazou@adacore.com>
-
- * match.pd ((T)P - (T)(P + A) -> -(T) A): Avoid artificial overflow
- on constants.
-
-2023-05-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.
-
-2023-05-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (fma<mode>4): New pattern.
- (*fma<mode>): Ditto.
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- (emit_vlmax_ternary_insn): New function.
- * config/riscv/riscv-v.cc (emit_vlmax_ternary_insn): Ditto.
-
-2023-05-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix vimuladd instruction bug.
-
-2023-05-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (global_state_unknown_p): New function.
- (riscv_mode_after): Fix incorrect VXM.
-
-2023-05-29 Pan Li <pan2.li@intel.com>
-
- * common/config/riscv/riscv-common.cc:
- (riscv_implied_info): Add zvfhmin item.
- (riscv_ext_version_table): Ditto.
- (riscv_ext_flag_table): Ditto.
- * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
- (TARGET_ZFHMIN): Align indent.
- (TARGET_ZFH): Ditto.
- (TARGET_ZVFHMIN): New macro.
-
-2023-05-27 liuhongt <hongtao.liu@intel.com>
-
- PR target/100711
- * config/i386/sse.md (*andnot<mode>3): Extend below splitter
- to VI_AVX2 to cover more modes.
-
-2023-05-27 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/x86-tune.def (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI):
- Remove ATOM and ICELAKE(and later) core processors.
-
-2023-05-26 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<optab><mode>2): Add vneg/vnot.
- (abs<mode>2): Add.
- * config/riscv/riscv-protos.h (emit_vlmax_masked_mu_insn):
- Declare.
- * config/riscv/riscv-v.cc (emit_vlmax_masked_mu_insn): New
- function.
-
-2023-05-26 Robin Dapp <rdapp@ventanamicro.com>
- Juzhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (<optab><v_double_trunc><mode>2): New
- expander.
- (<optab><v_quad_trunc><mode>2): Dito.
- (<optab><v_oct_trunc><mode>2): Dito.
- (trunc<mode><v_double_trunc>2): Dito.
- (trunc<mode><v_quad_trunc>2): Dito.
- (trunc<mode><v_oct_trunc>2): Dito.
- * config/riscv/riscv-protos.h (vectorize_related_mode): Define.
- (autovectorize_vector_modes): Define.
- * config/riscv/riscv-v.cc (vectorize_related_mode): Implement
- hook.
- (autovectorize_vector_modes): Implement hook.
- * config/riscv/riscv.cc (riscv_autovectorize_vector_modes):
- Implement target hook.
- (riscv_vectorize_related_mode): Implement target hook.
- (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define.
- (TARGET_VECTORIZE_RELATED_MODE): Define.
- * config/riscv/vector-iterators.md: Add lowercase versions of
- mode_attr iterators.
-
-2023-05-26 Andrew Stubbs <ams@codesourcery.com>
- Tobias Burnus <tobias@codesourcery.com>
-
- * config/gcn/gcn-hsa.h (XNACKOPT): New macro.
- (ASM_SPEC): Use XNACKOPT.
- * config/gcn/gcn-opts.h (enum sram_ecc_type): Rename to ...
- (enum hsaco_attr_type): ... this, and generalize the names.
- (TARGET_XNACK): New macro.
- * config/gcn/gcn.cc (gcn_option_override): Update to sorry for all
- but -mxnack=off.
- (output_file_start): Update xnack handling.
- (gcn_hsa_declare_function_name): Use TARGET_XNACK.
- * config/gcn/gcn.opt (-mxnack): Add the "on/off/any" syntax.
- (sram_ecc_type): Rename to ...
- (hsaco_attr_type: ... this.)
- * config/gcn/mkoffload.cc (SET_XNACK_ANY): New macro.
- (TEST_XNACK): Delete.
- (TEST_XNACK_ANY): New macro.
- (TEST_XNACK_ON): New macro.
- (main): Support the new -mxnack=on/off/any syntax.
- * doc/invoke.texi (-mxnack): Update for new syntax.
-
-2023-05-26 Andrew Pinski <apinski@marvell.com>
-
- * genmatch.cc (emit_debug_printf): New function.
- (dt_simplify::gen_1): Emit printf into the code
- before the `return true` or returning the folded result
- instead of emitting it always.
-
-2023-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa-protos.h
- (xtensa_expand_block_set_unrolled_loop,
- xtensa_expand_block_set_small_loop): Remove.
- (xtensa_expand_block_set): New prototype.
- * config/xtensa/xtensa.cc
- (xtensa_expand_block_set_libcall): New subfunction.
- (xtensa_expand_block_set_unrolled_loop,
- xtensa_expand_block_set_small_loop): Rewrite as subfunctions.
- (xtensa_expand_block_set): New function that calls the above
- subfunctions.
- * config/xtensa/xtensa.md (memsetsi): Change to invoke only
- xtensa_expand_block_set().
-
-2023-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa-protos.h (xtensa_m1_or_1_thru_15):
- New prototype.
- * config/xtensa/xtensa.cc (xtensa_m1_or_1_thru_15):
- New function.
- * config/xtensa/constraints.md (O):
- Change to use the above function.
- * config/xtensa/xtensa.md (*subsi3_from_const):
- New insn_and_split pattern.
-
-2023-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3):
- Retract excessive line folding, and correct the value of
- the "length" insn attribute related to TARGET_DENSITY.
- (*extzvsi-1bit_addsubx): Ditto.
-
-2023-05-26 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_vecop_qihi):
- Do not disable call to ix86_expand_vecop_qihi2.
-
-2023-05-26 liuhongt <hongtao.liu@intel.com>
-
- PR target/109610
- PR target/109858
- * ira-costs.cc (scan_one_insn): Only use NO_REGS in cost
- calculation when !hard_regno_mode_ok for GENERAL_REGS and
- mode, otherwise still use GENERAL_REGS.
-
-2023-05-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (vector_zero_call_used_regs): Add
- explict VL and drop VL in ops.
-
-2023-05-25 Jin Ma <jinma@linux.alibaba.com>
-
- * sched-deps.cc (sched_macro_fuse_insns): Insns should not be fusion
- in different BB blocks.
-
-2023-05-25 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
- Rewrite to expand to 2x-wider (e.g. V16QI -> V16HImode)
- instructions when available. Emulate truncation via
- ix86_expand_vec_perm_const_1 when native truncate insn
- is not available.
- (ix86_expand_vecop_qihi_partial) <case MULT>: Use pmovzx
- when available. Trivially rename some variables.
- (ix86_expand_vecop_qihi): Unconditionally call ix86_expand_vecop_qihi2.
- * config/i386/i386.cc (ix86_multiplication_cost): Rewrite cost
- calculation of V*QImode emulations to account for generation of
- 2x-wider mode instructions.
- (ix86_shift_rotate_cost): Update cost calculation of V*QImode
- emulations to account for generation of 2x-wider mode instructions.
-
-2023-05-25 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/104327
- * config/avr/avr.cc (avr_can_inline_p): New static function.
- (TARGET_CAN_INLINE_P): Define to that function.
-
-2023-05-25 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/82931
- * config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6.
- Handle any bit position and use mode QISI.
- * config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost
- of 2 insns for bit-transfer of respective style.
-
-2023-05-25 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/iterators.md (MVE_6): Remove.
- * config/arm/mve.md: Replace MVE_6 with MVE_5.
-
-2023-05-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- Richard Sandiford <richard.sandiford@arm.com>
-
- * tree-vect-loop-manip.cc (vect_adjust_loop_lens_control): New
- function.
- (vect_set_loop_controls_directly): Add decrement IV support.
- (vect_set_loop_condition_partial_vectors): Ditto.
- * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): New
- variable.
- * tree-vectorizer.h (LOOP_VINFO_USING_DECREMENTING_IV_P): New
- macro.
-
-2023-05-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_fcadd<rot><mode>): Rename to...
- (aarch64_fcadd<rot><mode><vczle><vczbe>): ... This.
- Fix canonicalization of PLUS operands.
- (aarch64_fcmla<rot><mode>): Rename to...
- (aarch64_fcmla<rot><mode><vczle><vczbe>): ... This.
- Fix canonicalization of PLUS operands.
- (aarch64_fcmla_lane<rot><mode>): Rename to...
- (aarch64_fcmla_lane<rot><mode><vczle><vczbe>): ... This.
- Fix canonicalization of PLUS operands.
- (aarch64_fcmla_laneq<rot>v4hf): Rename to...
- (aarch64_fcmla_laneq<rot>v4hf<vczle><vczbe>): ... This.
- Fix canonicalization of PLUS operands.
- (aarch64_fcmlaq_lane<rot><mode>): Fix canonicalization of PLUS operands.
-
-2023-05-25 Chris Sidebottom <chris.sidebottom@arm.com>
-
- * config/arm/arm.md (rbitsi2): Rename to...
- (arm_rbit): ... This.
- (ctzsi2): Adjust for the above.
- (arm_rev16si2): Convert to define_expand.
- (arm_rev16si2_alt1): New pattern.
- (arm_rev16si2_alt): Rename to...
- (*arm_rev16si2_alt2): ... This.
- * config/arm/arm_acle.h (__ror, __rorl, __rorll, __clz, __clzl, __clzll,
- __cls, __clsl, __clsll, __revsh, __rev, __revl, __revll, __rev16,
- __rev16l, __rev16ll, __rbit, __rbitl, __rbitll): Define intrinsics.
- * config/arm/arm_acle_builtins.def (rbit, rev16si2): Define builtins.
-
-2023-05-25 Alex Coplan <alex.coplan@arm.com>
-
- PR target/109800
- * config/arm/arm.md (movdf): Generate temporary pseudo in DImode
- instead of DFmode.
- * config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an
- lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into
- DFmode as an rvalue.
-
-2023-05-25 Richard Biener <rguenther@suse.de>
-
- PR target/109955
- * tree-vect-stmts.cc (vectorizable_condition): For
- embedded comparisons also handle the case when the target
- only provides vec_cmp and vcond_mask.
-
-2023-05-25 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc.cc (arc_call_tls_get_addr): Simplify access using
- TLS Local Dynamic.
-
-2023-05-25 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- * config/aarch64/aarch64.cc (scalar_move_insn_p): New function.
- (seq_cost_ignoring_scalar_moves): Likewise.
- (aarch64_expand_vector_init): Call seq_cost_ignoring_scalar_moves.
-
-2023-05-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/arm_neon.h (vcage_f64): Reimplement with builtins.
- (vcage_f32): Likewise.
- (vcages_f32): Likewise.
- (vcageq_f32): Likewise.
- (vcaged_f64): Likewise.
- (vcageq_f64): Likewise.
- (vcagts_f32): Likewise.
- (vcagt_f32): Likewise.
- (vcagt_f64): Likewise.
- (vcagtq_f32): Likewise.
- (vcagtd_f64): Likewise.
- (vcagtq_f64): Likewise.
- (vcale_f32): Likewise.
- (vcale_f64): Likewise.
- (vcaled_f64): Likewise.
- (vcales_f32): Likewise.
- (vcaleq_f32): Likewise.
- (vcaleq_f64): Likewise.
- (vcalt_f32): Likewise.
- (vcalt_f64): Likewise.
- (vcaltd_f64): Likewise.
- (vcaltq_f32): Likewise.
- (vcaltq_f64): Likewise.
- (vcalts_f32): Likewise.
-
-2023-05-25 Hu, Lin1 <lin1.hu@intel.com>
-
- PR target/109173
- PR target/109174
- * config/i386/avx512bwintrin.h (_mm512_srli_epi16): Change type from
- int to const int or const int to const unsigned int.
- (_mm512_mask_srli_epi16): Ditto.
- (_mm512_slli_epi16): Ditto.
- (_mm512_mask_slli_epi16): Ditto.
- (_mm512_maskz_slli_epi16): Ditto.
- (_mm512_srai_epi16): Ditto.
- (_mm512_mask_srai_epi16): Ditto.
- (_mm512_maskz_srai_epi16): Ditto.
- * config/i386/avx512fintrin.h (_mm512_slli_epi64): Ditto.
- (_mm512_mask_slli_epi64): Ditto.
- (_mm512_maskz_slli_epi64): Ditto.
- (_mm512_srli_epi64): Ditto.
- (_mm512_mask_srli_epi64): Ditto.
- (_mm512_maskz_srli_epi64): Ditto.
- (_mm512_srai_epi64): Ditto.
- (_mm512_mask_srai_epi64): Ditto.
- (_mm512_maskz_srai_epi64): Ditto.
- (_mm512_slli_epi32): Ditto.
- (_mm512_mask_slli_epi32): Ditto.
- (_mm512_maskz_slli_epi32): Ditto.
- (_mm512_srli_epi32): Ditto.
- (_mm512_mask_srli_epi32): Ditto.
- (_mm512_maskz_srli_epi32): Ditto.
- (_mm512_srai_epi32): Ditto.
- (_mm512_mask_srai_epi32): Ditto.
- (_mm512_maskz_srai_epi32): Ditto.
- * config/i386/avx512vlbwintrin.h (_mm256_mask_srai_epi16): Ditto.
- (_mm256_maskz_srai_epi16): Ditto.
- (_mm_mask_srai_epi16): Ditto.
- (_mm_maskz_srai_epi16): Ditto.
- (_mm256_mask_slli_epi16): Ditto.
- (_mm256_maskz_slli_epi16): Ditto.
- (_mm_mask_slli_epi16): Ditto.
- (_mm_maskz_slli_epi16): Ditto.
- (_mm_maskz_srli_epi16): Ditto.
- * config/i386/avx512vlintrin.h (_mm256_mask_srli_epi32): Ditto.
- (_mm256_maskz_srli_epi32): Ditto.
- (_mm_mask_srli_epi32): Ditto.
- (_mm_maskz_srli_epi32): Ditto.
- (_mm256_mask_srli_epi64): Ditto.
- (_mm256_maskz_srli_epi64): Ditto.
- (_mm_mask_srli_epi64): Ditto.
- (_mm_maskz_srli_epi64): Ditto.
- (_mm256_mask_srai_epi32): Ditto.
- (_mm256_maskz_srai_epi32): Ditto.
- (_mm_mask_srai_epi32): Ditto.
- (_mm_maskz_srai_epi32): Ditto.
- (_mm256_srai_epi64): Ditto.
- (_mm256_mask_srai_epi64): Ditto.
- (_mm256_maskz_srai_epi64): Ditto.
- (_mm_srai_epi64): Ditto.
- (_mm_mask_srai_epi64): Ditto.
- (_mm_maskz_srai_epi64): Ditto.
- (_mm_mask_slli_epi32): Ditto.
- (_mm_maskz_slli_epi32): Ditto.
- (_mm_mask_slli_epi64): Ditto.
- (_mm_maskz_slli_epi64): Ditto.
- (_mm256_mask_slli_epi32): Ditto.
- (_mm256_maskz_slli_epi32): Ditto.
- (_mm256_mask_slli_epi64): Ditto.
- (_mm256_maskz_slli_epi64): Ditto.
-
-2023-05-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz
- instructions.
-
-2023-05-25 Aldy Hernandez <aldyh@redhat.com>
-
- * data-streamer-in.cc (streamer_read_value_range): Handle NANs.
- * data-streamer-out.cc (streamer_write_vrange): Same.
- * value-range.h (class vrange): Make streamer_write_vrange a friend.
-
-2023-05-25 Aldy Hernandez <aldyh@redhat.com>
-
- * value-query.cc (range_query::get_tree_range): Set NAN directly
- if necessary.
- * value-range.cc (frange::set): Assert that bounds are not NAN.
-
-2023-05-25 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (add_vrange): Handle known NANs.
-
-2023-05-25 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (frange::set_nan): New.
-
-2023-05-25 Alexandre Oliva <oliva@adacore.com>
-
- PR target/100106
- * emit-rtl.cc (validate_subreg): Reject a SUBREG of a MEM that
- requires stricter alignment than MEM's.
-
-2023-05-24 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/107822
- PR tree-optimization/107986
- * Makefile.in (OBJS): Add gimple-range-phi.o.
- * gimple-range-cache.h (ranger_cache::m_estimate): New
- phi_analyzer pointer member.
- * gimple-range-fold.cc (fold_using_range::range_of_phi): Use
- phi_analyzer if no loop info is available.
- * gimple-range-phi.cc: New file.
- * gimple-range-phi.h: New file.
- * tree-vrp.cc (execute_ranger_vrp): Utililze a phi_analyzer.
-
-2023-05-24 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-fold.cc (fur_list::fur_list): Add range_query param
- to contructors.
- (fold_range): Add range_query parameter.
- (fur_relation::fur_relation): New.
- (fur_relation::trio): New.
- (fur_relation::register_relation): New.
- (fold_relations): New.
- * gimple-range-fold.h (fold_range): Adjust prototypes.
- (fold_relations): New.
-
-2023-05-24 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-cache.cc (ssa_cache::range_of_expr): New.
- * gimple-range-cache.h (class ssa_cache): Inherit from range_query.
- (ranger_cache::const_query): New.
- * gimple-range.cc (gimple_ranger::const_query): New.
- * gimple-range.h (gimple_ranger::const_query): New prototype.
-
-2023-05-24 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-cache.cc (ssa_cache::dump): Use get_range.
- (ssa_cache::dump_range_query): Delete.
- (ssa_lazy_cache::dump_range_query): Delete.
- (ssa_lazy_cache::get_range): Move from header file.
- (ssa_lazy_cache::clear_range): ditto.
- (ssa_lazy_cache::clear): Ditto.
- * gimple-range-cache.h (class ssa_cache): Virtualize.
- (class ssa_lazy_cache): Inherit and virtualize.
-
-2023-05-24 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (vrange::kind): Remove.
-
-2023-05-24 Roger Sayle <roger@nextmovesoftware.com>
-
- PR middle-end/109840
- * match.pd <popcount optimizations>: Preserve zero-extension when
- optimizing popcount((T)bswap(x)) and popcount((T)rotate(x,y)) as
- popcount((T)x), so the popcount's argument keeps the same type.
- <parity optimizations>: Likewise preserve extensions when
- simplifying parity((T)bswap(x)) and parity((T)rotate(x,y)) as
- parity((T)x), so that the parity's argument type is the same.
-
-2023-05-24 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-cp.cc (ipa_value_range_from_jfunc): Use new ipa_vr API.
- (ipcp_store_vr_results): Same.
- * ipa-prop.cc (ipa_vr::ipa_vr): New.
- (ipa_vr::get_vrange): New.
- (ipa_vr::set_unknown): New.
- (ipa_vr::streamer_read): New.
- (ipa_vr::streamer_write): New.
- (write_ipcp_transformation_info): Use new ipa_vr API.
- (read_ipcp_transformation_info): Same.
- (ipa_vr::nonzero_p): Delete.
- (ipcp_update_vr): Use new ipa_vr API.
- * ipa-prop.h (class ipa_vr): Provide an API and hide internals.
- * ipa-sra.cc (zap_useless_ipcp_results): Use new ipa_vr API.
-
-2023-05-24 Jan-Benedict Glaw <jbglaw@lug-owl.de>
-
- * config/mcore/mcore.cc (output_inline_const) Make buffer smaller to
- silence overflow warnings later on.
-
-2023-05-24 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
- Remove handling of V8QImode.
- * config/i386/mmx.md (v<insn>v8qi3): Move from sse.md.
- Call ix86_expand_vecop_qihi_partial. Enable for TARGET_MMX_WITH_SSE.
- (v<insn>v4qi3): Ditto.
- * config/i386/sse.md (v<insn>v8qi3): Remove.
-
-2023-05-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_simd_lshr<mode>): Rename to...
- (aarch64_simd_lshr<mode><vczle><vczbe>): ... This.
- (aarch64_simd_ashr<mode>): Rename to...
- (aarch64_simd_ashr<mode><vczle><vczbe>): ... This.
- (aarch64_simd_imm_shl<mode>): Rename to...
- (aarch64_simd_imm_shl<mode><vczle><vczbe>): ... This.
- (aarch64_simd_reg_sshl<mode>): Rename to...
- (aarch64_simd_reg_sshl<mode><vczle><vczbe>): ... This.
- (aarch64_simd_reg_shl<mode>_unsigned): Rename to...
- (aarch64_simd_reg_shl<mode>_unsigned<vczle><vczbe>): ... This.
- (aarch64_simd_reg_shl<mode>_signed): Rename to...
- (aarch64_simd_reg_shl<mode>_signed<vczle><vczbe>): ... This.
- (vec_shr_<mode>): Rename to...
- (vec_shr_<mode><vczle><vczbe>): ... This.
- (aarch64_<sur>shl<mode>): Rename to...
- (aarch64_<sur>shl<mode><vczle><vczbe>): ... This.
- (aarch64_<sur>q<r>shl<mode>): Rename to...
- (aarch64_<sur>q<r>shl<mode><vczle><vczbe>): ... This.
-
-2023-05-24 Richard Biener <rguenther@suse.de>
-
- PR target/109944
- * config/i386/i386-expand.cc (ix86_expand_vector_init_general):
- Perform final vector composition using
- ix86_expand_vector_init_general instead of setting
- the highpart and lowpart which causes spilling.
-
-2023-05-24 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109695
- * gimple-range-cache.cc (ranger_cache::get_global_range): Add
- changed param.
- * gimple-range-cache.h (ranger_cache::get_global_range): Ditto.
- * gimple-range.cc (gimple_ranger::range_of_stmt): Pass changed
- flag to set_global_range.
- (gimple_ranger::prefill_stmt_dependencies): Ditto.
-
-2023-05-24 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109695
- * gimple-range-cache.cc (temporal_cache::temporal_value): Return
- a positive int.
- (temporal_cache::current_p): Check always_current method.
- (temporal_cache::set_always_current): Add param and set value
- appropriately.
- (temporal_cache::always_current_p): New.
- (ranger_cache::get_global_range): Adjust.
- (ranger_cache::set_global_range): set always current first.
-
-2023-05-24 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109695
- * gimple-range-cache.cc (ranger_cache::get_global_range): Call
- fold_range with global query to choose an initial value.
-
-2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum frm_field_enum): Add FRM_
- prefix.
-
-2023-05-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109849
- * tree-ssa-pre.cc (do_hoist_insertion): Do not intersect
- expressions but take the first sets.
-
-2023-05-24 Gaius Mulley <gaiusmod2@gmail.com>
-
- PR modula2/109952
- * doc/gm2.texi (High procedure function): New node.
- (Using): New menu entry for High procedure function.
-
-2023-05-24 Richard Sandiford <richard.sandiford@arm.com>
-
- PR rtl-optimization/109940
- * early-remat.cc (postorder_index): Rename to...
- (rpo_index): ...this.
- (compare_candidates): Sort by decreasing rpo_index rather than
- increasing postorder_index.
- (early_remat::sort_candidates): Calculate the forward RPO from
- DF_FORWARD.
- (early_remat::local_phase): Follow forward RPO using DF_FORWARD,
- rather than DF_BACKWARD in reverse.
-
-2023-05-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/109939
- * config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use
- qualifier_none for the return operand.
-
-2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (<optab><mode>3): New pattern.
- (one_cmpl<mode>2): Ditto.
- (*<optab>not<mode>): Ditto.
- (*n<optab><mode>): Ditto.
- * config/riscv/riscv-v.cc (expand_vec_cmp_float): Change to
- one_cmpl.
-
-2023-05-24 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-slp.cc (vect_transform_slp_perm_load_1): Adjust the
- calculation on n_perms by considering nvectors_per_build.
-
-2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- Richard Sandiford <richard.sandiford@arm.com>
-
- * config/riscv/autovec.md (@vcond_mask_<mode><vm>): New pattern.
- (vec_cmp<mode><vm>): New pattern.
- (vec_cmpu<mode><vm>): New pattern.
- (vcond<V:mode><VI:mode>): New pattern.
- (vcondu<V:mode><VI:mode>): New pattern.
- * config/riscv/riscv-protos.h (enum insn_type): Add new enum.
- (emit_vlmax_merge_insn): New function.
- (emit_vlmax_cmp_insn): Ditto.
- (emit_vlmax_cmp_mu_insn): Ditto.
- (expand_vec_cmp): Ditto.
- (expand_vec_cmp_float): Ditto.
- (expand_vcond): Ditto.
- * config/riscv/riscv-v.cc (emit_vlmax_merge_insn): Ditto.
- (emit_vlmax_cmp_insn): Ditto.
- (emit_vlmax_cmp_mu_insn): Ditto.
- (get_cmp_insn_code): Ditto.
- (expand_vec_cmp): Ditto.
- (expand_vec_cmp_float): Ditto.
- (expand_vcond): Ditto.
-
-2023-05-24 Pan Li <pan2.li@intel.com>
-
- * config/riscv/genrvv-type-indexer.cc (main): Add
- unsigned_eew*_lmul1_interpret for indexer.
- * config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
- Register vuint*m1_t interpret function.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
- New macro for vuint8m1_t.
- (DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
- (DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
- (DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
- (vbool1_t): Add to unsigned_eew*_interpret_ops.
- (vbool2_t): Likewise.
- (vbool4_t): Likewise.
- (vbool8_t): Likewise.
- (vbool16_t): Likewise.
- (vbool32_t): Likewise.
- (vbool64_t): Likewise.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
- New macro for vuint*m1_t.
- (DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
- (DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
- (DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
- (required_extensions_p): Add vuint*m1_t interpret case.
- * config/riscv/riscv-vector-builtins.def (unsigned_eew8_lmul1_interpret):
- Add vuint*m1_t interpret to base type.
- (unsigned_eew16_lmul1_interpret): Likewise.
- (unsigned_eew32_lmul1_interpret): Likewise.
- (unsigned_eew64_lmul1_interpret): Likewise.
-
-2023-05-24 Pan Li <pan2.li@intel.com>
-
- * config/riscv/genrvv-type-indexer.cc (EEW_SIZE_LIST): New macro
- for the eew size list.
- (LMUL1_LOG2): New macro for the log2 value of lmul=1.
- (main): Add signed_eew*_lmul1_interpret for indexer.
- * config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
- Register vint*m1_t interpret function.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
- New macro for vint8m1_t.
- (DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
- (DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
- (DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
- (vbool1_t): Add to signed_eew*_interpret_ops.
- (vbool2_t): Likewise.
- (vbool4_t): Likewise.
- (vbool8_t): Likewise.
- (vbool16_t): Likewise.
- (vbool32_t): Likewise.
- (vbool64_t): Likewise.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
- New macro for vint*m1_t.
- (DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
- (DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
- (DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
- (required_extensions_p): Add vint8m1_t interpret case.
- * config/riscv/riscv-vector-builtins.def (signed_eew8_lmul1_interpret):
- Add vint*m1_t interpret to base type.
- (signed_eew16_lmul1_interpret): Likewise.
- (signed_eew32_lmul1_interpret): Likewise.
- (signed_eew64_lmul1_interpret): Likewise.
-
-2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Adjust for new interface.
- * config/riscv/riscv-protos.h (emit_vlmax_insn): Add VL operand.
- (emit_nonvlmax_insn): Add AVL operand.
- * config/riscv/riscv-v.cc (emit_vlmax_insn): Add VL operand.
- (emit_nonvlmax_insn): Add AVL operand.
- (sew64_scalar_helper): Adjust for new interface.
- (expand_tuple_move): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_vec_series): Remove magic number.
- (expand_const_vector): Ditto.
- (legitimize_move): Ditto.
- (sew64_scalar_helper): Ditto.
- (expand_tuple_move): Ditto.
- (expand_vector_init_insert_elems): Ditto.
- * config/riscv/riscv.cc (vector_zero_call_used_regs): Ditto.
-
-2023-05-24 liuhongt <hongtao.liu@intel.com>
-
- PR target/109900
- * config/i386/i386.cc (ix86_gimple_fold_builtin): Fold
- _mm{,256,512}_abs_{epi8,epi16,epi32,epi64} and
- _mm_abs_{pi8,pi16,pi32} into gimple ABS_EXPR.
- (ix86_masked_all_ones): Handle 64-bit mask.
- * config/i386/i386-builtin.def: Replace icode of related
- non-mask simd abs builtins with CODE_FOR_nothing.
-
-2023-05-23 Martin Uecker <uecker@tugraz.at>
-
- PR c/109450
- * function.cc (gimplify_parm_type): Remove function.
- (gimplify_parameters): Call gimplify_type_sizes.
-
-2023-05-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
- and change to also accept '*subx' pattern.
- (*subx): Remove.
-
-2023-05-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/predicates.md (addsub_operator): New.
- * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3,
- *extzvsi-1bit_addsubx): New insn_and_split patterns.
- * config/xtensa/xtensa.cc (xtensa_rtx_costs):
- Add a special case about ifcvt 'noce_try_cmove()' to handle
- constant loads that do not fit into signed 12 bits in the
- patterns added above.
-
-2023-05-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109747
- * tree-vect-slp.cc (vect_prologue_cost_for_slp): Pass down
- the SLP node only once to the cost hook.
-
-2023-05-23 Georg-Johann Lay <avr@gjlay.de>
-
- * config/avr/avr.cc (avr_insn_cost): New static function.
- (TARGET_INSN_COST): Define to that function.
-
-2023-05-23 Richard Biener <rguenther@suse.de>
-
- PR target/109944
- * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
- For vector construction or splats apply GPR->XMM move
- costing. QImode memory can be handled directly only
- with SSE4.1 pinsrb.
-
-2023-05-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108752
- * tree-vect-stmts.cc (vectorizable_operation): For bit
- operations with generic word_mode vectors do not cost
- an extra stmt. For plus, minus and negate also cost the
- constant materialization.
-
-2023-05-23 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_vecop_qihi_partial):
- Call ix86_expand_vec_shift_qihi_constant for shifts
- with constant count operand.
- * config/i386/i386.cc (ix86_shift_rotate_cost):
- Handle V4QImode and V8QImode.
- * config/i386/mmx.md (<insn>v8qi3): New insn pattern.
- (<insn>v4qi3): Ditto.
-
-2023-05-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Add mode.
-
-2023-05-23 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/109934
- * value-range.cc (irange::invert): Remove buggy special case.
-
-2023-05-23 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-pre.cc (compute_antic_aux): Dump the correct
- ANTIC_OUT.
-
-2023-05-23 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/109632
- * config/aarch64/aarch64.cc (aarch64_modes_tieable_p): Allow
- subregs between any scalars that are 64 bits or smaller.
- * config/aarch64/iterators.md (SUBDI_BITS): New int iterator.
- (bits_etype): New int attribute.
- * config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
- (*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>): New patterns.
- (*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Likewise.
-
-2023-05-23 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/md.texi: Document that <FOO> can be used to refer to the
- numerical value of an int iterator FOO. Tweak other parts of
- the int iterator documentation.
- * read-rtl.cc (iterator_group::has_self_attr): New field.
- (map_attr_string): When has_self_attr is true, make <FOO>
- expand to the current value of iterator FOO.
- (initialize_iterators): Set has_self_attr for int iterators.
-
-2023-05-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Refactor the framework of RVV auto-vectorization.
- * config/riscv/riscv-protos.h (RVV_MISC_OP_NUM): Ditto.
- (RVV_UNOP_NUM): New macro.
- (RVV_BINOP_NUM): Ditto.
- (legitimize_move): Refactor the framework of RVV auto-vectorization.
- (emit_vlmax_op): Ditto.
- (emit_vlmax_reg_op): Ditto.
- (emit_len_op): Ditto.
- (emit_len_binop): Ditto.
- (emit_vlmax_tany_many): Ditto.
- (emit_nonvlmax_tany_many): Ditto.
- (sew64_scalar_helper): Ditto.
- (expand_tuple_move): Ditto.
- * config/riscv/riscv-v.cc (emit_pred_op): Ditto.
- (emit_pred_binop): Ditto.
- (emit_vlmax_op): Ditto.
- (emit_vlmax_tany_many): New function.
- (emit_len_op): Remove.
- (emit_nonvlmax_tany_many): New function.
- (emit_vlmax_reg_op): Remove.
- (emit_len_binop): Ditto.
- (emit_index_op): Ditto.
- (expand_vec_series): Refactor the framework of RVV auto-vectorization.
- (expand_const_vector): Ditto.
- (legitimize_move): Ditto.
- (sew64_scalar_helper): Ditto.
- (expand_tuple_move): Ditto.
- (expand_vector_init_insert_elems): Ditto.
- * config/riscv/riscv.cc (vector_zero_call_used_regs): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-05-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/109855
- * config/aarch64/aarch64-simd.md (add_vec_concat_subst_le): Add predicate
- and constraint for operand 0.
- (add_vec_concat_subst_be): Likewise.
-
-2023-05-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109849
- * tree-ssa-pre.cc (do_hoist_insertion): Compute ANTIC_OUT
- and use that to determine what to hoist.
-
-2023-05-23 Eric Botcazou <ebotcazou@adacore.com>
-
- * fold-const.cc (native_encode_initializer) <CONSTRUCTOR>: Apply the
- specific treatment for bit-fields only if they have an integral type
- and filter out non-integral bit-fields that do not start and end on
- a byte boundary.
-
-2023-05-23 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/109920
- * value-range.h (RESIZABLE>::~int_range): Use delete[].
-
-2023-05-22 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.cc (ix86_shift_rotate_cost): Correct
- calcuation of integer vector mode costs to reflect generated
- instruction sequences of different integer vector modes and
- different target ABIs. Remove "speed" function argument.
- (ix86_rtx_costs): Update call for removed function argument.
- (ix86_vector_costs::add_stmt_cost): Ditto.
-
-2023-05-22 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (class Value_Range): Implement set_zero,
- set_nonzero, and nonzero_p.
-
-2023-05-22 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.cc (ix86_multiplication_cost): Add
- the cost of a memory read to the cost of V?QImode sequences.
-
-2023-05-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc: Add "m_" prefix.
-
-2023-05-22 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-loop.cc (vect_get_loop_len): Fix issue for
- multiple-rgroup of length.
- * tree-vect-stmts.cc (vectorizable_store): Ditto.
- (vectorizable_load): Ditto.
- * tree-vectorizer.h (vect_get_loop_len): Ditto.
-
-2023-05-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_const_insns): Reorganize the
- codes.
-
-2023-05-22 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-slp.cc (vect_transform_slp_perm_load_1): Refactor the
- handling for the case index == count.
-
-2023-05-21 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/90622
- * config/avr/avr.cc (avr_fold_builtin) [AVR_BUILTIN_INSERT_BITS]:
- Don't fold to XOR / AND / XOR if just one bit is copied to the
- same position.
-
-2023-05-21 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/nvptx/nvptx.cc (nvptx_expand_brev): Expand target
- builtin for bit reversal using brev instruction.
- (enum nvptx_builtins): Add NVPTX_BUILTIN_BREV and
- NVPTX_BUILTIN_BREVLL.
- (nvptx_init_builtins): Define "brev" and "brevll".
- (nvptx_expand_builtin): Expand NVPTX_BUILTIN_BREV and
- NVPTX_BUILTIN_BREVLL via nvptx_expand_brev function.
- * doc/extend.texi (Nvidia PTX Builtin-in Functions): New
- section, document __builtin_nvptx_brev{,ll}.
-
-2023-05-21 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109505
- * match.pd ((x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2),
- Combine successive equal operations with constants,
- (A +- CST1) +- CST2 -> A + CST3, (CST1 - A) +- CST2 -> CST3 - A,
- CST1 - (CST2 - A) -> CST3 + A): Use ! on ops with 2 CONSTANT_CLASS_P
- operands.
-
-2023-05-21 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (expand_single_bit_test): Correct bitpos for big-endian.
-
-2023-05-21 Pan Li <pan2.li@intel.com>
-
- * config/riscv/genrvv-type-indexer.cc (BOOL_SIZE_LIST): Add the
- rest bool size, aka 2, 4, 8, 16, 32, 64.
- * config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
- Register vbool[2|4|8|16|32|64] interpret function.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_BOOL2_INTERPRET_OPS):
- New macro for vbool2_t.
- (DEF_RVV_BOOL4_INTERPRET_OPS): Likewise.
- (DEF_RVV_BOOL8_INTERPRET_OPS): Likewise.
- (DEF_RVV_BOOL16_INTERPRET_OPS): Likewise.
- (DEF_RVV_BOOL32_INTERPRET_OPS): Likewise.
- (DEF_RVV_BOOL64_INTERPRET_OPS): Likewise.
- (vint8m1_t): Add the type to bool[2|4|8|16|32|64]_interpret_ops.
- (vint16m1_t): Likewise.
- (vint32m1_t): Likewise.
- (vint64m1_t): Likewise.
- (vuint8m1_t): Likewise.
- (vuint16m1_t): Likewise.
- (vuint32m1_t): Likewise.
- (vuint64m1_t): Likewise.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_BOOL2_INTERPRET_OPS):
- New macro for vbool2_t.
- (DEF_RVV_BOOL4_INTERPRET_OPS): Likewise.
- (DEF_RVV_BOOL8_INTERPRET_OPS): Likewise.
- (DEF_RVV_BOOL16_INTERPRET_OPS): Likewise.
- (DEF_RVV_BOOL32_INTERPRET_OPS): Likewise.
- (DEF_RVV_BOOL64_INTERPRET_OPS): Likewise.
- (required_extensions_p): Add vbool[2|4|8|16|32|64] interpret case.
- * config/riscv/riscv-vector-builtins.def (bool2_interpret): Add
- vbool2_t interprect to base type.
- (bool4_interpret): Likewise.
- (bool8_interpret): Likewise.
- (bool16_interpret): Likewise.
- (bool32_interpret): Likewise.
- (bool64_interpret): Likewise.
-
-2023-05-21 Andrew Pinski <apinski@marvell.com>
-
- PR middle-end/109919
- * expr.cc (expand_single_bit_test): Don't use the
- target for expand_expr.
-
-2023-05-20 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/install.texi (Specific): Remove de facto empty alpha*-*-*
- section.
-
-2023-05-20 Pan Li <pan2.li@intel.com>
-
- * mode-switching.cc (entity_map): Initialize the array to zero.
- (bb_info): Ditto.
-
-2023-05-20 Triffid Hunter <triffid.hunter@gmail.com>
-
- PR target/105753
- * config/avr/avr.md (divmodpsi, udivmodpsi, divmodsi, udivmodsi):
- Remove superfluous "parallel" in insn pattern.
- ([u]divmod<mode>4): Tidy code. Use gcc_unreachable() instead of
- printing error text to assembly.
-
-2023-05-20 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (fold_single_bit_test): Rename to ...
- (expand_single_bit_test): This and expand directly.
- (do_store_flag): Update for the rename function.
-
-2023-05-20 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (fold_single_bit_test): Use BIT_FIELD_REF
- instead of shift/and.
-
-2023-05-20 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (fold_single_bit_test): Add an assert
- and simplify based on code being NE_EXPR or EQ_EXPR.
-
-2023-05-20 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (fold_single_bit_test): Take inner and bitnum
- instead of arg0 and arg1. Update the code.
- (do_store_flag): Don't create a tree when calling
- fold_single_bit_test instead just call it with the bitnum
- and the inner tree.
-
-2023-05-20 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (fold_single_bit_test): Use get_def_for_expr
- instead of checking the inner's code.
-
-2023-05-20 Andrew Pinski <apinski@marvell.com>
-
- * expr.cc (fold_single_bit_test_into_sign_test): Inline into ...
- (fold_single_bit_test): This and simplify.
-
-2023-05-20 Andrew Pinski <apinski@marvell.com>
-
- * fold-const.cc (fold_single_bit_test_into_sign_test): Move to
- expr.cc.
- (fold_single_bit_test): Likewise.
- * expr.cc (fold_single_bit_test_into_sign_test): Move from fold-const.cc
- (fold_single_bit_test): Likewise and make static.
- * fold-const.h (fold_single_bit_test): Remove declaration.
-
-2023-05-20 Die Li <lidie@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Fix mode
- checking.
-
-2023-05-20 Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
-
- * config/riscv/bitmanip.md (branch<X:mode>_bext): New split pattern.
-
-2023-05-20 Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
-
- PR target/106888
- * config/riscv/bitmanip.md
- (<bitmanip_optab>disi2): Match with any_extend.
- (<bitmanip_optab>disi2_sext): New pattern to match
- with sign extend using an ANDI instruction.
-
-2023-05-19 Nathan Sidwell <nathan@acm.org>
-
- PR other/99451
- * opts.h (handle_deferred_dump_options): Declare.
- * opts-global.cc (handle_common_deferred_options): Do not handle
- dump options here.
- (handle_deferred_dump_options): New.
- * toplev.cc (toplev::main): Call it after plugin init.
-
-2023-05-19 Joern Rennecke <joern.rennecke@embecosm.com>
-
- * config/riscv/constraints.md (DsS, DsD): Restore agreement
- with shiftm1 mode attribute.
-
-2023-05-19 Andrew Pinski <apinski@marvell.com>
-
- PR driver/33980
- * gcc.cc (default_compilers["@c-header"]): Add %w
- after the --output-pch.
-
-2023-05-19 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_split_integer): if loval is equal
- to hival, ASHIFT the corresponding regs.
-
-2023-05-19 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_const_insns): Remove else.
-
-2023-05-19 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/105776
- * tree-ssa-math-opts.cc (arith_overflow_check_p): If cast_stmt is
- non-NULL, allow division statement to have a cast as single imm use
- rather than comparison/condition.
- (match_arith_overflow): In that case remove the cast stmt in addition
- to the division statement.
-
-2023-05-19 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/101856
- * tree-ssa-math-opts.cc (match_arith_overflow): Pattern detect
- unsigned __builtin_mul_overflow_p even when umulv4_optab doesn't
- support it but umul_highpart_optab does.
-
-2023-05-19 Eric Botcazou <ebotcazou@adacore.com>
-
- * varasm.cc (output_constructor_bitfield): Call tree_to_uhwi instead
- of tree_to_shwi on array indices. Minor tweaks.
-
-2023-05-18 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
-
- * alias.cc (ref_all_alias_ptr_type_p): Use _P() defines from tree.h.
- * attribs.cc (diag_attr_exclusions): Ditto.
- (decl_attributes): Ditto.
- (build_type_attribute_qual_variant): Ditto.
- * builtins.cc (fold_builtin_carg): Ditto.
- (fold_builtin_next_arg): Ditto.
- (do_mpc_arg2): Ditto.
- * cfgexpand.cc (expand_return): Ditto.
- * cgraph.h (decl_in_symtab_p): Ditto.
- (symtab_node::get_create): Ditto.
- * dwarf2out.cc (base_type_die): Ditto.
- (implicit_ptr_descriptor): Ditto.
- (gen_array_type_die): Ditto.
- (gen_type_die_with_usage): Ditto.
- (optimize_location_into_implicit_ptr): Ditto.
- * expr.cc (do_store_flag): Ditto.
- * fold-const.cc (negate_expr_p): Ditto.
- (fold_negate_expr_1): Ditto.
- (fold_convert_const): Ditto.
- (fold_convert_loc): Ditto.
- (constant_boolean_node): Ditto.
- (fold_binary_op_with_conditional_arg): Ditto.
- (build_fold_addr_expr_with_type_loc): Ditto.
- (fold_comparison): Ditto.
- (fold_checksum_tree): Ditto.
- (tree_unary_nonnegative_warnv_p): Ditto.
- (integer_valued_real_unary_p): Ditto.
- (fold_read_from_constant_string): Ditto.
- * gcc-rich-location.cc (maybe_range_label_for_tree_type_mismatch::get_text): Ditto.
- * gimple-expr.cc (useless_type_conversion_p): Ditto.
- (is_gimple_reg): Ditto.
- (is_gimple_asm_val): Ditto.
- (mark_addressable): Ditto.
- * gimple-expr.h (is_gimple_variable): Ditto.
- (virtual_operand_p): Ditto.
- * gimple-ssa-warn-access.cc (pass_waccess::check_dangling_stores): Ditto.
- * gimplify.cc (gimplify_bind_expr): Ditto.
- (gimplify_return_expr): Ditto.
- (gimple_add_padding_init_for_auto_var): Ditto.
- (gimplify_addr_expr): Ditto.
- (omp_add_variable): Ditto.
- (omp_notice_variable): Ditto.
- (omp_get_base_pointer): Ditto.
- (omp_strip_components_and_deref): Ditto.
- (omp_strip_indirections): Ditto.
- (omp_accumulate_sibling_list): Ditto.
- (omp_build_struct_sibling_lists): Ditto.
- (gimplify_adjust_omp_clauses_1): Ditto.
- (gimplify_adjust_omp_clauses): Ditto.
- (gimplify_omp_for): Ditto.
- (goa_lhs_expr_p): Ditto.
- (gimplify_one_sizepos): Ditto.
- * graphite-scop-detection.cc (scop_detection::graphite_can_represent_scev): Ditto.
- * ipa-devirt.cc (odr_types_equivalent_p): Ditto.
- * ipa-prop.cc (ipa_set_jf_constant): Ditto.
- (propagate_controlled_uses): Ditto.
- * ipa-sra.cc (type_prevails_p): Ditto.
- (scan_expr_access): Ditto.
- * optabs-tree.cc (optab_for_tree_code): Ditto.
- * toplev.cc (wrapup_global_declaration_1): Ditto.
- * trans-mem.cc (transaction_invariant_address_p): Ditto.
- * tree-cfg.cc (verify_types_in_gimple_reference): Ditto.
- (verify_gimple_comparison): Ditto.
- (verify_gimple_assign_binary): Ditto.
- (verify_gimple_assign_single): Ditto.
- * tree-complex.cc (get_component_ssa_name): Ditto.
- * tree-emutls.cc (lower_emutls_2): Ditto.
- * tree-inline.cc (copy_tree_body_r): Ditto.
- (estimate_move_cost): Ditto.
- (copy_decl_for_dup_finish): Ditto.
- * tree-nested.cc (convert_nonlocal_omp_clauses): Ditto.
- (note_nonlocal_vla_type): Ditto.
- (convert_local_omp_clauses): Ditto.
- (remap_vla_decls): Ditto.
- (fixup_vla_decls): Ditto.
- * tree-parloops.cc (loop_has_vector_phi_nodes): Ditto.
- * tree-pretty-print.cc (print_declaration): Ditto.
- (print_call_name): Ditto.
- * tree-sra.cc (compare_access_positions): Ditto.
- * tree-ssa-alias.cc (compare_type_sizes): Ditto.
- * tree-ssa-ccp.cc (get_default_value): Ditto.
- * tree-ssa-coalesce.cc (populate_coalesce_list_for_outofssa): Ditto.
- * tree-ssa-dom.cc (reduce_vector_comparison_to_scalar_comparison): Ditto.
- * tree-ssa-forwprop.cc (can_propagate_from): Ditto.
- * tree-ssa-propagate.cc (may_propagate_copy): Ditto.
- * tree-ssa-sccvn.cc (fully_constant_vn_reference_p): Ditto.
- * tree-ssa-sink.cc (statement_sink_location): Ditto.
- * tree-ssa-structalias.cc (type_must_have_pointers): Ditto.
- * tree-ssa-ter.cc (find_replaceable_in_bb): Ditto.
- * tree-ssa-uninit.cc (warn_uninit): Ditto.
- * tree-ssa.cc (maybe_rewrite_mem_ref_base): Ditto.
- (non_rewritable_mem_ref_base): Ditto.
- * tree-streamer-in.cc (lto_input_ts_type_non_common_tree_pointers): Ditto.
- * tree-streamer-out.cc (write_ts_type_non_common_tree_pointers): Ditto.
- * tree-vect-generic.cc (do_binop): Ditto.
- (do_cond): Ditto.
- * tree-vect-stmts.cc (vect_init_vector): Ditto.
- * tree-vector-builder.h (tree_vector_builder::note_representative): Ditto.
- * tree.cc (sign_mask_for): Ditto.
- (verify_type_variant): Ditto.
- (gimple_canonical_types_compatible_p): Ditto.
- (verify_type): Ditto.
- * ubsan.cc (get_ubsan_type_info_for_type): Ditto.
- * var-tracking.cc (prepare_call_arguments): Ditto.
- (vt_add_function_parameters): Ditto.
- * varasm.cc (decode_addr_const): Ditto.
-
-2023-05-18 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
-
- * omp-low.cc (scan_sharing_clauses): Use _P() defines from tree.h.
- (lower_reduction_clauses): Ditto.
- (lower_send_clauses): Ditto.
- (lower_omp_task_reductions): Ditto.
- * omp-oacc-neuter-broadcast.cc (install_var_field): Ditto.
- (worker_single_copy): Ditto.
- * omp-offload.cc (oacc_rewrite_var_decl): Ditto.
- * omp-simd-clone.cc (plausible_type_for_simd_clone): Ditto.
-
-2023-05-18 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
-
- * lto-streamer-in.cc (lto_input_var_decl_ref): Use _P defines from
- tree.h.
- (lto_read_body_or_constructor): Ditto.
- * lto-streamer-out.cc (tree_is_indexable): Ditto.
- (lto_output_var_decl_ref): Ditto.
- (DFS::DFS_write_tree_body): Ditto.
- (wrap_refs): Ditto.
- (write_symbol_extension_info): Ditto.
-
-2023-05-18 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
-
- * config/aarch64/aarch64.cc (aarch64_short_vector_p): Use _P
- defines from tree.h.
- (aarch64_mangle_type): Ditto.
- * config/alpha/alpha.cc (alpha_in_small_data_p): Ditto.
- (alpha_gimplify_va_arg_1): Ditto.
- * config/arc/arc.cc (arc_encode_section_info): Ditto.
- (arc_is_aux_reg_p): Ditto.
- (arc_is_uncached_mem_p): Ditto.
- (arc_handle_aux_attribute): Ditto.
- * config/arm/arm.cc (arm_handle_isr_attribute): Ditto.
- (arm_handle_cmse_nonsecure_call): Ditto.
- (arm_set_default_type_attributes): Ditto.
- (arm_is_segment_info_known): Ditto.
- (arm_mangle_type): Ditto.
- * config/arm/unknown-elf.h (IN_NAMED_SECTION_P): Ditto.
- * config/avr/avr.cc (avr_lookup_function_attribute1): Ditto.
- (avr_decl_absdata_p): Ditto.
- (avr_insert_attributes): Ditto.
- (avr_section_type_flags): Ditto.
- (avr_encode_section_info): Ditto.
- * config/bfin/bfin.cc (bfin_handle_l2_attribute): Ditto.
- * config/bpf/bpf.cc (bpf_core_compute): Ditto.
- * config/c6x/c6x.cc (c6x_in_small_data_p): Ditto.
- * config/csky/csky.cc (csky_handle_isr_attribute): Ditto.
- (csky_mangle_type): Ditto.
- * config/darwin-c.cc (darwin_pragma_unused): Ditto.
- * config/darwin.cc (is_objc_metadata): Ditto.
- * config/epiphany/epiphany.cc (epiphany_function_ok_for_sibcall): Ditto.
- * config/epiphany/epiphany.h (ROUND_TYPE_ALIGN): Ditto.
- * config/frv/frv.cc (frv_emit_movsi): Ditto.
- * config/gcn/gcn-tree.cc (gcn_lockless_update): Ditto.
- * config/gcn/gcn.cc (gcn_asm_output_symbol_ref): Ditto.
- * config/h8300/h8300.cc (h8300_encode_section_info): Ditto.
- * config/i386/i386-expand.cc: Ditto.
- * config/i386/i386.cc (type_natural_mode): Ditto.
- (ix86_function_arg): Ditto.
- (ix86_data_alignment): Ditto.
- (ix86_local_alignment): Ditto.
- (ix86_simd_clone_compute_vecsize_and_simdlen): Ditto.
- * config/i386/winnt-cxx.cc (i386_pe_type_dllimport_p): Ditto.
- (i386_pe_type_dllexport_p): Ditto.
- (i386_pe_adjust_class_at_definition): Ditto.
- * config/i386/winnt.cc (i386_pe_determine_dllimport_p): Ditto.
- (i386_pe_binds_local_p): Ditto.
- (i386_pe_section_type_flags): Ditto.
- * config/ia64/ia64.cc (ia64_encode_section_info): Ditto.
- (ia64_gimplify_va_arg): Ditto.
- (ia64_in_small_data_p): Ditto.
- * config/iq2000/iq2000.cc (iq2000_function_arg): Ditto.
- * config/lm32/lm32.cc (lm32_in_small_data_p): Ditto.
- * config/loongarch/loongarch.cc (loongarch_handle_model_attribute): Ditto.
- * config/m32c/m32c.cc (m32c_insert_attributes): Ditto.
- * config/mcore/mcore.cc (mcore_mark_dllimport): Ditto.
- (mcore_encode_section_info): Ditto.
- * config/microblaze/microblaze.cc (microblaze_elf_in_small_data_p): Ditto.
- * config/mips/mips.cc (mips_output_aligned_decl_common): Ditto.
- * config/mmix/mmix.cc (mmix_encode_section_info): Ditto.
- * config/nvptx/nvptx.cc (nvptx_encode_section_info): Ditto.
- (pass_in_memory): Ditto.
- (nvptx_generate_vector_shuffle): Ditto.
- (nvptx_lockless_update): Ditto.
- * config/pa/pa.cc (pa_function_arg_padding): Ditto.
- (pa_function_value): Ditto.
- (pa_function_arg): Ditto.
- * config/pa/pa.h (IN_NAMED_SECTION_P): Ditto.
- (TEXT_SPACE_P): Ditto.
- * config/pa/som.h (MAKE_DECL_ONE_ONLY): Ditto.
- * config/pdp11/pdp11.cc (pdp11_return_in_memory): Ditto.
- * config/riscv/riscv.cc (riscv_in_small_data_p): Ditto.
- (riscv_mangle_type): Ditto.
- * config/rl78/rl78.cc (rl78_insert_attributes): Ditto.
- (rl78_addsi3_internal): Ditto.
- * config/rs6000/aix.h (ROUND_TYPE_ALIGN): Ditto.
- * config/rs6000/darwin.h (ROUND_TYPE_ALIGN): Ditto.
- * config/rs6000/freebsd64.h (ROUND_TYPE_ALIGN): Ditto.
- * config/rs6000/linux64.h (ROUND_TYPE_ALIGN): Ditto.
- * config/rs6000/rs6000-call.cc (rs6000_function_arg_boundary): Ditto.
- (rs6000_function_arg_advance_1): Ditto.
- (rs6000_function_arg): Ditto.
- (rs6000_pass_by_reference): Ditto.
- * config/rs6000/rs6000-logue.cc (rs6000_function_ok_for_sibcall): Ditto.
- * config/rs6000/rs6000.cc (rs6000_data_alignment): Ditto.
- (rs6000_set_default_type_attributes): Ditto.
- (rs6000_elf_in_small_data_p): Ditto.
- (IN_NAMED_SECTION): Ditto.
- (rs6000_xcoff_encode_section_info): Ditto.
- (rs6000_function_value): Ditto.
- (invalid_arg_for_unprototyped_fn): Ditto.
- * config/s390/s390-c.cc (s390_fn_types_compatible): Ditto.
- (s390_vec_n_elem): Ditto.
- * config/s390/s390.cc (s390_check_type_for_vector_abi): Ditto.
- (s390_function_arg_integer): Ditto.
- (s390_return_in_memory): Ditto.
- (s390_encode_section_info): Ditto.
- * config/sh/sh.cc (sh_gimplify_va_arg_expr): Ditto.
- (sh_function_value): Ditto.
- * config/sol2.cc (solaris_insert_attributes): Ditto.
- * config/sparc/sparc.cc (function_arg_slotno): Ditto.
- * config/sparc/sparc.h (ROUND_TYPE_ALIGN): Ditto.
- * config/stormy16/stormy16.cc (xstormy16_encode_section_info): Ditto.
- (xstormy16_handle_below100_attribute): Ditto.
- * config/v850/v850.cc (v850_encode_section_info): Ditto.
- (v850_insert_attributes): Ditto.
- * config/visium/visium.cc (visium_pass_by_reference): Ditto.
- (visium_return_in_memory): Ditto.
- * config/xtensa/xtensa.cc (xtensa_multibss_section_type_flags): Ditto.
-
-2023-05-18 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_vecop_qihi_partial): New.
- (ix86_expand_vecop_qihi): Add op2vec bool variable.
- Do not set REG_EQUAL note.
- * config/i386/i386-protos.h (ix86_expand_vecop_qihi_partial):
- Add prototype.
- * config/i386/i386.cc (ix86_multiplication_cost): Handle
- V4QImode and V8QImode.
- * config/i386/mmx.md (mulv8qi3): New expander.
- (mulv4qi3): Ditto.
- * config/i386/sse.md (mulv8qi3): Remove.
-
-2023-05-18 Georg-Johann Lay <avr@gjlay.de>
-
- * config/avr/gen-avr-mmcu-specs.cc: Remove stale */ after // comment.
-
-2023-05-18 Jonathan Wakely <jwakely@redhat.com>
-
- PR bootstrap/105831
- * config.gcc: Use = operator instead of ==.
-
-2023-05-18 Michael Bäuerle <micha@NetBSD.org>
-
- PR bootstrap/105831
- * config/nvptx/gen-opt.sh: Use = operator instead of ==.
- * configure.ac: Likewise.
- * configure: Regenerate.
-
-2023-05-18 Stam Markianos-Wright <stam.markianos-wright@arm.com>
-
- * config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types.
- (__ARM_mve_coerce1): Remove.
- (__ARM_mve_coerce2): Remove.
- (__ARM_mve_coerce3): Remove.
- (__ARM_mve_coerce_i_scalar): New.
- (__ARM_mve_coerce_s8_ptr): New.
- (__ARM_mve_coerce_u8_ptr): New.
- (__ARM_mve_coerce_s16_ptr): New.
- (__ARM_mve_coerce_u16_ptr): New.
- (__ARM_mve_coerce_s32_ptr): New.
- (__ARM_mve_coerce_u32_ptr): New.
- (__ARM_mve_coerce_s64_ptr): New.
- (__ARM_mve_coerce_u64_ptr): New.
- (__ARM_mve_coerce_f_scalar): New.
- (__ARM_mve_coerce_f16_ptr): New.
- (__ARM_mve_coerce_f32_ptr): New.
- (__arm_vst4q): Change _coerce_ overloads.
- (__arm_vbicq): Change _coerce_ overloads.
- (__arm_vld1q): Change _coerce_ overloads.
- (__arm_vld1q_z): Change _coerce_ overloads.
- (__arm_vld2q): Change _coerce_ overloads.
- (__arm_vld4q): Change _coerce_ overloads.
- (__arm_vldrhq_gather_offset): Change _coerce_ overloads.
- (__arm_vldrhq_gather_offset_z): Change _coerce_ overloads.
- (__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads.
- (__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads.
- (__arm_vldrwq_gather_offset): Change _coerce_ overloads.
- (__arm_vldrwq_gather_offset_z): Change _coerce_ overloads.
- (__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads.
- (__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads.
- (__arm_vst1q_p): Change _coerce_ overloads.
- (__arm_vst2q): Change _coerce_ overloads.
- (__arm_vst1q): Change _coerce_ overloads.
- (__arm_vstrhq): Change _coerce_ overloads.
- (__arm_vstrhq_p): Change _coerce_ overloads.
- (__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads.
- (__arm_vstrhq_scatter_offset): Change _coerce_ overloads.
- (__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads.
- (__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads.
- (__arm_vstrwq_p): Change _coerce_ overloads.
- (__arm_vstrwq): Change _coerce_ overloads.
- (__arm_vstrwq_scatter_offset): Change _coerce_ overloads.
- (__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads.
- (__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads.
- (__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads.
- (__arm_vsetq_lane): Change _coerce_ overloads.
- (__arm_vldrbq_gather_offset): Change _coerce_ overloads.
- (__arm_vdwdupq_x_u8): Change _coerce_ overloads.
- (__arm_vdwdupq_x_u16): Change _coerce_ overloads.
- (__arm_vdwdupq_x_u32): Change _coerce_ overloads.
- (__arm_viwdupq_x_u8): Change _coerce_ overloads.
- (__arm_viwdupq_x_u16): Change _coerce_ overloads.
- (__arm_viwdupq_x_u32): Change _coerce_ overloads.
- (__arm_vidupq_x_u8): Change _coerce_ overloads.
- (__arm_vddupq_x_u8): Change _coerce_ overloads.
- (__arm_vidupq_x_u16): Change _coerce_ overloads.
- (__arm_vddupq_x_u16): Change _coerce_ overloads.
- (__arm_vidupq_x_u32): Change _coerce_ overloads.
- (__arm_vddupq_x_u32): Change _coerce_ overloads.
- (__arm_vldrdq_gather_offset): Change _coerce_ overloads.
- (__arm_vldrdq_gather_offset_z): Change _coerce_ overloads.
- (__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads.
- (__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads.
- (__arm_vldrbq_gather_offset_z): Change _coerce_ overloads.
- (__arm_vidupq_u16): Change _coerce_ overloads.
- (__arm_vidupq_u32): Change _coerce_ overloads.
- (__arm_vidupq_u8): Change _coerce_ overloads.
- (__arm_vddupq_u16): Change _coerce_ overloads.
- (__arm_vddupq_u32): Change _coerce_ overloads.
- (__arm_vddupq_u8): Change _coerce_ overloads.
- (__arm_viwdupq_m): Change _coerce_ overloads.
- (__arm_viwdupq_u16): Change _coerce_ overloads.
- (__arm_viwdupq_u32): Change _coerce_ overloads.
- (__arm_viwdupq_u8): Change _coerce_ overloads.
- (__arm_vdwdupq_m): Change _coerce_ overloads.
- (__arm_vdwdupq_u16): Change _coerce_ overloads.
- (__arm_vdwdupq_u32): Change _coerce_ overloads.
- (__arm_vdwdupq_u8): Change _coerce_ overloads.
- (__arm_vstrbq): Change _coerce_ overloads.
- (__arm_vstrbq_p): Change _coerce_ overloads.
- (__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads.
- (__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads.
- (__arm_vstrdq_scatter_offset): Change _coerce_ overloads.
- (__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads.
- (__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads.
-
-2023-05-18 Stam Markianos-Wright <stam.markianos-wright@arm.com>
-
- * config/arm/arm_mve.h (__arm_vbicq): Change coerce on
- scalar constant.
-
-2023-05-18 Stam Markianos-Wright <stam.markianos-wright@arm.com>
-
- * config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
- (__arm_vadcq_u32): Likewise.
- (__arm_vadcq_m_s32): Likewise.
- (__arm_vadcq_m_u32): Likewise.
- (__arm_vsbcq_s32): Likewise.
- (__arm_vsbcq_u32): Likewise.
- (__arm_vsbcq_m_s32): Likewise.
- (__arm_vsbcq_m_u32): Likewise.
- * config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile.
-
-2023-05-18 Andrea Corallo <andrea.corallo@arm.com>
-
- * config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrev64q_f<mode>)
- (mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf)
- (mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_<supf><mode>)
- (mve_vrev64q_<supf><mode>, mve_vcvtq_from_f_<supf><mode>)
- (mve_vmovltq_<supf><mode>, mve_vmovlbq_<supf><mode>)
- (mve_vcvtpq_<supf><mode>, mve_vcvtnq_<supf><mode>)
- (mve_vcvtmq_<supf><mode>, mve_vcvtaq_<supf><mode>)
- (mve_vmvnq_n_<supf><mode>, mve_vrev16q_<supf>v16qi)
- (mve_vctp<MVE_vctp>q<MVE_vpred>, mve_vbrsrq_n_f<mode>)
- (mve_vbrsrq_n_<supf><mode>, mve_vandq_f<mode>, mve_vbicq_f<mode>)
- (mve_vctp<MVE_vctp>q_m<MVE_vpred>, mve_vcvtbq_f16_f32v8hf)
- (mve_vcvttq_f16_f32v8hf, mve_veorq_f<mode>)
- (mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
- (mve_vmlsldavxq_s<mode>, mve_vornq_f<mode>, mve_vorrq_f<mode>)
- (mve_vrmlaldavhxq_sv4si, mve_vcvtq_m_to_f_<supf><mode>)
- (mve_vshlcq_<supf><mode>, mve_vmvnq_m_<supf><mode>)
- (mve_vpselq_<supf><mode>, mve_vcvtbq_m_f16_f32v8hf)
- (mve_vcvtbq_m_f32_f16v4sf, mve_vcvttq_m_f16_f32v8hf)
- (mve_vcvttq_m_f32_f16v4sf, mve_vmlaldavq_p_<supf><mode>)
- (mve_vmlsldavaq_s<mode>, mve_vmlsldavaxq_s<mode>)
- (mve_vmlsldavq_p_s<mode>, mve_vmlsldavxq_p_s<mode>)
- (mve_vmvnq_m_n_<supf><mode>, mve_vorrq_m_n_<supf><mode>)
- (mve_vpselq_f<mode>, mve_vrev32q_m_fv8hf)
- (mve_vrev32q_m_<supf><mode>, mve_vrev64q_m_f<mode>)
- (mve_vrmlaldavhaxq_sv4si, mve_vrmlaldavhxq_p_sv4si)
- (mve_vrmlsldavhaxq_sv4si, mve_vrmlsldavhq_p_sv4si)
- (mve_vrmlsldavhxq_p_sv4si, mve_vrev16q_m_<supf>v16qi)
- (mve_vrmlaldavhq_p_<supf>v4si, mve_vrmlsldavhaq_sv4si)
- (mve_vandq_m_<supf><mode>, mve_vbicq_m_<supf><mode>)
- (mve_veorq_m_<supf><mode>, mve_vornq_m_<supf><mode>)
- (mve_vorrq_m_<supf><mode>, mve_vandq_m_f<mode>)
- (mve_vbicq_m_f<mode>, mve_veorq_m_f<mode>, mve_vornq_m_f<mode>)
- (mve_vorrq_m_f<mode>)
- (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn)
- (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn)
- (mve_vstrdq_scatter_base_wb_p_<supf>v2di) : Fix spacing and
- capitalization in the emitted asm.
-
-2023-05-18 Andrea Corallo <andrea.corallo@arm.com>
-
- * config/arm/constraints.md (mve_vldrd_immediate): Move it to
- predicates.md.
- (Ri): Move constraint definition from predicates.md.
- (Rl): Define new constraint.
- * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Add
- missing constraint.
- (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
- for op 1, use mve_vstrw_immediate predicate and Rl constraint for
- op 2. Fix asm output spacing.
- (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing constraint.
- * config/arm/predicates.md (Ri) Move constraint to constraints.md
- (mve_vldrd_immediate): Move it from
- constraints.md.
- (mve_vstrw_immediate): New predicate.
-
-2023-05-18 Pan Li <pan2.li@intel.com>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- Kito Cheng <kito.cheng@sifive.com>
- Richard Biener <rguenther@suse.de>
- Richard Sandiford <richard.sandiford@arm.com>
-
- * combine.cc (struct reg_stat_type): Extend machine_mode to 16 bits.
- * cse.cc (struct qty_table_elem): Extend machine_mode to 16 bits
- (struct table_elt): Extend machine_mode to 16 bits.
- (struct set): Ditto.
- * genmodes.cc (emit_mode_wider): Extend type from char to short.
- (emit_mode_complex): Ditto.
- (emit_mode_inner): Ditto.
- (emit_class_narrowest_mode): Ditto.
- * genopinit.cc (main): Extend the machine_mode limit.
- * ira-int.h (struct ira_allocno): Extend machine_mode to 16 bits and
- re-ordered the struct fields for padding.
- * machmode.h (MACHINE_MODE_BITSIZE): New macro.
- (GET_MODE_2XWIDER_MODE): Extend type from char to short.
- (get_mode_alignment): Extend type from char to short.
- * ree.cc (struct ext_modified): Extend machine_mode to 16 bits and
- removed the ATTRIBUTE_PACKED.
- * rtl-ssa/accesses.h: Extend machine_mode to 16 bits, narrow
- * rtl-ssa/internals.inl (rtl_ssa::access_info): Adjust the assignment.
- m_kind to 2 bits and remove m_spare.
- * rtl.h (RTX_CODE_BITSIZE): New macro.
- (struct rtx_def): Swap both the bit size and location between the
- rtx_code and the machine_mode.
- (subreg_shape::unique_id): Extend the machine_mode limit.
- * rtlanal.h: Extend machine_mode to 16 bits.
- * tree-core.h (struct tree_type_common): Extend machine_mode to 16
- bits and re-ordered the struct fields for padding.
- (struct tree_decl_common): Extend machine_mode to 16 bits.
-
-2023-05-17 Jin Ma <jinma@linux.alibaba.com>
-
- * genrecog.cc (print_nonbool_test): Fix type error of
- switch (SUBREG_BYTE (op))'.
-
-2023-05-17 Jin Ma <jinma@linux.alibaba.com>
-
- * common/config/riscv/riscv-common.cc: Remove
- trailing spaces on lines.
- * config/riscv/riscv.cc (riscv_legitimize_move): Likewise.
- * config/riscv/riscv.h (enum reg_class): Likewise.
- * config/riscv/riscv.md: Likewise.
-
-2023-05-17 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa.md (clear_cache): New.
-
-2023-05-17 Arsen Arsenović <arsen@aarsen.me>
-
- * doc/extend.texi (C++ Concepts) <forall>: Remove extraneous
- parenthesis. Fix misnamed index entry.
- <concept>: Fix misnamed index entry.
-
-2023-05-17 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * config/riscv/riscv.md (*<optab><GPR:mode>3_mask): New pattern,
- combined from ...
- (*<optab>si3_mask, *<optab>di3_mask): Here.
- (*<optab>si3_mask_1, *<optab>di3_mask_1): And here.
- * config/riscv/bitmanip.md (*<bitmanip_optab><GPR:mode>3_mask): New
- pattern.
- (*<bitmanip_optab>si3_sext_mask): Likewise.
- * config/riscv/iterators.md (shiftm1): Use const_si_mask_operand
- and const_di_mask_operand.
- (bitmanip_rotate): New iterator.
- (bitmanip_optab): Add rotates.
- * config/riscv/predicates.md (const_si_mask_operand): Renamed
- from const31_operand. Generalize to handle more mask constants.
- (const_di_mask_operand): Similarly.
-
-2023-05-17 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/109884
- * config/i386/i386-builtin-types.def (FLOAT128): Use
- float128t_type_node rather than float128_type_node.
-
-2023-05-17 Alexander Monakov <amonakov@ispras.ru>
-
- * tree-ssa-math-opts.cc (convert_mult_to_fma): Enable only for
- FP_CONTRACT_FAST (no functional change).
-
-2023-05-17 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.cc (ix86_multiplication_cost): Correct
- calcuation of integer vector mode costs to reflect generated
- instruction sequences of different integer vector modes and
- different target ABIs.
-
-2023-05-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-opts.h (enum riscv_entity): New enum.
- * config/riscv/riscv.cc (riscv_emit_mode_set): New function.
- (riscv_mode_needed): Ditto.
- (riscv_mode_after): Ditto.
- (riscv_mode_entry): Ditto.
- (riscv_mode_exit): Ditto.
- (riscv_mode_priority): Ditto.
- (TARGET_MODE_EMIT): New target hook.
- (TARGET_MODE_NEEDED): Ditto.
- (TARGET_MODE_AFTER): Ditto.
- (TARGET_MODE_ENTRY): Ditto.
- (TARGET_MODE_EXIT): Ditto.
- (TARGET_MODE_PRIORITY): Ditto.
- * config/riscv/riscv.h (OPTIMIZE_MODE_SWITCHING): Ditto.
- (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
- * config/riscv/riscv.md: Add csrwvxrm.
- * config/riscv/vector.md (rnu,rne,rdn,rod,none): New attribute.
- (vxrmsi): New pattern.
-
-2023-05-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Introduce rounding mode.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
- (struct narrow_alu_def): Ditto.
- * config/riscv/riscv-vector-builtins.cc (function_builder::apply_predication): Ditto.
- (function_expander::use_exact_insn): Ditto.
- * config/riscv/riscv-vector-builtins.h (function_checker::arg_num): New function.
- (function_base::has_rounding_mode_operand_p): New function.
-
-2023-05-17 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-forwprop.cc (simplify_builtin_call): Check
- against 0 instead of calling integer_zerop.
-
-2023-05-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins.cc (register_vxrm): New function.
- (DEF_RVV_VXRM_ENUM): New macro.
- (handle_pragma_vector): Add vxrm enum register.
- * config/riscv/riscv-vector-builtins.def (DEF_RVV_VXRM_ENUM): New macro.
- (RNU): Ditto.
- (RNE): Ditto.
- (RDN): Ditto.
- (ROD): Ditto.
-
-2023-05-17 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (Value_Range::operator=): New.
-
-2023-05-17 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (vrange::operator=): Add a stub to copy
- unsupported ranges.
- * value-range.h (is_a <unsupported_range>): New.
- (Value_Range::operator=): Support copying unsupported ranges.
-
-2023-05-17 Aldy Hernandez <aldyh@redhat.com>
-
- * data-streamer-in.cc (streamer_read_real_value): New.
- (streamer_read_value_range): New.
- * data-streamer-out.cc (streamer_write_real_value): New.
- (streamer_write_vrange): New.
- * data-streamer.h (streamer_write_vrange): New.
- (streamer_read_value_range): New.
-
-2023-05-17 Jonathan Wakely <jwakely@redhat.com>
-
- PR c++/109532
- * doc/invoke.texi (Code Gen Options): Note that -fshort-enums
- is ignored for a fixed underlying type.
- (C++ Dialect Options): Likewise for -fstrict-enums.
-
-2023-05-17 Tobias Burnus <tobias@codesourcery.com>
-
- * gimplify.cc (gimplify_scan_omp_clauses): Remove Fortran
- special case.
-
-2023-05-17 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.cc (TARGET_ATOMIC_ALIGN_FOR_MODE):
- New.
- (s390_atomic_align_for_mode): New.
-
-2023-05-17 Jakub Jelinek <jakub@redhat.com>
-
- * wide-int.cc (wi::from_array): Add missing closing paren in function
- comment.
+2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
+ Register these builtins with a pointer to uint64_t rather than unsigned
+ DI mode.
+
+2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
+
+ PR target/113615
+ * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
+ Conditionalize on '!TARGET_RDNA2_PLUS'.
+ * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
+ (gcn_expand_reduc_scalar):
+ 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
+
+2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
+
+ * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
+ '__gfx90a__' target CPU definition. Add some safeguards for the future.
+
+2024-02-19 Richard Biener <rguenther@suse.de>
+
+ PR rtl-optimization/54052
+ * rtl-ssa/blocks.cc (function_info::place_phis): Filter
+ local defs by LR_OUT.
+
+2024-02-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/113967
+ * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
+ in condition that @rpos is multiple of vector element size.
+
+2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/113696
+ * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
+ Suppress vsetvl fusion.
+
+2024-02-18 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/113912
+ * config/i386/i386.cc (ix86_can_use_push2pop2): New.
+ (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
+ (ix86_emit_save_regs): Don't generate push2 if
+ ix86_can_use_push2pop2 return false.
+ (ix86_expand_epilogue): Don't generate pop2 if
+ ix86_can_use_push2pop2 return false.
+
+2024-02-18 Georg-Johann Lay <avr@gjlay.de>
+
+ * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
+ Note on complete device support.
+
+2024-02-18 Georg-Johann Lay <avr@gjlay.de>
+
+ * doc/extend.texi (AVR Function Attributes): Fuse description
+ of "signal" and "interrupt" attribute. Link pseudo instruction.
+
+2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
+ symbol type conversions.
+ (__cacop_d): Likewise.
+ (__cpucfg): Likewise.
+ (__asrtle_d): Likewise.
+ (__asrtgt_d): Likewise.
+ (__lddir_d): Likewise.
+ (__ldpte_d): Likewise.
+ (__crc_w_b_w): Likewise.
+ (__crc_w_h_w): Likewise.
+ (__crc_w_w_w): Likewise.
+ (__crc_w_d_w): Likewise.
+ (__crcc_w_b_w): Likewise.
+ (__crcc_w_h_w): Likewise.
+ (__crcc_w_w_w): Likewise.
+ (__crcc_w_d_w): Likewise.
+ (__csrrd_w): Likewise.
+ (__csrwr_w): Likewise.
+ (__csrxchg_w): Likewise.
+ (__csrrd_d): Likewise.
+ (__csrwr_d): Likewise.
+ (__csrxchg_d): Likewise.
+ (__iocsrrd_b): Likewise.
+ (__iocsrrd_h): Likewise.
+ (__iocsrrd_w): Likewise.
+ (__iocsrrd_d): Likewise.
+ (__iocsrwr_b): Likewise.
+ (__iocsrwr_h): Likewise.
+ (__iocsrwr_w): Likewise.
+ (__iocsrwr_d): Likewise.
+ (__frecipe_s): Likewise.
+ (__frecipe_d): Likewise.
+ (__frsqrte_s): Likewise.
+ (__frsqrte_d): Likewise.
+
+2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
+ function return value type to unsigned short.
+
+2024-02-16 Edwin Lu <ewlu@rivosinc.com>
-2023-05-17 Kewen Lin <linkw@linux.ibm.com>
-
- * tree-vect-loop.cc (vect_analyze_loop_1): Don't retry analysis with
- suggested unroll factor once the previous analysis fails.
-
-2023-05-17 Pan Li <pan2.li@intel.com>
-
- * config/riscv/genrvv-type-indexer.cc (BOOL_SIZE_LIST): New
- macro.
- (main): Add bool1 to the type indexer.
- * config/riscv/riscv-vector-builtins-functions.def
- (vreinterpret): Register vbool1 interpret function.
- * config/riscv/riscv-vector-builtins-types.def
- (DEF_RVV_BOOL1_INTERPRET_OPS): New macro.
- (vint8m1_t): Add the type to bool1_interpret_ops.
- (vint16m1_t): Ditto.
- (vint32m1_t): Ditto.
- (vint64m1_t): Ditto.
- (vuint8m1_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint64m1_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc
- (DEF_RVV_BOOL1_INTERPRET_OPS): New macro.
- (required_extensions_p): Add bool1 interpret case.
- * config/riscv/riscv-vector-builtins.def
- (bool1_interpret): Add bool1 interpret to base type.
- * config/riscv/vector.md (@vreinterpret<mode>): Add new expand
- with VB dest for vreinterpret.
-
-2023-05-17 Jiufu Guo <guojiufu@linux.ibm.com>
-
- PR target/106708
- * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Support building
- constants through "lis; xoris".
-
-2023-05-16 Ajit Kumar Agarwal <aagarwa1@linux.ibm.com>
-
- * common/config/rs6000/rs6000-common.cc: Add REE pass as a
- default rs6000 target pass for O2 and above.
- * doc/invoke.texi: Document -free
-
-2023-05-16 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc (riscv_compute_multilib):
- Fix wrong select_kind...
-
-2023-05-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-protos.h (s390_expand_setmem): Change
- function signature.
- * config/s390/s390.cc (s390_expand_setmem): For memset's less
- than or equal to 256 byte do not perform a libc call.
- * config/s390/s390.md: Change expander into a version which
- takes 8 operands.
-
-2023-05-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-protos.h (s390_expand_movmem): New.
- * config/s390/s390.cc (s390_expand_movmem): New.
- * config/s390/s390.md (movmem<mode>): New.
- (*mvcrl): New.
- (mvcrl): New.
-
-2023-05-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-protos.h (s390_expand_cpymem): Change
- function signature.
- * config/s390/s390.cc (s390_expand_cpymem): For memcpy's less
- than or equal to 256 byte do not perform a libc call.
- (s390_expand_insv): Adapt new function signature of
- s390_expand_cpymem.
- * config/s390/s390.md: Change expander into a version which
- takes 8 operands.
-
-2023-05-16 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109424
- * match.pd: Add patterns for min/max of zero_one_valued
- values to `&`/`|`.
-
-2023-05-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum frm_field_enum): New enum.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_ternop_insn): Add default rounding mode.
- (function_expander::use_widen_ternop_insn): Ditto.
- * config/riscv/riscv.cc (riscv_hard_regno_nregs): Add FRM REGNUM.
- (riscv_hard_regno_mode_ok): Ditto.
- (riscv_conditional_register_usage): Ditto.
- * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto.
- (FRM_REG_P): Ditto.
- (RISCV_DWARF_FRM): Ditto.
- * config/riscv/riscv.md: Ditto.
- * config/riscv/vector-iterators.md: split no frm and has frm operations.
- * config/riscv/vector.md (@pred_<optab><mode>_scalar): New pattern.
- (@pred_<optab><mode>): Ditto.
-
-2023-05-15 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/109695
- * value-range.cc (irange::operator=): Resize range.
- (irange::union_): Same.
- (irange::intersect): Same.
- (irange::invert): Same.
- (int_range_max): Default to 3 sub-ranges and resize as needed.
- * value-range.h (irange::maybe_resize): New.
- (~int_range): New.
- (int_range::int_range): Adjust for resizing.
- (int_range::operator=): Same.
-
-2023-05-15 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-cp.cc (ipcp_vr_lattice::meet_with_1): Avoid unnecessary
- range copying
- * value-range.cc (irange::union_nonzero_bits): Return TRUE only
- when range changed.
-
-2023-05-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum vxrm_field_enum): New enum.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_exact_insn): Add default rounding mode operand.
- * config/riscv/riscv.cc (riscv_hard_regno_nregs): Add VXRM_REGNUM.
- (riscv_hard_regno_mode_ok): Ditto.
- (riscv_conditional_register_usage): Ditto.
- * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto.
- (VXRM_REG_P): Ditto.
- (RISCV_DWARF_VXRM): Ditto.
- * config/riscv/riscv.md: Ditto.
- * config/riscv/vector.md: Ditto
-
-2023-05-15 Pan Li <pan2.li@intel.com>
-
- * optabs.cc (maybe_gen_insn): Add case to generate instruction
- that has 11 operands.
-
-2023-05-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_rtx_costs, NEG case): Add costing
- logic for vector modes.
-
-2023-05-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_cm<optab><mode>): Rename to...
- (aarch64_cm<optab><mode><vczle><vczbe>): ... This.
- (aarch64_cmtst<mode>): Rename to...
- (aarch64_cmtst<mode><vczle><vczbe>): ... This.
- (*aarch64_cmtst_same_<mode>): Rename to...
- (*aarch64_cmtst_same_<mode><vczle><vczbe>): ... This.
- (*aarch64_cmtstdi): Rename to...
- (*aarch64_cmtstdi<vczle><vczbe>): ... This.
- (aarch64_fac<optab><mode>): Rename to...
- (aarch64_fac<optab><mode><vczle><vczbe>): ... This.
-
-2023-05-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>): Rename to...
- (aarch64_s<optab><mode><vczle><vczbe>): ... This.
-
-2023-05-15 Pan Li <pan2.li@intel.com>
- Juzhe-Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-v.cc (const_vlmax_p): New function for
- deciding the mode is constant or not.
- (set_len_and_policy): Optimize VLS-VLMAX code gen to vsetivli.
-
-2023-05-15 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109848
- * tree-ssa-forwprop.cc (pass_forwprop::execute): Put the
- TARGET_MEM_REF address preparation before the store, not
- before the CTOR.
-
-2023-05-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc
- (riscv_vectorize_preferred_vector_alignment): New function.
- (TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT): New target hook.
-
-2023-05-14 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109829
- * match.pd: Add pattern for `signbit(x) !=/== 0 ? x : -x`.
-
-2023-05-14 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/109807
- * config/i386/i386.cc: Revert the 2023-05-11 change.
- (ix86_widen_mult_cost): Return high value instead of
- ICEing for unsupported modes.
-
-2023-05-14 Ard Biesheuvel <ardb@kernel.org>
-
- * config/i386/i386.cc (x86_function_profiler): Take
- ix86_direct_extern_access into account when generating calls
- to __fentry__()
-
-2023-05-14 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-vector-builtins.cc (required_extensions_p):
- Refactor the or pattern to switch cases.
-
-2023-05-13 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- * config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback): Rename
- aarch64_expand_vector_init to this, and remove interleaving case.
- Recursively call aarch64_expand_vector_init_fallback, instead of
- aarch64_expand_vector_init.
- (aarch64_unzip_vector_init): New function.
- (aarch64_expand_vector_init): Likewise.
-
-2023-05-13 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns):
- Pull out function call from the gcc_assert.
-
-2023-05-13 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-vsetvl.cc (vlmul_to_str): New.
- (policy_to_str): New.
- (vector_insn_info::dump): Use vlmul_to_str and policy_to_str.
-
-2023-05-13 Andrew Pinski <apinski@marvell.com>
+ * doc/sourcebuild.texi: add scan-assembler-bound
+
+2024-02-16 Jason Merrill <jason@redhat.com>
- PR tree-optimization/109834
- * match.pd (popcount(bswap(x))->popcount(x)): Fix up unsigned type checking.
- (popcount(rotate(x,y))->popcount(x)): Likewise.
-
-2023-05-12 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also
- reject ymm instructions for TARGET_PREFER_AVX128. Use generic
- gen_extend_insn to generate zero/sign extension instructions.
- Fix comments.
- (ix86_expand_vecop_qihi): Initialize interleave functions
- for MULT code only. Fix comments.
-
-2023-05-12 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/109797
- * config/i386/mmx.md (mulv2si3): Remove expander.
- (mulv2si3): Rename insn pattern from *mulv2si.
-
-2023-05-12 Tobias Burnus <tobias@codesourcery.com>
-
- PR libstdc++/109816
- * lto-cgraph.cc (output_symtab): Guard lto_output_toplevel_asms by
- '!lto_stream_offload_p'.
-
-2023-05-12 Kito Cheng <kito.cheng@sifive.com>
- Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/109743
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vsetvl_at_end): New.
- (local_avl_compatible_p): New.
- (pass_vsetvl::local_eliminate_vsetvl_insn): Enhance local optimizations
- for LCM, rewrite as a backward algorithm.
- (pass_vsetvl::cleanup_insns): Use new local_eliminate_vsetvl_insn
- interface, handle a BB at once.
-
-2023-05-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/64731
- * tree-ssa-forwprop.cc (pass_forwprop::execute): Also
- handle TARGET_MEM_REF destinations of stores from vector
- CTORs.
-
-2023-05-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109791
- * match.pd (minus (convert ADDR_EXPR@0) (convert (pointer_plus @1 @2))):
- New pattern.
- (minus (convert (pointer_plus @1 @2)) (convert ADDR_EXPR@0)):
- Likewise.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vsriq): New.
- * config/arm/arm-mve-builtins-base.def (vsriq): New.
- * config/arm/arm-mve-builtins-base.h (vsriq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vsriq.
- * config/arm/arm_mve.h (vsriq): Remove.
- (vsriq_m): Remove.
- (vsriq_n_u8): Remove.
- (vsriq_n_s8): Remove.
- (vsriq_n_u16): Remove.
- (vsriq_n_s16): Remove.
- (vsriq_n_u32): Remove.
- (vsriq_n_s32): Remove.
- (vsriq_m_n_s8): Remove.
- (vsriq_m_n_u8): Remove.
- (vsriq_m_n_s16): Remove.
- (vsriq_m_n_u16): Remove.
- (vsriq_m_n_s32): Remove.
- (vsriq_m_n_u32): Remove.
- (__arm_vsriq_n_u8): Remove.
- (__arm_vsriq_n_s8): Remove.
- (__arm_vsriq_n_u16): Remove.
- (__arm_vsriq_n_s16): Remove.
- (__arm_vsriq_n_u32): Remove.
- (__arm_vsriq_n_s32): Remove.
- (__arm_vsriq_m_n_s8): Remove.
- (__arm_vsriq_m_n_u8): Remove.
- (__arm_vsriq_m_n_s16): Remove.
- (__arm_vsriq_m_n_u16): Remove.
- (__arm_vsriq_m_n_s32): Remove.
- (__arm_vsriq_m_n_u32): Remove.
- (__arm_vsriq): Remove.
- (__arm_vsriq_m): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vsri.
- * config/arm/mve.md (mve_vsriq_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_n_<supf><mode>): .,. this.
- (mve_vsriq_m_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (ternary_rshift): New.
- * config/arm/arm-mve-builtins-shapes.h (ternary_rshift): New.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vsliq): New.
- * config/arm/arm-mve-builtins-base.def (vsliq): New.
- * config/arm/arm-mve-builtins-base.h (vsliq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vsliq.
- * config/arm/arm_mve.h (vsliq): Remove.
- (vsliq_m): Remove.
- (vsliq_n_u8): Remove.
- (vsliq_n_s8): Remove.
- (vsliq_n_u16): Remove.
- (vsliq_n_s16): Remove.
- (vsliq_n_u32): Remove.
- (vsliq_n_s32): Remove.
- (vsliq_m_n_s8): Remove.
- (vsliq_m_n_s32): Remove.
- (vsliq_m_n_s16): Remove.
- (vsliq_m_n_u8): Remove.
- (vsliq_m_n_u32): Remove.
- (vsliq_m_n_u16): Remove.
- (__arm_vsliq_n_u8): Remove.
- (__arm_vsliq_n_s8): Remove.
- (__arm_vsliq_n_u16): Remove.
- (__arm_vsliq_n_s16): Remove.
- (__arm_vsliq_n_u32): Remove.
- (__arm_vsliq_n_s32): Remove.
- (__arm_vsliq_m_n_s8): Remove.
- (__arm_vsliq_m_n_s32): Remove.
- (__arm_vsliq_m_n_s16): Remove.
- (__arm_vsliq_m_n_u8): Remove.
- (__arm_vsliq_m_n_u32): Remove.
- (__arm_vsliq_m_n_u16): Remove.
- (__arm_vsliq): Remove.
- (__arm_vsliq_m): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn>): Add vsli.
- * config/arm/mve.md (mve_vsliq_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vsliq_m_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (ternary_lshift): New.
- * config/arm/arm-mve-builtins-shapes.h (ternary_lshift): New.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vpselq): New.
- * config/arm/arm-mve-builtins-base.def (vpselq): New.
- * config/arm/arm-mve-builtins-base.h (vpselq): New.
- * config/arm/arm_mve.h (vpselq): Remove.
- (vpselq_u8): Remove.
- (vpselq_s8): Remove.
- (vpselq_u16): Remove.
- (vpselq_s16): Remove.
- (vpselq_u32): Remove.
- (vpselq_s32): Remove.
- (vpselq_u64): Remove.
- (vpselq_s64): Remove.
- (vpselq_f16): Remove.
- (vpselq_f32): Remove.
- (__arm_vpselq_u8): Remove.
- (__arm_vpselq_s8): Remove.
- (__arm_vpselq_u16): Remove.
- (__arm_vpselq_s16): Remove.
- (__arm_vpselq_u32): Remove.
- (__arm_vpselq_s32): Remove.
- (__arm_vpselq_u64): Remove.
- (__arm_vpselq_s64): Remove.
- (__arm_vpselq_f16): Remove.
- (__arm_vpselq_f32): Remove.
- (__arm_vpselq): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (vpsel): New.
- * config/arm/arm-mve-builtins-shapes.h (vpsel): New.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm.cc (arm_expand_vcond): Use gen_mve_q instead of
- gen_mve_vpselq.
- * config/arm/iterators.md (MVE_VPSELQ_F): New.
- (mve_insn): Add vpsel.
- * config/arm/mve.md (@mve_vpselq_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (@mve_vpselq_f<mode>): Rename into ...
- (@mve_<mve_insn>q_f<mode>): ... this.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vfmaq, vfmasq, vfmsq): New.
- * config/arm/arm-mve-builtins-base.def (vfmaq, vfmasq, vfmsq): New.
- * config/arm/arm-mve-builtins-base.h (vfmaq, vfmasq, vfmsq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vfmaq, vfmasq,
- vfmsq.
- * config/arm/arm_mve.h (vfmaq): Remove.
- (vfmasq): Remove.
- (vfmsq): Remove.
- (vfmaq_m): Remove.
- (vfmasq_m): Remove.
- (vfmsq_m): Remove.
- (vfmaq_f16): Remove.
- (vfmaq_n_f16): Remove.
- (vfmasq_n_f16): Remove.
- (vfmsq_f16): Remove.
- (vfmaq_f32): Remove.
- (vfmaq_n_f32): Remove.
- (vfmasq_n_f32): Remove.
- (vfmsq_f32): Remove.
- (vfmaq_m_f32): Remove.
- (vfmaq_m_f16): Remove.
- (vfmaq_m_n_f32): Remove.
- (vfmaq_m_n_f16): Remove.
- (vfmasq_m_n_f32): Remove.
- (vfmasq_m_n_f16): Remove.
- (vfmsq_m_f32): Remove.
- (vfmsq_m_f16): Remove.
- (__arm_vfmaq_f16): Remove.
- (__arm_vfmaq_n_f16): Remove.
- (__arm_vfmasq_n_f16): Remove.
- (__arm_vfmsq_f16): Remove.
- (__arm_vfmaq_f32): Remove.
- (__arm_vfmaq_n_f32): Remove.
- (__arm_vfmasq_n_f32): Remove.
- (__arm_vfmsq_f32): Remove.
- (__arm_vfmaq_m_f32): Remove.
- (__arm_vfmaq_m_f16): Remove.
- (__arm_vfmaq_m_n_f32): Remove.
- (__arm_vfmaq_m_n_f16): Remove.
- (__arm_vfmasq_m_n_f32): Remove.
- (__arm_vfmasq_m_n_f16): Remove.
- (__arm_vfmsq_m_f32): Remove.
- (__arm_vfmsq_m_f16): Remove.
- (__arm_vfmaq): Remove.
- (__arm_vfmasq): Remove.
- (__arm_vfmsq): Remove.
- (__arm_vfmaq_m): Remove.
- (__arm_vfmasq_m): Remove.
- (__arm_vfmsq_m): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_FP_M_BINARY): Add VFMAQ_M_F,
- VFMSQ_M_F.
- (MVE_FP_M_N_BINARY): Add VFMAQ_M_N_F, VFMASQ_M_N_F.
- (MVE_VFMxQ_F, MVE_VFMAxQ_N_F): New.
- (mve_insn): Add vfma, vfmas, vfms.
- * config/arm/mve.md (mve_vfmaq_f<mode>, mve_vfmsq_f<mode>): Merge
- into ...
- (@mve_<mve_insn>q_f<mode>): ... this.
- (mve_vfmaq_n_f<mode>, mve_vfmasq_n_f<mode>): Merge into ...
- (@mve_<mve_insn>q_n_f<mode>): ... this.
- (mve_vfmaq_m_f<mode>, mve_vfmsq_m_f<mode>): Merge into
- @mve_<mve_insn>q_m_f<mode>.
- (mve_vfmaq_m_n_f<mode>, mve_vfmasq_m_n_f<mode>): Merge into
- @mve_<mve_insn>q_m_n_f<mode>.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (ternary_opt_n): New.
- * config/arm/arm-mve-builtins-shapes.h (ternary_opt_n): New.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc
- (FUNCTION_WITH_RTX_M_N_NO_F): New.
- (vmvnq): New.
- * config/arm/arm-mve-builtins-base.def (vmvnq): New.
- * config/arm/arm-mve-builtins-base.h (vmvnq): New.
- * config/arm/arm_mve.h (vmvnq): Remove.
- (vmvnq_m): Remove.
- (vmvnq_x): Remove.
- (vmvnq_s8): Remove.
- (vmvnq_s16): Remove.
- (vmvnq_s32): Remove.
- (vmvnq_n_s16): Remove.
- (vmvnq_n_s32): Remove.
- (vmvnq_u8): Remove.
- (vmvnq_u16): Remove.
- (vmvnq_u32): Remove.
- (vmvnq_n_u16): Remove.
- (vmvnq_n_u32): Remove.
- (vmvnq_m_u8): Remove.
- (vmvnq_m_s8): Remove.
- (vmvnq_m_u16): Remove.
- (vmvnq_m_s16): Remove.
- (vmvnq_m_u32): Remove.
- (vmvnq_m_s32): Remove.
- (vmvnq_m_n_s16): Remove.
- (vmvnq_m_n_u16): Remove.
- (vmvnq_m_n_s32): Remove.
- (vmvnq_m_n_u32): Remove.
- (vmvnq_x_s8): Remove.
- (vmvnq_x_s16): Remove.
- (vmvnq_x_s32): Remove.
- (vmvnq_x_u8): Remove.
- (vmvnq_x_u16): Remove.
- (vmvnq_x_u32): Remove.
- (vmvnq_x_n_s16): Remove.
- (vmvnq_x_n_s32): Remove.
- (vmvnq_x_n_u16): Remove.
- (vmvnq_x_n_u32): Remove.
- (__arm_vmvnq_s8): Remove.
- (__arm_vmvnq_s16): Remove.
- (__arm_vmvnq_s32): Remove.
- (__arm_vmvnq_n_s16): Remove.
- (__arm_vmvnq_n_s32): Remove.
- (__arm_vmvnq_u8): Remove.
- (__arm_vmvnq_u16): Remove.
- (__arm_vmvnq_u32): Remove.
- (__arm_vmvnq_n_u16): Remove.
- (__arm_vmvnq_n_u32): Remove.
- (__arm_vmvnq_m_u8): Remove.
- (__arm_vmvnq_m_s8): Remove.
- (__arm_vmvnq_m_u16): Remove.
- (__arm_vmvnq_m_s16): Remove.
- (__arm_vmvnq_m_u32): Remove.
- (__arm_vmvnq_m_s32): Remove.
- (__arm_vmvnq_m_n_s16): Remove.
- (__arm_vmvnq_m_n_u16): Remove.
- (__arm_vmvnq_m_n_s32): Remove.
- (__arm_vmvnq_m_n_u32): Remove.
- (__arm_vmvnq_x_s8): Remove.
- (__arm_vmvnq_x_s16): Remove.
- (__arm_vmvnq_x_s32): Remove.
- (__arm_vmvnq_x_u8): Remove.
- (__arm_vmvnq_x_u16): Remove.
- (__arm_vmvnq_x_u32): Remove.
- (__arm_vmvnq_x_n_s16): Remove.
- (__arm_vmvnq_x_n_s32): Remove.
- (__arm_vmvnq_x_n_u16): Remove.
- (__arm_vmvnq_x_n_u32): Remove.
- (__arm_vmvnq): Remove.
- (__arm_vmvnq_m): Remove.
- (__arm_vmvnq_x): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vmvn.
- * config/arm/mve.md (mve_vmvnq_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vmvnq_m_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_m_<supf><mode>): ... this.
- (mve_vmvnq_m_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (mvn): New.
- * config/arm/arm-mve-builtins-shapes.h (mvn): New.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vbrsrq): New.
- * config/arm/arm-mve-builtins-base.def (vbrsrq): New.
- * config/arm/arm-mve-builtins-base.h (vbrsrq): New.
- * config/arm/arm_mve.h (vbrsrq): Remove.
- (vbrsrq_m): Remove.
- (vbrsrq_x): Remove.
- (vbrsrq_n_f16): Remove.
- (vbrsrq_n_f32): Remove.
- (vbrsrq_n_u8): Remove.
- (vbrsrq_n_s8): Remove.
- (vbrsrq_n_u16): Remove.
- (vbrsrq_n_s16): Remove.
- (vbrsrq_n_u32): Remove.
- (vbrsrq_n_s32): Remove.
- (vbrsrq_m_n_s8): Remove.
- (vbrsrq_m_n_s32): Remove.
- (vbrsrq_m_n_s16): Remove.
- (vbrsrq_m_n_u8): Remove.
- (vbrsrq_m_n_u32): Remove.
- (vbrsrq_m_n_u16): Remove.
- (vbrsrq_m_n_f32): Remove.
- (vbrsrq_m_n_f16): Remove.
- (vbrsrq_x_n_s8): Remove.
- (vbrsrq_x_n_s16): Remove.
- (vbrsrq_x_n_s32): Remove.
- (vbrsrq_x_n_u8): Remove.
- (vbrsrq_x_n_u16): Remove.
- (vbrsrq_x_n_u32): Remove.
- (vbrsrq_x_n_f16): Remove.
- (vbrsrq_x_n_f32): Remove.
- (__arm_vbrsrq_n_u8): Remove.
- (__arm_vbrsrq_n_s8): Remove.
- (__arm_vbrsrq_n_u16): Remove.
- (__arm_vbrsrq_n_s16): Remove.
- (__arm_vbrsrq_n_u32): Remove.
- (__arm_vbrsrq_n_s32): Remove.
- (__arm_vbrsrq_m_n_s8): Remove.
- (__arm_vbrsrq_m_n_s32): Remove.
- (__arm_vbrsrq_m_n_s16): Remove.
- (__arm_vbrsrq_m_n_u8): Remove.
- (__arm_vbrsrq_m_n_u32): Remove.
- (__arm_vbrsrq_m_n_u16): Remove.
- (__arm_vbrsrq_x_n_s8): Remove.
- (__arm_vbrsrq_x_n_s16): Remove.
- (__arm_vbrsrq_x_n_s32): Remove.
- (__arm_vbrsrq_x_n_u8): Remove.
- (__arm_vbrsrq_x_n_u16): Remove.
- (__arm_vbrsrq_x_n_u32): Remove.
- (__arm_vbrsrq_n_f16): Remove.
- (__arm_vbrsrq_n_f32): Remove.
- (__arm_vbrsrq_m_n_f32): Remove.
- (__arm_vbrsrq_m_n_f16): Remove.
- (__arm_vbrsrq_x_n_f16): Remove.
- (__arm_vbrsrq_x_n_f32): Remove.
- (__arm_vbrsrq): Remove.
- (__arm_vbrsrq_m): Remove.
- (__arm_vbrsrq_x): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VBRSR_M_N_FP, MVE_VBRSR_N_FP): New.
- (mve_insn): Add vbrsr.
- * config/arm/mve.md (mve_vbrsrq_n_f<mode>): Rename into ...
- (@mve_<mve_insn>q_n_f<mode>): ... this.
- (mve_vbrsrq_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vbrsrq_m_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
- (mve_vbrsrq_m_n_f<mode>): Rename into ...
- (@mve_<mve_insn>q_m_n_f<mode>): ... this.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_imm32): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_imm32): New.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vqshluq): New.
- * config/arm/arm-mve-builtins-base.def (vqshluq): New.
- * config/arm/arm-mve-builtins-base.h (vqshluq): New.
- * config/arm/arm_mve.h (vqshluq): Remove.
- (vqshluq_m): Remove.
- (vqshluq_n_s8): Remove.
- (vqshluq_n_s16): Remove.
- (vqshluq_n_s32): Remove.
- (vqshluq_m_n_s8): Remove.
- (vqshluq_m_n_s16): Remove.
- (vqshluq_m_n_s32): Remove.
- (__arm_vqshluq_n_s8): Remove.
- (__arm_vqshluq_n_s16): Remove.
- (__arm_vqshluq_n_s32): Remove.
- (__arm_vqshluq_m_n_s8): Remove.
- (__arm_vqshluq_m_n_s16): Remove.
- (__arm_vqshluq_m_n_s32): Remove.
- (__arm_vqshluq): Remove.
- (__arm_vqshluq_m): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vqshlu.
- (supf): Add VQSHLUQ_M_N_S, VQSHLUQ_N_S.
- (VQSHLUQ_M_N, VQSHLUQ_N): New.
- * config/arm/mve.md (mve_vqshluq_n_s<mode>): Change name into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vqshluq_m_n_s<mode>): Change name into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc
- (binary_lshift_unsigned): New.
- * config/arm/arm-mve-builtins-shapes.h
- (binary_lshift_unsigned): New.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vrmlaldavhaq)
- (vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
- * config/arm/arm-mve-builtins-base.def (vrmlaldavhaq)
- (vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
- * config/arm/arm-mve-builtins-base.h (vrmlaldavhaq)
- (vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
- * config/arm/arm-mve-builtins-functions.h: Handle vrmlaldavhaq,
- vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq.
- * config/arm/arm_mve.h (vrmlaldavhaq): Remove.
- (vrmlaldavhaxq): Remove.
- (vrmlsldavhaq): Remove.
- (vrmlsldavhaxq): Remove.
- (vrmlaldavhaq_p): Remove.
- (vrmlaldavhaxq_p): Remove.
- (vrmlsldavhaq_p): Remove.
- (vrmlsldavhaxq_p): Remove.
- (vrmlaldavhaq_s32): Remove.
- (vrmlaldavhaq_u32): Remove.
- (vrmlaldavhaxq_s32): Remove.
- (vrmlsldavhaq_s32): Remove.
- (vrmlsldavhaxq_s32): Remove.
- (vrmlaldavhaq_p_s32): Remove.
- (vrmlaldavhaq_p_u32): Remove.
- (vrmlaldavhaxq_p_s32): Remove.
- (vrmlsldavhaq_p_s32): Remove.
- (vrmlsldavhaxq_p_s32): Remove.
- (__arm_vrmlaldavhaq_s32): Remove.
- (__arm_vrmlaldavhaq_u32): Remove.
- (__arm_vrmlaldavhaxq_s32): Remove.
- (__arm_vrmlsldavhaq_s32): Remove.
- (__arm_vrmlsldavhaxq_s32): Remove.
- (__arm_vrmlaldavhaq_p_s32): Remove.
- (__arm_vrmlaldavhaq_p_u32): Remove.
- (__arm_vrmlaldavhaxq_p_s32): Remove.
- (__arm_vrmlsldavhaq_p_s32): Remove.
- (__arm_vrmlsldavhaxq_p_s32): Remove.
- (__arm_vrmlaldavhaq): Remove.
- (__arm_vrmlaldavhaxq): Remove.
- (__arm_vrmlsldavhaq): Remove.
- (__arm_vrmlsldavhaxq): Remove.
- (__arm_vrmlaldavhaq_p): Remove.
- (__arm_vrmlaldavhaxq_p): Remove.
- (__arm_vrmlsldavhaq_p): Remove.
- (__arm_vrmlsldavhaxq_p): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VRMLxLDAVHAxQ)
- (MVE_VRMLxLDAVHAxQ_P): New.
- (mve_insn): Add vrmlaldavha, vrmlaldavhax, vrmlsldavha,
- vrmlsldavhax.
- (supf): Add VRMLALDAVHAXQ_P_S, VRMLALDAVHAXQ_S, VRMLSLDAVHAQ_P_S,
- VRMLSLDAVHAQ_S, VRMLSLDAVHAXQ_P_S, VRMLSLDAVHAXQ_S,
- VRMLALDAVHAQ_P_S.
- * config/arm/mve.md (mve_vrmlaldavhaq_<supf>v4si)
- (mve_vrmlaldavhaxq_sv4si, mve_vrmlsldavhaxq_sv4si)
- (mve_vrmlsldavhaq_sv4si): Merge into ...
- (@mve_<mve_insn>q_<supf>v4si): ... this.
- (mve_vrmlaldavhaq_p_sv4si, mve_vrmlaldavhaq_p_uv4si)
- (mve_vrmlaldavhaxq_p_sv4si, mve_vrmlsldavhaq_p_sv4si)
- (mve_vrmlsldavhaxq_p_sv4si): Merge into ...
- (@mve_<mve_insn>q_p_<supf>v4si): ... this.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vqdmullbq, vqdmulltq): New.
- * config/arm/arm-mve-builtins-base.def (vqdmullbq, vqdmulltq):
- New.
- * config/arm/arm-mve-builtins-base.h (vqdmullbq, vqdmulltq): New.
- * config/arm/arm_mve.h (vqdmulltq): Remove.
- (vqdmullbq): Remove.
- (vqdmullbq_m): Remove.
- (vqdmulltq_m): Remove.
- (vqdmulltq_s16): Remove.
- (vqdmulltq_n_s16): Remove.
- (vqdmullbq_s16): Remove.
- (vqdmullbq_n_s16): Remove.
- (vqdmulltq_s32): Remove.
- (vqdmulltq_n_s32): Remove.
- (vqdmullbq_s32): Remove.
- (vqdmullbq_n_s32): Remove.
- (vqdmullbq_m_n_s32): Remove.
- (vqdmullbq_m_n_s16): Remove.
- (vqdmullbq_m_s32): Remove.
- (vqdmullbq_m_s16): Remove.
- (vqdmulltq_m_n_s32): Remove.
- (vqdmulltq_m_n_s16): Remove.
- (vqdmulltq_m_s32): Remove.
- (vqdmulltq_m_s16): Remove.
- (__arm_vqdmulltq_s16): Remove.
- (__arm_vqdmulltq_n_s16): Remove.
- (__arm_vqdmullbq_s16): Remove.
- (__arm_vqdmullbq_n_s16): Remove.
- (__arm_vqdmulltq_s32): Remove.
- (__arm_vqdmulltq_n_s32): Remove.
- (__arm_vqdmullbq_s32): Remove.
- (__arm_vqdmullbq_n_s32): Remove.
- (__arm_vqdmullbq_m_n_s32): Remove.
- (__arm_vqdmullbq_m_n_s16): Remove.
- (__arm_vqdmullbq_m_s32): Remove.
- (__arm_vqdmullbq_m_s16): Remove.
- (__arm_vqdmulltq_m_n_s32): Remove.
- (__arm_vqdmulltq_m_n_s16): Remove.
- (__arm_vqdmulltq_m_s32): Remove.
- (__arm_vqdmulltq_m_s16): Remove.
- (__arm_vqdmulltq): Remove.
- (__arm_vqdmullbq): Remove.
- (__arm_vqdmullbq_m): Remove.
- (__arm_vqdmulltq_m): Remove.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VQDMULLxQ, MVE_VQDMULLxQ_M)
- (MVE_VQDMULLxQ_M_N, MVE_VQDMULLxQ_N): New.
- (mve_insn): Add vqdmullb, vqdmullt.
- (supf): Add VQDMULLBQ_S, VQDMULLBQ_M_S, VQDMULLBQ_M_N_S,
- VQDMULLBQ_N_S, VQDMULLTQ_S, VQDMULLTQ_M_S, VQDMULLTQ_M_N_S,
- VQDMULLTQ_N_S.
- * config/arm/mve.md (mve_vqdmullbq_n_s<mode>)
- (mve_vqdmulltq_n_s<mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vqdmullbq_s<mode>, mve_vqdmulltq_s<mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vqdmullbq_m_n_s<mode>, mve_vqdmulltq_m_n_s<mode>): Merge into
- ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
- (mve_vqdmullbq_m_s<mode>, mve_vqdmulltq_m_s<mode>): Merge into ...
- (@mve_<mve_insn>q_m_<supf><mode>): ... this.
-
-2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_widen_opt_n): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_widen_opt_n): New.
-
-2023-05-12 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi):
- Drop unused parameter.
- (riscv_select_multilib): Ditto.
- (riscv_compute_multilib): Update call site of
- riscv_select_multilib_by_abi and riscv_select_multilib_by_abi.
-
-2023-05-12 Juzhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (vec_init<mode><vel>): New pattern.
- * config/riscv/riscv-protos.h (expand_vec_init): New function.
- * config/riscv/riscv-v.cc (class rvv_builder): New class.
- (rvv_builder::can_duplicate_repeating_sequence_p): New function.
- (rvv_builder::get_merged_repeating_sequence): Ditto.
- (expand_vector_init_insert_elems): Ditto.
- (expand_vec_init): Ditto.
- * config/riscv/vector-iterators.md: New attribute.
-
-2023-05-12 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * config/rs6000/rs6000-builtins.def
- (__builtin_vsx_scalar_insert_exp): Replace bif-pattern from xsiexpdp
- to xsiexpdp_di.
- (__builtin_vsx_scalar_insert_exp_dp): Replace bif-pattern from
- xsiexpdpf to xsiexpdpf_di.
- * config/rs6000/vsx.md (xsiexpdp): Rename to...
- (xsiexpdp_<mode>): ..., set the mode of second operand to GPR and
- replace TARGET_64BIT with TARGET_POWERPC64.
- (xsiexpdpf): Rename to...
- (xsiexpdpf_<mode>): ..., set the mode of second operand to GPR and
- replace TARGET_64BIT with TARGET_POWERPC64.
-
-2023-05-12 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * config/rs6000/rs6000-builtins.def
- (__builtin_vsx_scalar_extract_sig): Set return type to const signed
- long long.
- * config/rs6000/vsx.md (xsxsigdp): Replace TARGET_64BIT with
- TARGET_POWERPC64.
-
-2023-05-12 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * config/rs6000/rs6000-builtins.def
- (__builtin_vsx_scalar_extract_exp): Set return type to const signed
- int and set its bif-pattern to xsxexpdp_si, move it from power9-64
- to power9 catalog.
- * config/rs6000/vsx.md (xsxexpdp): Rename to ...
- (xsxexpdp_<mode>): ..., set mode of operand 0 to GPR and remove
- TARGET_64BIT check.
- * doc/extend.texi (scalar_extract_exp): Remove 64-bit environment
- requirement when it has a 64-bit argument.
-
-2023-05-12 Pan Li <pan2.li@intel.com>
- Richard Sandiford <richard.sandiford@arm.com>
- Richard Biener <rguenther@suse.de>
- Jakub Jelinek <jakub@redhat.com>
-
- * mux-utils.h: Add overload operator == and != for pointer_mux.
- * var-tracking.cc: Included mux-utils.h for pointer_tmux.
- (decl_or_value): Changed from void * to pointer_mux<tree_node, rtx_def>.
- (dv_is_decl_p): Reconciled to the new type, aka pointer_mux.
- (dv_as_decl): Ditto.
- (dv_as_opaque): Removed due to unnecessary.
- (struct variable_hasher): Take decl_or_value as compare_type.
- (variable_hasher::equal): Diito.
- (dv_from_decl): Reconciled to the new type, aka pointer_mux.
- (dv_from_value): Ditto.
- (attrs_list_member): Ditto.
- (vars_copy): Ditto.
- (var_reg_decl_set): Ditto.
- (var_reg_delete_and_set): Ditto.
- (find_loc_in_1pdv): Ditto.
- (canonicalize_values_star): Ditto.
- (variable_post_merge_new_vals): Ditto.
- (dump_onepart_variable_differences): Ditto.
- (variable_different_p): Ditto.
- (set_slot_part): Ditto.
- (clobber_slot_part): Ditto.
- (clobber_variable_part): Ditto.
-
-2023-05-11 mtsamis <manolis.tsamis@vrull.eu>
-
- * match.pd: simplify vector shift + bit_and + multiply.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmlaq, vmlasq, vqdmlahq)
- (vqdmlashq, vqrdmlahq, vqrdmlashq): New.
- * config/arm/arm-mve-builtins-base.def (vmlaq, vmlasq, vqdmlahq)
- (vqdmlashq, vqrdmlahq, vqrdmlashq): New.
- * config/arm/arm-mve-builtins-base.h (vmlaq, vmlasq, vqdmlahq)
- (vqdmlashq, vqrdmlahq, vqrdmlashq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vmlaq, vmlasq,
- vqdmlahq, vqdmlashq, vqrdmlahq, vqrdmlashq.
- * config/arm/arm_mve.h (vqrdmlashq): Remove.
- (vqrdmlahq): Remove.
- (vqdmlashq): Remove.
- (vqdmlahq): Remove.
- (vmlasq): Remove.
- (vmlaq): Remove.
- (vmlaq_m): Remove.
- (vmlasq_m): Remove.
- (vqdmlashq_m): Remove.
- (vqdmlahq_m): Remove.
- (vqrdmlahq_m): Remove.
- (vqrdmlashq_m): Remove.
- (vmlasq_n_u8): Remove.
- (vmlaq_n_u8): Remove.
- (vqrdmlashq_n_s8): Remove.
- (vqrdmlahq_n_s8): Remove.
- (vqdmlahq_n_s8): Remove.
- (vqdmlashq_n_s8): Remove.
- (vmlasq_n_s8): Remove.
- (vmlaq_n_s8): Remove.
- (vmlasq_n_u16): Remove.
- (vmlaq_n_u16): Remove.
- (vqrdmlashq_n_s16): Remove.
- (vqrdmlahq_n_s16): Remove.
- (vqdmlashq_n_s16): Remove.
- (vqdmlahq_n_s16): Remove.
- (vmlasq_n_s16): Remove.
- (vmlaq_n_s16): Remove.
- (vmlasq_n_u32): Remove.
- (vmlaq_n_u32): Remove.
- (vqrdmlashq_n_s32): Remove.
- (vqrdmlahq_n_s32): Remove.
- (vqdmlashq_n_s32): Remove.
- (vqdmlahq_n_s32): Remove.
- (vmlasq_n_s32): Remove.
- (vmlaq_n_s32): Remove.
- (vmlaq_m_n_s8): Remove.
- (vmlaq_m_n_s32): Remove.
- (vmlaq_m_n_s16): Remove.
- (vmlaq_m_n_u8): Remove.
- (vmlaq_m_n_u32): Remove.
- (vmlaq_m_n_u16): Remove.
- (vmlasq_m_n_s8): Remove.
- (vmlasq_m_n_s32): Remove.
- (vmlasq_m_n_s16): Remove.
- (vmlasq_m_n_u8): Remove.
- (vmlasq_m_n_u32): Remove.
- (vmlasq_m_n_u16): Remove.
- (vqdmlashq_m_n_s8): Remove.
- (vqdmlashq_m_n_s32): Remove.
- (vqdmlashq_m_n_s16): Remove.
- (vqdmlahq_m_n_s8): Remove.
- (vqdmlahq_m_n_s32): Remove.
- (vqdmlahq_m_n_s16): Remove.
- (vqrdmlahq_m_n_s8): Remove.
- (vqrdmlahq_m_n_s32): Remove.
- (vqrdmlahq_m_n_s16): Remove.
- (vqrdmlashq_m_n_s8): Remove.
- (vqrdmlashq_m_n_s32): Remove.
- (vqrdmlashq_m_n_s16): Remove.
- (__arm_vmlasq_n_u8): Remove.
- (__arm_vmlaq_n_u8): Remove.
- (__arm_vqrdmlashq_n_s8): Remove.
- (__arm_vqdmlashq_n_s8): Remove.
- (__arm_vqrdmlahq_n_s8): Remove.
- (__arm_vqdmlahq_n_s8): Remove.
- (__arm_vmlasq_n_s8): Remove.
- (__arm_vmlaq_n_s8): Remove.
- (__arm_vmlasq_n_u16): Remove.
- (__arm_vmlaq_n_u16): Remove.
- (__arm_vqrdmlashq_n_s16): Remove.
- (__arm_vqdmlashq_n_s16): Remove.
- (__arm_vqrdmlahq_n_s16): Remove.
- (__arm_vqdmlahq_n_s16): Remove.
- (__arm_vmlasq_n_s16): Remove.
- (__arm_vmlaq_n_s16): Remove.
- (__arm_vmlasq_n_u32): Remove.
- (__arm_vmlaq_n_u32): Remove.
- (__arm_vqrdmlashq_n_s32): Remove.
- (__arm_vqdmlashq_n_s32): Remove.
- (__arm_vqrdmlahq_n_s32): Remove.
- (__arm_vqdmlahq_n_s32): Remove.
- (__arm_vmlasq_n_s32): Remove.
- (__arm_vmlaq_n_s32): Remove.
- (__arm_vmlaq_m_n_s8): Remove.
- (__arm_vmlaq_m_n_s32): Remove.
- (__arm_vmlaq_m_n_s16): Remove.
- (__arm_vmlaq_m_n_u8): Remove.
- (__arm_vmlaq_m_n_u32): Remove.
- (__arm_vmlaq_m_n_u16): Remove.
- (__arm_vmlasq_m_n_s8): Remove.
- (__arm_vmlasq_m_n_s32): Remove.
- (__arm_vmlasq_m_n_s16): Remove.
- (__arm_vmlasq_m_n_u8): Remove.
- (__arm_vmlasq_m_n_u32): Remove.
- (__arm_vmlasq_m_n_u16): Remove.
- (__arm_vqdmlahq_m_n_s8): Remove.
- (__arm_vqdmlahq_m_n_s32): Remove.
- (__arm_vqdmlahq_m_n_s16): Remove.
- (__arm_vqrdmlahq_m_n_s8): Remove.
- (__arm_vqrdmlahq_m_n_s32): Remove.
- (__arm_vqrdmlahq_m_n_s16): Remove.
- (__arm_vqrdmlashq_m_n_s8): Remove.
- (__arm_vqrdmlashq_m_n_s32): Remove.
- (__arm_vqrdmlashq_m_n_s16): Remove.
- (__arm_vqdmlashq_m_n_s8): Remove.
- (__arm_vqdmlashq_m_n_s16): Remove.
- (__arm_vqdmlashq_m_n_s32): Remove.
- (__arm_vmlasq): Remove.
- (__arm_vmlaq): Remove.
- (__arm_vqrdmlashq): Remove.
- (__arm_vqdmlashq): Remove.
- (__arm_vqrdmlahq): Remove.
- (__arm_vqdmlahq): Remove.
- (__arm_vmlaq_m): Remove.
- (__arm_vmlasq_m): Remove.
- (__arm_vqdmlahq_m): Remove.
- (__arm_vqrdmlahq_m): Remove.
- (__arm_vqrdmlashq_m): Remove.
- (__arm_vqdmlashq_m): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VMLxQ_N): New.
- (mve_insn): Add vmla, vmlas, vqdmlah, vqdmlash, vqrdmlah,
- vqrdmlash.
- (supf): Add VQDMLAHQ_N_S, VQDMLASHQ_N_S, VQRDMLAHQ_N_S,
- VQRDMLASHQ_N_S.
- * config/arm/mve.md (mve_vmlaq_n_<supf><mode>)
- (mve_vmlasq_n_<supf><mode>, mve_vqdmlahq_n_<supf><mode>)
- (mve_vqdmlashq_n_<supf><mode>, mve_vqrdmlahq_n_<supf><mode>)
- (mve_vqrdmlashq_n_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (ternary_n): New.
- * config/arm/arm-mve-builtins-shapes.h (ternary_n): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vqdmladhq, vqdmladhxq)
- (vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq)
- (vqrdmlsdhxq): New.
- * config/arm/arm-mve-builtins-base.def (vqdmladhq, vqdmladhxq)
- (vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq)
- (vqrdmlsdhxq): New.
- * config/arm/arm-mve-builtins-base.h (vqdmladhq, vqdmladhxq)
- (vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq)
- (vqrdmlsdhxq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vqrdmladhq,
- vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq vqdmladhq, vqdmladhxq,
- vqdmlsdhq, vqdmlsdhxq.
- * config/arm/arm_mve.h (vqrdmlsdhxq): Remove.
- (vqrdmlsdhq): Remove.
- (vqrdmladhxq): Remove.
- (vqrdmladhq): Remove.
- (vqdmlsdhxq): Remove.
- (vqdmlsdhq): Remove.
- (vqdmladhxq): Remove.
- (vqdmladhq): Remove.
- (vqdmladhq_m): Remove.
- (vqdmladhxq_m): Remove.
- (vqdmlsdhq_m): Remove.
- (vqdmlsdhxq_m): Remove.
- (vqrdmladhq_m): Remove.
- (vqrdmladhxq_m): Remove.
- (vqrdmlsdhq_m): Remove.
- (vqrdmlsdhxq_m): Remove.
- (vqrdmlsdhxq_s8): Remove.
- (vqrdmlsdhq_s8): Remove.
- (vqrdmladhxq_s8): Remove.
- (vqrdmladhq_s8): Remove.
- (vqdmlsdhxq_s8): Remove.
- (vqdmlsdhq_s8): Remove.
- (vqdmladhxq_s8): Remove.
- (vqdmladhq_s8): Remove.
- (vqrdmlsdhxq_s16): Remove.
- (vqrdmlsdhq_s16): Remove.
- (vqrdmladhxq_s16): Remove.
- (vqrdmladhq_s16): Remove.
- (vqdmlsdhxq_s16): Remove.
- (vqdmlsdhq_s16): Remove.
- (vqdmladhxq_s16): Remove.
- (vqdmladhq_s16): Remove.
- (vqrdmlsdhxq_s32): Remove.
- (vqrdmlsdhq_s32): Remove.
- (vqrdmladhxq_s32): Remove.
- (vqrdmladhq_s32): Remove.
- (vqdmlsdhxq_s32): Remove.
- (vqdmlsdhq_s32): Remove.
- (vqdmladhxq_s32): Remove.
- (vqdmladhq_s32): Remove.
- (vqdmladhq_m_s8): Remove.
- (vqdmladhq_m_s32): Remove.
- (vqdmladhq_m_s16): Remove.
- (vqdmladhxq_m_s8): Remove.
- (vqdmladhxq_m_s32): Remove.
- (vqdmladhxq_m_s16): Remove.
- (vqdmlsdhq_m_s8): Remove.
- (vqdmlsdhq_m_s32): Remove.
- (vqdmlsdhq_m_s16): Remove.
- (vqdmlsdhxq_m_s8): Remove.
- (vqdmlsdhxq_m_s32): Remove.
- (vqdmlsdhxq_m_s16): Remove.
- (vqrdmladhq_m_s8): Remove.
- (vqrdmladhq_m_s32): Remove.
- (vqrdmladhq_m_s16): Remove.
- (vqrdmladhxq_m_s8): Remove.
- (vqrdmladhxq_m_s32): Remove.
- (vqrdmladhxq_m_s16): Remove.
- (vqrdmlsdhq_m_s8): Remove.
- (vqrdmlsdhq_m_s32): Remove.
- (vqrdmlsdhq_m_s16): Remove.
- (vqrdmlsdhxq_m_s8): Remove.
- (vqrdmlsdhxq_m_s32): Remove.
- (vqrdmlsdhxq_m_s16): Remove.
- (__arm_vqrdmlsdhxq_s8): Remove.
- (__arm_vqrdmlsdhq_s8): Remove.
- (__arm_vqrdmladhxq_s8): Remove.
- (__arm_vqrdmladhq_s8): Remove.
- (__arm_vqdmlsdhxq_s8): Remove.
- (__arm_vqdmlsdhq_s8): Remove.
- (__arm_vqdmladhxq_s8): Remove.
- (__arm_vqdmladhq_s8): Remove.
- (__arm_vqrdmlsdhxq_s16): Remove.
- (__arm_vqrdmlsdhq_s16): Remove.
- (__arm_vqrdmladhxq_s16): Remove.
- (__arm_vqrdmladhq_s16): Remove.
- (__arm_vqdmlsdhxq_s16): Remove.
- (__arm_vqdmlsdhq_s16): Remove.
- (__arm_vqdmladhxq_s16): Remove.
- (__arm_vqdmladhq_s16): Remove.
- (__arm_vqrdmlsdhxq_s32): Remove.
- (__arm_vqrdmlsdhq_s32): Remove.
- (__arm_vqrdmladhxq_s32): Remove.
- (__arm_vqrdmladhq_s32): Remove.
- (__arm_vqdmlsdhxq_s32): Remove.
- (__arm_vqdmlsdhq_s32): Remove.
- (__arm_vqdmladhxq_s32): Remove.
- (__arm_vqdmladhq_s32): Remove.
- (__arm_vqdmladhq_m_s8): Remove.
- (__arm_vqdmladhq_m_s32): Remove.
- (__arm_vqdmladhq_m_s16): Remove.
- (__arm_vqdmladhxq_m_s8): Remove.
- (__arm_vqdmladhxq_m_s32): Remove.
- (__arm_vqdmladhxq_m_s16): Remove.
- (__arm_vqdmlsdhq_m_s8): Remove.
- (__arm_vqdmlsdhq_m_s32): Remove.
- (__arm_vqdmlsdhq_m_s16): Remove.
- (__arm_vqdmlsdhxq_m_s8): Remove.
- (__arm_vqdmlsdhxq_m_s32): Remove.
- (__arm_vqdmlsdhxq_m_s16): Remove.
- (__arm_vqrdmladhq_m_s8): Remove.
- (__arm_vqrdmladhq_m_s32): Remove.
- (__arm_vqrdmladhq_m_s16): Remove.
- (__arm_vqrdmladhxq_m_s8): Remove.
- (__arm_vqrdmladhxq_m_s32): Remove.
- (__arm_vqrdmladhxq_m_s16): Remove.
- (__arm_vqrdmlsdhq_m_s8): Remove.
- (__arm_vqrdmlsdhq_m_s32): Remove.
- (__arm_vqrdmlsdhq_m_s16): Remove.
- (__arm_vqrdmlsdhxq_m_s8): Remove.
- (__arm_vqrdmlsdhxq_m_s32): Remove.
- (__arm_vqrdmlsdhxq_m_s16): Remove.
- (__arm_vqrdmlsdhxq): Remove.
- (__arm_vqrdmlsdhq): Remove.
- (__arm_vqrdmladhxq): Remove.
- (__arm_vqrdmladhq): Remove.
- (__arm_vqdmlsdhxq): Remove.
- (__arm_vqdmlsdhq): Remove.
- (__arm_vqdmladhxq): Remove.
- (__arm_vqdmladhq): Remove.
- (__arm_vqdmladhq_m): Remove.
- (__arm_vqdmladhxq_m): Remove.
- (__arm_vqdmlsdhq_m): Remove.
- (__arm_vqdmlsdhxq_m): Remove.
- (__arm_vqrdmladhq_m): Remove.
- (__arm_vqrdmladhxq_m): Remove.
- (__arm_vqrdmlsdhq_m): Remove.
- (__arm_vqrdmlsdhxq_m): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VQxDMLxDHxQ_S): New.
- (mve_insn): Add vqdmladh, vqdmladhx, vqdmlsdh, vqdmlsdhx,
- vqrdmladh, vqrdmladhx, vqrdmlsdh, vqrdmlsdhx.
- (supf): Add VQDMLADHQ_S, VQDMLADHXQ_S, VQDMLSDHQ_S, VQDMLSDHXQ_S,
- VQRDMLADHQ_S,VQRDMLADHXQ_S, VQRDMLSDHQ_S, VQRDMLSDHXQ_S.
- * config/arm/mve.md (mve_vqrdmladhq_s<mode>)
- (mve_vqrdmladhxq_s<mode>, mve_vqrdmlsdhq_s<mode>)
- (mve_vqrdmlsdhxq_s<mode>, mve_vqdmlsdhxq_s<mode>)
- (mve_vqdmlsdhq_s<mode>, mve_vqdmladhxq_s<mode>)
- (mve_vqdmladhq_s<mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (ternary): New.
- * config/arm/arm-mve-builtins-shapes.h (ternary): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmlaldavaq, vmlaldavaxq)
- (vmlsldavaq, vmlsldavaxq): New.
- * config/arm/arm-mve-builtins-base.def (vmlaldavaq, vmlaldavaxq)
- (vmlsldavaq, vmlsldavaxq): New.
- * config/arm/arm-mve-builtins-base.h (vmlaldavaq, vmlaldavaxq)
- (vmlsldavaq, vmlsldavaxq): New.
- * config/arm/arm_mve.h (vmlaldavaq): Remove.
- (vmlaldavaxq): Remove.
- (vmlsldavaq): Remove.
- (vmlsldavaxq): Remove.
- (vmlaldavaq_p): Remove.
- (vmlaldavaxq_p): Remove.
- (vmlsldavaq_p): Remove.
- (vmlsldavaxq_p): Remove.
- (vmlaldavaq_s16): Remove.
- (vmlaldavaxq_s16): Remove.
- (vmlsldavaq_s16): Remove.
- (vmlsldavaxq_s16): Remove.
- (vmlaldavaq_u16): Remove.
- (vmlaldavaq_s32): Remove.
- (vmlaldavaxq_s32): Remove.
- (vmlsldavaq_s32): Remove.
- (vmlsldavaxq_s32): Remove.
- (vmlaldavaq_u32): Remove.
- (vmlaldavaq_p_s32): Remove.
- (vmlaldavaq_p_s16): Remove.
- (vmlaldavaq_p_u32): Remove.
- (vmlaldavaq_p_u16): Remove.
- (vmlaldavaxq_p_s32): Remove.
- (vmlaldavaxq_p_s16): Remove.
- (vmlsldavaq_p_s32): Remove.
- (vmlsldavaq_p_s16): Remove.
- (vmlsldavaxq_p_s32): Remove.
- (vmlsldavaxq_p_s16): Remove.
- (__arm_vmlaldavaq_s16): Remove.
- (__arm_vmlaldavaxq_s16): Remove.
- (__arm_vmlsldavaq_s16): Remove.
- (__arm_vmlsldavaxq_s16): Remove.
- (__arm_vmlaldavaq_u16): Remove.
- (__arm_vmlaldavaq_s32): Remove.
- (__arm_vmlaldavaxq_s32): Remove.
- (__arm_vmlsldavaq_s32): Remove.
- (__arm_vmlsldavaxq_s32): Remove.
- (__arm_vmlaldavaq_u32): Remove.
- (__arm_vmlaldavaq_p_s32): Remove.
- (__arm_vmlaldavaq_p_s16): Remove.
- (__arm_vmlaldavaq_p_u32): Remove.
- (__arm_vmlaldavaq_p_u16): Remove.
- (__arm_vmlaldavaxq_p_s32): Remove.
- (__arm_vmlaldavaxq_p_s16): Remove.
- (__arm_vmlsldavaq_p_s32): Remove.
- (__arm_vmlsldavaq_p_s16): Remove.
- (__arm_vmlsldavaxq_p_s32): Remove.
- (__arm_vmlsldavaxq_p_s16): Remove.
- (__arm_vmlaldavaq): Remove.
- (__arm_vmlaldavaxq): Remove.
- (__arm_vmlsldavaq): Remove.
- (__arm_vmlsldavaxq): Remove.
- (__arm_vmlaldavaq_p): Remove.
- (__arm_vmlaldavaxq_p): Remove.
- (__arm_vmlsldavaq_p): Remove.
- (__arm_vmlsldavaxq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VMLxLDAVAxQ, MVE_VMLxLDAVAxQ_P):
- New.
- (mve_insn): Add vmlaldava, vmlaldavax, vmlsldava, vmlsldavax.
- (supf): Add VMLALDAVAXQ_P_S, VMLALDAVAXQ_S, VMLSLDAVAQ_P_S,
- VMLSLDAVAQ_S, VMLSLDAVAXQ_P_S, VMLSLDAVAXQ_S.
- * config/arm/mve.md (mve_vmlaldavaq_<supf><mode>)
- (mve_vmlsldavaq_s<mode>, mve_vmlsldavaxq_s<mode>)
- (mve_vmlaldavaxq_s<mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vmlaldavaq_p_<supf><mode>, mve_vmlaldavaxq_p_<supf><mode>)
- (mve_vmlsldavaq_p_s<mode>, mve_vmlsldavaxq_p_s<mode>): Merge into
- ...
- (@mve_<mve_insn>q_p_<supf><mode>): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_acca_int64): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_acca_int64): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vrmlaldavhq, vrmlaldavhxq)
- (vrmlsldavhq, vrmlsldavhxq): New.
- * config/arm/arm-mve-builtins-base.def (vrmlaldavhq, vrmlaldavhxq)
- (vrmlsldavhq, vrmlsldavhxq): New.
- * config/arm/arm-mve-builtins-base.h (vrmlaldavhq, vrmlaldavhxq)
- (vrmlsldavhq, vrmlsldavhxq): New.
- * config/arm/arm-mve-builtins-functions.h
- (unspec_mve_function_exact_insn_pred_p): Handle vrmlaldavhq,
- vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq.
- * config/arm/arm_mve.h (vrmlaldavhq): Remove.
- (vrmlsldavhxq): Remove.
- (vrmlsldavhq): Remove.
- (vrmlaldavhxq): Remove.
- (vrmlaldavhq_p): Remove.
- (vrmlaldavhxq_p): Remove.
- (vrmlsldavhq_p): Remove.
- (vrmlsldavhxq_p): Remove.
- (vrmlaldavhq_u32): Remove.
- (vrmlsldavhxq_s32): Remove.
- (vrmlsldavhq_s32): Remove.
- (vrmlaldavhxq_s32): Remove.
- (vrmlaldavhq_s32): Remove.
- (vrmlaldavhq_p_s32): Remove.
- (vrmlaldavhxq_p_s32): Remove.
- (vrmlsldavhq_p_s32): Remove.
- (vrmlsldavhxq_p_s32): Remove.
- (vrmlaldavhq_p_u32): Remove.
- (__arm_vrmlaldavhq_u32): Remove.
- (__arm_vrmlsldavhxq_s32): Remove.
- (__arm_vrmlsldavhq_s32): Remove.
- (__arm_vrmlaldavhxq_s32): Remove.
- (__arm_vrmlaldavhq_s32): Remove.
- (__arm_vrmlaldavhq_p_s32): Remove.
- (__arm_vrmlaldavhxq_p_s32): Remove.
- (__arm_vrmlsldavhq_p_s32): Remove.
- (__arm_vrmlsldavhxq_p_s32): Remove.
- (__arm_vrmlaldavhq_p_u32): Remove.
- (__arm_vrmlaldavhq): Remove.
- (__arm_vrmlsldavhxq): Remove.
- (__arm_vrmlsldavhq): Remove.
- (__arm_vrmlaldavhxq): Remove.
- (__arm_vrmlaldavhq_p): Remove.
- (__arm_vrmlaldavhxq_p): Remove.
- (__arm_vrmlsldavhq_p): Remove.
- (__arm_vrmlsldavhxq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VRMLxLDAVxQ, MVE_VRMLxLDAVHxQ_P):
- New.
- (mve_insn): Add vrmlaldavh, vrmlaldavhx, vrmlsldavh, vrmlsldavhx.
- (supf): Add VRMLALDAVHXQ_P_S, VRMLALDAVHXQ_S, VRMLSLDAVHQ_P_S,
- VRMLSLDAVHQ_S, VRMLSLDAVHXQ_P_S, VRMLSLDAVHXQ_S.
- * config/arm/mve.md (mve_vrmlaldavhxq_sv4si)
- (mve_vrmlsldavhq_sv4si, mve_vrmlsldavhxq_sv4si)
- (mve_vrmlaldavhq_<supf>v4si): Merge into ...
- (@mve_<mve_insn>q_<supf>v4si): ... this.
- (mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhq_p_sv4si)
- (mve_vrmlsldavhxq_p_sv4si, mve_vrmlaldavhq_p_<supf>v4si): Merge
- into ...
- (@mve_<mve_insn>q_p_<supf>v4si): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmlaldavq, vmlaldavxq)
- (vmlsldavq, vmlsldavxq): New.
- * config/arm/arm-mve-builtins-base.def (vmlaldavq, vmlaldavxq)
- (vmlsldavq, vmlsldavxq): New.
- * config/arm/arm-mve-builtins-base.h (vmlaldavq, vmlaldavxq)
- (vmlsldavq, vmlsldavxq): New.
- * config/arm/arm_mve.h (vmlaldavq): Remove.
- (vmlsldavxq): Remove.
- (vmlsldavq): Remove.
- (vmlaldavxq): Remove.
- (vmlaldavq_p): Remove.
- (vmlaldavxq_p): Remove.
- (vmlsldavq_p): Remove.
- (vmlsldavxq_p): Remove.
- (vmlaldavq_u16): Remove.
- (vmlsldavxq_s16): Remove.
- (vmlsldavq_s16): Remove.
- (vmlaldavxq_s16): Remove.
- (vmlaldavq_s16): Remove.
- (vmlaldavq_u32): Remove.
- (vmlsldavxq_s32): Remove.
- (vmlsldavq_s32): Remove.
- (vmlaldavxq_s32): Remove.
- (vmlaldavq_s32): Remove.
- (vmlaldavq_p_s16): Remove.
- (vmlaldavxq_p_s16): Remove.
- (vmlsldavq_p_s16): Remove.
- (vmlsldavxq_p_s16): Remove.
- (vmlaldavq_p_u16): Remove.
- (vmlaldavq_p_s32): Remove.
- (vmlaldavxq_p_s32): Remove.
- (vmlsldavq_p_s32): Remove.
- (vmlsldavxq_p_s32): Remove.
- (vmlaldavq_p_u32): Remove.
- (__arm_vmlaldavq_u16): Remove.
- (__arm_vmlsldavxq_s16): Remove.
- (__arm_vmlsldavq_s16): Remove.
- (__arm_vmlaldavxq_s16): Remove.
- (__arm_vmlaldavq_s16): Remove.
- (__arm_vmlaldavq_u32): Remove.
- (__arm_vmlsldavxq_s32): Remove.
- (__arm_vmlsldavq_s32): Remove.
- (__arm_vmlaldavxq_s32): Remove.
- (__arm_vmlaldavq_s32): Remove.
- (__arm_vmlaldavq_p_s16): Remove.
- (__arm_vmlaldavxq_p_s16): Remove.
- (__arm_vmlsldavq_p_s16): Remove.
- (__arm_vmlsldavxq_p_s16): Remove.
- (__arm_vmlaldavq_p_u16): Remove.
- (__arm_vmlaldavq_p_s32): Remove.
- (__arm_vmlaldavxq_p_s32): Remove.
- (__arm_vmlsldavq_p_s32): Remove.
- (__arm_vmlsldavxq_p_s32): Remove.
- (__arm_vmlaldavq_p_u32): Remove.
- (__arm_vmlaldavq): Remove.
- (__arm_vmlsldavxq): Remove.
- (__arm_vmlsldavq): Remove.
- (__arm_vmlaldavxq): Remove.
- (__arm_vmlaldavq_p): Remove.
- (__arm_vmlaldavxq_p): Remove.
- (__arm_vmlsldavq_p): Remove.
- (__arm_vmlsldavxq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VMLxLDAVxQ, MVE_VMLxLDAVxQ_P): New.
- (mve_insn): Add vmlaldav, vmlaldavx, vmlsldav, vmlsldavx.
- (supf): Add VMLALDAVXQ_S, VMLSLDAVQ_S, VMLSLDAVXQ_S,
- VMLALDAVXQ_P_S, VMLSLDAVQ_P_S, VMLSLDAVXQ_P_S.
- * config/arm/mve.md (mve_vmlaldavq_<supf><mode>)
- (mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
- (mve_vmlsldavxq_s<mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vmlaldavq_p_<supf><mode>, mve_vmlaldavxq_p_s<mode>)
- (mve_vmlsldavq_p_s<mode>, mve_vmlsldavxq_p_s<mode>): Merge into
- ...
- (@mve_<mve_insn>q_p_<supf><mode>): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_acc_int64): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_acc_int64): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vabavq): New.
- * config/arm/arm-mve-builtins-base.def (vabavq): New.
- * config/arm/arm-mve-builtins-base.h (vabavq): New.
- * config/arm/arm_mve.h (vabavq): Remove.
- (vabavq_p): Remove.
- (vabavq_s8): Remove.
- (vabavq_s16): Remove.
- (vabavq_s32): Remove.
- (vabavq_u8): Remove.
- (vabavq_u16): Remove.
- (vabavq_u32): Remove.
- (vabavq_p_s8): Remove.
- (vabavq_p_u8): Remove.
- (vabavq_p_s16): Remove.
- (vabavq_p_u16): Remove.
- (vabavq_p_s32): Remove.
- (vabavq_p_u32): Remove.
- (__arm_vabavq_s8): Remove.
- (__arm_vabavq_s16): Remove.
- (__arm_vabavq_s32): Remove.
- (__arm_vabavq_u8): Remove.
- (__arm_vabavq_u16): Remove.
- (__arm_vabavq_u32): Remove.
- (__arm_vabavq_p_s8): Remove.
- (__arm_vabavq_p_u8): Remove.
- (__arm_vabavq_p_s16): Remove.
- (__arm_vabavq_p_u16): Remove.
- (__arm_vabavq_p_s32): Remove.
- (__arm_vabavq_p_u32): Remove.
- (__arm_vabavq): Remove.
- (__arm_vabavq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vabav.
- * config/arm/mve.md (mve_vabavq_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this,.
- (mve_vabavq_p_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_p_<supf><mode>): ... this,.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmladavaxq, vmladavaq)
- (vmlsdavaq, vmlsdavaxq): New.
- * config/arm/arm-mve-builtins-base.def (vmladavaxq, vmladavaq)
- (vmlsdavaq, vmlsdavaxq): New.
- * config/arm/arm-mve-builtins-base.h (vmladavaxq, vmladavaq)
- (vmlsdavaq, vmlsdavaxq): New.
- * config/arm/arm_mve.h (vmladavaq): Remove.
- (vmlsdavaxq): Remove.
- (vmlsdavaq): Remove.
- (vmladavaxq): Remove.
- (vmladavaq_p): Remove.
- (vmladavaxq_p): Remove.
- (vmlsdavaq_p): Remove.
- (vmlsdavaxq_p): Remove.
- (vmladavaq_u8): Remove.
- (vmlsdavaxq_s8): Remove.
- (vmlsdavaq_s8): Remove.
- (vmladavaxq_s8): Remove.
- (vmladavaq_s8): Remove.
- (vmladavaq_u16): Remove.
- (vmlsdavaxq_s16): Remove.
- (vmlsdavaq_s16): Remove.
- (vmladavaxq_s16): Remove.
- (vmladavaq_s16): Remove.
- (vmladavaq_u32): Remove.
- (vmlsdavaxq_s32): Remove.
- (vmlsdavaq_s32): Remove.
- (vmladavaxq_s32): Remove.
- (vmladavaq_s32): Remove.
- (vmladavaq_p_s8): Remove.
- (vmladavaq_p_s32): Remove.
- (vmladavaq_p_s16): Remove.
- (vmladavaq_p_u8): Remove.
- (vmladavaq_p_u32): Remove.
- (vmladavaq_p_u16): Remove.
- (vmladavaxq_p_s8): Remove.
- (vmladavaxq_p_s32): Remove.
- (vmladavaxq_p_s16): Remove.
- (vmlsdavaq_p_s8): Remove.
- (vmlsdavaq_p_s32): Remove.
- (vmlsdavaq_p_s16): Remove.
- (vmlsdavaxq_p_s8): Remove.
- (vmlsdavaxq_p_s32): Remove.
- (vmlsdavaxq_p_s16): Remove.
- (__arm_vmladavaq_u8): Remove.
- (__arm_vmlsdavaxq_s8): Remove.
- (__arm_vmlsdavaq_s8): Remove.
- (__arm_vmladavaxq_s8): Remove.
- (__arm_vmladavaq_s8): Remove.
- (__arm_vmladavaq_u16): Remove.
- (__arm_vmlsdavaxq_s16): Remove.
- (__arm_vmlsdavaq_s16): Remove.
- (__arm_vmladavaxq_s16): Remove.
- (__arm_vmladavaq_s16): Remove.
- (__arm_vmladavaq_u32): Remove.
- (__arm_vmlsdavaxq_s32): Remove.
- (__arm_vmlsdavaq_s32): Remove.
- (__arm_vmladavaxq_s32): Remove.
- (__arm_vmladavaq_s32): Remove.
- (__arm_vmladavaq_p_s8): Remove.
- (__arm_vmladavaq_p_s32): Remove.
- (__arm_vmladavaq_p_s16): Remove.
- (__arm_vmladavaq_p_u8): Remove.
- (__arm_vmladavaq_p_u32): Remove.
- (__arm_vmladavaq_p_u16): Remove.
- (__arm_vmladavaxq_p_s8): Remove.
- (__arm_vmladavaxq_p_s32): Remove.
- (__arm_vmladavaxq_p_s16): Remove.
- (__arm_vmlsdavaq_p_s8): Remove.
- (__arm_vmlsdavaq_p_s32): Remove.
- (__arm_vmlsdavaq_p_s16): Remove.
- (__arm_vmlsdavaxq_p_s8): Remove.
- (__arm_vmlsdavaxq_p_s32): Remove.
- (__arm_vmlsdavaxq_p_s16): Remove.
- (__arm_vmladavaq): Remove.
- (__arm_vmlsdavaxq): Remove.
- (__arm_vmlsdavaq): Remove.
- (__arm_vmladavaxq): Remove.
- (__arm_vmladavaq_p): Remove.
- (__arm_vmladavaxq_p): Remove.
- (__arm_vmlsdavaq_p): Remove.
- (__arm_vmlsdavaxq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_acca_int32): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_acca_int32): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmladavq, vmladavxq)
- (vmlsdavq, vmlsdavxq): New.
- * config/arm/arm-mve-builtins-base.def (vmladavq, vmladavxq)
- (vmlsdavq, vmlsdavxq): New.
- * config/arm/arm-mve-builtins-base.h (vmladavq, vmladavxq)
- (vmlsdavq, vmlsdavxq): New.
- * config/arm/arm_mve.h (vmladavq): Remove.
- (vmlsdavxq): Remove.
- (vmlsdavq): Remove.
- (vmladavxq): Remove.
- (vmladavq_p): Remove.
- (vmlsdavxq_p): Remove.
- (vmlsdavq_p): Remove.
- (vmladavxq_p): Remove.
- (vmladavq_u8): Remove.
- (vmlsdavxq_s8): Remove.
- (vmlsdavq_s8): Remove.
- (vmladavxq_s8): Remove.
- (vmladavq_s8): Remove.
- (vmladavq_u16): Remove.
- (vmlsdavxq_s16): Remove.
- (vmlsdavq_s16): Remove.
- (vmladavxq_s16): Remove.
- (vmladavq_s16): Remove.
- (vmladavq_u32): Remove.
- (vmlsdavxq_s32): Remove.
- (vmlsdavq_s32): Remove.
- (vmladavxq_s32): Remove.
- (vmladavq_s32): Remove.
- (vmladavq_p_u8): Remove.
- (vmlsdavxq_p_s8): Remove.
- (vmlsdavq_p_s8): Remove.
- (vmladavxq_p_s8): Remove.
- (vmladavq_p_s8): Remove.
- (vmladavq_p_u16): Remove.
- (vmlsdavxq_p_s16): Remove.
- (vmlsdavq_p_s16): Remove.
- (vmladavxq_p_s16): Remove.
- (vmladavq_p_s16): Remove.
- (vmladavq_p_u32): Remove.
- (vmlsdavxq_p_s32): Remove.
- (vmlsdavq_p_s32): Remove.
- (vmladavxq_p_s32): Remove.
- (vmladavq_p_s32): Remove.
- (__arm_vmladavq_u8): Remove.
- (__arm_vmlsdavxq_s8): Remove.
- (__arm_vmlsdavq_s8): Remove.
- (__arm_vmladavxq_s8): Remove.
- (__arm_vmladavq_s8): Remove.
- (__arm_vmladavq_u16): Remove.
- (__arm_vmlsdavxq_s16): Remove.
- (__arm_vmlsdavq_s16): Remove.
- (__arm_vmladavxq_s16): Remove.
- (__arm_vmladavq_s16): Remove.
- (__arm_vmladavq_u32): Remove.
- (__arm_vmlsdavxq_s32): Remove.
- (__arm_vmlsdavq_s32): Remove.
- (__arm_vmladavxq_s32): Remove.
- (__arm_vmladavq_s32): Remove.
- (__arm_vmladavq_p_u8): Remove.
- (__arm_vmlsdavxq_p_s8): Remove.
- (__arm_vmlsdavq_p_s8): Remove.
- (__arm_vmladavxq_p_s8): Remove.
- (__arm_vmladavq_p_s8): Remove.
- (__arm_vmladavq_p_u16): Remove.
- (__arm_vmlsdavxq_p_s16): Remove.
- (__arm_vmlsdavq_p_s16): Remove.
- (__arm_vmladavxq_p_s16): Remove.
- (__arm_vmladavq_p_s16): Remove.
- (__arm_vmladavq_p_u32): Remove.
- (__arm_vmlsdavxq_p_s32): Remove.
- (__arm_vmlsdavq_p_s32): Remove.
- (__arm_vmladavxq_p_s32): Remove.
- (__arm_vmladavq_p_s32): Remove.
- (__arm_vmladavq): Remove.
- (__arm_vmlsdavxq): Remove.
- (__arm_vmlsdavq): Remove.
- (__arm_vmladavxq): Remove.
- (__arm_vmladavq_p): Remove.
- (__arm_vmlsdavxq_p): Remove.
- (__arm_vmlsdavq_p): Remove.
- (__arm_vmladavxq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VMLxDAVQ, MVE_VMLxDAVQ_P)
- (MVE_VMLxDAVAQ, MVE_VMLxDAVAQ_P): New.
- (mve_insn): Add vmladava, vmladavax, vmladav, vmladavx, vmlsdava,
- vmlsdavax, vmlsdav, vmlsdavx.
- (supf): Add VMLADAVAXQ_P_S, VMLADAVAXQ_S, VMLADAVXQ_P_S,
- VMLADAVXQ_S, VMLSDAVAQ_P_S, VMLSDAVAQ_S, VMLSDAVAXQ_P_S,
- VMLSDAVAXQ_S, VMLSDAVQ_P_S, VMLSDAVQ_S, VMLSDAVXQ_P_S,
- VMLSDAVXQ_S.
- * config/arm/mve.md (mve_vmladavq_<supf><mode>)
- (mve_vmladavxq_s<mode>, mve_vmlsdavq_s<mode>)
- (mve_vmlsdavxq_s<mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vmlsdavaq_s<mode>, mve_vmladavaxq_s<mode>)
- (mve_vmlsdavaxq_s<mode>, mve_vmladavaq_<supf><mode>): Merge into
- ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vmladavq_p_<supf><mode>, mve_vmladavxq_p_s<mode>)
- (mve_vmlsdavq_p_s<mode>, mve_vmlsdavxq_p_s<mode>): Merge into ...
- (@mve_<mve_insn>q_p_<supf><mode>): ... this.
- (mve_vmladavaq_p_<supf><mode>, mve_vmladavaxq_p_s<mode>)
- (mve_vmlsdavaq_p_s<mode>, mve_vmlsdavaxq_p_s<mode>): Merge into
- ...
- (@mve_<mve_insn>q_p_<supf><mode>): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_acc_int32): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_acc_int32): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vaddlvaq): New.
- * config/arm/arm-mve-builtins-base.def (vaddlvaq): New.
- * config/arm/arm-mve-builtins-base.h (vaddlvaq): New.
- * config/arm/arm_mve.h (vaddlvaq): Remove.
- (vaddlvaq_p): Remove.
- (vaddlvaq_u32): Remove.
- (vaddlvaq_s32): Remove.
- (vaddlvaq_p_s32): Remove.
- (vaddlvaq_p_u32): Remove.
- (__arm_vaddlvaq_u32): Remove.
- (__arm_vaddlvaq_s32): Remove.
- (__arm_vaddlvaq_p_s32): Remove.
- (__arm_vaddlvaq_p_u32): Remove.
- (__arm_vaddlvaq): Remove.
- (__arm_vaddlvaq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (unary_widen_acc): New.
- * config/arm/arm-mve-builtins-shapes.h (unary_widen_acc): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vaddlva.
- * config/arm/mve.md (mve_vaddlvaq_<supf>v4si): Rename into ...
- (@mve_<mve_insn>q_<supf>v4si): ... this.
- (mve_vaddlvaq_p_<supf>v4si): Rename into ...
- (@mve_<mve_insn>q_p_<supf>v4si): ... this.
-
-2023-05-11 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/109807
- * config/i386/i386.cc (ix86_widen_mult_cost):
- Handle V4HImode and V2SImode.
-
-2023-05-11 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-dce.cc (simple_dce_from_worklist): For ssa names
- defined by a phi node with more than one uses, allow for the
- only uses are in that same defining statement.
-
-2023-05-11 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv.cc (riscv_const_insns): Add permissible
- vector constants.
-
-2023-05-11 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector.md: Add comments for simplifying to vmset.
-
-2023-05-11 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<optab><mode>3): Add scalar shift
+ * gdbhooks.py: Fix regex syntax.
+
+2024-02-16 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/113895
+ * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
+ consistency checking when there are out-of-bound array
+ accesses. Allow -1 off when from an array reference with
+ constant index.
+
+2024-02-16 Kito Cheng <kito.cheng@sifive.com>
+
+ PR target/106543
+ * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
pattern.
- (v<optab><mode>3): Add vector shift pattern.
- * config/riscv/vector-iterators.md: New iterator.
-
-2023-05-11 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md: Use renamed functions.
- * config/riscv/riscv-protos.h (emit_vlmax_op): Rename.
- (emit_vlmax_reg_op): To this.
- (emit_nonvlmax_op): Rename.
- (emit_len_op): To this.
- (emit_nonvlmax_binop): Rename.
- (emit_len_binop): To this.
- * config/riscv/riscv-v.cc (emit_pred_op): Add default parameter.
- (emit_pred_binop): Remove vlmax_p.
- (emit_vlmax_op): Rename.
- (emit_vlmax_reg_op): To this.
- (emit_nonvlmax_op): Rename.
- (emit_len_op): To this.
- (emit_nonvlmax_binop): Rename.
- (emit_len_binop): To this.
- (sew64_scalar_helper): Use renamed functions.
- (expand_tuple_move): Use renamed functions.
- * config/riscv/riscv.cc (vector_zero_call_used_regs): Use
- renamed functions.
- * config/riscv/vector.md: Use renamed functions.
-
-2023-05-11 Robin Dapp <rdapp@ventanamicro.com>
- Michael Collison <collison@rivosinc.com>
-
- * config/riscv/autovec.md (<optab><mode>3): Add integer binops.
- * config/riscv/riscv-protos.h (emit_nonvlmax_binop): Declare.
- * config/riscv/riscv-v.cc (emit_pred_op): New function.
- (set_expander_dest_and_mask): New function.
- (emit_pred_binop): New function.
- (emit_nonvlmax_binop): New function.
-
-2023-05-11 Pan Li <pan2.li@intel.com>
-
- * cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR.
- * gimple-loop-interchange.cc
- (tree_loop_interchange::map_inductions_to_loop): Ditto.
- * tree-ssa-loop-ivcanon.cc (create_canonical_iv): Ditto.
- * tree-ssa-loop-ivopts.cc (create_new_iv): Ditto.
- * tree-ssa-loop-manip.cc (create_iv): Ditto.
- (tree_transform_and_unroll_loop): Ditto.
- (canonicalize_loop_ivs): Ditto.
- * tree-ssa-loop-manip.h (create_iv): Ditto.
- * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Ditto.
- * tree-vect-loop-manip.cc (vect_set_loop_controls_directly):
- Ditto.
- (vect_set_loop_condition_normal): Ditto.
- * tree-vect-loop.cc (vect_create_epilog_for_reduction): Ditto.
- * tree-vect-stmts.cc (vectorizable_store): Ditto.
- (vectorizable_load): Ditto.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmovlbq, vmovltq): New.
- * config/arm/arm-mve-builtins-base.def (vmovlbq, vmovltq): New.
- * config/arm/arm-mve-builtins-base.h (vmovlbq, vmovltq): New.
- * config/arm/arm_mve.h (vmovlbq): Remove.
- (vmovltq): Remove.
- (vmovlbq_m): Remove.
- (vmovltq_m): Remove.
- (vmovlbq_x): Remove.
- (vmovltq_x): Remove.
- (vmovlbq_s8): Remove.
- (vmovlbq_s16): Remove.
- (vmovltq_s8): Remove.
- (vmovltq_s16): Remove.
- (vmovltq_u8): Remove.
- (vmovltq_u16): Remove.
- (vmovlbq_u8): Remove.
- (vmovlbq_u16): Remove.
- (vmovlbq_m_s8): Remove.
- (vmovltq_m_s8): Remove.
- (vmovlbq_m_u8): Remove.
- (vmovltq_m_u8): Remove.
- (vmovlbq_m_s16): Remove.
- (vmovltq_m_s16): Remove.
- (vmovlbq_m_u16): Remove.
- (vmovltq_m_u16): Remove.
- (vmovlbq_x_s8): Remove.
- (vmovlbq_x_s16): Remove.
- (vmovlbq_x_u8): Remove.
- (vmovlbq_x_u16): Remove.
- (vmovltq_x_s8): Remove.
- (vmovltq_x_s16): Remove.
- (vmovltq_x_u8): Remove.
- (vmovltq_x_u16): Remove.
- (__arm_vmovlbq_s8): Remove.
- (__arm_vmovlbq_s16): Remove.
- (__arm_vmovltq_s8): Remove.
- (__arm_vmovltq_s16): Remove.
- (__arm_vmovltq_u8): Remove.
- (__arm_vmovltq_u16): Remove.
- (__arm_vmovlbq_u8): Remove.
- (__arm_vmovlbq_u16): Remove.
- (__arm_vmovlbq_m_s8): Remove.
- (__arm_vmovltq_m_s8): Remove.
- (__arm_vmovlbq_m_u8): Remove.
- (__arm_vmovltq_m_u8): Remove.
- (__arm_vmovlbq_m_s16): Remove.
- (__arm_vmovltq_m_s16): Remove.
- (__arm_vmovlbq_m_u16): Remove.
- (__arm_vmovltq_m_u16): Remove.
- (__arm_vmovlbq_x_s8): Remove.
- (__arm_vmovlbq_x_s16): Remove.
- (__arm_vmovlbq_x_u8): Remove.
- (__arm_vmovlbq_x_u16): Remove.
- (__arm_vmovltq_x_s8): Remove.
- (__arm_vmovltq_x_s16): Remove.
- (__arm_vmovltq_x_u8): Remove.
- (__arm_vmovltq_x_u16): Remove.
- (__arm_vmovlbq): Remove.
- (__arm_vmovltq): Remove.
- (__arm_vmovlbq_m): Remove.
- (__arm_vmovltq_m): Remove.
- (__arm_vmovlbq_x): Remove.
- (__arm_vmovltq_x): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (unary_widen): New.
- * config/arm/arm-mve-builtins-shapes.h (unary_widen): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vmovlb, vmovlt.
- (VMOVLBQ, VMOVLTQ): Merge into ...
- (VMOVLxQ): ... this.
- (VMOVLTQ_M, VMOVLBQ_M): Merge into ...
- (VMOVLxQ_M): ... this.
- * config/arm/mve.md (mve_vmovltq_<supf><mode>)
- (mve_vmovlbq_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vmovlbq_m_<supf><mode>, mve_vmovltq_m_<supf><mode>): Merge
- into ...
- (@mve_<mve_insn>q_m_<supf><mode>): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vaddlvq): New.
- * config/arm/arm-mve-builtins-base.def (vaddlvq): New.
- * config/arm/arm-mve-builtins-base.h (vaddlvq): New.
- * config/arm/arm-mve-builtins-functions.h
- (unspec_mve_function_exact_insn_pred_p): Handle vaddlvq.
- * config/arm/arm_mve.h (vaddlvq): Remove.
- (vaddlvq_p): Remove.
- (vaddlvq_s32): Remove.
- (vaddlvq_u32): Remove.
- (vaddlvq_p_s32): Remove.
- (vaddlvq_p_u32): Remove.
- (__arm_vaddlvq_s32): Remove.
- (__arm_vaddlvq_u32): Remove.
- (__arm_vaddlvq_p_s32): Remove.
- (__arm_vaddlvq_p_u32): Remove.
- (__arm_vaddlvq): Remove.
- (__arm_vaddlvq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vaddlv.
- * config/arm/mve.md (mve_vaddlvq_<supf>v4si): Rename into ...
- (@mve_<mve_insn>q_<supf>v4si): ... this.
- (mve_vaddlvq_p_<supf>v4si): Rename into ...
- (@mve_<mve_insn>q_p_<supf>v4si): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (unary_acc): New.
- * config/arm/arm-mve-builtins-shapes.h (unary_acc): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vaddvaq): New.
- * config/arm/arm-mve-builtins-base.def (vaddvaq): New.
- * config/arm/arm-mve-builtins-base.h (vaddvaq): New.
- * config/arm/arm_mve.h (vaddvaq): Remove.
- (vaddvaq_p): Remove.
- (vaddvaq_u8): Remove.
- (vaddvaq_s8): Remove.
- (vaddvaq_u16): Remove.
- (vaddvaq_s16): Remove.
- (vaddvaq_u32): Remove.
- (vaddvaq_s32): Remove.
- (vaddvaq_p_u8): Remove.
- (vaddvaq_p_s8): Remove.
- (vaddvaq_p_u16): Remove.
- (vaddvaq_p_s16): Remove.
- (vaddvaq_p_u32): Remove.
- (vaddvaq_p_s32): Remove.
- (__arm_vaddvaq_u8): Remove.
- (__arm_vaddvaq_s8): Remove.
- (__arm_vaddvaq_u16): Remove.
- (__arm_vaddvaq_s16): Remove.
- (__arm_vaddvaq_u32): Remove.
- (__arm_vaddvaq_s32): Remove.
- (__arm_vaddvaq_p_u8): Remove.
- (__arm_vaddvaq_p_s8): Remove.
- (__arm_vaddvaq_p_u16): Remove.
- (__arm_vaddvaq_p_s16): Remove.
- (__arm_vaddvaq_p_u32): Remove.
- (__arm_vaddvaq_p_s32): Remove.
- (__arm_vaddvaq): Remove.
- (__arm_vaddvaq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (unary_int32_acc): New.
- * config/arm/arm-mve-builtins-shapes.h (unary_int32_acc): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vaddva.
- * config/arm/mve.md (mve_vaddvaq_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vaddvaq_p_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_p_<supf><mode>): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vaddvq): New.
- * config/arm/arm-mve-builtins-base.def (vaddvq): New.
- * config/arm/arm-mve-builtins-base.h (vaddvq): New.
- * config/arm/arm_mve.h (vaddvq): Remove.
- (vaddvq_p): Remove.
- (vaddvq_s8): Remove.
- (vaddvq_s16): Remove.
- (vaddvq_s32): Remove.
- (vaddvq_u8): Remove.
- (vaddvq_u16): Remove.
- (vaddvq_u32): Remove.
- (vaddvq_p_u8): Remove.
- (vaddvq_p_s8): Remove.
- (vaddvq_p_u16): Remove.
- (vaddvq_p_s16): Remove.
- (vaddvq_p_u32): Remove.
- (vaddvq_p_s32): Remove.
- (__arm_vaddvq_s8): Remove.
- (__arm_vaddvq_s16): Remove.
- (__arm_vaddvq_s32): Remove.
- (__arm_vaddvq_u8): Remove.
- (__arm_vaddvq_u16): Remove.
- (__arm_vaddvq_u32): Remove.
- (__arm_vaddvq_p_u8): Remove.
- (__arm_vaddvq_p_s8): Remove.
- (__arm_vaddvq_p_u16): Remove.
- (__arm_vaddvq_p_s16): Remove.
- (__arm_vaddvq_p_u32): Remove.
- (__arm_vaddvq_p_s32): Remove.
- (__arm_vaddvq): Remove.
- (__arm_vaddvq_p): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (unary_int32): New.
- * config/arm/arm-mve-builtins-shapes.h (unary_int32): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vaddv.
- * config/arm/mve.md (@mve_vaddvq_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vaddvq_p_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_p_<supf><mode>): ... this.
- * config/arm/vec-common.md: Use gen_mve_q instead of
- gen_mve_vaddvq.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N): New.
- (vdupq): New.
- * config/arm/arm-mve-builtins-base.def (vdupq): New.
- * config/arm/arm-mve-builtins-base.h: (vdupq): New.
- * config/arm/arm_mve.h (vdupq_n): Remove.
- (vdupq_m): Remove.
- (vdupq_n_f16): Remove.
- (vdupq_n_f32): Remove.
- (vdupq_n_s8): Remove.
- (vdupq_n_s16): Remove.
- (vdupq_n_s32): Remove.
- (vdupq_n_u8): Remove.
- (vdupq_n_u16): Remove.
- (vdupq_n_u32): Remove.
- (vdupq_m_n_u8): Remove.
- (vdupq_m_n_s8): Remove.
- (vdupq_m_n_u16): Remove.
- (vdupq_m_n_s16): Remove.
- (vdupq_m_n_u32): Remove.
- (vdupq_m_n_s32): Remove.
- (vdupq_m_n_f16): Remove.
- (vdupq_m_n_f32): Remove.
- (vdupq_x_n_s8): Remove.
- (vdupq_x_n_s16): Remove.
- (vdupq_x_n_s32): Remove.
- (vdupq_x_n_u8): Remove.
- (vdupq_x_n_u16): Remove.
- (vdupq_x_n_u32): Remove.
- (vdupq_x_n_f16): Remove.
- (vdupq_x_n_f32): Remove.
- (__arm_vdupq_n_s8): Remove.
- (__arm_vdupq_n_s16): Remove.
- (__arm_vdupq_n_s32): Remove.
- (__arm_vdupq_n_u8): Remove.
- (__arm_vdupq_n_u16): Remove.
- (__arm_vdupq_n_u32): Remove.
- (__arm_vdupq_m_n_u8): Remove.
- (__arm_vdupq_m_n_s8): Remove.
- (__arm_vdupq_m_n_u16): Remove.
- (__arm_vdupq_m_n_s16): Remove.
- (__arm_vdupq_m_n_u32): Remove.
- (__arm_vdupq_m_n_s32): Remove.
- (__arm_vdupq_x_n_s8): Remove.
- (__arm_vdupq_x_n_s16): Remove.
- (__arm_vdupq_x_n_s32): Remove.
- (__arm_vdupq_x_n_u8): Remove.
- (__arm_vdupq_x_n_u16): Remove.
- (__arm_vdupq_x_n_u32): Remove.
- (__arm_vdupq_n_f16): Remove.
- (__arm_vdupq_n_f32): Remove.
- (__arm_vdupq_m_n_f16): Remove.
- (__arm_vdupq_m_n_f32): Remove.
- (__arm_vdupq_x_n_f16): Remove.
- (__arm_vdupq_x_n_f32): Remove.
- (__arm_vdupq_n): Remove.
- (__arm_vdupq_m): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (unary_n): New.
- * config/arm/arm-mve-builtins-shapes.h (unary_n): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_FP_M_N_VDUPQ_ONLY)
- (MVE_FP_N_VDUPQ_ONLY): New.
- (mve_insn): Add vdupq.
- * config/arm/mve.md (mve_vdupq_n_f<mode>): Rename into ...
- (@mve_<mve_insn>q_n_f<mode>): ... this.
- (mve_vdupq_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vdupq_m_n_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
- (mve_vdupq_m_n_f<mode>): Rename into ...
- (@mve_<mve_insn>q_m_n_f<mode>): ... this.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vrev16q, vrev32q, vrev64q):
- New.
- * config/arm/arm-mve-builtins-base.def (vrev16q, vrev32q)
- (vrev64q): New.
- * config/arm/arm-mve-builtins-base.h (vrev16q, vrev32q)
- (vrev64q): New.
- * config/arm/arm_mve.h (vrev16q): Remove.
- (vrev32q): Remove.
- (vrev64q): Remove.
- (vrev64q_m): Remove.
- (vrev16q_m): Remove.
- (vrev32q_m): Remove.
- (vrev16q_x): Remove.
- (vrev32q_x): Remove.
- (vrev64q_x): Remove.
- (vrev64q_f16): Remove.
- (vrev64q_f32): Remove.
- (vrev32q_f16): Remove.
- (vrev16q_s8): Remove.
- (vrev32q_s8): Remove.
- (vrev32q_s16): Remove.
- (vrev64q_s8): Remove.
- (vrev64q_s16): Remove.
- (vrev64q_s32): Remove.
- (vrev64q_u8): Remove.
- (vrev64q_u16): Remove.
- (vrev64q_u32): Remove.
- (vrev32q_u8): Remove.
- (vrev32q_u16): Remove.
- (vrev16q_u8): Remove.
- (vrev64q_m_u8): Remove.
- (vrev64q_m_s8): Remove.
- (vrev64q_m_u16): Remove.
- (vrev64q_m_s16): Remove.
- (vrev64q_m_u32): Remove.
- (vrev64q_m_s32): Remove.
- (vrev16q_m_s8): Remove.
- (vrev32q_m_f16): Remove.
- (vrev16q_m_u8): Remove.
- (vrev32q_m_s8): Remove.
- (vrev64q_m_f16): Remove.
- (vrev32q_m_u8): Remove.
- (vrev32q_m_s16): Remove.
- (vrev64q_m_f32): Remove.
- (vrev32q_m_u16): Remove.
- (vrev16q_x_s8): Remove.
- (vrev16q_x_u8): Remove.
- (vrev32q_x_s8): Remove.
- (vrev32q_x_s16): Remove.
- (vrev32q_x_u8): Remove.
- (vrev32q_x_u16): Remove.
- (vrev64q_x_s8): Remove.
- (vrev64q_x_s16): Remove.
- (vrev64q_x_s32): Remove.
- (vrev64q_x_u8): Remove.
- (vrev64q_x_u16): Remove.
- (vrev64q_x_u32): Remove.
- (vrev32q_x_f16): Remove.
- (vrev64q_x_f16): Remove.
- (vrev64q_x_f32): Remove.
- (__arm_vrev16q_s8): Remove.
- (__arm_vrev32q_s8): Remove.
- (__arm_vrev32q_s16): Remove.
- (__arm_vrev64q_s8): Remove.
- (__arm_vrev64q_s16): Remove.
- (__arm_vrev64q_s32): Remove.
- (__arm_vrev64q_u8): Remove.
- (__arm_vrev64q_u16): Remove.
- (__arm_vrev64q_u32): Remove.
- (__arm_vrev32q_u8): Remove.
- (__arm_vrev32q_u16): Remove.
- (__arm_vrev16q_u8): Remove.
- (__arm_vrev64q_m_u8): Remove.
- (__arm_vrev64q_m_s8): Remove.
- (__arm_vrev64q_m_u16): Remove.
- (__arm_vrev64q_m_s16): Remove.
- (__arm_vrev64q_m_u32): Remove.
- (__arm_vrev64q_m_s32): Remove.
- (__arm_vrev16q_m_s8): Remove.
- (__arm_vrev16q_m_u8): Remove.
- (__arm_vrev32q_m_s8): Remove.
- (__arm_vrev32q_m_u8): Remove.
- (__arm_vrev32q_m_s16): Remove.
- (__arm_vrev32q_m_u16): Remove.
- (__arm_vrev16q_x_s8): Remove.
- (__arm_vrev16q_x_u8): Remove.
- (__arm_vrev32q_x_s8): Remove.
- (__arm_vrev32q_x_s16): Remove.
- (__arm_vrev32q_x_u8): Remove.
- (__arm_vrev32q_x_u16): Remove.
- (__arm_vrev64q_x_s8): Remove.
- (__arm_vrev64q_x_s16): Remove.
- (__arm_vrev64q_x_s32): Remove.
- (__arm_vrev64q_x_u8): Remove.
- (__arm_vrev64q_x_u16): Remove.
- (__arm_vrev64q_x_u32): Remove.
- (__arm_vrev64q_f16): Remove.
- (__arm_vrev64q_f32): Remove.
- (__arm_vrev32q_f16): Remove.
- (__arm_vrev32q_m_f16): Remove.
- (__arm_vrev64q_m_f16): Remove.
- (__arm_vrev64q_m_f32): Remove.
- (__arm_vrev32q_x_f16): Remove.
- (__arm_vrev64q_x_f16): Remove.
- (__arm_vrev64q_x_f32): Remove.
- (__arm_vrev16q): Remove.
- (__arm_vrev32q): Remove.
- (__arm_vrev64q): Remove.
- (__arm_vrev64q_m): Remove.
- (__arm_vrev16q_m): Remove.
- (__arm_vrev32q_m): Remove.
- (__arm_vrev16q_x): Remove.
- (__arm_vrev32q_x): Remove.
- (__arm_vrev64q_x): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_V8HF, MVE_V16QI)
- (MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY)
- (MVE_FP_M_VREV32Q_ONLY): New iterators.
- (mve_insn): Add vrev16q, vrev32q, vrev64q.
- * config/arm/mve.md (mve_vrev64q_f<mode>): Rename into ...
- (@mve_<mve_insn>q_f<mode>): ... this
- (mve_vrev32q_fv8hf): Rename into @mve_<mve_insn>q_f<mode>.
- (mve_vrev64q_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vrev32q_<supf><mode>): Rename into
- @mve_<mve_insn>q_<supf><mode>.
- (mve_vrev16q_<supf>v16qi): Rename into
- @mve_<mve_insn>q_<supf><mode>.
- (mve_vrev64q_m_<supf><mode>): Rename into
- @mve_<mve_insn>q_m_<supf><mode>.
- (mve_vrev32q_m_fv8hf): Rename into @mve_<mve_insn>q_m_f<mode>.
- (mve_vrev32q_m_<supf><mode>): Rename into
- @mve_<mve_insn>q_m_<supf><mode>.
- (mve_vrev64q_m_f<mode>): Rename into @mve_<mve_insn>q_m_f<mode>.
- (mve_vrev16q_m_<supf>v16qi): Rename into
- @mve_<mve_insn>q_m_<supf><mode>.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vcmpeqq, vcmpneq, vcmpgeq)
- (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
- * config/arm/arm-mve-builtins-base.def (vcmpeqq, vcmpneq, vcmpgeq)
- (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
- * config/arm/arm-mve-builtins-base.h (vcmpeqq, vcmpneq, vcmpgeq)
- (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
- * config/arm/arm-mve-builtins-functions.h (class
- unspec_based_mve_function_exact_insn_vcmp): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vcmp.
- * config/arm/arm_mve.h (vcmpneq): Remove.
- (vcmphiq): Remove.
- (vcmpeqq): Remove.
- (vcmpcsq): Remove.
- (vcmpltq): Remove.
- (vcmpleq): Remove.
- (vcmpgtq): Remove.
- (vcmpgeq): Remove.
- (vcmpneq_m): Remove.
- (vcmphiq_m): Remove.
- (vcmpeqq_m): Remove.
- (vcmpcsq_m): Remove.
- (vcmpcsq_m_n): Remove.
- (vcmpltq_m): Remove.
- (vcmpleq_m): Remove.
- (vcmpgtq_m): Remove.
- (vcmpgeq_m): Remove.
- (vcmpneq_s8): Remove.
- (vcmpneq_s16): Remove.
- (vcmpneq_s32): Remove.
- (vcmpneq_u8): Remove.
- (vcmpneq_u16): Remove.
- (vcmpneq_u32): Remove.
- (vcmpneq_n_u8): Remove.
- (vcmphiq_u8): Remove.
- (vcmphiq_n_u8): Remove.
- (vcmpeqq_u8): Remove.
- (vcmpeqq_n_u8): Remove.
- (vcmpcsq_u8): Remove.
- (vcmpcsq_n_u8): Remove.
- (vcmpneq_n_s8): Remove.
- (vcmpltq_s8): Remove.
- (vcmpltq_n_s8): Remove.
- (vcmpleq_s8): Remove.
- (vcmpleq_n_s8): Remove.
- (vcmpgtq_s8): Remove.
- (vcmpgtq_n_s8): Remove.
- (vcmpgeq_s8): Remove.
- (vcmpgeq_n_s8): Remove.
- (vcmpeqq_s8): Remove.
- (vcmpeqq_n_s8): Remove.
- (vcmpneq_n_u16): Remove.
- (vcmphiq_u16): Remove.
- (vcmphiq_n_u16): Remove.
- (vcmpeqq_u16): Remove.
- (vcmpeqq_n_u16): Remove.
- (vcmpcsq_u16): Remove.
- (vcmpcsq_n_u16): Remove.
- (vcmpneq_n_s16): Remove.
- (vcmpltq_s16): Remove.
- (vcmpltq_n_s16): Remove.
- (vcmpleq_s16): Remove.
- (vcmpleq_n_s16): Remove.
- (vcmpgtq_s16): Remove.
- (vcmpgtq_n_s16): Remove.
- (vcmpgeq_s16): Remove.
- (vcmpgeq_n_s16): Remove.
- (vcmpeqq_s16): Remove.
- (vcmpeqq_n_s16): Remove.
- (vcmpneq_n_u32): Remove.
- (vcmphiq_u32): Remove.
- (vcmphiq_n_u32): Remove.
- (vcmpeqq_u32): Remove.
- (vcmpeqq_n_u32): Remove.
- (vcmpcsq_u32): Remove.
- (vcmpcsq_n_u32): Remove.
- (vcmpneq_n_s32): Remove.
- (vcmpltq_s32): Remove.
- (vcmpltq_n_s32): Remove.
- (vcmpleq_s32): Remove.
- (vcmpleq_n_s32): Remove.
- (vcmpgtq_s32): Remove.
- (vcmpgtq_n_s32): Remove.
- (vcmpgeq_s32): Remove.
- (vcmpgeq_n_s32): Remove.
- (vcmpeqq_s32): Remove.
- (vcmpeqq_n_s32): Remove.
- (vcmpneq_n_f16): Remove.
- (vcmpneq_f16): Remove.
- (vcmpltq_n_f16): Remove.
- (vcmpltq_f16): Remove.
- (vcmpleq_n_f16): Remove.
- (vcmpleq_f16): Remove.
- (vcmpgtq_n_f16): Remove.
- (vcmpgtq_f16): Remove.
- (vcmpgeq_n_f16): Remove.
- (vcmpgeq_f16): Remove.
- (vcmpeqq_n_f16): Remove.
- (vcmpeqq_f16): Remove.
- (vcmpneq_n_f32): Remove.
- (vcmpneq_f32): Remove.
- (vcmpltq_n_f32): Remove.
- (vcmpltq_f32): Remove.
- (vcmpleq_n_f32): Remove.
- (vcmpleq_f32): Remove.
- (vcmpgtq_n_f32): Remove.
- (vcmpgtq_f32): Remove.
- (vcmpgeq_n_f32): Remove.
- (vcmpgeq_f32): Remove.
- (vcmpeqq_n_f32): Remove.
- (vcmpeqq_f32): Remove.
- (vcmpeqq_m_f16): Remove.
- (vcmpeqq_m_f32): Remove.
- (vcmpneq_m_u8): Remove.
- (vcmpneq_m_n_u8): Remove.
- (vcmphiq_m_u8): Remove.
- (vcmphiq_m_n_u8): Remove.
- (vcmpeqq_m_u8): Remove.
- (vcmpeqq_m_n_u8): Remove.
- (vcmpcsq_m_u8): Remove.
- (vcmpcsq_m_n_u8): Remove.
- (vcmpneq_m_s8): Remove.
- (vcmpneq_m_n_s8): Remove.
- (vcmpltq_m_s8): Remove.
- (vcmpltq_m_n_s8): Remove.
- (vcmpleq_m_s8): Remove.
- (vcmpleq_m_n_s8): Remove.
- (vcmpgtq_m_s8): Remove.
- (vcmpgtq_m_n_s8): Remove.
- (vcmpgeq_m_s8): Remove.
- (vcmpgeq_m_n_s8): Remove.
- (vcmpeqq_m_s8): Remove.
- (vcmpeqq_m_n_s8): Remove.
- (vcmpneq_m_u16): Remove.
- (vcmpneq_m_n_u16): Remove.
- (vcmphiq_m_u16): Remove.
- (vcmphiq_m_n_u16): Remove.
- (vcmpeqq_m_u16): Remove.
- (vcmpeqq_m_n_u16): Remove.
- (vcmpcsq_m_u16): Remove.
- (vcmpcsq_m_n_u16): Remove.
- (vcmpneq_m_s16): Remove.
- (vcmpneq_m_n_s16): Remove.
- (vcmpltq_m_s16): Remove.
- (vcmpltq_m_n_s16): Remove.
- (vcmpleq_m_s16): Remove.
- (vcmpleq_m_n_s16): Remove.
- (vcmpgtq_m_s16): Remove.
- (vcmpgtq_m_n_s16): Remove.
- (vcmpgeq_m_s16): Remove.
- (vcmpgeq_m_n_s16): Remove.
- (vcmpeqq_m_s16): Remove.
- (vcmpeqq_m_n_s16): Remove.
- (vcmpneq_m_u32): Remove.
- (vcmpneq_m_n_u32): Remove.
- (vcmphiq_m_u32): Remove.
- (vcmphiq_m_n_u32): Remove.
- (vcmpeqq_m_u32): Remove.
- (vcmpeqq_m_n_u32): Remove.
- (vcmpcsq_m_u32): Remove.
- (vcmpcsq_m_n_u32): Remove.
- (vcmpneq_m_s32): Remove.
- (vcmpneq_m_n_s32): Remove.
- (vcmpltq_m_s32): Remove.
- (vcmpltq_m_n_s32): Remove.
- (vcmpleq_m_s32): Remove.
- (vcmpleq_m_n_s32): Remove.
- (vcmpgtq_m_s32): Remove.
- (vcmpgtq_m_n_s32): Remove.
- (vcmpgeq_m_s32): Remove.
- (vcmpgeq_m_n_s32): Remove.
- (vcmpeqq_m_s32): Remove.
- (vcmpeqq_m_n_s32): Remove.
- (vcmpeqq_m_n_f16): Remove.
- (vcmpgeq_m_f16): Remove.
- (vcmpgeq_m_n_f16): Remove.
- (vcmpgtq_m_f16): Remove.
- (vcmpgtq_m_n_f16): Remove.
- (vcmpleq_m_f16): Remove.
- (vcmpleq_m_n_f16): Remove.
- (vcmpltq_m_f16): Remove.
- (vcmpltq_m_n_f16): Remove.
- (vcmpneq_m_f16): Remove.
- (vcmpneq_m_n_f16): Remove.
- (vcmpeqq_m_n_f32): Remove.
- (vcmpgeq_m_f32): Remove.
- (vcmpgeq_m_n_f32): Remove.
- (vcmpgtq_m_f32): Remove.
- (vcmpgtq_m_n_f32): Remove.
- (vcmpleq_m_f32): Remove.
- (vcmpleq_m_n_f32): Remove.
- (vcmpltq_m_f32): Remove.
- (vcmpltq_m_n_f32): Remove.
- (vcmpneq_m_f32): Remove.
- (vcmpneq_m_n_f32): Remove.
- (__arm_vcmpneq_s8): Remove.
- (__arm_vcmpneq_s16): Remove.
- (__arm_vcmpneq_s32): Remove.
- (__arm_vcmpneq_u8): Remove.
- (__arm_vcmpneq_u16): Remove.
- (__arm_vcmpneq_u32): Remove.
- (__arm_vcmpneq_n_u8): Remove.
- (__arm_vcmphiq_u8): Remove.
- (__arm_vcmphiq_n_u8): Remove.
- (__arm_vcmpeqq_u8): Remove.
- (__arm_vcmpeqq_n_u8): Remove.
- (__arm_vcmpcsq_u8): Remove.
- (__arm_vcmpcsq_n_u8): Remove.
- (__arm_vcmpneq_n_s8): Remove.
- (__arm_vcmpltq_s8): Remove.
- (__arm_vcmpltq_n_s8): Remove.
- (__arm_vcmpleq_s8): Remove.
- (__arm_vcmpleq_n_s8): Remove.
- (__arm_vcmpgtq_s8): Remove.
- (__arm_vcmpgtq_n_s8): Remove.
- (__arm_vcmpgeq_s8): Remove.
- (__arm_vcmpgeq_n_s8): Remove.
- (__arm_vcmpeqq_s8): Remove.
- (__arm_vcmpeqq_n_s8): Remove.
- (__arm_vcmpneq_n_u16): Remove.
- (__arm_vcmphiq_u16): Remove.
- (__arm_vcmphiq_n_u16): Remove.
- (__arm_vcmpeqq_u16): Remove.
- (__arm_vcmpeqq_n_u16): Remove.
- (__arm_vcmpcsq_u16): Remove.
- (__arm_vcmpcsq_n_u16): Remove.
- (__arm_vcmpneq_n_s16): Remove.
- (__arm_vcmpltq_s16): Remove.
- (__arm_vcmpltq_n_s16): Remove.
- (__arm_vcmpleq_s16): Remove.
- (__arm_vcmpleq_n_s16): Remove.
- (__arm_vcmpgtq_s16): Remove.
- (__arm_vcmpgtq_n_s16): Remove.
- (__arm_vcmpgeq_s16): Remove.
- (__arm_vcmpgeq_n_s16): Remove.
- (__arm_vcmpeqq_s16): Remove.
- (__arm_vcmpeqq_n_s16): Remove.
- (__arm_vcmpneq_n_u32): Remove.
- (__arm_vcmphiq_u32): Remove.
- (__arm_vcmphiq_n_u32): Remove.
- (__arm_vcmpeqq_u32): Remove.
- (__arm_vcmpeqq_n_u32): Remove.
- (__arm_vcmpcsq_u32): Remove.
- (__arm_vcmpcsq_n_u32): Remove.
- (__arm_vcmpneq_n_s32): Remove.
- (__arm_vcmpltq_s32): Remove.
- (__arm_vcmpltq_n_s32): Remove.
- (__arm_vcmpleq_s32): Remove.
- (__arm_vcmpleq_n_s32): Remove.
- (__arm_vcmpgtq_s32): Remove.
- (__arm_vcmpgtq_n_s32): Remove.
- (__arm_vcmpgeq_s32): Remove.
- (__arm_vcmpgeq_n_s32): Remove.
- (__arm_vcmpeqq_s32): Remove.
- (__arm_vcmpeqq_n_s32): Remove.
- (__arm_vcmpneq_m_u8): Remove.
- (__arm_vcmpneq_m_n_u8): Remove.
- (__arm_vcmphiq_m_u8): Remove.
- (__arm_vcmphiq_m_n_u8): Remove.
- (__arm_vcmpeqq_m_u8): Remove.
- (__arm_vcmpeqq_m_n_u8): Remove.
- (__arm_vcmpcsq_m_u8): Remove.
- (__arm_vcmpcsq_m_n_u8): Remove.
- (__arm_vcmpneq_m_s8): Remove.
- (__arm_vcmpneq_m_n_s8): Remove.
- (__arm_vcmpltq_m_s8): Remove.
- (__arm_vcmpltq_m_n_s8): Remove.
- (__arm_vcmpleq_m_s8): Remove.
- (__arm_vcmpleq_m_n_s8): Remove.
- (__arm_vcmpgtq_m_s8): Remove.
- (__arm_vcmpgtq_m_n_s8): Remove.
- (__arm_vcmpgeq_m_s8): Remove.
- (__arm_vcmpgeq_m_n_s8): Remove.
- (__arm_vcmpeqq_m_s8): Remove.
- (__arm_vcmpeqq_m_n_s8): Remove.
- (__arm_vcmpneq_m_u16): Remove.
- (__arm_vcmpneq_m_n_u16): Remove.
- (__arm_vcmphiq_m_u16): Remove.
- (__arm_vcmphiq_m_n_u16): Remove.
- (__arm_vcmpeqq_m_u16): Remove.
- (__arm_vcmpeqq_m_n_u16): Remove.
- (__arm_vcmpcsq_m_u16): Remove.
- (__arm_vcmpcsq_m_n_u16): Remove.
- (__arm_vcmpneq_m_s16): Remove.
- (__arm_vcmpneq_m_n_s16): Remove.
- (__arm_vcmpltq_m_s16): Remove.
- (__arm_vcmpltq_m_n_s16): Remove.
- (__arm_vcmpleq_m_s16): Remove.
- (__arm_vcmpleq_m_n_s16): Remove.
- (__arm_vcmpgtq_m_s16): Remove.
- (__arm_vcmpgtq_m_n_s16): Remove.
- (__arm_vcmpgeq_m_s16): Remove.
- (__arm_vcmpgeq_m_n_s16): Remove.
- (__arm_vcmpeqq_m_s16): Remove.
- (__arm_vcmpeqq_m_n_s16): Remove.
- (__arm_vcmpneq_m_u32): Remove.
- (__arm_vcmpneq_m_n_u32): Remove.
- (__arm_vcmphiq_m_u32): Remove.
- (__arm_vcmphiq_m_n_u32): Remove.
- (__arm_vcmpeqq_m_u32): Remove.
- (__arm_vcmpeqq_m_n_u32): Remove.
- (__arm_vcmpcsq_m_u32): Remove.
- (__arm_vcmpcsq_m_n_u32): Remove.
- (__arm_vcmpneq_m_s32): Remove.
- (__arm_vcmpneq_m_n_s32): Remove.
- (__arm_vcmpltq_m_s32): Remove.
- (__arm_vcmpltq_m_n_s32): Remove.
- (__arm_vcmpleq_m_s32): Remove.
- (__arm_vcmpleq_m_n_s32): Remove.
- (__arm_vcmpgtq_m_s32): Remove.
- (__arm_vcmpgtq_m_n_s32): Remove.
- (__arm_vcmpgeq_m_s32): Remove.
- (__arm_vcmpgeq_m_n_s32): Remove.
- (__arm_vcmpeqq_m_s32): Remove.
- (__arm_vcmpeqq_m_n_s32): Remove.
- (__arm_vcmpneq_n_f16): Remove.
- (__arm_vcmpneq_f16): Remove.
- (__arm_vcmpltq_n_f16): Remove.
- (__arm_vcmpltq_f16): Remove.
- (__arm_vcmpleq_n_f16): Remove.
- (__arm_vcmpleq_f16): Remove.
- (__arm_vcmpgtq_n_f16): Remove.
- (__arm_vcmpgtq_f16): Remove.
- (__arm_vcmpgeq_n_f16): Remove.
- (__arm_vcmpgeq_f16): Remove.
- (__arm_vcmpeqq_n_f16): Remove.
- (__arm_vcmpeqq_f16): Remove.
- (__arm_vcmpneq_n_f32): Remove.
- (__arm_vcmpneq_f32): Remove.
- (__arm_vcmpltq_n_f32): Remove.
- (__arm_vcmpltq_f32): Remove.
- (__arm_vcmpleq_n_f32): Remove.
- (__arm_vcmpleq_f32): Remove.
- (__arm_vcmpgtq_n_f32): Remove.
- (__arm_vcmpgtq_f32): Remove.
- (__arm_vcmpgeq_n_f32): Remove.
- (__arm_vcmpgeq_f32): Remove.
- (__arm_vcmpeqq_n_f32): Remove.
- (__arm_vcmpeqq_f32): Remove.
- (__arm_vcmpeqq_m_f16): Remove.
- (__arm_vcmpeqq_m_f32): Remove.
- (__arm_vcmpeqq_m_n_f16): Remove.
- (__arm_vcmpgeq_m_f16): Remove.
- (__arm_vcmpgeq_m_n_f16): Remove.
- (__arm_vcmpgtq_m_f16): Remove.
- (__arm_vcmpgtq_m_n_f16): Remove.
- (__arm_vcmpleq_m_f16): Remove.
- (__arm_vcmpleq_m_n_f16): Remove.
- (__arm_vcmpltq_m_f16): Remove.
- (__arm_vcmpltq_m_n_f16): Remove.
- (__arm_vcmpneq_m_f16): Remove.
- (__arm_vcmpneq_m_n_f16): Remove.
- (__arm_vcmpeqq_m_n_f32): Remove.
- (__arm_vcmpgeq_m_f32): Remove.
- (__arm_vcmpgeq_m_n_f32): Remove.
- (__arm_vcmpgtq_m_f32): Remove.
- (__arm_vcmpgtq_m_n_f32): Remove.
- (__arm_vcmpleq_m_f32): Remove.
- (__arm_vcmpleq_m_n_f32): Remove.
- (__arm_vcmpltq_m_f32): Remove.
- (__arm_vcmpltq_m_n_f32): Remove.
- (__arm_vcmpneq_m_f32): Remove.
- (__arm_vcmpneq_m_n_f32): Remove.
- (__arm_vcmpneq): Remove.
- (__arm_vcmphiq): Remove.
- (__arm_vcmpeqq): Remove.
- (__arm_vcmpcsq): Remove.
- (__arm_vcmpltq): Remove.
- (__arm_vcmpleq): Remove.
- (__arm_vcmpgtq): Remove.
- (__arm_vcmpgeq): Remove.
- (__arm_vcmpneq_m): Remove.
- (__arm_vcmphiq_m): Remove.
- (__arm_vcmpeqq_m): Remove.
- (__arm_vcmpcsq_m): Remove.
- (__arm_vcmpltq_m): Remove.
- (__arm_vcmpleq_m): Remove.
- (__arm_vcmpgtq_m): Remove.
- (__arm_vcmpgeq_m): Remove.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (cmp): New.
- * config/arm/arm-mve-builtins-shapes.h (cmp): New.
-
-2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F, MVE_CMP_M_N)
- (MVE_CMP_M_N_F, mve_cmp_op1): New.
- (isu): Add VCMP*
- (supf): Likewise.
- * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>): Rename into ...
- (@mve_vcmp<mve_cmp_op>q_n_<mode>): ... this.
- (mve_vcmpeqq_m_f<mode>, mve_vcmpgeq_m_f<mode>)
- (mve_vcmpgtq_m_f<mode>, mve_vcmpleq_m_f<mode>)
- (mve_vcmpltq_m_f<mode>, mve_vcmpneq_m_f<mode>): Merge into ...
- (@mve_vcmp<mve_cmp_op1>q_m_f<mode>): ... this.
- (mve_vcmpcsq_m_u<mode>, mve_vcmpeqq_m_<supf><mode>)
- (mve_vcmpgeq_m_s<mode>, mve_vcmpgtq_m_s<mode>)
- (mve_vcmphiq_m_u<mode>, mve_vcmpleq_m_s<mode>)
- (mve_vcmpltq_m_s<mode>, mve_vcmpneq_m_<supf><mode>): Merge into
- ...
- (@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>): ... this.
- (mve_vcmpcsq_m_n_u<mode>, mve_vcmpeqq_m_n_<supf><mode>)
- (mve_vcmpgeq_m_n_s<mode>, mve_vcmpgtq_m_n_s<mode>)
- (mve_vcmphiq_m_n_u<mode>, mve_vcmpleq_m_n_s<mode>)
- (mve_vcmpltq_m_n_s<mode>, mve_vcmpneq_m_n_<supf><mode>): Merge
- into ...
- (@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>): ... this.
- (mve_vcmpeqq_m_n_f<mode>, mve_vcmpgeq_m_n_f<mode>)
- (mve_vcmpgtq_m_n_f<mode>, mve_vcmpleq_m_n_f<mode>)
- (mve_vcmpltq_m_n_f<mode>, mve_vcmpneq_m_n_f<mode>): Merge into ...
- (@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>): ... this.
-
-2023-05-11 Roger Sayle <roger@nextmovesoftware.com>
-
- * match.pd <popcount optimizations>: Simplify popcount(X|Y) +
- popcount(X&Y) as popcount(X)+popcount(Y). Likewise, simplify
- popcount(X)+popcount(Y)-popcount(X&Y) as popcount(X|Y), and
- vice versa.
-
-2023-05-11 Roger Sayle <roger@nextmovesoftware.com>
-
- * match.pd <popcount optimizations>: Simplify popcount(bswap(x))
- as popcount(x). Simplify popcount(rotate(x,y)) as popcount(x).
- <parity optimizations>: Simplify parity(bswap(x)) as parity(x).
- Simplify parity(rotate(x,y)) as parity(x).
-
-2023-05-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (@vec_series<mode>): New pattern
- * config/riscv/riscv-protos.h (expand_vec_series): New function.
- * config/riscv/riscv-v.cc (emit_binop): Ditto.
- (emit_index_op): Ditto.
- (expand_vec_series): Ditto.
- (expand_const_vector): Add series vector handling.
- * config/riscv/riscv.cc (riscv_const_insns): Enable series vector for testing.
-
-2023-05-10 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386.md (*concat<mode><dwi>3_1): Use preferred
- [(const_int 0)] idiom, instead of [(clobber (const_int 0))].
- (*concat<mode><dwi>3_2): Likewise.
- (*concat<mode><dwi>3_3): Likewise.
- (*concat<mode><dwi>3_4): Likewise.
- (*concat<mode><dwi>3_5): Likewise.
- (*concat<mode><dwi>3_6): Likewise.
- (*concat<mode><dwi>3_7): Likewise.
-
-2023-05-10 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/92658
- * config/i386/mmx.md (sse4_1_<code>v2qiv2si2): New insn pattern.
- (<insn>v4qiv4hi2): New expander.
- (<insn>v2hiv2si2): Ditto.
- (<insn>v2qiv2si2): Ditto.
- (<insn>v2qiv2hi2): Ditto.
-
-2023-05-10 Jeff Law <jlaw@ventanamicro>
-
- * config/h8300/constraints.md (Q): Make this a special memory
- constraint.
- (Zz): Similarly.
-
-2023-05-10 Jakub Jelinek <jakub@redhat.com>
-
- PR fortran/109788
- * ipa-prop.cc (ipa_get_callee_param_type): Don't return TREE_VALUE (t)
- if t is void_list_node.
-
-2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>_insn_le): Delete.
- (aarch64_sqmovun<mode>_insn_be): Delete.
- (aarch64_sqmovun<mode><vczle><vczbe>): New define_insn.
- (aarch64_sqmovun<mode>): Delete expander.
-
-2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_<PERMUTE:perm_insn><mode>):
- Rename to...
- (aarch64_<PERMUTE:perm_insn><mode><vczle><vczbe>): ... This.
- (aarch64_rev<REVERSE:rev_op><mode>): Rename to...
- (aarch64_rev<REVERSE:rev_op><mode><vczle><vczbe>): ... This.
-
-2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_<su_optab>q<addsub><mode>):
- Rename to...
- (aarch64_<su_optab>q<addsub><mode><vczle><vczbe>): ... This.
- (aarch64_<sur>qadd<mode>): Rename to...
- (aarch64_<sur>qadd<mode><vczle><vczbe>): ... This.
-
-2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md
- (aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): Delete.
- (aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): Delete.
- (aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): New define_insn.
- (aarch64_<sur>q<r>shr<u>n_n<mode>): Simplify expander.
-
-2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le): Delete.
- (aarch64_xtn<mode>_insn_be): Likewise.
- (trunc<mode><Vnarrowq>2): Rename to...
- (trunc<mode><Vnarrowq>2<vczle><vczbe>): ... This.
- (aarch64_xtn<mode>): Move under the above. Just emit the truncate RTL.
- (aarch64_<su>qmovn<mode>): Likewise.
- (aarch64_<su>qmovn<mode><vczle><vczbe>): New define_insn.
- (aarch64_<su>qmovn<mode>_insn_le): Delete.
- (aarch64_<su>qmovn<mode>_insn_be): Likewise.
-
-2023-05-10 Li Xu <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
- intruction replace null avl with (const_int 0).
-
-2023-05-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix
- incorrect codes.
-
-2023-05-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/109773
- * config/riscv/riscv-vsetvl.cc (avl_source_has_vsetvl_p): New function.
- (source_equal_p): Fix dead loop in vsetvl avl checking.
-
-2023-05-10 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.cc (cris_postdbr_cmpelim): Correct mode
- of modeadjusted_dccr.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmaxaq, vminaq): New.
- * config/arm/arm-mve-builtins-base.def (vmaxaq, vminaq): New.
- * config/arm/arm-mve-builtins-base.h (vmaxaq, vminaq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vmaxaq and
- vminaq.
- * config/arm/arm_mve.h (vminaq): Remove.
- (vmaxaq): Remove.
- (vminaq_m): Remove.
- (vmaxaq_m): Remove.
- (vminaq_s8): Remove.
- (vmaxaq_s8): Remove.
- (vminaq_s16): Remove.
- (vmaxaq_s16): Remove.
- (vminaq_s32): Remove.
- (vmaxaq_s32): Remove.
- (vminaq_m_s8): Remove.
- (vmaxaq_m_s8): Remove.
- (vminaq_m_s16): Remove.
- (vmaxaq_m_s16): Remove.
- (vminaq_m_s32): Remove.
- (vmaxaq_m_s32): Remove.
- (__arm_vminaq_s8): Remove.
- (__arm_vmaxaq_s8): Remove.
- (__arm_vminaq_s16): Remove.
- (__arm_vmaxaq_s16): Remove.
- (__arm_vminaq_s32): Remove.
- (__arm_vmaxaq_s32): Remove.
- (__arm_vminaq_m_s8): Remove.
- (__arm_vmaxaq_m_s8): Remove.
- (__arm_vminaq_m_s16): Remove.
- (__arm_vmaxaq_m_s16): Remove.
- (__arm_vminaq_m_s32): Remove.
- (__arm_vmaxaq_m_s32): Remove.
- (__arm_vminaq): Remove.
- (__arm_vmaxaq): Remove.
- (__arm_vminaq_m): Remove.
- (__arm_vmaxaq_m): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VMAXAVMINAQ, MVE_VMAXAVMINAQ_M):
- New.
- (mve_insn): Add vmaxa, vmina.
- (supf): Add VMAXAQ_S, VMAXAQ_M_S, VMINAQ_S, VMINAQ_M_S.
- * config/arm/mve.md (mve_vmaxaq_s<mode>, mve_vminaq_s<mode>):
- Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vmaxaq_m_s<mode>, mve_vminaq_m_s<mode>): Merge into ...
- (@mve_<mve_insn>q_m_<supf><mode>): ... this.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_maxamina): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_maxamina): New.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmaxnmaq, vminnmaq): New.
- * config/arm/arm-mve-builtins-base.def (vmaxnmaq, vminnmaq): New.
- * config/arm/arm-mve-builtins-base.h (vmaxnmaq, vminnmaq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vmaxnmaq and
- vminnmaq.
- * config/arm/arm_mve.h (vminnmaq): Remove.
- (vmaxnmaq): Remove.
- (vmaxnmaq_m): Remove.
- (vminnmaq_m): Remove.
- (vminnmaq_f16): Remove.
- (vmaxnmaq_f16): Remove.
- (vminnmaq_f32): Remove.
- (vmaxnmaq_f32): Remove.
- (vmaxnmaq_m_f16): Remove.
- (vminnmaq_m_f16): Remove.
- (vmaxnmaq_m_f32): Remove.
- (vminnmaq_m_f32): Remove.
- (__arm_vminnmaq_f16): Remove.
- (__arm_vmaxnmaq_f16): Remove.
- (__arm_vminnmaq_f32): Remove.
- (__arm_vmaxnmaq_f32): Remove.
- (__arm_vmaxnmaq_m_f16): Remove.
- (__arm_vminnmaq_m_f16): Remove.
- (__arm_vmaxnmaq_m_f32): Remove.
- (__arm_vminnmaq_m_f32): Remove.
- (__arm_vminnmaq): Remove.
- (__arm_vmaxnmaq): Remove.
- (__arm_vmaxnmaq_m): Remove.
- (__arm_vminnmaq_m): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VMAXNMA_VMINNMAQ)
- (MVE_VMAXNMA_VMINNMAQ_M): New.
- (mve_insn): Add vmaxnma, vminnma.
- * config/arm/mve.md (mve_vmaxnmaq_f<mode>, mve_vminnmaq_f<mode>):
- Merge into ...
- (@mve_<mve_insn>q_f<mode>): ... this.
- (mve_vmaxnmaq_m_f<mode>, mve_vminnmaq_m_f<mode>): Merge into ...
- (@mve_<mve_insn>q_m_f<mode>): ... this.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_F): New.
- (vmaxnmavq, vmaxnmvq, vminnmavq, vminnmvq): New.
- * config/arm/arm-mve-builtins-base.def (vmaxnmavq, vmaxnmvq)
- (vminnmavq, vminnmvq): New.
- * config/arm/arm-mve-builtins-base.h (vmaxnmavq, vmaxnmvq)
- (vminnmavq, vminnmvq): New.
- * config/arm/arm_mve.h (vminnmvq): Remove.
- (vminnmavq): Remove.
- (vmaxnmvq): Remove.
- (vmaxnmavq): Remove.
- (vmaxnmavq_p): Remove.
- (vmaxnmvq_p): Remove.
- (vminnmavq_p): Remove.
- (vminnmvq_p): Remove.
- (vminnmvq_f16): Remove.
- (vminnmavq_f16): Remove.
- (vmaxnmvq_f16): Remove.
- (vmaxnmavq_f16): Remove.
- (vminnmvq_f32): Remove.
- (vminnmavq_f32): Remove.
- (vmaxnmvq_f32): Remove.
- (vmaxnmavq_f32): Remove.
- (vmaxnmavq_p_f16): Remove.
- (vmaxnmvq_p_f16): Remove.
- (vminnmavq_p_f16): Remove.
- (vminnmvq_p_f16): Remove.
- (vmaxnmavq_p_f32): Remove.
- (vmaxnmvq_p_f32): Remove.
- (vminnmavq_p_f32): Remove.
- (vminnmvq_p_f32): Remove.
- (__arm_vminnmvq_f16): Remove.
- (__arm_vminnmavq_f16): Remove.
- (__arm_vmaxnmvq_f16): Remove.
- (__arm_vmaxnmavq_f16): Remove.
- (__arm_vminnmvq_f32): Remove.
- (__arm_vminnmavq_f32): Remove.
- (__arm_vmaxnmvq_f32): Remove.
- (__arm_vmaxnmavq_f32): Remove.
- (__arm_vmaxnmavq_p_f16): Remove.
- (__arm_vmaxnmvq_p_f16): Remove.
- (__arm_vminnmavq_p_f16): Remove.
- (__arm_vminnmvq_p_f16): Remove.
- (__arm_vmaxnmavq_p_f32): Remove.
- (__arm_vmaxnmvq_p_f32): Remove.
- (__arm_vminnmavq_p_f32): Remove.
- (__arm_vminnmvq_p_f32): Remove.
- (__arm_vminnmvq): Remove.
- (__arm_vminnmavq): Remove.
- (__arm_vmaxnmvq): Remove.
- (__arm_vmaxnmavq): Remove.
- (__arm_vmaxnmavq_p): Remove.
- (__arm_vmaxnmvq_p): Remove.
- (__arm_vminnmavq_p): Remove.
- (__arm_vminnmvq_p): Remove.
- (__arm_vmaxnmavq_m): Remove.
- (__arm_vmaxnmvq_m): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-functions.h
- (unspec_mve_function_exact_insn_pred_p): Use code_for_mve_q_p_f.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VMAXNMxV_MINNMxVQ)
- (MVE_VMAXNMxV_MINNMxVQ_P): New.
- (mve_insn): Add vmaxnmav, vmaxnmv, vminnmav, vminnmv.
- * config/arm/mve.md (mve_vmaxnmavq_f<mode>, mve_vmaxnmvq_f<mode>)
- (mve_vminnmavq_f<mode>, mve_vminnmvq_f<mode>): Merge into ...
- (@mve_<mve_insn>q_f<mode>): ... this.
- (mve_vmaxnmavq_p_f<mode>, mve_vmaxnmvq_p_f<mode>)
- (mve_vminnmavq_p_f<mode>, mve_vminnmvq_p_f<mode>): Merge into ...
- (@mve_<mve_insn>q_p_f<mode>): ... this.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmaxnmq, vminnmq): New.
- * config/arm/arm-mve-builtins-base.def (vmaxnmq, vminnmq): New.
- * config/arm/arm-mve-builtins-base.h (vmaxnmq, vminnmq): New.
- * config/arm/arm_mve.h (vminnmq): Remove.
- (vmaxnmq): Remove.
- (vmaxnmq_m): Remove.
- (vminnmq_m): Remove.
- (vminnmq_x): Remove.
- (vmaxnmq_x): Remove.
- (vminnmq_f16): Remove.
- (vmaxnmq_f16): Remove.
- (vminnmq_f32): Remove.
- (vmaxnmq_f32): Remove.
- (vmaxnmq_m_f32): Remove.
- (vmaxnmq_m_f16): Remove.
- (vminnmq_m_f32): Remove.
- (vminnmq_m_f16): Remove.
- (vminnmq_x_f16): Remove.
- (vminnmq_x_f32): Remove.
- (vmaxnmq_x_f16): Remove.
- (vmaxnmq_x_f32): Remove.
- (__arm_vminnmq_f16): Remove.
- (__arm_vmaxnmq_f16): Remove.
- (__arm_vminnmq_f32): Remove.
- (__arm_vmaxnmq_f32): Remove.
- (__arm_vmaxnmq_m_f32): Remove.
- (__arm_vmaxnmq_m_f16): Remove.
- (__arm_vminnmq_m_f32): Remove.
- (__arm_vminnmq_m_f16): Remove.
- (__arm_vminnmq_x_f16): Remove.
- (__arm_vminnmq_x_f32): Remove.
- (__arm_vmaxnmq_x_f16): Remove.
- (__arm_vmaxnmq_x_f32): Remove.
- (__arm_vminnmq): Remove.
- (__arm_vmaxnmq): Remove.
- (__arm_vmaxnmq_m): Remove.
- (__arm_vminnmq_m): Remove.
- (__arm_vminnmq_x): Remove.
- (__arm_vmaxnmq_x): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MAX_MIN_F): New.
- (MVE_FP_M_BINARY): Add VMAXNMQ_M_F, VMINNMQ_M_F.
- (mve_insn): Add vmaxnm, vminnm.
- (max_min_f_str): New.
- * config/arm/mve.md (mve_vmaxnmq_f<mode>, mve_vminnmq_f<mode>):
- Merge into ...
- (@mve_<max_min_f_str>q_f<mode>): ... this.
- (mve_vmaxnmq_m_f<mode>, mve_vminnmq_m_f<mode>): Merge into ...
- (@mve_<mve_insn>q_m_f<mode>): ... this.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/vec-common.md (smin<mode>3): Use VDQWH iterator.
- (smax<mode>3): Likewise.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_S_U)
- (FUNCTION_PRED_P_S): New.
- (vmaxavq, vminavq, vmaxvq, vminvq): New.
- * config/arm/arm-mve-builtins-base.def (vmaxavq, vminavq, vmaxvq)
- (vminvq): New.
- * config/arm/arm-mve-builtins-base.h (vmaxavq, vminavq, vmaxvq)
- (vminvq): New.
- * config/arm/arm_mve.h (vminvq): Remove.
- (vmaxvq): Remove.
- (vminvq_p): Remove.
- (vmaxvq_p): Remove.
- (vminvq_u8): Remove.
- (vmaxvq_u8): Remove.
- (vminvq_s8): Remove.
- (vmaxvq_s8): Remove.
- (vminvq_u16): Remove.
- (vmaxvq_u16): Remove.
- (vminvq_s16): Remove.
- (vmaxvq_s16): Remove.
- (vminvq_u32): Remove.
- (vmaxvq_u32): Remove.
- (vminvq_s32): Remove.
- (vmaxvq_s32): Remove.
- (vminvq_p_u8): Remove.
- (vmaxvq_p_u8): Remove.
- (vminvq_p_s8): Remove.
- (vmaxvq_p_s8): Remove.
- (vminvq_p_u16): Remove.
- (vmaxvq_p_u16): Remove.
- (vminvq_p_s16): Remove.
- (vmaxvq_p_s16): Remove.
- (vminvq_p_u32): Remove.
- (vmaxvq_p_u32): Remove.
- (vminvq_p_s32): Remove.
- (vmaxvq_p_s32): Remove.
- (__arm_vminvq_u8): Remove.
- (__arm_vmaxvq_u8): Remove.
- (__arm_vminvq_s8): Remove.
- (__arm_vmaxvq_s8): Remove.
- (__arm_vminvq_u16): Remove.
- (__arm_vmaxvq_u16): Remove.
- (__arm_vminvq_s16): Remove.
- (__arm_vmaxvq_s16): Remove.
- (__arm_vminvq_u32): Remove.
- (__arm_vmaxvq_u32): Remove.
- (__arm_vminvq_s32): Remove.
- (__arm_vmaxvq_s32): Remove.
- (__arm_vminvq_p_u8): Remove.
- (__arm_vmaxvq_p_u8): Remove.
- (__arm_vminvq_p_s8): Remove.
- (__arm_vmaxvq_p_s8): Remove.
- (__arm_vminvq_p_u16): Remove.
- (__arm_vmaxvq_p_u16): Remove.
- (__arm_vminvq_p_s16): Remove.
- (__arm_vmaxvq_p_s16): Remove.
- (__arm_vminvq_p_u32): Remove.
- (__arm_vmaxvq_p_u32): Remove.
- (__arm_vminvq_p_s32): Remove.
- (__arm_vmaxvq_p_s32): Remove.
- (__arm_vminvq): Remove.
- (__arm_vmaxvq): Remove.
- (__arm_vminvq_p): Remove.
- (__arm_vmaxvq_p): Remove.
- (vminavq): Remove.
- (vmaxavq): Remove.
- (vminavq_p): Remove.
- (vmaxavq_p): Remove.
- (vminavq_s8): Remove.
- (vmaxavq_s8): Remove.
- (vminavq_s16): Remove.
- (vmaxavq_s16): Remove.
- (vminavq_s32): Remove.
- (vmaxavq_s32): Remove.
- (vminavq_p_s8): Remove.
- (vmaxavq_p_s8): Remove.
- (vminavq_p_s16): Remove.
- (vmaxavq_p_s16): Remove.
- (vminavq_p_s32): Remove.
- (vmaxavq_p_s32): Remove.
- (__arm_vminavq_s8): Remove.
- (__arm_vmaxavq_s8): Remove.
- (__arm_vminavq_s16): Remove.
- (__arm_vmaxavq_s16): Remove.
- (__arm_vminavq_s32): Remove.
- (__arm_vmaxavq_s32): Remove.
- (__arm_vminavq_p_s8): Remove.
- (__arm_vmaxavq_p_s8): Remove.
- (__arm_vminavq_p_s16): Remove.
- (__arm_vmaxavq_p_s16): Remove.
- (__arm_vminavq_p_s32): Remove.
- (__arm_vmaxavq_p_s32): Remove.
- (__arm_vminavq): Remove.
- (__arm_vmaxavq): Remove.
- (__arm_vminavq_p): Remove.
- (__arm_vmaxavq_p): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VMAXVQ_VMINVQ, MVE_VMAXVQ_VMINVQ_P): New.
- (mve_insn): Add vmaxav, vmaxv, vminav, vminv.
- (supf): Add VMAXAVQ_S, VMAXAVQ_P_S, VMINAVQ_S, VMINAVQ_P_S.
- * config/arm/mve.md (mve_vmaxavq_s<mode>, mve_vmaxvq_<supf><mode>)
- (mve_vminavq_s<mode>, mve_vminvq_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vmaxavq_p_s<mode>, mve_vmaxvq_p_<supf><mode>)
- (mve_vminavq_p_s<mode>, mve_vminvq_p_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_p_<supf><mode>): ... this.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-functions.h (class
- unspec_mve_function_exact_insn_pred_p): New.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_maxavminav): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_maxavminav): New.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_maxvminv): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_maxvminv): New.
-
-2023-05-09 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_adjust_reg_alloc_order):
- Declare.
- * config/aarch64/aarch64.h (REG_ALLOC_ORDER): Define.
- (ADJUST_REG_ALLOC_ORDER): Likewise.
- * config/aarch64/aarch64.cc (aarch64_adjust_reg_alloc_order): New
- function.
- * config/aarch64/aarch64-sve.md (*vcond_mask_<mode><vpred>): Use
- Upa rather than Upl for unpredicated movprfx alternatives.
-
-2023-05-09 Jeff Law <jlaw@ventanamicro>
-
- * config/h8300/testcompare.md: Add peephole2 which uses a memory
- load to set flags, thus eliminating a compare against zero.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vshllbq, vshlltq): New.
- * config/arm/arm-mve-builtins-base.def (vshllbq, vshlltq): New.
- * config/arm/arm-mve-builtins-base.h (vshllbq, vshlltq): New.
- * config/arm/arm_mve.h (vshlltq): Remove.
- (vshllbq): Remove.
- (vshllbq_m): Remove.
- (vshlltq_m): Remove.
- (vshllbq_x): Remove.
- (vshlltq_x): Remove.
- (vshlltq_n_u8): Remove.
- (vshllbq_n_u8): Remove.
- (vshlltq_n_s8): Remove.
- (vshllbq_n_s8): Remove.
- (vshlltq_n_u16): Remove.
- (vshllbq_n_u16): Remove.
- (vshlltq_n_s16): Remove.
- (vshllbq_n_s16): Remove.
- (vshllbq_m_n_s8): Remove.
- (vshllbq_m_n_s16): Remove.
- (vshllbq_m_n_u8): Remove.
- (vshllbq_m_n_u16): Remove.
- (vshlltq_m_n_s8): Remove.
- (vshlltq_m_n_s16): Remove.
- (vshlltq_m_n_u8): Remove.
- (vshlltq_m_n_u16): Remove.
- (vshllbq_x_n_s8): Remove.
- (vshllbq_x_n_s16): Remove.
- (vshllbq_x_n_u8): Remove.
- (vshllbq_x_n_u16): Remove.
- (vshlltq_x_n_s8): Remove.
- (vshlltq_x_n_s16): Remove.
- (vshlltq_x_n_u8): Remove.
- (vshlltq_x_n_u16): Remove.
- (__arm_vshlltq_n_u8): Remove.
- (__arm_vshllbq_n_u8): Remove.
- (__arm_vshlltq_n_s8): Remove.
- (__arm_vshllbq_n_s8): Remove.
- (__arm_vshlltq_n_u16): Remove.
- (__arm_vshllbq_n_u16): Remove.
- (__arm_vshlltq_n_s16): Remove.
- (__arm_vshllbq_n_s16): Remove.
- (__arm_vshllbq_m_n_s8): Remove.
- (__arm_vshllbq_m_n_s16): Remove.
- (__arm_vshllbq_m_n_u8): Remove.
- (__arm_vshllbq_m_n_u16): Remove.
- (__arm_vshlltq_m_n_s8): Remove.
- (__arm_vshlltq_m_n_s16): Remove.
- (__arm_vshlltq_m_n_u8): Remove.
- (__arm_vshlltq_m_n_u16): Remove.
- (__arm_vshllbq_x_n_s8): Remove.
- (__arm_vshllbq_x_n_s16): Remove.
- (__arm_vshllbq_x_n_u8): Remove.
- (__arm_vshllbq_x_n_u16): Remove.
- (__arm_vshlltq_x_n_s8): Remove.
- (__arm_vshlltq_x_n_s16): Remove.
- (__arm_vshlltq_x_n_u8): Remove.
- (__arm_vshlltq_x_n_u16): Remove.
- (__arm_vshlltq): Remove.
- (__arm_vshllbq): Remove.
- (__arm_vshllbq_m): Remove.
- (__arm_vshlltq_m): Remove.
- (__arm_vshllbq_x): Remove.
- (__arm_vshlltq_x): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (mve_insn): Add vshllb, vshllt.
- (VSHLLBQ_N, VSHLLTQ_N): Remove.
- (VSHLLxQ_N): New.
- (VSHLLBQ_M_N, VSHLLTQ_M_N): Remove.
- (VSHLLxQ_M_N): New.
- * config/arm/mve.md (mve_vshllbq_n_<supf><mode>)
- (mve_vshlltq_n_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vshllbq_m_n_<supf><mode>, mve_vshlltq_m_n_<supf><mode>):
- Merge into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_widen_n): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_widen_n): New.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vmovnbq, vmovntq, vqmovnbq)
- (vqmovntq, vqmovunbq, vqmovuntq): New.
- * config/arm/arm-mve-builtins-base.def (vmovnbq, vmovntq)
- (vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq): New.
- * config/arm/arm-mve-builtins-base.h (vmovnbq, vmovntq, vqmovnbq)
- (vqmovntq, vqmovunbq, vqmovuntq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vmovnbq,
- vmovntq, vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq.
- * config/arm/arm_mve.h (vqmovntq): Remove.
- (vqmovnbq): Remove.
- (vqmovnbq_m): Remove.
- (vqmovntq_m): Remove.
- (vqmovntq_u16): Remove.
- (vqmovnbq_u16): Remove.
- (vqmovntq_s16): Remove.
- (vqmovnbq_s16): Remove.
- (vqmovntq_u32): Remove.
- (vqmovnbq_u32): Remove.
- (vqmovntq_s32): Remove.
- (vqmovnbq_s32): Remove.
- (vqmovnbq_m_s16): Remove.
- (vqmovntq_m_s16): Remove.
- (vqmovnbq_m_u16): Remove.
- (vqmovntq_m_u16): Remove.
- (vqmovnbq_m_s32): Remove.
- (vqmovntq_m_s32): Remove.
- (vqmovnbq_m_u32): Remove.
- (vqmovntq_m_u32): Remove.
- (__arm_vqmovntq_u16): Remove.
- (__arm_vqmovnbq_u16): Remove.
- (__arm_vqmovntq_s16): Remove.
- (__arm_vqmovnbq_s16): Remove.
- (__arm_vqmovntq_u32): Remove.
- (__arm_vqmovnbq_u32): Remove.
- (__arm_vqmovntq_s32): Remove.
- (__arm_vqmovnbq_s32): Remove.
- (__arm_vqmovnbq_m_s16): Remove.
- (__arm_vqmovntq_m_s16): Remove.
- (__arm_vqmovnbq_m_u16): Remove.
- (__arm_vqmovntq_m_u16): Remove.
- (__arm_vqmovnbq_m_s32): Remove.
- (__arm_vqmovntq_m_s32): Remove.
- (__arm_vqmovnbq_m_u32): Remove.
- (__arm_vqmovntq_m_u32): Remove.
- (__arm_vqmovntq): Remove.
- (__arm_vqmovnbq): Remove.
- (__arm_vqmovnbq_m): Remove.
- (__arm_vqmovntq_m): Remove.
- (vmovntq): Remove.
- (vmovnbq): Remove.
- (vmovnbq_m): Remove.
- (vmovntq_m): Remove.
- (vmovntq_u16): Remove.
- (vmovnbq_u16): Remove.
- (vmovntq_s16): Remove.
- (vmovnbq_s16): Remove.
- (vmovntq_u32): Remove.
- (vmovnbq_u32): Remove.
- (vmovntq_s32): Remove.
- (vmovnbq_s32): Remove.
- (vmovnbq_m_s16): Remove.
- (vmovntq_m_s16): Remove.
- (vmovnbq_m_u16): Remove.
- (vmovntq_m_u16): Remove.
- (vmovnbq_m_s32): Remove.
- (vmovntq_m_s32): Remove.
- (vmovnbq_m_u32): Remove.
- (vmovntq_m_u32): Remove.
- (__arm_vmovntq_u16): Remove.
- (__arm_vmovnbq_u16): Remove.
- (__arm_vmovntq_s16): Remove.
- (__arm_vmovnbq_s16): Remove.
- (__arm_vmovntq_u32): Remove.
- (__arm_vmovnbq_u32): Remove.
- (__arm_vmovntq_s32): Remove.
- (__arm_vmovnbq_s32): Remove.
- (__arm_vmovnbq_m_s16): Remove.
- (__arm_vmovntq_m_s16): Remove.
- (__arm_vmovnbq_m_u16): Remove.
- (__arm_vmovntq_m_u16): Remove.
- (__arm_vmovnbq_m_s32): Remove.
- (__arm_vmovntq_m_s32): Remove.
- (__arm_vmovnbq_m_u32): Remove.
- (__arm_vmovntq_m_u32): Remove.
- (__arm_vmovntq): Remove.
- (__arm_vmovnbq): Remove.
- (__arm_vmovnbq_m): Remove.
- (__arm_vmovntq_m): Remove.
- (vqmovuntq): Remove.
- (vqmovunbq): Remove.
- (vqmovunbq_m): Remove.
- (vqmovuntq_m): Remove.
- (vqmovuntq_s16): Remove.
- (vqmovunbq_s16): Remove.
- (vqmovuntq_s32): Remove.
- (vqmovunbq_s32): Remove.
- (vqmovunbq_m_s16): Remove.
- (vqmovuntq_m_s16): Remove.
- (vqmovunbq_m_s32): Remove.
- (vqmovuntq_m_s32): Remove.
- (__arm_vqmovuntq_s16): Remove.
- (__arm_vqmovunbq_s16): Remove.
- (__arm_vqmovuntq_s32): Remove.
- (__arm_vqmovunbq_s32): Remove.
- (__arm_vqmovunbq_m_s16): Remove.
- (__arm_vqmovuntq_m_s16): Remove.
- (__arm_vqmovunbq_m_s32): Remove.
- (__arm_vqmovuntq_m_s32): Remove.
- (__arm_vqmovuntq): Remove.
- (__arm_vqmovunbq): Remove.
- (__arm_vqmovunbq_m): Remove.
- (__arm_vqmovuntq_m): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_MOVN, MVE_MOVN_M): New.
- (mve_insn): Add vmovnb, vmovnt, vqmovnb, vqmovnt, vqmovunb,
- vqmovunt.
- (isu): Likewise.
- (supf): Add VQMOVUNBQ_M_S, VQMOVUNBQ_S, VQMOVUNTQ_M_S,
- VQMOVUNTQ_S.
- * config/arm/mve.md (mve_vmovnbq_<supf><mode>)
- (mve_vmovntq_<supf><mode>, mve_vqmovnbq_<supf><mode>)
- (mve_vqmovntq_<supf><mode>, mve_vqmovunbq_s<mode>)
- (mve_vqmovuntq_s<mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vmovnbq_m_<supf><mode>, mve_vmovntq_m_<supf><mode>)
- (mve_vqmovnbq_m_<supf><mode>, mve_vqmovntq_m_<supf><mode>)
- (mve_vqmovunbq_m_s<mode>, mve_vqmovuntq_m_s<mode>): Merge into ...
- (@mve_<mve_insn>q_m_<supf><mode>): ... this.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_move_narrow): New.
- (binary_move_narrow_unsigned): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_move_narrow): New.
- (binary_move_narrow_unsigned): New.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_F): New.
- (vrndaq, vrndmq, vrndnq, vrndpq, vrndq, vrndxq): New.
- * config/arm/arm-mve-builtins-base.def (vrndaq, vrndmq, vrndnq)
- (vrndpq, vrndq, vrndxq): New.
- * config/arm/arm-mve-builtins-base.h (vrndaq, vrndmq, vrndnq)
- (vrndpq, vrndq, vrndxq): New.
- * config/arm/arm_mve.h (vrndxq): Remove.
- (vrndq): Remove.
- (vrndpq): Remove.
- (vrndnq): Remove.
- (vrndmq): Remove.
- (vrndaq): Remove.
- (vrndaq_m): Remove.
- (vrndmq_m): Remove.
- (vrndnq_m): Remove.
- (vrndpq_m): Remove.
- (vrndq_m): Remove.
- (vrndxq_m): Remove.
- (vrndq_x): Remove.
- (vrndnq_x): Remove.
- (vrndmq_x): Remove.
- (vrndpq_x): Remove.
- (vrndaq_x): Remove.
- (vrndxq_x): Remove.
- (vrndxq_f16): Remove.
- (vrndxq_f32): Remove.
- (vrndq_f16): Remove.
- (vrndq_f32): Remove.
- (vrndpq_f16): Remove.
- (vrndpq_f32): Remove.
- (vrndnq_f16): Remove.
- (vrndnq_f32): Remove.
- (vrndmq_f16): Remove.
- (vrndmq_f32): Remove.
- (vrndaq_f16): Remove.
- (vrndaq_f32): Remove.
- (vrndaq_m_f16): Remove.
- (vrndmq_m_f16): Remove.
- (vrndnq_m_f16): Remove.
- (vrndpq_m_f16): Remove.
- (vrndq_m_f16): Remove.
- (vrndxq_m_f16): Remove.
- (vrndaq_m_f32): Remove.
- (vrndmq_m_f32): Remove.
- (vrndnq_m_f32): Remove.
- (vrndpq_m_f32): Remove.
- (vrndq_m_f32): Remove.
- (vrndxq_m_f32): Remove.
- (vrndq_x_f16): Remove.
- (vrndq_x_f32): Remove.
- (vrndnq_x_f16): Remove.
- (vrndnq_x_f32): Remove.
- (vrndmq_x_f16): Remove.
- (vrndmq_x_f32): Remove.
- (vrndpq_x_f16): Remove.
- (vrndpq_x_f32): Remove.
- (vrndaq_x_f16): Remove.
- (vrndaq_x_f32): Remove.
- (vrndxq_x_f16): Remove.
- (vrndxq_x_f32): Remove.
- (__arm_vrndxq_f16): Remove.
- (__arm_vrndxq_f32): Remove.
- (__arm_vrndq_f16): Remove.
- (__arm_vrndq_f32): Remove.
- (__arm_vrndpq_f16): Remove.
- (__arm_vrndpq_f32): Remove.
- (__arm_vrndnq_f16): Remove.
- (__arm_vrndnq_f32): Remove.
- (__arm_vrndmq_f16): Remove.
- (__arm_vrndmq_f32): Remove.
- (__arm_vrndaq_f16): Remove.
- (__arm_vrndaq_f32): Remove.
- (__arm_vrndaq_m_f16): Remove.
- (__arm_vrndmq_m_f16): Remove.
- (__arm_vrndnq_m_f16): Remove.
- (__arm_vrndpq_m_f16): Remove.
- (__arm_vrndq_m_f16): Remove.
- (__arm_vrndxq_m_f16): Remove.
- (__arm_vrndaq_m_f32): Remove.
- (__arm_vrndmq_m_f32): Remove.
- (__arm_vrndnq_m_f32): Remove.
- (__arm_vrndpq_m_f32): Remove.
- (__arm_vrndq_m_f32): Remove.
- (__arm_vrndxq_m_f32): Remove.
- (__arm_vrndq_x_f16): Remove.
- (__arm_vrndq_x_f32): Remove.
- (__arm_vrndnq_x_f16): Remove.
- (__arm_vrndnq_x_f32): Remove.
- (__arm_vrndmq_x_f16): Remove.
- (__arm_vrndmq_x_f32): Remove.
- (__arm_vrndpq_x_f16): Remove.
- (__arm_vrndpq_x_f32): Remove.
- (__arm_vrndaq_x_f16): Remove.
- (__arm_vrndaq_x_f32): Remove.
- (__arm_vrndxq_x_f16): Remove.
- (__arm_vrndxq_x_f32): Remove.
- (__arm_vrndxq): Remove.
- (__arm_vrndq): Remove.
- (__arm_vrndpq): Remove.
- (__arm_vrndnq): Remove.
- (__arm_vrndmq): Remove.
- (__arm_vrndaq): Remove.
- (__arm_vrndaq_m): Remove.
- (__arm_vrndmq_m): Remove.
- (__arm_vrndnq_m): Remove.
- (__arm_vrndpq_m): Remove.
- (__arm_vrndq_m): Remove.
- (__arm_vrndxq_m): Remove.
- (__arm_vrndq_x): Remove.
- (__arm_vrndnq_x): Remove.
- (__arm_vrndmq_x): Remove.
- (__arm_vrndpq_x): Remove.
- (__arm_vrndaq_x): Remove.
- (__arm_vrndxq_x): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_N_NO_U_F): New.
- (vabsq, vnegq, vclsq, vclzq, vqabsq, vqnegq): New.
- * config/arm/arm-mve-builtins-base.def (vabsq, vnegq, vclsq)
- (vclzq, vqabsq, vqnegq): New.
- * config/arm/arm-mve-builtins-base.h (vabsq, vnegq, vclsq, vclzq)
- (vqabsq, vqnegq): New.
- * config/arm/arm_mve.h (vabsq): Remove.
- (vabsq_m): Remove.
- (vabsq_x): Remove.
- (vabsq_f16): Remove.
- (vabsq_f32): Remove.
- (vabsq_s8): Remove.
- (vabsq_s16): Remove.
- (vabsq_s32): Remove.
- (vabsq_m_s8): Remove.
- (vabsq_m_s16): Remove.
- (vabsq_m_s32): Remove.
- (vabsq_m_f16): Remove.
- (vabsq_m_f32): Remove.
- (vabsq_x_s8): Remove.
- (vabsq_x_s16): Remove.
- (vabsq_x_s32): Remove.
- (vabsq_x_f16): Remove.
- (vabsq_x_f32): Remove.
- (__arm_vabsq_s8): Remove.
- (__arm_vabsq_s16): Remove.
- (__arm_vabsq_s32): Remove.
- (__arm_vabsq_m_s8): Remove.
- (__arm_vabsq_m_s16): Remove.
- (__arm_vabsq_m_s32): Remove.
- (__arm_vabsq_x_s8): Remove.
- (__arm_vabsq_x_s16): Remove.
- (__arm_vabsq_x_s32): Remove.
- (__arm_vabsq_f16): Remove.
- (__arm_vabsq_f32): Remove.
- (__arm_vabsq_m_f16): Remove.
- (__arm_vabsq_m_f32): Remove.
- (__arm_vabsq_x_f16): Remove.
- (__arm_vabsq_x_f32): Remove.
- (__arm_vabsq): Remove.
- (__arm_vabsq_m): Remove.
- (__arm_vabsq_x): Remove.
- (vnegq): Remove.
- (vnegq_m): Remove.
- (vnegq_x): Remove.
- (vnegq_f16): Remove.
- (vnegq_f32): Remove.
- (vnegq_s8): Remove.
- (vnegq_s16): Remove.
- (vnegq_s32): Remove.
- (vnegq_m_s8): Remove.
- (vnegq_m_s16): Remove.
- (vnegq_m_s32): Remove.
- (vnegq_m_f16): Remove.
- (vnegq_m_f32): Remove.
- (vnegq_x_s8): Remove.
- (vnegq_x_s16): Remove.
- (vnegq_x_s32): Remove.
- (vnegq_x_f16): Remove.
- (vnegq_x_f32): Remove.
- (__arm_vnegq_s8): Remove.
- (__arm_vnegq_s16): Remove.
- (__arm_vnegq_s32): Remove.
- (__arm_vnegq_m_s8): Remove.
- (__arm_vnegq_m_s16): Remove.
- (__arm_vnegq_m_s32): Remove.
- (__arm_vnegq_x_s8): Remove.
- (__arm_vnegq_x_s16): Remove.
- (__arm_vnegq_x_s32): Remove.
- (__arm_vnegq_f16): Remove.
- (__arm_vnegq_f32): Remove.
- (__arm_vnegq_m_f16): Remove.
- (__arm_vnegq_m_f32): Remove.
- (__arm_vnegq_x_f16): Remove.
- (__arm_vnegq_x_f32): Remove.
- (__arm_vnegq): Remove.
- (__arm_vnegq_m): Remove.
- (__arm_vnegq_x): Remove.
- (vclsq): Remove.
- (vclsq_m): Remove.
- (vclsq_x): Remove.
- (vclsq_s8): Remove.
- (vclsq_s16): Remove.
- (vclsq_s32): Remove.
- (vclsq_m_s8): Remove.
- (vclsq_m_s16): Remove.
- (vclsq_m_s32): Remove.
- (vclsq_x_s8): Remove.
- (vclsq_x_s16): Remove.
- (vclsq_x_s32): Remove.
- (__arm_vclsq_s8): Remove.
- (__arm_vclsq_s16): Remove.
- (__arm_vclsq_s32): Remove.
- (__arm_vclsq_m_s8): Remove.
- (__arm_vclsq_m_s16): Remove.
- (__arm_vclsq_m_s32): Remove.
- (__arm_vclsq_x_s8): Remove.
- (__arm_vclsq_x_s16): Remove.
- (__arm_vclsq_x_s32): Remove.
- (__arm_vclsq): Remove.
- (__arm_vclsq_m): Remove.
- (__arm_vclsq_x): Remove.
- (vclzq): Remove.
- (vclzq_m): Remove.
- (vclzq_x): Remove.
- (vclzq_s8): Remove.
- (vclzq_s16): Remove.
- (vclzq_s32): Remove.
- (vclzq_u8): Remove.
- (vclzq_u16): Remove.
- (vclzq_u32): Remove.
- (vclzq_m_u8): Remove.
- (vclzq_m_s8): Remove.
- (vclzq_m_u16): Remove.
- (vclzq_m_s16): Remove.
- (vclzq_m_u32): Remove.
- (vclzq_m_s32): Remove.
- (vclzq_x_s8): Remove.
- (vclzq_x_s16): Remove.
- (vclzq_x_s32): Remove.
- (vclzq_x_u8): Remove.
- (vclzq_x_u16): Remove.
- (vclzq_x_u32): Remove.
- (__arm_vclzq_s8): Remove.
- (__arm_vclzq_s16): Remove.
- (__arm_vclzq_s32): Remove.
- (__arm_vclzq_u8): Remove.
- (__arm_vclzq_u16): Remove.
- (__arm_vclzq_u32): Remove.
- (__arm_vclzq_m_u8): Remove.
- (__arm_vclzq_m_s8): Remove.
- (__arm_vclzq_m_u16): Remove.
- (__arm_vclzq_m_s16): Remove.
- (__arm_vclzq_m_u32): Remove.
- (__arm_vclzq_m_s32): Remove.
- (__arm_vclzq_x_s8): Remove.
- (__arm_vclzq_x_s16): Remove.
- (__arm_vclzq_x_s32): Remove.
- (__arm_vclzq_x_u8): Remove.
- (__arm_vclzq_x_u16): Remove.
- (__arm_vclzq_x_u32): Remove.
- (__arm_vclzq): Remove.
- (__arm_vclzq_m): Remove.
- (__arm_vclzq_x): Remove.
- (vqabsq): Remove.
- (vqnegq): Remove.
- (vqnegq_m): Remove.
- (vqabsq_m): Remove.
- (vqabsq_s8): Remove.
- (vqabsq_s16): Remove.
- (vqabsq_s32): Remove.
- (vqnegq_s8): Remove.
- (vqnegq_s16): Remove.
- (vqnegq_s32): Remove.
- (vqnegq_m_s8): Remove.
- (vqabsq_m_s8): Remove.
- (vqnegq_m_s16): Remove.
- (vqabsq_m_s16): Remove.
- (vqnegq_m_s32): Remove.
- (vqabsq_m_s32): Remove.
- (__arm_vqabsq_s8): Remove.
- (__arm_vqabsq_s16): Remove.
- (__arm_vqabsq_s32): Remove.
- (__arm_vqnegq_s8): Remove.
- (__arm_vqnegq_s16): Remove.
- (__arm_vqnegq_s32): Remove.
- (__arm_vqnegq_m_s8): Remove.
- (__arm_vqabsq_m_s8): Remove.
- (__arm_vqnegq_m_s16): Remove.
- (__arm_vqabsq_m_s16): Remove.
- (__arm_vqnegq_m_s32): Remove.
- (__arm_vqabsq_m_s32): Remove.
- (__arm_vqabsq): Remove.
- (__arm_vqnegq): Remove.
- (__arm_vqnegq_m): Remove.
- (__arm_vqabsq_m): Remove.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_INT_M_UNARY, MVE_INT_UNARY)
- (MVE_FP_UNARY, MVE_FP_M_UNARY): New.
- (mve_insn): Add vabs, vcls, vclz, vneg, vqabs, vqneg, vrnda,
- vrndm, vrndn, vrndp, vrnd, vrndx.
- (isu): Add VABSQ_M_S, VCLSQ_M_S, VCLZQ_M_S, VCLZQ_M_U, VNEGQ_M_S,
- VQABSQ_M_S, VQNEGQ_M_S.
- (mve_mnemo): New.
- * config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrndxq_f<mode>)
- (mve_vrndq_f<mode>, mve_vrndpq_f<mode>, mve_vrndnq_f<mode>)
- (mve_vrndmq_f<mode>, mve_vrndaq_f<mode>): Merge into ...
- (@mve_<mve_insn>q_f<mode>): ... this.
- (mve_vnegq_f<mode>, mve_vabsq_f<mode>): Merge into ...
- (mve_v<absneg_str>q_f<mode>): ... this.
- (mve_vnegq_s<mode>, mve_vabsq_s<mode>): Merge into ...
- (mve_v<absneg_str>q_s<mode>): ... this.
- (mve_vclsq_s<mode>, mve_vqnegq_s<mode>, mve_vqabsq_s<mode>): Merge into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- (mve_vabsq_m_s<mode>, mve_vclsq_m_s<mode>)
- (mve_vclzq_m_<supf><mode>, mve_vnegq_m_s<mode>)
- (mve_vqabsq_m_s<mode>, mve_vqnegq_m_s<mode>): Merge into ...
- (@mve_<mve_insn>q_m_<supf><mode>): ... this.
- (mve_vabsq_m_f<mode>, mve_vnegq_m_f<mode>, mve_vrndaq_m_f<mode>)
- (mve_vrndmq_m_f<mode>, mve_vrndnq_m_f<mode>, mve_vrndpq_m_f<mode>)
- (mve_vrndxq_m_f<mode>): Merge into ...
- (@mve_<mve_insn>q_m_f<mode>): ... this.
-
-2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (unary): New.
- * config/arm/arm-mve-builtins-shapes.h (unary): New.
-
-2023-05-09 Jakub Jelinek <jakub@redhat.com>
-
- * mux-utils.h: Fix comment typo, avoides -> avoids.
-
-2023-05-09 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109778
- * wide-int.h (wi::lrotate, wi::rrotate): Call wi::lrshift on
- wi::zext (x, width) rather than x if width != precision, rather
- than using wi::zext (right, width) after the shift.
- * tree-ssa-ccp.cc (bit_value_binop): Call wi::ext on the results
- of wi::lrotate or wi::rrotate.
-
-2023-05-09 Alexander Monakov <amonakov@ispras.ru>
-
- * genmatch.cc (get_out_file): Make static and rename to ...
- (choose_output): ... this. Reimplement. Update all uses ...
- (decision_tree::gen): ... here and ...
- (main): ... here.
-
-2023-05-09 Alexander Monakov <amonakov@ispras.ru>
-
- * genmatch.cc (showUsage): Reimplement as ...
- (usage): ...this. Adjust all uses.
- (main): Print usage when no arguments. Add missing 'return 1'.
-
-2023-05-09 Alexander Monakov <amonakov@ispras.ru>
-
- * genmatch.cc (header_file): Make static.
- (emit_func): Rename to...
- (fp_decl): ... this. Adjust all uses.
- (fp_decl_done): New function. Use it...
- (decision_tree::gen): ... here and...
- (write_predicate): ... here.
- (main): Adjust.
-
-2023-05-09 Richard Sandiford <richard.sandiford@arm.com>
-
- * ira-conflicts.cc (can_use_same_reg_p): Skip over non-matching
- earlyclobbers.
-
-2023-05-08 Roger Sayle <roger@nextmovesoftware.com>
- Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (any_or_plus): Move definition earlier.
- (*insvti_highpart_1): New define_insn_and_split to overwrite
- (insv) the highpart of a TImode register/memory.
-
-2023-05-08 Eugene Rozenfeld <erozen@microsoft.com>
-
- * auto-profile.cc (auto_profile): Check todo from early_inline
- to see if cleanup_tree_vfg needs to be called.
- (early_inline): Return todo from early_inliner.
-
-2023-05-08 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vector_info):
- New.
- (pass_vsetvl::get_block_info): New.
- (pass_vsetvl::update_vector_info): New.
- (pass_vsetvl::simple_vsetvl): Use get_vector_info.
- (pass_vsetvl::compute_local_backward_infos): Ditto.
- (pass_vsetvl::transfer_before): Ditto.
- (pass_vsetvl::transfer_after): Ditto.
- (pass_vsetvl::emit_local_forward_vsetvls): Ditto.
- (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
- (pass_vsetvl::cleanup_insns): Ditto.
- (pass_vsetvl::compute_local_backward_infos): Use
- update_vector_info.
-
-2023-05-08 Jeff Law <jlaw@ventanamicro>
-
- * config/stormy16/stormy16.md (zero_extendhisi2): Fix length.
-
-2023-05-08 Richard Biener <rguenther@suse.de>
- Michael Meissner <meissner@linux.ibm.com>
-
- PR middle-end/108623
- * tree-core.h (tree_type_common): Bump up precision field to 16 bits.
- Align bit fields > 1 bit to at least an 8-bit boundary.
-
-2023-05-08 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109424
- PR tree-optimization/59424
- * tree-ssa-phiopt.cc (factor_out_conditional_conversion): Rename to ...
- (factor_out_conditional_operation): This and add support for all unary
- operations.
- (pass_phiopt::execute): Update call to factor_out_conditional_conversion
- to call factor_out_conditional_operation instead.
-
-2023-05-08 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (pass_phiopt::execute): Loop
- over factor_out_conditional_conversion.
-
-2023-05-08 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/49959
- PR tree-optimization/103771
- * tree-ssa-phiopt.cc (pass_phiopt::execute): Support
- Diamond shapped bb form for factor_out_conditional_conversion.
-
-2023-05-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (movmisalign<mode>): New pattern.
- * config/riscv/riscv-protos.h (riscv_vector_mask_mode_p): Delete.
- (riscv_vector_get_mask_mode): Ditto.
- (get_mask_policy_no_pred): Ditto.
- (get_tail_policy_no_pred): Ditto.
- (get_mask_mode): New function.
- * config/riscv/riscv-v.cc (get_mask_policy_no_pred): Delete.
- (get_tail_policy_no_pred): Ditto.
- (riscv_vector_mask_mode_p): Ditto.
- (riscv_vector_get_mask_mode): Ditto.
- (get_mask_mode): New function.
- * config/riscv/riscv-vector-builtins.cc (use_real_merge_p): Remove
- global extern.
- (get_tail_policy_for_pred): Ditto.
- * config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred): Ditto.
- (get_mask_policy_for_pred): Ditto
- * config/riscv/riscv.cc (riscv_get_mask_mode): Refine codes.
-
-2023-05-08 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): New.
- (riscv_select_multilib): New.
- (riscv_compute_multilib): Extract logic to riscv_select_multilib and
- also handle select_by_abi.
- * config/riscv/elf.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Change it
- to select_by_abi_arch_cmodel from 1.
- * config/riscv/linux.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Define.
- * config/riscv/riscv-opts.h (enum riscv_multilib_select_kind): New.
-
-2023-05-08 Alexander Monakov <amonakov@ispras.ru>
-
- * Makefile.in: (gimple-match-head.o-warn): Remove.
- (GIMPLE_MATCH_PD_SEQ_SRC): Do not depend on
- gimple-match-exports.cc.
- (gimple-match-auto.h): Only depend on s-gimple-match.
- (generic-match-auto.h): Likewise.
-
-2023-05-08 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109691
- * tree-ssa-dce.cc (simple_dce_from_worklist): Add need_eh_cleanup
- argument.
- If the removed statement can throw, have need_eh_cleanup
- include the bb of that statement.
- * tree-ssa-dce.h (simple_dce_from_worklist): Update declaration.
- * tree-ssa-propagate.cc (struct prop_stats_d): Remove
- num_dce.
- (substitute_and_fold_dom_walker::substitute_and_fold_dom_walker):
- Initialize dceworklist instead of stmts_to_remove.
- (substitute_and_fold_dom_walker::~substitute_and_fold_dom_walker):
- Destore dceworklist instead of stmts_to_remove.
- (substitute_and_fold_dom_walker::before_dom_children):
- Set dceworklist instead of adding to stmts_to_remove.
- (substitute_and_fold_engine::substitute_and_fold):
- Call simple_dce_from_worklist instead of poping
- from the list.
- Don't update the stat on removal statements.
-
-2023-05-07 Andrew Pinski <apinski@marvell.com>
-
- PR target/109762
- * config/aarch64/aarch64-builtins.cc (aarch64_simd_switcher::aarch64_simd_switcher):
- Change argument type to aarch64_feature_flags.
- * config/aarch64/aarch64-protos.h (aarch64_simd_switcher): Change
- constructor argument type to aarch64_feature_flags.
- Change m_old_asm_isa_flags to be aarch64_feature_flags.
-
-2023-05-07 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate
- more parallel code if can_create_pseudo_p.
-
-2023-05-07 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/43644
- * lower-subreg.cc (resolve_simple_move): Don't emit a clobber
- immediately before moving a multi-word register by parts.
-
-2023-05-06 Jeff Law <jlaw@ventanamicro>
-
- * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): Delete.
-
-2023-05-06 Michael Collison <collison@rivosinc.com>
-
- * tree-vect-slp.cc (can_duplicate_and_interleave_p):
- Check that GET_MODE_NUNITS is a multiple of 2.
-
-2023-05-06 Michael Collison <collison@rivosinc.com>
-
- * config/riscv/riscv.cc
- (riscv_estimated_poly_value): Implement
- TARGET_ESTIMATED_POLY_VALUE.
- (riscv_preferred_simd_mode): Implement
- TARGET_VECTORIZE_PREFERRED_SIMD_MODE.
- (riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE.
- (riscv_empty_mask_is_expensive): Implement
- TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE.
- (riscv_vectorize_create_costs): Implement
- TARGET_VECTORIZE_CREATE_COSTS.
- (riscv_support_vector_misalignment): Implement
- TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT.
- (TARGET_ESTIMATED_POLY_VALUE): Register target macro.
- (TARGET_VECTORIZE_GET_MASK_MODE): Ditto.
- (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto.
- (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto.
-
-2023-05-06 Jeff Law <jlaw@ventanamicro>
-
- * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Remove
- duplicate definition.
-
-2023-05-06 Michael Collison <collison@rivosinc.com>
-
- * config/riscv/riscv-v.cc (autovec_use_vlmax_p): New function.
- (riscv_vector_preferred_simd_mode): Ditto.
- (get_mask_policy_no_pred): Ditto.
- (get_tail_policy_no_pred): Ditto.
- (riscv_vector_mask_mode_p): Ditto.
- (riscv_vector_get_mask_mode): Ditto.
-
-2023-05-06 Michael Collison <collison@rivosinc.com>
-
- * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
- Remove static declaration to to make externally visible.
- (get_mask_policy_for_pred): Ditto.
- * config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred):
- New external declaration.
- (get_mask_policy_for_pred): Ditto.
-
-2023-05-06 Michael Collison <collison@rivosinc.com>
-
- * config/riscv/riscv-protos.h (riscv_vector_mask_mode_p): New.
- (riscv_vector_get_mask_mode): Ditto.
- (get_mask_policy_no_pred): Ditto.
- (get_tail_policy_no_pred): Ditto.
-
-2023-05-06 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.h (struct machine_function): Add
- reg_is_wrapped_separately array for register wrapping
- information.
- * config/loongarch/loongarch.cc
- (loongarch_get_separate_components): New function.
- (loongarch_components_for_bb): Likewise.
- (loongarch_disqualify_components): Likewise.
- (loongarch_process_components): Likewise.
- (loongarch_emit_prologue_components): Likewise.
- (loongarch_emit_epilogue_components): Likewise.
- (loongarch_set_handled_components): Likewise.
- (TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS): Define.
- (TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB): Likewise.
- (TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS): Likewise.
- (TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS): Likewise.
- (TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS): Likewise.
- (TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Likewise.
- (loongarch_for_each_saved_reg): Skip registers that are wrapped
- separately.
-
-2023-05-06 Xi Ruoyao <xry111@xry111.site>
- PR other/109522
- * Makefile.in (s-macro_list): Pass -nostdinc to
- $(GCC_FOR_TARGET).
+2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
-2023-05-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (preferred_simd_mode): New function.
- * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
- (preferred_simd_mode): Ditto.
- * config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in function arg.
- (riscv_convert_vector_bits): Adjust for RVV auto-vectorization.
- (riscv_preferred_simd_mode): New function.
- (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): New target hook support.
- * config/riscv/vector.md: Add autovec.md.
- * config/riscv/autovec.md: New file.
-
-2023-05-06 Jakub Jelinek <jakub@redhat.com>
-
- * real.h (dconst_pi): Define.
- (dconst_e_ptr): Formatting fix.
- (dconst_pi_ptr): Declare.
- * real.cc (dconst_pi_ptr): New function.
- * gimple-range-op.cc (cfn_sincos::fold_range): Intersect the generic
- boundaries range with range computed from sin/cos of the particular
- bounds if the argument range is shorter than 2*pi.
- (cfn_sincos::op1_range): Take bulps into account when determining
- which result ranges are always invalid or behave like known NAN.
-
-2023-05-06 Aldy Hernandez <aldyh@redhat.com>
-
- * gimple-range-cache.cc (sbr_sparse_bitmap::set_bb_range): Do not
- pass type to vrange_storage::equal_p.
- * value-range-storage.cc (vrange_storage::equal_p): Remove type.
- (irange_storage::equal_p): Same.
- (frange_storage::equal_p): Same.
- * value-range-storage.h (class frange_storage): Same.
-
-2023-05-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/109748
- * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): Remove it.
- (pass_vsetvl::local_eliminate_vsetvl_insn): New function.
-
-2023-05-06 liuhongt <hongtao.liu@intel.com>
-
- * combine.cc (maybe_swap_commutative_operands): Canonicalize
- vec_merge when mask is constant.
- * doc/md.texi: Document vec_merge canonicalization.
-
-2023-05-06 Jakub Jelinek <jakub@redhat.com>
-
- * value-range.h (frange_arithmetic): Declare.
- * range-op-float.cc (frange_arithmetic): No longer static.
- * gimple-range-op.cc (frange_mpfr_arg1): New function.
- (cfn_sqrt::fold_range): Intersect the generic boundaries range
- with range computed from sqrt of the particular bounds.
- (cfn_sqrt::op1_range): Intersect the generic boundaries range
- with range computed from squared particular bounds.
-
-2023-05-06 Jakub Jelinek <jakub@redhat.com>
-
- * Makefile.in (check_p_numbers): Rename to one_to_9999, move
- earlier with helper variables also renamed.
- (MATCH_SPLUT_SEQ): Use $(wordlist 1,$(NUM_MATCH_SPLITS),$(one_to_9999))
- instead of $(shell seq 1 $(NUM_MATCH_SPLITS)).
- (check_p_subdirs): Use $(one_to_9999) instead of $(check_p_numbers).
-
-2023-05-06 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.md (splitop): Add PLUS.
- * config/cris/cris.cc (cris_split_constant): Also handle
- PLUS when a split into two insns may be useful.
-
-2023-05-05 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.md (movandsplit1): New define_peephole2.
-
-2023-05-05 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.md (lsrandsplit1): New define_peephole2.
-
-2023-05-05 Hans-Peter Nilsson <hp@axis.com>
-
- * doc/md.texi (define_peephole2): Document order of scanning.
-
-2023-05-05 Pan Li <pan2.li@intel.com>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Allow const as the operand of RVV
- indexed load/store.
-
-2023-05-05 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv.h (VECTOR_STORE_FLAG_VALUE): Add new macro
- consumed by simplify_rtx.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vrshrq, vshrq): New.
- * config/arm/arm-mve-builtins-base.def (vrshrq, vshrq): New.
- * config/arm/arm-mve-builtins-base.h (vrshrq, vshrq): New.
- * config/arm/arm_mve.h (vshrq): Remove.
- (vrshrq): Remove.
- (vrshrq_m): Remove.
- (vshrq_m): Remove.
- (vrshrq_x): Remove.
- (vshrq_x): Remove.
- (vshrq_n_s8): Remove.
- (vshrq_n_s16): Remove.
- (vshrq_n_s32): Remove.
- (vshrq_n_u8): Remove.
- (vshrq_n_u16): Remove.
- (vshrq_n_u32): Remove.
- (vrshrq_n_u8): Remove.
- (vrshrq_n_s8): Remove.
- (vrshrq_n_u16): Remove.
- (vrshrq_n_s16): Remove.
- (vrshrq_n_u32): Remove.
- (vrshrq_n_s32): Remove.
- (vrshrq_m_n_s8): Remove.
- (vrshrq_m_n_s32): Remove.
- (vrshrq_m_n_s16): Remove.
- (vrshrq_m_n_u8): Remove.
- (vrshrq_m_n_u32): Remove.
- (vrshrq_m_n_u16): Remove.
- (vshrq_m_n_s8): Remove.
- (vshrq_m_n_s32): Remove.
- (vshrq_m_n_s16): Remove.
- (vshrq_m_n_u8): Remove.
- (vshrq_m_n_u32): Remove.
- (vshrq_m_n_u16): Remove.
- (vrshrq_x_n_s8): Remove.
- (vrshrq_x_n_s16): Remove.
- (vrshrq_x_n_s32): Remove.
- (vrshrq_x_n_u8): Remove.
- (vrshrq_x_n_u16): Remove.
- (vrshrq_x_n_u32): Remove.
- (vshrq_x_n_s8): Remove.
- (vshrq_x_n_s16): Remove.
- (vshrq_x_n_s32): Remove.
- (vshrq_x_n_u8): Remove.
- (vshrq_x_n_u16): Remove.
- (vshrq_x_n_u32): Remove.
- (__arm_vshrq_n_s8): Remove.
- (__arm_vshrq_n_s16): Remove.
- (__arm_vshrq_n_s32): Remove.
- (__arm_vshrq_n_u8): Remove.
- (__arm_vshrq_n_u16): Remove.
- (__arm_vshrq_n_u32): Remove.
- (__arm_vrshrq_n_u8): Remove.
- (__arm_vrshrq_n_s8): Remove.
- (__arm_vrshrq_n_u16): Remove.
- (__arm_vrshrq_n_s16): Remove.
- (__arm_vrshrq_n_u32): Remove.
- (__arm_vrshrq_n_s32): Remove.
- (__arm_vrshrq_m_n_s8): Remove.
- (__arm_vrshrq_m_n_s32): Remove.
- (__arm_vrshrq_m_n_s16): Remove.
- (__arm_vrshrq_m_n_u8): Remove.
- (__arm_vrshrq_m_n_u32): Remove.
- (__arm_vrshrq_m_n_u16): Remove.
- (__arm_vshrq_m_n_s8): Remove.
- (__arm_vshrq_m_n_s32): Remove.
- (__arm_vshrq_m_n_s16): Remove.
- (__arm_vshrq_m_n_u8): Remove.
- (__arm_vshrq_m_n_u32): Remove.
- (__arm_vshrq_m_n_u16): Remove.
- (__arm_vrshrq_x_n_s8): Remove.
- (__arm_vrshrq_x_n_s16): Remove.
- (__arm_vrshrq_x_n_s32): Remove.
- (__arm_vrshrq_x_n_u8): Remove.
- (__arm_vrshrq_x_n_u16): Remove.
- (__arm_vrshrq_x_n_u32): Remove.
- (__arm_vshrq_x_n_s8): Remove.
- (__arm_vshrq_x_n_s16): Remove.
- (__arm_vshrq_x_n_s32): Remove.
- (__arm_vshrq_x_n_u8): Remove.
- (__arm_vshrq_x_n_u16): Remove.
- (__arm_vshrq_x_n_u32): Remove.
- (__arm_vshrq): Remove.
- (__arm_vrshrq): Remove.
- (__arm_vrshrq_m): Remove.
- (__arm_vshrq_m): Remove.
- (__arm_vrshrq_x): Remove.
- (__arm_vshrq_x): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_VSHRQ_M_N, MVE_VSHRQ_N): New.
- (mve_insn): Add vrshr, vshr.
- * config/arm/mve.md (mve_vshrq_n_<supf><mode>)
- (mve_vrshrq_n_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vrshrq_m_n_<supf><mode>, mve_vshrq_m_n_<supf><mode>): Merge
- into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_rshift): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_rshift): New.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_U_F): New.
- (vqshrunbq, vqshruntq, vqrshrunbq, vqrshruntq): New.
- * config/arm/arm-mve-builtins-base.def (vqshrunbq, vqshruntq)
- (vqrshrunbq, vqrshruntq): New.
- * config/arm/arm-mve-builtins-base.h (vqshrunbq, vqshruntq)
- (vqrshrunbq, vqrshruntq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vqshrunbq,
- vqshruntq, vqrshrunbq, vqrshruntq.
- * config/arm/arm_mve.h (vqrshrunbq): Remove.
- (vqrshruntq): Remove.
- (vqrshrunbq_m): Remove.
- (vqrshruntq_m): Remove.
- (vqrshrunbq_n_s16): Remove.
- (vqrshrunbq_n_s32): Remove.
- (vqrshruntq_n_s16): Remove.
- (vqrshruntq_n_s32): Remove.
- (vqrshrunbq_m_n_s32): Remove.
- (vqrshrunbq_m_n_s16): Remove.
- (vqrshruntq_m_n_s32): Remove.
- (vqrshruntq_m_n_s16): Remove.
- (__arm_vqrshrunbq_n_s16): Remove.
- (__arm_vqrshrunbq_n_s32): Remove.
- (__arm_vqrshruntq_n_s16): Remove.
- (__arm_vqrshruntq_n_s32): Remove.
- (__arm_vqrshrunbq_m_n_s32): Remove.
- (__arm_vqrshrunbq_m_n_s16): Remove.
- (__arm_vqrshruntq_m_n_s32): Remove.
- (__arm_vqrshruntq_m_n_s16): Remove.
- (__arm_vqrshrunbq): Remove.
- (__arm_vqrshruntq): Remove.
- (__arm_vqrshrunbq_m): Remove.
- (__arm_vqrshruntq_m): Remove.
- (vqshrunbq): Remove.
- (vqshruntq): Remove.
- (vqshrunbq_m): Remove.
- (vqshruntq_m): Remove.
- (vqshrunbq_n_s16): Remove.
- (vqshruntq_n_s16): Remove.
- (vqshrunbq_n_s32): Remove.
- (vqshruntq_n_s32): Remove.
- (vqshrunbq_m_n_s32): Remove.
- (vqshrunbq_m_n_s16): Remove.
- (vqshruntq_m_n_s32): Remove.
- (vqshruntq_m_n_s16): Remove.
- (__arm_vqshrunbq_n_s16): Remove.
- (__arm_vqshruntq_n_s16): Remove.
- (__arm_vqshrunbq_n_s32): Remove.
- (__arm_vqshruntq_n_s32): Remove.
- (__arm_vqshrunbq_m_n_s32): Remove.
- (__arm_vqshrunbq_m_n_s16): Remove.
- (__arm_vqshruntq_m_n_s32): Remove.
- (__arm_vqshruntq_m_n_s16): Remove.
- (__arm_vqshrunbq): Remove.
- (__arm_vqshruntq): Remove.
- (__arm_vqshrunbq_m): Remove.
- (__arm_vqshruntq_m): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_SHRN_N): Add VQRSHRUNBQ,
- VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ.
- (MVE_SHRN_M_N): Likewise.
- (mve_insn): Add vqrshrunb, vqrshrunt, vqshrunb, vqshrunt.
- (isu): Add VQRSHRUNBQ, VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ.
- (supf): Likewise.
- * config/arm/mve.md (mve_vqrshrunbq_n_s<mode>): Remove.
- (mve_vqrshruntq_n_s<mode>): Remove.
- (mve_vqshrunbq_n_s<mode>): Remove.
- (mve_vqshruntq_n_s<mode>): Remove.
- (mve_vqrshrunbq_m_n_s<mode>): Remove.
- (mve_vqrshruntq_m_n_s<mode>): Remove.
- (mve_vqshrunbq_m_n_s<mode>): Remove.
- (mve_vqshruntq_m_n_s<mode>): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc
- (binary_rshift_narrow_unsigned): New.
- * config/arm/arm-mve-builtins-shapes.h
- (binary_rshift_narrow_unsigned): New.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_F): New.
- (vshrnbq, vshrntq, vrshrnbq, vrshrntq, vqshrnbq, vqshrntq)
- (vqrshrnbq, vqrshrntq): New.
- * config/arm/arm-mve-builtins-base.def (vshrnbq, vshrntq)
- (vrshrnbq, vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq):
- New.
- * config/arm/arm-mve-builtins-base.h (vshrnbq, vshrntq, vrshrnbq)
- (vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vshrnbq,
- vshrntq, vrshrnbq, vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq,
- vqrshrntq.
- * config/arm/arm_mve.h (vshrnbq): Remove.
- (vshrntq): Remove.
- (vshrnbq_m): Remove.
- (vshrntq_m): Remove.
- (vshrnbq_n_s16): Remove.
- (vshrntq_n_s16): Remove.
- (vshrnbq_n_u16): Remove.
- (vshrntq_n_u16): Remove.
- (vshrnbq_n_s32): Remove.
- (vshrntq_n_s32): Remove.
- (vshrnbq_n_u32): Remove.
- (vshrntq_n_u32): Remove.
- (vshrnbq_m_n_s32): Remove.
- (vshrnbq_m_n_s16): Remove.
- (vshrnbq_m_n_u32): Remove.
- (vshrnbq_m_n_u16): Remove.
- (vshrntq_m_n_s32): Remove.
- (vshrntq_m_n_s16): Remove.
- (vshrntq_m_n_u32): Remove.
- (vshrntq_m_n_u16): Remove.
- (__arm_vshrnbq_n_s16): Remove.
- (__arm_vshrntq_n_s16): Remove.
- (__arm_vshrnbq_n_u16): Remove.
- (__arm_vshrntq_n_u16): Remove.
- (__arm_vshrnbq_n_s32): Remove.
- (__arm_vshrntq_n_s32): Remove.
- (__arm_vshrnbq_n_u32): Remove.
- (__arm_vshrntq_n_u32): Remove.
- (__arm_vshrnbq_m_n_s32): Remove.
- (__arm_vshrnbq_m_n_s16): Remove.
- (__arm_vshrnbq_m_n_u32): Remove.
- (__arm_vshrnbq_m_n_u16): Remove.
- (__arm_vshrntq_m_n_s32): Remove.
- (__arm_vshrntq_m_n_s16): Remove.
- (__arm_vshrntq_m_n_u32): Remove.
- (__arm_vshrntq_m_n_u16): Remove.
- (__arm_vshrnbq): Remove.
- (__arm_vshrntq): Remove.
- (__arm_vshrnbq_m): Remove.
- (__arm_vshrntq_m): Remove.
- (vrshrnbq): Remove.
- (vrshrntq): Remove.
- (vrshrnbq_m): Remove.
- (vrshrntq_m): Remove.
- (vrshrnbq_n_s16): Remove.
- (vrshrntq_n_s16): Remove.
- (vrshrnbq_n_u16): Remove.
- (vrshrntq_n_u16): Remove.
- (vrshrnbq_n_s32): Remove.
- (vrshrntq_n_s32): Remove.
- (vrshrnbq_n_u32): Remove.
- (vrshrntq_n_u32): Remove.
- (vrshrnbq_m_n_s32): Remove.
- (vrshrnbq_m_n_s16): Remove.
- (vrshrnbq_m_n_u32): Remove.
- (vrshrnbq_m_n_u16): Remove.
- (vrshrntq_m_n_s32): Remove.
- (vrshrntq_m_n_s16): Remove.
- (vrshrntq_m_n_u32): Remove.
- (vrshrntq_m_n_u16): Remove.
- (__arm_vrshrnbq_n_s16): Remove.
- (__arm_vrshrntq_n_s16): Remove.
- (__arm_vrshrnbq_n_u16): Remove.
- (__arm_vrshrntq_n_u16): Remove.
- (__arm_vrshrnbq_n_s32): Remove.
- (__arm_vrshrntq_n_s32): Remove.
- (__arm_vrshrnbq_n_u32): Remove.
- (__arm_vrshrntq_n_u32): Remove.
- (__arm_vrshrnbq_m_n_s32): Remove.
- (__arm_vrshrnbq_m_n_s16): Remove.
- (__arm_vrshrnbq_m_n_u32): Remove.
- (__arm_vrshrnbq_m_n_u16): Remove.
- (__arm_vrshrntq_m_n_s32): Remove.
- (__arm_vrshrntq_m_n_s16): Remove.
- (__arm_vrshrntq_m_n_u32): Remove.
- (__arm_vrshrntq_m_n_u16): Remove.
- (__arm_vrshrnbq): Remove.
- (__arm_vrshrntq): Remove.
- (__arm_vrshrnbq_m): Remove.
- (__arm_vrshrntq_m): Remove.
- (vqshrnbq): Remove.
- (vqshrntq): Remove.
- (vqshrnbq_m): Remove.
- (vqshrntq_m): Remove.
- (vqshrnbq_n_s16): Remove.
- (vqshrntq_n_s16): Remove.
- (vqshrnbq_n_u16): Remove.
- (vqshrntq_n_u16): Remove.
- (vqshrnbq_n_s32): Remove.
- (vqshrntq_n_s32): Remove.
- (vqshrnbq_n_u32): Remove.
- (vqshrntq_n_u32): Remove.
- (vqshrnbq_m_n_s32): Remove.
- (vqshrnbq_m_n_s16): Remove.
- (vqshrnbq_m_n_u32): Remove.
- (vqshrnbq_m_n_u16): Remove.
- (vqshrntq_m_n_s32): Remove.
- (vqshrntq_m_n_s16): Remove.
- (vqshrntq_m_n_u32): Remove.
- (vqshrntq_m_n_u16): Remove.
- (__arm_vqshrnbq_n_s16): Remove.
- (__arm_vqshrntq_n_s16): Remove.
- (__arm_vqshrnbq_n_u16): Remove.
- (__arm_vqshrntq_n_u16): Remove.
- (__arm_vqshrnbq_n_s32): Remove.
- (__arm_vqshrntq_n_s32): Remove.
- (__arm_vqshrnbq_n_u32): Remove.
- (__arm_vqshrntq_n_u32): Remove.
- (__arm_vqshrnbq_m_n_s32): Remove.
- (__arm_vqshrnbq_m_n_s16): Remove.
- (__arm_vqshrnbq_m_n_u32): Remove.
- (__arm_vqshrnbq_m_n_u16): Remove.
- (__arm_vqshrntq_m_n_s32): Remove.
- (__arm_vqshrntq_m_n_s16): Remove.
- (__arm_vqshrntq_m_n_u32): Remove.
- (__arm_vqshrntq_m_n_u16): Remove.
- (__arm_vqshrnbq): Remove.
- (__arm_vqshrntq): Remove.
- (__arm_vqshrnbq_m): Remove.
- (__arm_vqshrntq_m): Remove.
- (vqrshrnbq): Remove.
- (vqrshrntq): Remove.
- (vqrshrnbq_m): Remove.
- (vqrshrntq_m): Remove.
- (vqrshrnbq_n_s16): Remove.
- (vqrshrnbq_n_u16): Remove.
- (vqrshrnbq_n_s32): Remove.
- (vqrshrnbq_n_u32): Remove.
- (vqrshrntq_n_s16): Remove.
- (vqrshrntq_n_u16): Remove.
- (vqrshrntq_n_s32): Remove.
- (vqrshrntq_n_u32): Remove.
- (vqrshrnbq_m_n_s32): Remove.
- (vqrshrnbq_m_n_s16): Remove.
- (vqrshrnbq_m_n_u32): Remove.
- (vqrshrnbq_m_n_u16): Remove.
- (vqrshrntq_m_n_s32): Remove.
- (vqrshrntq_m_n_s16): Remove.
- (vqrshrntq_m_n_u32): Remove.
- (vqrshrntq_m_n_u16): Remove.
- (__arm_vqrshrnbq_n_s16): Remove.
- (__arm_vqrshrnbq_n_u16): Remove.
- (__arm_vqrshrnbq_n_s32): Remove.
- (__arm_vqrshrnbq_n_u32): Remove.
- (__arm_vqrshrntq_n_s16): Remove.
- (__arm_vqrshrntq_n_u16): Remove.
- (__arm_vqrshrntq_n_s32): Remove.
- (__arm_vqrshrntq_n_u32): Remove.
- (__arm_vqrshrnbq_m_n_s32): Remove.
- (__arm_vqrshrnbq_m_n_s16): Remove.
- (__arm_vqrshrnbq_m_n_u32): Remove.
- (__arm_vqrshrnbq_m_n_u16): Remove.
- (__arm_vqrshrntq_m_n_s32): Remove.
- (__arm_vqrshrntq_m_n_s16): Remove.
- (__arm_vqrshrntq_m_n_u32): Remove.
- (__arm_vqrshrntq_m_n_u16): Remove.
- (__arm_vqrshrnbq): Remove.
- (__arm_vqrshrntq): Remove.
- (__arm_vqrshrnbq_m): Remove.
- (__arm_vqrshrntq_m): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_SHRN_N, MVE_SHRN_M_N): New.
- (mve_insn): Add vqrshrnb, vqrshrnt, vqshrnb, vqshrnt, vrshrnb,
- vrshrnt, vshrnb, vshrnt.
- (isu): New.
- * config/arm/mve.md (mve_vqrshrnbq_n_<supf><mode>)
- (mve_vqrshrntq_n_<supf><mode>, mve_vqshrnbq_n_<supf><mode>)
- (mve_vqshrntq_n_<supf><mode>, mve_vrshrnbq_n_<supf><mode>)
- (mve_vrshrntq_n_<supf><mode>, mve_vshrnbq_n_<supf><mode>)
- (mve_vshrntq_n_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vqrshrnbq_m_n_<supf><mode>, mve_vqrshrntq_m_n_<supf><mode>)
- (mve_vqshrnbq_m_n_<supf><mode>, mve_vqshrntq_m_n_<supf><mode>)
- (mve_vrshrnbq_m_n_<supf><mode>, mve_vrshrntq_m_n_<supf><mode>)
- (mve_vshrnbq_m_n_<supf><mode>, mve_vshrntq_m_n_<supf><mode>):
- Merge into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_rshift_narrow):
- New.
- * config/arm/arm-mve-builtins-shapes.h (binary_rshift_narrow): New.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_NO_F): New.
- (vmaxq, vminq): New.
- * config/arm/arm-mve-builtins-base.def (vmaxq, vminq): New.
- * config/arm/arm-mve-builtins-base.h (vmaxq, vminq): New.
- * config/arm/arm_mve.h (vminq): Remove.
- (vmaxq): Remove.
- (vmaxq_m): Remove.
- (vminq_m): Remove.
- (vminq_x): Remove.
- (vmaxq_x): Remove.
- (vminq_u8): Remove.
- (vmaxq_u8): Remove.
- (vminq_s8): Remove.
- (vmaxq_s8): Remove.
- (vminq_u16): Remove.
- (vmaxq_u16): Remove.
- (vminq_s16): Remove.
- (vmaxq_s16): Remove.
- (vminq_u32): Remove.
- (vmaxq_u32): Remove.
- (vminq_s32): Remove.
- (vmaxq_s32): Remove.
- (vmaxq_m_s8): Remove.
- (vmaxq_m_s32): Remove.
- (vmaxq_m_s16): Remove.
- (vmaxq_m_u8): Remove.
- (vmaxq_m_u32): Remove.
- (vmaxq_m_u16): Remove.
- (vminq_m_s8): Remove.
- (vminq_m_s32): Remove.
- (vminq_m_s16): Remove.
- (vminq_m_u8): Remove.
- (vminq_m_u32): Remove.
- (vminq_m_u16): Remove.
- (vminq_x_s8): Remove.
- (vminq_x_s16): Remove.
- (vminq_x_s32): Remove.
- (vminq_x_u8): Remove.
- (vminq_x_u16): Remove.
- (vminq_x_u32): Remove.
- (vmaxq_x_s8): Remove.
- (vmaxq_x_s16): Remove.
- (vmaxq_x_s32): Remove.
- (vmaxq_x_u8): Remove.
- (vmaxq_x_u16): Remove.
- (vmaxq_x_u32): Remove.
- (__arm_vminq_u8): Remove.
- (__arm_vmaxq_u8): Remove.
- (__arm_vminq_s8): Remove.
- (__arm_vmaxq_s8): Remove.
- (__arm_vminq_u16): Remove.
- (__arm_vmaxq_u16): Remove.
- (__arm_vminq_s16): Remove.
- (__arm_vmaxq_s16): Remove.
- (__arm_vminq_u32): Remove.
- (__arm_vmaxq_u32): Remove.
- (__arm_vminq_s32): Remove.
- (__arm_vmaxq_s32): Remove.
- (__arm_vmaxq_m_s8): Remove.
- (__arm_vmaxq_m_s32): Remove.
- (__arm_vmaxq_m_s16): Remove.
- (__arm_vmaxq_m_u8): Remove.
- (__arm_vmaxq_m_u32): Remove.
- (__arm_vmaxq_m_u16): Remove.
- (__arm_vminq_m_s8): Remove.
- (__arm_vminq_m_s32): Remove.
- (__arm_vminq_m_s16): Remove.
- (__arm_vminq_m_u8): Remove.
- (__arm_vminq_m_u32): Remove.
- (__arm_vminq_m_u16): Remove.
- (__arm_vminq_x_s8): Remove.
- (__arm_vminq_x_s16): Remove.
- (__arm_vminq_x_s32): Remove.
- (__arm_vminq_x_u8): Remove.
- (__arm_vminq_x_u16): Remove.
- (__arm_vminq_x_u32): Remove.
- (__arm_vmaxq_x_s8): Remove.
- (__arm_vmaxq_x_s16): Remove.
- (__arm_vmaxq_x_s32): Remove.
- (__arm_vmaxq_x_u8): Remove.
- (__arm_vmaxq_x_u16): Remove.
- (__arm_vmaxq_x_u32): Remove.
- (__arm_vminq): Remove.
- (__arm_vmaxq): Remove.
- (__arm_vmaxq_m): Remove.
- (__arm_vminq_m): Remove.
- (__arm_vminq_x): Remove.
- (__arm_vmaxq_x): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MAX_MIN_SU): New.
- (max_min_su_str): New.
- (max_min_supf): New.
- * config/arm/mve.md (mve_vmaxq_s<mode>, mve_vmaxq_u<mode>)
- (mve_vminq_s<mode>, mve_vminq_u<mode>): Merge into ...
- (mve_<max_min_su_str>q_<max_min_supf><mode>): ... this.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_M_N_R): New.
- (vqshlq, vshlq): New.
- * config/arm/arm-mve-builtins-base.def (vqshlq, vshlq): New.
- * config/arm/arm-mve-builtins-base.h (vqshlq, vshlq): New.
- * config/arm/arm_mve.h (vshlq): Remove.
- (vshlq_r): Remove.
- (vshlq_n): Remove.
- (vshlq_m_r): Remove.
- (vshlq_m): Remove.
- (vshlq_m_n): Remove.
- (vshlq_x): Remove.
- (vshlq_x_n): Remove.
- (vshlq_s8): Remove.
- (vshlq_s16): Remove.
- (vshlq_s32): Remove.
- (vshlq_u8): Remove.
- (vshlq_u16): Remove.
- (vshlq_u32): Remove.
- (vshlq_r_u8): Remove.
- (vshlq_n_u8): Remove.
- (vshlq_r_s8): Remove.
- (vshlq_n_s8): Remove.
- (vshlq_r_u16): Remove.
- (vshlq_n_u16): Remove.
- (vshlq_r_s16): Remove.
- (vshlq_n_s16): Remove.
- (vshlq_r_u32): Remove.
- (vshlq_n_u32): Remove.
- (vshlq_r_s32): Remove.
- (vshlq_n_s32): Remove.
- (vshlq_m_r_u8): Remove.
- (vshlq_m_r_s8): Remove.
- (vshlq_m_r_u16): Remove.
- (vshlq_m_r_s16): Remove.
- (vshlq_m_r_u32): Remove.
- (vshlq_m_r_s32): Remove.
- (vshlq_m_u8): Remove.
- (vshlq_m_s8): Remove.
- (vshlq_m_u16): Remove.
- (vshlq_m_s16): Remove.
- (vshlq_m_u32): Remove.
- (vshlq_m_s32): Remove.
- (vshlq_m_n_s8): Remove.
- (vshlq_m_n_s32): Remove.
- (vshlq_m_n_s16): Remove.
- (vshlq_m_n_u8): Remove.
- (vshlq_m_n_u32): Remove.
- (vshlq_m_n_u16): Remove.
- (vshlq_x_s8): Remove.
- (vshlq_x_s16): Remove.
- (vshlq_x_s32): Remove.
- (vshlq_x_u8): Remove.
- (vshlq_x_u16): Remove.
- (vshlq_x_u32): Remove.
- (vshlq_x_n_s8): Remove.
- (vshlq_x_n_s16): Remove.
- (vshlq_x_n_s32): Remove.
- (vshlq_x_n_u8): Remove.
- (vshlq_x_n_u16): Remove.
- (vshlq_x_n_u32): Remove.
- (__arm_vshlq_s8): Remove.
- (__arm_vshlq_s16): Remove.
- (__arm_vshlq_s32): Remove.
- (__arm_vshlq_u8): Remove.
- (__arm_vshlq_u16): Remove.
- (__arm_vshlq_u32): Remove.
- (__arm_vshlq_r_u8): Remove.
- (__arm_vshlq_n_u8): Remove.
- (__arm_vshlq_r_s8): Remove.
- (__arm_vshlq_n_s8): Remove.
- (__arm_vshlq_r_u16): Remove.
- (__arm_vshlq_n_u16): Remove.
- (__arm_vshlq_r_s16): Remove.
- (__arm_vshlq_n_s16): Remove.
- (__arm_vshlq_r_u32): Remove.
- (__arm_vshlq_n_u32): Remove.
- (__arm_vshlq_r_s32): Remove.
- (__arm_vshlq_n_s32): Remove.
- (__arm_vshlq_m_r_u8): Remove.
- (__arm_vshlq_m_r_s8): Remove.
- (__arm_vshlq_m_r_u16): Remove.
- (__arm_vshlq_m_r_s16): Remove.
- (__arm_vshlq_m_r_u32): Remove.
- (__arm_vshlq_m_r_s32): Remove.
- (__arm_vshlq_m_u8): Remove.
- (__arm_vshlq_m_s8): Remove.
- (__arm_vshlq_m_u16): Remove.
- (__arm_vshlq_m_s16): Remove.
- (__arm_vshlq_m_u32): Remove.
- (__arm_vshlq_m_s32): Remove.
- (__arm_vshlq_m_n_s8): Remove.
- (__arm_vshlq_m_n_s32): Remove.
- (__arm_vshlq_m_n_s16): Remove.
- (__arm_vshlq_m_n_u8): Remove.
- (__arm_vshlq_m_n_u32): Remove.
- (__arm_vshlq_m_n_u16): Remove.
- (__arm_vshlq_x_s8): Remove.
- (__arm_vshlq_x_s16): Remove.
- (__arm_vshlq_x_s32): Remove.
- (__arm_vshlq_x_u8): Remove.
- (__arm_vshlq_x_u16): Remove.
- (__arm_vshlq_x_u32): Remove.
- (__arm_vshlq_x_n_s8): Remove.
- (__arm_vshlq_x_n_s16): Remove.
- (__arm_vshlq_x_n_s32): Remove.
- (__arm_vshlq_x_n_u8): Remove.
- (__arm_vshlq_x_n_u16): Remove.
- (__arm_vshlq_x_n_u32): Remove.
- (__arm_vshlq): Remove.
- (__arm_vshlq_r): Remove.
- (__arm_vshlq_n): Remove.
- (__arm_vshlq_m_r): Remove.
- (__arm_vshlq_m): Remove.
- (__arm_vshlq_m_n): Remove.
- (__arm_vshlq_x): Remove.
- (__arm_vshlq_x_n): Remove.
- (vqshlq): Remove.
- (vqshlq_r): Remove.
- (vqshlq_n): Remove.
- (vqshlq_m_r): Remove.
- (vqshlq_m_n): Remove.
- (vqshlq_m): Remove.
- (vqshlq_u8): Remove.
- (vqshlq_r_u8): Remove.
- (vqshlq_n_u8): Remove.
- (vqshlq_s8): Remove.
- (vqshlq_r_s8): Remove.
- (vqshlq_n_s8): Remove.
- (vqshlq_u16): Remove.
- (vqshlq_r_u16): Remove.
- (vqshlq_n_u16): Remove.
- (vqshlq_s16): Remove.
- (vqshlq_r_s16): Remove.
- (vqshlq_n_s16): Remove.
- (vqshlq_u32): Remove.
- (vqshlq_r_u32): Remove.
- (vqshlq_n_u32): Remove.
- (vqshlq_s32): Remove.
- (vqshlq_r_s32): Remove.
- (vqshlq_n_s32): Remove.
- (vqshlq_m_r_u8): Remove.
- (vqshlq_m_r_s8): Remove.
- (vqshlq_m_r_u16): Remove.
- (vqshlq_m_r_s16): Remove.
- (vqshlq_m_r_u32): Remove.
- (vqshlq_m_r_s32): Remove.
- (vqshlq_m_n_s8): Remove.
- (vqshlq_m_n_s32): Remove.
- (vqshlq_m_n_s16): Remove.
- (vqshlq_m_n_u8): Remove.
- (vqshlq_m_n_u32): Remove.
- (vqshlq_m_n_u16): Remove.
- (vqshlq_m_s8): Remove.
- (vqshlq_m_s32): Remove.
- (vqshlq_m_s16): Remove.
- (vqshlq_m_u8): Remove.
- (vqshlq_m_u32): Remove.
- (vqshlq_m_u16): Remove.
- (__arm_vqshlq_u8): Remove.
- (__arm_vqshlq_r_u8): Remove.
- (__arm_vqshlq_n_u8): Remove.
- (__arm_vqshlq_s8): Remove.
- (__arm_vqshlq_r_s8): Remove.
- (__arm_vqshlq_n_s8): Remove.
- (__arm_vqshlq_u16): Remove.
- (__arm_vqshlq_r_u16): Remove.
- (__arm_vqshlq_n_u16): Remove.
- (__arm_vqshlq_s16): Remove.
- (__arm_vqshlq_r_s16): Remove.
- (__arm_vqshlq_n_s16): Remove.
- (__arm_vqshlq_u32): Remove.
- (__arm_vqshlq_r_u32): Remove.
- (__arm_vqshlq_n_u32): Remove.
- (__arm_vqshlq_s32): Remove.
- (__arm_vqshlq_r_s32): Remove.
- (__arm_vqshlq_n_s32): Remove.
- (__arm_vqshlq_m_r_u8): Remove.
- (__arm_vqshlq_m_r_s8): Remove.
- (__arm_vqshlq_m_r_u16): Remove.
- (__arm_vqshlq_m_r_s16): Remove.
- (__arm_vqshlq_m_r_u32): Remove.
- (__arm_vqshlq_m_r_s32): Remove.
- (__arm_vqshlq_m_n_s8): Remove.
- (__arm_vqshlq_m_n_s32): Remove.
- (__arm_vqshlq_m_n_s16): Remove.
- (__arm_vqshlq_m_n_u8): Remove.
- (__arm_vqshlq_m_n_u32): Remove.
- (__arm_vqshlq_m_n_u16): Remove.
- (__arm_vqshlq_m_s8): Remove.
- (__arm_vqshlq_m_s32): Remove.
- (__arm_vqshlq_m_s16): Remove.
- (__arm_vqshlq_m_u8): Remove.
- (__arm_vqshlq_m_u32): Remove.
- (__arm_vqshlq_m_u16): Remove.
- (__arm_vqshlq): Remove.
- (__arm_vqshlq_r): Remove.
- (__arm_vqshlq_n): Remove.
- (__arm_vqshlq_m_r): Remove.
- (__arm_vqshlq_m_n): Remove.
- (__arm_vqshlq_m): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-functions.h (class
- unspec_mve_function_exact_insn_vshl): New.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_lshift_r): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_lshift_r): New.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins.cc (has_inactive_argument)
- (finish_opt_n_resolution): Handle MODE_r.
- * config/arm/arm-mve-builtins.def (r): New mode.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_lshift): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_lshift): New.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_N): New.
- (vabdq): New.
- * config/arm/arm-mve-builtins-base.def (vabdq): New.
- * config/arm/arm-mve-builtins-base.h (vabdq): New.
- * config/arm/arm_mve.h (vabdq): Remove.
- (vabdq_m): Remove.
- (vabdq_x): Remove.
- (vabdq_u8): Remove.
- (vabdq_s8): Remove.
- (vabdq_u16): Remove.
- (vabdq_s16): Remove.
- (vabdq_u32): Remove.
- (vabdq_s32): Remove.
- (vabdq_f16): Remove.
- (vabdq_f32): Remove.
- (vabdq_m_s8): Remove.
- (vabdq_m_s32): Remove.
- (vabdq_m_s16): Remove.
- (vabdq_m_u8): Remove.
- (vabdq_m_u32): Remove.
- (vabdq_m_u16): Remove.
- (vabdq_m_f32): Remove.
- (vabdq_m_f16): Remove.
- (vabdq_x_s8): Remove.
- (vabdq_x_s16): Remove.
- (vabdq_x_s32): Remove.
- (vabdq_x_u8): Remove.
- (vabdq_x_u16): Remove.
- (vabdq_x_u32): Remove.
- (vabdq_x_f16): Remove.
- (vabdq_x_f32): Remove.
- (__arm_vabdq_u8): Remove.
- (__arm_vabdq_s8): Remove.
- (__arm_vabdq_u16): Remove.
- (__arm_vabdq_s16): Remove.
- (__arm_vabdq_u32): Remove.
- (__arm_vabdq_s32): Remove.
- (__arm_vabdq_m_s8): Remove.
- (__arm_vabdq_m_s32): Remove.
- (__arm_vabdq_m_s16): Remove.
- (__arm_vabdq_m_u8): Remove.
- (__arm_vabdq_m_u32): Remove.
- (__arm_vabdq_m_u16): Remove.
- (__arm_vabdq_x_s8): Remove.
- (__arm_vabdq_x_s16): Remove.
- (__arm_vabdq_x_s32): Remove.
- (__arm_vabdq_x_u8): Remove.
- (__arm_vabdq_x_u16): Remove.
- (__arm_vabdq_x_u32): Remove.
- (__arm_vabdq_f16): Remove.
- (__arm_vabdq_f32): Remove.
- (__arm_vabdq_m_f32): Remove.
- (__arm_vabdq_m_f16): Remove.
- (__arm_vabdq_x_f16): Remove.
- (__arm_vabdq_x_f32): Remove.
- (__arm_vabdq): Remove.
- (__arm_vabdq_m): Remove.
- (__arm_vabdq_x): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_FP_M_BINARY): Add vabdq.
- (MVE_FP_VABDQ_ONLY): New.
- (mve_insn): Add vabd.
- * config/arm/mve.md (mve_vabdq_f<mode>): Move into ...
- (@mve_<mve_insn>q_f<mode>): ... this.
- (mve_vabdq_m_f<mode>): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vqrdmulhq): New.
- * config/arm/arm-mve-builtins-base.def (vqrdmulhq): New.
- * config/arm/arm-mve-builtins-base.h (vqrdmulhq): New.
- * config/arm/arm_mve.h (vqrdmulhq): Remove.
- (vqrdmulhq_m): Remove.
- (vqrdmulhq_s8): Remove.
- (vqrdmulhq_n_s8): Remove.
- (vqrdmulhq_s16): Remove.
- (vqrdmulhq_n_s16): Remove.
- (vqrdmulhq_s32): Remove.
- (vqrdmulhq_n_s32): Remove.
- (vqrdmulhq_m_n_s8): Remove.
- (vqrdmulhq_m_n_s32): Remove.
- (vqrdmulhq_m_n_s16): Remove.
- (vqrdmulhq_m_s8): Remove.
- (vqrdmulhq_m_s32): Remove.
- (vqrdmulhq_m_s16): Remove.
- (__arm_vqrdmulhq_s8): Remove.
- (__arm_vqrdmulhq_n_s8): Remove.
- (__arm_vqrdmulhq_s16): Remove.
- (__arm_vqrdmulhq_n_s16): Remove.
- (__arm_vqrdmulhq_s32): Remove.
- (__arm_vqrdmulhq_n_s32): Remove.
- (__arm_vqrdmulhq_m_n_s8): Remove.
- (__arm_vqrdmulhq_m_n_s32): Remove.
- (__arm_vqrdmulhq_m_n_s16): Remove.
- (__arm_vqrdmulhq_m_s8): Remove.
- (__arm_vqrdmulhq_m_s32): Remove.
- (__arm_vqrdmulhq_m_s16): Remove.
- (__arm_vqrdmulhq): Remove.
- (__arm_vqrdmulhq_m): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_SHIFT_M_R, MVE_SHIFT_M_N)
- (MVE_SHIFT_N, MVE_SHIFT_R): New.
- (mve_insn): Add vqshl, vshl.
- * config/arm/mve.md (mve_vqshlq_n_<supf><mode>)
- (mve_vshlq_n_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vqshlq_r_<supf><mode>, mve_vshlq_r_<supf><mode>): Merge into
- ...
- (@mve_<mve_insn>q_r_<supf><mode>): ... this.
- (mve_vqshlq_m_r_<supf><mode>, mve_vshlq_m_r_<supf><mode>): Merge
- into ...
- (@mve_<mve_insn>q_m_r_<supf><mode>): ... this.
- (mve_vqshlq_m_n_<supf><mode>, mve_vshlq_m_n_<supf><mode>): Merge
- into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
- * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Transform
- into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vqrshlq, vrshlq): New.
- * config/arm/arm-mve-builtins-base.def (vqrshlq, vrshlq): New.
- * config/arm/arm-mve-builtins-base.h (vqrshlq, vrshlq): New.
- * config/arm/arm-mve-builtins.cc (has_inactive_argument): Handle
- vqrshlq, vrshlq.
- * config/arm/arm_mve.h (vrshlq): Remove.
- (vrshlq_m_n): Remove.
- (vrshlq_m): Remove.
- (vrshlq_x): Remove.
- (vrshlq_u8): Remove.
- (vrshlq_n_u8): Remove.
- (vrshlq_s8): Remove.
- (vrshlq_n_s8): Remove.
- (vrshlq_u16): Remove.
- (vrshlq_n_u16): Remove.
- (vrshlq_s16): Remove.
- (vrshlq_n_s16): Remove.
- (vrshlq_u32): Remove.
- (vrshlq_n_u32): Remove.
- (vrshlq_s32): Remove.
- (vrshlq_n_s32): Remove.
- (vrshlq_m_n_u8): Remove.
- (vrshlq_m_n_s8): Remove.
- (vrshlq_m_n_u16): Remove.
- (vrshlq_m_n_s16): Remove.
- (vrshlq_m_n_u32): Remove.
- (vrshlq_m_n_s32): Remove.
- (vrshlq_m_s8): Remove.
- (vrshlq_m_s32): Remove.
- (vrshlq_m_s16): Remove.
- (vrshlq_m_u8): Remove.
- (vrshlq_m_u32): Remove.
- (vrshlq_m_u16): Remove.
- (vrshlq_x_s8): Remove.
- (vrshlq_x_s16): Remove.
- (vrshlq_x_s32): Remove.
- (vrshlq_x_u8): Remove.
- (vrshlq_x_u16): Remove.
- (vrshlq_x_u32): Remove.
- (__arm_vrshlq_u8): Remove.
- (__arm_vrshlq_n_u8): Remove.
- (__arm_vrshlq_s8): Remove.
- (__arm_vrshlq_n_s8): Remove.
- (__arm_vrshlq_u16): Remove.
- (__arm_vrshlq_n_u16): Remove.
- (__arm_vrshlq_s16): Remove.
- (__arm_vrshlq_n_s16): Remove.
- (__arm_vrshlq_u32): Remove.
- (__arm_vrshlq_n_u32): Remove.
- (__arm_vrshlq_s32): Remove.
- (__arm_vrshlq_n_s32): Remove.
- (__arm_vrshlq_m_n_u8): Remove.
- (__arm_vrshlq_m_n_s8): Remove.
- (__arm_vrshlq_m_n_u16): Remove.
- (__arm_vrshlq_m_n_s16): Remove.
- (__arm_vrshlq_m_n_u32): Remove.
- (__arm_vrshlq_m_n_s32): Remove.
- (__arm_vrshlq_m_s8): Remove.
- (__arm_vrshlq_m_s32): Remove.
- (__arm_vrshlq_m_s16): Remove.
- (__arm_vrshlq_m_u8): Remove.
- (__arm_vrshlq_m_u32): Remove.
- (__arm_vrshlq_m_u16): Remove.
- (__arm_vrshlq_x_s8): Remove.
- (__arm_vrshlq_x_s16): Remove.
- (__arm_vrshlq_x_s32): Remove.
- (__arm_vrshlq_x_u8): Remove.
- (__arm_vrshlq_x_u16): Remove.
- (__arm_vrshlq_x_u32): Remove.
- (__arm_vrshlq): Remove.
- (__arm_vrshlq_m_n): Remove.
- (__arm_vrshlq_m): Remove.
- (__arm_vrshlq_x): Remove.
- (vqrshlq): Remove.
- (vqrshlq_m_n): Remove.
- (vqrshlq_m): Remove.
- (vqrshlq_u8): Remove.
- (vqrshlq_n_u8): Remove.
- (vqrshlq_s8): Remove.
- (vqrshlq_n_s8): Remove.
- (vqrshlq_u16): Remove.
- (vqrshlq_n_u16): Remove.
- (vqrshlq_s16): Remove.
- (vqrshlq_n_s16): Remove.
- (vqrshlq_u32): Remove.
- (vqrshlq_n_u32): Remove.
- (vqrshlq_s32): Remove.
- (vqrshlq_n_s32): Remove.
- (vqrshlq_m_n_u8): Remove.
- (vqrshlq_m_n_s8): Remove.
- (vqrshlq_m_n_u16): Remove.
- (vqrshlq_m_n_s16): Remove.
- (vqrshlq_m_n_u32): Remove.
- (vqrshlq_m_n_s32): Remove.
- (vqrshlq_m_s8): Remove.
- (vqrshlq_m_s32): Remove.
- (vqrshlq_m_s16): Remove.
- (vqrshlq_m_u8): Remove.
- (vqrshlq_m_u32): Remove.
- (vqrshlq_m_u16): Remove.
- (__arm_vqrshlq_u8): Remove.
- (__arm_vqrshlq_n_u8): Remove.
- (__arm_vqrshlq_s8): Remove.
- (__arm_vqrshlq_n_s8): Remove.
- (__arm_vqrshlq_u16): Remove.
- (__arm_vqrshlq_n_u16): Remove.
- (__arm_vqrshlq_s16): Remove.
- (__arm_vqrshlq_n_s16): Remove.
- (__arm_vqrshlq_u32): Remove.
- (__arm_vqrshlq_n_u32): Remove.
- (__arm_vqrshlq_s32): Remove.
- (__arm_vqrshlq_n_s32): Remove.
- (__arm_vqrshlq_m_n_u8): Remove.
- (__arm_vqrshlq_m_n_s8): Remove.
- (__arm_vqrshlq_m_n_u16): Remove.
- (__arm_vqrshlq_m_n_s16): Remove.
- (__arm_vqrshlq_m_n_u32): Remove.
- (__arm_vqrshlq_m_n_s32): Remove.
- (__arm_vqrshlq_m_s8): Remove.
- (__arm_vqrshlq_m_s32): Remove.
- (__arm_vqrshlq_m_s16): Remove.
- (__arm_vqrshlq_m_u8): Remove.
- (__arm_vqrshlq_m_u32): Remove.
- (__arm_vqrshlq_m_u16): Remove.
- (__arm_vqrshlq): Remove.
- (__arm_vqrshlq_m_n): Remove.
- (__arm_vqrshlq_m): Remove.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_RSHIFT_M_N, MVE_RSHIFT_N): New.
- (mve_insn): Add vqrshl, vrshl.
- * config/arm/mve.md (mve_vqrshlq_n_<supf><mode>)
- (mve_vrshlq_n_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vqrshlq_m_n_<supf><mode>, mve_vrshlq_m_n_<supf><mode>): Merge
- into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_round_lshift): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_round_lshift): New.
-
-2023-05-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/109615
- * config/riscv/riscv-vsetvl.cc (avl_info::multiple_source_equal_p): Add
- denegrate PHI optmization.
-
-2023-05-05 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/predicates.md (register_no_SP_operand):
- Rename from index_register_operand.
- (call_register_operand): Update for rename.
- * config/i386/i386.md (*lea<mode>_general_[1234]): Update for rename.
-
-2023-05-05 Tamar Christina <tamar.christina@arm.com>
-
- PR bootstrap/84402
- * Makefile.in (NUM_MATCH_SPLITS, MATCH_SPLITS_SEQ,
- GIMPLE_MATCH_PD_SEQ_SRC, GIMPLE_MATCH_PD_SEQ_O,
- GENERIC_MATCH_PD_SEQ_SRC, GENERIC_MATCH_PD_SEQ_O): New.
- (OBJS, MOSTLYCLEANFILES, .PRECIOUS): Use them.
- (s-match): Split into s-generic-match and s-gimple-match.
- * configure.ac (with-matchpd-partitions,
- DEFAULT_MATCHPD_PARTITIONS): New.
- * configure: Regenerate.
+ * doc/sourcebuild.texi (Effective-Target Keywords, Other
+ attribugs): Document linker_plugin.
+ (Require Support): Document dg-require-linker-plugin.
-2023-05-05 Tamar Christina <tamar.christina@arm.com>
+2024-02-16 Kito Cheng <kito.cheng@sifive.com>
- PR bootstrap/84402
- * genmatch.cc (emit_func, SIZED_BASED_CHUNKS, get_out_file): New.
- (decision_tree::gen): Accept list of files instead of single and update
- to write function definition to header and main file.
- (write_predicate): Likewise.
- (write_header): Emit pragmas and new includes.
- (main): Create file buffers and cleanup.
- (showUsage, write_header_includes): New.
+ PR target/109349
+ * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
+ * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
+ (RISCV_MINOR_VERSION_BASE): Ditto.
+ (RISCV_REVISION_VERSION_BASE): Ditto.
+ * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
+ rather than magic number.
+ * config/riscv/riscv.h (riscv_arch_help): New.
+ (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
+ (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
+ --print-supported-extensions.
+ * config/riscv/riscv.opt (march=help): New.
+ (print-supported-extensions): New.
+ (-print-supported-extensions): New.
+ * doc/invoke.texi (RISC-V Options): Document -march=help.
-2023-05-05 Tamar Christina <tamar.christina@arm.com>
+2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
- PR bootstrap/84402
- * Makefile.in (OBJS): Add gimple-match-exports.o.
- * genmatch.cc (decision_tree::gen): Export gimple_gimplify helpers.
- * gimple-match-head.cc (gimple_simplify, gimple_resimplify1,
- gimple_resimplify2, gimple_resimplify3, gimple_resimplify4,
- gimple_resimplify5, constant_for_folding, convert_conditional_op,
- maybe_resimplify_conditional_op, gimple_match_op::resimplify,
- maybe_build_generic_op, build_call_internal, maybe_push_res_to_seq,
- do_valueize, try_conditional_simplification, gimple_extract,
- gimple_extract_op, canonicalize_code, commutative_binary_op_p,
- commutative_ternary_op_p, first_commutative_argument,
- associative_binary_op_p, directly_supported_p,
- get_conditional_internal_fn): Moved to gimple-match-exports.cc
- * gimple-match-exports.cc: New file.
-
-2023-05-05 Tamar Christina <tamar.christina@arm.com>
+ PR target/113780
+ * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
+ for indirect calls with 4 or more arguments in pac-enabled functions.
- PR bootstrap/84402
- * genmatch.cc (decision_tree::gen, write_predicate): Generate new
- debug_dump var.
- (dt_simplify::gen_1): Use it.
+2024-02-15 David Faust <david.faust@oracle.com>
-2023-05-05 Tamar Christina <tamar.christina@arm.com>
+ * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
+ use ldxb instead of ldxh.
- PR bootstrap/84402
- * genmatch.cc (output_line_directive): Only emit commented directive
- when -vv.
+2024-02-15 Jakub Jelinek <jakub@redhat.com>
-2023-05-05 Tamar Christina <tamar.christina@arm.com>
+ PR middle-end/113921
+ * cfgrtl.h (prepend_insn_to_edge): New declaration.
+ * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
+ comment.
+ (prepend_insn_to_edge): New function.
+ * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
+ insert_insn_on_edge.
+
+2024-02-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/111156
+ * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
+ at the pattern stmt if any.
+
+2024-02-15 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/113927
+ * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
+ * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
+ * config/avr/avr.cc (avr_adiw_reg_p): New function.
+ (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
+ Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
+ * config/avr/avr.md: Same.
+ (attr "isa") <tiny, no_tiny>: Remove.
+ <adiw, no_adiw>: Add.
+ (define_insn, define_insn_and_split): When an alternative has
+ constraint "w", then set attribute "isa" to "adiw".
+ * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
+ Built-in define __AVR_HAVE_ADIW__.
+ * doc/invoke.texi (AVR Options): Document it.
+
+2024-02-15 Andrew Stubbs <ams@baylibre.com>
- PR bootstrap/84402
- * genmatch.cc (dt_simplify::gen_1): Only emit labels if used.
+ * config/gcn/gcn-valu.md
+ (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
+ * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
+ details are supported on RDNA devices.
-2023-05-05 Tobias Burnus <tobias@codesourcery.com>
+2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
- * config/gcn/gcn.cc (gcn_vectorize_builtin_vectorized_function): Remove
- unused in_mode/in_n variables.
+ PR middle-end/113508
+ * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
+ usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
+ smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
+ Add sentence about what the mode m is.
-2023-05-05 Richard Biener <rguenther@suse.de>
+2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
- PR tree-optimization/109735
- * tree-vect-stmts.cc (vectorizable_operation): Perform
- conversion for POINTER_DIFF_EXPR unconditionally.
+ * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
+ smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
+ var.
-2023-05-05 Uros Bizjak <ubizjak@gmail.com>
+2024-02-15 Richard Biener <rguenther@suse.de>
- * config/i386/mmx.md (mulv2si3): New expander.
- (*mulv2si3): New insn pattern.
+ * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
+ stmts.
-2023-05-05 Tobias Burnus <tobias@codesourcery.com>
- Thomas Schwinge <thomas@codesourcery.com>
+2024-02-15 Jakub Jelinek <jakub@redhat.com>
- PR libgomp/108098
- * config/nvptx/mkoffload.cc (process): Emit dummy procedure
- alongside reverse-offload function table to prevent NULL values
- of the function addresses.
+ PR tree-optimization/113567
+ * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
+ _BitInt multiplication, division or modulo with
+ SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
+ force the affected inputs into a new SSA_NAME.
-2023-05-05 Jakub Jelinek <jakub@redhat.com>
-
- * builtins.cc (do_mpfr_ckconv, do_mpc_ckconv): Fix comment typo,
- mpft_t -> mpfr_t.
- * fold-const-call.cc (do_mpfr_ckconv, do_mpc_ckconv): Likewise.
-
-2023-05-05 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109732
- * tree-ssa-phiopt.cc (match_simplify_replacement): Fix the selection
- of the argtrue/argfalse.
-
-2023-05-05 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109722
- * match.pd: Extend the `ABS<a> == 0` pattern
- to cover `ABSU<a> == 0` too.
-
-2023-05-04 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/109733
- * config/i386/predicates.md (index_reg_operand): New predicate.
- * config/i386/i386.md (ashift to lea spliter): Use
- general_reg_operand and index_reg_operand predicates.
-
-2023-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>_insn_le):
- Rename and reimplement with RTL codes to...
- (aarch64_<optab>hn2<mode>_insn_le): .. This.
- (aarch64_r<optab>hn2<mode>_insn_le): New pattern.
- (aarch64_<sur><addsub>hn2<mode>_insn_be): Rename and reimplement with RTL
- codes to...
- (aarch64_<optab>hn2<mode>_insn_be): ... This.
- (aarch64_r<optab>hn2<mode>_insn_be): New pattern.
- (aarch64_<sur><addsub>hn2<mode>): Rename and adjust expander to...
- (aarch64_<optab>hn2<mode>): ... This.
- (aarch64_r<optab>hn2<mode>): New expander.
- * config/aarch64/iterators.md (UNSPEC_ADDHN, UNSPEC_RADDHN,
- UNSPEC_SUBHN, UNSPEC_RSUBHN): Delete unspecs.
- (ADDSUBHN): Delete.
- (sur): Remove handling of the above.
- (addsub): Likewise.
-
-2023-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>_insn_le):
- Delete.
- (aarch64_<optab>hn<mode>_insn<vczle><vczbe>): New define_insn.
- (aarch64_<sur><addsub>hn<mode>_insn_be): Delete.
- (aarch64_r<optab>hn<mode>_insn<vczle><vczbe>): New define_insn.
- (aarch64_<sur><addsub>hn<mode>): Delete.
- (aarch64_<optab>hn<mode>): New define_expand.
- (aarch64_r<optab>hn<mode>): Likewise.
- * config/aarch64/predicates.md (aarch64_simd_raddsubhn_imm_vec):
- New predicate.
-
-2023-05-04 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Handle
- diamond form bb with forwarder only empty blocks better.
-
-2023-05-04 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-threadupdate.cc (copy_phi_arg_into_existing_phi): Move to ...
- * tree-cfg.cc (copy_phi_arg_into_existing_phi): Here and remove static.
- (gimple_duplicate_sese_tail): Use copy_phi_arg_into_existing_phi instead
- of an inline version of it.
- * tree-cfgcleanup.cc (remove_forwarder_block): Likewise.
- * tree-cfg.h (copy_phi_arg_into_existing_phi): New declaration.
-
-2023-05-04 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Change
- the default argument value for dce_ssa_names to nullptr.
- Check to make sure dce_ssa_names is a non-nullptr before
- calling simple_dce_from_worklist.
-
-2023-05-04 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/predicates.md (index_register_operand): Reject
- arg_pointer_rtx, frame_pointer_rtx, stack_pointer_rtx and
- VIRTUAL_REGISTER_P operands. Allow subregs of memory before reload.
- (call_register_no_elim_operand): Rewrite as ...
- (call_register_operand): ... this.
- (call_insn_operand): Use call_register_operand predicate.
-
-2023-05-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109721
- * tree-vect-stmts.cc (vectorizable_operation): Make sure
- to test word_mode for all !target_support_p operations.
-
-2023-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_<su>aba<mode>): Rename to...
- (aarch64_<su>aba<mode><vczle><vczbe>): ... This.
- (aarch64_mla<mode>): Rename to...
- (aarch64_mla<mode><vczle><vczbe>): ... This.
- (*aarch64_mla_elt<mode>): Rename to...
- (*aarch64_mla_elt<mode><vczle><vczbe>): ... This.
- (*aarch64_mla_elt_<vswap_width_name><mode>): Rename to...
- (*aarch64_mla_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
- (aarch64_mla_n<mode>): Rename to...
- (aarch64_mla_n<mode><vczle><vczbe>): ... This.
- (aarch64_mls<mode>): Rename to...
- (aarch64_mls<mode><vczle><vczbe>): ... This.
- (*aarch64_mls_elt<mode>): Rename to...
- (*aarch64_mls_elt<mode><vczle><vczbe>): ... This.
- (*aarch64_mls_elt_<vswap_width_name><mode>): Rename to...
- (*aarch64_mls_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
- (aarch64_mls_n<mode>): Rename to...
- (aarch64_mls_n<mode><vczle><vczbe>): ... This.
- (fma<mode>4): Rename to...
- (fma<mode>4<vczle><vczbe>): ... This.
- (*aarch64_fma4_elt<mode>): Rename to...
- (*aarch64_fma4_elt<mode><vczle><vczbe>): ... This.
- (*aarch64_fma4_elt_<vswap_width_name><mode>): Rename to...
- (*aarch64_fma4_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
- (*aarch64_fma4_elt_from_dup<mode>): Rename to...
- (*aarch64_fma4_elt_from_dup<mode><vczle><vczbe>): ... This.
- (fnma<mode>4): Rename to...
- (fnma<mode>4<vczle><vczbe>): ... This.
- (*aarch64_fnma4_elt<mode>): Rename to...
- (*aarch64_fnma4_elt<mode><vczle><vczbe>): ... This.
- (*aarch64_fnma4_elt_<vswap_width_name><mode>): Rename to...
- (*aarch64_fnma4_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
- (*aarch64_fnma4_elt_from_dup<mode>): Rename to...
- (*aarch64_fnma4_elt_from_dup<mode><vczle><vczbe>): ... This.
- (aarch64_simd_bsl<mode>_internal): Rename to...
- (aarch64_simd_bsl<mode>_internal<vczle><vczbe>): ... This.
- (*aarch64_simd_bsl<mode>_alt): Rename to...
- (*aarch64_simd_bsl<mode>_alt<vczle><vczbe>): ... This.
-
-2023-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>): Rename to...
- (aarch64_<su>abd<mode><vczle><vczbe>): ... This.
- (fabd<mode>3): Rename to...
- (fabd<mode>3<vczle><vczbe>): ... This.
- (aarch64_<optab>p<mode>): Rename to...
- (aarch64_<optab>p<mode><vczle><vczbe>): ... This.
- (aarch64_faddp<mode>): Rename to...
- (aarch64_faddp<mode><vczle><vczbe>): ... This.
-
-2023-05-04 Martin Liska <mliska@suse.cz>
-
- * gcov.cc (GCOV_JSON_FORMAT_VERSION): New definition.
- (print_version): Use it.
- (generate_results): Likewise.
-
-2023-05-04 Richard Biener <rguenther@suse.de>
-
- * tree-cfg.h (last_stmt): Rename to ...
- (last_nondebug_stmt): ... this.
- * tree-cfg.cc (last_stmt): Rename to ...
- (last_nondebug_stmt): ... this.
- (assign_discriminators): Adjust.
- (group_case_labels_stmt): Likewise.
- (gimple_can_duplicate_bb_p): Likewise.
- (execute_fixup_cfg): Likewise.
- * auto-profile.cc (afdo_propagate_circuit): Likewise.
- * gimple-range.cc (gimple_ranger::range_on_exit): Likewise.
- * omp-expand.cc (workshare_safe_to_combine_p): Likewise.
- (determine_parallel_type): Likewise.
- (adjust_context_and_scope): Likewise.
- (expand_task_call): Likewise.
- (remove_exit_barrier): Likewise.
- (expand_omp_taskreg): Likewise.
- (expand_omp_for_init_counts): Likewise.
- (expand_omp_for_init_vars): Likewise.
- (expand_omp_for_static_chunk): Likewise.
- (expand_omp_simd): Likewise.
- (expand_oacc_for): Likewise.
- (expand_omp_for): Likewise.
- (expand_omp_sections): Likewise.
- (expand_omp_atomic_fetch_op): Likewise.
- (expand_omp_atomic_cas): Likewise.
- (expand_omp_atomic): Likewise.
- (expand_omp_target): Likewise.
- (expand_omp): Likewise.
- (omp_make_gimple_edges): Likewise.
- * trans-mem.cc (tm_region_init): Likewise.
- * tree-inline.cc (redirect_all_calls): Likewise.
- * tree-parloops.cc (gen_parallel_loop): Likewise.
- * tree-ssa-loop-ch.cc (do_while_loop_p): Likewise.
- * tree-ssa-loop-ivcanon.cc (canonicalize_loop_induction_variables):
- Likewise.
- * tree-ssa-loop-ivopts.cc (stmt_after_ip_normal_pos): Likewise.
- (may_eliminate_iv): Likewise.
- * tree-ssa-loop-manip.cc (standard_iv_increment_position): Likewise.
- * tree-ssa-loop-niter.cc (do_warn_aggressive_loop_optimizations):
- Likewise.
- (estimate_numbers_of_iterations): Likewise.
- * tree-ssa-loop-split.cc (compute_added_num_insns): Likewise.
- * tree-ssa-loop-unswitch.cc (get_predicates_for_bb): Likewise.
- (set_predicates_for_bb): Likewise.
- (init_loop_unswitch_info): Likewise.
- (hoist_guard): Likewise.
- * tree-ssa-phiopt.cc (match_simplify_replacement): Likewise.
- (minmax_replacement): Likewise.
- * tree-ssa-reassoc.cc (update_range_test): Likewise.
- (optimize_range_tests_to_bit_test): Likewise.
- (optimize_range_tests_var_bound): Likewise.
- (optimize_range_tests): Likewise.
- (no_side_effect_bb): Likewise.
- (suitable_cond_bb): Likewise.
- (maybe_optimize_range_tests): Likewise.
- (reassociate_bb): Likewise.
- * tree-vrp.cc (rvrp_folder::pre_fold_bb): Likewise.
-
-2023-05-04 Jakub Jelinek <jakub@redhat.com>
-
- PR debug/109676
- * config/i386/i386-features.cc (timode_scalar_chain::convert_insn):
- If src is REG, change its mode to V1TImode and call fix_debug_reg_uses
- for it only if it still has TImode. Don't decide whether to call
- fix_debug_reg_uses based on whether SRC is ever set or not.
-
-2023-05-04 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.cc (cris_split_constant): New function.
- * config/cris/cris.md (splitop): New iterator.
- (opsplit1): New define_peephole2.
- * config/cris/cris-protos.h (cris_split_constant): Declare.
- (cris_splittable_constant_p): New macro.
-
-2023-05-04 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.cc (TARGET_SPILL_CLASS): Define
- to ALL_REGS.
-
-2023-05-04 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.cc (cris_side_effect_mode_ok): Use
- lra_in_progress, not reload_in_progress.
- * config/cris/cris.md ("movdi", "*addi_reload"): Ditto.
- * config/cris/constraints.md ("Q"): Ditto.
-
-2023-05-03 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-dce.cc (simple_dce_from_worklist): Record
- stats on removed number of statements and phis.
-
-2023-05-03 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/109711
- * value-range.cc (irange::verify_range): Allow types of
- error_mark_node.
-
-2023-05-03 Alexander Monakov <amonakov@ispras.ru>
-
- PR sanitizer/90746
- * calls.cc (can_implement_as_sibling_call_p): Reject calls
- to __sanitizer_cov_trace_pc.
-
-2023-05-03 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/109661
- * config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Add
- a new ABI break parameter for GCC 14. Set it to the alignment
- of enums that have an underlying type. Take the true alignment
- of such enums from the TYPE_ALIGN of the underlying type's
- TYPE_MAIN_VARIANT.
- (aarch64_function_arg_boundary): Update accordingly.
- (aarch64_layout_arg, aarch64_gimplify_va_arg_expr): Likewise.
- Warn about ABI differences.
-
-2023-05-03 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/109661
- * config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Rename
- ABI break variables to abi_break_gcc_9 and abi_break_gcc_13.
- (aarch64_layout_arg, aarch64_function_arg_boundary): Likewise.
- (aarch64_gimplify_va_arg_expr): Likewise.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_M_N_NO_F)
- (FUNCTION_WITHOUT_N_NO_F, FUNCTION_WITH_M_N_NO_U_F): New.
- (vhaddq, vhsubq, vmulhq, vqaddq, vqsubq, vqdmulhq, vrhaddq)
- (vrmulhq): New.
- * config/arm/arm-mve-builtins-base.def (vhaddq, vhsubq, vmulhq)
- (vqaddq, vqsubq, vqdmulhq, vrhaddq, vrmulhq): New.
- * config/arm/arm-mve-builtins-base.h (vhaddq, vhsubq, vmulhq)
- (vqaddq, vqsubq, vqdmulhq, vrhaddq, vrmulhq): New.
- * config/arm/arm_mve.h (vhsubq): Remove.
- (vhaddq): Remove.
- (vhaddq_m): Remove.
- (vhsubq_m): Remove.
- (vhaddq_x): Remove.
- (vhsubq_x): Remove.
- (vhsubq_u8): Remove.
- (vhsubq_n_u8): Remove.
- (vhaddq_u8): Remove.
- (vhaddq_n_u8): Remove.
- (vhsubq_s8): Remove.
- (vhsubq_n_s8): Remove.
- (vhaddq_s8): Remove.
- (vhaddq_n_s8): Remove.
- (vhsubq_u16): Remove.
- (vhsubq_n_u16): Remove.
- (vhaddq_u16): Remove.
- (vhaddq_n_u16): Remove.
- (vhsubq_s16): Remove.
- (vhsubq_n_s16): Remove.
- (vhaddq_s16): Remove.
- (vhaddq_n_s16): Remove.
- (vhsubq_u32): Remove.
- (vhsubq_n_u32): Remove.
- (vhaddq_u32): Remove.
- (vhaddq_n_u32): Remove.
- (vhsubq_s32): Remove.
- (vhsubq_n_s32): Remove.
- (vhaddq_s32): Remove.
- (vhaddq_n_s32): Remove.
- (vhaddq_m_n_s8): Remove.
- (vhaddq_m_n_s32): Remove.
- (vhaddq_m_n_s16): Remove.
- (vhaddq_m_n_u8): Remove.
- (vhaddq_m_n_u32): Remove.
- (vhaddq_m_n_u16): Remove.
- (vhaddq_m_s8): Remove.
- (vhaddq_m_s32): Remove.
- (vhaddq_m_s16): Remove.
- (vhaddq_m_u8): Remove.
- (vhaddq_m_u32): Remove.
- (vhaddq_m_u16): Remove.
- (vhsubq_m_n_s8): Remove.
- (vhsubq_m_n_s32): Remove.
- (vhsubq_m_n_s16): Remove.
- (vhsubq_m_n_u8): Remove.
- (vhsubq_m_n_u32): Remove.
- (vhsubq_m_n_u16): Remove.
- (vhsubq_m_s8): Remove.
- (vhsubq_m_s32): Remove.
- (vhsubq_m_s16): Remove.
- (vhsubq_m_u8): Remove.
- (vhsubq_m_u32): Remove.
- (vhsubq_m_u16): Remove.
- (vhaddq_x_n_s8): Remove.
- (vhaddq_x_n_s16): Remove.
- (vhaddq_x_n_s32): Remove.
- (vhaddq_x_n_u8): Remove.
- (vhaddq_x_n_u16): Remove.
- (vhaddq_x_n_u32): Remove.
- (vhaddq_x_s8): Remove.
- (vhaddq_x_s16): Remove.
- (vhaddq_x_s32): Remove.
- (vhaddq_x_u8): Remove.
- (vhaddq_x_u16): Remove.
- (vhaddq_x_u32): Remove.
- (vhsubq_x_n_s8): Remove.
- (vhsubq_x_n_s16): Remove.
- (vhsubq_x_n_s32): Remove.
- (vhsubq_x_n_u8): Remove.
- (vhsubq_x_n_u16): Remove.
- (vhsubq_x_n_u32): Remove.
- (vhsubq_x_s8): Remove.
- (vhsubq_x_s16): Remove.
- (vhsubq_x_s32): Remove.
- (vhsubq_x_u8): Remove.
- (vhsubq_x_u16): Remove.
- (vhsubq_x_u32): Remove.
- (__arm_vhsubq_u8): Remove.
- (__arm_vhsubq_n_u8): Remove.
- (__arm_vhaddq_u8): Remove.
- (__arm_vhaddq_n_u8): Remove.
- (__arm_vhsubq_s8): Remove.
- (__arm_vhsubq_n_s8): Remove.
- (__arm_vhaddq_s8): Remove.
- (__arm_vhaddq_n_s8): Remove.
- (__arm_vhsubq_u16): Remove.
- (__arm_vhsubq_n_u16): Remove.
- (__arm_vhaddq_u16): Remove.
- (__arm_vhaddq_n_u16): Remove.
- (__arm_vhsubq_s16): Remove.
- (__arm_vhsubq_n_s16): Remove.
- (__arm_vhaddq_s16): Remove.
- (__arm_vhaddq_n_s16): Remove.
- (__arm_vhsubq_u32): Remove.
- (__arm_vhsubq_n_u32): Remove.
- (__arm_vhaddq_u32): Remove.
- (__arm_vhaddq_n_u32): Remove.
- (__arm_vhsubq_s32): Remove.
- (__arm_vhsubq_n_s32): Remove.
- (__arm_vhaddq_s32): Remove.
- (__arm_vhaddq_n_s32): Remove.
- (__arm_vhaddq_m_n_s8): Remove.
- (__arm_vhaddq_m_n_s32): Remove.
- (__arm_vhaddq_m_n_s16): Remove.
- (__arm_vhaddq_m_n_u8): Remove.
- (__arm_vhaddq_m_n_u32): Remove.
- (__arm_vhaddq_m_n_u16): Remove.
- (__arm_vhaddq_m_s8): Remove.
- (__arm_vhaddq_m_s32): Remove.
- (__arm_vhaddq_m_s16): Remove.
- (__arm_vhaddq_m_u8): Remove.
- (__arm_vhaddq_m_u32): Remove.
- (__arm_vhaddq_m_u16): Remove.
- (__arm_vhsubq_m_n_s8): Remove.
- (__arm_vhsubq_m_n_s32): Remove.
- (__arm_vhsubq_m_n_s16): Remove.
- (__arm_vhsubq_m_n_u8): Remove.
- (__arm_vhsubq_m_n_u32): Remove.
- (__arm_vhsubq_m_n_u16): Remove.
- (__arm_vhsubq_m_s8): Remove.
- (__arm_vhsubq_m_s32): Remove.
- (__arm_vhsubq_m_s16): Remove.
- (__arm_vhsubq_m_u8): Remove.
- (__arm_vhsubq_m_u32): Remove.
- (__arm_vhsubq_m_u16): Remove.
- (__arm_vhaddq_x_n_s8): Remove.
- (__arm_vhaddq_x_n_s16): Remove.
- (__arm_vhaddq_x_n_s32): Remove.
- (__arm_vhaddq_x_n_u8): Remove.
- (__arm_vhaddq_x_n_u16): Remove.
- (__arm_vhaddq_x_n_u32): Remove.
- (__arm_vhaddq_x_s8): Remove.
- (__arm_vhaddq_x_s16): Remove.
- (__arm_vhaddq_x_s32): Remove.
- (__arm_vhaddq_x_u8): Remove.
- (__arm_vhaddq_x_u16): Remove.
- (__arm_vhaddq_x_u32): Remove.
- (__arm_vhsubq_x_n_s8): Remove.
- (__arm_vhsubq_x_n_s16): Remove.
- (__arm_vhsubq_x_n_s32): Remove.
- (__arm_vhsubq_x_n_u8): Remove.
- (__arm_vhsubq_x_n_u16): Remove.
- (__arm_vhsubq_x_n_u32): Remove.
- (__arm_vhsubq_x_s8): Remove.
- (__arm_vhsubq_x_s16): Remove.
- (__arm_vhsubq_x_s32): Remove.
- (__arm_vhsubq_x_u8): Remove.
- (__arm_vhsubq_x_u16): Remove.
- (__arm_vhsubq_x_u32): Remove.
- (__arm_vhsubq): Remove.
- (__arm_vhaddq): Remove.
- (__arm_vhaddq_m): Remove.
- (__arm_vhsubq_m): Remove.
- (__arm_vhaddq_x): Remove.
- (__arm_vhsubq_x): Remove.
- (vmulhq): Remove.
- (vmulhq_m): Remove.
- (vmulhq_x): Remove.
- (vmulhq_u8): Remove.
- (vmulhq_s8): Remove.
- (vmulhq_u16): Remove.
- (vmulhq_s16): Remove.
- (vmulhq_u32): Remove.
- (vmulhq_s32): Remove.
- (vmulhq_m_s8): Remove.
- (vmulhq_m_s32): Remove.
- (vmulhq_m_s16): Remove.
- (vmulhq_m_u8): Remove.
- (vmulhq_m_u32): Remove.
- (vmulhq_m_u16): Remove.
- (vmulhq_x_s8): Remove.
- (vmulhq_x_s16): Remove.
- (vmulhq_x_s32): Remove.
- (vmulhq_x_u8): Remove.
- (vmulhq_x_u16): Remove.
- (vmulhq_x_u32): Remove.
- (__arm_vmulhq_u8): Remove.
- (__arm_vmulhq_s8): Remove.
- (__arm_vmulhq_u16): Remove.
- (__arm_vmulhq_s16): Remove.
- (__arm_vmulhq_u32): Remove.
- (__arm_vmulhq_s32): Remove.
- (__arm_vmulhq_m_s8): Remove.
- (__arm_vmulhq_m_s32): Remove.
- (__arm_vmulhq_m_s16): Remove.
- (__arm_vmulhq_m_u8): Remove.
- (__arm_vmulhq_m_u32): Remove.
- (__arm_vmulhq_m_u16): Remove.
- (__arm_vmulhq_x_s8): Remove.
- (__arm_vmulhq_x_s16): Remove.
- (__arm_vmulhq_x_s32): Remove.
- (__arm_vmulhq_x_u8): Remove.
- (__arm_vmulhq_x_u16): Remove.
- (__arm_vmulhq_x_u32): Remove.
- (__arm_vmulhq): Remove.
- (__arm_vmulhq_m): Remove.
- (__arm_vmulhq_x): Remove.
- (vqsubq): Remove.
- (vqaddq): Remove.
- (vqaddq_m): Remove.
- (vqsubq_m): Remove.
- (vqsubq_u8): Remove.
- (vqsubq_n_u8): Remove.
- (vqaddq_u8): Remove.
- (vqaddq_n_u8): Remove.
- (vqsubq_s8): Remove.
- (vqsubq_n_s8): Remove.
- (vqaddq_s8): Remove.
- (vqaddq_n_s8): Remove.
- (vqsubq_u16): Remove.
- (vqsubq_n_u16): Remove.
- (vqaddq_u16): Remove.
- (vqaddq_n_u16): Remove.
- (vqsubq_s16): Remove.
- (vqsubq_n_s16): Remove.
- (vqaddq_s16): Remove.
- (vqaddq_n_s16): Remove.
- (vqsubq_u32): Remove.
- (vqsubq_n_u32): Remove.
- (vqaddq_u32): Remove.
- (vqaddq_n_u32): Remove.
- (vqsubq_s32): Remove.
- (vqsubq_n_s32): Remove.
- (vqaddq_s32): Remove.
- (vqaddq_n_s32): Remove.
- (vqaddq_m_n_s8): Remove.
- (vqaddq_m_n_s32): Remove.
- (vqaddq_m_n_s16): Remove.
- (vqaddq_m_n_u8): Remove.
- (vqaddq_m_n_u32): Remove.
- (vqaddq_m_n_u16): Remove.
- (vqaddq_m_s8): Remove.
- (vqaddq_m_s32): Remove.
- (vqaddq_m_s16): Remove.
- (vqaddq_m_u8): Remove.
- (vqaddq_m_u32): Remove.
- (vqaddq_m_u16): Remove.
- (vqsubq_m_n_s8): Remove.
- (vqsubq_m_n_s32): Remove.
- (vqsubq_m_n_s16): Remove.
- (vqsubq_m_n_u8): Remove.
- (vqsubq_m_n_u32): Remove.
- (vqsubq_m_n_u16): Remove.
- (vqsubq_m_s8): Remove.
- (vqsubq_m_s32): Remove.
- (vqsubq_m_s16): Remove.
- (vqsubq_m_u8): Remove.
- (vqsubq_m_u32): Remove.
- (vqsubq_m_u16): Remove.
- (__arm_vqsubq_u8): Remove.
- (__arm_vqsubq_n_u8): Remove.
- (__arm_vqaddq_u8): Remove.
- (__arm_vqaddq_n_u8): Remove.
- (__arm_vqsubq_s8): Remove.
- (__arm_vqsubq_n_s8): Remove.
- (__arm_vqaddq_s8): Remove.
- (__arm_vqaddq_n_s8): Remove.
- (__arm_vqsubq_u16): Remove.
- (__arm_vqsubq_n_u16): Remove.
- (__arm_vqaddq_u16): Remove.
- (__arm_vqaddq_n_u16): Remove.
- (__arm_vqsubq_s16): Remove.
- (__arm_vqsubq_n_s16): Remove.
- (__arm_vqaddq_s16): Remove.
- (__arm_vqaddq_n_s16): Remove.
- (__arm_vqsubq_u32): Remove.
- (__arm_vqsubq_n_u32): Remove.
- (__arm_vqaddq_u32): Remove.
- (__arm_vqaddq_n_u32): Remove.
- (__arm_vqsubq_s32): Remove.
- (__arm_vqsubq_n_s32): Remove.
- (__arm_vqaddq_s32): Remove.
- (__arm_vqaddq_n_s32): Remove.
- (__arm_vqaddq_m_n_s8): Remove.
- (__arm_vqaddq_m_n_s32): Remove.
- (__arm_vqaddq_m_n_s16): Remove.
- (__arm_vqaddq_m_n_u8): Remove.
- (__arm_vqaddq_m_n_u32): Remove.
- (__arm_vqaddq_m_n_u16): Remove.
- (__arm_vqaddq_m_s8): Remove.
- (__arm_vqaddq_m_s32): Remove.
- (__arm_vqaddq_m_s16): Remove.
- (__arm_vqaddq_m_u8): Remove.
- (__arm_vqaddq_m_u32): Remove.
- (__arm_vqaddq_m_u16): Remove.
- (__arm_vqsubq_m_n_s8): Remove.
- (__arm_vqsubq_m_n_s32): Remove.
- (__arm_vqsubq_m_n_s16): Remove.
- (__arm_vqsubq_m_n_u8): Remove.
- (__arm_vqsubq_m_n_u32): Remove.
- (__arm_vqsubq_m_n_u16): Remove.
- (__arm_vqsubq_m_s8): Remove.
- (__arm_vqsubq_m_s32): Remove.
- (__arm_vqsubq_m_s16): Remove.
- (__arm_vqsubq_m_u8): Remove.
- (__arm_vqsubq_m_u32): Remove.
- (__arm_vqsubq_m_u16): Remove.
- (__arm_vqsubq): Remove.
- (__arm_vqaddq): Remove.
- (__arm_vqaddq_m): Remove.
- (__arm_vqsubq_m): Remove.
- (vqdmulhq): Remove.
- (vqdmulhq_m): Remove.
- (vqdmulhq_s8): Remove.
- (vqdmulhq_n_s8): Remove.
- (vqdmulhq_s16): Remove.
- (vqdmulhq_n_s16): Remove.
- (vqdmulhq_s32): Remove.
- (vqdmulhq_n_s32): Remove.
- (vqdmulhq_m_n_s8): Remove.
- (vqdmulhq_m_n_s32): Remove.
- (vqdmulhq_m_n_s16): Remove.
- (vqdmulhq_m_s8): Remove.
- (vqdmulhq_m_s32): Remove.
- (vqdmulhq_m_s16): Remove.
- (__arm_vqdmulhq_s8): Remove.
- (__arm_vqdmulhq_n_s8): Remove.
- (__arm_vqdmulhq_s16): Remove.
- (__arm_vqdmulhq_n_s16): Remove.
- (__arm_vqdmulhq_s32): Remove.
- (__arm_vqdmulhq_n_s32): Remove.
- (__arm_vqdmulhq_m_n_s8): Remove.
- (__arm_vqdmulhq_m_n_s32): Remove.
- (__arm_vqdmulhq_m_n_s16): Remove.
- (__arm_vqdmulhq_m_s8): Remove.
- (__arm_vqdmulhq_m_s32): Remove.
- (__arm_vqdmulhq_m_s16): Remove.
- (__arm_vqdmulhq): Remove.
- (__arm_vqdmulhq_m): Remove.
- (vrhaddq): Remove.
- (vrhaddq_m): Remove.
- (vrhaddq_x): Remove.
- (vrhaddq_u8): Remove.
- (vrhaddq_s8): Remove.
- (vrhaddq_u16): Remove.
- (vrhaddq_s16): Remove.
- (vrhaddq_u32): Remove.
- (vrhaddq_s32): Remove.
- (vrhaddq_m_s8): Remove.
- (vrhaddq_m_s32): Remove.
- (vrhaddq_m_s16): Remove.
- (vrhaddq_m_u8): Remove.
- (vrhaddq_m_u32): Remove.
- (vrhaddq_m_u16): Remove.
- (vrhaddq_x_s8): Remove.
- (vrhaddq_x_s16): Remove.
- (vrhaddq_x_s32): Remove.
- (vrhaddq_x_u8): Remove.
- (vrhaddq_x_u16): Remove.
- (vrhaddq_x_u32): Remove.
- (__arm_vrhaddq_u8): Remove.
- (__arm_vrhaddq_s8): Remove.
- (__arm_vrhaddq_u16): Remove.
- (__arm_vrhaddq_s16): Remove.
- (__arm_vrhaddq_u32): Remove.
- (__arm_vrhaddq_s32): Remove.
- (__arm_vrhaddq_m_s8): Remove.
- (__arm_vrhaddq_m_s32): Remove.
- (__arm_vrhaddq_m_s16): Remove.
- (__arm_vrhaddq_m_u8): Remove.
- (__arm_vrhaddq_m_u32): Remove.
- (__arm_vrhaddq_m_u16): Remove.
- (__arm_vrhaddq_x_s8): Remove.
- (__arm_vrhaddq_x_s16): Remove.
- (__arm_vrhaddq_x_s32): Remove.
- (__arm_vrhaddq_x_u8): Remove.
- (__arm_vrhaddq_x_u16): Remove.
- (__arm_vrhaddq_x_u32): Remove.
- (__arm_vrhaddq): Remove.
- (__arm_vrhaddq_m): Remove.
- (__arm_vrhaddq_x): Remove.
- (vrmulhq): Remove.
- (vrmulhq_m): Remove.
- (vrmulhq_x): Remove.
- (vrmulhq_u8): Remove.
- (vrmulhq_s8): Remove.
- (vrmulhq_u16): Remove.
- (vrmulhq_s16): Remove.
- (vrmulhq_u32): Remove.
- (vrmulhq_s32): Remove.
- (vrmulhq_m_s8): Remove.
- (vrmulhq_m_s32): Remove.
- (vrmulhq_m_s16): Remove.
- (vrmulhq_m_u8): Remove.
- (vrmulhq_m_u32): Remove.
- (vrmulhq_m_u16): Remove.
- (vrmulhq_x_s8): Remove.
- (vrmulhq_x_s16): Remove.
- (vrmulhq_x_s32): Remove.
- (vrmulhq_x_u8): Remove.
- (vrmulhq_x_u16): Remove.
- (vrmulhq_x_u32): Remove.
- (__arm_vrmulhq_u8): Remove.
- (__arm_vrmulhq_s8): Remove.
- (__arm_vrmulhq_u16): Remove.
- (__arm_vrmulhq_s16): Remove.
- (__arm_vrmulhq_u32): Remove.
- (__arm_vrmulhq_s32): Remove.
- (__arm_vrmulhq_m_s8): Remove.
- (__arm_vrmulhq_m_s32): Remove.
- (__arm_vrmulhq_m_s16): Remove.
- (__arm_vrmulhq_m_u8): Remove.
- (__arm_vrmulhq_m_u32): Remove.
- (__arm_vrmulhq_m_u16): Remove.
- (__arm_vrmulhq_x_s8): Remove.
- (__arm_vrmulhq_x_s16): Remove.
- (__arm_vrmulhq_x_s32): Remove.
- (__arm_vrmulhq_x_u8): Remove.
- (__arm_vrmulhq_x_u16): Remove.
- (__arm_vrmulhq_x_u32): Remove.
- (__arm_vrmulhq): Remove.
- (__arm_vrmulhq_m): Remove.
- (__arm_vrmulhq_x): Remove.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_INT_SU_BINARY): New.
- (mve_insn): Add vabdq, vhaddq, vhsubq, vmulhq, vqaddq, vqdmulhq,
- vqrdmulhq, vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq.
- (supf): Add VQDMULHQ_S, VQRDMULHQ_S.
- * config/arm/mve.md (mve_vabdq_<supf><mode>)
- (@mve_vhaddq_<supf><mode>, mve_vhsubq_<supf><mode>)
- (mve_vmulhq_<supf><mode>, mve_vqaddq_<supf><mode>)
- (mve_vqdmulhq_s<mode>, mve_vqrdmulhq_s<mode>)
- (mve_vqrshlq_<supf><mode>, mve_vqshlq_<supf><mode>)
- (mve_vqsubq_<supf><mode>, @mve_vrhaddq_<supf><mode>)
- (mve_vrmulhq_<supf><mode>, mve_vrshlq_<supf><mode>): Merge into
- ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
- * config/arm/vec-common.md (avg<mode>3_floor, uavg<mode>3_floor)
- (avg<mode>3_ceil, uavg<mode>3_ceil): Use gen_mve_q instead of
- gen_mve_vhaddq / gen_mve_vrhaddq.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_INT_SU_M_N_BINARY): New.
- (mve_insn): Add vhaddq, vhsubq, vmlaq, vmlasq, vqaddq, vqdmlahq,
- vqdmlashq, vqdmulhq, vqrdmlahq, vqrdmlashq, vqrdmulhq, vqsubq.
- (supf): Add VQDMLAHQ_M_N_S, VQDMLASHQ_M_N_S, VQRDMLAHQ_M_N_S,
- VQRDMLASHQ_M_N_S, VQDMULHQ_M_N_S, VQRDMULHQ_M_N_S.
- * config/arm/mve.md (mve_vhaddq_m_n_<supf><mode>)
- (mve_vhsubq_m_n_<supf><mode>, mve_vmlaq_m_n_<supf><mode>)
- (mve_vmlasq_m_n_<supf><mode>, mve_vqaddq_m_n_<supf><mode>)
- (mve_vqdmlahq_m_n_s<mode>, mve_vqdmlashq_m_n_s<mode>)
- (mve_vqrdmlahq_m_n_s<mode>, mve_vqrdmlashq_m_n_s<mode>)
- (mve_vqsubq_m_n_<supf><mode>, mve_vqdmulhq_m_n_s<mode>)
- (mve_vqrdmulhq_m_n_s<mode>): Merge into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_INT_SU_N_BINARY): New.
- (mve_insn): Add vhaddq, vhsubq, vqaddq, vqdmulhq, vqrdmulhq,
- vqsubq.
- (supf): Add VQDMULHQ_N_S, VQRDMULHQ_N_S.
- * config/arm/mve.md (mve_vhaddq_n_<supf><mode>)
- (mve_vhsubq_n_<supf><mode>, mve_vqaddq_n_<supf><mode>)
- (mve_vqdmulhq_n_s<mode>, mve_vqrdmulhq_n_s<mode>)
- (mve_vqsubq_n_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_INT_SU_M_BINARY): New.
- (mve_insn): Add vabdq, vhaddq, vhsubq, vmaxq, vminq, vmulhq,
- vqaddq, vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq, vqdmulhq,
- vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq, vqrdmulhq,
- vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq, vshlq.
- (supf): Add VQDMLADHQ_M_S, VQDMLADHXQ_M_S, VQDMLSDHQ_M_S,
- VQDMLSDHXQ_M_S, VQDMULHQ_M_S, VQRDMLADHQ_M_S, VQRDMLADHXQ_M_S,
- VQRDMLSDHQ_M_S, VQRDMLSDHXQ_M_S, VQRDMULHQ_M_S.
- * config/arm/mve.md (@mve_<mve_insn>q_m_<supf><mode>): New.
- (mve_vshlq_m_<supf><mode>): Merged into
- @mve_<mve_insn>q_m_<supf><mode>.
- (mve_vabdq_m_<supf><mode>): Likewise.
- (mve_vhaddq_m_<supf><mode>): Likewise.
- (mve_vhsubq_m_<supf><mode>): Likewise.
- (mve_vmaxq_m_<supf><mode>): Likewise.
- (mve_vminq_m_<supf><mode>): Likewise.
- (mve_vmulhq_m_<supf><mode>): Likewise.
- (mve_vqaddq_m_<supf><mode>): Likewise.
- (mve_vqrshlq_m_<supf><mode>): Likewise.
- (mve_vqshlq_m_<supf><mode>): Likewise.
- (mve_vqsubq_m_<supf><mode>): Likewise.
- (mve_vrhaddq_m_<supf><mode>): Likewise.
- (mve_vrmulhq_m_<supf><mode>): Likewise.
- (mve_vrshlq_m_<supf><mode>): Likewise.
- (mve_vqdmladhq_m_s<mode>): Likewise.
- (mve_vqdmladhxq_m_s<mode>): Likewise.
- (mve_vqdmlsdhq_m_s<mode>): Likewise.
- (mve_vqdmlsdhxq_m_s<mode>): Likewise.
- (mve_vqdmulhq_m_s<mode>): Likewise.
- (mve_vqrdmladhq_m_s<mode>): Likewise.
- (mve_vqrdmladhxq_m_s<mode>): Likewise.
- (mve_vqrdmlsdhq_m_s<mode>): Likewise.
- (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
- (mve_vqrdmulhq_m_s<mode>): Likewise.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_M_N): New. (vcreateq): New.
- * config/arm/arm-mve-builtins-base.def (vcreateq): New.
- * config/arm/arm-mve-builtins-base.h (vcreateq): New.
- * config/arm/arm_mve.h (vcreateq_f16): Remove.
- (vcreateq_f32): Remove.
- (vcreateq_u8): Remove.
- (vcreateq_u16): Remove.
- (vcreateq_u32): Remove.
- (vcreateq_u64): Remove.
- (vcreateq_s8): Remove.
- (vcreateq_s16): Remove.
- (vcreateq_s32): Remove.
- (vcreateq_s64): Remove.
- (__arm_vcreateq_u8): Remove.
- (__arm_vcreateq_u16): Remove.
- (__arm_vcreateq_u32): Remove.
- (__arm_vcreateq_u64): Remove.
- (__arm_vcreateq_s8): Remove.
- (__arm_vcreateq_s16): Remove.
- (__arm_vcreateq_s32): Remove.
- (__arm_vcreateq_s64): Remove.
- (__arm_vcreateq_f16): Remove.
- (__arm_vcreateq_f32): Remove.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_FP_CREATE_ONLY): New.
- (mve_insn): Add VCREATEQ_S, VCREATEQ_U, VCREATEQ_F.
- * config/arm/mve.md (mve_vcreateq_f<mode>): Rename into ...
- (@mve_<mve_insn>q_f<mode>): ... this.
- (mve_vcreateq_<supf><mode>): Rename into ...
- (@mve_<mve_insn>q_<supf><mode>): ... this.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (create): New.
- * config/arm/arm-mve-builtins-shapes.h: (create): New.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-functions.h (class
- unspec_mve_function_exact_insn): New.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_N_NO_N_F): New.
- (vorrq): New.
- * config/arm/arm-mve-builtins-base.def (vorrq): New.
- * config/arm/arm-mve-builtins-base.h (vorrq): New.
- * config/arm/arm-mve-builtins.cc
- (function_instance::has_inactive_argument): Handle vorrq.
- * config/arm/arm_mve.h (vorrq): Remove.
- (vorrq_m_n): Remove.
- (vorrq_m): Remove.
- (vorrq_x): Remove.
- (vorrq_u8): Remove.
- (vorrq_s8): Remove.
- (vorrq_u16): Remove.
- (vorrq_s16): Remove.
- (vorrq_u32): Remove.
- (vorrq_s32): Remove.
- (vorrq_n_u16): Remove.
- (vorrq_f16): Remove.
- (vorrq_n_s16): Remove.
- (vorrq_n_u32): Remove.
- (vorrq_f32): Remove.
- (vorrq_n_s32): Remove.
- (vorrq_m_n_s16): Remove.
- (vorrq_m_n_u16): Remove.
- (vorrq_m_n_s32): Remove.
- (vorrq_m_n_u32): Remove.
- (vorrq_m_s8): Remove.
- (vorrq_m_s32): Remove.
- (vorrq_m_s16): Remove.
- (vorrq_m_u8): Remove.
- (vorrq_m_u32): Remove.
- (vorrq_m_u16): Remove.
- (vorrq_m_f32): Remove.
- (vorrq_m_f16): Remove.
- (vorrq_x_s8): Remove.
- (vorrq_x_s16): Remove.
- (vorrq_x_s32): Remove.
- (vorrq_x_u8): Remove.
- (vorrq_x_u16): Remove.
- (vorrq_x_u32): Remove.
- (vorrq_x_f16): Remove.
- (vorrq_x_f32): Remove.
- (__arm_vorrq_u8): Remove.
- (__arm_vorrq_s8): Remove.
- (__arm_vorrq_u16): Remove.
- (__arm_vorrq_s16): Remove.
- (__arm_vorrq_u32): Remove.
- (__arm_vorrq_s32): Remove.
- (__arm_vorrq_n_u16): Remove.
- (__arm_vorrq_n_s16): Remove.
- (__arm_vorrq_n_u32): Remove.
- (__arm_vorrq_n_s32): Remove.
- (__arm_vorrq_m_n_s16): Remove.
- (__arm_vorrq_m_n_u16): Remove.
- (__arm_vorrq_m_n_s32): Remove.
- (__arm_vorrq_m_n_u32): Remove.
- (__arm_vorrq_m_s8): Remove.
- (__arm_vorrq_m_s32): Remove.
- (__arm_vorrq_m_s16): Remove.
- (__arm_vorrq_m_u8): Remove.
- (__arm_vorrq_m_u32): Remove.
- (__arm_vorrq_m_u16): Remove.
- (__arm_vorrq_x_s8): Remove.
- (__arm_vorrq_x_s16): Remove.
- (__arm_vorrq_x_s32): Remove.
- (__arm_vorrq_x_u8): Remove.
- (__arm_vorrq_x_u16): Remove.
- (__arm_vorrq_x_u32): Remove.
- (__arm_vorrq_f16): Remove.
- (__arm_vorrq_f32): Remove.
- (__arm_vorrq_m_f32): Remove.
- (__arm_vorrq_m_f16): Remove.
- (__arm_vorrq_x_f16): Remove.
- (__arm_vorrq_x_f32): Remove.
- (__arm_vorrq): Remove.
- (__arm_vorrq_m_n): Remove.
- (__arm_vorrq_m): Remove.
- (__arm_vorrq_x): Remove.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_orrq): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_orrq): New.
- * config/arm/arm-mve-builtins.cc (preds_m_or_none): Remove static.
- * config/arm/arm-mve-builtins.h (preds_m_or_none): Declare.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M): New.
- (vandq,veorq): New.
- * config/arm/arm-mve-builtins-base.def (vandq, veorq): New.
- * config/arm/arm-mve-builtins-base.h (vandq, veorq): New.
- * config/arm/arm_mve.h (vandq): Remove.
- (vandq_m): Remove.
- (vandq_x): Remove.
- (vandq_u8): Remove.
- (vandq_s8): Remove.
- (vandq_u16): Remove.
- (vandq_s16): Remove.
- (vandq_u32): Remove.
- (vandq_s32): Remove.
- (vandq_f16): Remove.
- (vandq_f32): Remove.
- (vandq_m_s8): Remove.
- (vandq_m_s32): Remove.
- (vandq_m_s16): Remove.
- (vandq_m_u8): Remove.
- (vandq_m_u32): Remove.
- (vandq_m_u16): Remove.
- (vandq_m_f32): Remove.
- (vandq_m_f16): Remove.
- (vandq_x_s8): Remove.
- (vandq_x_s16): Remove.
- (vandq_x_s32): Remove.
- (vandq_x_u8): Remove.
- (vandq_x_u16): Remove.
- (vandq_x_u32): Remove.
- (vandq_x_f16): Remove.
- (vandq_x_f32): Remove.
- (__arm_vandq_u8): Remove.
- (__arm_vandq_s8): Remove.
- (__arm_vandq_u16): Remove.
- (__arm_vandq_s16): Remove.
- (__arm_vandq_u32): Remove.
- (__arm_vandq_s32): Remove.
- (__arm_vandq_m_s8): Remove.
- (__arm_vandq_m_s32): Remove.
- (__arm_vandq_m_s16): Remove.
- (__arm_vandq_m_u8): Remove.
- (__arm_vandq_m_u32): Remove.
- (__arm_vandq_m_u16): Remove.
- (__arm_vandq_x_s8): Remove.
- (__arm_vandq_x_s16): Remove.
- (__arm_vandq_x_s32): Remove.
- (__arm_vandq_x_u8): Remove.
- (__arm_vandq_x_u16): Remove.
- (__arm_vandq_x_u32): Remove.
- (__arm_vandq_f16): Remove.
- (__arm_vandq_f32): Remove.
- (__arm_vandq_m_f32): Remove.
- (__arm_vandq_m_f16): Remove.
- (__arm_vandq_x_f16): Remove.
- (__arm_vandq_x_f32): Remove.
- (__arm_vandq): Remove.
- (__arm_vandq_m): Remove.
- (__arm_vandq_x): Remove.
- (veorq_m): Remove.
- (veorq_x): Remove.
- (veorq_u8): Remove.
- (veorq_s8): Remove.
- (veorq_u16): Remove.
- (veorq_s16): Remove.
- (veorq_u32): Remove.
- (veorq_s32): Remove.
- (veorq_f16): Remove.
- (veorq_f32): Remove.
- (veorq_m_s8): Remove.
- (veorq_m_s32): Remove.
- (veorq_m_s16): Remove.
- (veorq_m_u8): Remove.
- (veorq_m_u32): Remove.
- (veorq_m_u16): Remove.
- (veorq_m_f32): Remove.
- (veorq_m_f16): Remove.
- (veorq_x_s8): Remove.
- (veorq_x_s16): Remove.
- (veorq_x_s32): Remove.
- (veorq_x_u8): Remove.
- (veorq_x_u16): Remove.
- (veorq_x_u32): Remove.
- (veorq_x_f16): Remove.
- (veorq_x_f32): Remove.
- (__arm_veorq_u8): Remove.
- (__arm_veorq_s8): Remove.
- (__arm_veorq_u16): Remove.
- (__arm_veorq_s16): Remove.
- (__arm_veorq_u32): Remove.
- (__arm_veorq_s32): Remove.
- (__arm_veorq_m_s8): Remove.
- (__arm_veorq_m_s32): Remove.
- (__arm_veorq_m_s16): Remove.
- (__arm_veorq_m_u8): Remove.
- (__arm_veorq_m_u32): Remove.
- (__arm_veorq_m_u16): Remove.
- (__arm_veorq_x_s8): Remove.
- (__arm_veorq_x_s16): Remove.
- (__arm_veorq_x_s32): Remove.
- (__arm_veorq_x_u8): Remove.
- (__arm_veorq_x_u16): Remove.
- (__arm_veorq_x_u32): Remove.
- (__arm_veorq_f16): Remove.
- (__arm_veorq_f32): Remove.
- (__arm_veorq_m_f32): Remove.
- (__arm_veorq_m_f16): Remove.
- (__arm_veorq_x_f16): Remove.
- (__arm_veorq_x_f32): Remove.
- (__arm_veorq): Remove.
- (__arm_veorq_m): Remove.
- (__arm_veorq_x): Remove.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_INT_M_BINARY_LOGIC)
- (MVE_FP_M_BINARY_LOGIC): New.
- (MVE_INT_M_N_BINARY_LOGIC): New.
- (MVE_INT_N_BINARY_LOGIC): New.
- (mve_insn): Add vand, veor, vorr, vbic.
- * config/arm/mve.md (mve_vandq_m_<supf><mode>)
- (mve_veorq_m_<supf><mode>, mve_vorrq_m_<supf><mode>)
- (mve_vbicq_m_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_m_<supf><mode>): ... this.
- (mve_vandq_m_f<mode>, mve_veorq_m_f<mode>, mve_vorrq_m_f<mode>)
- (mve_vbicq_m_f<mode>): Merge into ...
- (@mve_<mve_insn>q_m_f<mode>): ... this.
- (mve_vorrq_n_<supf><mode>)
- (mve_vbicq_n_<supf><mode>): Merge into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vorrq_m_n_<supf><mode>, mve_vbicq_m_n_<supf><mode>): Merge
- into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary): New.
- * config/arm/arm-mve-builtins-shapes.h (binary): New.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_N):
- New.
- (vaddq, vmulq, vsubq): New.
- * config/arm/arm-mve-builtins-base.def (vaddq, vmulq, vsubq): New.
- * config/arm/arm-mve-builtins-base.h (vaddq, vmulq, vsubq): New.
- * config/arm/arm_mve.h (vaddq): Remove.
- (vaddq_m): Remove.
- (vaddq_x): Remove.
- (vaddq_n_u8): Remove.
- (vaddq_n_s8): Remove.
- (vaddq_n_u16): Remove.
- (vaddq_n_s16): Remove.
- (vaddq_n_u32): Remove.
- (vaddq_n_s32): Remove.
- (vaddq_n_f16): Remove.
- (vaddq_n_f32): Remove.
- (vaddq_m_n_s8): Remove.
- (vaddq_m_n_s32): Remove.
- (vaddq_m_n_s16): Remove.
- (vaddq_m_n_u8): Remove.
- (vaddq_m_n_u32): Remove.
- (vaddq_m_n_u16): Remove.
- (vaddq_m_s8): Remove.
- (vaddq_m_s32): Remove.
- (vaddq_m_s16): Remove.
- (vaddq_m_u8): Remove.
- (vaddq_m_u32): Remove.
- (vaddq_m_u16): Remove.
- (vaddq_m_f32): Remove.
- (vaddq_m_f16): Remove.
- (vaddq_m_n_f32): Remove.
- (vaddq_m_n_f16): Remove.
- (vaddq_s8): Remove.
- (vaddq_s16): Remove.
- (vaddq_s32): Remove.
- (vaddq_u8): Remove.
- (vaddq_u16): Remove.
- (vaddq_u32): Remove.
- (vaddq_f16): Remove.
- (vaddq_f32): Remove.
- (vaddq_x_s8): Remove.
- (vaddq_x_s16): Remove.
- (vaddq_x_s32): Remove.
- (vaddq_x_n_s8): Remove.
- (vaddq_x_n_s16): Remove.
- (vaddq_x_n_s32): Remove.
- (vaddq_x_u8): Remove.
- (vaddq_x_u16): Remove.
- (vaddq_x_u32): Remove.
- (vaddq_x_n_u8): Remove.
- (vaddq_x_n_u16): Remove.
- (vaddq_x_n_u32): Remove.
- (vaddq_x_f16): Remove.
- (vaddq_x_f32): Remove.
- (vaddq_x_n_f16): Remove.
- (vaddq_x_n_f32): Remove.
- (__arm_vaddq_n_u8): Remove.
- (__arm_vaddq_n_s8): Remove.
- (__arm_vaddq_n_u16): Remove.
- (__arm_vaddq_n_s16): Remove.
- (__arm_vaddq_n_u32): Remove.
- (__arm_vaddq_n_s32): Remove.
- (__arm_vaddq_m_n_s8): Remove.
- (__arm_vaddq_m_n_s32): Remove.
- (__arm_vaddq_m_n_s16): Remove.
- (__arm_vaddq_m_n_u8): Remove.
- (__arm_vaddq_m_n_u32): Remove.
- (__arm_vaddq_m_n_u16): Remove.
- (__arm_vaddq_m_s8): Remove.
- (__arm_vaddq_m_s32): Remove.
- (__arm_vaddq_m_s16): Remove.
- (__arm_vaddq_m_u8): Remove.
- (__arm_vaddq_m_u32): Remove.
- (__arm_vaddq_m_u16): Remove.
- (__arm_vaddq_s8): Remove.
- (__arm_vaddq_s16): Remove.
- (__arm_vaddq_s32): Remove.
- (__arm_vaddq_u8): Remove.
- (__arm_vaddq_u16): Remove.
- (__arm_vaddq_u32): Remove.
- (__arm_vaddq_x_s8): Remove.
- (__arm_vaddq_x_s16): Remove.
- (__arm_vaddq_x_s32): Remove.
- (__arm_vaddq_x_n_s8): Remove.
- (__arm_vaddq_x_n_s16): Remove.
- (__arm_vaddq_x_n_s32): Remove.
- (__arm_vaddq_x_u8): Remove.
- (__arm_vaddq_x_u16): Remove.
- (__arm_vaddq_x_u32): Remove.
- (__arm_vaddq_x_n_u8): Remove.
- (__arm_vaddq_x_n_u16): Remove.
- (__arm_vaddq_x_n_u32): Remove.
- (__arm_vaddq_n_f16): Remove.
- (__arm_vaddq_n_f32): Remove.
- (__arm_vaddq_m_f32): Remove.
- (__arm_vaddq_m_f16): Remove.
- (__arm_vaddq_m_n_f32): Remove.
- (__arm_vaddq_m_n_f16): Remove.
- (__arm_vaddq_f16): Remove.
- (__arm_vaddq_f32): Remove.
- (__arm_vaddq_x_f16): Remove.
- (__arm_vaddq_x_f32): Remove.
- (__arm_vaddq_x_n_f16): Remove.
- (__arm_vaddq_x_n_f32): Remove.
- (__arm_vaddq): Remove.
- (__arm_vaddq_m): Remove.
- (__arm_vaddq_x): Remove.
- (vmulq): Remove.
- (vmulq_m): Remove.
- (vmulq_x): Remove.
- (vmulq_u8): Remove.
- (vmulq_n_u8): Remove.
- (vmulq_s8): Remove.
- (vmulq_n_s8): Remove.
- (vmulq_u16): Remove.
- (vmulq_n_u16): Remove.
- (vmulq_s16): Remove.
- (vmulq_n_s16): Remove.
- (vmulq_u32): Remove.
- (vmulq_n_u32): Remove.
- (vmulq_s32): Remove.
- (vmulq_n_s32): Remove.
- (vmulq_n_f16): Remove.
- (vmulq_f16): Remove.
- (vmulq_n_f32): Remove.
- (vmulq_f32): Remove.
- (vmulq_m_n_s8): Remove.
- (vmulq_m_n_s32): Remove.
- (vmulq_m_n_s16): Remove.
- (vmulq_m_n_u8): Remove.
- (vmulq_m_n_u32): Remove.
- (vmulq_m_n_u16): Remove.
- (vmulq_m_s8): Remove.
- (vmulq_m_s32): Remove.
- (vmulq_m_s16): Remove.
- (vmulq_m_u8): Remove.
- (vmulq_m_u32): Remove.
- (vmulq_m_u16): Remove.
- (vmulq_m_f32): Remove.
- (vmulq_m_f16): Remove.
- (vmulq_m_n_f32): Remove.
- (vmulq_m_n_f16): Remove.
- (vmulq_x_s8): Remove.
- (vmulq_x_s16): Remove.
- (vmulq_x_s32): Remove.
- (vmulq_x_n_s8): Remove.
- (vmulq_x_n_s16): Remove.
- (vmulq_x_n_s32): Remove.
- (vmulq_x_u8): Remove.
- (vmulq_x_u16): Remove.
- (vmulq_x_u32): Remove.
- (vmulq_x_n_u8): Remove.
- (vmulq_x_n_u16): Remove.
- (vmulq_x_n_u32): Remove.
- (vmulq_x_f16): Remove.
- (vmulq_x_f32): Remove.
- (vmulq_x_n_f16): Remove.
- (vmulq_x_n_f32): Remove.
- (__arm_vmulq_u8): Remove.
- (__arm_vmulq_n_u8): Remove.
- (__arm_vmulq_s8): Remove.
- (__arm_vmulq_n_s8): Remove.
- (__arm_vmulq_u16): Remove.
- (__arm_vmulq_n_u16): Remove.
- (__arm_vmulq_s16): Remove.
- (__arm_vmulq_n_s16): Remove.
- (__arm_vmulq_u32): Remove.
- (__arm_vmulq_n_u32): Remove.
- (__arm_vmulq_s32): Remove.
- (__arm_vmulq_n_s32): Remove.
- (__arm_vmulq_m_n_s8): Remove.
- (__arm_vmulq_m_n_s32): Remove.
- (__arm_vmulq_m_n_s16): Remove.
- (__arm_vmulq_m_n_u8): Remove.
- (__arm_vmulq_m_n_u32): Remove.
- (__arm_vmulq_m_n_u16): Remove.
- (__arm_vmulq_m_s8): Remove.
- (__arm_vmulq_m_s32): Remove.
- (__arm_vmulq_m_s16): Remove.
- (__arm_vmulq_m_u8): Remove.
- (__arm_vmulq_m_u32): Remove.
- (__arm_vmulq_m_u16): Remove.
- (__arm_vmulq_x_s8): Remove.
- (__arm_vmulq_x_s16): Remove.
- (__arm_vmulq_x_s32): Remove.
- (__arm_vmulq_x_n_s8): Remove.
- (__arm_vmulq_x_n_s16): Remove.
- (__arm_vmulq_x_n_s32): Remove.
- (__arm_vmulq_x_u8): Remove.
- (__arm_vmulq_x_u16): Remove.
- (__arm_vmulq_x_u32): Remove.
- (__arm_vmulq_x_n_u8): Remove.
- (__arm_vmulq_x_n_u16): Remove.
- (__arm_vmulq_x_n_u32): Remove.
- (__arm_vmulq_n_f16): Remove.
- (__arm_vmulq_f16): Remove.
- (__arm_vmulq_n_f32): Remove.
- (__arm_vmulq_f32): Remove.
- (__arm_vmulq_m_f32): Remove.
- (__arm_vmulq_m_f16): Remove.
- (__arm_vmulq_m_n_f32): Remove.
- (__arm_vmulq_m_n_f16): Remove.
- (__arm_vmulq_x_f16): Remove.
- (__arm_vmulq_x_f32): Remove.
- (__arm_vmulq_x_n_f16): Remove.
- (__arm_vmulq_x_n_f32): Remove.
- (__arm_vmulq): Remove.
- (__arm_vmulq_m): Remove.
- (__arm_vmulq_x): Remove.
- (vsubq): Remove.
- (vsubq_m): Remove.
- (vsubq_x): Remove.
- (vsubq_n_f16): Remove.
- (vsubq_n_f32): Remove.
- (vsubq_u8): Remove.
- (vsubq_n_u8): Remove.
- (vsubq_s8): Remove.
- (vsubq_n_s8): Remove.
- (vsubq_u16): Remove.
- (vsubq_n_u16): Remove.
- (vsubq_s16): Remove.
- (vsubq_n_s16): Remove.
- (vsubq_u32): Remove.
- (vsubq_n_u32): Remove.
- (vsubq_s32): Remove.
- (vsubq_n_s32): Remove.
- (vsubq_f16): Remove.
- (vsubq_f32): Remove.
- (vsubq_m_s8): Remove.
- (vsubq_m_u8): Remove.
- (vsubq_m_s16): Remove.
- (vsubq_m_u16): Remove.
- (vsubq_m_s32): Remove.
- (vsubq_m_u32): Remove.
- (vsubq_m_n_s8): Remove.
- (vsubq_m_n_s32): Remove.
- (vsubq_m_n_s16): Remove.
- (vsubq_m_n_u8): Remove.
- (vsubq_m_n_u32): Remove.
- (vsubq_m_n_u16): Remove.
- (vsubq_m_f32): Remove.
- (vsubq_m_f16): Remove.
- (vsubq_m_n_f32): Remove.
- (vsubq_m_n_f16): Remove.
- (vsubq_x_s8): Remove.
- (vsubq_x_s16): Remove.
- (vsubq_x_s32): Remove.
- (vsubq_x_n_s8): Remove.
- (vsubq_x_n_s16): Remove.
- (vsubq_x_n_s32): Remove.
- (vsubq_x_u8): Remove.
- (vsubq_x_u16): Remove.
- (vsubq_x_u32): Remove.
- (vsubq_x_n_u8): Remove.
- (vsubq_x_n_u16): Remove.
- (vsubq_x_n_u32): Remove.
- (vsubq_x_f16): Remove.
- (vsubq_x_f32): Remove.
- (vsubq_x_n_f16): Remove.
- (vsubq_x_n_f32): Remove.
- (__arm_vsubq_u8): Remove.
- (__arm_vsubq_n_u8): Remove.
- (__arm_vsubq_s8): Remove.
- (__arm_vsubq_n_s8): Remove.
- (__arm_vsubq_u16): Remove.
- (__arm_vsubq_n_u16): Remove.
- (__arm_vsubq_s16): Remove.
- (__arm_vsubq_n_s16): Remove.
- (__arm_vsubq_u32): Remove.
- (__arm_vsubq_n_u32): Remove.
- (__arm_vsubq_s32): Remove.
- (__arm_vsubq_n_s32): Remove.
- (__arm_vsubq_m_s8): Remove.
- (__arm_vsubq_m_u8): Remove.
- (__arm_vsubq_m_s16): Remove.
- (__arm_vsubq_m_u16): Remove.
- (__arm_vsubq_m_s32): Remove.
- (__arm_vsubq_m_u32): Remove.
- (__arm_vsubq_m_n_s8): Remove.
- (__arm_vsubq_m_n_s32): Remove.
- (__arm_vsubq_m_n_s16): Remove.
- (__arm_vsubq_m_n_u8): Remove.
- (__arm_vsubq_m_n_u32): Remove.
- (__arm_vsubq_m_n_u16): Remove.
- (__arm_vsubq_x_s8): Remove.
- (__arm_vsubq_x_s16): Remove.
- (__arm_vsubq_x_s32): Remove.
- (__arm_vsubq_x_n_s8): Remove.
- (__arm_vsubq_x_n_s16): Remove.
- (__arm_vsubq_x_n_s32): Remove.
- (__arm_vsubq_x_u8): Remove.
- (__arm_vsubq_x_u16): Remove.
- (__arm_vsubq_x_u32): Remove.
- (__arm_vsubq_x_n_u8): Remove.
- (__arm_vsubq_x_n_u16): Remove.
- (__arm_vsubq_x_n_u32): Remove.
- (__arm_vsubq_n_f16): Remove.
- (__arm_vsubq_n_f32): Remove.
- (__arm_vsubq_f16): Remove.
- (__arm_vsubq_f32): Remove.
- (__arm_vsubq_m_f32): Remove.
- (__arm_vsubq_m_f16): Remove.
- (__arm_vsubq_m_n_f32): Remove.
- (__arm_vsubq_m_n_f16): Remove.
- (__arm_vsubq_x_f16): Remove.
- (__arm_vsubq_x_f32): Remove.
- (__arm_vsubq_x_n_f16): Remove.
- (__arm_vsubq_x_n_f32): Remove.
- (__arm_vsubq): Remove.
- (__arm_vsubq_m): Remove.
- (__arm_vsubq_x): Remove.
- * config/arm/arm_mve_builtins.def (vsubq_u, vsubq_s, vsubq_f):
- Remove.
- (vmulq_u, vmulq_s, vmulq_f): Remove.
- * config/arm/mve.md (mve_vsubq_<supf><mode>): Remove.
- (mve_vmulq_<supf><mode>): Remove.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/iterators.md (MVE_INT_BINARY_RTX, MVE_INT_M_BINARY)
- (MVE_INT_M_N_BINARY, MVE_INT_N_BINARY, MVE_FP_M_BINARY)
- (MVE_FP_M_N_BINARY, MVE_FP_N_BINARY, mve_addsubmul, mve_insn): New
- iterators.
- * config/arm/mve.md
- (mve_vsubq_n_f<mode>, mve_vaddq_n_f<mode>, mve_vmulq_n_f<mode>):
- Factorize into ...
- (@mve_<mve_insn>q_n_f<mode>): ... this.
- (mve_vaddq_n_<supf><mode>, mve_vmulq_n_<supf><mode>)
- (mve_vsubq_n_<supf><mode>): Factorize into ...
- (@mve_<mve_insn>q_n_<supf><mode>): ... this.
- (mve_vaddq<mode>, mve_vmulq<mode>, mve_vsubq<mode>): Factorize
- into ...
- (mve_<mve_addsubmul>q<mode>): ... this.
- (mve_vaddq_f<mode>, mve_vmulq_f<mode>, mve_vsubq_f<mode>):
- Factorize into ...
- (mve_<mve_addsubmul>q_f<mode>): ... this.
- (mve_vaddq_m_<supf><mode>, mve_vmulq_m_<supf><mode>)
- (mve_vsubq_m_<supf><mode>): Factorize into ...
- (@mve_<mve_insn>q_m_<supf><mode>): ... this,
- (mve_vaddq_m_n_<supf><mode>, mve_vmulq_m_n_<supf><mode>)
- (mve_vsubq_m_n_<supf><mode>): Factorize into ...
- (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
- (mve_vaddq_m_f<mode>, mve_vmulq_m_f<mode>, mve_vsubq_m_f<mode>):
- Factorize into ...
- (@mve_<mve_insn>q_m_f<mode>): ... this.
- (mve_vaddq_m_n_f<mode>, mve_vmulq_m_n_f<mode>)
- (mve_vsubq_m_n_f<mode>): Factorize into ...
- (@mve_<mve_insn>q_m_n_f<mode>): ... this.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-functions.h (class
- unspec_based_mve_function_base): New.
- (class unspec_based_mve_function_exact_insn): New.
-
-2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-shapes.cc (binary_opt_n): New.
- * config/arm/arm-mve-builtins-shapes.h (binary_opt_n): New.
-
-2023-05-03 Murray Steele <murray.steele@arm.com>
- Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (class
- vuninitializedq_impl): New.
- * config/arm/arm-mve-builtins-base.def (vuninitializedq): New.
- * config/arm/arm-mve-builtins-base.h (vuninitializedq): New
- declaration.
- * config/arm/arm-mve-builtins-shapes.cc (inherent): New.
- * config/arm/arm-mve-builtins-shapes.h (inherent): New
- declaration.
- * config/arm/arm_mve_types.h (__arm_vuninitializedq): Move to ...
- * config/arm/arm_mve.h (__arm_vuninitializedq): ... here.
- (__arm_vuninitializedq_u8): Remove.
- (__arm_vuninitializedq_u16): Remove.
- (__arm_vuninitializedq_u32): Remove.
- (__arm_vuninitializedq_u64): Remove.
- (__arm_vuninitializedq_s8): Remove.
- (__arm_vuninitializedq_s16): Remove.
- (__arm_vuninitializedq_s32): Remove.
- (__arm_vuninitializedq_s64): Remove.
- (__arm_vuninitializedq_f16): Remove.
- (__arm_vuninitializedq_f32): Remove.
-
-2023-05-03 Murray Steele <murray.steele@arm.com>
- Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-mve-builtins-base.cc (vreinterpretq_impl): New class.
- * config/arm/arm-mve-builtins-base.def: Define vreinterpretq.
- * config/arm/arm-mve-builtins-base.h (vreinterpretq): New declaration.
- * config/arm/arm-mve-builtins-shapes.cc (parse_element_type): New function.
- (parse_type): Likewise.
- (parse_signature): Likewise.
- (build_one): Likewise.
- (build_all): Likewise.
- (overloaded_base): New struct.
- (unary_convert_def): Likewise.
- * config/arm/arm-mve-builtins-shapes.h (unary_convert): Declare.
- * config/arm/arm-mve-builtins.cc (TYPES_reinterpret_signed1): New
- macro.
- (TYPES_reinterpret_unsigned1): Likewise.
- (TYPES_reinterpret_integer): Likewise.
- (TYPES_reinterpret_integer1): Likewise.
- (TYPES_reinterpret_float1): Likewise.
- (TYPES_reinterpret_float): Likewise.
- (reinterpret_integer): New.
- (reinterpret_float): New.
- (handle_arm_mve_h): Register builtins.
- * config/arm/arm_mve.h (vreinterpretq_s16): Remove.
- (vreinterpretq_s32): Likewise.
- (vreinterpretq_s64): Likewise.
- (vreinterpretq_s8): Likewise.
- (vreinterpretq_u16): Likewise.
- (vreinterpretq_u32): Likewise.
- (vreinterpretq_u64): Likewise.
- (vreinterpretq_u8): Likewise.
- (vreinterpretq_f16): Likewise.
- (vreinterpretq_f32): Likewise.
- (vreinterpretq_s16_s32): Likewise.
- (vreinterpretq_s16_s64): Likewise.
- (vreinterpretq_s16_s8): Likewise.
- (vreinterpretq_s16_u16): Likewise.
- (vreinterpretq_s16_u32): Likewise.
- (vreinterpretq_s16_u64): Likewise.
- (vreinterpretq_s16_u8): Likewise.
- (vreinterpretq_s32_s16): Likewise.
- (vreinterpretq_s32_s64): Likewise.
- (vreinterpretq_s32_s8): Likewise.
- (vreinterpretq_s32_u16): Likewise.
- (vreinterpretq_s32_u32): Likewise.
- (vreinterpretq_s32_u64): Likewise.
- (vreinterpretq_s32_u8): Likewise.
- (vreinterpretq_s64_s16): Likewise.
- (vreinterpretq_s64_s32): Likewise.
- (vreinterpretq_s64_s8): Likewise.
- (vreinterpretq_s64_u16): Likewise.
- (vreinterpretq_s64_u32): Likewise.
- (vreinterpretq_s64_u64): Likewise.
- (vreinterpretq_s64_u8): Likewise.
- (vreinterpretq_s8_s16): Likewise.
- (vreinterpretq_s8_s32): Likewise.
- (vreinterpretq_s8_s64): Likewise.
- (vreinterpretq_s8_u16): Likewise.
- (vreinterpretq_s8_u32): Likewise.
- (vreinterpretq_s8_u64): Likewise.
- (vreinterpretq_s8_u8): Likewise.
- (vreinterpretq_u16_s16): Likewise.
- (vreinterpretq_u16_s32): Likewise.
- (vreinterpretq_u16_s64): Likewise.
- (vreinterpretq_u16_s8): Likewise.
- (vreinterpretq_u16_u32): Likewise.
- (vreinterpretq_u16_u64): Likewise.
- (vreinterpretq_u16_u8): Likewise.
- (vreinterpretq_u32_s16): Likewise.
- (vreinterpretq_u32_s32): Likewise.
- (vreinterpretq_u32_s64): Likewise.
- (vreinterpretq_u32_s8): Likewise.
- (vreinterpretq_u32_u16): Likewise.
- (vreinterpretq_u32_u64): Likewise.
- (vreinterpretq_u32_u8): Likewise.
- (vreinterpretq_u64_s16): Likewise.
- (vreinterpretq_u64_s32): Likewise.
- (vreinterpretq_u64_s64): Likewise.
- (vreinterpretq_u64_s8): Likewise.
- (vreinterpretq_u64_u16): Likewise.
- (vreinterpretq_u64_u32): Likewise.
- (vreinterpretq_u64_u8): Likewise.
- (vreinterpretq_u8_s16): Likewise.
- (vreinterpretq_u8_s32): Likewise.
- (vreinterpretq_u8_s64): Likewise.
- (vreinterpretq_u8_s8): Likewise.
- (vreinterpretq_u8_u16): Likewise.
- (vreinterpretq_u8_u32): Likewise.
- (vreinterpretq_u8_u64): Likewise.
- (vreinterpretq_s32_f16): Likewise.
- (vreinterpretq_s32_f32): Likewise.
- (vreinterpretq_u16_f16): Likewise.
- (vreinterpretq_u16_f32): Likewise.
- (vreinterpretq_u32_f16): Likewise.
- (vreinterpretq_u32_f32): Likewise.
- (vreinterpretq_u64_f16): Likewise.
- (vreinterpretq_u64_f32): Likewise.
- (vreinterpretq_u8_f16): Likewise.
- (vreinterpretq_u8_f32): Likewise.
- (vreinterpretq_f16_f32): Likewise.
- (vreinterpretq_f16_s16): Likewise.
- (vreinterpretq_f16_s32): Likewise.
- (vreinterpretq_f16_s64): Likewise.
- (vreinterpretq_f16_s8): Likewise.
- (vreinterpretq_f16_u16): Likewise.
- (vreinterpretq_f16_u32): Likewise.
- (vreinterpretq_f16_u64): Likewise.
- (vreinterpretq_f16_u8): Likewise.
- (vreinterpretq_f32_f16): Likewise.
- (vreinterpretq_f32_s16): Likewise.
- (vreinterpretq_f32_s32): Likewise.
- (vreinterpretq_f32_s64): Likewise.
- (vreinterpretq_f32_s8): Likewise.
- (vreinterpretq_f32_u16): Likewise.
- (vreinterpretq_f32_u32): Likewise.
- (vreinterpretq_f32_u64): Likewise.
- (vreinterpretq_f32_u8): Likewise.
- (vreinterpretq_s16_f16): Likewise.
- (vreinterpretq_s16_f32): Likewise.
- (vreinterpretq_s64_f16): Likewise.
- (vreinterpretq_s64_f32): Likewise.
- (vreinterpretq_s8_f16): Likewise.
- (vreinterpretq_s8_f32): Likewise.
- (__arm_vreinterpretq_f16): Likewise.
- (__arm_vreinterpretq_f32): Likewise.
- (__arm_vreinterpretq_s16): Likewise.
- (__arm_vreinterpretq_s32): Likewise.
- (__arm_vreinterpretq_s64): Likewise.
- (__arm_vreinterpretq_s8): Likewise.
- (__arm_vreinterpretq_u16): Likewise.
- (__arm_vreinterpretq_u32): Likewise.
- (__arm_vreinterpretq_u64): Likewise.
- (__arm_vreinterpretq_u8): Likewise.
- * config/arm/arm_mve_types.h (__arm_vreinterpretq_s16_s32): Remove.
- (__arm_vreinterpretq_s16_s64): Likewise.
- (__arm_vreinterpretq_s16_s8): Likewise.
- (__arm_vreinterpretq_s16_u16): Likewise.
- (__arm_vreinterpretq_s16_u32): Likewise.
- (__arm_vreinterpretq_s16_u64): Likewise.
- (__arm_vreinterpretq_s16_u8): Likewise.
- (__arm_vreinterpretq_s32_s16): Likewise.
- (__arm_vreinterpretq_s32_s64): Likewise.
- (__arm_vreinterpretq_s32_s8): Likewise.
- (__arm_vreinterpretq_s32_u16): Likewise.
- (__arm_vreinterpretq_s32_u32): Likewise.
- (__arm_vreinterpretq_s32_u64): Likewise.
- (__arm_vreinterpretq_s32_u8): Likewise.
- (__arm_vreinterpretq_s64_s16): Likewise.
- (__arm_vreinterpretq_s64_s32): Likewise.
- (__arm_vreinterpretq_s64_s8): Likewise.
- (__arm_vreinterpretq_s64_u16): Likewise.
- (__arm_vreinterpretq_s64_u32): Likewise.
- (__arm_vreinterpretq_s64_u64): Likewise.
- (__arm_vreinterpretq_s64_u8): Likewise.
- (__arm_vreinterpretq_s8_s16): Likewise.
- (__arm_vreinterpretq_s8_s32): Likewise.
- (__arm_vreinterpretq_s8_s64): Likewise.
- (__arm_vreinterpretq_s8_u16): Likewise.
- (__arm_vreinterpretq_s8_u32): Likewise.
- (__arm_vreinterpretq_s8_u64): Likewise.
- (__arm_vreinterpretq_s8_u8): Likewise.
- (__arm_vreinterpretq_u16_s16): Likewise.
- (__arm_vreinterpretq_u16_s32): Likewise.
- (__arm_vreinterpretq_u16_s64): Likewise.
- (__arm_vreinterpretq_u16_s8): Likewise.
- (__arm_vreinterpretq_u16_u32): Likewise.
- (__arm_vreinterpretq_u16_u64): Likewise.
- (__arm_vreinterpretq_u16_u8): Likewise.
- (__arm_vreinterpretq_u32_s16): Likewise.
- (__arm_vreinterpretq_u32_s32): Likewise.
- (__arm_vreinterpretq_u32_s64): Likewise.
- (__arm_vreinterpretq_u32_s8): Likewise.
- (__arm_vreinterpretq_u32_u16): Likewise.
- (__arm_vreinterpretq_u32_u64): Likewise.
- (__arm_vreinterpretq_u32_u8): Likewise.
- (__arm_vreinterpretq_u64_s16): Likewise.
- (__arm_vreinterpretq_u64_s32): Likewise.
- (__arm_vreinterpretq_u64_s64): Likewise.
- (__arm_vreinterpretq_u64_s8): Likewise.
- (__arm_vreinterpretq_u64_u16): Likewise.
- (__arm_vreinterpretq_u64_u32): Likewise.
- (__arm_vreinterpretq_u64_u8): Likewise.
- (__arm_vreinterpretq_u8_s16): Likewise.
- (__arm_vreinterpretq_u8_s32): Likewise.
- (__arm_vreinterpretq_u8_s64): Likewise.
- (__arm_vreinterpretq_u8_s8): Likewise.
- (__arm_vreinterpretq_u8_u16): Likewise.
- (__arm_vreinterpretq_u8_u32): Likewise.
- (__arm_vreinterpretq_u8_u64): Likewise.
- (__arm_vreinterpretq_s32_f16): Likewise.
- (__arm_vreinterpretq_s32_f32): Likewise.
- (__arm_vreinterpretq_s16_f16): Likewise.
- (__arm_vreinterpretq_s16_f32): Likewise.
- (__arm_vreinterpretq_s64_f16): Likewise.
- (__arm_vreinterpretq_s64_f32): Likewise.
- (__arm_vreinterpretq_s8_f16): Likewise.
- (__arm_vreinterpretq_s8_f32): Likewise.
- (__arm_vreinterpretq_u16_f16): Likewise.
- (__arm_vreinterpretq_u16_f32): Likewise.
- (__arm_vreinterpretq_u32_f16): Likewise.
- (__arm_vreinterpretq_u32_f32): Likewise.
- (__arm_vreinterpretq_u64_f16): Likewise.
- (__arm_vreinterpretq_u64_f32): Likewise.
- (__arm_vreinterpretq_u8_f16): Likewise.
- (__arm_vreinterpretq_u8_f32): Likewise.
- (__arm_vreinterpretq_f16_f32): Likewise.
- (__arm_vreinterpretq_f16_s16): Likewise.
- (__arm_vreinterpretq_f16_s32): Likewise.
- (__arm_vreinterpretq_f16_s64): Likewise.
- (__arm_vreinterpretq_f16_s8): Likewise.
- (__arm_vreinterpretq_f16_u16): Likewise.
- (__arm_vreinterpretq_f16_u32): Likewise.
- (__arm_vreinterpretq_f16_u64): Likewise.
- (__arm_vreinterpretq_f16_u8): Likewise.
- (__arm_vreinterpretq_f32_f16): Likewise.
- (__arm_vreinterpretq_f32_s16): Likewise.
- (__arm_vreinterpretq_f32_s32): Likewise.
- (__arm_vreinterpretq_f32_s64): Likewise.
- (__arm_vreinterpretq_f32_s8): Likewise.
- (__arm_vreinterpretq_f32_u16): Likewise.
- (__arm_vreinterpretq_f32_u32): Likewise.
- (__arm_vreinterpretq_f32_u64): Likewise.
- (__arm_vreinterpretq_f32_u8): Likewise.
- (__arm_vreinterpretq_s16): Likewise.
- (__arm_vreinterpretq_s32): Likewise.
- (__arm_vreinterpretq_s64): Likewise.
- (__arm_vreinterpretq_s8): Likewise.
- (__arm_vreinterpretq_u16): Likewise.
- (__arm_vreinterpretq_u32): Likewise.
- (__arm_vreinterpretq_u64): Likewise.
- (__arm_vreinterpretq_u8): Likewise.
- (__arm_vreinterpretq_f16): Likewise.
- (__arm_vreinterpretq_f32): Likewise.
- * config/arm/mve.md (@arm_mve_reinterpret<mode>): New pattern.
- * config/arm/unspecs.md: (REINTERPRET): New unspec.
-
-2023-05-03 Murray Steele <murray.steele@arm.com>
- Christophe Lyon <christophe.lyon@arm.com>
- Christophe Lyon <christophe.lyon@arm.com
-
- * config.gcc: Add arm-mve-builtins-base.o and
- arm-mve-builtins-shapes.o to extra_objs.
- * config/arm/arm-builtins.cc (arm_builtin_decl): Handle MVE builtin
- numberspace.
- (arm_expand_builtin): Likewise
- (arm_check_builtin_call): Likewise
- (arm_describe_resolver): Likewise.
- * config/arm/arm-builtins.h (enum resolver_ident): Add
- arm_mve_resolver.
- * config/arm/arm-c.cc (arm_pragma_arm): Handle new pragma.
- (arm_resolve_overloaded_builtin): Handle MVE builtins.
- (arm_register_target_pragmas): Register arm_check_builtin_call.
- * config/arm/arm-mve-builtins.cc (class registered_function): New
- class.
- (struct registered_function_hasher): New struct.
- (pred_suffixes): New table.
- (mode_suffixes): New table.
- (type_suffix_info): New table.
- (TYPES_float16): New.
- (TYPES_all_float): New.
- (TYPES_integer_8): New.
- (TYPES_integer_8_16): New.
- (TYPES_integer_16_32): New.
- (TYPES_integer_32): New.
- (TYPES_signed_16_32): New.
- (TYPES_signed_32): New.
- (TYPES_all_signed): New.
- (TYPES_all_unsigned): New.
- (TYPES_all_integer): New.
- (TYPES_all_integer_with_64): New.
- (DEF_VECTOR_TYPE): New.
- (DEF_DOUBLE_TYPE): New.
- (DEF_MVE_TYPES_ARRAY): New.
- (all_integer): New.
- (all_integer_with_64): New.
- (float16): New.
- (all_float): New.
- (all_signed): New.
- (all_unsigned): New.
- (integer_8): New.
- (integer_8_16): New.
- (integer_16_32): New.
- (integer_32): New.
- (signed_16_32): New.
- (signed_32): New.
- (register_vector_type): Use void_type_node for mve.fp-only types when
- mve.fp is not enabled.
- (register_builtin_tuple_types): Likewise.
- (handle_arm_mve_h): New function..
- (matches_type_p): Likewise..
- (report_out_of_range): Likewise.
- (report_not_enum): Likewise.
- (report_missing_float): Likewise.
- (report_non_ice): Likewise.
- (check_requires_float): Likewise.
- (function_instance::hash): Likewise
- (function_instance::call_properties): Likewise.
- (function_instance::reads_global_state_p): Likewise.
- (function_instance::modifies_global_state_p): Likewise.
- (function_instance::could_trap_p): Likewise.
- (function_instance::has_inactive_argument): Likewise.
- (registered_function_hasher::hash): Likewise.
- (registered_function_hasher::equal): Likewise.
- (function_builder::function_builder): Likewise.
- (function_builder::~function_builder): Likewise.
- (function_builder::append_name): Likewise.
- (function_builder::finish_name): Likewise.
- (function_builder::get_name): Likewise.
- (add_attribute): Likewise.
- (function_builder::get_attributes): Likewise.
- (function_builder::add_function): Likewise.
- (function_builder::add_unique_function): Likewise.
- (function_builder::add_overloaded_function): Likewise.
- (function_builder::add_overloaded_functions): Likewise.
- (function_builder::register_function_group): Likewise.
- (function_call_info::function_call_info): Likewise.
- (function_resolver::function_resolver): Likewise.
- (function_resolver::get_vector_type): Likewise.
- (function_resolver::get_scalar_type_name): Likewise.
- (function_resolver::get_argument_type): Likewise.
- (function_resolver::scalar_argument_p): Likewise.
- (function_resolver::report_no_such_form): Likewise.
- (function_resolver::lookup_form): Likewise.
- (function_resolver::resolve_to): Likewise.
- (function_resolver::infer_vector_or_tuple_type): Likewise.
- (function_resolver::infer_vector_type): Likewise.
- (function_resolver::require_vector_or_scalar_type): Likewise.
- (function_resolver::require_vector_type): Likewise.
- (function_resolver::require_matching_vector_type): Likewise.
- (function_resolver::require_derived_vector_type): Likewise.
- (function_resolver::require_derived_scalar_type): Likewise.
- (function_resolver::require_integer_immediate): Likewise.
- (function_resolver::require_scalar_type): Likewise.
- (function_resolver::check_num_arguments): Likewise.
- (function_resolver::check_gp_argument): Likewise.
- (function_resolver::finish_opt_n_resolution): Likewise.
- (function_resolver::resolve_unary): Likewise.
- (function_resolver::resolve_unary_n): Likewise.
- (function_resolver::resolve_uniform): Likewise.
- (function_resolver::resolve_uniform_opt_n): Likewise.
- (function_resolver::resolve): Likewise.
- (function_checker::function_checker): Likewise.
- (function_checker::argument_exists_p): Likewise.
- (function_checker::require_immediate): Likewise.
- (function_checker::require_immediate_enum): Likewise.
- (function_checker::require_immediate_range): Likewise.
- (function_checker::check): Likewise.
- (gimple_folder::gimple_folder): Likewise.
- (gimple_folder::fold): Likewise.
- (function_expander::function_expander): Likewise.
- (function_expander::direct_optab_handler): Likewise.
- (function_expander::get_fallback_value): Likewise.
- (function_expander::get_reg_target): Likewise.
- (function_expander::add_output_operand): Likewise.
- (function_expander::add_input_operand): Likewise.
- (function_expander::add_integer_operand): Likewise.
- (function_expander::generate_insn): Likewise.
- (function_expander::use_exact_insn): Likewise.
- (function_expander::use_unpred_insn): Likewise.
- (function_expander::use_pred_x_insn): Likewise.
- (function_expander::use_cond_insn): Likewise.
- (function_expander::map_to_rtx_codes): Likewise.
- (function_expander::expand): Likewise.
- (resolve_overloaded_builtin): Likewise.
- (check_builtin_call): Likewise.
- (gimple_fold_builtin): Likewise.
- (expand_builtin): Likewise.
- (gt_ggc_mx): Likewise.
- (gt_pch_nx): Likewise.
- (gt_pch_nx): Likewise.
- * config/arm/arm-mve-builtins.def(s8): Define new type suffix.
- (s16): Likewise.
- (s32): Likewise.
- (s64): Likewise.
- (u8): Likewise.
- (u16): Likewise.
- (u32): Likewise.
- (u64): Likewise.
- (f16): Likewise.
- (f32): Likewise.
- (n): New mode.
- (offset): New mode.
- * config/arm/arm-mve-builtins.h (MAX_TUPLE_SIZE): New constant.
- (CP_READ_FPCR): Likewise.
- (CP_RAISE_FP_EXCEPTIONS): Likewise.
- (CP_READ_MEMORY): Likewise.
- (CP_WRITE_MEMORY): Likewise.
- (enum units_index): New enum.
- (enum predication_index): New.
- (enum type_class_index): New.
- (enum mode_suffix_index): New enum.
- (enum type_suffix_index): New.
- (struct mode_suffix_info): New struct.
- (struct type_suffix_info): New.
- (struct function_group_info): Likewise.
- (class function_instance): Likewise.
- (class registered_function): Likewise.
- (class function_builder): Likewise.
- (class function_call_info): Likewise.
- (class function_resolver): Likewise.
- (class function_checker): Likewise.
- (class gimple_folder): Likewise.
- (class function_expander): Likewise.
- (get_mve_pred16_t): Likewise.
- (find_mode_suffix): New function.
- (class function_base): Likewise.
- (class function_shape): Likewise.
- (function_instance::operator==): New function.
- (function_instance::operator!=): Likewise.
- (function_instance::vectors_per_tuple): Likewise.
- (function_instance::mode_suffix): Likewise.
- (function_instance::type_suffix): Likewise.
- (function_instance::scalar_type): Likewise.
- (function_instance::vector_type): Likewise.
- (function_instance::tuple_type): Likewise.
- (function_instance::vector_mode): Likewise.
- (function_call_info::function_returns_void_p): Likewise.
- (function_base::call_properties): Likewise.
- * config/arm/arm-protos.h (enum arm_builtin_class): Add
- ARM_BUILTIN_MVE.
- (handle_arm_mve_h): New.
- (resolve_overloaded_builtin): New.
- (check_builtin_call): New.
- (gimple_fold_builtin): New.
- (expand_builtin): New.
- * config/arm/arm.cc (TARGET_GIMPLE_FOLD_BUILTIN): Define as
- arm_gimple_fold_builtin.
- (arm_gimple_fold_builtin): New function.
- * config/arm/arm_mve.h: Use new arm_mve.h pragma.
- * config/arm/predicates.md (arm_any_register_operand): New predicate.
- * config/arm/t-arm: (arm-mve-builtins.o): Add includes.
- (arm-mve-builtins-shapes.o): New target.
- (arm-mve-builtins-base.o): New target.
- * config/arm/arm-mve-builtins-base.cc: New file.
- * config/arm/arm-mve-builtins-base.def: New file.
- * config/arm/arm-mve-builtins-base.h: New file.
- * config/arm/arm-mve-builtins-functions.h: New file.
- * config/arm/arm-mve-builtins-shapes.cc: New file.
- * config/arm/arm-mve-builtins-shapes.h: New file.
-
-2023-05-03 Murray Steele <murray.steele@arm.com>
- Christophe Lyon <christophe.lyon@arm.com>
- Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/arm-builtins.cc (arm_general_add_builtin_function):
- New function.
- (arm_init_builtin): Use arm_general_add_builtin_function instead
- of arm_add_builtin_function.
- (arm_init_acle_builtins): Likewise.
- (arm_init_mve_builtins): Likewise.
- (arm_init_crypto_builtins): Likewise.
- (arm_init_builtins): Likewise.
- (arm_general_builtin_decl): New function.
- (arm_builtin_decl): Defer to numberspace-specialized functions.
- (arm_expand_builtin_args): Rename into arm_general_expand_builtin_args.
- (arm_expand_builtin_1): Rename into arm_general_expand_builtin_1 and ...
- (arm_general_expand_builtin_1): ... specialize for general builtins.
- (arm_expand_acle_builtin): Use arm_general_expand_builtin
- instead of arm_expand_builtin.
- (arm_expand_mve_builtin): Likewise.
- (arm_expand_neon_builtin): Likewise.
- (arm_expand_vfp_builtin): Likewise.
- (arm_general_expand_builtin): New function.
- (arm_expand_builtin): Specialize for general builtins.
- (arm_general_check_builtin_call): New function.
- (arm_check_builtin_call): Specialize for general builtins.
- (arm_describe_resolver): Validate numberspace.
- (arm_cde_end_args): Likewise.
- * config/arm/arm-protos.h (enum arm_builtin_class): New enum.
- (ARM_BUILTIN_SHIFT, ARM_BUILTIN_CLASS): New constants.
-
-2023-05-03 Martin Liska <mliska@suse.cz>
-
- PR target/109713
- * config/riscv/sync.md: Add gcc_unreachable to a switch.
-
-2023-05-03 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-loop-split.cc (split_at_bb_p): Avoid last_stmt.
- (patch_loop_exit): Likewise.
- (connect_loops): Likewise.
- (split_loop): Likewise.
- (control_dep_semi_invariant_p): Likewise.
- (do_split_loop_on_cond): Likewise.
- (split_loop_on_cond): Likewise.
- * tree-ssa-loop-unswitch.cc (find_unswitching_predicates_for_bb):
- Likewise.
- (simplify_loop_version): Likewise.
- (evaluate_bbs): Likewise.
- (find_loop_guard): Likewise.
- (clean_up_after_unswitching): Likewise.
- * tree-ssa-math-opts.cc (maybe_optimize_guarding_check):
- Likewise.
- (optimize_spaceship): Take a gcond * argument, avoid
- last_stmt.
- (math_opts_dom_walker::after_dom_children): Adjust call to
- optimize_spaceship.
- * tree-vrp.cc (maybe_set_nonzero_bits): Avoid last_stmt.
- * value-pointer-equiv.cc (pointer_equiv_analyzer::visit_edge):
- Likewise.
+2024-02-14 Uros Bizjak <ubizjak@gmail.com>
-2023-05-03 Andreas Schwab <schwab@suse.de>
+ PR target/113871
+ * config/i386/mmx.md (V248FI): New mode iterator.
+ (V24FI_32): DItto.
+ (vec_shl_<V248FI:mode>): New expander.
+ (vec_shl_<V24FI_32:mode>): Ditto.
+ (vec_shr_<V248FI:mode>): Ditto.
+ (vec_shr_<V24FI_32:mode>): Ditto.
+ * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
+ (vec_shr_<V248FI:mode>): Ditto.
- * config/riscv/linux.h (LIB_SPEC): Don't redefine.
+2024-02-14 Jan Hubicka <jh@suse.cz>
-2023-05-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+ PR tree-optimization/111054
+ * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
- * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load):
- New function.
- (class vlseg): New class.
- (class vsseg): Ditto.
- (class vlsseg): Ditto.
- (class vssseg): Ditto.
- (class seg_indexed_load): Ditto.
- (class seg_indexed_store): Ditto.
- (class vlsegff): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vlseg):
- Ditto.
- (vsseg): Ditto.
- (vlsseg): Ditto.
- (vssseg): Ditto.
- (vluxseg): Ditto.
- (vloxseg): Ditto.
- (vsuxseg): Ditto.
- (vsoxseg): Ditto.
- (vlsegff): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct
- seg_loadstore_def): Ditto.
- (struct seg_indexed_loadstore_def): Ditto.
- (struct seg_fault_load_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc
- (function_builder::append_nf): New function.
- * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t):
- Change ptr from double into float.
- (vfloat32m1x3_t): Ditto.
- (vfloat32m1x4_t): Ditto.
- (vfloat32m1x5_t): Ditto.
- (vfloat32m1x6_t): Ditto.
- (vfloat32m1x7_t): Ditto.
- (vfloat32m1x8_t): Ditto.
- (vfloat32m2x2_t): Ditto.
- (vfloat32m2x3_t): Ditto.
- (vfloat32m2x4_t): Ditto.
- (vfloat32m4x2_t): Ditto.
- * config/riscv/riscv-vector-builtins.h: Add segment intrinsics.
- * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for
- segment ff load.
- * config/riscv/riscv.md: Add segment instructions.
- * config/riscv/vector-iterators.md: Support segment intrinsics.
- * config/riscv/vector.md (@pred_unit_strided_load<mode>): New
- pattern.
- (@pred_unit_strided_store<mode>): Ditto.
- (@pred_strided_load<mode>): Ditto.
- (@pred_strided_store<mode>): Ditto.
- (@pred_fault_load<mode>): Ditto.
- (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto.
- (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto.
- (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto.
- (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto.
- (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto.
- (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto.
- (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto.
- (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto.
- (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto.
- (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto.
- (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto.
- (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto.
- (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto.
- (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto.
-
-2023-05-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/genrvv-type-indexer.cc (valid_type): Adapt for
- tuple type support.
- (inttype): Ditto.
- (floattype): Ditto.
- (main): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vset): Add
- tuple type vset.
- (vget): Add tuple type vget.
- * config/riscv/riscv-vector-builtins-types.def
- (DEF_RVV_TUPLE_OPS): New macro.
- (vint8mf8x2_t): Ditto.
- (vuint8mf8x2_t): Ditto.
- (vint8mf8x3_t): Ditto.
- (vuint8mf8x3_t): Ditto.
- (vint8mf8x4_t): Ditto.
- (vuint8mf8x4_t): Ditto.
- (vint8mf8x5_t): Ditto.
- (vuint8mf8x5_t): Ditto.
- (vint8mf8x6_t): Ditto.
- (vuint8mf8x6_t): Ditto.
- (vint8mf8x7_t): Ditto.
- (vuint8mf8x7_t): Ditto.
- (vint8mf8x8_t): Ditto.
- (vuint8mf8x8_t): Ditto.
- (vint8mf4x2_t): Ditto.
- (vuint8mf4x2_t): Ditto.
- (vint8mf4x3_t): Ditto.
- (vuint8mf4x3_t): Ditto.
- (vint8mf4x4_t): Ditto.
- (vuint8mf4x4_t): Ditto.
- (vint8mf4x5_t): Ditto.
- (vuint8mf4x5_t): Ditto.
- (vint8mf4x6_t): Ditto.
- (vuint8mf4x6_t): Ditto.
- (vint8mf4x7_t): Ditto.
- (vuint8mf4x7_t): Ditto.
- (vint8mf4x8_t): Ditto.
- (vuint8mf4x8_t): Ditto.
- (vint8mf2x2_t): Ditto.
- (vuint8mf2x2_t): Ditto.
- (vint8mf2x3_t): Ditto.
- (vuint8mf2x3_t): Ditto.
- (vint8mf2x4_t): Ditto.
- (vuint8mf2x4_t): Ditto.
- (vint8mf2x5_t): Ditto.
- (vuint8mf2x5_t): Ditto.
- (vint8mf2x6_t): Ditto.
- (vuint8mf2x6_t): Ditto.
- (vint8mf2x7_t): Ditto.
- (vuint8mf2x7_t): Ditto.
- (vint8mf2x8_t): Ditto.
- (vuint8mf2x8_t): Ditto.
- (vint8m1x2_t): Ditto.
- (vuint8m1x2_t): Ditto.
- (vint8m1x3_t): Ditto.
- (vuint8m1x3_t): Ditto.
- (vint8m1x4_t): Ditto.
- (vuint8m1x4_t): Ditto.
- (vint8m1x5_t): Ditto.
- (vuint8m1x5_t): Ditto.
- (vint8m1x6_t): Ditto.
- (vuint8m1x6_t): Ditto.
- (vint8m1x7_t): Ditto.
- (vuint8m1x7_t): Ditto.
- (vint8m1x8_t): Ditto.
- (vuint8m1x8_t): Ditto.
- (vint8m2x2_t): Ditto.
- (vuint8m2x2_t): Ditto.
- (vint8m2x3_t): Ditto.
- (vuint8m2x3_t): Ditto.
- (vint8m2x4_t): Ditto.
- (vuint8m2x4_t): Ditto.
- (vint8m4x2_t): Ditto.
- (vuint8m4x2_t): Ditto.
- (vint16mf4x2_t): Ditto.
- (vuint16mf4x2_t): Ditto.
- (vint16mf4x3_t): Ditto.
- (vuint16mf4x3_t): Ditto.
- (vint16mf4x4_t): Ditto.
- (vuint16mf4x4_t): Ditto.
- (vint16mf4x5_t): Ditto.
- (vuint16mf4x5_t): Ditto.
- (vint16mf4x6_t): Ditto.
- (vuint16mf4x6_t): Ditto.
- (vint16mf4x7_t): Ditto.
- (vuint16mf4x7_t): Ditto.
- (vint16mf4x8_t): Ditto.
- (vuint16mf4x8_t): Ditto.
- (vint16mf2x2_t): Ditto.
- (vuint16mf2x2_t): Ditto.
- (vint16mf2x3_t): Ditto.
- (vuint16mf2x3_t): Ditto.
- (vint16mf2x4_t): Ditto.
- (vuint16mf2x4_t): Ditto.
- (vint16mf2x5_t): Ditto.
- (vuint16mf2x5_t): Ditto.
- (vint16mf2x6_t): Ditto.
- (vuint16mf2x6_t): Ditto.
- (vint16mf2x7_t): Ditto.
- (vuint16mf2x7_t): Ditto.
- (vint16mf2x8_t): Ditto.
- (vuint16mf2x8_t): Ditto.
- (vint16m1x2_t): Ditto.
- (vuint16m1x2_t): Ditto.
- (vint16m1x3_t): Ditto.
- (vuint16m1x3_t): Ditto.
- (vint16m1x4_t): Ditto.
- (vuint16m1x4_t): Ditto.
- (vint16m1x5_t): Ditto.
- (vuint16m1x5_t): Ditto.
- (vint16m1x6_t): Ditto.
- (vuint16m1x6_t): Ditto.
- (vint16m1x7_t): Ditto.
- (vuint16m1x7_t): Ditto.
- (vint16m1x8_t): Ditto.
- (vuint16m1x8_t): Ditto.
- (vint16m2x2_t): Ditto.
- (vuint16m2x2_t): Ditto.
- (vint16m2x3_t): Ditto.
- (vuint16m2x3_t): Ditto.
- (vint16m2x4_t): Ditto.
- (vuint16m2x4_t): Ditto.
- (vint16m4x2_t): Ditto.
- (vuint16m4x2_t): Ditto.
- (vint32mf2x2_t): Ditto.
- (vuint32mf2x2_t): Ditto.
- (vint32mf2x3_t): Ditto.
- (vuint32mf2x3_t): Ditto.
- (vint32mf2x4_t): Ditto.
- (vuint32mf2x4_t): Ditto.
- (vint32mf2x5_t): Ditto.
- (vuint32mf2x5_t): Ditto.
- (vint32mf2x6_t): Ditto.
- (vuint32mf2x6_t): Ditto.
- (vint32mf2x7_t): Ditto.
- (vuint32mf2x7_t): Ditto.
- (vint32mf2x8_t): Ditto.
- (vuint32mf2x8_t): Ditto.
- (vint32m1x2_t): Ditto.
- (vuint32m1x2_t): Ditto.
- (vint32m1x3_t): Ditto.
- (vuint32m1x3_t): Ditto.
- (vint32m1x4_t): Ditto.
- (vuint32m1x4_t): Ditto.
- (vint32m1x5_t): Ditto.
- (vuint32m1x5_t): Ditto.
- (vint32m1x6_t): Ditto.
- (vuint32m1x6_t): Ditto.
- (vint32m1x7_t): Ditto.
- (vuint32m1x7_t): Ditto.
- (vint32m1x8_t): Ditto.
- (vuint32m1x8_t): Ditto.
- (vint32m2x2_t): Ditto.
- (vuint32m2x2_t): Ditto.
- (vint32m2x3_t): Ditto.
- (vuint32m2x3_t): Ditto.
- (vint32m2x4_t): Ditto.
- (vuint32m2x4_t): Ditto.
- (vint32m4x2_t): Ditto.
- (vuint32m4x2_t): Ditto.
- (vint64m1x2_t): Ditto.
- (vuint64m1x2_t): Ditto.
- (vint64m1x3_t): Ditto.
- (vuint64m1x3_t): Ditto.
- (vint64m1x4_t): Ditto.
- (vuint64m1x4_t): Ditto.
- (vint64m1x5_t): Ditto.
- (vuint64m1x5_t): Ditto.
- (vint64m1x6_t): Ditto.
- (vuint64m1x6_t): Ditto.
- (vint64m1x7_t): Ditto.
- (vuint64m1x7_t): Ditto.
- (vint64m1x8_t): Ditto.
- (vuint64m1x8_t): Ditto.
- (vint64m2x2_t): Ditto.
- (vuint64m2x2_t): Ditto.
- (vint64m2x3_t): Ditto.
- (vuint64m2x3_t): Ditto.
- (vint64m2x4_t): Ditto.
- (vuint64m2x4_t): Ditto.
- (vint64m4x2_t): Ditto.
- (vuint64m4x2_t): Ditto.
- (vfloat32mf2x2_t): Ditto.
- (vfloat32mf2x3_t): Ditto.
- (vfloat32mf2x4_t): Ditto.
- (vfloat32mf2x5_t): Ditto.
- (vfloat32mf2x6_t): Ditto.
- (vfloat32mf2x7_t): Ditto.
- (vfloat32mf2x8_t): Ditto.
- (vfloat32m1x2_t): Ditto.
- (vfloat32m1x3_t): Ditto.
- (vfloat32m1x4_t): Ditto.
- (vfloat32m1x5_t): Ditto.
- (vfloat32m1x6_t): Ditto.
- (vfloat32m1x7_t): Ditto.
- (vfloat32m1x8_t): Ditto.
- (vfloat32m2x2_t): Ditto.
- (vfloat32m2x3_t): Ditto.
- (vfloat32m2x4_t): Ditto.
- (vfloat32m4x2_t): Ditto.
- (vfloat64m1x2_t): Ditto.
- (vfloat64m1x3_t): Ditto.
- (vfloat64m1x4_t): Ditto.
- (vfloat64m1x5_t): Ditto.
- (vfloat64m1x6_t): Ditto.
- (vfloat64m1x7_t): Ditto.
- (vfloat64m1x8_t): Ditto.
- (vfloat64m2x2_t): Ditto.
- (vfloat64m2x3_t): Ditto.
- (vfloat64m2x4_t): Ditto.
- (vfloat64m4x2_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TUPLE_OPS):
- Ditto.
- (DEF_RVV_TYPE_INDEX): Ditto.
- (rvv_arg_type_info::get_tuple_subpart_type): New function.
- (DEF_RVV_TUPLE_TYPE): New macro.
- * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE_INDEX):
- Adapt for tuple vget/vset support.
- (vint8mf4_t): Ditto.
- (vuint8mf4_t): Ditto.
- (vint8mf2_t): Ditto.
- (vuint8mf2_t): Ditto.
- (vint8m1_t): Ditto.
- (vuint8m1_t): Ditto.
- (vint8m2_t): Ditto.
- (vuint8m2_t): Ditto.
- (vint8m4_t): Ditto.
- (vuint8m4_t): Ditto.
- (vint8m8_t): Ditto.
- (vuint8m8_t): Ditto.
- (vint16mf4_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vuint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vuint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vuint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vuint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vuint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vuint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vuint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vuint32m8_t): Ditto.
- (vint64m1_t): Ditto.
- (vuint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vuint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vuint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint64m8_t): Ditto.
- (vfloat32mf2_t): Ditto.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat32m8_t): Ditto.
- (vfloat64m1_t): Ditto.
- (vfloat64m2_t): Ditto.
- (vfloat64m4_t): Ditto.
- (vfloat64m8_t): Ditto.
- (tuple_subpart): Add tuple subpart base type.
- * config/riscv/riscv-vector-builtins.h (struct
- rvv_arg_type_info): Ditto.
- (tuple_type_field): New function.
-
-2023-05-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro.
- (RVV_TUPLE_PARTIAL_MODES): Ditto.
- * config/riscv/riscv-protos.h (riscv_v_ext_tuple_mode_p): New
- function.
- (get_nf): Ditto.
- (get_subpart_mode): Ditto.
- (get_tuple_mode): Ditto.
- (expand_tuple_move): Ditto.
- * config/riscv/riscv-v.cc (ENTRY): New macro.
- (TUPLE_ENTRY): Ditto.
- (get_nf): New function.
- (get_subpart_mode): Ditto.
- (get_tuple_mode): Ditto.
- (expand_tuple_move): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TUPLE_TYPE):
- New macro.
- (register_tuple_type): New function
- * config/riscv/riscv-vector-builtins.def (DEF_RVV_TUPLE_TYPE):
- New macro.
- (vint8mf8x2_t): New macro.
- (vuint8mf8x2_t): Ditto.
- (vint8mf8x3_t): Ditto.
- (vuint8mf8x3_t): Ditto.
- (vint8mf8x4_t): Ditto.
- (vuint8mf8x4_t): Ditto.
- (vint8mf8x5_t): Ditto.
- (vuint8mf8x5_t): Ditto.
- (vint8mf8x6_t): Ditto.
- (vuint8mf8x6_t): Ditto.
- (vint8mf8x7_t): Ditto.
- (vuint8mf8x7_t): Ditto.
- (vint8mf8x8_t): Ditto.
- (vuint8mf8x8_t): Ditto.
- (vint8mf4x2_t): Ditto.
- (vuint8mf4x2_t): Ditto.
- (vint8mf4x3_t): Ditto.
- (vuint8mf4x3_t): Ditto.
- (vint8mf4x4_t): Ditto.
- (vuint8mf4x4_t): Ditto.
- (vint8mf4x5_t): Ditto.
- (vuint8mf4x5_t): Ditto.
- (vint8mf4x6_t): Ditto.
- (vuint8mf4x6_t): Ditto.
- (vint8mf4x7_t): Ditto.
- (vuint8mf4x7_t): Ditto.
- (vint8mf4x8_t): Ditto.
- (vuint8mf4x8_t): Ditto.
- (vint8mf2x2_t): Ditto.
- (vuint8mf2x2_t): Ditto.
- (vint8mf2x3_t): Ditto.
- (vuint8mf2x3_t): Ditto.
- (vint8mf2x4_t): Ditto.
- (vuint8mf2x4_t): Ditto.
- (vint8mf2x5_t): Ditto.
- (vuint8mf2x5_t): Ditto.
- (vint8mf2x6_t): Ditto.
- (vuint8mf2x6_t): Ditto.
- (vint8mf2x7_t): Ditto.
- (vuint8mf2x7_t): Ditto.
- (vint8mf2x8_t): Ditto.
- (vuint8mf2x8_t): Ditto.
- (vint8m1x2_t): Ditto.
- (vuint8m1x2_t): Ditto.
- (vint8m1x3_t): Ditto.
- (vuint8m1x3_t): Ditto.
- (vint8m1x4_t): Ditto.
- (vuint8m1x4_t): Ditto.
- (vint8m1x5_t): Ditto.
- (vuint8m1x5_t): Ditto.
- (vint8m1x6_t): Ditto.
- (vuint8m1x6_t): Ditto.
- (vint8m1x7_t): Ditto.
- (vuint8m1x7_t): Ditto.
- (vint8m1x8_t): Ditto.
- (vuint8m1x8_t): Ditto.
- (vint8m2x2_t): Ditto.
- (vuint8m2x2_t): Ditto.
- (vint8m2x3_t): Ditto.
- (vuint8m2x3_t): Ditto.
- (vint8m2x4_t): Ditto.
- (vuint8m2x4_t): Ditto.
- (vint8m4x2_t): Ditto.
- (vuint8m4x2_t): Ditto.
- (vint16mf4x2_t): Ditto.
- (vuint16mf4x2_t): Ditto.
- (vint16mf4x3_t): Ditto.
- (vuint16mf4x3_t): Ditto.
- (vint16mf4x4_t): Ditto.
- (vuint16mf4x4_t): Ditto.
- (vint16mf4x5_t): Ditto.
- (vuint16mf4x5_t): Ditto.
- (vint16mf4x6_t): Ditto.
- (vuint16mf4x6_t): Ditto.
- (vint16mf4x7_t): Ditto.
- (vuint16mf4x7_t): Ditto.
- (vint16mf4x8_t): Ditto.
- (vuint16mf4x8_t): Ditto.
- (vint16mf2x2_t): Ditto.
- (vuint16mf2x2_t): Ditto.
- (vint16mf2x3_t): Ditto.
- (vuint16mf2x3_t): Ditto.
- (vint16mf2x4_t): Ditto.
- (vuint16mf2x4_t): Ditto.
- (vint16mf2x5_t): Ditto.
- (vuint16mf2x5_t): Ditto.
- (vint16mf2x6_t): Ditto.
- (vuint16mf2x6_t): Ditto.
- (vint16mf2x7_t): Ditto.
- (vuint16mf2x7_t): Ditto.
- (vint16mf2x8_t): Ditto.
- (vuint16mf2x8_t): Ditto.
- (vint16m1x2_t): Ditto.
- (vuint16m1x2_t): Ditto.
- (vint16m1x3_t): Ditto.
- (vuint16m1x3_t): Ditto.
- (vint16m1x4_t): Ditto.
- (vuint16m1x4_t): Ditto.
- (vint16m1x5_t): Ditto.
- (vuint16m1x5_t): Ditto.
- (vint16m1x6_t): Ditto.
- (vuint16m1x6_t): Ditto.
- (vint16m1x7_t): Ditto.
- (vuint16m1x7_t): Ditto.
- (vint16m1x8_t): Ditto.
- (vuint16m1x8_t): Ditto.
- (vint16m2x2_t): Ditto.
- (vuint16m2x2_t): Ditto.
- (vint16m2x3_t): Ditto.
- (vuint16m2x3_t): Ditto.
- (vint16m2x4_t): Ditto.
- (vuint16m2x4_t): Ditto.
- (vint16m4x2_t): Ditto.
- (vuint16m4x2_t): Ditto.
- (vint32mf2x2_t): Ditto.
- (vuint32mf2x2_t): Ditto.
- (vint32mf2x3_t): Ditto.
- (vuint32mf2x3_t): Ditto.
- (vint32mf2x4_t): Ditto.
- (vuint32mf2x4_t): Ditto.
- (vint32mf2x5_t): Ditto.
- (vuint32mf2x5_t): Ditto.
- (vint32mf2x6_t): Ditto.
- (vuint32mf2x6_t): Ditto.
- (vint32mf2x7_t): Ditto.
- (vuint32mf2x7_t): Ditto.
- (vint32mf2x8_t): Ditto.
- (vuint32mf2x8_t): Ditto.
- (vint32m1x2_t): Ditto.
- (vuint32m1x2_t): Ditto.
- (vint32m1x3_t): Ditto.
- (vuint32m1x3_t): Ditto.
- (vint32m1x4_t): Ditto.
- (vuint32m1x4_t): Ditto.
- (vint32m1x5_t): Ditto.
- (vuint32m1x5_t): Ditto.
- (vint32m1x6_t): Ditto.
- (vuint32m1x6_t): Ditto.
- (vint32m1x7_t): Ditto.
- (vuint32m1x7_t): Ditto.
- (vint32m1x8_t): Ditto.
- (vuint32m1x8_t): Ditto.
- (vint32m2x2_t): Ditto.
- (vuint32m2x2_t): Ditto.
- (vint32m2x3_t): Ditto.
- (vuint32m2x3_t): Ditto.
- (vint32m2x4_t): Ditto.
- (vuint32m2x4_t): Ditto.
- (vint32m4x2_t): Ditto.
- (vuint32m4x2_t): Ditto.
- (vint64m1x2_t): Ditto.
- (vuint64m1x2_t): Ditto.
- (vint64m1x3_t): Ditto.
- (vuint64m1x3_t): Ditto.
- (vint64m1x4_t): Ditto.
- (vuint64m1x4_t): Ditto.
- (vint64m1x5_t): Ditto.
- (vuint64m1x5_t): Ditto.
- (vint64m1x6_t): Ditto.
- (vuint64m1x6_t): Ditto.
- (vint64m1x7_t): Ditto.
- (vuint64m1x7_t): Ditto.
- (vint64m1x8_t): Ditto.
- (vuint64m1x8_t): Ditto.
- (vint64m2x2_t): Ditto.
- (vuint64m2x2_t): Ditto.
- (vint64m2x3_t): Ditto.
- (vuint64m2x3_t): Ditto.
- (vint64m2x4_t): Ditto.
- (vuint64m2x4_t): Ditto.
- (vint64m4x2_t): Ditto.
- (vuint64m4x2_t): Ditto.
- (vfloat32mf2x2_t): Ditto.
- (vfloat32mf2x3_t): Ditto.
- (vfloat32mf2x4_t): Ditto.
- (vfloat32mf2x5_t): Ditto.
- (vfloat32mf2x6_t): Ditto.
- (vfloat32mf2x7_t): Ditto.
- (vfloat32mf2x8_t): Ditto.
- (vfloat32m1x2_t): Ditto.
- (vfloat32m1x3_t): Ditto.
- (vfloat32m1x4_t): Ditto.
- (vfloat32m1x5_t): Ditto.
- (vfloat32m1x6_t): Ditto.
- (vfloat32m1x7_t): Ditto.
- (vfloat32m1x8_t): Ditto.
- (vfloat32m2x2_t): Ditto.
- (vfloat32m2x3_t): Ditto.
- (vfloat32m2x4_t): Ditto.
- (vfloat32m4x2_t): Ditto.
- (vfloat64m1x2_t): Ditto.
- (vfloat64m1x3_t): Ditto.
- (vfloat64m1x4_t): Ditto.
- (vfloat64m1x5_t): Ditto.
- (vfloat64m1x6_t): Ditto.
- (vfloat64m1x7_t): Ditto.
- (vfloat64m1x8_t): Ditto.
- (vfloat64m2x2_t): Ditto.
- (vfloat64m2x3_t): Ditto.
- (vfloat64m2x4_t): Ditto.
- (vfloat64m4x2_t): Ditto.
- * config/riscv/riscv-vector-builtins.h (DEF_RVV_TUPLE_TYPE):
- Ditto.
- * config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): Ditto.
- * config/riscv/riscv.cc (riscv_v_ext_tuple_mode_p): New
- function.
- (TUPLE_ENTRY): Ditto.
- (riscv_v_ext_mode_p): New function.
- (riscv_v_adjust_nunits): Add tuple mode adjustment.
- (riscv_classify_address): Ditto.
- (riscv_binary_cost): Ditto.
- (riscv_rtx_costs): Ditto.
- (riscv_secondary_memory_needed): Ditto.
- (riscv_hard_regno_nregs): Ditto.
- (riscv_hard_regno_mode_ok): Ditto.
- (riscv_vector_mode_supported_p): Ditto.
- (riscv_regmode_natural_size): Ditto.
- (riscv_array_mode): New function.
- (TARGET_ARRAY_MODE): New target hook.
- * config/riscv/riscv.md: Add tuple modes.
- * config/riscv/vector-iterators.md: Ditto.
- * config/riscv/vector.md (mov<mode>): Add tuple modes data
- movement.
- (*mov<VT:mode>_<P:mode>): Ditto.
-
-2023-05-03 Richard Biener <rguenther@suse.de>
-
- * cse.cc (cse_insn): Track an equivalence to the destination
- separately and delay using src_related for it.
-
-2023-05-03 Richard Biener <rguenther@suse.de>
-
- * cse.cc (HASH): Turn into inline function and mix
- in another HASH_SHIFT bits.
- (SAFE_HASH): Likewise.
-
-2023-05-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_<sur>h<addsub><mode>): Rename to...
- (aarch64_<sur>h<addsub><mode><vczle><vczbe>): ... This.
-
-2023-05-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (add<mode>3): Rename to...
- (add<mode>3<vczle><vczbe>): ... This.
- (sub<mode>3): Rename to...
- (sub<mode>3<vczle><vczbe>): ... This.
- (mul<mode>3): Rename to...
- (mul<mode>3<vczle><vczbe>): ... This.
- (*div<mode>3): Rename to...
- (*div<mode>3<vczle><vczbe>): ... This.
- (neg<mode>2): Rename to...
- (neg<mode>2<vczle><vczbe>): ... This.
- (abs<mode>2): Rename to...
- (abs<mode>2<vczle><vczbe>): ... This.
- (<frint_pattern><mode>2): Rename to...
- (<frint_pattern><mode>2<vczle><vczbe>): ... This.
- (<fmaxmin><mode>3): Rename to...
- (<fmaxmin><mode>3<vczle><vczbe>): ... This.
- (*sqrt<mode>2): Rename to...
- (*sqrt<mode>2<vczle><vczbe>): ... This.
-
-2023-05-03 Kito Cheng <kito.cheng@sifive.com>
-
- * doc/md.texi (RISC-V): Add vr, vm, vd constarint.
-
-2023-05-03 Martin Liska <mliska@suse.cz>
-
- PR tree-optimization/109693
- * value-range-storage.cc (vrange_allocator::vrange_allocator):
- Remove unused field.
- * value-range-storage.h: Likewise.
-
-2023-05-02 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (move_stmt): New function.
- (match_simplify_replacement): Use move_stmt instead
- of the inlined version.
-
-2023-05-02 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (a != 0 ? CLRSB(a) : CST -> CLRSB(a)): New
- pattern.
+2024-02-14 Tamar Christina <tamar.christina@arm.com>
-2023-05-02 Andrew Pinski <apinski@marvell.com>
+ * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
- PR tree-optimization/109702
- * match.pd: Fix "a != 0 ? FUNC(a) : CST" patterns
- for FUNC of POPCOUNT BSWAP FFS PARITY CLZ and CTZ.
+2024-02-14 Richard Biener <rguenther@suse.de>
-2023-05-02 Andrew Pinski <apinski@marvell.com>
+ PR tree-optimization/113910
+ * bitmap.cc (bitmap_hash): Mix the full element "hash" to
+ the hashval_t hash.
- PR target/109657
- * config/aarch64/aarch64.md (*cmov<mode>_insn_m1): New
- insn_and_split pattern.
+2024-02-14 Jakub Jelinek <jakub@redhat.com>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
+ (pp_integer_with_precision): For unsigned ptrdiff_t printing
+ with u, o or x print ptrdiff_t argument converted to
+ unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
- * config/riscv/sync.md (atomic_load<mode>): Implement atomic
- load mapping.
+2024-02-14 Richard Biener <rguenther@suse.de>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ PR middle-end/113576
+ * expr.cc (do_store_flag): For vector bool compares of vectors
+ with padding zero that.
+ * dojump.cc (do_compare_and_jump): Likewise.
- * config/riscv/sync.md (mem_thread_fence_1): Change fence
- depending on the given memory model.
+2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ * doc/install.texi (Prerequisites): Update gettext link.
- * config/riscv/riscv-protos.h (riscv_union_memmodels): Expose
- riscv_union_memmodels function to sync.md.
- * config/riscv/riscv.cc (riscv_union_memmodels): Add function to
- get the union of two memmodels in sync.md.
- (riscv_print_operand): Add %I and %J flags that output the
- optimal LR/SC flag bits for a given memory model.
- * config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl
- bits on SC op and replace with optimized %I, %J flags.
+2024-02-13 H.J. Lu <hjl.tools@gmail.com>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ PR target/113876
+ * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
+ Return false if the incoming stack isn't 16-byte aligned.
- * config/riscv/riscv.cc
- (riscv_memmodel_needs_amo_release): Change function name.
- (riscv_print_operand): Remove unneeded %F case.
- * config/riscv/sync.md: Remove unneeded fences.
+2024-02-13 Tobias Burnus <tburnus@baylibre.com>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ PR middle-end/113904
+ * omp-general.cc (struct omp_ts_info): Update for splitting of
+ OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
+ * omp-selectors.h (enum omp_tp_type): Replace
+ OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
- PR target/89835
- * config/riscv/sync.md (atomic_store<mode>): Use simple store
- instruction in combination with fence(s).
+2024-02-13 Monk Chiang <monk.chiang@sifive.com>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ PR target/113742
+ * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
+ recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
- * config/riscv/riscv.cc (riscv_print_operand): Change behavior
- of %A to include release bits.
+2024-02-13 Richard Biener <rguenther@suse.de>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ PR tree-optimization/113895
+ * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
+ offset to discover constant array indices in bits, handle
+ COMPONENT_REF to bitfields.
- * config/riscv/sync.md (atomic_cas_value_strong<mode>): Change
- FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl
- pair.
+2024-02-13 Richard Biener <rguenther@suse.de>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ PR tree-optimization/113831
+ * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
+ typo in comment.
- * config/riscv/sync.md: Change LR.aq/SC.rl pairs into
- sequentially consistent LR.aqrl/SC.rl pairs.
+2024-02-13 Richard Biener <rguenther@suse.de>
-2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
+ PR tree-optimization/113902
+ * tree-vect-loop.cc (move_early_exit_stmts): Track
+ last_seen_vuse for VUSE updating.
- * config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
- sanitize memmodel input with memmodel_base.
+2024-02-13 Tamar Christina <tamar.christina@arm.com>
-2023-05-02 Yanzhang Wang <yanzhang.wang@intel.com>
- Pan Li <pan2.li@intel.com>
+ PR tree-optimization/113734
+ * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
+ an early break loop as partial.
- PR target/109617
- * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.
+2024-02-13 Richard Biener <rguenther@suse.de>
-2023-05-02 Romain Naour <romain.naour@gmail.com>
+ PR tree-optimization/113898
+ * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
+ missing accumulated off adjustment.
- * config/riscv/genrvv-type-indexer.cc: Use log2 from the C header, without
- the namespace.
+2024-02-13 Jakub Jelinek <jakub@redhat.com>
-2023-05-02 Martin Liska <mliska@suse.cz>
+ * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
+ instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
+ it against UINT_MAX and ULONG_MAX.
- * doc/invoke.texi: Update documentation based on param.opt file.
+2024-02-13 David Malcolm <dmalcolm@redhat.com>
-2023-05-02 Richard Biener <rguenther@suse.de>
+ * diagnostic-core.h (emit_diagnostic_valist): Rename overload
+ to...
+ (emit_diagnostic_valist_meta): ...this.
+ * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
+ (emit_diagnostic_valist_meta): ...this.
- PR tree-optimization/109672
- * tree-vect-stmts.cc (vectorizable_operation): For plus,
- minus and negate always check the vector mode is word mode.
+2024-02-12 Jakub Jelinek <jakub@redhat.com>
-2023-05-01 Andrew Pinski <apinski@marvell.com>
+ PR tree-optimization/113849
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
+ fast path for widening casts where !m_upwards_2limb and lhs_type
+ has precision which is a multiple of limb_prec.
- * tree-ssa-phiopt.cc: Update comment about
- how the transformation are implemented.
+2024-02-12 Jakub Jelinek <jakub@redhat.com>
-2023-05-01 Jeff Law <jlaw@ventanamicro>
+ PR c++/113674
+ * attribs.cc (extract_attribute_substring): Remove.
+ (lookup_scoped_attribute_spec): Don't call it.
- * config/stormy16/stormy16.cc (TARGET_LRA_P): Remove defintion.
+2024-02-12 Jakub Jelinek <jakub@redhat.com>
-2023-05-01 Jeff Law <jlaw@ventanamicro>
+ * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
+ and cast to fmt_size_t instead of %lu and cast to unsigned long.
- * config/cris/cris.cc (TARGET_LRA_P): Remove.
- * config/epiphany/epiphany.cc (TARGET_LRA_P): Remove.
- * config/iq2000/iq2000.cc (TARGET_LRA_P): Remove.
- * config/m32r/m32r.cc (TARGET_LRA_P): Remove.
- * config/microblaze/microblaze.cc (TARGET_LRA_P): Remove.
- * config/mmix/mmix.cc (TARGET_LRA_P): Remove.
-
-2023-05-01 Rasmus Villemoes <rasmus.villemoes@prevas.dk>
-
- * print-tree.h (PRINT_DECL_REMAP_DEBUG): New flag.
- * print-tree.cc (print_decl_identifier): Implement it.
- * toplev.cc (output_stack_usage_1): Use it.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (class int_range): Remove gt_ggc_mx and gt_pch_nx
- friends.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (irange::set_nonzero): Inline.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * gimple-range-op.cc (cfn_ffs::fold_range): Use the correct
- precision.
- * gimple-ssa-warn-alloca.cc (alloca_call_type): Use <2> for
- invalid_range, as it is an inverse range.
- * tree-vrp.cc (find_case_label_range): Avoid trees.
- * value-range.cc (irange::irange_set): Delete.
- (irange::irange_set_1bit_anti_range): Delete.
- (irange::irange_set_anti_range): Delete.
- (irange::set): Cleanup.
- * value-range.h (class irange): Remove irange_set,
- irange_set_anti_range, irange_set_1bit_anti_range.
- (irange::set_undefined): Remove set to m_type.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op.cc (update_known_bitmask): Adjust for irange containing
- wide_ints internally.
- * tree-ssanames.cc (set_nonzero_bits): Same.
- * tree-ssanames.h (set_nonzero_bits): Same.
- * value-range-storage.cc (irange_storage::set_irange): Same.
- (irange_storage::get_irange): Same.
- * value-range.cc (irange::operator=): Same.
- (irange::irange_set): Same.
- (irange::irange_set_1bit_anti_range): Same.
- (irange::irange_set_anti_range): Same.
- (irange::set): Same.
- (irange::verify_range): Same.
- (irange::contains_p): Same.
- (irange::irange_single_pair_union): Same.
- (irange::union_): Same.
- (irange::irange_contains_p): Same.
- (irange::intersect): Same.
- (irange::invert): Same.
- (irange::set_range_from_nonzero_bits): Same.
- (irange::set_nonzero_bits): Same.
- (mask_to_wi): Same.
- (irange::intersect_nonzero_bits): Same.
- (irange::union_nonzero_bits): Same.
- (gt_ggc_mx): Same.
- (gt_pch_nx): Same.
- (tree_range): Same.
- (range_tests_strict_enum): Same.
- (range_tests_misc): Same.
- (range_tests_nonzero_bits): Same.
- * value-range.h (irange::type): Same.
- (irange::varying_compatible_p): Same.
- (irange::irange): Same.
- (int_range::int_range): Same.
- (irange::set_undefined): Same.
- (irange::set_varying): Same.
- (irange::lower_bound): Same.
- (irange::upper_bound): Same.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * gimple-range-fold.cc (tree_lower_bound): Delete.
- (tree_upper_bound): Delete.
- (vrp_val_max): Delete.
- (vrp_val_min): Delete.
- (fold_using_range::range_of_ssa_name_with_loop_info): Call
- range_of_var_in_loop.
- * vr-values.cc (valid_value_p): Delete.
- (fix_overflow): Delete.
- (get_scev_info): New.
- (bounds_of_var_in_loop): Refactor into...
- (induction_variable_may_overflow_p): ...this,
- (range_from_loop_direction): ...and this,
- (range_of_var_in_loop): ...and this.
- * vr-values.h (bounds_of_var_in_loop): Delete.
- (range_of_var_in_loop): New.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * gimple-range-fold.cc (adjust_pointer_diff_expr): Rewrite with
- irange_val*.
- (vrp_val_max): New.
- (vrp_val_min): New.
- * gimple-range-op.cc (cfn_strlen::fold_range): Use irange_val_*.
- * range-op.cc (max_limit): Same.
- (min_limit): Same.
- (plus_minus_ranges): Same.
- (operator_rshift::op1_range): Same.
- (operator_cast::inside_domain_p): Same.
- * value-range.cc (vrp_val_is_max): Delete.
- (vrp_val_is_min): Delete.
- (range_tests_misc): Use irange_val_*.
- * value-range.h (vrp_val_is_min): Delete.
- (vrp_val_is_max): Delete.
- (vrp_val_max): Delete.
- (irange_val_min): New.
- (vrp_val_min): Delete.
- (irange_val_max): New.
- * vr-values.cc (check_for_binary_op_overflow): Use irange_val_*.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * fold-const.cc (expr_not_equal_to): Convert to irange wide_int API.
- * gimple-fold.cc (size_must_be_zero_p): Same.
- * gimple-loop-versioning.cc
- (loop_versioning::prune_loop_conditions): Same.
- * gimple-range-edge.cc (gcond_edge_range): Same.
- (gimple_outgoing_range::calc_switch_ranges): Same.
- * gimple-range-fold.cc (adjust_imagpart_expr): Same.
- (adjust_realpart_expr): Same.
- (fold_using_range::range_of_address): Same.
- (fold_using_range::relation_fold_and_or): Same.
- * gimple-range-gori.cc (gori_compute::gori_compute): Same.
- (range_is_either_true_or_false): Same.
- * gimple-range-op.cc (cfn_toupper_tolower::get_letter_range): Same.
- (cfn_clz::fold_range): Same.
- (cfn_ctz::fold_range): Same.
- * gimple-range-tests.cc (class test_expr_eval): Same.
- * gimple-ssa-warn-alloca.cc (alloca_call_type): Same.
- * ipa-cp.cc (ipa_value_range_from_jfunc): Same.
- (propagate_vr_across_jump_function): Same.
- (decide_whether_version_node): Same.
- * ipa-prop.cc (ipa_get_value_range): Same.
- * ipa-prop.h (ipa_range_set_and_normalize): Same.
- * range-op.cc (get_shift_range): Same.
- (value_range_from_overflowed_bounds): Same.
- (value_range_with_overflow): Same.
- (create_possibly_reversed_range): Same.
- (equal_op1_op2_relation): Same.
- (not_equal_op1_op2_relation): Same.
- (lt_op1_op2_relation): Same.
- (le_op1_op2_relation): Same.
- (gt_op1_op2_relation): Same.
- (ge_op1_op2_relation): Same.
- (operator_mult::op1_range): Same.
- (operator_exact_divide::op1_range): Same.
- (operator_lshift::op1_range): Same.
- (operator_rshift::op1_range): Same.
- (operator_cast::op1_range): Same.
- (operator_logical_and::fold_range): Same.
- (set_nonzero_range_from_mask): Same.
- (operator_bitwise_or::op1_range): Same.
- (operator_bitwise_xor::op1_range): Same.
- (operator_addr_expr::fold_range): Same.
- (pointer_plus_operator::wi_fold): Same.
- (pointer_or_operator::op1_range): Same.
- (INT): Same.
- (UINT): Same.
- (INT16): Same.
- (UINT16): Same.
- (SCHAR): Same.
- (UCHAR): Same.
- (range_op_cast_tests): Same.
- (range_op_lshift_tests): Same.
- (range_op_rshift_tests): Same.
- (range_op_bitwise_and_tests): Same.
- (range_relational_tests): Same.
- * range.cc (range_zero): Same.
- (range_nonzero): Same.
- * range.h (range_true): Same.
- (range_false): Same.
- (range_true_and_false): Same.
- * tree-data-ref.cc (split_constant_offset_1): Same.
- * tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Same.
- * tree-ssa-loop-unswitch.cc (struct unswitch_predicate): Same.
- (find_unswitching_predicates_for_bb): Same.
- * tree-ssa-phiopt.cc (value_replacement): Same.
- * tree-ssa-threadbackward.cc
- (back_threader::find_taken_edge_cond): Same.
- * tree-ssanames.cc (ssa_name_has_boolean_range): Same.
- * tree-vrp.cc (find_case_label_range): Same.
- * value-query.cc (range_query::get_tree_range): Same.
- * value-range.cc (irange::set_nonnegative): Same.
- (frange::contains_p): Same.
- (frange::singleton_p): Same.
- (frange::internal_singleton_p): Same.
- (irange::irange_set): Same.
- (irange::irange_set_1bit_anti_range): Same.
- (irange::irange_set_anti_range): Same.
- (irange::set): Same.
- (irange::operator==): Same.
- (irange::singleton_p): Same.
- (irange::contains_p): Same.
- (irange::set_range_from_nonzero_bits): Same.
- (DEFINE_INT_RANGE_INSTANCE): Same.
- (INT): Same.
- (UINT): Same.
- (SCHAR): Same.
- (UINT128): Same.
- (UCHAR): Same.
- (range): New.
- (tree_range): New.
- (range_int): New.
- (range_uint): New.
- (range_uint128): New.
- (range_uchar): New.
- (range_char): New.
- (build_range3): Convert to irange wide_int API.
- (range_tests_irange3): Same.
- (range_tests_int_range_max): Same.
- (range_tests_strict_enum): Same.
- (range_tests_misc): Same.
- (range_tests_nonzero_bits): Same.
- (range_tests_nan): Same.
- (range_tests_signed_zeros): Same.
- * value-range.h (Value_Range::Value_Range): Same.
- (irange::set): Same.
- (irange::nonzero_p): Same.
- (irange::contains_p): Same.
- (range_includes_zero_p): Same.
- (irange::set_nonzero): Same.
- (irange::set_zero): Same.
- (contains_zero_p): Same.
- (frange::contains_p): Same.
- * vr-values.cc
- (simplify_using_ranges::op_with_boolean_value_range_p): Same.
- (bounds_of_var_in_loop): Same.
- (simplify_using_ranges::legacy_fold_cond_overflow): Same.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (irange::irange_union): Rename to...
- (irange::union_): ...this.
- (irange::irange_intersect): Rename to...
- (irange::intersect): ...this.
- * value-range.h (irange::union_): Delete.
- (irange::intersect): Delete.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * vr-values.cc (bounds_of_var_in_loop): Convert to irange API.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * vr-values.cc (check_for_binary_op_overflow): Tidy up by using
- ranger API.
- (compare_ranges): Delete.
- (compare_range_with_value): Delete.
- (bounds_of_var_in_loop): Tidy up by using ranger API.
- (simplify_using_ranges::fold_cond_with_ops): Cleanup and rename
- from vrp_evaluate_conditional_warnv_with_ops_using_ranges.
- (simplify_using_ranges::legacy_fold_cond_overflow): Remove
- strict_overflow_p and only_ranges.
- (simplify_using_ranges::legacy_fold_cond): Adjust call to
- legacy_fold_cond_overflow.
- (simplify_using_ranges::simplify_abs_using_ranges): Adjust for
- rename.
- (range_fits_type_p): Rename value_range to irange.
- * vr-values.h (range_fits_type_p): Adjust prototype.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (irange::irange_set_anti_range): Remove uses of
- tree_lower_bound and tree_upper_bound.
- (irange::verify_range): Same.
- (irange::operator==): Same.
- (irange::singleton_p): Same.
- * value-range.h (irange::tree_lower_bound): Delete.
- (irange::tree_upper_bound): Delete.
- (irange::lower_bound): Delete.
- (irange::upper_bound): Delete.
- (irange::zero_p): Remove uses of tree_lower_bound and
- tree_upper_bound.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-ssa-loop-niter.cc (refine_value_range_using_guard): Remove
- kind() call.
- (determine_value_range): Same.
- (record_nonwrapping_iv): Same.
- (infer_loop_bounds_from_signedness): Same.
- (scev_var_range_cant_overflow): Same.
- * tree-vrp.cc (operand_less_p): Delete.
- * tree-vrp.h (operand_less_p): Delete.
- * value-range.cc (get_legacy_range): Remove uses of deprecated API.
- (irange::value_inside_range): Delete.
- * value-range.h (vrange::kind): Delete.
- (irange::num_pairs): Remove check of m_kind.
- (irange::min): Delete.
- (irange::max): Delete.
-
-2023-05-01 Aldy Hernandez <aldyh@redhat.com>
-
- * gimple-fold.cc (maybe_fold_comparisons_from_match_pd): Adjust
- for vrange_storage.
- * gimple-range-cache.cc (sbr_vector::sbr_vector): Same.
- (sbr_vector::grow): Same.
- (sbr_vector::set_bb_range): Same.
- (sbr_vector::get_bb_range): Same.
- (sbr_sparse_bitmap::sbr_sparse_bitmap): Same.
- (sbr_sparse_bitmap::set_bb_range): Same.
- (sbr_sparse_bitmap::get_bb_range): Same.
- (block_range_cache::block_range_cache): Same.
- (ssa_global_cache::ssa_global_cache): Same.
- (ssa_global_cache::get_global_range): Same.
- (ssa_global_cache::set_global_range): Same.
- * gimple-range-cache.h: Same.
- * gimple-range-edge.cc
- (gimple_outgoing_range::gimple_outgoing_range): Same.
- (gimple_outgoing_range::switch_edge_range): Same.
- (gimple_outgoing_range::calc_switch_ranges): Same.
- * gimple-range-edge.h: Same.
- * gimple-range-infer.cc
- (infer_range_manager::infer_range_manager): Same.
- (infer_range_manager::get_nonzero): Same.
- (infer_range_manager::maybe_adjust_range): Same.
- (infer_range_manager::add_range): Same.
- * gimple-range-infer.h: Rename obstack_vrange_allocator to
- vrange_allocator.
- * tree-core.h (struct irange_storage_slot): Remove.
- (struct tree_ssa_name): Remove irange_info and frange_info. Make
- range_info a pointer to vrange_storage.
- * tree-ssanames.cc (range_info_fits_p): Adjust for vrange_storage.
- (range_info_alloc): Same.
- (range_info_free): Same.
- (range_info_get_range): Same.
- (range_info_set_range): Same.
- (get_nonzero_bits): Same.
- * value-query.cc (get_ssa_name_range_info): Same.
- * value-range-storage.cc (class vrange_internal_alloc): New.
- (class vrange_obstack_alloc): New.
- (class vrange_ggc_alloc): New.
- (vrange_allocator::vrange_allocator): New.
- (vrange_allocator::~vrange_allocator): New.
- (vrange_storage::alloc_slot): New.
- (vrange_allocator::alloc): New.
- (vrange_allocator::free): New.
- (vrange_allocator::clone): New.
- (vrange_allocator::clone_varying): New.
- (vrange_allocator::clone_undefined): New.
- (vrange_storage::alloc): New.
- (vrange_storage::set_vrange): Remove slot argument.
- (vrange_storage::get_vrange): Same.
- (vrange_storage::fits_p): Same.
- (vrange_storage::equal_p): New.
- (irange_storage::write_lengths_address): New.
- (irange_storage::lengths_address): New.
- (irange_storage_slot::alloc_slot): Remove.
- (irange_storage::alloc): New.
- (irange_storage_slot::irange_storage_slot): Remove.
- (irange_storage::irange_storage): New.
- (write_wide_int): New.
- (irange_storage_slot::set_irange): Remove.
- (irange_storage::set_irange): New.
- (read_wide_int): New.
- (irange_storage_slot::get_irange): Remove.
- (irange_storage::get_irange): New.
- (irange_storage_slot::size): Remove.
- (irange_storage::equal_p): New.
- (irange_storage_slot::num_wide_ints_needed): Remove.
- (irange_storage::size): New.
- (irange_storage_slot::fits_p): Remove.
- (irange_storage::fits_p): New.
- (irange_storage_slot::dump): Remove.
- (irange_storage::dump): New.
- (frange_storage_slot::alloc_slot): Remove.
- (frange_storage::alloc): New.
- (frange_storage_slot::set_frange): Remove.
- (frange_storage::set_frange): New.
- (frange_storage_slot::get_frange): Remove.
- (frange_storage::get_frange): New.
- (frange_storage_slot::fits_p): Remove.
- (frange_storage::equal_p): New.
- (frange_storage::fits_p): New.
- (ggc_vrange_allocator): New.
- (ggc_alloc_vrange_storage): New.
- * value-range-storage.h (class vrange_storage): Rewrite.
- (class irange_storage): Rewrite.
- (class frange_storage): Rewrite.
- (class obstack_vrange_allocator): Remove.
- (class ggc_vrange_allocator): Remove.
- (vrange_allocator::alloc_vrange): Remove.
- (vrange_allocator::alloc_irange): Remove.
- (vrange_allocator::alloc_frange): Remove.
- (ggc_alloc_vrange_storage): New.
- * value-range.h (class irange): Rename vrange_allocator to
- irange_storage.
- (class frange): Same.
-
-2023-04-30 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/stormy16/stormy16.md (neghi2): Rewrite pattern using
- inc to avoid clobbering the carry flag.
-
-2023-04-30 Andrew Pinski <apinski@marvell.com>
-
- * match.pd: Add patterns for "a != 0 ? FUNC(a) : CST"
- for FUNC of POPCOUNT BSWAP FFS PARITY CLZ and CTZ.
-
-2023-04-30 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p):
- Allow some builtin/internal function calls which
- are known not to trap/throw.
- (phiopt_worker::match_simplify_replacement):
- Use name instead of getting the lhs again.
-
-2023-04-30 Joakim Nohlgård <joakim@nohlgard.se>
+2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
+ * Makefile.in: Add no-info dependency.
+ * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
+ available.
* configure: Regenerate.
- * configure.ac: Use ld -r in the check for HAVE_LD_RO_RW_SECTION_MIXING
-
-2023-04-29 Hans-Peter Nilsson <hp@axis.com>
-
- * reload1.cc (emit_insn_if_valid_for_reload_1): Rename from
- emit_insn_if_valid_for_reload.
- (emit_insn_if_valid_for_reload): Call new helper, and if a SET fails
- to be recognized, also try emitting a parallel that clobbers
- TARGET_FLAGS_REGNUM, as applicable.
-
-2023-04-29 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/stormy16/stormy16.md (neghi2): Convert from a define_expand
- to a define_insn.
- (*rotatehi_1): New define_insn for efficient 2 insn sequence.
- (*rotatehi_8, *rotaterthi_8): New define_insn to emit a swpb.
-
-2023-04-29 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/stormy16/stormy16.md (any_lshift): New code iterator.
- (any_or_plus): Likewise.
- (any_rotate): Likewise.
- (*<any_lshift>_and_internal): New define_insn_and_split to
- recognize a logical shift followed by an AND, and split it
- again after reload.
- (*swpn): New define_insn matching xstormy16's swpn.
- (*swpn_zext): New define_insn recognizing swpn followed by
- zero_extendqihi2, i.e. with the high byte set to zero.
- (*swpn_sext): Likewise, for swpn followed by cbw.
- (*swpn_sext_2): Likewise, for an alternate RTL form.
- (*swpn_zext_ior): A pre-reload splitter so that an swpn+zext+ior
- sequence is split in the correct place to recognize the *swpn_zext
- followed by any_or_plus (ior, xor or plus) instruction.
-
-2023-04-29 Mikael Pettersson <mikpelinux@gmail.com>
-
- PR target/105525
- * config.gcc (vax-*-linux*): Add glibc-stdint.h.
- (lm32-*-uclinux*): Likewise.
-
-2023-04-29 Fei Gao <gaofei@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_avoid_save_libcall): helper function
- for riscv_use_save_libcall.
- (riscv_use_save_libcall): call riscv_avoid_save_libcall.
- (riscv_compute_frame_info): restructure to decouple stack allocation
- for rv32e w/o save-restore.
-
-2023-04-28 Eugene Rozenfeld <erozen@microsoft.com>
-
- * doc/install.texi: Fix documentation typo
-
-2023-04-28 Matevos Mehrabyan <matevosmehrabyan@gmail.com>
-
- * config/riscv/iterators.md (only_div, paired_mod): New iterators.
- (u): Add div/udiv cases.
- * config/riscv/riscv-protos.h (riscv_use_divmod_expander): Prototype.
- * config/riscv/riscv.cc (struct riscv_tune_param): Add field for
- divmod expansion.
- (rocket_tune_info, sifive_7_tune_info): Initialize new field.
- (thead_c906_tune_info): Likewise.
- (optimize_size_tune_info): Likewise.
- (riscv_use_divmod_expander): New function.
- * config/riscv/riscv.md (<u>divmod<mode>4): New expander.
-
-2023-04-28 Karen Sargsyan <karen1999411@gmail.com>
-
- * config/riscv/bitmanip.md: Added clmulr instruction.
- * config/riscv/riscv-builtins.cc (AVAIL): Add new.
- * config/riscv/riscv.md: (UNSPEC_CLMULR): Add new unspec type.
- (type): Add clmul
- * config/riscv/riscv-cmo.def: Added built-in function for clmulr.
- * config/riscv/crypto.md: Move clmul[h] instructions to bitmanip.md.
- * config/riscv/riscv-scalar-crypto.def: Move clmul[h] built-in
- functions to riscv-cmo.def.
- * config/riscv/generic.md: Add clmul to list of instructions
- using the generic_imul reservation.
-
-2023-04-28 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * config/riscv/bitmanip.md: Added expanders for minu/maxu instructions
-
-2023-04-28 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/100958
- * tree-ssa-phiopt.cc (two_value_replacement): Remove.
- (pass_phiopt::execute): Don't call two_value_replacement.
- * match.pd (a !=/== CST1 ? CST2 : CST3): Add pattern to
- handle what two_value_replacement did.
-
-2023-04-28 Andrew Pinski <apinski@marvell.com>
-
- * match.pd: Add patterns for
- "(A CMP B) ? MIN/MAX<A, C> : MIN/MAX <B, C>".
-
-2023-04-28 Andrew Pinski <apinski@marvell.com>
-
- * match.pd: Factor out the deciding the min/max from
- the "(cond (cmp (convert1? x) c1) (convert2? x) c2)"
- pattern to ...
- * fold-const.cc (minmax_from_comparison): this new function.
- * fold-const.h (minmax_from_comparison): New prototype.
-
-2023-04-28 Roger Sayle <roger@nextmovesoftware.com>
-
- PR rtl-optimization/109476
- * lower-subreg.cc: Include explow.h for force_reg.
- (find_decomposable_shift_zext): Pass an additional SPEED_P argument.
- If decomposing a suitable LSHIFTRT and we're not splitting
- ZERO_EXTEND (based on the current SPEED_P), then use a ZERO_EXTEND
- instead of setting a high part SUBREG to zero, which helps combine.
- (decompose_multiword_subregs): Update call to resolve_shift_zext.
-
-2023-04-28 Richard Biener <rguenther@suse.de>
-
- * tree-vect-data-refs.cc (vect_analyze_data_refs): Always
- consider scatters.
- * tree-vect-stmts.cc (vect_model_store_cost): Pass in the
- gather-scatter info and cost emulated scatters accordingly.
- (get_load_store_type): Support emulated scatters.
- (vectorizable_store): Likewise. Emulate them by extracting
- scalar offsets and data, doing scalar stores.
-
-2023-04-28 Richard Biener <rguenther@suse.de>
-
- * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
- Tame down element extracts and scalar loads for gather/scatter
- similar to elementwise strided accesses.
-
-2023-04-28 Pan Li <pan2.li@intel.com>
- kito-cheng <kito.cheng@sifive.com>
-
- * config/riscv/vector.md: Add new define split to perform
- the simplification.
-
-2023-04-28 Richard Biener <rguenther@suse.de>
-
- PR ipa/109652
- * ipa-param-manipulation.cc
- (ipa_param_body_adjustments::modify_expression): Allow
- conversion of a register to a non-register type. Elide
- conversions inside BIT_FIELD_REFs.
-
-2023-04-28 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109644
- * tree-cfg.cc (verify_types_in_gimple_reference): Check
- register constraints on the outermost VIEW_CONVERT_EXPR
- only. Do not allow register or invariant bases on
- multi-level or possibly variable index handled components.
-
-2023-04-28 Richard Biener <rguenther@suse.de>
-
- * gimplify.cc (gimplify_compound_lval): When there's a
- non-register type produced by one of the handled component
- operations make sure we get a non-register base.
-
-2023-04-28 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108752
- * tree-vect-generic.cc (build_replicated_const): Rename
- to build_replicated_int_cst and move to tree.{h,cc}.
- (do_plus_minus): Adjust.
- (do_negate): Likewise.
- * tree-vect-stmts.cc (vectorizable_operation): Emit emulated
- arithmetic vector operations in lowered form.
- * tree.h (build_replicated_int_cst): Declare.
- * tree.cc (build_replicated_int_cst): Moved from
- tree-vect-generic.cc build_replicated_const.
-
-2023-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_rbit<mode>): Rename to...
- (aarch64_rbit<mode><vczle><vczbe>): ... This.
- (neg<mode>2): Rename to...
- (neg<mode>2<vczle><vczbe>): ... This.
- (abs<mode>2): Rename to...
- (abs<mode>2<vczle><vczbe>): ... This.
- (aarch64_abs<mode>): Rename to...
- (aarch64_abs<mode><vczle><vczbe>): ... This.
- (one_cmpl<mode>2): Rename to...
- (one_cmpl<mode>2<vczle><vczbe>): ... This.
- (clrsb<mode>2): Rename to...
- (clrsb<mode>2<vczle><vczbe>): ... This.
- (clz<mode>2): Rename to...
- (clz<mode>2<vczle><vczbe>): ... This.
- (popcount<mode>2): Rename to...
- (popcount<mode>2<vczle><vczbe>): ... This.
-
-2023-04-28 Jakub Jelinek <jakub@redhat.com>
-
- * gimple-range-op.cc (class cfn_sqrt): New type.
- (op_cfn_sqrt): New variable.
- (gimple_range_op_handler::maybe_builtin_call): Handle
- CASE_CFN_SQRT{,_FN}.
-
-2023-04-28 Aldy Hernandez <aldyh@redhat.com>
- Jakub Jelinek <jakub@redhat.com>
-
- * value-range.h (frange_nextafter): Declare.
- * gimple-range-op.cc (class cfn_sincos): New.
- (op_cfn_sin, op_cfn_cos): New variables.
- (gimple_range_op_handler::maybe_builtin_call): Handle
- CASE_CFN_{SIN,COS}{,_FN}.
-
-2023-04-28 Jakub Jelinek <jakub@redhat.com>
-
- * target.def (libm_function_max_error): New target hook.
- * doc/tm.texi.in (TARGET_LIBM_FUNCTION_MAX_ERROR): Add.
- * doc/tm.texi: Regenerated.
- * targhooks.h (default_libm_function_max_error,
- glibc_linux_libm_function_max_error): Declare.
- * targhooks.cc: Include case-cfn-macros.h.
- (default_libm_function_max_error,
- glibc_linux_libm_function_max_error): New functions.
- * config/linux.h (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
- * config/linux-protos.h (linux_libm_function_max_error): Declare.
- * config/linux.cc: Include target.h and targhooks.h.
- (linux_libm_function_max_error): New function.
- * config/arc/arc.cc: Include targhooks.h and case-cfn-macros.h.
- (arc_libm_function_max_error): New function.
- (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
- * config/i386/i386.cc (ix86_libc_has_fast_function): Formatting fix.
- (ix86_libm_function_max_error): New function.
- (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
- * config/rs6000/rs6000-protos.h
- (rs6000_linux_libm_function_max_error): Declare.
- * config/rs6000/rs6000-linux.cc: Include target.h, targhooks.h, tree.h
- and case-cfn-macros.h.
- (rs6000_linux_libm_function_max_error): New function.
- * config/rs6000/linux.h (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
- * config/rs6000/linux64.h (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
- * config/or1k/or1k.cc: Include targhooks.h and case-cfn-macros.h.
- (or1k_libm_function_max_error): New function.
- (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
-
-2023-04-28 Alexandre Oliva <oliva@adacore.com>
-
- * gimple-harden-conditionals.cc (insert_edge_check_and_trap):
- Move detach value calls...
- (pass_harden_conditional_branches::execute): ... here.
- (pass_harden_compares::execute): Detach values before
- compares.
-
-2023-04-27 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md (cmul<conj_op><mode>3): Use gcn_gen_undef.
- (cml<addsub_as><mode>4): Likewise.
- (vec_addsub<mode>3): Likewise.
- (cadd<rot><mode>3): Likewise.
- (vec_fmaddsub<mode>4): Likewise.
- (vec_fmsubadd<mode>4): Likewise, and use sub for the odd lanes.
-
-2023-04-27 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (phiopt_early_allow): Allow for
- up to 2 min/max expressions in the sequence/match code.
-
-2023-04-27 Andrew Pinski <apinski@marvell.com>
-
- * rtlanal.cc (may_trap_p_1): Treat SMIN/SMAX similar as
- COMPARISON.
- * tree-eh.cc (operation_could_trap_helper_p): Treate
- MIN_EXPR/MAX_EXPR similar as other comparisons.
-
-2023-04-27 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (cond_store_replacement): Remove
- prototype.
- (cond_if_else_store_replacement): Likewise.
- (get_non_trapping): Likewise.
- (store_elim_worker): Move into ...
- (pass_cselim::execute): This.
-
-2023-04-27 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (two_value_replacement): Remove
- prototype.
- (match_simplify_replacement): Likewise.
- (factor_out_conditional_conversion): Likewise.
- (value_replacement): Likewise.
- (minmax_replacement): Likewise.
- (spaceship_replacement): Likewise.
- (cond_removal_in_builtin_zero_pattern): Likewise.
- (hoist_adjacent_loads): Likewise.
- (tree_ssa_phiopt_worker): Move into ...
- (pass_phiopt::execute): this.
-
-2023-04-27 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Remove
- do_store_elim argument and split that part out to ...
- (store_elim_worker): This new function.
- (pass_cselim::execute): Call store_elim_worker.
- (pass_phiopt::execute): Update call to tree_ssa_phiopt_worker.
-
-2023-04-27 Jan Hubicka <jh@suse.cz>
-
- * cfgloopmanip.h (unloop_loops): Export.
- * tree-ssa-loop-ch.cc (ch_base::copy_headers): Unloop loops
- that no longer loop.
- * tree-ssa-loop-ivcanon.cc (unloop_loops): Export; do not free
- vectors of loops to unloop.
- (canonicalize_induction_variables): Free vectors here.
- (tree_unroll_loops_completely): Free vectors here.
-
-2023-04-27 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109170
- * gimple-range-op.cc (gimple_range_op_handler::maybe_builtin_call):
- Handle __builtin_expect and similar via cfn_pass_through_arg1
- and inspecting the calls fnspec.
- * builtins.cc (builtin_fnspec): Handle BUILT_IN_EXPECT
- and BUILT_IN_EXPECT_WITH_PROBABILITY.
-
-2023-04-27 Alexandre Oliva <oliva@adacore.com>
-
- * genmultilib: Use CONFIG_SHELL to run sub-scripts.
-
-2023-04-27 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/109639
- * ipa-cp.cc (ipa_value_range_from_jfunc): Normalize range.
- (propagate_vr_across_jump_function): Same.
- * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same.
- * ipa-prop.h (ipa_range_set_and_normalize): New.
- * value-range.cc (irange::set): Assert min and max are INTEGER_CST.
-
-2023-04-27 Richard Biener <rguenther@suse.de>
-
- * match.pd (BIT_FIELD_REF CONSTRUCTOR@0 @1 @2): Do not
- create a CTOR operand in the result when simplifying GIMPLE.
-
-2023-04-27 Richard Biener <rguenther@suse.de>
-
- * gimplify.cc (gimplify_compound_lval): When the base
- gimplified to a register make sure to split up chains
- of operations.
-
-2023-04-27 Richard Biener <rguenther@suse.de>
-
- PR ipa/109607
- * ipa-param-manipulation.h
- (ipa_param_body_adjustments::modify_expression): Add extra_stmts
- argument.
- * ipa-param-manipulation.cc
- (ipa_param_body_adjustments::modify_expression): Likewise.
- When we need a conversion and the replacement is a register
- split the conversion out.
- (ipa_param_body_adjustments::modify_assignment): Pass
- extra_stmts to RHS modify_expression.
-
-2023-04-27 Jonathan Wakely <jwakely@redhat.com>
-
- * doc/extend.texi (Zero Length): Describe example.
-
-2023-04-27 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109594
- * tree-ssa.cc (non_rewritable_mem_ref_base): Constrain
- what we rewrite to a register based on the above.
-
-2023-04-26 Patrick O'Neill <patrick@rivosinc.com>
-
- * config/riscv/riscv.cc: Fix whitespace.
- * config/riscv/sync.md: Fix whitespace.
-
-2023-04-26 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/108697
- * gimple-range-cache.cc (ssa_global_cache::clear_range): Do
- not clear the vector on an out of range query.
- (ssa_cache::dump): Use dump_range_query instead of get_range.
- (ssa_cache::dump_range_query): New.
- (ssa_lazy_cache::dump_range_query): New.
- (ssa_lazy_cache::set_range): New.
- * gimple-range-cache.h (ssa_cache::dump_range_query): New.
- (class ssa_lazy_cache): New.
- (ssa_lazy_cache::ssa_lazy_cache): New.
- (ssa_lazy_cache::~ssa_lazy_cache): New.
- (ssa_lazy_cache::get_range): New.
- (ssa_lazy_cache::clear_range): New.
- (ssa_lazy_cache::clear): New.
- (ssa_lazy_cache::dump): New.
- * gimple-range-path.cc (path_range_query::path_range_query): Do
- not allocate a ssa_cache object nor has_cache bitmap.
- (path_range_query::~path_range_query): Do not free objects.
- (path_range_query::clear_cache): Remove.
- (path_range_query::get_cache): Adjust.
- (path_range_query::set_cache): Remove.
- (path_range_query::dump): Don't call through a pointer.
- (path_range_query::internal_range_of_expr): Set cache directly.
- (path_range_query::reset_path): Clear cache directly.
- (path_range_query::ssa_range_in_phi): Fold with globals only.
- (path_range_query::compute_ranges_in_phis): Simply set range.
- (path_range_query::compute_ranges_in_block): Call cache directly.
- * gimple-range-path.h (class path_range_query): Replace bitmap
- and cache pointer with lazy cache object.
- * gimple-range.h (class assume_query): Use ssa_lazy_cache.
-
-2023-04-26 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-cache.cc (ssa_cache::ssa_cache): Rename.
- (ssa_cache::~ssa_cache): Rename.
- (ssa_cache::has_range): New.
- (ssa_cache::get_range): Rename.
- (ssa_cache::set_range): Rename.
- (ssa_cache::clear_range): Rename.
- (ssa_cache::clear): Rename.
- (ssa_cache::dump): Rename and use get_range.
- (ranger_cache::get_global_range): Use get_range and set_range.
- (ranger_cache::range_of_def): Use get_range.
- * gimple-range-cache.h (class ssa_cache): Rename class and methods.
- (class ranger_cache): Use ssa_cache.
- * gimple-range-path.cc (path_range_query::path_range_query): Use
- ssa_cache.
- (path_range_query::get_cache): Use get_range.
- (path_range_query::set_cache): Use set_range.
- * gimple-range-path.h (class path_range_query): Use ssa_cache.
- * gimple-range.cc (assume_query::assume_range_p): Use get_range.
- (assume_query::range_of_expr): Use get_range.
- (assume_query::assume_query): Use set_range.
- (assume_query::calculate_op): Use get_range and set_range.
- * gimple-range.h (class assume_query): Use ssa_cache.
-
-2023-04-26 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-cache.cc (sbr_vector::sbr_vector): Add parameter
- and local to optionally zero memory.
- (br_vector::grow): Only zero memory if flag is set.
- (class sbr_lazy_vector): New.
- (sbr_lazy_vector::sbr_lazy_vector): New.
- (sbr_lazy_vector::set_bb_range): New.
- (sbr_lazy_vector::get_bb_range): New.
- (sbr_lazy_vector::bb_range_p): New.
- (block_range_cache::set_bb_range): Check flags and Use sbr_lazy_vector.
- * gimple-range-gori.cc (gori_map::calculate_gori): Use
- param_vrp_switch_limit.
- (gori_compute::gori_compute): Use param_vrp_switch_limit.
- * params.opt (vrp_sparse_threshold): Rename from evrp_sparse_threshold.
- (vrp_switch_limit): Rename from evrp_switch_limit.
- (vrp_vector_threshold): New.
-
-2023-04-26 Andrew MacLeod <amacleod@redhat.com>
-
- * value-relation.cc (dom_oracle::query_relation): Check early for lack
- of any relation.
- * value-relation.h (equiv_oracle::has_equiv_p): New.
-
-2023-04-26 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109417
- * gimple-range-gori.cc (range_def_chain::register_dependency):
- Save the ssa version number, not the pointer.
- (gori_compute::may_recompute_p): No need to check if a dependency
- is in the free list.
- * gimple-range-gori.h (class range_def_chain): Change ssa1 and ssa2
- fields to be unsigned int instead of trees.
- (ange_def_chain::depend1): Adjust.
- (ange_def_chain::depend2): Adjust.
- * gimple-range.h: Include "ssa.h" to inline ssa_name().
-
-2023-04-26 David Edelsohn <dje.gcc@gmail.com>
-
- * config/rs6000/aix72.h (TARGET_DEFAULT): Use ISA_2_6_MASKS_SERVER.
- * config/rs6000/aix73.h (TARGET_DEFAULT): Use ISA_2_7_MASKS_SERVER.
- (PROCESSOR_DEFAULT): Use PROCESSOR_POWER8.
-
-2023-04-26 Patrick O'Neill <patrick@rivosinc.com>
-
- PR target/104338
- * config/riscv/riscv-protos.h: Add helper function stubs.
- * config/riscv/riscv.cc: Add helper functions for subword masking.
- * config/riscv/riscv.opt: Add command-line flags -minline-atomics and
- -mno-inline-atomics.
- * config/riscv/sync.md: Add masking logic and inline asm for fetch_and_op,
- fetch_and_nand, CAS, and exchange ops.
- * doc/invoke.texi: Add blurb regarding new command-line flags
- -minline-atomics and -mno-inline-atomics.
-
-2023-04-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_rshrn2<mode>_insn_le):
- Reimplement using standard RTL codes instead of unspec.
- (aarch64_rshrn2<mode>_insn_be): Likewise.
- (aarch64_rshrn2<mode>): Adjust for the above.
- * config/aarch64/aarch64.md (UNSPEC_RSHRN): Delete.
-
-2023-04-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_rshrn<mode>_insn_le): Reimplement
- with standard RTL codes instead of an UNSPEC.
- (aarch64_rshrn<mode>_insn_be): Likewise.
- (aarch64_rshrn<mode>): Adjust for the above.
- * config/aarch64/predicates.md (aarch64_simd_rshrn_imm_vec): Define.
-
-2023-04-26 Pan Li <pan2.li@intel.com>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_classify_address): Allow
- const0_rtx for the RVV load/store.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op.cc (range_op_cast_tests): Remove legacy support.
- * value-range-storage.h (vrange_allocator::alloc_irange): Same.
- * value-range.cc (irange::operator=): Same.
- (get_legacy_range): Same.
- (irange::copy_legacy_to_multi_range): Delete.
- (irange::copy_to_legacy): Delete.
- (irange::irange_set_anti_range): Delete.
- (irange::set): Remove legacy support.
- (irange::verify_range): Same.
- (irange::legacy_lower_bound): Delete.
- (irange::legacy_upper_bound): Delete.
- (irange::legacy_equal_p): Delete.
- (irange::operator==): Remove legacy support.
- (irange::singleton_p): Same.
- (irange::value_inside_range): Same.
- (irange::contains_p): Same.
- (intersect_ranges): Delete.
- (irange::legacy_intersect): Delete.
- (union_ranges): Delete.
- (irange::legacy_union): Delete.
- (irange::legacy_verbose_union_): Delete.
- (irange::legacy_verbose_intersect): Delete.
- (irange::irange_union): Remove legacy support.
- (irange::irange_intersect): Same.
- (irange::intersect): Same.
- (irange::invert): Same.
- (ranges_from_anti_range): Delete.
- (gt_pch_nx): Adjust for legacy removal.
- (gt_ggc_mx): Same.
- (range_tests_legacy): Delete.
- (range_tests_misc): Adjust for legacy removal.
- (range_tests): Same.
- * value-range.h (class irange): Same.
- (irange::legacy_mode_p): Delete.
- (ranges_from_anti_range): Delete.
- (irange::nonzero_p): Adjust for legacy removal.
- (irange::lower_bound): Same.
- (irange::upper_bound): Same.
- (irange::union_): Same.
- (irange::intersect): Same.
- (irange::set_nonzero): Same.
- (irange::set_zero): Same.
- * vr-values.cc (simplify_using_ranges::legacy_fold_cond_overflow): Same.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (irange::copy_legacy_to_multi_range): Rewrite use
- of range_has_numeric_bounds_p with irange API.
- (range_has_numeric_bounds_p): Delete.
- * value-range.h (range_has_numeric_bounds_p): Delete.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-data-ref.cc (compute_distributive_range): Replace uses of
- range_int_cst_p with irange API.
- * tree-ssa-strlen.cc (get_range_strlen_dynamic): Same.
- * tree-vrp.h (range_int_cst_p): Delete.
- * vr-values.cc (check_for_binary_op_overflow): Replace usees of
- range_int_cst_p with irange API.
- (vr_set_zero_nonzero_bits): Same.
- (range_fits_type_p): Same.
- (simplify_using_ranges::simplify_casted_cond): Same.
- * tree-vrp.cc (range_int_cst_p): Remove.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-ssa-strlen.cc (compare_nonzero_chars): Convert to wide_ints.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * builtins.cc (expand_builtin_strnlen): Rewrite deprecated irange
- API uses to new API.
- * gimple-predicate-analysis.cc (find_var_cmp_const): Same.
- * internal-fn.cc (get_min_precision): Same.
- * match.pd: Same.
- * tree-affine.cc (expr_to_aff_combination): Same.
- * tree-data-ref.cc (dr_step_indicator): Same.
- * tree-dfa.cc (get_ref_base_and_extent): Same.
- * tree-scalar-evolution.cc (iv_can_overflow_p): Same.
- * tree-ssa-phiopt.cc (two_value_replacement): Same.
- * tree-ssa-pre.cc (insert_into_preds_of_block): Same.
- * tree-ssa-reassoc.cc (optimize_range_tests_to_bit_test): Same.
- * tree-ssa-strlen.cc (compare_nonzero_chars): Same.
- * tree-switch-conversion.cc (bit_test_cluster::emit): Same.
- * tree-vect-patterns.cc (vect_recog_divmod_pattern): Same.
- * tree.cc (get_range_pos_neg): Same.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-prop.cc (ipa_print_node_jump_functions_for_edge): Use
- vrange::dump instead of ad-hoc dumper.
- * tree-ssa-strlen.cc (dump_strlen_info): Same.
- * value-range-pretty-print.cc (visit): Pass TDF_NOUID to
- dump_generic_node.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op.cc (operator_cast::op1_range): Use
- create_possibly_reversed_range.
- (operator_bitwise_and::simple_op1_range_solver): Same.
- * value-range.cc (swap_out_of_order_endpoints): Delete.
- (irange::set): Remove call to swap_out_of_order_endpoints.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * builtins.cc (determine_block_size): Convert use of legacy API to
- get_legacy_range.
- * gimple-array-bounds.cc (check_out_of_bounds_and_warn): Same.
- (array_bounds_checker::check_array_ref): Same.
- * gimple-ssa-warn-restrict.cc
- (builtin_memref::extend_offset_range): Same.
- * ipa-cp.cc (ipcp_store_vr_results): Same.
- * ipa-fnsummary.cc (set_switch_stmt_execution_predicate): Same.
- * ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Same.
- (ipa_write_jump_function): Same.
- * pointer-query.cc (get_size_range): Same.
- * tree-data-ref.cc (split_constant_offset): Same.
- * tree-ssa-strlen.cc (get_range): Same.
- (maybe_diag_stxncpy_trunc): Same.
- (strlen_pass::get_len_or_size): Same.
- (strlen_pass::count_nonzero_bytes_addr): Same.
- * tree-vect-patterns.cc (vect_get_range_info): Same.
- * value-range.cc (irange::maybe_anti_range): Remove.
- (get_legacy_range): New.
- (irange::copy_to_legacy): Use get_legacy_range.
- (ranges_from_anti_range): Same.
- * value-range.h (class irange): Remove maybe_anti_range.
- (get_legacy_range): New.
- * vr-values.cc (check_for_binary_op_overflow): Convert use of
- legacy API to get_legacy_range.
- (compare_ranges): Same.
- (compare_range_with_value): Same.
- (bounds_of_var_in_loop): Same.
- (find_case_label_ranges): Same.
- (simplify_using_ranges::simplify_switch_using_ranges): Same.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range-pretty-print.cc (vrange_printer::visit): Remove
- constant_p use.
- * value-range.cc (irange::constant_p): Remove.
- (irange::get_nonzero_bits_from_range): Remove constant_p use.
- * value-range.h (class irange): Remove constant_p.
- (irange::num_pairs): Remove constant_p use.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (irange::copy_legacy_to_multi_range): Remove
- symbolics support.
- (irange::set): Same.
- (irange::legacy_lower_bound): Same.
- (irange::legacy_upper_bound): Same.
- (irange::contains_p): Same.
- (range_tests_legacy): Same.
- (irange::normalize_addresses): Remove.
- (irange::normalize_symbolics): Remove.
- (irange::symbolic_p): Remove.
- * value-range.h (class irange): Remove symbolic_p,
- normalize_symbolics, and normalize_addresses.
- * vr-values.cc (simplify_using_ranges::two_valued_val_range_p):
- Remove symbolics support.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (irange::may_contain_p): Remove.
- * value-range.h (range_includes_zero_p): Rewrite may_contain_p
- usage with contains_p.
- * vr-values.cc (compare_range_with_value): Same.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * tree-vrp.cc (supported_types_p): Remove.
- (defined_ranges_p): Remove.
- (range_fold_binary_expr): Remove.
- (range_fold_unary_expr): Remove.
- * tree-vrp.h (range_fold_unary_expr): Remove.
- (range_fold_binary_expr): Remove.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-cp.cc (ipa_vr_operation_and_type_effects): Convert to ranger API.
- (ipa_value_range_from_jfunc): Same.
- (propagate_vr_across_jump_function): Same.
- * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same.
- * ipa-prop.cc (ipa_compute_jump_functions_for_edge): Same.
- * vr-values.cc (bounds_of_var_in_loop): Same.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * gimple-array-bounds.cc (array_bounds_checker::get_value_range):
- Add irange argument.
- (check_out_of_bounds_and_warn): Remove check for vr.
- (array_bounds_checker::check_array_ref): Remove pointer qualifier
- for vr and adjust accordingly.
- * gimple-array-bounds.h (get_value_range): Add irange argument.
- * value-query.cc (class equiv_allocator): Delete.
- (range_query::get_value_range): Delete.
- (range_query::range_query): Remove allocator access.
- (range_query::~range_query): Same.
- * value-query.h (get_value_range): Delete.
- * vr-values.cc
- (simplify_using_ranges::op_with_boolean_value_range_p): Remove
- call to get_value_range.
- (check_for_binary_op_overflow): Same.
- (simplify_using_ranges::legacy_fold_cond_overflow): Same.
- (simplify_using_ranges::simplify_abs_using_ranges): Same.
- (simplify_using_ranges::simplify_cond_using_ranges_1): Same.
- (simplify_using_ranges::simplify_casted_cond): Same.
- (simplify_using_ranges::simplify_switch_using_ranges): Same.
- (simplify_using_ranges::two_valued_val_range_p): Same.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * vr-values.cc
- (simplify_using_ranges::vrp_evaluate_conditional_warnv_with_ops):
- Rename to...
- (simplify_using_ranges::legacy_fold_cond_overflow): ...this.
- (simplify_using_ranges::vrp_visit_cond_stmt): Rename to...
- (simplify_using_ranges::legacy_fold_cond): ...this.
- (simplify_using_ranges::fold_cond): Rename
- vrp_evaluate_conditional_warnv_with_ops to
- legacy_fold_cond_overflow.
- * vr-values.h (class vr_values): Replace vrp_visit_cond_stmt and
- vrp_evaluate_conditional_warnv_with_ops with legacy_fold_cond and
- legacy_fold_cond_overflow respectively.
-
-2023-04-26 Aldy Hernandez <aldyh@redhat.com>
-
- * vr-values.cc (get_vr_for_comparison): Remove.
- (compare_name_with_value): Same.
- (vrp_evaluate_conditional_warnv_with_ops): Remove calls to
- compare_name_with_value.
- * vr-values.h: Remove compare_name_with_value.
- Remove get_vr_for_comparison.
-
-2023-04-26 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/stormy16/stormy16.md (bswaphi2): New define_insn.
- (bswapsi2): New define_insn.
- (swaphi): New define_insn to exchange two registers (swpw).
- (define_peephole2): Recognize exchange of registers as swaphi.
-
-2023-04-26 Richard Biener <rguenther@suse.de>
-
- * gimple-range-path.cc (path_range_query::compute_outgoing_relations):
- Avoid last_stmt.
- * ipa-pure-const.cc (pass_nothrow::execute): Likewise.
- * predict.cc (apply_return_prediction): Likewise.
- * sese.cc (set_ifsese_condition): Likewise. Simplify.
- * tree-cfg.cc (assert_unreachable_fallthru_edge_p): Avoid last_stmt.
- (make_edges_bb): Likewise.
- (make_cond_expr_edges): Likewise.
- (end_recording_case_labels): Likewise.
- (make_gimple_asm_edges): Likewise.
- (cleanup_dead_labels): Likewise.
- (group_case_labels): Likewise.
- (gimple_can_merge_blocks_p): Likewise.
- (gimple_merge_blocks): Likewise.
- (find_taken_edge): Likewise. Also handle empty fallthru blocks.
- (gimple_duplicate_sese_tail): Avoid last_stmt.
- (find_loop_dist_alias): Likewise.
- (gimple_block_ends_with_condjump_p): Likewise.
- (gimple_purge_dead_eh_edges): Likewise.
- (gimple_purge_dead_abnormal_call_edges): Likewise.
- (pass_warn_function_return::execute): Likewise.
- (execute_fixup_cfg): Likewise.
- * tree-eh.cc (redirect_eh_edge_1): Likewise.
- (pass_lower_resx::execute): Likewise.
- (pass_lower_eh_dispatch::execute): Likewise.
- (cleanup_empty_eh): Likewise.
- * tree-if-conv.cc (if_convertible_bb_p): Likewise.
- (predicate_bbs): Likewise.
- (ifcvt_split_critical_edges): Likewise.
- * tree-loop-distribution.cc (create_edge_for_control_dependence):
- Likewise.
- (loop_distribution::transform_reduction_loop): Likewise.
- * tree-parloops.cc (transform_to_exit_first_loop_alt): Likewise.
- (try_transform_to_exit_first_loop_alt): Likewise.
- (transform_to_exit_first_loop): Likewise.
- (create_parallel_loop): Likewise.
- * tree-scalar-evolution.cc (get_loop_exit_condition): Likewise.
- * tree-ssa-dce.cc (mark_last_stmt_necessary): Likewise.
- (eliminate_unnecessary_stmts): Likewise.
- * tree-ssa-dom.cc
- (dom_opt_dom_walker::set_global_ranges_from_unreachable_edges):
- Likewise.
- * tree-ssa-ifcombine.cc (ifcombine_ifandif): Likewise.
- (pass_tree_ifcombine::execute): Likewise.
- * tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Likewise.
- (should_duplicate_loop_header_p): Likewise.
- * tree-ssa-loop-ivcanon.cc (create_canonical_iv): Likewise.
- (tree_estimate_loop_size): Likewise.
- (try_unroll_loop_completely): Likewise.
- * tree-ssa-loop-ivopts.cc (tree_ssa_iv_optimize_loop): Likewise.
- * tree-ssa-loop-manip.cc (ip_normal_pos): Likewise.
- (canonicalize_loop_ivs): Likewise.
- * tree-ssa-loop-niter.cc (determine_value_range): Likewise.
- (bound_difference): Likewise.
- (number_of_iterations_popcount): Likewise.
- (number_of_iterations_cltz): Likewise.
- (number_of_iterations_cltz_complement): Likewise.
- (simplify_using_initial_conditions): Likewise.
- (number_of_iterations_exit_assumptions): Likewise.
- (loop_niter_by_eval): Likewise.
- (estimate_numbers_of_iterations): Likewise.
-
-2023-04-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Refine vmadc/vmsbc RA constraint.
-
-2023-04-26 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/108758
- * config/rs6000/rs6000-builtins.def
- (__builtin_vsx_scalar_cmp_exp_qp_eq, __builtin_vsx_scalar_cmp_exp_qp_gt
- __builtin_vsx_scalar_cmp_exp_qp_lt,
- __builtin_vsx_scalar_cmp_exp_qp_unordered): Move from stanza ieee128-hw
- to power9-vector.
-
-2023-04-26 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/109069
- * config/rs6000/altivec.md (sldoi_to_mov<mode>): Replace predicate
- easy_vector_constant with const_vector_each_byte_same, add
- handlings in preparation for !easy_vector_constant, and update
- VECTOR_UNIT_ALTIVEC_OR_VSX_P with VECTOR_MEM_ALTIVEC_OR_VSX_P.
- * config/rs6000/predicates.md (const_vector_each_byte_same): New
- predicate.
-
-2023-04-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md (*pred_cmp<mode>_merge_tie_mask): New pattern.
- (*pred_ltge<mode>_merge_tie_mask): Ditto.
- (*pred_cmp<mode>_scalar_merge_tie_mask): Ditto.
- (*pred_eqne<mode>_scalar_merge_tie_mask): Ditto.
- (*pred_cmp<mode>_extended_scalar_merge_tie_mask): Ditto.
- (*pred_eqne<mode>_extended_scalar_merge_tie_mask): Ditto.
- (*pred_cmp<mode>_narrow_merge_tie_mask): Ditto.
-
-2023-04-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix redundant vmv1r.v.
-
-2023-04-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix RA constraint.
-
-2023-04-26 Pan Li <pan2.li@intel.com>
-
- PR target/109272
- * tree-ssa-sccvn.cc (vn_reference_eq): add type vector subparts
- check for vn_reference equal.
-
-2023-04-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add enum for
- auto-vectorization preference.
- (enum riscv_autovec_lmul_enum): Add enum for choosing LMUL of RVV
- auto-vectorization.
- * config/riscv/riscv.opt: Add compile option for RVV auto-vectorization.
-
-2023-04-26 Jivan Hakobyan <jivanhakobyan9@gmail.com>
-
- * config/riscv/bitmanip.md: Updated predicates of bclri<mode>_nottwobits
- and bclridisi_nottwobits patterns.
- * config/riscv/predicates.md: (not_uimm_extra_bit_or_nottwobits): Adjust
- predicate to avoid splitting arith constants.
- (const_nottwobits_not_arith_operand): New predicate.
-
-2023-04-25 Hans-Peter Nilsson <hp@axis.com>
-
- * recog.cc (peep2_attempt, peep2_update_life): Correct
- head-comment description of parameter match_len.
-
-2023-04-25 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.md: riscv_move_integer() drop in_splitter arg.
- riscv_split_symbol() drop in_splitter arg.
- * config/riscv/riscv.cc: riscv_move_integer() drop in_splitter arg.
- riscv_split_symbol() drop in_splitter arg.
- riscv_force_temporary() drop in_splitter arg.
- * config/riscv/riscv-protos.h: riscv_move_integer() drop in_splitter arg.
- riscv_split_symbol() drop in_splitter arg.
-
-2023-04-25 Eric Botcazou <ebotcazou@adacore.com>
-
- * tree-ssa.cc (insert_debug_temp_for_var_def): Do not create
- superfluous debug temporaries for single GIMPLE assignments.
-
-2023-04-25 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109609
- * attr-fnspec.h (arg_max_access_size_given_by_arg_p):
- Clarify semantics.
- * tree-ssa-alias.cc (check_fnspec): Correctly interpret
- the size given by arg_max_access_size_given_by_arg_p as
- maximum, not exact, size.
-
-2023-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (orn<mode>3): Rename to...
- (orn<mode>3<vczle><vczbe>): ... This.
- (bic<mode>3): Rename to...
- (bic<mode>3<vczle><vczbe>): ... This.
- (<su><maxmin><mode>3): Rename to...
- (<su><maxmin><mode>3<vczle><vczbe>): ... This.
-
-2023-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3): New define_expand.
- * config/aarch64/iterators.md (VQDIV): New mode iterator.
- (vnx2di): New mode attribute.
-
-2023-04-25 Richard Biener <rguenther@suse.de>
-
- PR rtl-optimization/109585
- * tree-ssa-alias.cc (aliasing_component_refs_p): Fix typo.
-
-2023-04-25 Jakub Jelinek <jakub@redhat.com>
- PR target/109566
- * config/rs6000/rs6000.cc (rs6000_is_valid_rotate_dot_mask): For
- !TARGET_64BIT, don't return true if UINTVAL (mask) << (63 - nb)
- is larger than signed int maximum.
+2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
-2023-04-25 Martin Liska <mliska@suse.cz>
+ PR target/113855
+ * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
+ available to all sub-targets.
+ * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
+ * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
- * doc/gcov.texi: Document the new "calls" field and document
- the API bump. Mention also "block_ids" for lines.
- * gcov.cc (output_intermediate_json_line): Output info about
- calls and extend branches as well.
- (generate_results): Bump version to 2.
- (output_line_details): Use block ID instead of a non-sensual
- index.
+2024-02-12 Richard Biener <rguenther@suse.de>
-2023-04-25 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/stormy16/stormy16.md (zero_extendqihi2): Restore/fix
- length attribute for the first (memory operand) alternative.
-
-2023-04-25 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-simd.md(aarch64_simd_stp<mode>): New.
- * config/aarch64/constraints.md: Make "Umn" relaxed memory
- constraint.
- * config/aarch64/iterators.md(ldpstp_vel_sz): New.
-
-2023-04-25 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (frange::set): Adjust constructor.
- * value-range.h (nan_state::nan_state): Replace default
- constructor with one taking an argument.
-
-2023-04-25 Aldy Hernandez <aldyh@redhat.com>
-
- * ipa-cp.cc (ipa_range_contains_p): New.
- (decide_whether_version_node): Use it.
-
-2023-04-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- * tree-ssa-forwprop.cc (is_combined_permutation_identity): Try to
- simplify two successive VEC_PERM_EXPRs with same VLA mask,
- where mask chooses elements in reverse order.
-
-2023-04-24 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (match_simplify_replacement): Add new arguments
- and support diamond shaped basic block form.
- (tree_ssa_phiopt_worker): Update call to match_simplify_replacement
-
-2023-04-24 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p):
- Instead of calling last_and_only_stmt, look for the last statement
- manually.
-
-2023-04-24 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p):
- New function.
- (match_simplify_replacement): Call
- empty_bb_or_one_feeding_into_p instead of doing it inline.
-
-2023-04-24 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/68894
- * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Remove the
- continue for the do_hoist_loads diamond case.
-
-2023-04-24 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Rearrange
- code for better code readability.
-
-2023-04-24 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109604
- * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Move the
- diamond form check from ...
- (minmax_replacement): Here.
-
-2023-04-24 Patrick Palka <ppalka@redhat.com>
-
- * tree.cc (strip_array_types): Don't define here.
- (is_typedef_decl): Don't define here.
- (typedef_variant_p): Don't define here.
- * tree.h (strip_array_types): Define here.
- (is_typedef_decl): Define here.
- (typedef_variant_p): Define here.
-
-2023-04-24 Frederik Harwath <frederik@codesourcery.com>
-
- * doc/generic.texi (OpenMP): Add != to allowed
- conditions and state that vars can be unsigned.
- * tree.def (OMP_FOR): Likewise.
-
-2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (mulv2di3): New expander.
-
-2023-04-24 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
-
- * doc/install.texi: Consistently use Solaris rather than Solaris 2.
- Remove explicit Solaris 11 references.
- Markup fixes.
- (Options specification, --with-gnu-as): as and gas always differ
- on Solaris.
- Remove /usr/ccs/bin reference.
- (Installing GCC: Binaries, Solaris (SPARC, Intel)): Remove.
- (i?86-*-solaris2*): Merge assembler, linker recommendations ...
- (*-*-solaris2*): ... here.
- Update bundled GCC versions.
- Don't refer to pre-built binaries.
- Remove /bin/sh warning.
- Update assembler, linker recommendations.
- Document GNAT bootstrap compiler.
- (sparc-sun-solaris2*): Remove non-UltraSPARC reference.
- (sparc64-*-solaris2*): Move content...
- (sparcv9-*-solaris2*): ...here.
- Add GDC for 64-bit bootstrap compilers.
-
-2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/109406
- * config/aarch64/aarch64-sve.md (<optab><mode>3): Handle TARGET_SVE2 MUL
- case.
- * config/aarch64/aarch64-sve2.md (*aarch64_mul_unpredicated_<mode>): New
- pattern.
-
-2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur>abal2<mode>): Rename to...
- (aarch64_<su>abal2<mode>_insn): ... This. Use RTL codes instead of unspec.
- (aarch64_<su>abal2<mode>): New define_expand.
- * config/aarch64/aarch64.cc (aarch64_abd_rtx_p): New function.
- (aarch64_rtx_costs): Handle ABD rtxes.
- * config/aarch64/aarch64.md (UNSPEC_SABAL2, UNSPEC_UABAL2): Delete.
- * config/aarch64/iterators.md (ABAL2): Delete.
- (sur): Remove handling of UNSPEC_UABAL2 and UNSPEC_SABAL2.
-
-2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur>abal<mode>): Rename to...
- (aarch64_<su>abal<mode>): ... This. Use RTL codes instead of unspec.
- (<sur>sadv16qi): Rename to...
- (<su>sadv16qi): ... This. Adjust for the above.
- * config/aarch64/aarch64-sve.md (<sur>sad<vsi2qi>): Rename to...
- (<su>sad<vsi2qi>): ... This. Adjust for the above.
- * config/aarch64/aarch64.md (UNSPEC_SABAL, UNSPEC_UABAL): Delete.
- * config/aarch64/iterators.md (ABAL): Delete.
- (sur): Remove handling of UNSPEC_SABAL and UNSPEC_UABAL.
-
-2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur>abdl2<mode>): Rename to...
- (aarch64_<su>abdl2<mode>_insn): ... This. Use RTL codes instead of unspec.
- (aarch64_<su>abdl2<mode>): New define_expand.
- * config/aarch64/aarch64.md (UNSPEC_SABDL2, UNSPEC_UABDL2): Delete.
- * config/aarch64/iterators.md (ABDL2): Delete.
- (sur): Remove handling of UNSPEC_SABDL2 and UNSPEC_UABDL2.
-
-2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_<sur>abdl<mode>): Rename to...
- (aarch64_<su>abdl<mode>): ... This. Use standard RTL ops instead of
- unspec.
- * config/aarch64/aarch64.md (UNSPEC_SABDL, UNSPEC_UABDL): Delete.
- * config/aarch64/iterators.md (ABDL): Delete.
- (sur): Remove handling of UNSPEC_SABDL and UNSPEC_UABDL.
-
-2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md
- (*aarch64_<su>addlv<VDQV_L:mode>_ze<GPI:mode>): New pattern.
-
-2023-04-24 Richard Biener <rguenther@suse.de>
-
- * gimple-ssa-split-paths.cc (is_feasible_trace): Avoid
- last_stmt.
- * graphite-scop-detection.cc (single_pred_cond_non_loop_exit):
- Likewise.
- * ipa-fnsummary.cc (set_cond_stmt_execution_predicate): Likewise.
- (set_switch_stmt_execution_predicate): Likewise.
- (phi_result_unknown_predicate): Likewise.
- * ipa-prop.cc (compute_complex_ancestor_jump_func): Likewise.
- (ipa_analyze_indirect_call_uses): Likewise.
- * predict.cc (predict_iv_comparison): Likewise.
- (predict_extra_loop_exits): Likewise.
- (predict_loops): Likewise.
- (tree_predict_by_opcode): Likewise.
- * gimple-predicate-analysis.cc (predicate::init_from_control_deps):
- Likewise.
- * gimple-pretty-print.cc (dump_implicit_edges): Likewise.
- * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Likewise.
- (replace_phi_edge_with_variable): Likewise.
- (two_value_replacement): Likewise.
- (value_replacement): Likewise.
- (minmax_replacement): Likewise.
- (spaceship_replacement): Likewise.
- (cond_removal_in_builtin_zero_pattern): Likewise.
- * tree-ssa-reassoc.cc (maybe_optimize_range_tests): Likewise.
- * tree-ssa-sccvn.cc (vn_phi_eq): Likewise.
- (vn_phi_lookup): Likewise.
- (vn_phi_insert): Likewise.
- * tree-ssa-structalias.cc (compute_points_to_sets): Likewise.
- * tree-ssa-threadbackward.cc (back_threader::maybe_thread_block):
- Likewise.
- (back_threader_profitability::possibly_profitable_path_p):
- Likewise.
- * tree-ssa-threadedge.cc (jump_threader::thread_outgoing_edges):
- Likewise.
- * tree-switch-conversion.cc (pass_convert_switch::execute):
- Likewise.
- (pass_lower_switch<O0>::execute): Likewise.
- * tree-tailcall.cc (tree_optimize_tail_calls_1): Likewise.
- * tree-vect-loop-manip.cc (vect_loop_versioning): Likewise.
- * tree-vect-slp.cc (vect_slp_function): Likewise.
- * tree-vect-stmts.cc (cfun_returns): Likewise.
- * tree-vectorizer.cc (vect_loop_vectorized_call): Likewise.
- (vect_loop_dist_alias_call): Likewise.
-
-2023-04-24 Richard Biener <rguenther@suse.de>
-
- * cfgcleanup.cc (outgoing_edges_match): Use FORWARDER_BLOCK_P.
-
-2023-04-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc
- (vector_infos_manager::all_avail_in_compatible_p): New function.
- (pass_vsetvl::refine_vsetvls): Optimize vsetvls.
- * config/riscv/riscv-vsetvl.h: New function.
-
-2023-04-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::pre_vsetvl): Add function
- comment for cleanup_insns.
-
-2023-04-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: New unspec to refine fault first load pattern.
- * config/riscv/vector.md: Refine fault first load pattern to erase avl from instructions
- with the fault first load property.
-
-2023-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_): Rename to...
- (aarch64_float_truncate_lo_<mode><vczle><vczbe>): ... This.
-
-2023-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (aarch64_addp<mode>): Rename to...
- (aarch64_addp<mode><vczle><vczbe>): ... This.
-
-2023-04-23 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/stormy16/stormy16.cc (xstormy16_rtx_costs): Rewrite to
- provide reasonable values for common arithmetic operations and
- immediate operands (in several machine modes).
-
-2023-04-23 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/stormy16/stormy16.cc (xstormy16_print_operand): Add %h
- format specifier to output high_part register name of SImode reg.
- * config/stormy16/stormy16.md (extendhisi2): New define_insn.
- (zero_extendqihi2): Fix lengths, consistent formatting and add
- "and Rx,#255" alternative, for documentation purposes.
- (zero_extendhisi2): New define_insn.
-
-2023-04-23 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/stormy16/stormy16.cc (xstormy16_output_shift): Implement
- SImode shifts by two by performing a single bit SImode shift twice.
-
-2023-04-23 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/109593
- * value-range.cc (frange::operator==): Handle NANs.
-
-2023-04-23 liuhongt <hongtao.liu@intel.com>
-
- PR rtl-optimization/108707
- * ira-costs.cc (scan_one_insn): Use NO_REGS instead of
- GENERAL_REGS when preferred reg_class is not known.
-
-2023-04-22 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker):
- Change the code around slightly to move diamond
- handling for do_store_elim/do_hoist_loads out of
- the big if/else.
-
-2023-04-22 Andrew Pinski <apinski@marvell.com>
-
- * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker):
- Remove check on empty_block_p.
-
-2023-04-22 Jakub Jelinek <jakub@redhat.com>
-
- PR bootstrap/109589
- * system.h (class auto_mpz): Workaround PR62101 bug in GCC 4.8 and 4.9.
- * realmpfr.h (class auto_mpfr): Likewise.
-
-2023-04-22 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109583
- * match.pd (fneg/fadd simplify): Don't call related_vector_mode
- if vec_mode is not VECTOR_MODE_P.
-
-2023-04-22 Jan Hubicka <hubicka@ucw.cz>
- Ondrej Kubanek <kubanek0ondrej@gmail.com>
-
- * cfgloopmanip.h (adjust_loop_info_after_peeling): Declare.
- * tree-ssa-loop-ch.cc (ch_base::copy_headers): Fix updating of
- loop profile and bounds after header duplication.
- * tree-ssa-loop-ivcanon.cc (adjust_loop_info_after_peeling):
- Break out from try_peel_loop; fix handling of 0 iterations.
- (try_peel_loop): Use adjust_loop_info_after_peeling.
-
-2023-04-21 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109546
- * tree-vrp.cc (remove_unreachable::remove_and_update_globals): Do
- not fold conditions with ADDR_EXPR early.
-
-2023-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64.md (aarch64_umax<mode>3_insn): Delete.
- (umax<mode>3): Emit raw UMAX RTL instead of going through gen_ function
- for umax.
- (<optab><mode>3): New define_expand for MAXMIN_NOUMAX codes.
- (*aarch64_<optab><mode>3_zero): Define.
- (*aarch64_<optab><mode>3_cssc): Likewise.
- * config/aarch64/iterators.md (maxminand): New code attribute.
-
-2023-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/108779
- * config/aarch64/aarch64-opts.h (enum aarch64_tp_reg): Define.
- * config/aarch64/aarch64-protos.h (aarch64_output_load_tp):
- Define prototype.
- * config/aarch64/aarch64.cc (aarch64_tpidr_register): Declare.
- (aarch64_override_options_internal): Handle the above.
- (aarch64_output_load_tp): New function.
- * config/aarch64/aarch64.md (aarch64_load_tp_hard): Call
- aarch64_output_load_tp.
- * config/aarch64/aarch64.opt (aarch64_tp_reg): Define enum.
- (mtp=): New option.
- * doc/invoke.texi (AArch64 Options): Document -mtp=.
-
-2023-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- PR target/99195
- * config/aarch64/aarch64-simd.md (add_vec_concat_subst_le): Define.
- (add_vec_concat_subst_be): Likewise.
- (vczle): Likewise.
- (vczbe): Likewise.
- (add<mode>3): Rename to...
- (add<mode>3<vczle><vczbe>): ... This.
- (sub<mode>3): Rename to...
- (sub<mode>3<vczle><vczbe>): ... This.
- (mul<mode>3): Rename to...
- (mul<mode>3<vczle><vczbe>): ... This.
- (and<mode>3): Rename to...
- (and<mode>3<vczle><vczbe>): ... This.
- (ior<mode>3): Rename to...
- (ior<mode>3<vczle><vczbe>): ... This.
- (xor<mode>3): Rename to...
- (xor<mode>3<vczle><vczbe>): ... This.
- * config/aarch64/iterators.md (VDZ): Define.
-
-2023-04-21 Patrick Palka <ppalka@redhat.com>
-
- * tree.cc (walk_tree_1): Avoid repeatedly dereferencing tp
- and type_p.
-
-2023-04-21 Jan Hubicka <jh@suse.cz>
-
- * tree-ssa-loop-ch.cc (ch_base::copy_headers): Fix previous
- commit.
-
-2023-04-21 Vineet Gupta <vineetg@rivosinc.com>
-
- * expmed.h (x_shift*_cost): convert to int [speed][mode][shift].
- (shift*_cost_ptr ()): Access x_shift*_cost array directly.
-
-2023-04-21 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-
- * config/aarch64/aarch64.cc (aarch64_simd_dup_constant): Use
- force_reg instead of copy_to_mode_reg.
- (aarch64_expand_vector_init): Likewise.
-
-2023-04-21 Uroš Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.h (REG_OK_FOR_INDEX_P, REG_OK_FOR_BASE_P): Remove.
- (REG_OK_FOR_INDEX_NONSTRICT_P, REG_OK_FOR_BASE_NONSTRICT_P): Ditto.
- (REG_OK_FOR_INDEX_STRICT_P, REG_OK_FOR_BASE_STRICT_P): Ditto.
- (FIRST_INDEX_REG, LAST_INDEX_REG): New defines.
- (LEGACY_INDEX_REG_P, LEGACY_INDEX_REGNO_P): New macros.
- (INDEX_REG_P, INDEX_REGNO_P): Ditto.
- (REGNO_OK_FOR_INDEX_P): Use INDEX_REGNO_P predicates.
- (REGNO_OK_FOR_INDEX_NONSTRICT_P): New macro.
- (EG_OK_FOR_BASE_NONSTRICT_P): Ditto.
- * config/i386/predicates.md (index_register_operand):
- Use REGNO_OK_FOR_INDEX_P and REGNO_OK_FOR_INDEX_NONSTRICT_P macros.
- * config/i386/i386.cc (ix86_legitimate_address_p): Use
- REGNO_OK_FOR_BASE_P, REGNO_OK_FOR_BASE_NONSTRICT_P,
- REGNO_OK_FOR_INDEX_P and REGNO_OK_FOR_INDEX_NONSTRICT_P macros.
-
-2023-04-21 Jan Hubicka <hubicka@ucw.cz>
- Ondrej Kubanek <kubanek0ondrej@gmail.com>
-
- * tree-ssa-loop-ch.cc (ch_base::copy_headers): Update loop header and
- latch.
-
-2023-04-21 Richard Biener <rguenther@suse.de>
-
- * is-a.h (safe_is_a): New.
-
-2023-04-21 Richard Biener <rguenther@suse.de>
-
- * gimple-iterator.h (gimple_stmt_iterator::operator*): Add.
- (gphi_iterator::operator*): Likewise.
-
-2023-04-21 Jan Hubicka <hubicka@ucw.cz>
- Michal Jires <michal@jires.eu>
-
- * ipa-inline.cc (class inline_badness): New class.
- (edge_heap_t, edge_heap_node_t): Use inline_badness for badness instead
- of sreal.
- (update_edge_key): Update.
- (lookup_recursive_calls): Likewise.
- (recursive_inlining): Likewise.
- (add_new_edges_to_heap): Likewise.
- (inline_small_functions): Likewise.
-
-2023-04-21 Jan Hubicka <hubicka@ucw.cz>
-
- * ipa-devirt.cc (odr_types_equivalent_p): Cleanup warned checks.
-
-2023-04-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109573
- * tree-vect-loop.cc (vectorizable_live_operation): Allow
- unhandled SSA copy as well. Demote assert to checking only.
-
-2023-04-21 Richard Biener <rguenther@suse.de>
-
- * df-core.cc (df_analyze): Compute RPO on the reverse graph
- for DF_BACKWARD problems.
- (loop_post_order_compute): Rename to ...
- (loop_rev_post_order_compute): ... this, compute a RPO.
- (loop_inverted_post_order_compute): Rename to ...
- (loop_inverted_rev_post_order_compute): ... this, compute a RPO.
- (df_analyze_loop): Use RPO on the forward graph for DF_FORWARD
- problems, RPO on the inverted graph for DF_BACKWARD.
-
-2023-04-21 Richard Biener <rguenther@suse.de>
-
- * cfganal.h (inverted_rev_post_order_compute): Rename
- from ...
- (inverted_post_order_compute): ... this. Add struct function
- argument, change allocation to a C array.
- * cfganal.cc (inverted_rev_post_order_compute): Likewise.
- * lcm.cc (compute_antinout_edge): Adjust.
- * lra-lives.cc (lra_create_live_ranges_1): Likewise.
- * tree-ssa-dce.cc (remove_dead_stmt): Likewise.
- * tree-ssa-pre.cc (compute_antic): Likewise.
-
-2023-04-21 Richard Biener <rguenther@suse.de>
-
- * df.h (df_d::postorder_inverted): Change back to int *,
- clarify comments.
- * df-core.cc (rest_of_handle_df_finish): Adjust.
- (df_analyze_1): Likewise.
- (df_analyze): For DF_FORWARD problems use RPO on the forward
- graph. Adjust.
- (loop_inverted_post_order_compute): Adjust API.
- (df_analyze_loop): Adjust.
- (df_get_n_blocks): Likewise.
- (df_get_postorder): Likewise.
-
-2023-04-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/108270
- * config/riscv/riscv-vsetvl.cc
- (vector_infos_manager::all_empty_predecessor_p): New function.
- (pass_vsetvl::backward_demand_fusion): Ditto.
- * config/riscv/riscv-vsetvl.h: Ditto.
-
-2023-04-21 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/109582
- * config/riscv/generic.md: Change standard names to insn names.
-
-2023-04-21 Richard Biener <rguenther@suse.de>
-
- * lcm.cc (compute_antinout_edge): Use RPO on the inverted graph.
- (compute_laterin): Use RPO.
- (compute_available): Likewise.
-
-2023-04-21 Peng Fan <fanpeng@loongson.cn>
-
- * config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER): Redefine.
-
-2023-04-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/109547
- * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): New function.
- (vector_insn_info::skip_avl_compatible_p): Ditto.
- (vector_insn_info::merge): Remove default value.
- (pass_vsetvl::compute_local_backward_infos): Ditto.
- (pass_vsetvl::cleanup_insns): Add local vsetvl elimination.
- * config/riscv/riscv-vsetvl.h: Ditto.
-
-2023-04-20 Alejandro Colomar <alx.manpages@gmail.com>
-
- * doc/extend.texi (Common Function Attributes): Remove duplicate
- word.
-
-2023-04-20 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109564
- * gimple-range-fold.cc (fold_using_range::range_of_phi): Do no ignore
- UNDEFINED range names when deciding if all PHI arguments are the same,
-
-2023-04-20 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109011
- * tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern): Use
- .CTZ (X) = .POPCOUNT ((X - 1) & ~X) in preference to
- .CTZ (X) = PREC - .POPCOUNT (X | -X).
-
-2023-04-20 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-constraints.cc (match_reload): Exclude some hard regs for
- multi-reg inout reload pseudos used in asm in different mode.
-
-2023-04-20 Uros Bizjak <ubizjak@gmail.com>
-
- * config/arm/arm.cc (thumb1_legitimate_address_p):
- Use VIRTUAL_REGISTER_P predicate.
- (arm_eliminable_register): Ditto.
- * config/avr/avr.md (push<mode>_1): Ditto.
- * config/bfin/predicates.md (register_no_elim_operand): Ditto.
- * config/h8300/predicates.md (register_no_sp_elim_operand): Ditto.
- * config/i386/predicates.md (register_no_elim_operand): Ditto.
- * config/iq2000/predicates.md (call_insn_operand): Ditto.
- * config/microblaze/microblaze.h (CALL_INSN_OP): Ditto.
-
-2023-04-20 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/78952
- * config/i386/predicates.md (extract_operator): New predicate.
- * config/i386/i386.md (any_extract): Remove code iterator.
- (*cmpqi_ext<mode>_1_mem_rex64): Use extract_operator predicate.
- (*cmpqi_ext<mode>_1): Ditto.
- (*cmpqi_ext<mode>_2): Ditto.
- (*cmpqi_ext<mode>_3_mem_rex64): Ditto.
- (*cmpqi_ext<mode>_3): Ditto.
- (*cmpqi_ext<mode>_4): Ditto.
- (*extzvqi_mem_rex64): Ditto.
- (*extzvqi): Ditto.
- (*insvqi_2): Ditto.
- (*extendqi<SWI24:mode>_ext_1): Ditto.
- (*addqi_ext<mode>_0): Ditto.
- (*addqi_ext<mode>_1): Ditto.
- (*addqi_ext<mode>_2): Ditto.
- (*subqi_ext<mode>_0): Ditto.
- (*subqi_ext<mode>_2): Ditto.
- (*testqi_ext<mode>_1): Ditto.
- (*testqi_ext<mode>_2): Ditto.
- (*andqi_ext<mode>_0): Ditto.
- (*andqi_ext<mode>_1): Ditto.
- (*andqi_ext<mode>_1_cc): Ditto.
- (*andqi_ext<mode>_2): Ditto.
- (*<any_or:code>qi_ext<mode>_0): Ditto.
- (*<any_or:code>qi_ext<mode>_1): Ditto.
- (*<any_or:code>qi_ext<mode>_2): Ditto.
- (*xorqi_ext<mode>_1_cc): Ditto.
- (*negqi_ext<mode>_2): Ditto.
- (*ashlqi_ext<mode>_2): Ditto.
- (*<any_shiftrt:insn>qi_ext<mode>_2): Ditto.
-
-2023-04-20 Raphael Zinsly <rzinsly@ventanamicro.com>
-
- PR target/108248
- * config/riscv/bitmanip.md (clz, ctz, pcnt, min, max patterns): Use
- <bitmanip_insn> as the type to allow for fine grained control of
- scheduling these insns.
- * config/riscv/generic.md (generic_alu): Add bitmanip, clz, ctz, pcnt,
- min, max.
- * config/riscv/riscv.md (type attribute): Add types for clz, ctz,
- pcnt, signed and unsigned min/max.
-
-2023-04-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv.h (enum reg_class): Fix RVV register order.
-
-2023-04-20 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
-
- PR target/109535
- * config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function.
- (pass_vsetvl::cleanup_insns): Fix bug.
-
-2023-04-20 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md (vnsi, VnSI): Add scalar modes.
- (ldexp<mode>3): Delete.
- (ldexp<mode>3<exec>): Change "B" to "A".
-
-2023-04-20 Jakub Jelinek <jakub@redhat.com>
- Jonathan Wakely <jwakely@redhat.com>
-
- * tree.h (built_in_function_equal_p): New helper function.
- (fndecl_built_in_p): Turn into variadic template to support
- 1 or more built_in_function arguments.
- * builtins.cc (fold_builtin_expect): Use 3 argument fndecl_built_in_p.
- * gimplify.cc (goa_stabilize_expr): Likewise.
- * cgraphclones.cc (cgraph_node::create_clone): Likewise.
- * ipa-fnsummary.cc (compute_fn_summary): Likewise.
- * omp-low.cc (setjmp_or_longjmp_p): Likewise.
- * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee,
- cgraph_update_edges_for_call_stmt_node,
- cgraph_edge::verify_corresponds_to_fndecl,
- cgraph_node::verify_node): Likewise.
- * tree-stdarg.cc (optimize_va_list_gpr_fpr_size): Likewise.
- * gimple-ssa-warn-access.cc (matching_alloc_calls_p): Likewise.
- * ipa-prop.cc (try_make_edge_direct_virtual_call): Likewise.
-
-2023-04-20 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109011
- * tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern): New function.
- (vect_recog_popcount_clz_ctz_ffs_pattern): Move vect_pattern_detected
- call later. Don't punt for IFN_CTZ or IFN_FFS if it doesn't have
- direct optab support, but has instead IFN_CLZ, IFN_POPCOUNT or
- for IFN_FFS IFN_CTZ support, use vect_recog_ctz_ffs_pattern for that
- case.
- (vect_vect_recog_func_ptrs): Add ctz_ffs entry.
-
-2023-04-20 Richard Biener <rguenther@suse.de>
-
- * df-core.cc (rest_of_handle_df_initialize): Remove
- computation of df->postorder, df->postorder_inverted and
- df->n_blocks.
-
-2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA2_AVX_UNSET): Add OPTION_MASK_ISA2_VAES_UNSET.
- (ix86_handle_option): Set AVX flag for VAES.
- * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins):
- Add OPTION_MASK_ISA2_VAES_UNSET.
- (def_builtin): Share builtin between AES and VAES.
- * config/i386/i386-expand.cc (ix86_check_builtin_isa_match):
- Ditto.
- * config/i386/i386.md (aes): New isa attribute.
- * config/i386/sse.md (aesenc): Add pattern for VAES with xmm.
- (aesenclast): Ditto.
- (aesdec): Ditto.
- (aesdeclast): Ditto.
- * config/i386/vaesintrin.h: Remove redundant avx target push.
- * config/i386/wmmintrin.h (_mm_aesdec_si128): Change to macro.
- (_mm_aesdeclast_si128): Ditto.
- (_mm_aesenc_si128): Ditto.
- (_mm_aesenclast_si128): Ditto.
-
-2023-04-20 Hu, Lin1 <lin1.hu@intel.com>
-
- * config/i386/avx2intrin.h
- (_MM_REDUCE_OPERATOR_BASIC_EPI16): New macro.
- (_MM_REDUCE_OPERATOR_MAX_MIN_EP16): Ditto.
- (_MM256_REDUCE_OPERATOR_BASIC_EPI16): Ditto.
- (_MM256_REDUCE_OPERATOR_MAX_MIN_EP16): Ditto.
- (_MM_REDUCE_OPERATOR_BASIC_EPI8): Ditto.
- (_MM_REDUCE_OPERATOR_MAX_MIN_EP8): Ditto.
- (_MM256_REDUCE_OPERATOR_BASIC_EPI8): Ditto.
- (_MM256_REDUCE_OPERATOR_MAX_MIN_EP8): Ditto.
- (_mm_reduce_add_epi16): New instrinsics.
- (_mm_reduce_mul_epi16): Ditto.
- (_mm_reduce_and_epi16): Ditto.
- (_mm_reduce_or_epi16): Ditto.
- (_mm_reduce_max_epi16): Ditto.
- (_mm_reduce_max_epu16): Ditto.
- (_mm_reduce_min_epi16): Ditto.
- (_mm_reduce_min_epu16): Ditto.
- (_mm256_reduce_add_epi16): Ditto.
- (_mm256_reduce_mul_epi16): Ditto.
- (_mm256_reduce_and_epi16): Ditto.
- (_mm256_reduce_or_epi16): Ditto.
- (_mm256_reduce_max_epi16): Ditto.
- (_mm256_reduce_max_epu16): Ditto.
- (_mm256_reduce_min_epi16): Ditto.
- (_mm256_reduce_min_epu16): Ditto.
- (_mm_reduce_add_epi8): Ditto.
- (_mm_reduce_mul_epi8): Ditto.
- (_mm_reduce_and_epi8): Ditto.
- (_mm_reduce_or_epi8): Ditto.
- (_mm_reduce_max_epi8): Ditto.
- (_mm_reduce_max_epu8): Ditto.
- (_mm_reduce_min_epi8): Ditto.
- (_mm_reduce_min_epu8): Ditto.
- (_mm256_reduce_add_epi8): Ditto.
- (_mm256_reduce_mul_epi8): Ditto.
- (_mm256_reduce_and_epi8): Ditto.
- (_mm256_reduce_or_epi8): Ditto.
- (_mm256_reduce_max_epi8): Ditto.
- (_mm256_reduce_max_epu8): Ditto.
- (_mm256_reduce_min_epi8): Ditto.
- (_mm256_reduce_min_epu8): Ditto.
- * config/i386/avx512vlbwintrin.h:
- (_mm_mask_reduce_add_epi16): Ditto.
- (_mm_mask_reduce_mul_epi16): Ditto.
- (_mm_mask_reduce_and_epi16): Ditto.
- (_mm_mask_reduce_or_epi16): Ditto.
- (_mm_mask_reduce_max_epi16): Ditto.
- (_mm_mask_reduce_max_epu16): Ditto.
- (_mm_mask_reduce_min_epi16): Ditto.
- (_mm_mask_reduce_min_epu16): Ditto.
- (_mm256_mask_reduce_add_epi16): Ditto.
- (_mm256_mask_reduce_mul_epi16): Ditto.
- (_mm256_mask_reduce_and_epi16): Ditto.
- (_mm256_mask_reduce_or_epi16): Ditto.
- (_mm256_mask_reduce_max_epi16): Ditto.
- (_mm256_mask_reduce_max_epu16): Ditto.
- (_mm256_mask_reduce_min_epi16): Ditto.
- (_mm256_mask_reduce_min_epu16): Ditto.
- (_mm_mask_reduce_add_epi8): Ditto.
- (_mm_mask_reduce_mul_epi8): Ditto.
- (_mm_mask_reduce_and_epi8): Ditto.
- (_mm_mask_reduce_or_epi8): Ditto.
- (_mm_mask_reduce_max_epi8): Ditto.
- (_mm_mask_reduce_max_epu8): Ditto.
- (_mm_mask_reduce_min_epi8): Ditto.
- (_mm_mask_reduce_min_epu8): Ditto.
- (_mm256_mask_reduce_add_epi8): Ditto.
- (_mm256_mask_reduce_mul_epi8): Ditto.
- (_mm256_mask_reduce_and_epi8): Ditto.
- (_mm256_mask_reduce_or_epi8): Ditto.
- (_mm256_mask_reduce_max_epi8): Ditto.
- (_mm256_mask_reduce_max_epu8): Ditto.
- (_mm256_mask_reduce_min_epi8): Ditto.
- (_mm256_mask_reduce_min_epu8): Ditto.
-
-2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA_VPCLMULQDQ_SET):
- Add OPTION_MASK_ISA_PCLMUL_SET and OPTION_MASK_ISA_AVX_SET.
- (OPTION_MASK_ISA_AVX_UNSET):
- Add OPTION_MASK_ISA_VPCLMULQDQ_UNSET.
- (OPTION_MASK_ISA_PCLMUL_UNSET): Ditto.
- * config/i386/i386.md (vpclmulqdqvl): New.
- * config/i386/sse.md (pclmulqdq): Add evex encoding.
- * config/i386/vpclmulqdqintrin.h: Remove redudant avx target
- push.
-
-2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512vlbwintrin.h
- (_mm_mask_blend_epi16): Remove __OPTIMIZE__ wrapper.
- (_mm_mask_blend_epi8): Ditto.
- (_mm256_mask_blend_epi16): Ditto.
- (_mm256_mask_blend_epi8): Ditto.
- * config/i386/avx512vlintrin.h
- (_mm256_mask_blend_pd): Ditto.
- (_mm256_mask_blend_ps): Ditto.
- (_mm256_mask_blend_epi64): Ditto.
- (_mm256_mask_blend_epi32): Ditto.
- (_mm_mask_blend_pd): Ditto.
- (_mm_mask_blend_ps): Ditto.
- (_mm_mask_blend_epi64): Ditto.
- (_mm_mask_blend_epi32): Ditto.
- * config/i386/sse.md (VF_AVX512BWHFBF16): Removed.
- (VF_AVX512HFBFVL): Move it before the first usage.
- (<avx512>_blendm<mode>): Change iterator from VF_AVX512BWHFBF16
- to VF_AVX512HFBFVL.
-
-2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA_AVX512VBMI2_SET): Change OPTION_MASK_ISA_AVX512F_SET
- to OPTION_MASK_ISA_AVX512BW_SET.
- (OPTION_MASK_ISA_AVX512F_UNSET):
- Remove OPTION_MASK_ISA_AVX512VBMI2_UNSET.
- (OPTION_MASK_ISA_AVX512BW_UNSET):
- Add OPTION_MASK_ISA_AVX512VBMI2_UNSET.
- * config/i386/avx512vbmi2intrin.h: Do not push avx512bw.
- * config/i386/avx512vbmi2vlintrin.h: Ditto.
- * config/i386/i386-builtin.def: Remove OPTION_MASK_ISA_AVX512BW.
- * config/i386/sse.md (VI12_AVX512VLBW): Removed.
- (VI12_VI48F_AVX512VLBW): Rename to VI12_VI48F_AVX512VL.
- (compress<mode>_mask): Change iterator from VI12_AVX512VLBW to
- VI12_AVX512VL.
- (compressstore<mode>_mask): Ditto.
- (expand<mode>_mask): Ditto.
- (expand<mode>_maskz): Ditto.
- (*expand<mode>_mask): Change iterator from VI12_VI48F_AVX512VLBW to
- VI12_VI48F_AVX512VL.
-
-2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA_AVX512BITALG_SET):
- Change OPTION_MASK_ISA_AVX512F_SET
- to OPTION_MASK_ISA_AVX512BW_SET.
- (OPTION_MASK_ISA_AVX512F_UNSET):
- Remove OPTION_MASK_ISA_AVX512BITALG_SET.
- (OPTION_MASK_ISA_AVX512BW_UNSET):
- Add OPTION_MASK_ISA_AVX512BITALG_SET.
- * config/i386/avx512bitalgintrin.h: Do not push avx512bw.
- * config/i386/i386-builtin.def:
- Remove redundant OPTION_MASK_ISA_AVX512BW.
- * config/i386/sse.md (VI1_AVX512VLBW): Removed.
- (avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>):
- Change the iterator from VI1_AVX512VLBW to VI1_AVX512VL.
-
-2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386-expand.cc
- (ix86_check_builtin_isa_match): Correct wrong comments.
- Add a new macro SHARE_BUILTIN and refactor the current if
- clauses to macro.
-
-2023-04-20 Mo, Zewei <zewei.mo@intel.com>
-
- * config/i386/cpuid.h: Open a new section for Extended Features
- Leaf (%eax == 7, %ecx == 0) and Extended Features Sub-leaf (%eax == 7,
- %ecx == 1).
-
-2023-04-20 Hu, Lin1 <lin1.hu@intel.com>
-
- * config/i386/sse.md: Modify insn vperm{i,f}
- and vshuf{i,f}.
-
-2023-04-19 Max Filippov <jcmvbkbc@gmail.com>
-
- * config/xtensa/xtensa-opts.h: New header.
- * config/xtensa/xtensa.h (STRICT_ALIGNMENT): Redefine as
- xtensa_strict_align.
- * config/xtensa/xtensa.cc (xtensa_option_override): When
- -m[no-]strict-align is not specified in the command line set
- xtensa_strict_align to 0 if the hardware supports both unaligned
- loads and stores or to 1 otherwise.
- * config/xtensa/xtensa.opt (mstrict-align): New option.
- * doc/invoke.texi (Xtensa Options): Document -m[no-]strict-align.
-
-2023-04-19 Max Filippov <jcmvbkbc@gmail.com>
-
- * config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
- function.
-
-2023-04-19 Andrew Pinski <apinski@marvell.com>
-
- * config/i386/i386.md (*movsicc_noc_zext_1): New pattern.
-
-2023-04-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-modes.def (FLOAT_MODE): Add chunk 128 support.
- (VECTOR_BOOL_MODE): Ditto.
- (ADJUST_NUNITS): Ditto.
- (ADJUST_ALIGNMENT): Ditto.
- (ADJUST_BYTESIZE): Ditto.
- (ADJUST_PRECISION): Ditto.
- (RVV_MODES): Ditto.
- (VECTOR_MODE_WITH_PREFIX): Ditto.
- * config/riscv/riscv-v.cc (ENTRY): Ditto.
- (get_vlmul): Ditto.
- (get_ratio): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Ditto.
- * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Ditto.
- (vbool64_t): Ditto.
- (vbool32_t): Ditto.
- (vbool16_t): Ditto.
- (vbool8_t): Ditto.
- (vbool4_t): Ditto.
- (vbool2_t): Ditto.
- (vbool1_t): Ditto.
- (vint8mf8_t): Ditto.
- (vuint8mf8_t): Ditto.
- (vint8mf4_t): Ditto.
- (vuint8mf4_t): Ditto.
- (vint8mf2_t): Ditto.
- (vuint8mf2_t): Ditto.
- (vint8m1_t): Ditto.
- (vuint8m1_t): Ditto.
- (vint8m2_t): Ditto.
- (vuint8m2_t): Ditto.
- (vint8m4_t): Ditto.
- (vuint8m4_t): Ditto.
- (vint8m8_t): Ditto.
- (vuint8m8_t): Ditto.
- (vint16mf4_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vuint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vuint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vuint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vuint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vuint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vuint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vuint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vuint32m8_t): Ditto.
- (vint64m1_t): Ditto.
- (vuint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vuint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vuint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint64m8_t): Ditto.
- (vfloat32mf2_t): Ditto.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat32m8_t): Ditto.
- (vfloat64m1_t): Ditto.
- (vfloat64m2_t): Ditto.
- (vfloat64m4_t): Ditto.
- (vfloat64m8_t): Ditto.
- * config/riscv/riscv-vector-switch.def (ENTRY): Ditto.
- * config/riscv/riscv.cc (riscv_legitimize_poly_move): Ditto.
- (riscv_convert_vector_bits): Ditto.
- * config/riscv/riscv.md:
- * config/riscv/vector-iterators.md:
- * config/riscv/vector.md
- (@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
- (@pred_indexed_<order>store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX128_Q:mode><VNX128_Q:mode>): Ditto.
- (@pred_reduc_<reduc><mode><vlmul1_zve64>): Ditto.
- (@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>): Ditto.
- (@pred_reduc_plus<order><mode><vlmul1_zve64>): Ditto.
- (@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>): Ditto.
-
-2023-04-19 Pan Li <pan2.li@intel.com>
-
- * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
- Align IOR (A | (~A) -> -1) optimization MODE_CLASS condition to AND.
-
-2023-04-19 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/78904
- PR target/78952
- * config/i386/i386.md (*cmpqi_ext<mode>_1_mem_rex64): New insn pattern.
- (*cmpqi_ext<mode>_1): Use nonimmediate_operand predicate
- for operand 0. Use any_extract code iterator.
- (*cmpqi_ext<mode>_1 peephole2): New peephole2 pattern.
- (*cmpqi_ext<mode>_2): Use any_extract code iterator.
- (*cmpqi_ext<mode>_3_mem_rex64): New insn pattern.
- (*cmpqi_ext<mode>_1): Use general_operand predicate
- for operand 1. Use any_extract code iterator.
- (*cmpqi_ext<mode>_3 peephole2): New peephole2 pattern.
- (*cmpqi_ext<mode>_4): Use any_extract code iterator.
-
-2023-04-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_saddw2<mode>): Delete.
- (aarch64_uaddw2<mode>): Delete.
- (aarch64_ssubw2<mode>): Delete.
- (aarch64_usubw2<mode>): Delete.
- (aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>): New define_expand.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-structalias.cc (do_ds_constraint): Use
- solve_add_graph_edge.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-structalias.cc (solve_add_graph_edge): New function,
- split out from ...
- (do_sd_constraint): ... here.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- * tree-cfg.cc (gimple_can_merge_blocks_p): Remove condition
- rejecting the merge when A contains only a non-local label.
-
-2023-04-19 Uros Bizjak <ubizjak@gmail.com>
-
- * rtl.h (VIRTUAL_REGISTER_P): New predicate.
- (VIRTUAL_REGISTER_NUM_P): Ditto.
- (REGNO_PTR_FRAME_P): Use VIRTUAL_REGISTER_NUM_P predicate.
- * expr.cc (force_operand): Use VIRTUAL_REGISTER_P predicate.
- * function.cc (instantiate_decl_rtl): Ditto.
- * rtlanal.cc (rtx_addr_can_trap_p_1): Ditto.
- (nonzero_address_p): Ditto.
- (refers_to_regno_p): Use VIRTUAL_REGISTER_NUM_P predicate.
-
-2023-04-19 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (Value_Range::Value_Range): Avoid pointer sharing.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- * system.h (auto_mpz::operator->()): New.
- * realmpfr.h (auto_mpfr::operator->()): New.
- * builtins.cc (do_mpfr_lgamma_r): Use auto_mpfr.
- * real.cc (real_from_string): Likewise.
- (dconst_e_ptr): Likewise.
- (dconst_sqrt2_ptr): Likewise.
- * tree-ssa-loop-niter.cc (refine_value_range_using_guard):
- Use auto_mpz.
- (bound_difference_of_offsetted_base): Likewise.
- (number_of_iterations_ne): Likewise.
- (number_of_iterations_lt_to_ne): Likewise.
- * ubsan.cc: Include realmpfr.h.
- (ubsan_instrument_float_cast): Use auto_mpfr.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-structalias.cc (solve_graph): Remove self-copy
- edges, remove edges from escaped after special-casing them.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-structalias.cc (do_sd_constraint): Fixup escape
- special casing.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-structalias.cc (do_sd_constraint): Do not write
- to the LHS varinfo solution member.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-structalias.cc (topo_visit): Look at the real
- destination of edges.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/44794
- * tree-ssa-loop-manip.cc (tree_transform_and_unroll_loop):
- If an epilogue loop is required set its iteration upper bound.
-
-2023-04-19 Xi Ruoyao <xry111@xry111.site>
-
- PR target/109465
- * config/loongarch/loongarch-protos.h
- (loongarch_expand_block_move): Add a parameter as alignment RTX.
- * config/loongarch/loongarch.h:
- (LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER): Remove.
- (LARCH_MAX_MOVE_BYTES_STRAIGHT): Remove.
- (LARCH_MAX_MOVE_OPS_PER_LOOP_ITER): Define.
- (LARCH_MAX_MOVE_OPS_STRAIGHT): Define.
- (MOVE_RATIO): Use LARCH_MAX_MOVE_OPS_PER_LOOP_ITER instead of
- LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER.
- * config/loongarch/loongarch.cc (loongarch_expand_block_move):
- Take the alignment from the parameter, but set it to
- UNITS_PER_WORD if !TARGET_STRICT_ALIGN. Limit the length of
- straight-line implementation with LARCH_MAX_MOVE_OPS_STRAIGHT
- instead of LARCH_MAX_MOVE_BYTES_STRAIGHT.
- (loongarch_block_move_straight): When there are left-over bytes,
- half the mode size instead of falling back to byte mode at once.
- (loongarch_block_move_loop): Limit the length of loop body with
- LARCH_MAX_MOVE_OPS_PER_LOOP_ITER instead of
- LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER.
- * config/loongarch/loongarch.md (cpymemsi): Pass the alignment
- to loongarch_expand_block_move.
-
-2023-04-19 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc
- (loongarch_setup_incoming_varargs): Don't save more GARs than
- cfun->va_list_gpr_size / UNITS_PER_WORD.
-
-2023-04-19 Richard Biener <rguenther@suse.de>
+ PR tree-optimization/113831
+ PR tree-optimization/108355
+ * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
+ we see variable array indices and get_ref_base_and_extent
+ can resolve those to constants fix up the ops to constants
+ as well.
+ (ao_ref_init_from_vn_reference): Use 'off' member for
+ ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
+ (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
+
+2024-02-12 Pan Li <pan2.li@intel.com>
+
+ * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
+ Replace args to arguments for misspelled term.
+
+2024-02-12 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/112944
+ * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
+ <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
+ when not linked with -mrodata-in-ram.
+
+2024-02-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/113863
+ * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
+ Record crossed virtual PHIs.
+ * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
+ virtual PHIs.
+
+2024-02-10 Marek Polacek <polacek@redhat.com>
+
+ DR 2237
+ PR c++/107126
+ PR c++/97202
+ * doc/invoke.texi: Document -Wtemplate-id-cdtor.
+
+2024-02-10 Jakub Jelinek <jakub@redhat.com>
+
+ * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
+ computation of idx for i == 4 of bitint_prec_huge.
+
+2024-02-10 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/110754
+ * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
+ decls create PARM_DECL with pointer to original type, set
+ TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
+ DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
+ (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
+ wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
+ (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
+ of the var as argument.
+
+2024-02-10 Jakub Jelinek <jakub@redhat.com>
+
+ * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
+ size_t and precision 4 for ptrdiff_t. Formatting fix.
+ (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
+ Formatting fixes.
+ (test_pp_format): Test t and z modifiers.
+ * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
+
+2024-02-10 Jakub Jelinek <jakub@redhat.com>
+
+ * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
+ sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
+ and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
+ * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
+ and casts to fmt_size_t instead of "%ld" and casts to long.
+ (print_value_expr_statistics, print_type_hash_statistics): Likewise.
+ * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
+ instead of "%lu" and casts to unsigned long.
+ * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
+ unsigned long.
+ * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
+ and casts to fmt_size_t instead of "%ld" and casts to long.
+ * cfgexpand.cc (dump_stack_var_partition): Use
+ HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
+ and casts to unsigned long.
+ * gengtype.cc (adjust_field_rtx_def): Likewise.
+ * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
+ and casts to fmt_size_t instead of "%ld" and casts to long.
+ * postreload-gcse.cc (dump_hash_table): Likewise.
+ * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
+ and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
+ (ggc_internal_alloc, ggc_free): Likewise.
+ * genpreds.cc (write_lookup_constraint_1): Likewise.
+ (write_insn_constraint_len): Likewise.
+ * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
+ and casts to fmt_size_t instead of "%ld" and casts to long.
+ * varasm.cc (output_constant_pool_contents): Use
+ HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
+ * var-tracking.cc (dump_var): Likewise.
+
+2024-02-09 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/113783
+ * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
+ through VIEW_CONVERT_EXPR for final cast checks. Handle
+ VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
+ INTEGER_TYPEs.
+ (gimple_lower_bitint): Don't merge mergeable operations or other
+ casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
+ * expr.cc (expand_expr_real_1): Don't use convert_modes if either
+ mode is BLKmode.
+
+2024-02-09 Jakub Jelinek <jakub@redhat.com>
+
+ * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
+ HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
+ HOST_SIZE_T_PRINT_HEX_PURE): Define.
+ * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
+ fixes.
- * tree-ssa-loop-manip.cc (determine_exit_conditions): Fix
- no epilogue condition.
+2024-02-09 Jakub Jelinek <jakub@redhat.com>
-2023-04-19 Richard Biener <rguenther@suse.de>
+ PR middle-end/113415
+ * cfgexpand.cc (expand_asm_stmt): For asm goto, use
+ duplicate_insn_chain to duplicate after_rtl_seq sequence instead
+ of hand written loop with emit_insn of copy_insn and emit original
+ after_rtl_seq on the last edge.
- * gimple.h (gimple_assign_load): Outline...
- * gimple.cc (gimple_assign_load): ... here. Avoid
- get_base_address and instead just strip the outermost
- handled component, treating a remaining handled component
- as load.
-
-2023-04-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd-builtins.def (neg): Delete builtins
- definition.
- * config/aarch64/arm_fp16.h (vnegh_f16): Reimplement using normal negation.
+2024-02-09 Jakub Jelinek <jakub@redhat.com>
-2023-04-19 Jakub Jelinek <jakub@redhat.com>
+ PR tree-optimization/113818
+ * gimple-lower-bitint.cc (add_eh_edge): New function.
+ (bitint_large_huge::handle_load,
+ bitint_large_huge::lower_mergeable_stmt,
+ bitint_large_huge::lower_muldiv_stmt): Use it.
- PR tree-optimization/109011
- * tree-vect-patterns.cc (vect_recog_popcount_pattern): Rename to ...
- (vect_recog_popcount_clz_ctz_ffs_pattern): ... this. Handle also
- CLZ, CTZ and FFS. Remove vargs variable, use
- gimple_build_call_internal rather than gimple_build_call_internal_vec.
- (vect_vect_recog_func_ptrs): Adjust popcount entry.
+2024-02-09 Jakub Jelinek <jakub@redhat.com>
-2023-04-19 Jakub Jelinek <jakub@redhat.com>
+ PR tree-optimization/113774
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
+ emit any comparison if m_first and low + 1 is equal to
+ m_upwards_2limb, simplify condition for that. If not
+ single_comparison, not m_first and we can prove that the idx <= low
+ comparison will be always true, emit instead of idx <= low
+ comparison low <= low such that cfg cleanup will optimize it at
+ the end of the pass.
- PR target/109040
- * dse.cc (replace_read): If read_reg is a SUBREG of a word mode
- REG, for WORD_REGISTER_OPERATIONS copy SUBREG_REG of it into
- a new REG rather than the SUBREG.
+2024-02-08 Aldy Hernandez <aldyh@redhat.com>
-2023-04-19 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+ PR tree-optimization/113735
+ * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
+ limit_check().
- * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set_zero<mode>):
- New pattern.
+2024-02-08 Georg-Johann Lay <avr@gjlay.de>
-2023-04-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+ * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
+ (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
- PR target/108840
- * config/aarch64/aarch64.cc (aarch64_rtx_costs): Merge ASHIFT and
- ROTATE, ROTATERT, LSHIFTRT, ASHIFTRT cases. Handle subregs in op1.
+2024-02-08 H.J. Lu <hjl.tools@gmail.com>
-2023-04-19 Richard Biener <rguenther@suse.de>
+ PR target/113711
+ PR target/113733
+ * config/i386/constraints.md: List all constraints with j prefix.
+ (j>): Change auto-dec to auto-inc in documentation.
+ (je): Changed to a memory constraint with APX NDD TLS operand
+ check.
+ (jM): New memory constraint for APX NDD instructions.
+ (jO): Likewise.
+ * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
+ * config/i386/i386.cc (x86_poff_operand_p): Likewise.
+ * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
+ (*add<mode>_1[SWI48]): Use je and jM.
+ (addsi_1_zext): Use jM.
+ (*addv<dwi>4_doubleword_1[DWI]): Likewise.
+ (*sub<mode>_1[SWI]): Use jM.
+ (@add<mode>3_cc_overflow_1[SWI]): Likewise.
+ (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
+ (*and<dwi>3_doubleword): Likewise.
+ (*anddi_1): Use jM.
+ (*andsi_1_zext): Likewise.
+ (*and<mode>_1[SWI24]): Likewise.
+ (*<code><dwi>3_doubleword[any_or]): Use rjO
+ (*code<mode>_1[any_or SWI248]): Use jM.
+ (*<code>si_1_zext[zero_extend + any_or]): Likewise.
+ * config/i386/predicates.md (apx_ndd_memory_operand): New.
+ (apx_ndd_add_memory_operand): Likewise.
- PR rtl-optimization/109237
- * cse.cc (insn_live_p): Remove NEXT_INSN walk, instead check
- TREE_VISITED on INSN_VAR_LOCATION_DECL.
- (delete_trivially_dead_insns): Maintain TREE_VISITED on
- active debug bind INSN_VAR_LOCATION_DECL.
+2024-02-08 Georg-Johann Lay <avr@gjlay.de>
-2023-04-19 Richard Biener <rguenther@suse.de>
+ PR target/113824
+ * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
+ * doc/avr-mmcu.texi: Rebuild.
- PR rtl-optimization/109237
- * cfgcleanup.cc (bb_is_just_return): Walk insns backwards.
+2024-02-08 Tamar Christina <tamar.christina@arm.com>
-2023-04-19 Christophe Lyon <christophe.lyon@arm.com>
+ PR tree-optimization/113808
+ * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
+ value cross iterations.
- * doc/install.texi (enable-decimal-float): Add AArch64.
+2024-02-08 Georg-Johann Lay <avr@gjlay.de>
-2023-04-19 liuhongt <hongtao.liu@intel.com>
+ * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
+ defines __AVR_PM_BASE_ADDRESS__ if the core has it.
- PR rtl-optimization/109351
- * ira.cc (setup_class_subset_and_memory_move_costs): Check
- hard_regno_mode_ok before setting lowest memory move cost for
- the mode with different reg classes.
+2024-02-08 Richard Biener <rguenther@suse.de>
-2023-04-18 Jason Merrill <jason@redhat.com>
+ * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
+ Revert last change to dr_may_alias_p.
- * doc/invoke.texi: Remove stray @gol.
+2024-02-08 Georg-Johann Lay <avr@gjlay.de>
-2023-04-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
+ cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
+ Remove spec asm_misc.
+ * config/avr/specs.h: Same.
- * ifcvt.cc (cond_move_process_if_block): Consider the result of
- targetm.noce_conversion_profitable_p() when replacing the original
- sequence with the converted one.
+2024-02-08 Pan Li <pan2.li@intel.com>
-2023-04-18 Mark Harmstone <mark@harmstone.com>
+ PR target/113766
+ * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
+ sure the c.arg_num is >= 2 before checking.
+ (struct build_frm_base): Ditto.
+ (struct narrow_alu_def): Ditto.
- * common.opt (gcodeview): Add new option.
- * gcc.cc (driver_handle_option); Handle OPT_gcodeview.
- * opts.cc (command_handle_option): Similarly.
- * doc/invoke.texi: Add documentation for -gcodeview.
+2024-02-07 Richard Biener <rguenther@suse.de>
-2023-04-18 Andrew Pinski <apinski@marvell.com>
+ PR tree-optimization/113796
+ * tree-if-conv.cc (combine_blocks): Wipe range-info before
+ replacing PHIs and inserting predicates.
- * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Remove declaration.
- (make_pass_phiopt): Make execute out of line.
- (tree_ssa_cs_elim): Move code into ...
- (pass_cselim::execute): here.
+2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
+ Uros Bizjak <ubizjak@gmail.com>
-2023-04-18 Sam James <sam@gentoo.org>
+ PR target/113690
+ * config/i386/i386-features.cc (timode_convert_cst): New helper
+ function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
+ CONST_VECTOR.
+ (timode_scalar_chain::convert_op): Use timode_convert_cst.
+ (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
+ Use timode_convert_cst.
- * system.h: Drop unused INCLUDE_PTHREAD_H.
+2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
-2023-04-18 Kevin Lee <kevinl@rivosinc.com>
+ * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
+ * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
+ (AARCH64_FL_DEBUGv8p9): Likewise.
+ (AARCH64_FL_FGT2): Likewise.Likewise.
+ (AARCH64_FL_ITE): Likewise.
+ (AARCH64_FL_PFAR): Likewise.
+ (AARCH64_FL_PMUv3_ICNTR): Likewise.
+ (AARCH64_FL_PMUv3_SS): Likewise.
+ (AARCH64_FL_PMUv3p9): Likewise.
+ (AARCH64_FL_RASv2): Likewise.
+ (AARCH64_FL_S1PIE): Likewise.
+ (AARCH64_FL_S1POE): Likewise.
+ (AARCH64_FL_S2PIE): Likewise.
+ (AARCH64_FL_S2POE): Likewise.
+ (AARCH64_FL_SCTLR2): Likewise.
+ (AARCH64_FL_SEBEP): Likewise.
+ (AARCH64_FL_SPE_FDS): Likewise.
+ (AARCH64_FL_TCR2): Likewise.
+
+2024-02-07 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
+ Only check whether reads are in-bound in places that are not safe.
+ Fix dependence check. Add missing newline. Clarify comments.
+
+2024-02-07 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/113750
+ * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
+ for single predecessor when doing early break vect.
+ * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
+ after labels.
+
+2024-02-07 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/113731
+ * gimple-iterator.cc (gsi_move_before): Take new parameter for update
+ method.
+ * gimple-iterator.h (gsi_move_before): Default new param to
+ GSI_SAME_STMT.
+ * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
+ GSI_NEW_STMT.
- * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new
- condition.
+2024-02-07 Jakub Jelinek <jakub@redhat.com>
-2023-04-18 Sinan Lin <sinan.lin@linux.alibaba.com>
+ PR tree-optimization/113756
+ * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
+ use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
+ of lh_bits value and mask.
- * config/riscv/bitmanip.md (rotr<mode>3 expander): Enable for ZBKB.
- (bswapdi2, bswapsi2): Similarly.
+2024-02-07 Jakub Jelinek <jakub@redhat.com>
-2023-04-18 Uros Bizjak <ubizjak@gmail.com>
+ PR tree-optimization/113753
+ * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
+ UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
+ not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
+ so that they start with r[half_blocks_needed] lowest bit. Fix up
+ computation of top mask for SIGNED.
- PR target/94908
- * config/i386/i386-builtin.def (__builtin_ia32_insertps128):
- Use CODE_FOR_sse4_1_insertps_v4sf.
- * config/i386/i386-expand.cc (expand_vec_perm_insertps): New.
- (expand_vec_perm_1): Call expand_vec_per_insertps.
- * config/i386/i386.md ("unspec"): Declare UNSPEC_INSERTPS here.
- * config/i386/mmx.md (mmxscalarmode): New mode attribute.
- (@sse4_1_insertps_<mode>): New insn pattern.
- * config/i386/sse.md (@sse4_1_insertps_<mode>): Macroize insn
- pattern from sse4_1_insertps using VI4F_128 mode iterator.
+2024-02-07 Pan Li <pan2.li@intel.com>
-2023-04-18 Aldy Hernandez <aldyh@redhat.com>
+ PR target/113766
+ * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
+ the signature of func.
+ * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
+ * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
+ overloaded func with empty args error.
- * value-range.cc (gt_ggc_mx): New.
- (gt_pch_nx): New.
- * value-range.h (class vrange): Add GTY marker.
- (class frange): Same.
- (gt_ggc_mx): Remove.
- (gt_pch_nx): Remove.
+2024-02-06 H.J. Lu <hjl.tools@gmail.com>
-2023-04-18 Victor L. Do Nascimento <victor.donascimento@arm.com>
+ PR target/113689
+ * config/i386/i386.cc (x86_64_select_profile_regnum): Return
+ R10_REG after sorry.
- * lra-constraints.cc (constraint_unique): New.
- (process_address_1): Apply constraint_unique test.
- * recog.cc (constrain_operands): Allow relaxed memory
- constaints.
+2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
-2023-04-18 Kito Cheng <kito.cheng@sifive.com>
+ * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
+ Move before new caller, and add ".default" suffix.
+ (get_suffixed_assembler_name): New.
+ (make_resolver_func): Use get_suffixed_assembler_name.
+ (aarch64_generate_version_dispatcher_body): Redo name mangling.
- * doc/extend.texi (Target Builtins): Add RISC-V Vector
- Intrinsics.
- (RISC-V Vector Intrinsics): Document GCC implemented which
- version of RISC-V vector intrinsics and its reference.
+2024-02-06 Jakub Jelinek <jakub@redhat.com>
-2023-04-18 Richard Biener <rguenther@suse.de>
+ PR target/113763
+ * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
+ element from std::pair<unsigned int, char> to an unnamed struct.
+ Adjust uses of tile range variable.
- PR middle-end/108786
- * bitmap.h (bitmap_clear_first_set_bit): New.
- * bitmap.cc (bitmap_first_set_bit_worker): Rename from
- bitmap_first_set_bit and add optional clearing of the bit.
- (bitmap_first_set_bit): Wrap bitmap_first_set_bit_worker.
- (bitmap_clear_first_set_bit): Likewise.
- * df-core.cc (df_worklist_dataflow_doublequeue): Use
- bitmap_clear_first_set_bit.
- * graphite-scop-detection.cc (scop_detection::merge_sese):
- Likewise.
- * sanopt.cc (sanitize_asan_mark_unpoison): Likewise.
- (sanitize_asan_mark_poison): Likewise.
- * tree-cfgcleanup.cc (cleanup_tree_cfg_noloop): Likewise.
- * tree-into-ssa.cc (rewrite_blocks): Likewise.
- * tree-ssa-dce.cc (simple_dce_from_worklist): Likewise.
- * tree-ssa-sccvn.cc (do_rpo_vn_1): Likewise.
+2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-04-18 Richard Biener <rguenther@suse.de>
+ * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
+ (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
- * tree-ssa-structalias.cc (dump_sa_stats): Split out from...
- (dump_sa_points_to_info): ... this function.
- (compute_points_to_sets): Guard large dumps with TDF_DETAILS,
- and call dump_sa_stats guarded with TDF_STATS.
- (ipa_pta_execute): Likewise.
- (compute_may_aliases): Guard dump_alias_info with
- TDF_DETAILS|TDF_ALIAS.
+2024-02-06 Jakub Jelinek <jakub@redhat.com>
-2023-04-18 Andrew Pinski <apinski@marvell.com>
+ PR sanitizer/110676
+ * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
+ reset maxlen to sizetype maximum.
- * tree-ssa-phiopt.cc (gimple_simplify_phiopt): Dump
- the expression that is being tried when TDF_FOLDING
- is true.
- (phiopt_worker::match_simplify_replacement): Dump
- the sequence which was created by gimple_simplify_phiopt
- when TDF_FOLDING is true.
+2024-02-06 Jakub Jelinek <jakub@redhat.com>
-2023-04-18 Andrew Pinski <apinski@marvell.com>
+ PR tree-optimization/113736
+ * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
+ var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
- * tree-ssa-phiopt.cc (match_simplify_replacement):
- Simplify code that does the movement slightly.
+2024-02-06 Jakub Jelinek <jakub@redhat.com>
-2023-04-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+ PR tree-optimization/113759
+ * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
+ or from_unsignedN differs from properties of typeN, update typeN
+ to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
+ uselessly convertible to typeN, convert it using fold_convert or
+ build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
+ (convert_plusminus_to_widen): Likewise.
- * config/aarch64/aarch64.md (@aarch64_rev16<mode>): Change to
- define_expand.
- (rev16<mode>2): Rename to...
- (aarch64_rev16<mode>2_alt1): ... This.
- (rev16<mode>2_alt): Rename to...
- (*aarch64_rev16<mode>2_alt2): ... This.
+2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
-2023-04-18 Aldy Hernandez <aldyh@redhat.com>
+ PR target/112577
+ * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
+ vector structure modes correctly.
- * emit-rtl.cc (init_emit_once): Initialize dconstm0.
- * gimple-range-op.cc (class cfn_signbit): Remove dconstm0
- declaration.
- * range-op-float.cc (zero_range): Use dconstm0.
- (zero_to_inf_range): Same.
- * real.h (dconstm0): New.
- * value-range.cc (frange::flush_denormals_to_zero): Use dconstm0.
- (frange::set_zero): Do not declare dconstm0.
-
-2023-04-18 Richard Biener <rguenther@suse.de>
-
- * system.h (class auto_mpz): New,
- * realmpfr.h (class auto_mpfr): Likewise.
- * fold-const-call.cc (do_mpfr_arg1): Use auto_mpfr.
- (do_mpfr_arg2): Likewise.
- * tree-ssa-loop-niter.cc (bound_difference): Use auto_mpz;
-
-2023-04-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (aarch64_init_simd_intrinsics): Take
- builtin flags from intrinsic data rather than hardcoded FLAG_AUTO_FP.
-
-2023-04-18 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.cc (frange::operator==): Adjust for NAN.
- (range_tests_nan): Remove some NAN tests.
-
-2023-04-18 Aldy Hernandez <aldyh@redhat.com>
-
- * inchash.cc (hash::add_real_value): New.
- * inchash.h (class hash): Add add_real_value.
- * value-range.cc (add_vrange): New.
- * value-range.h (inchash::add_vrange): New.
-
-2023-04-18 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109539
- * gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses):
- Re-implement pointer relatedness for PHIs.
-
-2023-04-18 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md (SV_SFDF): New iterator.
- (SV_FP): New iterator.
- (scalar_mode, SCALAR_MODE): Add identity mappings for scalar modes.
- (recip<mode>2): Unify the two patterns using SV_FP.
- (div_scale<mode><exec_vcc>): New insn.
- (div_fmas<mode><exec>): New insn.
- (div_fixup<mode><exec>): New insn.
- (div<mode>3): Unify the two expanders and rewrite using hardfp.
- * config/gcn/gcn.cc (gcn_md_reorg): Support "vccwait" attribute.
- * config/gcn/gcn.md (unspec): Add UNSPEC_DIV_SCALE, UNSPEC_DIV_FMAS,
- and UNSPEC_DIV_FIXUP.
- (vccwait): New attribute.
-
-2023-04-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_validate_mcpu): Add hint to use -march
- if the argument matches that.
-
-2023-04-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/atomics.md
- (*aarch64_atomic_load<ALLX:mode>_rcpc_zext):
- Use SD_HSDI for destination mode iterator.
-
-2023-04-18 Jin Ma <jinma@linux.alibaba.com>
-
- * common/config/riscv/riscv-common.cc (multi_letter_subset_rank): Swap the order
- of z-extensions and s-extensions.
- (riscv_subset_list::parse): Likewise.
-
-2023-04-18 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109240
- * match.pd (fneg/fadd): Rewrite such that it handles both plus as
- first vec_perm operand and minus as second using fneg/fadd and
- minus as first vec_perm operand and plus as second using fneg/fsub.
-
-2023-04-18 Aldy Hernandez <aldyh@redhat.com>
-
- * data-streamer.cc (bp_pack_real_value): New.
- (bp_unpack_real_value): New.
- * data-streamer.h (bp_pack_real_value): New.
- (bp_unpack_real_value): New.
- * tree-streamer-in.cc (unpack_ts_real_cst_value_fields): Use
- bp_unpack_real_value.
- * tree-streamer-out.cc (pack_ts_real_cst_value_fields): Use
- bp_pack_real_value.
-
-2023-04-18 Aldy Hernandez <aldyh@redhat.com>
-
- * wide-int.h (WIDE_INT_MAX_HWIS): New.
- (class fixed_wide_int_storage): Use it.
- (trailing_wide_ints <N>::set_precision): Use it.
- (trailing_wide_ints <N>::extra_size): Use it.
-
-2023-04-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-protos.h
- (loongarch_addu16i_imm12_operand_p): New function prototype.
- (loongarch_split_plus_constant): Likewise.
- * config/loongarch/loongarch.cc
- (loongarch_addu16i_imm12_operand_p): New function.
- (loongarch_split_plus_constant): Likewise.
- * config/loongarch/loongarch.h (ADDU16I_OPERAND): New macro.
- (DUAL_IMM12_OPERAND): Likewise.
- (DUAL_ADDU16I_OPERAND): Likewise.
- * config/loongarch/constraints.md (La, Lb, Lc, Ld, Le): New
- constraint.
- * config/loongarch/predicates.md (const_dual_imm12_operand): New
- predicate.
- (const_addu16i_operand): Likewise.
- (const_addu16i_imm12_di_operand): Likewise.
- (const_addu16i_imm12_si_operand): Likewise.
- (plus_di_operand): Likewise.
- (plus_si_operand): Likewise.
- (plus_si_extend_operand): Likewise.
- * config/loongarch/loongarch.md (add<mode>3): Convert to
- define_insn_and_split. Use plus_<mode>_operand predicate
- instead of arith_operand. Add alternatives for La, Lb, Lc, Ld,
- and Le constraints.
- (*addsi3_extended): Convert to define_insn_and_split. Use
- plus_si_extend_operand instead of arith_operand. Add
- alternatives for La and Le alternatives.
-
-2023-04-18 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (Value_Range::Value_Range): New.
- (Value_Range::contains_p): New.
-
-2023-04-18 Aldy Hernandez <aldyh@redhat.com>
-
- * value-range.h (class vrange): Make m_discriminator const.
- (class irange): Make m_max_ranges const. Adjust constructors
- accordingly.
- (class unsupported_range): Construct vrange appropriately.
- (class frange): Same.
+2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
-2023-04-18 Lulu Cheng <chenglulu@loongson.cn>
+ * config/riscv/thead.cc (th_print_operand_address): Fix compiler
+ warning.
- * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove the macro
- definition.
+2024-02-05 H.J. Lu <hjl.tools@gmail.com>
-2023-04-18 Lulu Cheng <chenglulu@loongson.cn>
+ PR target/113689
+ * config/i386/i386.cc (x86_64_select_profile_regnum): New.
+ (x86_function_profiler): Call x86_64_select_profile_regnum to
+ get a scratch register for large model profiling.
- * doc/extend.texi: Add section for LoongArch Base Built-in functions.
+2024-02-05 Richard Ball <richard.ball@arm.com>
-2023-04-18 Fei Gao <gaofei@eswincomputing.com>
+ * config/arm/arm.cc (arm_output_mi_thunk): Emit
+ insn for bti_c when bti is enabled.
- * config/riscv/riscv.cc (riscv_first_stack_step): Make codes more
- readable.
- (riscv_expand_epilogue): Likewise.
+2024-02-05 Xi Ruoyao <xry111@xry111.site>
-2023-04-17 Fei Gao <gaofei@eswincomputing.com>
+ * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
+ neg.
- * config/riscv/riscv.cc (riscv_expand_prologue): Consider save-restore in
- stack allocation.
- (riscv_expand_epilogue): Consider save-restore in stack deallocation.
+2024-02-05 Xi Ruoyao <xry111@xry111.site>
-2023-04-17 Andrew Pinski <apinski@marvell.com>
+ * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
+ (neg<mode>2): Change the mode iterator from MSA to IMSA because
+ in FP arithmetic we cannot use (0 - x) for -x.
+ (neg<mode>2): New define_insn to implement FP vector negation,
+ using a bnegi instruction to negate the sign bit.
- * tree-ssa-phiopt.cc (gate_hoist_loads): Remove
- prototype.
+2024-02-05 Richard Biener <rguenther@suse.de>
-2023-04-17 Aldy Hernandez <aldyh@redhat.com>
+ PR tree-optimization/113707
+ * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
+ checking the avail set treat out-of-region defines as
+ available.
- * gimple-ssa-warn-alloca.cc (pass_walloca::execute): Do not export
- global ranges.
+2024-02-05 Richard Biener <rguenther@suse.de>
-2023-04-17 Fei Gao <gaofei@eswincomputing.com>
+ * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
+ the default mode when building a pointer.
- * config/riscv/riscv.cc (riscv_first_stack_step): Add a new function
- parameter remaining_size.
- (riscv_compute_frame_info): Adapt new riscv_first_stack_step interface.
- (riscv_expand_prologue): Likewise.
- (riscv_expand_epilogue): Likewise.
+2024-02-05 Jakub Jelinek <jakub@redhat.com>
-2023-04-17 Feng Wang <wangfeng@eswincomputing.com>
-
- * config/riscv/bitmanip.md (rotrsi3_sext): Support generating
- roriw for constant counts.
- * rtl.h (reverse_rotate_by_imm_p): Add function declartion
- * simplify-rtx.cc (reverse_rotate_by_imm_p): New function.
- (simplify_context::simplify_binary_operation_1): Use it.
- * expmed.cc (expand_shift_1): Likewise.
-
-2023-04-17 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/107769
- PR ipa/109318
- * cgraph.h (symtab_node::find_reference): Add parameter use_type.
- * ipa-prop.h (ipa_pass_through_data): New flag refdesc_decremented.
- (ipa_zap_jf_refdesc): New function.
- (ipa_get_jf_pass_through_refdesc_decremented): Likewise.
- (ipa_set_jf_pass_through_refdesc_decremented): Likewise.
- * ipa-cp.cc (ipcp_discover_new_direct_edges): Provide a value for
- the new parameter of find_reference.
- (adjust_references_in_caller): Likewise. Make sure the constant jump
- function is not used to decrement a refdec counter again. Only
- decrement refdesc counters when the pass_through jump function allows
- it. Added a detailed dump when decrementing refdesc counters.
- * ipa-prop.cc (ipa_print_node_jump_functions_for_edge): Dump new flag.
- (ipa_set_jf_simple_pass_through): Initialize the new flag.
- (ipa_set_jf_unary_pass_through): Likewise.
- (ipa_set_jf_arith_pass_through): Likewise.
- (remove_described_reference): Provide a value for the new parameter of
- find_reference.
- (update_jump_functions_after_inlining): Zap refdesc of new jfunc if
- the previous pass_through had a flag mandating that we do so.
- (propagate_controlled_uses): Likewise. Only decrement refdesc
- counters when the pass_through jump function allows it.
- (ipa_edge_args_sum_t::duplicate): Provide a value for the new
- parameter of find_reference.
- (ipa_write_jump_function): Assert the new flag does not have to be
- streamed.
- * symtab.cc (symtab_node::find_reference): Add parameter use_type, use
- it in searching.
-
-2023-04-17 Philipp Tomsich <philipp.tomsich@vrull.eu>
- Di Zhao <di.zhao@amperecomputing.com>
-
- * config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNING_OPTION):
- Add AARCH64_EXTRA_TUNE_NO_LDP_COMBINE.
- * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
- Check for the above tuning option when processing loads.
+ PR tree-optimization/113737
+ * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
+ has just a single label, remove it and make single successor edge
+ EDGE_FALLTHRU.
-2023-04-17 Richard Biener <rguenther@suse.de>
+2024-02-05 Jakub Jelinek <jakub@redhat.com>
- PR tree-optimization/109524
- * tree-vrp.cc (remove_unreachable::m_list): Change to a
- vector of pairs of block indices.
- (remove_unreachable::maybe_register_block): Adjust.
- (remove_unreachable::remove_and_update_globals): Likewise.
- Deal with removed blocks.
+ PR target/113059
+ * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
+ Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
+ df_analyze call.
-2023-04-16 Jeff Law <jlaw@ventanamicro>
+2024-02-05 Richard Biener <rguenther@suse.de>
- PR target/109508
- * config/riscv/riscv.cc (riscv_expand_conditional_move): For
- TARGET_SFB_ALU, force the true arm into a register.
+ PR target/113255
+ * config/i386/i386-expand.cc
+ (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
+ Use a new pseudo for the skipped number of bytes.
-2023-04-15 John David Anglin <danglin@gcc.gnu.org>
+2024-02-05 Monk Chiang <monk.chiang@sifive.com>
- PR target/104989
- * config/pa/pa-protos.h (pa_function_arg_size): Update prototype.
- * config/pa/pa.cc (pa_function_arg): Return NULL_RTX if argument
- size is zero.
- (pa_arg_partial_bytes): Don't call pa_function_arg_size twice.
- (pa_function_arg_size): Change return type to int. Return zero
- for arguments larger than 1 GB. Update comments.
+ * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
+ * doc/invoke.texi (RISC-V Options): Add sifive-p450,
+ sifive-p670.
-2023-04-15 Jakub Jelinek <jakub@redhat.com>
+2024-02-05 Monk Chiang <monk.chiang@sifive.com>
- PR tree-optimization/109154
- * tree-if-conv.cc (predicate_scalar_phi): For complex PHIs, emit just
- args_len - 1 COND_EXPRs rather than args_len. Formatting fix.
+ * config/riscv/riscv.md: Include sifive-p400.md.
+ * config/riscv/sifive-p400.md: New file.
+ * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
+ * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
+ Add sifive_p400.
+ * config/riscv/riscv.cc (sifive_p400_tune_info): New.
+ * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
+ * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
-2023-04-15 Jason Merrill <jason@redhat.com>
+2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
- PR c++/109514
- * gimple-ssa-warn-access.cc (pass_waccess::check_dangling_stores):
- Overhaul lhs_ref.ref analysis.
+ * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
+ Add missing ":SI" to the match_operator.
-2023-04-14 Richard Biener <rguenther@suse.de>
+2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
- PR tree-optimization/109502
- * tree-vect-stmts.cc (vectorizable_assignment): Fix
- check for conversion between mask and non-mask types.
+ * config/xtensa/xtensa.md (SHI): New mode iterator.
+ (2 split patterns related to constsynth):
+ Change to also accept HImode operands.
-2023-04-14 Jeff Law <jlaw@ventanamicro.com>
- Jakub Jelinek <jakub@redhat.com>
+2024-02-04 Jeff Law <jlaw@ventanamicro.com>
- PR target/108947
- PR target/109040
- * combine.cc (simplify_and_const_int_1): Compute nonzero_bits in
- word_mode rather than mode if WORD_REGISTER_OPERATIONS and mode is
- smaller than word_mode.
- * simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
- <case AND>: Likewise.
+ * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
+ similarly.
-2023-04-14 Jakub Jelinek <jakub@redhat.com>
+2024-02-04 Xi Ruoyao <xry111@xry111.site>
- * loop-iv.cc (iv_number_of_iterations): Use gen_int_mode instead
- of GEN_INT.
+ * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
+ incorrect expand.
+ * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
+ (elmsgnbit): Likewise.
+ (neg<mode:FVEC>2): New define_insn.
+ * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
+ are now instantiated in simd.md.
-2023-04-13 Andrew MacLeod <amacleod@redhat.com>
+2024-02-04 Xi Ruoyao <xry111@xry111.site>
- PR tree-optimization/108139
- PR tree-optimization/109462
- * gimple-range-cache.cc (ranger_cache::fill_block_cache): Remove
- equivalency check for PHI nodes.
- * gimple-range-fold.cc (fold_using_range::range_of_phi): Ensure def
- does not dominate single-arg equivalency edges.
+ * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
+ use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
+ MAX_MACHINE_MODE.
-2023-04-13 Richard Sandiford <richard.sandiford@arm.com>
+2024-02-04 Li Wei <liwei@loongson.cn>
- PR target/108910
- * config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Do
- not trust TYPE_ALIGN for pointer types; use POINTER_SIZE instead.
+ * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
+ (loongarch_expand_vselect_vconcat): Ditto.
+ (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
+ all 128-bit constant permutation situations.
+ (loongarch_expand_lsx_shuffle): Adjust and rename function name.
+ (loongarch_is_imm_set_shuffle): Renamed function name.
+ (loongarch_expand_vec_perm_even_odd): Function forward declaration.
+ (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
+ extract-even and extract-odd permutations.
+ (loongarch_is_odd_extraction): Delete.
+ (loongarch_is_even_extraction): Ditto.
+ (loongarch_expand_vec_perm_const): Adjust.
-2023-04-13 Richard Biener <rguenther@suse.de>
+2024-02-03 Jakub Jelinek <jakub@redhat.com>
- PR tree-optimization/109491
- * tree-ssa-sccvn.cc (expressions_equal_p): Restore the
- NULL operands test.
+ PR middle-end/113722
+ * wide-int.cc (wi::bswap_large): Rename third argument from
+ len to xlen and adjust use in safe_uhwi. Add len variable, set
+ it to BLOCKS_NEEDED (precision) and use it for clearing of val
+ and as canonize argument. Clear val using memset instead of
+ a loop.
-2023-04-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-02-03 Jakub Jelinek <jakub@redhat.com>
- PR target/109479
- * config/riscv/riscv-vector-builtins-types.def (vint8mf8_t): Fix predicate.
- (vint16mf4_t): Ditto.
- (vint32mf2_t): Ditto.
- (vint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint8mf8_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vuint64m1_t): Ditto.
- (vuint64m2_t): Ditto.
- (vuint64m4_t): Ditto.
- (vuint64m8_t): Ditto.
- (vfloat32mf2_t): Ditto.
- (vbool64_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (register_builtin_type): Add comments.
- (register_vector_type): Ditto.
- (check_required_extensions): Fix condition.
- * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ZVE64): Remove it.
- (RVV_REQUIRE_ELEN_64): New define.
- (RVV_REQUIRE_MIN_VLEN_64): Ditto.
- * config/riscv/riscv-vector-switch.def (TARGET_VECTOR_FP32): Remove it.
- (TARGET_VECTOR_FP64): Ditto.
- (ENTRY): Fix predicate.
- * config/riscv/vector-iterators.md: Fix predicate.
-
-2023-04-12 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109410
- * tree-ssa-reassoc.cc (build_and_add_sum): Split edge from entry
- block if first statement of the function is a call to returns_twice
- function.
-
-2023-04-12 Jakub Jelinek <jakub@redhat.com>
-
- PR target/109458
- * config/i386/i386.cc: Include rtl-error.h.
- (ix86_print_operand): For z modifier warning, use warning_for_asm
- if this_is_asm_operands. For Z modifier errors, use %c and code
- instead of hardcoded Z.
-
-2023-04-12 Costas Argyris <costas.argyris@gmail.com>
-
- * config/i386/x-mingw32-utf8: Remove extrataneous $@
-
-2023-04-12 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109462
- * gimple-range-cache.cc (ranger_cache::fill_block_cache): Don't
- check for equivalences if NAME is a phi node.
-
-2023-04-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109473
- * tree-vect-loop.cc (vect_create_epilog_for_reduction):
- Convert scalar result to the computation type before performing
- the reduction adjustment.
-
-2023-04-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109469
- * tree-vect-slp.cc (vect_slp_function): Skip region starts with
- a returns-twice call.
-
-2023-04-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109434
- * tree-ssa-dse.cc (initialize_ao_ref_for_dse): Properly
- handle possibly throwing calls when processing the LHS
- and may-defs are not OK.
-
-2023-04-11 Lin Sinan <mynameisxiaou@gmail.com>
-
- * config/riscv/predicates.md (uimm_extra_bit_or_twobits): Adjust
- predicate to avoid splitting arith constants.
-
-2023-04-11 Yanzhang Wang <yanzhang.wang@intel.com>
- Pan Li <pan2.li@intel.com>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- Kito Cheng <kito.cheng@sifive.com>
-
- PR target/109104
- * config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl): New.
- * config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): New.
- (emit_vlmax_vsetvl): Use emit_hard_vlmax_vsetvl.
- * config/riscv/riscv.cc (vector_zero_call_used_regs): New.
- (riscv_zero_call_used_regs): New.
- (TARGET_ZERO_CALL_USED_REGS): New.
-
-2023-04-11 Martin Liska <mliska@suse.cz>
-
- PR driver/108241
- * opts.cc (finish_options): Drop also
- x_flag_var_tracking_assignments.
-
-2023-04-11 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR tree-optimization/108888
- * tree-if-conv.cc (predicate_statements): Fix gimple call check.
-
-2023-04-11 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/108812
- * config/rs6000/vsx.md (vsx_sign_extend_qi_<mode>): Rename to...
- (vsx_sign_extend_v16qi_<mode>): ... this.
- (vsx_sign_extend_hi_<mode>): Rename to...
- (vsx_sign_extend_v8hi_<mode>): ... this.
- (vsx_sign_extend_si_v2di): Rename to...
- (vsx_sign_extend_v4si_v2di): ... this.
- (vsignextend_qi_<mode>): Remove.
- (vsignextend_hi_<mode>): Remove.
- (vsignextend_si_v2di): Remove.
- (vsignextend_v2di_v1ti): Remove.
- (*xxspltib_<mode>_split): Replace gen_vsx_sign_extend_qi_v2di with
- gen_vsx_sign_extend_v16qi_v2di and gen_vsx_sign_extend_qi_v4si
- with gen_vsx_sign_extend_v16qi_v4si.
- * config/rs6000/rs6000.md (split for DI constant generation):
- Replace gen_vsx_sign_extend_qi_si with gen_vsx_sign_extend_v16qi_si.
- (split for HSDI constant generation): Replace gen_vsx_sign_extend_qi_di
- with gen_vsx_sign_extend_v16qi_di and gen_vsx_sign_extend_qi_si
- with gen_vsx_sign_extend_v16qi_si.
- * config/rs6000/rs6000-builtins.def (__builtin_altivec_vsignextsb2d):
- Set bif-pattern to vsx_sign_extend_v16qi_v2di.
- (__builtin_altivec_vsignextsb2w): Set bif-pattern to
- vsx_sign_extend_v16qi_v4si.
- (__builtin_altivec_visgnextsh2d): Set bif-pattern to
- vsx_sign_extend_v8hi_v2di.
- (__builtin_altivec_vsignextsh2w): Set bif-pattern to
- vsx_sign_extend_v8hi_v4si.
- (__builtin_altivec_vsignextsw2d): Set bif-pattern to
- vsx_sign_extend_si_v2di.
- (__builtin_altivec_vsignext): Set bif-pattern to
- vsx_sign_extend_v2di_v1ti.
- * config/rs6000/rs6000-builtin.cc (lxvrse_expand_builtin): Replace
- gen_vsx_sign_extend_qi_v2di with gen_vsx_sign_extend_v16qi_v2di,
- gen_vsx_sign_extend_hi_v2di with gen_vsx_sign_extend_v8hi_v2di and
- gen_vsx_sign_extend_si_v2di with gen_vsx_sign_extend_v4si_v2di.
-
-2023-04-10 Michael Meissner <meissner@linux.ibm.com>
-
- PR target/70243
- * config/rs6000/vsx.md (vsx_fmav4sf4): Do not generate vmaddfp.
- (vsx_nfmsv4sf4): Do not generate vnmsubfp.
-
-2023-04-10 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/i386.h (PTA_GRANITERAPIDS): Add PTA_AMX_COMPLEX.
-
-2023-04-10 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Detect AMX-COMPLEX.
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA2_AMX_COMPLEX_SET,
- OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New.
- (ix86_handle_option): Handle -mamx-complex.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_AMX_COMPLEX.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- amx-complex.
- * config.gcc: Add amxcomplexintrin.h.
- * config/i386/cpuid.h (bit_AMX_COMPLEX): New.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Define
- __AMX_COMPLEX__.
- * config/i386/i386-isa.def (AMX_COMPLEX): Add DEF_PTA(AMX_COMPLEX).
- * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
- Handle amx-complex.
- * config/i386/i386.opt: Add option -mamx-complex.
- * config/i386/immintrin.h: Include amxcomplexintrin.h.
- * doc/extend.texi: Document amx-complex.
- * doc/invoke.texi: Document -mamx-complex.
- * doc/sourcebuild.texi: Document target amx-complex.
- * config/i386/amxcomplexintrin.h: New file.
-
-2023-04-08 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109392
- * tree-vect-generic.cc (tree_vec_extract): Handle failure
- of maybe_push_res_to_seq better.
-
-2023-04-08 Jakub Jelinek <jakub@redhat.com>
-
- * Makefile.in (CORETYPES_H): Depend on align.h, poly-int.h and
- poly-int-types.h.
- (SYSTEM_H): Depend on $(HASHTAB_H).
- * config/riscv/t-riscv (build/genrvv-type-indexer.o): Remove unused
- dependency on $(RTL_BASE_H), remove redundant dependency on
- insn-modes.h.
-
-2023-04-06 Richard Earnshaw <rearnsha@arm.com>
-
- PR target/107674
- * config/arm/arm.cc (arm_effective_regno): New function.
- (mve_vector_mem_operand): Use it.
-
-2023-04-06 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109417
- * gimple-range-gori.cc (gori_compute::may_recompute_p): Check if
- dependency is in SSA_NAME_FREE_LIST.
-
-2023-04-06 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/109427
- * params.opt (-param=vect-induction-float=):
- Fix option attribute typo for IntegerRange.
-
-2023-04-05 Jeff Law <jlaw@ventanamicro>
-
- PR target/108892
- * combine.cc (combine_instructions): Force re-recognition when
- after restoring the body of an insn to its original form.
-
-2023-04-05 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/108959
- * ipa-sra.cc (zap_useless_ipcp_results): New function.
- (process_isra_node_results): Call it.
-
-2023-04-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix incorrect operand order.
-
-2023-04-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+ * ggc-common.cc (gt_pch_save): Allow addr to be equal to
+ mmi.preferred_base + mmi.size - sizeof (void *).
- * config/riscv/riscv-vsetvl.cc
- (pass_vsetvl::compute_local_backward_infos): Update user vsetvl in local
- demand fusion.
+2024-02-03 Xi Ruoyao <xry111@xry111.site>
-2023-04-05 Li Xu <xuli1@eswincomputing.com>
+ * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
+ * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
+ the ODR-violating locale declaration.
- * config/riscv/riscv-vector-builtins.def: Fix typo.
- * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Ditto.
- * config/riscv/vector-iterators.md: Ditto.
+2024-02-02 Tamar Christina <tamar.christina@arm.com>
-2023-04-04 Hans-Peter Nilsson <hp@axis.com>
+ PR tree-optimization/113588
+ PR tree-optimization/113467
+ * tree-vect-data-refs.cc
+ (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
+ (vect_analyze_early_break_dependences): Update comments.
- * doc/md.texi (Including Patterns): Fix page break.
+2024-02-02 John David Anglin <danglin@gcc.gnu.org>
-2023-04-04 Jakub Jelinek <jakub@redhat.com>
+ PR target/59778
+ * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
+ and PA_BUILTIN_SET_FPSR builtins.
+ * (pa_builtins_icode): Declare.
+ * (def_builtin, pa_fpu_init_builtins): New.
+ * (pa_init_builtins): Initialize FPU builtins.
+ * (pa_builtin_decl, pa_expand_builtin_1): New.
+ * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
+ PA_BUILTIN_SET_FPSR builtins.
+ * (pa_atomic_assign_expand_fenv): New.
+ * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
+ UNSPECV constants.
+ (get_fpsr, put_fpsr): New expanders.
+ (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
+ insn patterns.
- PR tree-optimization/109386
- * range-op-float.cc (foperator_lt::op1_range, foperator_lt::op2_range,
- foperator_le::op1_range, foperator_le::op2_range,
- foperator_gt::op1_range, foperator_gt::op2_range,
- foperator_ge::op1_range, foperator_ge::op2_range): Make r varying for
- BRS_FALSE case even if the other op is maybe_isnan, not just
- known_isnan.
- (foperator_unordered_lt::op1_range, foperator_unordered_lt::op2_range,
- foperator_unordered_le::op1_range, foperator_unordered_le::op2_range,
- foperator_unordered_gt::op1_range, foperator_unordered_gt::op2_range,
- foperator_unordered_ge::op1_range, foperator_unordered_ge::op2_range):
- Make r varying for BRS_TRUE case even if the other op is maybe_isnan,
- not just known_isnan.
+2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-04-04 Marek Polacek <polacek@redhat.com>
+ PR target/113697
+ * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
- PR sanitizer/109107
- * fold-const.cc (fold_binary_loc): Use TYPE_OVERFLOW_SANITIZED
- when associating.
- * match.pd: Use TYPE_OVERFLOW_SANITIZED.
+2024-02-02 Jonathan Wakely <jwakely@redhat.com>
-2023-04-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
+ * doc/extend.texi (Common Type Attributes): Fix typo in
+ description of hardbool.
- * config/arm/mve.md (mve_vcvtq_n_to_f_<supf><mode>): Swap operands.
- (mve_vcreateq_f<mode>): Swap operands.
+2024-02-02 Jakub Jelinek <jakub@redhat.com>
-2023-04-04 Andrew Stubbs <ams@codesourcery.com>
+ PR tree-optimization/113692
+ * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
+ from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
+ final_cast_p.
- * config/gcn/gcn-valu.md (one_cmpl<mode>2<exec>): New.
+2024-02-02 Jakub Jelinek <jakub@redhat.com>
-2023-04-04 Jakub Jelinek <jakub@redhat.com>
+ PR middle-end/113699
+ * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
+ uninitialized large/huge _BitInt SSA_NAME inputs.
- PR target/109384
- * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
- Reword diagnostics about zfinx conflict with f, formatting fixes.
+2024-02-02 Jakub Jelinek <jakub@redhat.com>
-2023-04-04 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+ PR middle-end/113705
+ * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
+ around wi::to_wide in order to compare value in prec precision.
- * config/sol2.h (LIB_SPEC): Don't link with -lpthread.
+2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
-2023-04-04 Richard Biener <rguenther@suse.de>
+ Revert:
+ 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR tree-optimization/109304
- * tree-profile.cc (tree_profiling): Use symtab node
- availability to decide whether to skip adjusting calls.
- Do not adjust calls to internal functions.
+ * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
-2023-04-04 Kewen Lin <linkw@linux.ibm.com>
+2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR target/108807
- * config/rs6000/rs6000.cc (rs6000_expand_vector_set_var_p9): Fix gen
- function for permutation control vector by considering big endianness.
+ * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
-2023-04-04 Kewen Lin <linkw@linux.ibm.com>
+2024-02-02 Pan Li <pan2.li@intel.com>
- PR target/108699
- * config/rs6000/altivec.md (*p9v_parity<mode>2): Rename to ...
- (rs6000_vprtyb<mode>2): ... this.
- * config/rs6000/rs6000-builtins.def (VPRTYBD): Replace parityv2di2 with
- rs6000_vprtybv2di2.
- (VPRTYBW): Replace parityv4si2 with rs6000_vprtybv4si2.
- (VPRTYBQ): Replace parityv1ti2 with rs6000_vprtybv1ti2.
- * config/rs6000/vector.md (parity<mode>2 with VEC_IP): Expand with
- popcountv16qi2 and the corresponding rs6000_vprtyb<mode>2.
+ * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
+ (riscv_pass_by_reference): Ditto.
+ (riscv_fntype_abi): Ditto.
-2023-04-04 Hans-Peter Nilsson <hp@axis.com>
- Sandra Loosemore <sandra@codesourcery.com>
+2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * doc/md.texi (Insn Splitting): Tweak wording for readability.
+ * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
+ (pre_vsetvl::cleaup): Remove vsetvl_pre.
+ (pre_vsetvl::remove_vsetvl_pre_insns): New function.
-2023-04-03 Martin Jambor <mjambor@suse.cz>
+2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
- PR ipa/109303
- * ipa-prop.cc (determine_known_aggregate_parts): Check that the
- offset + size will be representable in unsigned int.
+ * config/loongarch/larchintrin.h
+ (__frecipe_s): Update function return type.
+ (__frecipe_d): Ditto.
+ (__frsqrte_s): Ditto.
+ (__frsqrte_d): Ditto.
-2023-04-03 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+2024-02-02 Li Wei <liwei@loongson.cn>
- * configure.ac (ZSTD_LIB): Move before zstd.h check.
- Unset gcc_cv_header_zstd_h without libzstd.
- * configure: Regenerate.
+ * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
+ (loongarch_vector_costs::add_stmt_cost): Adjust.
-2023-04-03 Martin Liska <mliska@suse.cz>
+2024-02-02 Xi Ruoyao <xry111@xry111.site>
- * doc/invoke.texi: Document new param.
+ * config/loongarch/loongarch.md (unspec): Add
+ UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
+ (la_pcrel64_two_parts): New define_insn.
+ * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
+ typo in the comment.
+ (loongarch_call_tls_get_addr): If -mcmodel=extreme
+ -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
+ addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
+ note to allow CSE addressing __tls_get_addr.
+ (loongarch_legitimize_tls_address): If -mcmodel=extreme
+ -mexplicit-relocs={always,auto}, address TLS IE symbols with
+ la_pcrel64_two_parts.
+ (loongarch_split_symbol): If -mcmodel=extreme
+ -mexplicit-relocs={always,auto}, address symbols with
+ la_pcrel64_two_parts.
+ (loongarch_output_mi_thunk): Clean up unreachable code. If
+ -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
+ thunks with la_pcrel64_two_parts.
-2023-04-03 Cupertino Miranda <cupertino.miranda@oracle.com>
+2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
- * doc/sourcebuild.texi (const_volatile_readonly_section): Document
- new check_effective_target function.
+ * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
+ Add support for call36.
-2023-04-03 Li Xu <xuli1@eswincomputing.com>
+2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
- * config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo.
- (vfloat32m8_t): Likewise
+ * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
+ When the code model of the symbol is extreme and -mexplicit-relocs=auto,
+ the macro instruction loading symbol address is not applicable.
+ (loongarch_call_tls_get_addr): Adjust code.
+ (loongarch_legitimize_tls_address): Likewise.
-2023-04-03 liuhongt <hongtao.liu@intel.com>
+2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
- * doc/md.texi: Document signbitm2.
+ * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
+ Add function declaration.
+ * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
+ For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
+ is not allowed
+ (loongarch_load_tls): Added macro support in extreme mode.
+ (loongarch_call_tls_get_addr): Likewise.
+ (loongarch_legitimize_tls_address): Likewise.
+ (loongarch_force_address): Likewise.
+ (loongarch_legitimize_move): Likewise.
+ (loongarch_output_mi_thunk): Likewise.
+ (loongarch_option_override_internal): Remove the code that detects
+ explicit relocs status.
+ (loongarch_handle_model_attribute): Likewise.
+ * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
+ * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
+ (symbolic_off64_or_reg_operand): Likewise.
+
+2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch.cc (loongarch_load_tls):
+ Load all types of tls symbols through one function.
+ (loongarch_got_load_tls_gd): Delete.
+ (loongarch_got_load_tls_ld): Delete.
+ (loongarch_got_load_tls_ie): Delete.
+ (loongarch_got_load_tls_le): Delete.
+ (loongarch_call_tls_get_addr): Modify the called function name.
+ (loongarch_legitimize_tls_address): Likewise.
+ * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
+ (@load_tls<mode>): New template.
+ (@got_load_tls_ld<mode>): Delete.
+ (@got_load_tls_le<mode>): Delete.
+ (@got_load_tls_ie<mode>): Delete.
-2023-04-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
+2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
- * config/riscv/vector.md: Fix RA constraint.
+ * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
+ (loongarch_legitimize_address): Add logical transformation code.
-2023-04-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+2024-02-01 Marek Polacek <polacek@redhat.com>
- * config/riscv/riscv-protos.h (gen_avl_for_scalar_move): New function.
- * config/riscv/riscv-v.cc (gen_avl_for_scalar_move): New function.
- * config/riscv/vector.md: Fix scalar move bug.
+ * doc/invoke.texi: Update -Wdangling-reference documentation.
-2023-04-01 Jakub Jelinek <jakub@redhat.com>
+2024-02-01 Uros Bizjak <ubizjak@gmail.com>
- * range-op-float.cc (foperator_equal::fold_range): If at least
- one of the op ranges is not singleton and neither is NaN and all
- 4 bounds are zero, return [1, 1].
- (foperator_not_equal::fold_range): In the same case return [0, 0].
+ PR target/113701
+ * config/i386/i386.md (*cmp<dwi>_doubleword):
+ Do not force SUBREG pieces to pseudos.
-2023-04-01 Jakub Jelinek <jakub@redhat.com>
+2024-02-01 John David Anglin <danglin@gcc.gnu.org>
- * range-op-float.cc (foperator_equal::fold_range): Perform the
- non-singleton handling regardless of maybe_isnan (op1, op2).
- (foperator_not_equal::fold_range): Likewise.
- (foperator_lt::fold_range, foperator_le::fold_range,
- foperator_gt::fold_range, foperator_ge::fold_range): Perform the
- real_* comparison check which results in range_false (type)
- even if maybe_isnan (op1, op2). Simplify.
- (foperator_ltgt): New class.
- (fop_ltgt): New variable.
- (floating_op_table::floating_op_table): Handle LTGT_EXPR using
- fop_ltgt.
+ * config/pa/pa.md (atomic_storedi_1): Fix bug in
+ alternative 1.
-2023-04-01 Jakub Jelinek <jakub@redhat.com>
+2024-02-01 Georg-Johann Lay <avr@gjlay.de>
- PR target/109254
- * builtins.cc (apply_args_size): If targetm.calls.get_raw_arg_mode
- returns VOIDmode, handle it like if the register isn't used for
- passing arguments at all.
- (apply_result_size): If targetm.calls.get_raw_result_mode returns
- VOIDmode, handle it like if the register isn't used for returning
- results at all.
- * target.def (get_raw_result_mode, get_raw_arg_mode): Document what it
- means to return VOIDmode.
- * doc/tm.texi: Regenerated.
- * config/aarch64/aarch64.cc (aarch64_function_value_regno_p): Return
- TARGET_SVE for P0_REGNUM.
- (aarch64_function_arg_regno_p): Also return true for p0-p3.
- (aarch64_get_reg_raw_mode): Return VOIDmode for PR_REGNUM_P regs.
+ * config/avr/avr.cc: Tabify.
-2023-03-31 Vladimir N. Makarov <vmakarov@redhat.com>
+2024-02-01 Richard Ball <richard.ball@arm.com>
- * lra-constraints.cc: (combine_reload_insn): New function.
+ PR tree-optimization/111268
+ * tree-vect-slp.cc (vectorizable_slp_permutation_1):
+ Add variable-length check for vector input arguments
+ to a function.
-2023-03-31 Jakub Jelinek <jakub@redhat.com>
+2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
- PR tree-optimization/91645
- * range-op-float.cc (foperator_unordered_lt::fold_range,
- foperator_unordered_le::fold_range,
- foperator_unordered_gt::fold_range,
- foperator_unordered_ge::fold_range,
- foperator_unordered_equal::fold_range): Call the ordered
- fold_range on ranges with cleared NaNs.
- * value-query.cc (range_query::get_tree_range): Handle also
- COMPARISON_CLASS_P trees.
+ * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
+ hard-code number of SGPR/VGPR/AVGPR registers.
+ * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
+ SGPR/VGPR/AVGPR registers.
-2023-03-31 Kito Cheng <kito.cheng@sifive.com>
- Andrew Pinski <pinskia@gmail.com>
+2024-02-01 Monk Chiang <monk.chiang@sifive.com>
- PR target/109328
- * config/riscv/t-riscv: Add missing dependencies.
+ * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
+ attribute, and include sifive-p600.md.
+ * config/riscv/generic-ooo.md: Update type attribute.
+ * config/riscv/generic.md: Update type attribute.
+ * config/riscv/sifive-7.md: Update type attribute.
+ * config/riscv/sifive-p600.md: New file.
+ * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
+ * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
+ Add sifive_p600.
+ * config/riscv/riscv.cc (sifive_p600_tune_info): New.
+ * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
+ * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
-2023-03-31 liuhongt <hongtao.liu@intel.com>
+2024-02-01 Monk Chiang <monk.chiang@sifive.com>
- * config/i386/i386.cc (inline_memory_move_cost): Return 100
- for MASK_REGS when MODE_SIZE > 8.
+ * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
+ Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
+ * config/riscv/riscv.opt: New macro for 7 new unprivileged
+ extensions.
+ * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
+ Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
-2023-03-31 liuhongt <hongtao.liu@intel.com>
+2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
- PR target/85048
- * config/i386/i386-builtin.def (BDESC): Adjust icode name from
- ufloat/ufix to floatuns/fixuns.
- * config/i386/i386-expand.cc
- (ix86_expand_vector_convert_uns_vsivsf): Adjust comments.
- * config/i386/sse.md
- (ufloat<sseintvecmodelower><mode>2<mask_name><round_name>):
- Renamed to ..
- (<mask_codefor>floatuns<sseintvecmodelower><mode>2<mask_name><round_name>):.. this.
- (<mask_codefor><avx512>_ufix_notrunc<sf2simodelower><mode><mask_name><round_name>):
- Renamed to ..
- (<mask_codefor><avx512>_fixuns_notrunc<sf2simodelower><mode><mask_name><round_name>):
- .. this.
- (<fixsuffix>fix_truncv16sfv16si2<mask_name><round_saeonly_name>):
- Renamed to ..
- (fix<fixunssuffix>_truncv16sfv16si2<mask_name><round_saeonly_name>):.. this.
- (ufloat<si2dfmodelower><mode>2<mask_name>): Renamed to ..
- (floatuns<si2dfmodelower><mode>2<mask_name>): .. this.
- (ufloatv2siv2df2<mask_name>): Renamed to ..
- (<mask_codefor>floatunsv2siv2df2<mask_name>): .. this.
- (ufix_notrunc<mode><si2dfmodelower>2<mask_name><round_name>):
- Renamed to ..
- (fixuns_notrunc<mode><si2dfmodelower>2<mask_name><round_name>):
- .. this.
- (ufix_notruncv2dfv2si2): Renamed to ..
- (fixuns_notruncv2dfv2si2):.. this.
- (ufix_notruncv2dfv2si2_mask): Renamed to ..
- (fixuns_notruncv2dfv2si2_mask): .. this.
- (*ufix_notruncv2dfv2si2_mask_1): Renamed to ..
- (*fixuns_notruncv2dfv2si2_mask_1): .. this.
- (ufix_truncv2dfv2si2): Renamed to ..
- (*fixuns_truncv2dfv2si2): .. this.
- (ufix_truncv2dfv2si2_mask): Renamed to ..
- (fixuns_truncv2dfv2si2_mask): .. this.
- (*ufix_truncv2dfv2si2_mask_1): Renamed to ..
- (*fixuns_truncv2dfv2si2_mask_1): .. this.
- (ufix_truncv4dfv4si2<mask_name>): Renamed to ..
- (fixuns_truncv4dfv4si2<mask_name>): .. this.
- (ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
- Renamed to ..
- (fixuns_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
- .. this.
- (ufix_trunc<mode><sseintvecmodelower>2<mask_name>): Renamed to ..
- (<mask_codefor>fixuns_trunc<mode><sseintvecmodelower>2<mask_name>):
- .. this.
-
-2023-03-30 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109154
- * gimple-range-gori.cc (gori_compute::may_recompute_p): Add depth limit.
- * gimple-range-gori.h (may_recompute_p): Add depth param.
- * params.opt (ranger-recompute-depth): New param.
-
-2023-03-30 Jason Merrill <jason@redhat.com>
-
- PR c++/107897
- PR c++/108887
- * cgraph.h: Move reset() from cgraph_node to symtab_node.
- * cgraphunit.cc (symtab_node::reset): Adjust. Also call
- remove_from_same_comdat_group.
-
-2023-03-30 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/107561
- * gimple-ssa-warn-access.cc (get_size_range): Add flags
- argument and pass it on.
- (check_access): When querying for the size range pass
- SR_ALLOW_ZERO when the known destination size is zero.
-
-2023-03-30 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109342
- * tree-ssa-sccvn.cc (vn_nary_op_get_predicated_value): New
- overload for edge. When that edge is a backedge use
- dominated_by_p directly.
-
-2023-03-30 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386-expand.cc (expand_vec_perm_blend): Generate
- vpblendd instead of vpblendw for V4SI under avx2.
-
-2023-03-29 Hans-Peter Nilsson <hp@axis.com>
-
- * config/cris/cris.cc (cris_rtx_costs) [CONST_INT]: Return 0
- for many quick operands, for register-sized modes.
-
-2023-03-29 Jiawei <jiawei@iscas.ac.cn>
-
- * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
- New check.
-
-2023-03-29 Martin Liska <mliska@suse.cz>
-
- PR bootstrap/109310
- * configure.ac: Emit a warning for deprecated option
- --enable-link-mutex.
- * configure: Regenerate.
+ * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
+ -static-libasan. Add missing whitespace.
-2023-03-29 Richard Biener <rguenther@suse.de>
+2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
- PR tree-optimization/109331
- * tree-ssa-forwprop.cc (pass_forwprop::execute): When we
- discover a taken edge make sure to cleanup the CFG.
+ * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
+ (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
+ Don't 'define_constants'.
-2023-03-29 Richard Biener <rguenther@suse.de>
+2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
- PR tree-optimization/109327
- * tree-ssa-forwprop.cc (pass_forwprop::execute): Deal with
- already removed stmts when draining to_remove.
+ * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
-2023-03-29 Richard Biener <rguenther@suse.de>
+2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
- PR ipa/106124
- * dwarf2out.cc (lookup_type_die): Reset TREE_ASM_WRITTEN
- so we can re-create the DIE for the type if required.
+ * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
+ [TARGET_RDNA3]: Adjust.
-2023-03-29 Jakub Jelinek <jakub@redhat.com>
- Richard Biener <rguenther@suse.de>
+2024-02-01 Richard Biener <rguenther@suse.de>
- PR tree-optimization/109301
- * tree-ssa-math-opts.cc (pass_data_cse_sincos): Change
- properties_provided from PROP_gimple_opt_math to 0.
- (pass_data_expand_powcabs): Change properties_provided from 0 to
- PROP_gimple_opt_math.
-
-2023-03-29 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109154
- * tree-if-conv.cc (gen_phi_arg_condition): Handle single
- inverted condition specially by inverting at the caller.
- (gen_phi_arg_condition): Swap COND_EXPR arms if requested.
-
-2023-03-28 David Malcolm <dmalcolm@redhat.com>
-
- PR c/107002
- * diagnostic-show-locus.cc (column_range::column_range): Factor
- out assertion conditional into...
- (column_range::valid_p): ...this new function.
- (line_corrections::add_hint): Don't attempt to consolidate hints
- if it would lead to invalid column_range instances.
-
-2023-03-28 Kito Cheng <kito.cheng@sifive.com>
-
- PR target/109312
- * config/riscv/riscv-c.cc (riscv_ext_version_value): New.
- (riscv_cpu_cpp_builtins): Define __riscv_v_intrinsic and
- minor refactor.
-
-2023-03-28 Alexander Monakov <amonakov@ispras.ru>
-
- PR rtl-optimization/109187
- * haifa-sched.cc (autopref_rank_for_schedule): Avoid use of overflowing
- subtraction in three-way comparison.
-
-2023-03-28 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/109265
- PR tree-optimization/109274
- * gimple-range-gori.cc (gori_compute::compute_operand_range): Do
- not create a relation record is op1 and op2 are the same symbol.
- (gori_compute::compute_operand1_range): Pass op1 == op2 to the
- handler for this stmt, but create a new record only if this statement
- generates a relation based on the ranges.
- (gori_compute::compute_operand2_range): Ditto.
- * value-relation.h (value_relation::set_relation): Always create the
- record that is requested.
-
-2023-03-28 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/107087
- * tree-ssa-forwprop.cc (pass_forwprop::execute): Track
- executable regions to avoid useless work and to better
- propagate degenerate PHIs.
-
-2023-03-28 Costas Argyris <costas.argyris@gmail.com>
-
- * config/i386/x-mingw32-utf8: update comments.
-
-2023-03-28 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/109072
- * config/aarch64/aarch64-protos.h (aarch64_vector_load_decl): Declare.
- * config/aarch64/aarch64.h (machine_function::vector_load_decls): New
- variable.
- * config/aarch64/aarch64-builtins.cc (aarch64_record_vector_load_arg):
- New function.
- (aarch64_general_gimple_fold_builtin): Delay folding of vld1 until
- after inlining. Record which decls are loaded from. Fix handling
- of vops for loads and stores.
- * config/aarch64/aarch64.cc (aarch64_vector_load_decl): New function.
- (aarch64_accesses_vector_load_decl_p): Likewise.
- (aarch64_vector_costs::m_stores_to_vector_load_decl): New member
- variable.
- (aarch64_vector_costs::add_stmt_cost): If the function has a vld1
- that loads from a decl, treat vector stores to those decls as
- zero cost.
- (aarch64_vector_costs::finish_cost): ...and in that case,
- if the vector code does nothing more than a store, give the
- prologue a zero cost as well.
-
-2023-03-28 Richard Biener <rguenther@suse.de>
-
- PR bootstrap/84402
- PR tree-optimization/108129
- * genmatch.cc (lower_for): For (match ...) delay
- substituting into the match operator if possible.
- (dt_operand::gen_gimple_expr): For user_id look at the
- first substitute for determining how to access operands.
- (dt_operand::gen_generic_expr): Likewise.
- (dt_node::gen_kids): Properly sort user_ids according
- to their substitutes.
- (dt_node::gen_kids_1): Code-generate user_id matching.
-
-2023-03-28 Jakub Jelinek <jakub@redhat.com>
- Jonathan Wakely <jwakely@redhat.com>
-
- * gcov-tool.cc (do_merge, do_merge_stream, do_rewrite, do_overlap):
- Use subcommand rather than sub-command in function comments.
-
-2023-03-28 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109154
- * value-range.h (frange::flush_denormals_to_zero): Make it public
- rather than private.
- * value-range.cc (frange::set): Don't call flush_denormals_to_zero
- here.
- * range-op-float.cc (range_operator_float::fold_range): Call
- flush_denormals_to_zero.
-
-2023-03-28 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/106190
- * sanopt.cc (pass_sanopt::execute): Return TODO_cleanup_cfg if any
- of the IFN_{UB,HWA,A}SAN_* internal fns are lowered.
-
-2023-03-28 Jakub Jelinek <jakub@redhat.com>
-
- * range-op-float.cc (float_widen_lhs_range): Use pass get_nan_state
- as 4th argument to set to avoid clear_nan and union_ calls.
-
-2023-03-28 Jakub Jelinek <jakub@redhat.com>
-
- PR target/109276
- * config/i386/i386.cc (assign_386_stack_local): For DImode
- with SLOT_FLOATxFDI_387 and -m32 -mpreferred-stack-boundary=2 pass
- align 32 rather than 0 to assign_stack_local.
-
-2023-03-28 Eric Botcazou <ebotcazou@adacore.com>
-
- PR target/109140
- * config/sparc/sparc.cc (sparc_expand_vcond): Call signed_condition
- on operand #3 to get the final condition code. Use std::swap.
- * config/sparc/sparc.md (vcondv8qiv8qi): New VIS 4 expander.
- (fucmp<gcond:code>8<P:mode>_vis): Move around.
- (fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis): Likewise.
- (vcondu<GCM:mode><GCM:mode>): New VIS 4 expander.
-
-2023-03-28 Eric Botcazou <ebotcazou@adacore.com>
-
- * doc/gm2.texi: Add missing Next, Previous and Top fields to most
- top-level sections.
-
-2023-03-28 Costas Argyris <costas.argyris@gmail.com>
-
- * config.host: Pull in i386/x-mingw32-utf8 Makefile
- fragment and reference utf8rc-mingw32.o explicitly
- for mingw hosts.
- * config/i386/sym-mingw32.cc: prevent name mangling of
- stub symbol.
- * config/i386/x-mingw32-utf8: Make utf8rc-mingw32.o
- depend on manifest file explicitly.
-
-2023-03-28 Richard Biener <rguenther@suse.de>
+ PR tree-optimization/113693
+ * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
+ data when available.
- Revert:
- 2023-03-27 Richard Biener <rguenther@suse.de>
+2024-02-01 Jakub Jelinek <jakub@redhat.com>
+ Jason Merrill <jason@redhat.com>
- PR rtl-optimization/109237
- * cfgcleanup.cc (bb_is_just_return): Walk insns backwards.
+ PR c++/113531
+ * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
+ on variables which were promoted to TREE_STATIC.
-2023-03-28 Richard Biener <rguenther@suse.de>
+2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
+ Richard Biener <rguenther@suse.de>
- * common.opt (gdwarf): Remove Negative(gdwarf-).
+ PR target/113560
+ * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
+ information via tree_non_zero_bits to check if this operand
+ is suitably extended for a widening (or highpart) multiplication.
+ (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
+ isn't already of the claimed type.
-2023-03-28 Richard Biener <rguenther@suse.de>
+2024-02-01 Edwin Lu <ewlu@rivosinc.com>
- * common.opt (gdwarf): Add RejectNegative.
- (gdwarf-): Likewise.
- (ggdb): Likewise.
- (gvms): Likewise.
+ Revert:
+ 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
-2023-03-28 Hans-Peter Nilsson <hp@axis.com>
+ * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
+ (generic_ooo_branch): ditto
+ * config/riscv/generic.md (generic_sfb_alu): ditto
+ (generic_fmul_half): ditto
+ * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
+ * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
+ (sifive_7_popcount): ditto
+ * config/riscv/vector.md: change rdfrm to fmove
+ * config/riscv/zc.md: change pushpop to load/store
- * config/cris/constraints.md ("T"): Correct to
- define_memory_constraint.
+2024-02-01 Edwin Lu <ewlu@rivosinc.com>
-2023-03-28 Hans-Peter Nilsson <hp@axis.com>
+ Revert:
+ 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
+ Robin Dapp <rdapp.gcc@gmail.com>
+
+ * config/riscv/generic-ooo.md (generic_ooo): Move reservation
+ (generic_ooo_vec_load): ditto
+ (generic_ooo_vec_store): ditto
+ (generic_ooo_vec_loadstore_seg): ditto
+ (generic_ooo_vec_alu): ditto
+ (generic_ooo_vec_fcmp): ditto
+ (generic_ooo_vec_imul): ditto
+ (generic_ooo_vec_fadd): ditto
+ (generic_ooo_vec_fmul): ditto
+ (generic_ooo_crypto): ditto
+ (generic_ooo_perm): ditto
+ (generic_ooo_vec_reduction): ditto
+ (generic_ooo_vec_ordered_reduction): ditto
+ (generic_ooo_vec_idiv): ditto
+ (generic_ooo_vec_float_divsqrt): ditto
+ (generic_ooo_vec_mask): ditto
+ (generic_ooo_vec_vesetvl): ditto
+ (generic_ooo_vec_setrm): ditto
+ (generic_ooo_vec_readlen): ditto
+ * config/riscv/riscv.md: include generic-vector-ooo
+ * config/riscv/generic-vector-ooo.md: New file. to here
+
+2024-02-01 Edwin Lu <ewlu@rivosinc.com>
- * config/cris/cris.md (BW2): New mode-iterator.
- (lra_szext_decomposed, lra_szext_decomposed_indirect_with_offset): New
- peephole2s.
+ Revert:
+ 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
-2023-03-28 Hans-Peter Nilsson <hp@axis.com>
+ * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
- * config/cris/cris.md ("*add<mode>3_addi"): Improve to bail only
- for possible eliminable compares.
+2024-02-01 Edwin Lu <ewlu@rivosinc.com>
-2023-03-28 Hans-Peter Nilsson <hp@axis.com>
+ * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
- * config/cris/constraints.md ("R"): Remove unused constraint.
+2024-02-01 Edwin Lu <ewlu@rivosinc.com>
+ Robin Dapp <rdapp.gcc@gmail.com>
-2023-03-27 Jonathan Wakely <jwakely@redhat.com>
+ * config/riscv/generic-ooo.md (generic_ooo): Move reservation
+ (generic_ooo_vec_load): ditto
+ (generic_ooo_vec_store): ditto
+ (generic_ooo_vec_loadstore_seg): ditto
+ (generic_ooo_vec_alu): ditto
+ (generic_ooo_vec_fcmp): ditto
+ (generic_ooo_vec_imul): ditto
+ (generic_ooo_vec_fadd): ditto
+ (generic_ooo_vec_fmul): ditto
+ (generic_ooo_crypto): ditto
+ (generic_ooo_perm): ditto
+ (generic_ooo_vec_reduction): ditto
+ (generic_ooo_vec_ordered_reduction): ditto
+ (generic_ooo_vec_idiv): ditto
+ (generic_ooo_vec_float_divsqrt): ditto
+ (generic_ooo_vec_mask): ditto
+ (generic_ooo_vec_vesetvl): ditto
+ (generic_ooo_vec_setrm): ditto
+ (generic_ooo_vec_readlen): ditto
+ * config/riscv/riscv.md: include generic-vector-ooo
+ * config/riscv/generic-vector-ooo.md: New file. to here
- PR gcov-profile/109297
- * gcov-tool.cc (merge_usage): Fix "subcomand" typo.
- (merge_stream_usage): Likewise.
- (overlap_usage): Likewise.
+2024-02-01 Edwin Lu <ewlu@rivosinc.com>
-2023-03-27 Christoph Müllner <christoph.muellner@vrull.eu>
+ * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
+ (generic_ooo_branch): ditto
+ * config/riscv/generic.md (generic_sfb_alu): ditto
+ (generic_fmul_half): ditto
+ * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
+ * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
+ (sifive_7_popcount): ditto
+ * config/riscv/vector.md: change rdfrm to fmove
+ * config/riscv/zc.md: change pushpop to load/store
- PR target/109296
- * config/riscv/thead.md: Add missing mode specifiers.
+2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
-2023-03-27 Philipp Tomsich <philipp.tomsich@vrull.eu>
- Jiangning Liu <jiangning.liu@amperecomputing.com>
- Manolis Tsamis <manolis.tsamis@vrull.eu>
+ PR target/113657
+ * config/aarch64/aarch64-simd.md (split for movv8di):
+ For strict aligned mode, use DImode instead of TImode.
- * config/aarch64/aarch64.cc: Update vector costs for ampere1.
+2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
-2023-03-27 Richard Biener <rguenther@suse.de>
+ PR middle-end/113607
+ * match.pd: Make sure else values match when folding a
+ vec_cond into a conditional operation.
- PR rtl-optimization/109237
- * cfgcleanup.cc (bb_is_just_return): Walk insns backwards.
+2024-01-31 Marek Polacek <polacek@redhat.com>
-2023-03-27 Richard Biener <rguenther@suse.de>
+ * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
- PR lto/109263
- * lto-wrapper.cc (run_gcc): Parse alternate debug options
- as well, they always enable debug.
+2024-01-31 Tamar Christina <tamar.christina@arm.com>
+ Matthew Malcomson <matthew.malcomson@arm.com>
-2023-03-27 Kewen Lin <linkw@linux.ibm.com>
+ PR sanitizer/112644
+ * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
+ memcmp.
+ * builtins.cc (expand_builtin): Include HWASAN when checking for
+ builtin inlining.
- PR target/109167
- * config/rs6000/emmintrin.h (_mm_bslli_si128): Move the implementation
- from ...
- (_mm_slli_si128): ... here. Change to call _mm_bslli_si128 directly.
+2024-01-31 Richard Biener <rguenther@suse.de>
-2023-03-27 Kewen Lin <linkw@linux.ibm.com>
+ PR middle-end/110176
+ * match.pd (zext (bool) <= (int) 4294967295u): Make sure
+ to match INTEGER_CST only without outstanding conversion.
- PR target/109082
- * config/rs6000/emmintrin.h (_mm_bslli_si128): Check __N is not less
- than zero when calling vec_sld.
- (_mm_bsrli_si128): Return __A if __N is zero, check __N is bigger than
- zero when calling vec_sld.
- (_mm_slli_si128): Return __A if _imm5 is zero, check _imm5 is bigger
- than zero when calling vec_sld.
+2024-01-31 Alex Coplan <alex.coplan@arm.com>
-2023-03-27 Sandra Loosemore <sandra@codesourcery.com>
+ PR target/111677
+ * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
+ V16QImode for the full 16-byte FPR saves in the vector PCS case.
- * doc/generic.texi (OpenMP): Document OMP_SIMD, OMP_DISTRIBUTE,
- OMP_TASKLOOP, and OMP_LOOP with OMP_FOR. Document how collapsed
- loops are represented and which fields are vectors. Add
- documentation for OMP_FOR_PRE_BODY field. Document internal
- form of non-rectangular loops and OMP_FOR_NON_RECTANGULAR.
- * tree.def (OMP_FOR): Make documentation consistent with the
- Texinfo manual, to fill some gaps and correct errors.
+2024-01-31 Richard Biener <rguenther@suse.de>
-2023-03-26 Andreas Schwab <schwab@linux-m68k.org>
+ PR tree-optimization/111444
+ * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
+ vn_reference_lookup_2 when optimistically skipping may-defs.
- PR target/106282
- * config/m68k/m68k.h (FINAL_PRESCAN_INSN): Define.
- * config/m68k/m68k.cc (m68k_final_prescan_insn): Define.
- (handle_move_double): Call it before handle_movsi.
- * config/m68k/m68k-protos.h: Declare it.
+2024-01-31 Richard Biener <rguenther@suse.de>
-2023-03-26 Jakub Jelinek <jakub@redhat.com>
+ PR tree-optimization/113630
+ * tree-ssa-pre.cc (compute_avail): Avoid registering a
+ reference with a representation with not matching base
+ access size.
- PR tree-optimization/109230
- * match.pd (fneg/fadd simplify): Verify also odd permutation indexes.
+2024-01-31 Jakub Jelinek <jakub@redhat.com>
-2023-03-26 Jakub Jelinek <jakub@redhat.com>
+ PR rtl-optimization/113656
+ * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
+ <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
- PR ipa/105685
- * predict.cc (compute_function_frequency): Don't call
- warn_function_cold if function already has cold attribute.
+2024-01-31 Jakub Jelinek <jakub@redhat.com>
-2023-03-26 Gerald Pfeifer <gerald@pfeifer.com>
+ PR debug/113637
+ * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
+ with BLKmode are larger than DWARF2_ADDR_SIZE.
- * doc/install.texi: Remove anachronistic note
- related to languages built and separate source tarballs.
+2024-01-31 Jakub Jelinek <jakub@redhat.com>
-2023-03-25 David Malcolm <dmalcolm@redhat.com>
+ PR tree-optimization/113639
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
+ For VIEW_CONVERT_EXPR set rhs1 to its operand.
- PR analyzer/109098
- * diagnostic-format-sarif.cc (read_until_eof): Delete.
- (maybe_read_file): Delete.
- (sarif_builder::maybe_make_artifact_content_object): Use
- get_source_file_content rather than maybe_read_file.
- Reject it if it's not valid UTF-8.
- * input.cc (file_cache_slot::get_full_file_content): New.
- (get_source_file_content): New.
- (selftest::check_cpp_valid_utf8_p): New.
- (selftest::test_cpp_valid_utf8_p): New.
- (selftest::input_cc_tests): Call selftest::test_cpp_valid_utf8_p.
- * input.h (get_source_file_content): New prototype.
+2024-01-31 Richard Biener <rguenther@suse.de>
-2023-03-24 David Malcolm <dmalcolm@redhat.com>
+ PR tree-optimization/113670
+ * tree-vect-data-refs.cc (vect_check_gather_scatter):
+ Make sure we can take the address of the reference base.
- * doc/analyzer.texi (Debugging the Analyzer): Add notes on useful
- debugging options.
- (Special Functions for Debugging the Analyzer): Convert to a
- table, and rewrite in places.
- (Other Debugging Techniques): Add notes on how to compare two
- different exploded graphs.
+2024-01-31 Georg-Johann Lay <avr@gjlay.de>
-2023-03-24 David Malcolm <dmalcolm@redhat.com>
+ * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
+ ATA5835, ATtiny64AUTO, ATA5700M322.
+ * doc/avr-mmcu.texi: Rebuild.
- PR other/109163
- * json.cc: Update comments to indicate that we now preserve
- insertion order of keys within objects.
- (object::print): Traverse keys in insertion order.
- (object::set): Preserve insertion order of keys.
- (selftest::test_writing_objects): Add an additional key to verify
- that we preserve insertion order.
- * json.h (object::m_keys): New field.
+2024-01-31 Alexandre Oliva <oliva@adacore.com>
-2023-03-24 Andrew MacLeod <amacleod@redhat.com>
+ PR debug/113394
+ * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
+ caller.
- PR tree-optimization/109238
- * gimple-range-cache.cc (ranger_cache::resolve_dom): Ignore
- predecessors which this block dominates.
+2024-01-31 Alexandre Oliva <oliva@adacore.com>
-2023-03-24 Richard Biener <rguenther@suse.de>
+ PR middle-end/112917
+ PR middle-end/113100
+ * builtins.cc (expand_builtin_stack_address): Use
+ STACK_ADDRESS_OFFSET.
+ * doc/extend.texi (__builtin_stack_address): Adjust.
+ * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
+ * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
+ * doc/tm.texi: Rebuilt.
- PR tree-optimization/106912
- * tree-profile.cc (tree_profiling): Update stmts only when
- profiling or testing coverage. Make sure to update calls
- fntype, stripping 'const' there.
+2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-24 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/109258
- * builtins.cc (inline_expand_builtin_bytecmp): Return NULL_RTX early
- if target == const0_rtx.
-
-2023-03-24 Alexandre Oliva <oliva@adacore.com>
+ PR target/113495
+ * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
+ (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
+ (pre_vsetvl::compute_transparent): New function.
+ (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
- * doc/sourcebuild.texi (weak_undefined, posix_memalign):
- Document options and effective targets.
-
-2023-03-24 Costas Argyris <costas.argyris@gmail.com>
-
- * config/i386/x-mingw32-utf8: Make HOST_EXTRA_OBJS_SYMBOL
- optional.
+2024-01-30 Fangrui Song <maskray@google.com>
-2023-03-23 Pat Haugen <pthaugen@linux.ibm.com>
+ PR target/105576
+ * config/i386/constraints.md: Define constraint "Ws".
+ * doc/md.texi: Document it.
- * config/rs6000/rs6000.md (*mod<mode>3, umod<mode>3): Add
- non-earlyclobber alternative.
-
-2023-03-23 Andrew Pinski <apinski@marvell.com>
+2024-01-30 Marek Polacek <polacek@redhat.com>
- PR c/84900
- * fold-const.cc (maybe_lvalue_p): Treat COMPOUND_LITERAL_EXPR
- as a lvalue.
+ PR c++/110358
+ PR c++/109640
+ * doc/invoke.texi: Update -Wdangling-reference description.
-2023-03-23 Richard Biener <rguenther@suse.de>
+2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
- PR tree-optimization/107569
- * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt):
- Do not push SSA names with zero uses as available leader.
- (process_bb): Likewise.
+ * config/xtensa/constraints.md (R, T, U):
+ Change define_constraint to define_memory_constraint.
+ * config/xtensa/predicates.md (move_operand): Don't check that a
+ constant pool operand size is a multiple of UNITS_PER_WORD.
+ * config/xtensa/xtensa.cc
+ (xtensa_lra_p, TARGET_LRA_P): Remove.
+ (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
+ clause as it can no longer be true.
+ (fixup_subreg_mem): Drop function.
+ (xtensa_output_integer_literal_parts): Consider 16-bit wide
+ constants.
+ (xtensa_legitimate_constant_p): Add short-circuit path for
+ integer load instructions. Don't check that mode size is
+ at least UNITS_PER_WORD.
+ * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
+ rather reload_in_progress and reload_completed.
+ (doloop_end): Drop operand 2.
+ (movhi_internal): Add alternative loading constant from a
+ literal pool.
+ (define_split for DI register_operand): Don't limit to
+ !TARGET_AUTO_LITPOOLS.
+ * config/xtensa/xtensa.opt (mlra): Change to no effect.
+
+2024-01-30 Pan Li <pan2.li@intel.com>
+
+ * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
+ calculate the gpr count required by vls mode.
+ (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
+ (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
+ for vls mode.
+ (riscv_get_arg_info): Add vls mode handling.
+ (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
+
+2024-01-30 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/113659
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Handle main exit without virtual use.
-2023-03-23 Richard Biener <rguenther@suse.de>
+2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
- PR tree-optimization/109262
- * tree-ssa-forwprop.cc (pass_forwprop::execute): When
- combining a piecewise complex load avoid touching loads
- that throw internally. Use fun, not cfun throughout.
+ * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
-2023-03-23 Jakub Jelinek <jakub@redhat.com>
+2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
- * value-range.cc (irange::irange_union, irange::intersect): Fix
- comment spelling bugs.
- * gimple-range-trace.cc (range_tracer::do_header): Likewise.
- * gimple-range-trace.h: Likewise.
- * gimple-range-edge.cc: Likewise.
- (gimple_outgoing_range_stmt_p,
- gimple_outgoing_range::switch_edge_range,
- gimple_outgoing_range::edge_range_p): Likewise.
- * gimple-range.cc (gimple_ranger::prefill_stmt_dependencies,
- gimple_ranger::fold_stmt, gimple_ranger::register_transitive_infer,
- assume_query::assume_query, assume_query::calculate_phi): Likewise.
- * gimple-range-edge.h: Likewise.
- * value-range.h (Value_Range::set, Value_Range::lower_bound,
- Value_Range::upper_bound, frange::set_undefined): Likewise.
- * gimple-range-gori.h (range_def_chain::depend, gori_map::m_outgoing,
- gori_compute): Likewise.
- * gimple-range-fold.h (fold_using_range): Likewise.
- * gimple-range-path.cc (path_range_query::compute_ranges_in_phis):
- Likewise.
- * gimple-range-gori.cc (range_def_chain::in_chain_p,
- range_def_chain::dump, gori_map::calculate_gori,
- gori_compute::compute_operand_range_switch,
- gori_compute::logical_combine, gori_compute::refine_using_relation,
- gori_compute::compute_operand1_range, gori_compute::may_recompute_p):
- Likewise.
- * gimple-range.h: Likewise.
- (enable_ranger): Likewise.
- * range-op.h (empty_range_varying): Likewise.
- * value-query.h (value_query): Likewise.
- * gimple-range-cache.cc (block_range_cache::set_bb_range,
- block_range_cache::dump, ssa_global_cache::clear_global_range,
- temporal_cache::temporal_value, temporal_cache::current_p,
- ranger_cache::range_of_def, ranger_cache::propagate_updated_value,
- ranger_cache::range_from_dom, ranger_cache::register_inferred_value):
- Likewise.
- * gimple-range-fold.cc (fur_edge::get_phi_operand,
- fur_stmt::get_operand, gimple_range_adjustment,
- fold_using_range::range_of_phi,
- fold_using_range::relation_fold_and_or): Likewise.
- * value-range-storage.h (irange_storage_slot::MAX_INTS): Likewise.
- * value-query.cc (range_query::value_of_expr,
- range_query::value_on_edge, range_query::query_relation): Likewise.
- * tree-vrp.cc (remove_unreachable::remove_and_update_globals,
- intersect_range_with_nonzero_bits): Likewise.
- * gimple-range-infer.cc (gimple_infer_range::check_assume_func,
- exit_range): Likewise.
- * value-relation.h: Likewise.
- (equiv_oracle, relation_trio::relation_trio, value_relation,
- value_relation::value_relation, pe_min): Likewise.
- * range-op-float.cc (range_operator_float::rv_fold,
- frange_arithmetic, foperator_unordered_equal::op1_range,
- foperator_div::rv_fold): Likewise.
- * gimple-range-op.cc (cfn_clz::fold_range): Likewise.
- * value-relation.cc (equiv_oracle::query_relation,
- equiv_oracle::register_equiv, equiv_oracle::add_equiv_to_block,
- value_relation::apply_transitive, relation_chain_head::find_relation,
- dom_oracle::query_relation, dom_oracle::find_relation_block,
- dom_oracle::find_relation_dom, path_oracle::register_equiv): Likewise.
- * range-op.cc (range_operator::wi_fold_in_parts_equiv,
- create_possibly_reversed_range, adjust_op1_for_overflow,
- operator_mult::wi_fold, operator_exact_divide::op1_range,
- operator_cast::lhs_op1_relation, operator_cast::fold_pair,
- operator_cast::fold_range, operator_abs::wi_fold, range_op_cast_tests,
- range_op_lshift_tests): Likewise.
-
-2023-03-23 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn.cc (gcn_class_max_nregs): Handle vectors in SGPRs.
- (move_callee_saved_registers): Detect the bug condition early.
-
-2023-03-23 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-protos.h (gcn_stepped_zero_int_parallel_p): New.
- * config/gcn/gcn-valu.md (V_1REG_ALT): New.
- (V_2REG_ALT): New.
- (vec_extract<V_1REG:mode><V_1REG_ALT:mode>_nop): New.
- (vec_extract<V_2REG:mode><V_2REG_ALT:mode>_nop): New.
- (vec_extract<V_ALL:mode><V_ALL_ALT:mode>): Use new patterns.
- * config/gcn/gcn.cc (gcn_stepped_zero_int_parallel_p): New.
- * config/gcn/predicates.md (ascending_zero_int_parallel): New.
-
-2023-03-23 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109176
- * tree-vect-generic.cc (expand_vector_condition): If a has
- vector boolean type and is a comparison, also check if both
- the comparison and VEC_COND_EXPR could be successfully expanded
- individually.
-
-2023-03-23 Pan Li <pan2.li@intel.com>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- PR target/108654
- PR target/108185
- * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Adjust size
- for vector mask modes.
- * config/riscv/riscv.cc (riscv_v_adjust_bytesize): New.
- * config/riscv/riscv.h (riscv_v_adjust_bytesize): New.
-
-2023-03-23 Songhe Zhu <zhusonghe@eswincomputing.com>
-
- * config/riscv/multilib-generator: Adjusting the loop of 'alt' in 'alts'.
-
-2023-03-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- PR target/109244
- * config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global.
- (emit_vlmax_op): Ditto.
- * config/riscv/riscv-v.cc (get_sew): New function.
- (emit_vlmax_vsetvl): Adapt function.
- (emit_pred_op): Ditto.
- (emit_vlmax_op): Ditto.
- (emit_nonvlmax_op): Ditto.
- (legitimize_move): Fix LRA ICE.
- (gen_no_side_effects_vsetvl_rtx): Adapt function.
- * config/riscv/vector.md (@mov<V_FRACT:mode><P:mode>_lra): New pattern.
- (@mov<VB:mode><P:mode>_lra): Ditto.
- (*mov<V_FRACT:mode><P:mode>_lra): Ditto.
- (*mov<VB:mode><P:mode>_lra): Ditto.
-
-2023-03-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- PR target/109228
- * config/riscv/riscv-vector-builtins-bases.cc (class vlenb): Add
- __riscv_vlenb support.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vlenb): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct vlenb_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc: Ditto.
-
-2023-03-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-vsetvl.cc (reg_available_p): Fix bugs.
- (pass_vsetvl::compute_local_backward_infos): Fix bugs.
- (pass_vsetvl::need_vsetvl): Fix bugs.
- (pass_vsetvl::backward_demand_fusion): Fix bugs.
- (pass_vsetvl::demand_fusion): Fix bugs.
- (eliminate_insn): Fix bugs.
- (insert_vsetvl): Ditto.
- (pass_vsetvl::emit_local_forward_vsetvls): Ditto.
- * config/riscv/riscv-vsetvl.h (enum vsetvl_type): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-03-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Fix ternary bug.
- * config/riscv/vector-iterators.md (nmsac): Ditto.
- (nmsub): Ditto.
- (msac): Ditto.
- (msub): Ditto.
- (nmadd): Ditto.
- (nmacc): Ditto.
- * config/riscv/vector.md (@pred_mul_<optab><mode>): Ditto.
- (@pred_mul_plus<mode>): Ditto.
- (*pred_madd<mode>): Ditto.
- (*pred_macc<mode>): Ditto.
- (*pred_mul_plus<mode>): Ditto.
- (@pred_mul_plus<mode>_scalar): Ditto.
- (*pred_madd<mode>_scalar): Ditto.
- (*pred_macc<mode>_scalar): Ditto.
- (*pred_mul_plus<mode>_scalar): Ditto.
- (*pred_madd<mode>_extended_scalar): Ditto.
- (*pred_macc<mode>_extended_scalar): Ditto.
- (*pred_mul_plus<mode>_extended_scalar): Ditto.
- (@pred_minus_mul<mode>): Ditto.
- (*pred_<madd_nmsub><mode>): Ditto.
- (*pred_nmsub<mode>): Ditto.
- (*pred_<macc_nmsac><mode>): Ditto.
- (*pred_nmsac<mode>): Ditto.
- (*pred_mul_<optab><mode>): Ditto.
- (*pred_minus_mul<mode>): Ditto.
- (@pred_mul_<optab><mode>_scalar): Ditto.
- (@pred_minus_mul<mode>_scalar): Ditto.
- (*pred_<madd_nmsub><mode>_scalar): Ditto.
- (*pred_nmsub<mode>_scalar): Ditto.
- (*pred_<macc_nmsac><mode>_scalar): Ditto.
- (*pred_nmsac<mode>_scalar): Ditto.
- (*pred_mul_<optab><mode>_scalar): Ditto.
- (*pred_minus_mul<mode>_scalar): Ditto.
- (*pred_<madd_nmsub><mode>_extended_scalar): Ditto.
- (*pred_nmsub<mode>_extended_scalar): Ditto.
- (*pred_<macc_nmsac><mode>_extended_scalar): Ditto.
- (*pred_nmsac<mode>_extended_scalar): Ditto.
- (*pred_mul_<optab><mode>_extended_scalar): Ditto.
- (*pred_minus_mul<mode>_extended_scalar): Ditto.
- (*pred_<madd_msub><mode>): Ditto.
- (*pred_<macc_msac><mode>): Ditto.
- (*pred_<madd_msub><mode>_scalar): Ditto.
- (*pred_<macc_msac><mode>_scalar): Ditto.
- (@pred_neg_mul_<optab><mode>): Ditto.
- (@pred_mul_neg_<optab><mode>): Ditto.
- (*pred_<nmadd_msub><mode>): Ditto.
- (*pred_<nmsub_nmadd><mode>): Ditto.
- (*pred_<nmacc_msac><mode>): Ditto.
- (*pred_<nmsac_nmacc><mode>): Ditto.
- (*pred_neg_mul_<optab><mode>): Ditto.
- (*pred_mul_neg_<optab><mode>): Ditto.
- (@pred_neg_mul_<optab><mode>_scalar): Ditto.
- (@pred_mul_neg_<optab><mode>_scalar): Ditto.
- (*pred_<nmadd_msub><mode>_scalar): Ditto.
- (*pred_<nmsub_nmadd><mode>_scalar): Ditto.
- (*pred_<nmacc_msac><mode>_scalar): Ditto.
- (*pred_<nmsac_nmacc><mode>_scalar): Ditto.
- (*pred_neg_mul_<optab><mode>_scalar): Ditto.
- (*pred_mul_neg_<optab><mode>_scalar): Ditto.
- (@pred_widen_neg_mul_<optab><mode>): Ditto.
- (@pred_widen_mul_neg_<optab><mode>): Ditto.
- (@pred_widen_neg_mul_<optab><mode>_scalar): Ditto.
- (@pred_widen_mul_neg_<optab><mode>_scalar): Ditto.
-
-2023-03-23 liuhongt <hongtao.liu@intel.com>
-
- * builtins.cc (builtin_memset_read_str): Replace
- targetm.gen_memset_scratch_rtx with gen_reg_rtx.
- (builtin_memset_gen_str): Ditto.
- * config/i386/i386-expand.cc
- (ix86_convert_const_wide_int_to_broadcast): Replace
- ix86_gen_scratch_sse_rtx with gen_reg_rtx.
- (ix86_expand_vector_move): Ditto.
- * config/i386/i386-protos.h (ix86_gen_scratch_sse_rtx):
- Removed.
- * config/i386/i386.cc (ix86_gen_scratch_sse_rtx): Removed.
- (TARGET_GEN_MEMSET_SCRATCH_RTX): Removed.
- * doc/tm.texi: Remove TARGET_GEN_MEMSET_SCRATCH_RTX.
- * doc/tm.texi.in: Ditto.
- * target.def: Ditto.
-
-2023-03-22 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra.cc (lra): Do not repeat inheritance and live range splitting
- when asm error is found.
-
-2023-03-22 Andrew Jenner <andrew@codesourcery.com>
-
- * config/gcn/gcn-protos.h (gcn_expand_dpp_swap_pairs_insn)
- (gcn_expand_dpp_distribute_even_insn)
- (gcn_expand_dpp_distribute_odd_insn): Declare.
- * config/gcn/gcn-valu.md (@dpp_swap_pairs<mode>)
- (@dpp_distribute_even<mode>, @dpp_distribute_odd<mode>)
- (cmul<conj_op><mode>3, cml<addsub_as><mode>4, vec_addsub<mode>3)
- (cadd<rot><mode>3, vec_fmaddsub<mode>4, vec_fmsubadd<mode>4)
- (fms<mode>4<exec>, fms<mode>4_negop2<exec>, fms<mode>4)
- (fms<mode>4_negop2): New patterns.
- * config/gcn/gcn.cc (gcn_expand_dpp_swap_pairs_insn)
- (gcn_expand_dpp_distribute_even_insn)
- (gcn_expand_dpp_distribute_odd_insn): New functions.
- * config/gcn/gcn.md: Add entries to unspec enum.
-
-2023-03-22 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/109008
- * value-range.cc (frange::set): Add nan_state argument.
- * value-range.h (class nan_state): New.
- (frange::get_nan_state): New.
-
-2023-03-22 Martin Liska <mliska@suse.cz>
+ PR libgcc/113403
+ * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
+ (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
+ * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
+ * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
+ * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
+ * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
- * configure: Regenerate.
+2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
-2023-03-21 Joseph Myers <joseph@codesourcery.com>
+ PR target/113623
+ * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
+ Mark all registers that occur in addresses as needing a GPR.
- * stor-layout.cc (finalize_type_size): Copy TYPE_TYPELESS_STORAGE
- to variants.
+2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
-2023-03-21 Andrew MacLeod <amacleod@redhat.com>
+ PR target/113636
+ * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
+ the containing insn as an extra parameter. Reset debug instructions
+ if they reference a register that is no longer used by real insns.
+ (early_ra::apply_allocation): Update calls accordingly.
- PR tree-optimization/109192
- * gimple-range-gori.cc (gori_compute::compute_operand_range):
- Terminate gori calculations if a relation is not relevant.
- * value-relation.h (value_relation::set_relation): Allow
- equality between op1 and op2 if they are the same.
+2024-01-30 Jakub Jelinek <jakub@redhat.com>
-2023-03-21 Richard Biener <rguenther@suse.de>
+ PR tree-optimization/113603
+ * tree-ssa-strlen.cc (strlen_pass::handle_store): After
+ count_nonzero_bytes call refetch si using get_strinfo in case it
+ has been unshared in the meantime.
- PR tree-optimization/109219
- * tree-vect-loop.cc (vectorizable_reduction): Check
- slp_node, not STMT_SLP_TYPE.
- * tree-vect-stmts.cc (vectorizable_condition): Likewise.
- * tree-vect-slp.cc (vect_slp_analyze_node_operations_1):
- Remove assertion on STMT_SLP_TYPE.
+2024-01-30 Jakub Jelinek <jakub@redhat.com>
-2023-03-21 Jakub Jelinek <jakub@redhat.com>
+ PR middle-end/101195
+ * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
+ fit into unsigned HOST_WIDE_INT, return constm1_rtx.
- PR tree-optimization/109215
- * tree.h (enum special_array_member): Adjust comments for int_0
- and trail_0.
- * tree.cc (component_ref_sam_type): Clear zero_elts if memtype
- has zero sized element type and the array has variable number of
- elements or constant one or more elements.
- (component_ref_size): Adjust comments, formatting fix.
+2024-01-30 Jin Ma <jinma@linux.alibaba.com>
-2023-03-21 Arsen Arsenović <arsen@aarsen.me>
+ * config/riscv/thead.cc (th_print_operand_address): Change %ld
+ to %lld.
- * configure.ac: Add check for the Texinfo 6.8
- CONTENTS_OUTPUT_LOCATION customization variable and set it if
- supported.
- * configure: Regenerate.
- * Makefile.in (MAKEINFO_TOC_INLINE_FLAG): New variable. Set by
- configure.ac to -c CONTENTS_OUTPUT_LOCATION=inline if
- CONTENTS_OUTPUT_LOCATION support is detected, empty otherwise.
- ($(build_htmldir)/%/index.html): Pass MAKEINFO_TOC_INLINE_FLAG.
+2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
+ Manolis Tsamis <manolis.tsamis@vrull.eu>
+ Philipp Tomsich <philipp.tomsich@vrull.eu>
-2023-03-21 Arsen Arsenović <arsen@aarsen.me>
+ * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
+ * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
+ Likewise.
+ * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
+ Call on framework moved later.
- * doc/extend.texi: Associate use_hazard_barrier_return index
- entry with its attribute.
- * doc/invoke.texi: Associate -fcanon-prefix-map index entry with
- its attribute
+2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
-2023-03-21 Arsen Arsenović <arsen@aarsen.me>
+ * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
+ instruction in naked function epilogues.
- * doc/implement-c.texi: Remove usage of @gol.
- * doc/invoke.texi: Ditto.
- * doc/sourcebuild.texi: Ditto.
- * doc/include/gcc-common.texi: Remove @gol. In new Makeinfo and
- texinfo.tex versions, the bug it was working around appears to
- be gone.
+2024-01-29 YunQiang Su <syq@gcc.gnu.org>
-2023-03-21 Arsen Arsenović <arsen@aarsen.me>
+ PR target/113655
+ * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
+ gcc_cv_as_mips_explicit_relocs.
+ * configure: Regnerated.
- * doc/include/texinfo.tex: Update to 2023-01-17.19.
+2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
-2023-03-21 Arsen Arsenović <arsen@aarsen.me>
+ PR target/108933
+ * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
+ Correct generated RTL.
+ (arm_rev16si2_alt1): Correctly handle conditional execution.
+ (arm_rev16si2_alt2): Likewise.
- * doc/include/gcc-common.texi: Add @defbuiltin{,x} and
- @enddefbuiltin for defining built-in functions.
- * doc/extend.texi: Apply @defbuiltin{,x} to many, but not all,
- places where it should be used.
+2024-01-29 Richard Biener <rguenther@suse.de>
-2023-03-21 Arsen Arsenović <arsen@aarsen.me>
+ PR middle-end/113622
+ * expr.cc (expand_assignment): Spill hard registers if
+ we index them with a variable offset.
- * doc/extend.texi (Formatted Output Function Checking): New
- subsection for grouping together printf et al.
- (Exception handling) Fix missing @ sign before copyright
- header, which lead to the copyright line leaking into
- '(gcc)Exception handling'.
- * doc/gcc.texi: Set document language to en_US.
- (@copying): Wrap front cover texts in quotations, move in manual
- description text.
+2024-01-29 Richard Biener <rguenther@suse.de>
-2023-03-21 Arsen Arsenović <arsen@aarsen.me>
+ PR middle-end/113622
+ * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
+ Also allow DECL_HARD_REGISTER variables.
- * doc/gcc.texi: Add the Indices appendix, to make texinfo
- generate nice indices overview page.
+2024-01-29 Alex Coplan <alex.coplan@arm.com>
-2023-03-21 Richard Biener <rguenther@suse.de>
+ PR target/113616
+ * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
+ Use iterate_safely when iterating over debug uses.
+ (fixup_debug_uses): Likewise.
+ (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
+ over nondebug insns instead of manually maintaining the next insn.
+ * iterator-utils.h (class safe_iterator): New.
+ (iterate_safely): New.
- PR tree-optimization/109170
- * gimple-range-op.cc (cfn_pass_through_arg1): New.
- (gimple_range_op_handler::maybe_builtin_call): Handle
- __builtin_expect via cfn_pass_through_arg1.
+2024-01-29 H.J. Lu <hjl.tools@gmail.com>
-2023-03-20 Michael Meissner <meissner@linux.ibm.com>
+ PR target/38534
+ * config/i386/i386-options.cc (ix86_set_func_type): Save
+ callee-saved registers in noreturn functions for -O0/-Og.
- PR target/109067
- * config/rs6000/rs6000.cc (create_complex_muldiv): Delete.
- (init_float128_ieee): Delete code to switch complex multiply and divide
- for long double.
- (complex_multiply_builtin_code): New helper function.
- (complex_divide_builtin_code): Likewise.
- (rs6000_mangle_decl_assembler_name): Add support for mangling the name
- of complex 128-bit multiply and divide built-in functions.
+2024-01-29 Tobias Burnus <tburnus@baylibre.com>
-2023-03-20 Peter Bergner <bergner@linux.ibm.com>
+ PR target/113615
+ * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
+ define for !TARGET_RDNA2_PLUS.
+
+2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/113281
+ * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
+ workaround for right shifts.
+ (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
+ (vect_determine_precisions_from_range): Be more selective about
+ which codes can be narrowed based on their input and output ranges.
+ For shifts, require at least one more bit of precision than the
+ maximum shift amount.
+
+2024-01-29 Tobias Burnus <tburnus@baylibre.com>
+
+ * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
+
+2024-01-29 Tobias Burnus <tburnus@baylibre.com>
+
+ * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
+ but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
+ LLVM 13.0.1+.
+
+2024-01-29 Tobias Burnus <tburnus@baylibre.com>
+
+ PR other/111966
+ * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
+ (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
+ (SET_SRAM_ECC_UNSET): ... this.
+ (copy_early_debug_info): Remove gfx900 special case, now handled as
+ part of the generic handling.
+ (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
+
+2024-01-29 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/110603
+ * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
+ setting of pdata->maxlen to vr.upper_bound (which is unconditionally
+ overwritten anyway). Avoid creating invalid range with minlen
+ larger than maxlen. Formatting fix.
+
+2024-01-29 Richard Biener <rguenther@suse.de>
+
+ PR debug/103047
+ * tree-inline.cc (initialize_inlined_parameters): Reverse
+ the decl chain of inlined parameters.
+
+2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
+ alignment of CFString constants by setting DECL_USER_ALIGN.
+
+2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
+ Jakub Jelinek <jakub@redhat.com>
+
+ PR libgcc/113402
+ * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
+ and BUILT_IN_GCC_NESTED_PTR_DELETED.
+ * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
+ BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
+ rename the library fallbacks to __gcc_nested_func_ptr_created and
+ __gcc_nested_func_ptr_deleted.
+ * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
+ and __gcc_nested_func_ptr_deleted.
+ * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
+ BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
+ * tree.cc (build_common_builtin_nodes): Build the
+ BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
+ builtins only for non-explicit.
+
+2024-01-28 YunQiang Su <syq@gcc.gnu.org>
+
+ * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
+
+2024-01-27 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/38534
+ * config/i386/i386-options.cc (ix86_set_func_type): Don't
+ save and restore callee saved registers for a noreturn function
+ with nothrow or compiled with -fno-exceptions.
+
+2024-01-27 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/103503
+ PR target/113312
+ * config/i386/i386-expand.cc (ix86_expand_call): Replace
+ no_caller_saved_registers check with call_saved_registers check.
+ Clobber all registers that are not used by the callee with
+ no_callee_saved_registers attribute.
+ * config/i386/i386-options.cc (ix86_set_func_type): Set
+ call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
+ noreturn function. Disallow no_callee_saved_registers with
+ interrupt or no_caller_saved_registers attributes together.
+ (ix86_set_current_function): Replace no_caller_saved_registers
+ check with call_saved_registers check.
+ (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
+ (ix86_handle_call_saved_registers_attribute): This.
+ (ix86_gnu_attributes): Add
+ ix86_handle_call_saved_registers_attribute.
+ * config/i386/i386.cc (ix86_conditional_register_usage): Replace
+ no_caller_saved_registers check with call_saved_registers check.
+ (ix86_function_ok_for_sibcall): Don't allow callee with
+ no_callee_saved_registers attribute when the calling function
+ has callee-saved registers.
+ (ix86_comp_type_attributes): Also check
+ no_callee_saved_registers.
+ (ix86_epilogue_uses): Replace no_caller_saved_registers check
+ with call_saved_registers check.
+ (ix86_hard_regno_scratch_ok): Likewise.
+ (ix86_save_reg): Replace no_caller_saved_registers check with
+ call_saved_registers check. Don't save any registers for
+ TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
+ TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
+ no_callee_saved_registers attribute is called.
+ (find_drap_reg): Replace no_caller_saved_registers check with
+ call_saved_registers check.
+ * config/i386/i386.h (call_saved_registers_type): New enum.
+ (machine_function): Replace no_caller_saved_registers with
+ call_saved_registers.
+ * doc/extend.texi: Document no_callee_saved_registers attribute.
+
+2024-01-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/113614
+ * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
+ widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
+ TRUNC_MOD_EXPR or FLOAT_EXPR uses.
+
+2024-01-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/113568
+ * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
+ For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
+ in the widening extension checks.
+
+2024-01-27 Jakub Jelinek <jakub@redhat.com>
+
+ * gimple-lower-bitint.cc (gimple_lower_bitint): For
+ TDF_DETAILS dump mapping of SSA_NAMEs to decls.
+
+2024-01-26 Hans-Peter Nilsson <hp@axis.com>
+
+ * cgraphunit.cc (process_function_and_variable_attributes): Tweak
+ the warning for an attribute-always_inline without inline declaration.
+
+2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR other/113575
+ * genopinit.cc (main): Split init_all_optabs into functions
+ of 1000 patterns each.
+
+2024-01-26 Tobias Burnus <tburnus@baylibre.com>
+
+ * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
+ TM_MULTILIB_CONFIG.
+ * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
+ * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
+ -march/-mtune.
+
+2024-01-26 Andrew Stubbs <ams@baylibre.com>
+
+ * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
+ * config/gcn/gcn-valu.md (all_convert): New iterator.
+ (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
+ define_expand, and rename the old one to ...
+ (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
+ (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
+ (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
+ (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
+ * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
+ (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
+ * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
+ (<u>mulqihi3_scalar): Likewise.
+
+2024-01-26 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/113602
+ * tree-data-ref.cc (dr_analyze_innermost): Fail when
+ the base object isn't addressable.
+
+2024-01-26 Tobias Burnus <tburnus@baylibre.com>
+
+ * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
+ "--amdhsa-code-object-version=" argument.
+ (ASM_SPEC): Use it; replace previous version of it.
+
+2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
+ (pre_vsetvl::emit_vsetvl): Ditto.
- PR target/109178
- * config/rs6000/rs6000-builtin.cc (stv_expand_builtin): Use tmode.
+2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
-2023-03-19 Jonny Grant <jg@jguk.org>
+ * config/loongarch/lasx.md (vec_extract<mode>_0):
+ New define_insn_and_split patten.
- * doc/extend.texi (Common Function Attributes) <nonnull>:
- Correct typo.
+2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
-2023-03-18 Peter Bergner <bergner@linux.ibm.com>
+ * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
- PR rtl-optimization/109179
- * lra-constraints.cc (combine_reload_insn): Enforce TO is not a debug
- insn or note. Move the tests earlier to guard lra_get_insn_recog_data.
+2024-01-26 Li Wei <liwei@loongson.cn>
-2023-03-17 Jakub Jelinek <jakub@redhat.com>
+ * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
- PR target/105554
- * function.h (push_struct_function): Add ABSTRACT_P argument defaulted
- to false.
- * function.cc (push_struct_function): Add ABSTRACT_P argument, pass it
- to allocate_struct_function instead of false.
- * tree-inline.cc (initialize_cfun): Don't copy DECL_ARGUMENTS
- nor DECL_RESULT here. Pass true as ABSTRACT_P to
- push_struct_function. Call targetm.target_option.relayout_function
- after it.
- (tree_function_versioning): Formatting fix.
+2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-17 Vladimir N. Makarov <vmakarov@redhat.com>
+ PR target/113469
+ * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
- * lra-constraints.cc: Include hooks.h.
- (combine_reload_insn): New function.
- (lra_constraints): Call it.
+2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
-2023-03-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
+ PR target/100212
+ * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
+ undefined shift after the call to exact_log2.
- * config/riscv/riscv-v.cc (legitimize_move): Allow undef value
- as legitimate value.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_ternop_insn): Fix bugs of ternary intrinsic.
- (function_expander::use_widen_ternop_insn): Ditto.
- * config/riscv/vector.md (@vundefined<mode>): New pattern.
- (pred_mul_<optab><mode>_undef_merge): Remove.
- (*pred_mul_<optab><mode>_undef_merge_scalar): Ditto.
- (*pred_mul_<optab><mode>_undef_merge_extended_scalar): Ditto.
- (pred_neg_mul_<optab><mode>_undef_merge): Ditto.
- (*pred_neg_mul_<optab><mode>_undef_merge_scalar): Ditto.
+2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
-2023-03-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+ PR target/100204
+ * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
+ before taking the negative of it.
- PR target/109092
- * config/riscv/riscv.md: Fix subreg bug.
-
-2023-03-17 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/108685
- * omp-expand.cc (expand_omp_for_ordered_loops): Add L0_BB argument,
- use its loop_father rather than BODY_BB's loop_father.
- (expand_omp_for_generic): Adjust expand_omp_for_ordered_loops caller.
- If broken_loop with ordered > collapse and at least one of those
- extra loops aren't guaranteed to have at least one iteration, change
- l0_bb's loop_father to entry_bb's loop_father. Set cont_bb's
- loop_father to l0_bb's loop_father rather than l1_bb's.
-
-2023-03-17 Jakub Jelinek <jakub@redhat.com>
-
- PR plugins/108634
- * gdbhooks.py (TreePrinter.to_string): Wrap
- gdb.parse_and_eval('tree_code_type') in a try block, parse
- and eval 'tree_code_type_tmpl<0>::tree_code_type' instead if it
- raises exception. Update comments for the recent tree_code_type
- changes.
-
-2023-03-17 Sandra Loosemore <sandra@codesourcery.com>
-
- * doc/extend.texi (BPF Built-in Functions): Fix numerous markup
- issues. Add more line breaks to example so it doesn't overflow
- the margins.
-
-2023-03-17 Sandra Loosemore <sandra@codesourcery.com>
-
- * doc/extend.texi (Common Function Attributes) <access>: Fix bad
- line breaks in examples.
- <malloc>: Fix bad line breaks in running text, also copy-edit
- for consistency.
- (Extended Asm) <Generic Operand Modifiers>: Fix @multitable width.
- * doc/invoke.texi (Option Summary) <Developer Options>: Fix misplaced
- @gol.
- (C++ Dialect Options) <-fcontracts>: Add line break in example.
- <-Wctad-maybe-unsupported>: Likewise.
- <-Winvalid-constexpr>: Likewise.
- (Warning Options) <-Wdangling-pointer>: Likewise.
- <-Winterference-size>: Likewise.
- <-Wvla-parameter>: Likewise.
- (Static Analyzer Options): Fix bad line breaks in running text,
- plus add some missing markup.
- (Optimize Options) <openacc-privatization>: Fix more bad line
- breaks in running text.
-
-2023-03-16 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (expand_vec_perm_pblendv):
- Handle 8-byte modes only with TARGET_MMX_WITH_SSE.
- (expand_vec_perm_2perm_pblendv): Ditto.
-
-2023-03-16 Martin Liska <mliska@suse.cz>
-
- PR middle-end/106133
- * gcc.cc (driver_handle_option): Use x_main_input_basename
- if x_dump_base_name is null.
- * opts.cc (common_handle_option): Likewise.
-
-2023-03-16 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109123
- * gimple-ssa-warn-access.cc (pass_waccess::warn_invalid_pointer):
- Do not emit -Wuse-after-free late.
- (pass_waccess::check_call): Always check call pointer uses.
-
-2023-03-16 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109141
- * tree-dfa.h (renumber_gimple_stmt_uids_in_block): New.
- * tree-dfa.cc (renumber_gimple_stmt_uids_in_block): Split
- out from ...
- (renumber_gimple_stmt_uids): ... here and
- (renumber_gimple_stmt_uids_in_blocks): ... here.
- * gimple-ssa-warn-access.cc (pass_waccess::use_after_inval_p):
- Use renumber_gimple_stmt_uids_in_block to also assign UIDs
- to PHIs.
- (pass_waccess::check_pointer_uses): Process all PHIs.
-
-2023-03-15 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/109097
- * diagnostic-format-sarif.cc (class sarif_invocation): New.
- (class sarif_ice_notification): New.
- (sarif_builder::m_invocation_obj): New field.
- (sarif_invocation::add_notification_for_ice): New.
- (sarif_invocation::prepare_to_flush): New.
- (sarif_ice_notification::sarif_ice_notification): New.
- (sarif_builder::sarif_builder): Add m_invocation_obj.
- (sarif_builder::end_diagnostic): Special-case DK_ICE and
- DK_ICE_NOBT.
- (sarif_builder::flush_to_file): Call prepare_to_flush on
- m_invocation_obj. Pass the latter to make_top_level_object.
- (sarif_builder::make_result_object): Move creation of "locations"
- array to...
- (sarif_builder::make_locations_arr): ...this new function.
- (sarif_builder::make_top_level_object): Add "invocation_obj" param
- and pass it to make_run_object.
- (sarif_builder::make_run_object): Add "invocation_obj" param and
- use it.
- (sarif_ice_handler): New callback.
- (diagnostic_output_format_init_sarif): Wire up sarif_ice_handler.
- * diagnostic.cc (diagnostic_initialize): Initialize new field
- "ice_handler_cb".
- (diagnostic_action_after_output): If it is set, make one attempt
- to call ice_handler_cb.
- * diagnostic.h (diagnostic_context::ice_handler_cb): New field.
-
-2023-03-15 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (expand_vec_perm_blend):
- Handle 8-byte modes only with TARGET_MMX_WITH_SSE. Handle V2SFmode
- and fix V2HImode handling.
- (expand_vec_perm_1): Try to emit BLEND instruction
- before MOVSS/MOVSD.
- * config/i386/mmx.md (*mmx_blendps): New insn pattern.
-
-2023-03-15 Tobias Burnus <tobias@codesourcery.com>
-
- * omp-low.cc (omp_runtime_api_call): Add omp_in_explicit_task.
-
-2023-03-15 Richard Biener <rguenther@suse.de>
-
- * gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses):
- Do not diagnose clobbers.
-
-2023-03-15 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109139
- * tree-ssa-live.cc (remove_unused_locals): Look at the
- base address for unused decls on the LHS of .DEFERRED_INIT.
-
-2023-03-15 Xi Ruoyao <xry111@xry111.site>
-
- PR other/109086
- * builtins.cc (inline_string_cmp): Force the character
- difference into "result" pseudo-register, instead of reassign
- the pseudo-register.
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config.gcc: Add thead.o to RISC-V extra_objs.
- * config/riscv/peephole.md: Add mempair peephole passes.
- * config/riscv/riscv-protos.h (riscv_split_64bit_move_p): New
- prototype.
- (th_mempair_operands_p): Likewise.
- (th_mempair_order_operands): Likewise.
- (th_mempair_prepare_save_restore_operands): Likewise.
- (th_mempair_save_restore_regs): Likewise.
- (th_mempair_output_move): Likewise.
- * config/riscv/riscv.cc (riscv_save_reg): Move code.
- (riscv_restore_reg): Move code.
- (riscv_for_each_saved_reg): Add code to emit mempair insns.
- * config/riscv/t-riscv: Add thead.cc.
- * config/riscv/thead.md (*th_mempair_load_<GPR:mode>2):
- New insn.
- (*th_mempair_store_<GPR:mode>2): Likewise.
- (*th_mempair_load_extendsidi2): Likewise.
- (*th_mempair_load_zero_extendsidi2): Likewise.
- * config/riscv/thead.cc: New file.
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS)
- New constraint "th_f_fmv".
- (TARGET_XTHEADFMV ? GR_REGS : NO_REGS): New constraint
- "th_r_fmv".
- * config/riscv/riscv.cc (riscv_split_doubleword_move):
- Add split code for XTheadFmv.
- (riscv_secondary_memory_needed): XTheadFmv does not need
- secondary memory.
- * config/riscv/riscv.md: Add new UNSPEC_XTHEADFMV and
- UNSPEC_XTHEADFMV_HW. Add support for XTheadFmv to
- movdf_hardfloat_rv32.
- * config/riscv/thead.md (th_fmv_hw_w_x): New INSN.
- (th_fmv_x_w): New INSN.
- (th_fmv_x_hw): New INSN.
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.md (maddhisi4): New expand.
- (msubhisi4): New expand.
- * config/riscv/thead.md (*th_mula<mode>): New pattern.
- (*th_mulawsi): New pattern.
- (*th_mulawsi2): New pattern.
- (*th_maddhisi4): New pattern.
- (*th_sextw_maddhisi4): New pattern.
- (*th_muls<mode>): New pattern.
- (*th_mulswsi): New pattern.
- (*th_mulswsi2): New pattern.
- (*th_msubhisi4): New pattern.
- (*th_sextw_msubhisi4): New pattern.
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator.
- * config/riscv/riscv-protos.h (riscv_expand_conditional_move):
- Add prototype.
- * config/riscv/riscv.cc (riscv_rtx_costs): Add costs for
- XTheadCondMov.
- (riscv_expand_conditional_move): New function.
- (riscv_expand_conditional_move_onesided): New function.
- * config/riscv/riscv.md: Add support for XTheadCondMov.
- * config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>): Add
- support for XTheadCondMov.
- (*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Likewise.
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/bitmanip.md (clzdi2): New expand.
- (clzsi2): New expand.
- (ctz<mode>2): New expand.
- (popcount<mode>2): New expand.
- (<bitmanip_optab>si2): Rename INSN.
- (*<bitmanip_optab>si2): Hide INSN name.
- (<bitmanip_optab>di2): Rename INSN.
- (*<bitmanip_optab>di2): Hide INSN name.
- (rotrsi3): Remove INSN.
- (rotr<mode>3): Add expand.
- (*rotrsi3): New INSN.
- (rotrdi3): Rename INSN.
- (*rotrdi3): Hide INSN name.
- (rotrsi3_sext): Rename INSN.
- (*rotrsi3_sext): Hide INSN name.
- (bswap<mode>2): Remove INSN.
- (bswapdi2): Add expand.
- (bswapsi2): Add expand.
- (*bswap<mode>2): Hide INSN name.
- * config/riscv/riscv.cc (riscv_rtx_costs): Add costs for sign
- extraction.
- * config/riscv/riscv.md (extv<mode>): New expand.
- (extzv<mode>): New expand.
- * config/riscv/thead.md (*th_srri<mode>3): New INSN.
- (*th_ext<mode>): New INSN.
- (*th_extu<mode>): New INSN.
- (*th_clz<mode>2): New INSN.
- (*th_rev<mode>2): New INSN.
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost.
- * config/riscv/thead.md (*th_tst<mode>3): New INSN.
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.md: Include thead.md
- * config/riscv/thead.md: New file.
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".
-
-2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * common/config/riscv/riscv-common.cc: Add xthead* extensions.
- * config/riscv/riscv-opts.h (MASK_XTHEADBA): New.
- (MASK_XTHEADBB): New.
- (MASK_XTHEADBS): New.
- (MASK_XTHEADCMO): New.
- (MASK_XTHEADCONDMOV): New.
- (MASK_XTHEADFMEMIDX): New.
- (MASK_XTHEADFMV): New.
- (MASK_XTHEADINT): New.
- (MASK_XTHEADMAC): New.
- (MASK_XTHEADMEMIDX): New.
- (MASK_XTHEADMEMPAIR): New.
- (MASK_XTHEADSYNC): New.
- (TARGET_XTHEADBA): New.
- (TARGET_XTHEADBB): New.
- (TARGET_XTHEADBS): New.
- (TARGET_XTHEADCMO): New.
- (TARGET_XTHEADCONDMOV): New.
- (TARGET_XTHEADFMEMIDX): New.
- (TARGET_XTHEADFMV): New.
- (TARGET_XTHEADINT): New.
- (TARGET_XTHEADMAC): New.
- (TARGET_XTHEADMEMIDX): New.
- (TARGET_XTHEADMEMPAIR): new.
- (TARGET_XTHEADSYNC): New.
- * config/riscv/riscv.opt: Add riscv_xthead_subext.
-
-2023-03-15 Hu, Lin1 <lin1.hu@intel.com>
-
- PR target/109117
- * config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
- __builtin_ia32_vaesdeclast_v16qi,__builtin_ia32_vaesenc_v16qi,
- __builtin_ia32_vaesenclast_v16qi): Require OPTION_MASK_ISA_AVX512VL.
+2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
-2023-03-14 Jakub Jelinek <jakub@redhat.com>
+ PR target/113526
+ * lra-constraints.cc (curr_insn_transform): Change class even for
+ spilled pseudo successfully matched with with NO_REGS.
- PR target/109109
- * config/i386/i386-expand.cc (split_double_concat): Fix splitting
- when lo is equal to dhi and hi is a MEM which uses dlo register.
+2024-01-25 Georg-Johann Lay <avr@gjlay.de>
-2023-03-14 Martin Jambor <mjambor@suse.cz>
+ PR target/113601
+ * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
- PR ipa/107925
- * ipa-cp.cc (update_profiling_info): Drop counts of orig_node to
- global0 instead of zeroing when it does not have as many counts as
- it should.
+2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
-2023-03-14 Martin Jambor <mjambor@suse.cz>
+ PR target/112987
+ * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
+ (aarch64_expand_epilogue): Use the new function.
+ (aarch64_split_compare_and_swap): Likewise.
+ (aarch64_split_atomic_op): Likewise.
- PR ipa/107925
- * ipa-cp.cc (update_specialized_profile): Drop orig_node_count to
- ipa count, remove assert, lenient_count_portion_handling, dump
- also orig_node_count.
-
-2023-03-14 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.cc (expand_vec_perm_movs):
- Handle V2SImode for TARGET_MMX_WITH_SSE.
- * config/i386/mmx.md (*mmx_movss_<mode>): Rename from *mmx_movss
- using V2FI mode iterator to handle both V2SI and V2SF modes.
+2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
-2023-03-14 Sam James <sam@gentoo.org>
+ PR middle-end/112971
+ * fold-const.cc (simplify_const_binop): New function for binop
+ simplification of two constant vectors when element-wise
+ handling is not necessary.
+ (const_binop): Call new function.
- * config/riscv/genrvv-type-indexer.cc: Avoid calloc() poisoning on musl by
- including <sstream> earlier.
- * system.h: Add INCLUDE_SSTREAM.
+2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
-2023-03-14 Richard Biener <rguenther@suse.de>
+ * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
+ * config/riscv/constraints.md: Likewise.
+ * config/riscv/corev.def: Likewise.
+ * config/riscv/corev.md: Likewise.
+ * config/riscv/predicates.md: Likewise.
+ * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
+ * config/riscv/riscv-ftypes.def: Likewise.
+ * config/riscv/riscv.opt: Likewise.
+ * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
+ * doc/extend.texi: Add XCVbitmanip builtin documentation.
+ * doc/sourcebuild.texi: Likewise.
- * tree-ssa-live.cc (remove_unused_locals): Do not treat
- the .DEFERRED_INIT of a variable as use, instead remove
- that if it is the only use.
+2024-01-25 Tobias Burnus <tburnus@baylibre.com>
-2023-03-14 Eric Botcazou <ebotcazou@adacore.com>
+ * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
- PR rtl-optimization/107762
- * expr.cc (emit_group_store): Revert latest change.
+2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
-2023-03-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ PR target/113538
+ * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
+ (riscv_fntype_abi): Ditto.
+ * config/riscv/riscv.opt: Ditto.
- PR tree-optimization/109005
- * tree-if-conv.cc (get_bitfield_rep): Replace BLKmode check with
- aggregate type check.
+2024-01-25 Jakub Jelinek <jakub@redhat.com>
-2023-03-14 Jakub Jelinek <jakub@redhat.com>
+ PR middle-end/113574
+ * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
+ count against TYPE_PRECISION rather than TYPE_SIZE.
- PR tree-optimization/109115
- * tree-vect-patterns.cc (vect_recog_divmod_pattern): Don't use
- r.upper_bound () on r.undefined_p () range.
+2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
-2023-03-14 Jan Hubicka <hubicka@ucw.cz>
+ PR target/113572
+ * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
+ Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
- PR tree-optimization/106896
- * profile-count.cc (profile_count::to_sreal_scale): Synchronize
- implementatoin with probability_in; avoid some asserts.
+2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
-2023-03-13 Max Filippov <jcmvbkbc@gmail.com>
+ PR target/113550
+ * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
+ whether each split instruction is a load that clobbers the source
+ address. Emit that instruction last if so.
- * config/xtensa/linux.h (TARGET_ASM_FILE_END): New macro.
+2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
-2023-03-13 Sean Bright <sean@seanbright.com>
+ PR target/113485
+ * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
+ pattern.
+ (<optab><Vnarrowq><mode>2): Use it instead of generating a
+ paradoxical subreg for the input.
- * doc/invoke.texi (Warning Options): Remove errant 'See'
- before @xref.
+2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-13 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
+ (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
+ predecessors dump information.
- * config/xtensa/xtensa.h (REG_OK_STRICT, REG_OK_FOR_INDEX_P,
- REG_OK_FOR_BASE_P): Remove.
+2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-13 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+ * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
+ redundant full available computation.
+ (pre_vsetvl::pre_global_vsetvl_info): Ditto.
- * config/riscv/vector-iterators.md (=vd,vr): Fine tune.
- (=vd,vd,vr,vr): Ditto.
- * config/riscv/vector.md: Ditto.
+2024-01-25 Jakub Jelinek <jakub@redhat.com>
-2023-03-13 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+ * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
+ * doc/rtl.texi (CONST_VECTOR): Likewise.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_compare_insn): Add operand predicate check.
+2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-13 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+ * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
+ * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
+ (pass_vsetvl::execute): Ditto.
+ * config/riscv/riscv.opt: Ditto.
- * config/riscv/vector.md: Fine tune RA constraints.
+2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
-2023-03-13 Tobias Burnus <tobias@codesourcery.com>
+ * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
+ * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
- * config/gcn/mkoffload.cc (main): Pass -save-temps on for the
- hsaco assemble/link.
+2024-01-25 Richard Biener <rguenther@suse.de>
-2023-03-13 Richard Biener <rguenther@suse.de>
+ PR tree-optimization/113576
+ * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
+ exits with may_be_zero niters when its the last one.
- PR tree-optimization/109046
- * tree-ssa-forwprop.cc (pass_forwprop::execute): Combine
- piecewise complex loads.
+2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
-2023-03-12 Jakub Jelinek <jakub@redhat.com>
+ * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
+ For symbols of type tls, non-zero Offset is not generated.
- * config/aarch64/aarch64.h (aarch64_bf16_type_node): Remove.
- (aarch64_bf16_ptr_type_node): Adjust comment.
- * config/aarch64/aarch64.cc (aarch64_gimplify_va_arg_expr): Use
- bfloat16_type_node rather than aarch64_bf16_type_node.
- (aarch64_libgcc_floating_mode_supported_p,
- aarch64_scalar_mode_supported_p): Also support BFmode.
- (aarch64_invalid_conversion, aarch64_invalid_unary_op): Remove.
- (aarch64_invalid_binary_op): Remove BFmode related rejections.
- (TARGET_INVALID_CONVERSION, TARGET_INVALID_UNARY_OP): Don't redefine.
- * config/aarch64/aarch64-builtins.cc (aarch64_bf16_type_node): Remove.
- (aarch64_int_or_fp_type): Use bfloat16_type_node rather than
- aarch64_bf16_type_node.
- (aarch64_init_simd_builtin_types): Likewise.
- (aarch64_init_bf16_types): Likewise. Don't create bfloat16_type_node,
- which is created in tree.cc already.
- * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): Likewise.
+2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
-2023-03-12 Roger Sayle <roger@nextmovesoftware.com>
+ * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
+ P9 with m32 and mpowerpc64.
- PR middle-end/109031
- * tree-chrec.cc (chrec_apply): When folding "{a, +, a} (x-1)",
- ensure that the type of x is as wide or wider than the type of a.
+2024-01-25 liuhongt <hongtao.liu@intel.com>
-2023-03-12 Tamar Christina <tamar.christina@arm.com>
+ * config/i386/i386-options.cc (ix86_option_override_internal):
+ Enable -mlam=u57 by default when compiled with
+ -fsanitize=hwaddress.
- PR target/108583
- * config/aarch64/aarch64-simd.md (@aarch64_bitmask_udiv<mode>3): Remove.
- (*bitmask_shift_plus<mode>): New.
- * config/aarch64/aarch64-sve2.md (*bitmask_shift_plus<mode>): New.
- (@aarch64_bitmask_udiv<mode>3): Remove.
- * config/aarch64/aarch64.cc
- (aarch64_vectorize_can_special_div_by_constant,
- TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST): Removed.
- (TARGET_VECTORIZE_PREFERRED_DIV_AS_SHIFTS_OVER_MULT,
- aarch64_vectorize_preferred_div_as_shifts_over_mult): New.
-
-2023-03-12 Tamar Christina <tamar.christina@arm.com>
-
- PR target/108583
- * target.def (preferred_div_as_shifts_over_mult): New.
- * doc/tm.texi.in: Document it.
- * doc/tm.texi: Regenerate.
- * targhooks.cc (default_preferred_div_as_shifts_over_mult): New.
- * targhooks.h (default_preferred_div_as_shifts_over_mult): New.
- * tree-vect-patterns.cc (vect_recog_divmod_pattern): Use it.
-
-2023-03-12 Tamar Christina <tamar.christina@arm.com>
- Richard Sandiford <richard.sandiford@arm.com>
+2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
- PR target/108583
- * tree-ssa-math-opts.cc (convert_mult_to_fma): Inhibit FMA in case not
- single use.
+ * common/config/riscv/riscv-common.cc (riscv_implied_info):
+ Remove {"ztso", "a"}.
-2023-03-12 Tamar Christina <tamar.christina@arm.com>
- Andrew MacLeod <amacleod@redhat.com>
+2024-01-24 Martin Jambor <mjambor@suse.cz>
- PR target/108583
- * gimple-range-op.h (gimple_range_op_handler): Add maybe_non_standard.
- * gimple-range-op.cc (gimple_range_op_handler::gimple_range_op_handler):
- Use it.
- (gimple_range_op_handler::maybe_non_standard): New.
- * range-op.cc (class operator_widen_plus_signed,
- operator_widen_plus_signed::wi_fold, class operator_widen_plus_unsigned,
- operator_widen_plus_unsigned::wi_fold, class operator_widen_mult_signed,
- operator_widen_mult_signed::wi_fold, class operator_widen_mult_unsigned,
- operator_widen_mult_unsigned::wi_fold,
- ptr_op_widen_mult_signed, ptr_op_widen_mult_unsigned,
- ptr_op_widen_plus_signed, ptr_op_widen_plus_unsigned): New.
- * range-op.h (ptr_op_widen_mult_signed, ptr_op_widen_mult_unsigned,
- ptr_op_widen_plus_signed, ptr_op_widen_plus_unsigned): New
+ PR ipa/108007
+ PR ipa/112616
+ * cgraph.h (cgraph_edge): Add a parameter to
+ redirect_call_stmt_to_callee.
+ * ipa-param-manipulation.h (ipa_param_adjustments): Add a
+ parameter to modify_call.
+ (ipa_release_ssas_in_hash): Declare.
+ * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
+ parameter killed_ssas, pass it to padjs->modify_call.
+ * ipa-param-manipulation.cc (purge_all_uses): New function.
+ (ipa_param_adjustments::modify_call): New parameter killed_ssas.
+ Instead of substituting uses, invoke purge_all_uses. If
+ hash of killed SSAs has not been provided, create a temporary one
+ and release SSAs that have been added to it.
+ (compare_ssa_versions): New function.
+ (ipa_release_ssas_in_hash): Likewise.
+ * tree-inline.cc (redirect_all_calls): Create
+ id->killed_new_ssa_names earlier, pass it to edge redirection,
+ adjust a comment.
+ (copy_body): Release SSAs in id->killed_new_ssa_names.
-2023-03-12 Tamar Christina <tamar.christina@arm.com>
+2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
- PR target/108583
- * doc/tm.texi (TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST): Remove.
- * doc/tm.texi.in: Likewise.
- * explow.cc (round_push, align_dynamic_address): Revert previous patch.
- * expmed.cc (expand_divmod): Likewise.
- * expmed.h (expand_divmod): Likewise.
- * expr.cc (force_operand, expand_expr_divmod): Likewise.
- * optabs.cc (expand_doubleword_mod, expand_doubleword_divmod): Likewise.
- * target.def (can_special_div_by_const): Remove.
- * target.h: Remove tree-core.h include
- * targhooks.cc (default_can_special_div_by_const): Remove.
- * targhooks.h (default_can_special_div_by_const): Remove.
- * tree-vect-generic.cc (expand_vector_operation): Remove hook.
- * tree-vect-patterns.cc (vect_recog_divmod_pattern): Remove hook.
- * tree-vect-stmts.cc (vectorizable_operation): Remove hook.
-
-2023-03-12 Sandra Loosemore <sandra@codesourcery.com>
-
- * doc/install.texi2html: Fix issue number typo in comment.
-
-2023-03-12 Gaius Mulley <gaiusmod2@gmail.com>
-
- * doc/gm2.texi (Elementary data types): Equivalence BOOLEAN with
- bool.
-
-2023-03-12 Sandra Loosemore <sandra@codesourcery.com>
-
- * doc/invoke.texi (Optimize Options): Add markup to
- description of asan-kernel-mem-intrinsic-prefix, and clarify
- wording slightly.
-
-2023-03-11 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/extend.texi (Named Address Spaces): Drop a redundant link
- to AVR-LibC.
-
-2023-03-11 Jeff Law <jlaw@ventanamicro>
-
- PR web/88860
- * doc/extend.texi: Clarify Attribute Syntax a bit.
-
-2023-03-11 Sandra Loosemore <sandra@codesourcery.com>
-
- * doc/install.texi (Prerequisites): Suggest using newer versions
- of Texinfo.
- (Final install): Clean up and modernize discussion of how to
- build or obtain the GCC manuals.
- * doc/install.texi2html: Update comment to point to the PR instead
- of "makeinfo 4.7 brokenness" (it's not specific to that version).
-
-2023-03-10 Jakub Jelinek <jakub@redhat.com>
-
- PR target/107703
- * optabs.cc (expand_fix): For conversions from BFmode to integral,
- use shifts to convert it to SFmode first and then convert SFmode
- to integral.
-
-2023-03-10 Andrew Pinski <apinski@marvell.com>
-
- * config/aarch64/aarch64.md: Add a new define_split
- to help combine.
-
-2023-03-10 Richard Biener <rguenther@suse.de>
-
- * tree-ssa-structalias.cc (solve_graph): Immediately
- iterate self-cycles.
-
-2023-03-10 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109008
- * range-op-float.cc (float_widen_lhs_range): If not
- -frounding-math and not IBM double double format, extend lhs
- range just by 0.5ulp rather than 1ulp in each direction.
-
-2023-03-10 Jakub Jelinek <jakub@redhat.com>
-
- PR target/107998
- * config.gcc (x86_64-*-cygwin*): Don't add i386/t-cygwin-w64 into
- $tmake_file.
- * config/i386/t-cygwin-w64: Remove.
-
-2023-03-10 Jakub Jelinek <jakub@redhat.com>
-
- PR plugins/108634
- * tree-core.h (tree_code_type, tree_code_length): For C++11 or
- C++14, don't declare as extern const arrays.
- (tree_code_type_tmpl, tree_code_length_tmpl): New types with
- static constexpr member arrays for C++11 or C++14.
- * tree.h (TREE_CODE_CLASS): For C++11 or C++14 use
- tree_code_type_tmpl <0>::tree_code_type instead of tree_code_type.
- (TREE_CODE_LENGTH): For C++11 or C++14 use
- tree_code_length_tmpl <0>::tree_code_length instead of
- tree_code_length.
- * tree.cc (tree_code_type, tree_code_length): Remove.
-
-2023-03-10 Jakub Jelinek <jakub@redhat.com>
-
- PR other/108464
- * common.opt (fcanon-prefix-map): New option.
- * opts.cc: Include file-prefix-map.h.
- (flag_canon_prefix_map): New variable.
- (common_handle_option): Handle OPT_fcanon_prefix_map.
- (gen_command_line_string): Ignore OPT_fcanon_prefix_map.
- * file-prefix-map.h (flag_canon_prefix_map): Declare.
- * file-prefix-map.cc (struct file_prefix_map): Add canonicalize
- member.
- (add_prefix_map): Initialize canonicalize member from
- flag_canon_prefix_map, and if true canonicalize it using lrealpath.
- (remap_filename): Revert 2022-11-01 and 2022-11-07 changes,
- use lrealpath result only for map->canonicalize map entries.
- * lto-opts.cc (lto_write_options): Ignore OPT_fcanon_prefix_map.
- * opts-global.cc (handle_common_deferred_options): Clear
- flag_canon_prefix_map at the start and handle OPT_fcanon_prefix_map.
- * doc/invoke.texi (-fcanon-prefix-map): Document.
- (-ffile-prefix-map, -fdebug-prefix-map, -fprofile-prefix-map): Add
- see also for -fcanon-prefix-map.
- * doc/cppopts.texi (-fmacro-prefix-map): Likewise.
+ PR target/113486
+ * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
+ TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
-2023-03-10 Jakub Jelinek <jakub@redhat.com>
+2024-01-24 Monk Chiang <monk.chiang@sifive.com>
- PR c/108079
- * cgraphunit.cc (check_global_declaration): Don't warn for unused
- variables which have OPT_Wunused_variable warning suppressed.
-
-2023-03-10 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/109008
- * range-op-float.cc (float_widen_lhs_range): If lb is
- minimum representable finite number or ub is maximum
- representable finite number, instead of widening it to
- -inf or inf widen it to negative or positive 0x0.8p+(EMAX+1).
- Temporarily clear flag_finite_math_only when canonicalizing
- the widened range.
-
-2023-03-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-builtins.cc (riscv_gimple_fold_builtin): New function.
- * config/riscv/riscv-protos.h (riscv_gimple_fold_builtin): Ditto.
- (gimple_fold_builtin): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc (class read_vl): New class.
- (class vleff): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (read_vl): Ditto.
- (vleff): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct read_vl_def): Ditto.
- (struct fault_load_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc
- (rvv_arg_type_info::get_tree_type): Add size_ptr.
- (gimple_folder::gimple_folder): New class.
- (gimple_folder::fold): Ditto.
- (gimple_fold_builtin): New function.
- (get_read_vl_instance): Ditto.
- (get_read_vl_decl): Ditto.
- * config/riscv/riscv-vector-builtins.def (size_ptr): Add size_ptr.
- * config/riscv/riscv-vector-builtins.h (class gimple_folder): New class.
- (get_read_vl_instance): New function.
- (get_read_vl_decl): Ditto.
- * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Ditto.
- (read_vl_insn_p): Ditto.
- (available_occurrence_p): Ditto.
- (backward_propagate_worthwhile_p): Ditto.
- (gen_vsetvl_pat): Adapt for vleff support.
- (get_forward_read_vl_insn): New function.
- (get_backward_fault_first_load_insn): Ditto.
- (source_equal_p): Adapt for vleff support.
- (first_ratio_invalid_for_second_sew_p): Remove.
- (first_ratio_invalid_for_second_lmul_p): Ditto.
- (first_lmul_less_than_second_lmul_p): Ditto.
- (first_ratio_less_than_second_ratio_p): Ditto.
- (support_relaxed_compatible_p): New function.
- (vector_insn_info::operator>): Remove.
- (vector_insn_info::operator>=): Refine.
- (vector_insn_info::parse_insn): Adapt for vleff support.
- (vector_insn_info::compatible_p): Ditto.
- (vector_insn_info::update_fault_first_load_avl): New function.
- (pass_vsetvl::transfer_after): Adapt for vleff support.
- (pass_vsetvl::demand_fusion): Ditto.
- (pass_vsetvl::cleanup_insns): Ditto.
- * config/riscv/riscv-vsetvl.def (DEF_INCOMPATIBLE_COND): Remove
- redundant condtions.
- * config/riscv/riscv-vsetvl.h (struct demands_cond): New function.
- * config/riscv/riscv.cc (TARGET_GIMPLE_FOLD_BUILTIN): New target hook.
- * config/riscv/riscv.md: Adapt for vleff support.
- * config/riscv/t-riscv: Ditto.
- * config/riscv/vector-iterators.md: New iterator.
- * config/riscv/vector.md (read_vlsi): New pattern.
- (read_vldi_zero_extend): Ditto.
- (@pred_fault_load<mode>): Ditto.
-
-2023-03-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_ternop_insn): Use maybe_gen_insn instead.
- (function_expander::use_widen_ternop_insn): Ditto.
- * optabs.cc (maybe_gen_insn): Extend nops handling.
-
-2023-03-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Split indexed load
- patterns according to RVV ISA.
- * config/riscv/vector-iterators.md: New iterators.
- * config/riscv/vector.md
- (@pred_indexed_<order>load<VNX1_QHSD:mode><VNX1_QHSDI:mode>): Remove.
- (@pred_indexed_<order>load<mode>_same_eew): New pattern.
- (@pred_indexed_<order>load<mode>_x2_greater_eew): Ditto.
- (@pred_indexed_<order>load<mode>_x4_greater_eew): Ditto.
- (@pred_indexed_<order>load<mode>_x8_greater_eew): Ditto.
- (@pred_indexed_<order>load<mode>_x2_smaller_eew): Ditto.
- (@pred_indexed_<order>load<mode>_x4_smaller_eew): Ditto.
- (@pred_indexed_<order>load<mode>_x8_smaller_eew): Ditto.
- (@pred_indexed_<order>load<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Remove.
- (@pred_indexed_<order>load<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
-
-2023-03-10 Michael Collison <collison@rivosinc.com>
-
- * tree-vect-loop-manip.cc (vect_do_peeling): Use
- result of constant_lower_bound instead of vf for the lower
- bound of the epilog loop trip count.
-
-2023-03-09 Tamar Christina <tamar.christina@arm.com>
-
- * passes.cc (emergency_dump_function): Finish graph generation.
-
-2023-03-09 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.md (tbranch_<code><mode>3): Restrict to SHORT
- and bottom bit only.
-
-2023-03-09 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/108980
- * gimple-array-bounds.cc (array_bounds_checker::check_array_ref):
- Reorgnize the call to warning for not strict flexible arrays
- to be before the check of warned.
-
-2023-03-09 Jason Merrill <jason@redhat.com>
-
- * doc/extend.texi: Comment out __is_deducible docs.
-
-2023-03-09 Jason Merrill <jason@redhat.com>
-
- PR c++/105841
- * doc/extend.texi (Type Traits):: Document __is_deducible.
-
-2023-03-09 Costas Argyris <costas.argyris@gmail.com>
-
- PR driver/108865
- * config.host: add object for x86_64-*-mingw*.
- * config/i386/sym-mingw32.cc: dummy file to attach
- symbol.
- * config/i386/utf8-mingw32.rc: windres resource file.
- * config/i386/winnt-utf8.manifest: XML manifest to
- enable UTF-8.
- * config/i386/x-mingw32: reference to x-mingw32-utf8.
- * config/i386/x-mingw32-utf8: Makefile fragment to
- embed UTF-8 manifest.
-
-2023-03-09 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * lra-constraints.cc (process_alt_operands): Use operand modes for
- clobbered regs instead of the biggest access mode.
-
-2023-03-09 Richard Biener <rguenther@suse.de>
-
- PR middle-end/108995
- * fold-const.cc (extract_muldiv_1): Avoid folding
- (CST * b) / CST2 when sanitizing overflow and we rely on
- overflow being undefined.
-
-2023-03-09 Jakub Jelinek <jakub@redhat.com>
- Richard Biener <rguenther@suse.de>
+ PR target/113095
+ * config/riscv/sfb.md: New splitters to rewrite single bit
+ sign extension as the condition to SFB instructions.
- PR tree-optimization/109008
- * range-op-float.cc (float_widen_lhs_range): New function.
- (foperator_plus::op1_range, foperator_minus::op1_range,
- foperator_minus::op2_range, foperator_mult::op1_range,
- foperator_div::op1_range, foperator_div::op2_range): Use it.
-
-2023-03-07 Jonathan Grant <jg@jguk.org>
-
- PR sanitizer/81649
- * doc/invoke.texi (Instrumentation Options): Clarify
- LeakSanitizer behavior.
-
-2023-03-07 Benson Muite <benson_muite@emailplus.org>
-
- * doc/install.texi (Prerequisites): Add link to gmplib.org.
-
-2023-03-07 Pan Li <pan2.li@intel.com>
- Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- PR target/108185
- PR target/108654
- * config/riscv/riscv-modes.def (ADJUST_PRECISION): Adjust VNx*BI
- modes.
- * config/riscv/riscv.cc (riscv_v_adjust_precision): New.
- * config/riscv/riscv.h (riscv_v_adjust_precision): New.
- * genmodes.cc (adj_precision): New.
- (ADJUST_PRECISION): New.
- (emit_mode_adjustments): Handle ADJUST_PRECISION.
-
-2023-03-07 Hans-Peter Nilsson <hp@axis.com>
-
- * doc/sourcebuild.texi: Document check_effective_target_tail_call.
-
-2023-03-06 Paul-Antoine Arras <pa@codesourcery.com>
-
- * config/gcn/gcn-valu.md (<expander><mode>3_exec): Add patterns for
- {s|u}{max|min} in QI, HI and DI modes.
- (<expander><mode>3): Add pattern for {s|u}{max|min} in DI mode.
- (cond_<fexpander><mode>): Add pattern for cond_f{max|min}.
- (cond_<expander><mode>): Add pattern for cond_{s|u}{max|min}.
- * config/gcn/gcn.cc (gcn_spill_class): Allow the exec register to be
- saved in SGPRs.
-
-2023-03-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109025
- * tree-vect-loop.cc (vect_is_simple_reduction): Verify
- the inner LC PHI use is the inner loop PHI latch definition
- before classifying an outer PHI as double reduction.
-
-2023-03-06 Jan Hubicka <hubicka@ucw.cz>
-
- PR target/108429
- * config/i386/x86-tune.def (X86_TUNE_USE_SCATTER_2PARTS): Enable for
- generic.
- (X86_TUNE_USE_SCATTER_4PARTS): Likewise.
- (X86_TUNE_USE_SCATTER): Likewise.
-
-2023-03-06 Xi Ruoyao <xry111@xry111.site>
-
- PR target/109000
- * config/loongarch/loongarch.h (FP_RETURN): Use
- TARGET_*_FLOAT_ABI instead of TARGET_*_FLOAT.
- (UNITS_PER_FP_ARG): Likewise.
-
-2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (reg_available_p): Fix bug.
- (pass_vsetvl::backward_demand_fusion): Ditto.
-
-2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
- SiYu Wu <siyu@isrc.iscas.ac.cn>
-
- * config/riscv/crypto.md (riscv_sm3p0_<mode>): Add ZKSED's and ZKSH's
- instructions.
- (riscv_sm3p1_<mode>): New.
- (riscv_sm4ed_<mode>): New.
- (riscv_sm4ks_<mode>): New.
- * config/riscv/riscv-builtins.cc (AVAIL): Add ZKSED's and ZKSH's AVAIL.
- * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): Add ZKSED's and
- ZKSH's built-in functions.
-
-2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
- SiYu Wu <siyu@isrc.iscas.ac.cn>
-
- * config/riscv/crypto.md (riscv_sha256sig0_<mode>): Add ZKNH's instructions.
- (riscv_sha256sig1_<mode>): New.
- (riscv_sha256sum0_<mode>): New.
- (riscv_sha256sum1_<mode>): New.
- (riscv_sha512sig0h): New.
- (riscv_sha512sig0l): New.
- (riscv_sha512sig1h): New.
- (riscv_sha512sig1l): New.
- (riscv_sha512sum0r): New.
- (riscv_sha512sum1r): New.
- (riscv_sha512sig0): New.
- (riscv_sha512sig1): New.
- (riscv_sha512sum0): New.
- (riscv_sha512sum1): New.
- * config/riscv/riscv-builtins.cc (AVAIL): And ZKNH's AVAIL.
- * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): And ZKNH's
- built-in functions.
- (DIRECT_BUILTIN): Add new.
-
-2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
- SiYu Wu <siyu@isrc.iscas.ac.cn>
-
- * config/riscv/constraints.md (D03): Add constants of bs and rnum.
- (DsA): New.
- * config/riscv/crypto.md (riscv_aes32dsi): Add ZKND's and ZKNE's instructions.
- (riscv_aes32dsmi): New.
- (riscv_aes64ds): New.
- (riscv_aes64dsm): New.
- (riscv_aes64im): New.
- (riscv_aes64ks1i): New.
- (riscv_aes64ks2): New.
- (riscv_aes32esi): New.
- (riscv_aes32esmi): New.
- (riscv_aes64es): New.
- (riscv_aes64esm): New.
- * config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL.
- * config/riscv/riscv-scalar-crypto.def (DIRECT_BUILTIN): Add ZKND's and
- ZKNE's built-in functions.
-
-2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
- SiYu Wu <siyu@isrc.iscas.ac.cn>
-
- * config/riscv/bitmanip.md: Add ZBKB's instructions.
- * config/riscv/riscv-builtins.cc (AVAIL): Add new.
- * config/riscv/riscv.md: Add new type for crypto instructions.
- * config/riscv/crypto.md: Add Scalar Cryptography extension's machine
- description file.
- * config/riscv/riscv-scalar-crypto.def: Add Scalar Cryptography
- extension's built-in function file.
-
-2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
- SiYu Wu <siyu@isrc.iscas.ac.cn>
-
- * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New.
- (RISCV_FTYPE_NAME3): New.
- (RISCV_ATYPE_QI): New.
- (RISCV_ATYPE_HI): New.
- (RISCV_FTYPE_ATYPES2): New.
- (RISCV_FTYPE_ATYPES3): New.
- * config/riscv/riscv-ftypes.def (2): New.
- (3): New.
-
-2023-03-05 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_rtx_costs): Fixed IN_RANGE() to
- use exact_log2().
-
-2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
-
- * config/riscv/predicates.md (vector_any_register_operand): New predicate.
- * config/riscv/riscv-c.cc (riscv_check_builtin_call): New function.
- (riscv_register_pragmas): Add builtin function check call.
- * config/riscv/riscv-protos.h (RVV_VUNDEF): Adapt macro.
- (check_builtin_call): New function.
- * config/riscv/riscv-vector-builtins-bases.cc (class vundefined): New class.
- (class vreinterpret): Ditto.
- (class vlmul_ext): Ditto.
- (class vlmul_trunc): Ditto.
- (class vset): Ditto.
- (class vget): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vluxei8): Change name.
- (vluxei16): Ditto.
- (vluxei32): Ditto.
- (vluxei64): Ditto.
- (vloxei8): Ditto.
- (vloxei16): Ditto.
- (vloxei32): Ditto.
- (vloxei64): Ditto.
- (vsuxei8): Ditto.
- (vsuxei16): Ditto.
- (vsuxei32): Ditto.
- (vsuxei64): Ditto.
- (vsoxei8): Ditto.
- (vsoxei16): Ditto.
- (vsoxei32): Ditto.
- (vsoxei64): Ditto.
- (vundefined): Add new intrinsic.
- (vreinterpret): Ditto.
- (vlmul_ext): Ditto.
- (vlmul_trunc): Ditto.
- (vset): Ditto.
- (vget): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct return_mask_def): New class.
- (struct narrow_alu_def): Ditto.
- (struct reduc_alu_def): Ditto.
- (struct vundefined_def): Ditto.
- (struct misc_def): Ditto.
- (struct vset_def): Ditto.
- (struct vget_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_EEW8_INTERPRET_OPS): New def.
- (DEF_RVV_EEW16_INTERPRET_OPS): Ditto.
- (DEF_RVV_EEW32_INTERPRET_OPS): Ditto.
- (DEF_RVV_EEW64_INTERPRET_OPS): Ditto.
- (DEF_RVV_X2_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X4_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X8_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X16_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X32_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X64_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_LMUL1_OPS): Ditto.
- (DEF_RVV_LMUL2_OPS): Ditto.
- (DEF_RVV_LMUL4_OPS): Ditto.
- (vint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint16m2_t): Ditto.
- (vuint16m4_t): Ditto.
- (vuint16m8_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
- (vuint64m1_t): Ditto.
- (vuint64m2_t): Ditto.
- (vuint64m4_t): Ditto.
- (vuint64m8_t): Ditto.
- (vint8mf4_t): Ditto.
- (vint8mf2_t): Ditto.
- (vint8m1_t): Ditto.
- (vint8m2_t): Ditto.
- (vint8m4_t): Ditto.
- (vint8m8_t): Ditto.
- (vuint8mf4_t): Ditto.
- (vuint8mf2_t): Ditto.
- (vuint8m1_t): Ditto.
- (vuint8m2_t): Ditto.
- (vuint8m4_t): Ditto.
- (vuint8m8_t): Ditto.
- (vint8mf8_t): Ditto.
- (vuint8mf8_t): Ditto.
- (vfloat32mf2_t): Ditto.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat64m1_t): Ditto.
- (vfloat64m2_t): Ditto.
- (vfloat64m4_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Ditto.
- (DEF_RVV_EEW8_INTERPRET_OPS): Ditto.
- (DEF_RVV_EEW16_INTERPRET_OPS): Ditto.
- (DEF_RVV_EEW32_INTERPRET_OPS): Ditto.
- (DEF_RVV_EEW64_INTERPRET_OPS): Ditto.
- (DEF_RVV_X2_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X4_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X8_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X16_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X32_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_X64_VLMUL_EXT_OPS): Ditto.
- (DEF_RVV_LMUL1_OPS): Ditto.
- (DEF_RVV_LMUL2_OPS): Ditto.
- (DEF_RVV_LMUL4_OPS): Ditto.
- (DEF_RVV_TYPE_INDEX): Ditto.
- (required_extensions_p): Adapt for new intrinsic support/
- (get_required_extensions): New function.
- (check_required_extensions): Ditto.
- (unsigned_base_type_p): Remove.
- (rvv_arg_type_info::get_scalar_ptr_type): New function.
- (get_mode_for_bitsize): Remove.
- (rvv_arg_type_info::get_scalar_const_ptr_type): New function.
- (rvv_arg_type_info::get_base_vector_type): Ditto.
- (rvv_arg_type_info::get_function_type_index): Ditto.
- (DEF_RVV_BASE_TYPE): New def.
- (function_builder::apply_predication): New class.
- (function_expander::mask_mode): Ditto.
- (function_checker::function_checker): Ditto.
- (function_checker::report_non_ice): Ditto.
- (function_checker::report_out_of_range): Ditto.
- (function_checker::require_immediate): Ditto.
- (function_checker::require_immediate_range): Ditto.
- (function_checker::check): Ditto.
- (check_builtin_call): Ditto.
- * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): New def.
- (DEF_RVV_BASE_TYPE): Ditto.
- (DEF_RVV_TYPE_INDEX): Ditto.
- (vbool64_t): Ditto.
- (vbool32_t): Ditto.
- (vbool16_t): Ditto.
- (vbool8_t): Ditto.
- (vbool4_t): Ditto.
- (vbool2_t): Ditto.
- (vbool1_t): Ditto.
- (vuint8mf8_t): Ditto.
- (vuint8mf4_t): Ditto.
- (vuint8mf2_t): Ditto.
- (vuint8m1_t): Ditto.
- (vuint8m2_t): Ditto.
- (vint8m4_t): Ditto.
- (vuint8m4_t): Ditto.
- (vint8m8_t): Ditto.
- (vuint8m8_t): Ditto.
- (vint16mf4_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint16m2_t): Ditto.
- (vuint16m4_t): Ditto.
- (vuint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
- (vuint64m1_t): Ditto.
- (vuint64m2_t): Ditto.
- (vuint64m4_t): Ditto.
- (vuint64m8_t): Ditto.
- (vfloat32mf2_t): Ditto.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat32m8_t): Ditto.
- (vfloat64m1_t): Ditto.
- (vfloat64m4_t): Ditto.
- (vector): Move it def.
- (scalar): Ditto.
- (mask): Ditto.
- (signed_vector): Ditto.
- (unsigned_vector): Ditto.
- (unsigned_scalar): Ditto.
- (vector_ptr): Ditto.
- (scalar_ptr): Ditto.
- (scalar_const_ptr): Ditto.
- (void): Ditto.
- (size): Ditto.
- (ptrdiff): Ditto.
- (unsigned_long): Ditto.
- (long): Ditto.
- (eew8_index): Ditto.
- (eew16_index): Ditto.
- (eew32_index): Ditto.
- (eew64_index): Ditto.
- (shift_vector): Ditto.
- (double_trunc_vector): Ditto.
- (quad_trunc_vector): Ditto.
- (oct_trunc_vector): Ditto.
- (double_trunc_scalar): Ditto.
- (double_trunc_signed_vector): Ditto.
- (double_trunc_unsigned_vector): Ditto.
- (double_trunc_unsigned_scalar): Ditto.
- (double_trunc_float_vector): Ditto.
- (float_vector): Ditto.
- (lmul1_vector): Ditto.
- (widen_lmul1_vector): Ditto.
- (eew8_interpret): Ditto.
- (eew16_interpret): Ditto.
- (eew32_interpret): Ditto.
- (eew64_interpret): Ditto.
- (vlmul_ext_x2): Ditto.
- (vlmul_ext_x4): Ditto.
- (vlmul_ext_x8): Ditto.
- (vlmul_ext_x16): Ditto.
- (vlmul_ext_x32): Ditto.
- (vlmul_ext_x64): Ditto.
- * config/riscv/riscv-vector-builtins.h (DEF_RVV_BASE_TYPE): New def.
- (struct function_type_info): New function.
- (struct rvv_arg_type_info): Ditto.
- (class function_checker): New class.
- (rvv_arg_type_info::get_scalar_type): New function.
- (rvv_arg_type_info::get_vector_type): Ditto.
- (function_expander::ret_mode): New function.
- (function_checker::arg_mode): Ditto.
- (function_checker::ret_mode): Ditto.
- * config/riscv/t-riscv: Add generator.
- * config/riscv/vector-iterators.md: New iterators.
- * config/riscv/vector.md (vundefined<mode>): New pattern.
- (@vundefined<mode>): Ditto.
- (@vreinterpret<mode>): Ditto.
- (@vlmul_extx2<mode>): Ditto.
- (@vlmul_extx4<mode>): Ditto.
- (@vlmul_extx8<mode>): Ditto.
- (@vlmul_extx16<mode>): Ditto.
- (@vlmul_extx32<mode>): Ditto.
- (@vlmul_extx64<mode>): Ditto.
- (*vlmul_extx2<mode>): Ditto.
- (*vlmul_extx4<mode>): Ditto.
- (*vlmul_extx8<mode>): Ditto.
- (*vlmul_extx16<mode>): Ditto.
- (*vlmul_extx32<mode>): Ditto.
- (*vlmul_extx64<mode>): Ditto.
- * config/riscv/genrvv-type-indexer.cc: New file.
-
-2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum vlen_enum): New enum.
- (slide1_sew64_helper): New function.
- * config/riscv/riscv-v.cc (compute_vlmax): Ditto.
- (get_unknown_min_value): Ditto.
- (force_vector_length_operand): Ditto.
- (gen_no_side_effects_vsetvl_rtx): Ditto.
- (get_vl_x2_rtx): Ditto.
- (slide1_sew64_helper): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc (class slideop): New class.
- (class vrgather): Ditto.
- (class vrgatherei16): Ditto.
- (class vcompress): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vslideup): Ditto.
- (vslidedown): Ditto.
- (vslide1up): Ditto.
- (vslide1down): Ditto.
- (vfslide1up): Ditto.
- (vfslide1down): Ditto.
- (vrgather): Ditto.
- (vrgatherei16): Ditto.
- (vcompress): Ditto.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_EI16_OPS): New macro.
- (vint8mf8_t): Ditto.
- (vint8mf4_t): Ditto.
- (vint8mf2_t): Ditto.
- (vint8m1_t): Ditto.
- (vint8m2_t): Ditto.
- (vint8m4_t): Ditto.
- (vint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint8mf8_t): Ditto.
- (vuint8mf4_t): Ditto.
- (vuint8mf2_t): Ditto.
- (vuint8m1_t): Ditto.
- (vuint8m2_t): Ditto.
- (vuint8m4_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint16m2_t): Ditto.
- (vuint16m4_t): Ditto.
- (vuint16m8_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
- (vuint64m1_t): Ditto.
- (vuint64m2_t): Ditto.
- (vuint64m4_t): Ditto.
- (vuint64m8_t): Ditto.
- (vfloat32mf2_t): Ditto.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat32m8_t): Ditto.
- (vfloat64m1_t): Ditto.
- (vfloat64m2_t): Ditto.
- (vfloat64m4_t): Ditto.
- (vfloat64m8_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_EI16_OPS): Ditto.
- * config/riscv/riscv.md: Adjust RVV instruction types.
- * config/riscv/vector-iterators.md (down): New iterator.
- (=vd,vr): New attribute.
- (UNSPEC_VSLIDE1UP): New unspec.
- * config/riscv/vector.md (@pred_slide<ud><mode>): New pattern.
- (*pred_slide<ud><mode>): Ditto.
- (*pred_slide<ud><mode>_extended): Ditto.
- (@pred_gather<mode>): Ditto.
- (@pred_gather<mode>_scalar): Ditto.
- (@pred_gatherei16<mode>): Ditto.
- (@pred_compress<mode>): Ditto.
-
-2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins.cc: Remove void_type_node.
-
-2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/constraints.md (Wb1): New constraint.
- * config/riscv/predicates.md
- (vector_least_significant_set_mask_operand): New predicate.
- (vector_broadcast_mask_operand): Ditto.
- * config/riscv/riscv-protos.h (enum vlmul_type): Adjust.
- (gen_scalar_move_mask): New function.
- * config/riscv/riscv-v.cc (gen_scalar_move_mask): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc (class vmv): New class.
- (class vmv_s): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vmv_x): Ditto.
- (vmv_s): Ditto.
- (vfmv_f): Ditto.
- (vfmv_s): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct scalar_move_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc (function_expander::mask_mode): Ditto.
- (function_expander::use_exact_insn): New function.
- (function_expander::use_contiguous_load_insn): New function.
- (function_expander::use_contiguous_store_insn): New function.
- (function_expander::use_ternop_insn): New function.
- (function_expander::use_widen_ternop_insn): New function.
- (function_expander::use_scalar_move_insn): New function.
- * config/riscv/riscv-vector-builtins.def (s): New operand suffix.
- * config/riscv/riscv-vector-builtins.h
- (function_expander::add_scalar_move_mask_operand): New class.
- * config/riscv/riscv-vsetvl.cc (ignore_vlmul_insn_p): New function.
- (scalar_move_insn_p): Ditto.
- (has_vsetvl_killed_avl_p): Ditto.
- (anticipatable_occurrence_p): Ditto.
- (insert_vsetvl): Ditto.
- (get_vl_vtype_info): Ditto.
- (calculate_sew): Ditto.
- (calculate_vlmul): Ditto.
- (incompatible_avl_p): Ditto.
- (different_sew_p): Ditto.
- (different_lmul_p): Ditto.
- (different_ratio_p): Ditto.
- (different_tail_policy_p): Ditto.
- (different_mask_policy_p): Ditto.
- (possible_zero_avl_p): Ditto.
- (first_ratio_invalid_for_second_sew_p): Ditto.
- (first_ratio_invalid_for_second_lmul_p): Ditto.
- (second_ratio_invalid_for_first_sew_p): Ditto.
- (second_ratio_invalid_for_first_lmul_p): Ditto.
- (second_sew_less_than_first_sew_p): Ditto.
- (first_sew_less_than_second_sew_p): Ditto.
- (compare_lmul): Ditto.
- (second_lmul_less_than_first_lmul_p): Ditto.
- (first_lmul_less_than_second_lmul_p): Ditto.
- (first_ratio_less_than_second_ratio_p): Ditto.
- (second_ratio_less_than_first_ratio_p): Ditto.
- (DEF_INCOMPATIBLE_COND): Ditto.
- (greatest_sew): Ditto.
- (first_sew): Ditto.
- (second_sew): Ditto.
- (first_vlmul): Ditto.
- (second_vlmul): Ditto.
- (first_ratio): Ditto.
- (second_ratio): Ditto.
- (vlmul_for_first_sew_second_ratio): Ditto.
- (ratio_for_second_sew_first_vlmul): Ditto.
- (DEF_SEW_LMUL_FUSE_RULE): Ditto.
- (always_unavailable): Ditto.
- (avl_unavailable_p): Ditto.
- (sew_unavailable_p): Ditto.
- (lmul_unavailable_p): Ditto.
- (ge_sew_unavailable_p): Ditto.
- (ge_sew_lmul_unavailable_p): Ditto.
- (ge_sew_ratio_unavailable_p): Ditto.
- (DEF_UNAVAILABLE_COND): Ditto.
- (same_sew_lmul_demand_p): Ditto.
- (propagate_avl_across_demands_p): Ditto.
- (reg_available_p): Ditto.
- (avl_info::has_non_zero_avl): Ditto.
- (vl_vtype_info::has_non_zero_avl): Ditto.
- (vector_insn_info::operator>=): Refactor.
- (vector_insn_info::parse_insn): Adjust for scalar move.
- (vector_insn_info::demand_vl_vtype): Remove.
- (vector_insn_info::compatible_p): New function.
- (vector_insn_info::compatible_avl_p): Ditto.
- (vector_insn_info::compatible_vtype_p): Ditto.
- (vector_insn_info::available_p): Ditto.
- (vector_insn_info::merge): Ditto.
- (vector_insn_info::fuse_avl): Ditto.
- (vector_insn_info::fuse_sew_lmul): Ditto.
- (vector_insn_info::fuse_tail_policy): Ditto.
- (vector_insn_info::fuse_mask_policy): Ditto.
- (vector_insn_info::dump): Ditto.
- (vector_infos_manager::release): Ditto.
- (pass_vsetvl::compute_local_backward_infos): Adjust for scalar move support.
- (pass_vsetvl::get_backward_fusion_type): Adjust for scalar move support.
- (pass_vsetvl::hard_empty_block_p): Ditto.
- (pass_vsetvl::backward_demand_fusion): Ditto.
- (pass_vsetvl::forward_demand_fusion): Ditto.
- (pass_vsetvl::refine_vsetvls): Ditto.
- (pass_vsetvl::cleanup_vsetvls): Ditto.
- (pass_vsetvl::commit_vsetvls): Ditto.
- (pass_vsetvl::propagate_avl): Ditto.
- * config/riscv/riscv-vsetvl.h (enum demand_status): New class.
- (struct demands_pair): Ditto.
- (struct demands_cond): Ditto.
- (struct demands_fuse_rule): Ditto.
- * config/riscv/vector-iterators.md: New iterator.
- * config/riscv/vector.md (@pred_broadcast<mode>): New pattern.
- (*pred_broadcast<mode>): Ditto.
- (*pred_broadcast<mode>_extended_scalar): Ditto.
- (@pred_extract_first<mode>): Ditto.
- (*pred_extract_first<mode>): Ditto.
- (@pred_extract_first_trunc<mode>): Ditto.
- * config/riscv/riscv-vsetvl.def: New file.
-
-2023-03-05 Lin Sinan <sinan.lin@linux.alibaba.com>
-
- * config/riscv/bitmanip.md: allow 0 constant in max/min
- pattern.
+2024-01-24 Jan Hubicka <jh@suse.cz>
-2023-03-05 Lin Sinan <sinan.lin@linux.alibaba.com>
+ PR middle-end/88345
+ * common.opt: (flimit-function-alignment): Reorder alphabeticaly
+ (fmin-function-alignment): New parameter.
+ * doc/invoke.texi: (-fmin-function-alignment): Document.
+ (-falign-functions,-falign-loops,-falign-labels): Mention that
+ aglinments are ignored in cold code.
+ * varasm.cc (assemble_start_function): Handle min-function-alignment.
- * config/riscv/bitmanip.md: Fix wrong index in the check.
+2024-01-24 Tamar Christina <tamar.christina@arm.com>
-2023-03-04 Jakub Jelinek <jakub@redhat.com>
+ PR target/109636
+ * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
+ mulv2di3): Remove.
+ * config/aarch64/iterators.md (VQDIV): Remove.
+ (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
+ SVE_I_SIMD_DI): New.
+ (VPRED, sve_lane_con): Add V4SI and V2DI.
+ * config/aarch64/aarch64-sve.md (<optab><mode>3,
+ @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
+ (mul<mode>3): New, split from <optab><mode>3.
+ (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
+ * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
+ *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
+ SVE_FULL_HSDI_SIMD_DI.
- PR middle-end/109006
- * vec.cc (test_auto_alias): Adjust comment for removal of
- m_vecdata.
- * read-rtl-function.cc (function_reader::parse_block): Likewise.
- * gdbhooks.py: Likewise.
+2024-01-24 Tamar Christina <tamar.christina@arm.com>
-2023-03-04 Jakub Jelinek <jakub@redhat.com>
+ PR tree-optimization/113552
+ * config/aarch64/aarch64.cc
+ (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
- PR testsuite/108973
- * selftest-diagnostic.cc
- (test_diagnostic_context::test_diagnostic_context): Set
- caret_max_width to 80.
+2024-01-24 Martin Jambor <mjambor@suse.cz>
-2023-03-03 Alexandre Oliva <oliva@adacore.com>
+ PR ipa/113490
+ * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
+ count is equal or greater than the limit. Use the limit from the
+ callee.
- * gimple-ssa-warn-access.cc
- (pass_waccess::check_dangling_stores): Skip non-stores.
+2024-01-24 YunQiang Su <syq@gcc.gnu.org>
-2023-03-03 Alexandre Oliva <oliva@adacore.com>
+ * configure.ac: Detect the explicit relocs support for
+ mips, and define C macro MIPS_EXPLICIT_RELOCS.
+ * config.in: Regenerated.
+ * configure: Regenerated.
+ * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
+ * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
+ * config/mips/mips.cc(mips_set_compression_mode): Sorry if
+ !TARGET_EXPLICIT_RELOCS instead of just set it.
+ * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
+ TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
+ * config/mips/mips.opt: Introduce -mexplicit-relocs= option
+ and define -m(no-)explicit-relocs as aliases.
- * config/arm/vfp.md (*thumb2_movsi_vfp): Drop blank after tab
- after vmsr and vmrs, and lower the case of P0.
+2024-01-24 Alex Coplan <alex.coplan@arm.com>
-2023-03-03 Jonathan Wakely <jwakely@redhat.com>
+ * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
+ to 1.
+ (-mlate-ldp-fusion): Likewise.
- PR middle-end/109006
- * gdbhooks.py (VecPrinter): Handle vec<T> as well as vec<T>*.
+2024-01-24 Tamar Christina <tamar.christina@arm.com>
-2023-03-03 Jonathan Wakely <jwakely@redhat.com>
+ * tree-vect-loop.cc (vect_get_vect_def,
+ vect_create_epilog_for_reduction): Rename main_exit_p to
+ last_val_reduc_p.
- PR middle-end/109006
- * gdbhooks.py (VecPrinter): Adjust for new vec layout.
+2024-01-24 Tamar Christina <tamar.christina@arm.com>
-2023-03-03 Jakub Jelinek <jakub@redhat.com>
+ PR tree-optimization/113364
+ * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
+ early exits then we must reduce from the first offset for all of them.
- PR c/108986
- * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
- Return immediately if OPT_Wnonnull or OPT_Wstringop_overflow_ is
- suppressed on stmt. For [static %E] warning, print access_nelts
- rather than access_size. Fix up comment wording.
+2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-03 Robin Dapp <rdapp@linux.ibm.com>
+ PR target/113495
+ * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
+ (get_regno): Ditto.
+ (get_bb_index): Ditto.
+ (pre_vsetvl::compute_avl_def_data): Ditto.
+ (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
+ (pre_vsetvl::pre_global_vsetvl_info): Ditto.
- * config/s390/driver-native.cc (s390_host_detect_local_cpu): Use
- arch14 instead of z16.
+2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
+ Richard Sandiford <richard.sandiford@arm.com>
-2023-03-03 Anthony Green <green@moxielogic.com>
+ PR target/100942
+ * ccmp.cc (ccmp_candidate_p): Add outer argument.
+ Allow if the outer is true and the lhs is used more
+ than once.
+ (expand_ccmp_expr): Update call to ccmp_candidate_p.
+ * expr.h (expand_expr_real_gassign): Declare.
+ * expr.cc (expand_expr_real_gassign): New function, split out from...
+ (expand_expr_real_1): ...here.
+ * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
+
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113089
+ * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
+ (fixup_debug_use): New.
+ (fixup_debug_uses_trailing_add): New.
+ (fixup_debug_uses): New. Use it ...
+ (ldp_bb_info::fuse_pair): ... here.
+ (try_promote_writeback): Call fixup_debug_uses_trailing_add to
+ fix up debug uses of the base register that are affected by
+ folding in the trailing add insn.
+
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113089
+ * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
+ Update trailing nondebug uses of the base register in the case
+ of cancelling writeback.
+
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113089
+ * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
+ (debug_insn_use_iterator): New.
+ (set_info::first_debug_insn_use): New.
+ (set_info::debug_insn_uses): New.
+ * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
+ (set_info::first_debug_insn_use): New.
+ (set_info::debug_insn_uses): New.
+
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113356
+ * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
+ Don't record hazards against the opposite insn in the pair.
+
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113070
+ * config/aarch64/aarch64-ldp-fusion.cc
+ (struct stp_change_builder): New.
+ (decide_stp_strategy): Reanme to ...
+ (try_repurpose_store): ... this.
+ (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
+ construct stp changes. Fix up uses when inserting new stp insns.
+
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113070
+ * rtl-ssa.h: Include hash-set.h.
+ * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
+ new_sets parameter and use it to keep track of new user-created sets.
+ (function_info::apply_changes_to_insn): Also call add_def on new sets.
+ (function_info::change_insns): Add hash_set to keep track of new
+ user-created defs. Plumb it through.
+ * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
+ apply_changes_to_insn.
+
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113070
+ * rtl-ssa/accesses.cc (function_info::create_use): New.
+ * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
+ Ensure new uses end up referring to permanent defs.
+ * rtl-ssa/functions.h (function_info::create_use): Declare.
- * config/moxie/moxie.cc (TARGET_LRA_P): Remove.
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
-2023-03-03 Anthony Green <green@moxielogic.com>
+ PR target/113070
+ * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
+ to finalize_new_accesses from the backwards placement loop, run it
+ forwards in a separate loop.
- * config/moxie/constraints.md (A, B, W): Change
- define_constraint to define_memory_constraint.
+2024-01-23 Richard Biener <rguenther@suse.de>
-2023-03-03 Xi Ruoyao <xry111@xry111.site>
+ PR tree-optimization/113552
+ * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
+ floor_log2 instead of exact_log2 on the number of calls.
- * toplev.cc (process_options): Fix the spelling of
- "-fstack-clash-protection".
+2024-01-23 Jeff Law <jlaw@ventanamicro.com>
+ Jakub Jelinek <jakub@redhat.com>
-2023-03-03 Richard Biener <rguenther@suse.de>
+ * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
+ decl.
- PR tree-optimization/109002
- * tree-ssa-pre.cc (compute_partial_antic_aux): Properly
- PHI-translate ANTIC_IN.
+2024-01-23 Richard Biener <rguenther@suse.de>
-2023-03-03 Jakub Jelinek <jakub@redhat.com>
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Separate single and multi-exit case when creating PHIs between
+ the main and epilogue.
- PR tree-optimization/108988
- * gimple-fold.cc (gimple_fold_builtin_fputs): Fold len to
- size_type_node before passing it as argument to fwrite. Formatting
- fixes.
+2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
-2023-03-03 Richard Biener <rguenther@suse.de>
+ PR target/112989
+ * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
+ MODE_single variants of functions that don't take tuple arguments.
- PR target/108738
- * config/i386/i386.opt (--param x86-stv-max-visits): New param.
- * doc/invoke.texi (--param x86-stv-max-visits): Document it.
- * config/i386/i386-features.h (scalar_chain::max_visits): New.
- (scalar_chain::build): Add bitmap parameter, return boolean.
- (scalar_chain::add_insn): Likewise.
- (scalar_chain::analyze_register_chain): Likewise.
- * config/i386/i386-features.cc (scalar_chain::scalar_chain):
- Initialize max_visits.
- (scalar_chain::analyze_register_chain): When we exhaust
- max_visits, abort. Also abort when running into any
- disallowed insn.
- (scalar_chain::add_insn): Propagate abort.
- (scalar_chain::build): Likewise. When aborting amend
- the set of disallowed insn with the insns set.
- (convert_scalars_to_vector): Adjust. Do not convert aborted
- chains.
+2024-01-23 Alex Coplan <alex.coplan@arm.com>
-2023-03-03 Richard Biener <rguenther@suse.de>
+ PR target/113114
+ * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
+ Don't assert recog success, just punt if the writeback pair
+ isn't recognized.
- PR debug/108772
- * dwarf2out.cc (dwarf2out_late_global_decl): Do not
- generate a DIE for a function scope static.
+2024-01-23 Jakub Jelinek <jakub@redhat.com>
-2023-03-03 Alexandre Oliva <oliva@adacore.com>
+ * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
+ ATTRIBUTE_UNUSED to decl.
- * config/vx-common.h (WINT_TYPE): Alias to "wchar_t".
+2024-01-23 Richard Biener <rguenther@suse.de>
-2023-03-02 Jakub Jelinek <jakub@redhat.com>
+ PR debug/107058
+ * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
+ handle unexpected but bogus DIE contexts when not checking
+ enabled.
- PR target/108883
- * target.h (emit_support_tinfos_callback): New typedef.
- * targhooks.h (default_emit_support_tinfos): Declare.
- * targhooks.cc (default_emit_support_tinfos): New function.
- * target.def (emit_support_tinfos): New target hook.
- * doc/tm.texi.in (emit_support_tinfos): Document it.
- * doc/tm.texi: Regenerated.
- * config/i386/i386.cc (ix86_emit_support_tinfos): New function.
- (TARGET_EMIT_SUPPORT_TINFOS): Redefine.
+2024-01-23 Jakub Jelinek <jakub@redhat.com>
-2023-03-02 Vladimir N. Makarov <vmakarov@redhat.com>
+ PR tree-optimization/113462
+ * fold-const.cc (native_interpret_int): Don't punt if total_bytes
+ is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
+ (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
+ sizes between 129 and 8192 bytes.
- * ira-costs.cc: Include print-rtl.h.
- (record_reg_classes, scan_one_insn): Add code to print debug info.
- (record_operand_costs): Find and use smaller cost for hard reg
- move.
+2024-01-23 Xi Ruoyao <xry111@xry111.site>
-2023-03-02 Kwok Cheung Yeung <kcy@codesourcery.com>
- Paul-Antoine Arras <pa@codesourcery.com>
+ * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
+ If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
+ for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
+ (loongarch_call_tls_get_addr): Do not split symbols of
+ SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
+ EXPLICIT_RELOCS_AUTO.
- * builtins.cc (mathfn_built_in_explicit): New.
- * config/gcn/gcn.cc: Include case-cfn-macros.h.
- (mathfn_built_in_explicit): Add prototype.
- (gcn_vectorize_builtin_vectorized_function): New.
- (gcn_libc_has_function): New.
- (TARGET_LIBC_HAS_FUNCTION): Define.
- (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Define.
+2024-01-23 Richard Biener <rguenther@suse.de>
-2023-03-02 Richard Sandiford <richard.sandiford@arm.com>
+ * alias.cc (known_base_value_p): Remove.
+ (find_base_value): Remove PLUS/MINUS handling
+ when both operands are not CONST_INT_P.
- PR tree-optimization/108979
- * tree-vect-stmts.cc (vectorizable_operation): Don't mask
- operations on invariants.
+2024-01-23 Richard Biener <rguenther@suse.de>
-2023-03-02 Robin Dapp <rdapp@linux.ibm.com>
+ PR rtl-optimization/113255
+ * alias.cc (find_base_term): Remove PLUS/MINUS handling
+ when both operands are not CONST_INT_P.
- * config/s390/predicates.md (vll_bias_operand): Add -1 bias.
- * config/s390/s390.cc (s390_option_override_internal): Make
- partial vector usage the default from z13 on.
- * config/s390/vector.md (len_load_v16qi): Add.
- (len_store_v16qi): Add.
+2024-01-23 Richard Biener <rguenther@suse.de>
-2023-03-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ PR debug/112718
+ * dwarf2out.cc (dwarf2out_finish): Reset all type units
+ for the fat part of an LTO compile.
- * simplify-rtx.cc (simplify_context::simplify_subreg): Use byte instead
- of constant 0 offset.
+2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
-2023-03-02 Robert Suchanek <robert.suchanek@imgtec.com>
+ * doc/sourcebuild.texi: Add attributes for keywords.
- * config/mips/mips.cc (mips_set_text_contents_type): Use HOST_WIDE_INT
- instead of long.
- * config/mips/mips-protos.h (mips_set_text_contents_type): Likewise.
+2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
-2023-03-02 Junxian Zhu <zhujunxian@oss.cipunited.com>
+ PR c++/90463
+ * doc/invoke.texi (Warning Options): Correct lists of options
+ enabled by -Wall and -Wextra by checking against common.opt
+ and c-family/c.opt.
- * config.gcc: add -with-{no-}msa build option.
- * config/mips/mips.h: Likewise.
- * doc/install.texi: Likewise.
+2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
-2023-03-02 Richard Sandiford <richard.sandiford@arm.com>
+ PR target/113030
+ * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
+ instead of cpu_optaliases.
+ (check_arch): Use arch_opt_alias instead of arch_optaliases.
- PR tree-optimization/108603
- * explow.cc (convert_memory_address_addr_space_1): Only wrap
- the result of a recursive call in a CONST if no instructions
- were emitted.
+2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-02 Richard Sandiford <richard.sandiford@arm.com>
+ * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
+ * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
+ * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
- PR tree-optimization/108430
- * tree-vect-stmts.cc (vectorizable_condition): Fix handling
- of inverted condition.
+2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-02 Jakub Jelinek <jakub@redhat.com>
+ PR target/109092
+ * config/riscv/riscv.md: Use reg instead of subreg.
- PR c++/108934
- * fold-const.cc (native_interpret_expr) <case REAL_CST>: Before memcmp
- comparison copy the bytes from ptr to a temporary buffer and clearing
- padding bits in there.
+2024-01-22 Tobias Burnus <tburnus@baylibre.com>
-2023-03-01 Tobias Burnus <tobias@codesourcery.com>
+ PR other/111966
+ * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
+ to match the compiler default.
+ (simple_object_copy_lto_debug_sections): Never unlink the outfile
+ on error as the caller does so.
+ (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
+ (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
- PR middle-end/108545
- * gimplify.cc (struct tree_operand_hash_no_se): New.
- (omp_index_mapping_groups_1, omp_index_mapping_groups,
- omp_reindex_mapping_groups, omp_mapped_by_containing_struct,
- omp_tsort_mapping_groups_1, omp_tsort_mapping_groups,
- oacc_resolve_clause_dependencies, omp_build_struct_sibling_lists,
- gimplify_scan_omp_clauses): Use tree_operand_hash_no_se instead
- of tree_operand_hash.
+2024-01-22 Richard Biener <rguenther@suse.de>
-2023-03-01 LIU Hao <lh_mouse@126.com>
+ PR tree-optimization/113373
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Create LC PHIs in the exit blocks where necessary.
+ * tree-vect-loop.cc (vectorizable_live_operation): Do not try
+ to handle missing LC PHIs.
+ (find_connected_edge): Remove.
+ (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
- PR pch/14940
- * config/i386/host-mingw32.cc (mingw32_gt_pch_get_address):
- Remove the size limit `pch_VA_max_size`
+2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-03-01 Tobias Burnus <tobias@codesourcery.com>
+ * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
- PR middle-end/108546
- * omp-low.cc (lower_omp_target): Remove optional handling
- on the receiver side, i.e. inside target (data), for
- use_device_ptr.
+2024-01-22 xuli <xuli1@eswincomputing.com>
-2023-03-01 Jakub Jelinek <jakub@redhat.com>
+ PR target/113420
+ * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
+ (registered_function::overloaded_hash):refactor.
+ (resolve_overloaded_builtin):avoid internal ICE.
- PR debug/108967
- * cfgexpand.cc (expand_debug_expr): Handle WIDEN_{PLUS,MINUS}_EXPR
- and VEC_WIDEN_{PLUS,MINUS}_{HI,LO}_EXPR.
+2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
-2023-03-01 Richard Biener <rguenther@suse.de>
+ PR target/82420
+ PR target/111279
+ * calls.cc (emit_library_call_value_1): Pass valid TYPE
+ to emit_push_insn.
+ * expr.cc (emit_push_insn): Likewise.
- PR tree-optimization/108970
- * tree-vect-loop-manip.cc (slpeel_can_duplicate_loop_p):
- Check we can copy the BBs.
- (slpeel_tree_duplicate_loop_to_edge_cfg): Avoid redundant
- check.
- (vect_do_peeling): Streamline error handling.
+2024-01-21 Jeff Law <jlaw@ventanamicro.com>
-2023-03-01 Richard Biener <rguenther@suse.de>
+ * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
+ correcction version of last change.
- PR tree-optimization/108950
- * tree-vect-patterns.cc (vect_recog_widen_sum_pattern):
- Check oprnd0 is defined in the loop.
- * tree-vect-loop.cc (vectorizable_reduction): Record all
- operands vector types, compute that of invariants and
- properly update their SLP nodes.
+2024-01-21 Jeff Law <jlaw@ventanamicro.com>
-2023-03-01 Kewen Lin <linkw@linux.ibm.com>
+ * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
+ fix bugs in signature.
- PR target/108240
- * config/rs6000/rs6000.cc (rs6000_option_override_internal): Allow
- implicit powerpc64 setting to be unset if 64 bit is enabled implicitly.
+2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
+ Richard Biener <rguenther@suse.de>
-2023-02-28 Qing Zhao <qing.zhao@oracle.com>
+ PR rtl-optimization/111267
+ * fwprop.cc (fwprop_propagation::profitabe_p): Rename
+ profitable_p method to likely_profitable_p.
+ (try_fwprop_subst_node): Update call to likely_profitable_p.
+ Only bail-out early when !prop.likely_profitable_p for instructions
+ that are not single sets. When comparing costs, bail-out if the
+ cost is unchanged and !prop.likely_profitable_p.
- PR middle-end/107411
- PR middle-end/107411
- * gimplify.cc (gimple_add_init_for_auto_var): Use sprintf to replace
- xasprintf.
- * tree-ssa-uninit.cc (warn_uninit): Handle the case when the
- LHS varaible of a .DEFERRED_INIT call doesn't have a DECL_NAME.
+2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
-2023-02-28 Jakub Jelinek <jakub@redhat.com>
+ PR c++/90464
+ * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
+ isn't enabled by -Wunused unless -Wextra is provided, and that
+ -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
+ -Wunused doesn't enable -Wunused-* options documented as behaving
+ otherwise, and list them explicitly.
- PR sanitizer/108894
- * ubsan.cc (ubsan_expand_bounds_ifn): Emit index >= bound
- comparison rather than index > bound.
- * gimple-fold.cc (gimple_fold_call): Use tree_int_cst_lt
- rather than tree_int_cst_le for IFN_UBSAN_BOUND comparison.
- * doc/invoke.texi (-fsanitize=bounds): Document that whether
- flexible array member-like arrays are instrumented or not depends
- on -fstrict-flex-arrays* options of strict_flex_array attributes.
- (-fsanitize=bounds-strict): Document that flexible array members
- are not instrumented.
+2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
-2023-02-27 Uroš Bizjak <ubizjak@gmail.com>
+ PR c/109708
+ * doc/invoke.texi (Warning Options): Fix broken example and
+ clean up/reorganize the others. Also describe what the short-form
+ options mean.
- PR target/108922
- Revert:
- * config/i386/i386.md (fmodxf3): Enable for flag_finite_math_only only.
- (fmod<mode>3): Ditto.
- (fpremxf4_i387): Ditto.
- (reminderxf3): Ditto.
- (reminder<mode>3): Ditto.
- (fprem1xf4_i387): Ditto.
-
-2023-02-27 Roger Sayle <roger@nextmovesoftware.com>
-
- * simplify-rtx.cc (simplify_unary_operation_1) <case FFS>: Avoid
- generating FFS with mismatched operand and result modes, by using
- an explicit SIGN_EXTEND/ZERO_EXTEND.
- <case POPCOUNT>: Likewise, for POPCOUNT of ZERO_EXTEND.
- <case PARITY>: Likewise, for PARITY of {ZERO,SIGN}_EXTEND.
-
-2023-02-27 Patrick Palka <ppalka@redhat.com>
-
- * hash-table.h (gt_pch_nx(hash_table<D>)): Remove static.
- * lra-int.h (lra_change_class): Likewise.
- * recog.h (which_op_alt): Likewise.
- * sel-sched-ir.h (sel_bb_empty_or_nop_p): Declare inline
- instead of static.
-
-2023-02-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
-
- * config/xtensa/xtensa-protos.h (xtensa_match_CLAMPS_imms_p):
- New prototype.
- * config/xtensa/xtensa.cc (xtensa_match_CLAMPS_imms_p):
- New function.
- * config/xtensa/xtensa.h (TARGET_CLAMPS): New macro definition.
- * config/xtensa/xtensa.md (*xtensa_clamps): New insn pattern.
-
-2023-02-27 Max Filippov <jcmvbkbc@gmail.com>
-
- * config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v2)
- (xtensa_get_config_v3): New functions.
-
-2023-02-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-simd.md (aarch64_abs<mode>): Fix typo in comment.
-
-2023-02-27 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/host-linux.cc (TRY_EMPTY_VM_SPACE): Modify the value of
- the macro to 0x1000000000.
-
-2023-02-25 Gaius Mulley <gaiusmod2@gmail.com>
-
- PR modula2/108261
- * doc/gm2.texi (-fm2-pathname): New option documented.
- (-fm2-pathnameI): New option documented.
- (-fm2-prefix=): New option documented.
- (-fruntime-modules=): Update default module list.
-
-2023-02-25 Max Filippov <jcmvbkbc@gmail.com>
-
- PR target/108919
- * config/xtensa/xtensa-protos.h
- (xtensa_prepare_expand_call): Rename to xtensa_expand_call.
- * config/xtensa/xtensa.cc (xtensa_prepare_expand_call): Rename
- to xtensa_expand_call.
- (xtensa_expand_call): Emit the call and add a clobber expression
- for the static chain to it in case of windowed ABI.
- * config/xtensa/xtensa.md (call, call_value, sibcall)
- (sibcall_value): Call xtensa_expand_call and complete expansion
- right after that call.
-
-2023-02-24 Richard Biener <rguenther@suse.de>
-
- * vec.h (vec<T, A, vl_embed>::m_vecdata): Remove.
- (vec<T, A, vl_embed>::m_vecpfx): Align as T to avoid
- changing alignment of vec<T, A, vl_embed> and simplifying
- address.
- (vec<T, A, vl_embed>::address): Compute as this + 1.
- (vec<T, A, vl_embed>::embedded_size): Use sizeof the
- vector instead of the offset of the m_vecdata member.
- (auto_vec<T, N>::m_data): Turn storage into
- uninitialized unsigned char.
- (auto_vec<T, N>::auto_vec): Allow allocation of one
- stack member. Initialize m_vec in a special way to
- avoid later stringop overflow diagnostics.
- * vec.cc (test_auto_alias): New.
- (vec_cc_tests): Call it.
-
-2023-02-24 Richard Biener <rguenther@suse.de>
-
- * vec.h (vec<T, A, vl_embed>::lower_bound): Adjust to
- take a const reference to the object, use address to
- access data.
- (vec<T, A, vl_embed>::contains): Use address to access data.
- (vec<T, A, vl_embed>::operator[]): Use address instead of
- m_vecdata to access data.
- (vec<T, A, vl_embed>::iterate): Likewise.
- (vec<T, A, vl_embed>::copy): Likewise.
- (vec<T, A, vl_embed>::quick_push): Likewise.
- (vec<T, A, vl_embed>::pop): Likewise.
- (vec<T, A, vl_embed>::quick_insert): Likewise.
- (vec<T, A, vl_embed>::ordered_remove): Likewise.
- (vec<T, A, vl_embed>::unordered_remove): Likewise.
- (vec<T, A, vl_embed>::block_remove): Likewise.
- (vec<T, A, vl_heap>::address): Likewise.
-
-2023-02-24 Martin Liska <mliska@suse.cz>
-
- PR sanitizer/108834
- * asan.cc (asan_add_global): Use proper TU name for normal
- global variables (and aux_base_name for the artificial one).
-
-2023-02-24 Jakub Jelinek <jakub@redhat.com>
-
- * config/i386/i386-builtin.def: Update description of BDESC
- and BDESC_FIRST in file comment to include mask2.
-
-2023-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/aarch64/aarch64-cores.def (FLAGS): Update comment.
-
-2023-02-24 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/108854
- * cgraphclones.cc (duplicate_thunk_for_node): If no parameter
- changes are needed, copy at least DECL_ARGUMENTS PARM_DECL
- nodes and adjust their DECL_CONTEXT.
-
-2023-02-24 Jakub Jelinek <jakub@redhat.com>
-
- PR target/108881
- * config/i386/i386-builtin.def (__builtin_ia32_cvtne2ps2bf16_v16bf,
- __builtin_ia32_cvtne2ps2bf16_v16bf_mask,
- __builtin_ia32_cvtne2ps2bf16_v16bf_maskz,
- __builtin_ia32_cvtne2ps2bf16_v8bf,
- __builtin_ia32_cvtne2ps2bf16_v8bf_mask,
- __builtin_ia32_cvtne2ps2bf16_v8bf_maskz,
- __builtin_ia32_cvtneps2bf16_v8sf_mask,
- __builtin_ia32_cvtneps2bf16_v8sf_maskz,
- __builtin_ia32_cvtneps2bf16_v4sf_mask,
- __builtin_ia32_cvtneps2bf16_v4sf_maskz,
- __builtin_ia32_dpbf16ps_v8sf, __builtin_ia32_dpbf16ps_v8sf_mask,
- __builtin_ia32_dpbf16ps_v8sf_maskz, __builtin_ia32_dpbf16ps_v4sf,
- __builtin_ia32_dpbf16ps_v4sf_mask,
- __builtin_ia32_dpbf16ps_v4sf_maskz): Require also
- OPTION_MASK_ISA_AVX512VL.
-
-2023-02-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * config/riscv/t-rtems: Keep only -mcmodel=medany 64-bit multilibs.
- Add non-compact 32-bit multilibs.
-
-2023-02-24 Junxian Zhu <zhujunxian@oss.cipunited.com>
-
- * config/mips/mips.md (*clo<mode>2): New pattern.
-
-2023-02-24 Prachi Godbole <prachi.godbole@imgtec.com>
-
- * config/mips/mips.h (machine_function): New variable
- use_hazard_barrier_return_p.
- * config/mips/mips.md (UNSPEC_JRHB): New unspec.
- (mips_hb_return_internal): New insn pattern.
- * config/mips/mips.cc (mips_attribute_table): Add attribute
- use_hazard_barrier_return.
- (mips_use_hazard_barrier_return_p): New static function.
- (mips_function_attr_inlinable_p): Likewise.
- (mips_compute_frame_info): Set use_hazard_barrier_return_p.
- Emit error for unsupported architecture choice.
- (mips_function_ok_for_sibcall, mips_can_use_return_insn):
- Return false for use_hazard_barrier_return.
- (mips_expand_epilogue): Emit hazard barrier return.
- * doc/extend.texi: Document use_hazard_barrier_return.
-
-2023-02-23 Max Filippov <jcmvbkbc@gmail.com>
-
- * config/xtensa/xtensa-dynconfig.cc (config.h, system.h)
- (coretypes.h, diagnostic.h, intl.h): Use "..." instead of <...>
- for the gcc-internal headers.
-
-2023-02-23 Max Filippov <jcmvbkbc@gmail.com>
-
- * config/xtensa/t-xtensa (xtensa-dynconfig.o): Use $(COMPILE)
- and $(POSTCOMPILE) instead of manual dependency listing.
- * config/xtensa/xtensa-dynconfig.c: Rename to ...
- * config/xtensa/xtensa-dynconfig.cc: ... this.
-
-2023-02-23 Arsen Arsenović <arsen@aarsen.me>
-
- * doc/cfg.texi: Reorder index entries around @items.
- * doc/cpp.texi: Ditto.
- * doc/cppenv.texi: Ditto.
- * doc/cppopts.texi: Ditto.
- * doc/generic.texi: Ditto.
- * doc/install.texi: Ditto.
- * doc/extend.texi: Ditto.
- * doc/invoke.texi: Ditto.
- * doc/md.texi: Ditto.
- * doc/rtl.texi: Ditto.
- * doc/tm.texi.in: Ditto.
- * doc/trouble.texi: Ditto.
- * doc/tm.texi: Regenerate.
+2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
-2023-02-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ PR c/102998
+ * doc/invoke.texi (Option Summary): Add -Warray-parameter.
+ (Warning Options): Correct/edit discussion of -Warray-parameter
+ to make the first example less confusing, and fill in missing info.
- * config/xtensa/xtensa.md: New peephole2 pattern that eliminates
- the occurrence of general-purpose register used only once and for
- transferring intermediate value.
+2024-01-20 Jakub Jelinek <jakub@redhat.com>
-2023-02-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ PR tree-optimization/113462
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
+ Handle rhs1 INTEGER_CST like SSA_NAME.
- * config/xtensa/xtensa.cc (machine_function): Add new member
- 'eliminated_callee_saved_bmp'.
- (xtensa_can_eliminate_callee_saved_reg_p): New function to
- determine whether the register can be eliminated or not.
- (xtensa_expand_prologue): Add invoking the above function and
- elimination the use of callee-saved register by using its stack
- slot through the stack pointer (or the frame pointer if needed)
- directly.
- (xtensa_expand_prologue): Modify to not emit register restoration
- insn from its stack slot if the register is already eliminated.
+2024-01-20 Jakub Jelinek <jakub@redhat.com>
-2023-02-23 Jakub Jelinek <jakub@redhat.com>
+ PR tree-optimization/113491
+ * tree-switch-conversion.cc (switch_conversion::build_constructors):
+ If elt.index has precision higher than sizetype, fold_convert it to
+ sizetype.
+ (switch_conversion::array_value_type): Return type if type is
+ BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
+ (switch_conversion::build_arrays): Use unsigned_type_for rather than
+ lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
+ above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
+ higher than sizetype, use sizetype as tidx type and fold_convert the
+ subtraction to sizetype.
- PR translation/108890
- * config/xtensa/xtensa-dynconfig.c (xtensa_load_config): Drop _()s
- around fatal_error format strings.
+2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-02-23 Richard Biener <rguenther@suse.de>
+ * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
+ (riscv_vector_mode_supported_any_target_p): Ditto.
- * tree-ssa-structalias.cc (handle_lhs_call): Do not
- re-create rhsc, only truncate it.
+2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
-2023-02-23 Jakub Jelinek <jakub@redhat.com>
+ PR target/110934
+ * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
+ (TARGET_ZERO_CALL_USED_REGS): Define.
- PR middle-end/106258
- * ipa-prop.cc (try_make_edge_direct_virtual_call): Handle
- BUILT_IN_UNREACHABLE_TRAP like BUILT_IN_UNREACHABLE.
+2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
-2023-02-23 Richard Biener <rguenther@suse.de>
+ PR target/108640
+ * config/m68k/m68k.cc (output_andsi3): Use QImode for
+ address adjusted for 1-byte RMW access.
+ (output_iorsi3): Likewise.
+ (output_xorsi3): Likewise.
- * tree-if-conv.cc (tree_if_conversion): Properly manage
- memory of refs and the contained data references.
+2024-01-19 Kito Cheng <kito.cheng@sifive.com>
-2023-02-23 Richard Biener <rguenther@suse.de>
+ * doc/invoke.texi (RISC-V Options): Add list of supported
+ extensions.
- PR tree-optimization/108888
- * tree-if-conv.cc (if_convertible_stmt_p): Set PLF_2 on
- calls to predicate.
- (predicate_statements): Only predicate calls with PLF_2.
+2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-02-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ PR target/113495
+ * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
+ (RVV_VUNDEF): Ditto.
+ * config/riscv/riscv-vsetvl.cc: Add timevar.
- * config/xtensa/xtensa.md
- (zero_cost_loop_start, zero_cost_loop_end, loop_end):
- Add missing "SI:" to PLUS RTXes.
+2024-01-19 Richard Biener <rguenther@suse.de>
-2023-02-23 Max Filippov <jcmvbkbc@gmail.com>
+ PR debug/113488
+ * lto-streamer-in.cc (lto_read_tree_1): When there isn't
+ an early DIE but there should be, do not pretend there is.
- PR target/108876
- * config/xtensa/xtensa.cc (xtensa_expand_epilogue):
- Emit (use (reg:SI A0_REG)) at the end in the sibling call
- (i.e. the same place as (return) in the normal call).
+2024-01-19 Richard Biener <rguenther@suse.de>
-2023-02-23 Max Filippov <jcmvbkbc@gmail.com>
+ PR tree-optimization/113494
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Handle endless loop on exit. Handle re-allocated PHI.
- Revert:
- 2023-02-21 Max Filippov <jcmvbkbc@gmail.com>
+2024-01-19 Jakub Jelinek <jakub@redhat.com>
- PR target/108876
- * config/xtensa/xtensa.cc (xtensa_expand_epilogue): Drop emit_use
- for A0_REG.
- * config/xtensa/xtensa.md (sibcall, sibcall_internal)
- (sibcall_value, sibcall_value_internal): Add 'use' expression
- for A0_REG.
+ PR tree-optimization/113464
+ * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
+ optimize loads into GIMPLE_ASM stmts.
-2023-02-23 Arsen Arsenović <arsen@aarsen.me>
+2024-01-19 Jakub Jelinek <jakub@redhat.com>
- * doc/cppdiropts.texi: Reorder @opindex commands to precede
- @items they relate to.
- * doc/cppopts.texi: Ditto.
- * doc/cppwarnopts.texi: Ditto.
- * doc/invoke.texi: Ditto.
- * doc/lto.texi: Ditto.
-
-2023-02-22 Andrew Stubbs <ams@codesourcery.com>
-
- * internal-fn.cc (expand_MASK_CALL): New.
- * internal-fn.def (MASK_CALL): New.
- * internal-fn.h (expand_MASK_CALL): New prototype.
- * omp-simd-clone.cc (simd_clone_adjust_argument_types): Set vector_type
- for mask arguments also.
- * tree-if-conv.cc: Include cgraph.h.
- (if_convertible_stmt_p): Do if conversions for calls to SIMD calls.
- (predicate_statements): Convert functions to IFN_MASK_CALL.
- * tree-vect-loop.cc (vect_get_datarefs_in_loop): Recognise
- IFN_MASK_CALL as a SIMD function call.
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Handle
- IFN_MASK_CALL as an inbranch SIMD function call.
- Generate the mask vector arguments.
-
-2023-02-22 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-bases.cc (class reducop): New class.
- (class widen_reducop): Ditto.
- (class freducop): Ditto.
- (class widen_freducop): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vredsum): Add reduction support.
- (vredmaxu): Ditto.
- (vredmax): Ditto.
- (vredminu): Ditto.
- (vredmin): Ditto.
- (vredand): Ditto.
- (vredor): Ditto.
- (vredxor): Ditto.
- (vwredsum): Ditto.
- (vwredsumu): Ditto.
- (vfredusum): Ditto.
- (vfredosum): Ditto.
- (vfredmax): Ditto.
- (vfredmin): Ditto.
- (vfwredosum): Ditto.
- (vfwredusum): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct reduc_alu_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_WI_OPS): New macro.
- (DEF_RVV_WU_OPS): Ditto.
- (DEF_RVV_WF_OPS): Ditto.
- (vint8mf8_t): Ditto.
- (vint8mf4_t): Ditto.
- (vint8mf2_t): Ditto.
- (vint8m1_t): Ditto.
- (vint8m2_t): Ditto.
- (vint8m4_t): Ditto.
- (vint8m8_t): Ditto.
- (vint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vuint8mf8_t): Ditto.
- (vuint8mf4_t): Ditto.
- (vuint8mf2_t): Ditto.
- (vuint8m1_t): Ditto.
- (vuint8m2_t): Ditto.
- (vuint8m4_t): Ditto.
- (vuint8m8_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint16m2_t): Ditto.
- (vuint16m4_t): Ditto.
- (vuint16m8_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
- (vfloat32mf2_t): Ditto.
- (vfloat32m1_t): Ditto.
- (vfloat32m2_t): Ditto.
- (vfloat32m4_t): Ditto.
- (vfloat32m8_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_WI_OPS): Ditto.
- (DEF_RVV_WU_OPS): Ditto.
- (DEF_RVV_WF_OPS): Ditto.
- (required_extensions_p): Add reduction support.
- (rvv_arg_type_info::get_base_vector_type): Ditto.
- (rvv_arg_type_info::get_tree_type): Ditto.
- * config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Ditto.
- * config/riscv/riscv.md: Ditto.
- * config/riscv/vector-iterators.md (minu): Ditto.
- * config/riscv/vector.md (@pred_reduc_<reduc><mode><vlmul1>): New patern.
- (@pred_reduc_<reduc><mode><vlmul1_zve32>): Ditto.
- (@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Ditto.
- (@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>):Ditto.
- (@pred_reduc_plus<order><mode><vlmul1>): Ditto.
- (@pred_reduc_plus<order><mode><vlmul1_zve32>): Ditto.
- (@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
-
-2023-02-22 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/iterators.md: New iterator.
- * config/riscv/riscv-vector-builtins-bases.cc (class widen_binop): New class.
- (enum ternop_type): New enum.
- (class vmacc): New class.
- (class imac): Ditto.
- (class vnmsac): Ditto.
- (enum widen_ternop_type): New enum.
- (class vmadd): Ditto.
- (class vnmsub): Ditto.
- (class iwmac): Ditto.
- (class vwmacc): Ditto.
- (class vwmaccu): Ditto.
- (class vwmaccsu): Ditto.
- (class vwmaccus): Ditto.
- (class reverse_binop): Ditto.
- (class vfmacc): Ditto.
- (class vfnmsac): Ditto.
- (class vfmadd): Ditto.
- (class vfnmsub): Ditto.
- (class vfnmacc): Ditto.
- (class vfmsac): Ditto.
- (class vfnmadd): Ditto.
- (class vfmsub): Ditto.
- (class vfwmacc): Ditto.
- (class vfwnmacc): Ditto.
- (class vfwmsac): Ditto.
- (class vfwnmsac): Ditto.
- (class float_misc): Ditto.
- (class fcmp): Ditto.
- (class vfclass): Ditto.
- (class vfcvt_x): Ditto.
- (class vfcvt_rtz_x): Ditto.
- (class vfcvt_f): Ditto.
- (class vfwcvt_x): Ditto.
- (class vfwcvt_rtz_x): Ditto.
- (class vfwcvt_f): Ditto.
- (class vfncvt_x): Ditto.
- (class vfncvt_rtz_x): Ditto.
- (class vfncvt_f): Ditto.
- (class vfncvt_rod_f): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h:
- * config/riscv/riscv-vector-builtins-functions.def (vzext): Ditto.
- (vsext): Ditto.
- (vfadd): Ditto.
- (vfsub): Ditto.
- (vfrsub): Ditto.
- (vfwadd): Ditto.
- (vfwsub): Ditto.
- (vfmul): Ditto.
- (vfdiv): Ditto.
- (vfrdiv): Ditto.
- (vfwmul): Ditto.
- (vfmacc): Ditto.
- (vfnmsac): Ditto.
- (vfmadd): Ditto.
- (vfnmsub): Ditto.
- (vfnmacc): Ditto.
- (vfmsac): Ditto.
- (vfnmadd): Ditto.
- (vfmsub): Ditto.
- (vfwmacc): Ditto.
- (vfwnmacc): Ditto.
- (vfwmsac): Ditto.
- (vfwnmsac): Ditto.
- (vfsqrt): Ditto.
- (vfrsqrt7): Ditto.
- (vfrec7): Ditto.
- (vfmin): Ditto.
- (vfmax): Ditto.
- (vfsgnj): Ditto.
- (vfsgnjn): Ditto.
- (vfsgnjx): Ditto.
- (vfneg): Ditto.
- (vfabs): Ditto.
- (vmfeq): Ditto.
- (vmfne): Ditto.
- (vmflt): Ditto.
- (vmfle): Ditto.
- (vmfgt): Ditto.
- (vmfge): Ditto.
- (vfclass): Ditto.
- (vfmerge): Ditto.
- (vfmv_v): Ditto.
- (vfcvt_x): Ditto.
- (vfcvt_xu): Ditto.
- (vfcvt_rtz_x): Ditto.
- (vfcvt_rtz_xu): Ditto.
- (vfcvt_f): Ditto.
- (vfwcvt_x): Ditto.
- (vfwcvt_xu): Ditto.
- (vfwcvt_rtz_x): Ditto.
- (vfwcvt_rtz_xu): Ditto.
- (vfwcvt_f): Ditto.
- (vfncvt_x): Ditto.
- (vfncvt_xu): Ditto.
- (vfncvt_rtz_x): Ditto.
- (vfncvt_rtz_xu): Ditto.
- (vfncvt_f): Ditto.
- (vfncvt_rod_f): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
- (struct move_def): Ditto.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_WEXTF_OPS): New macro.
- (DEF_RVV_CONVERT_I_OPS): Ditto.
- (DEF_RVV_CONVERT_U_OPS): Ditto.
- (DEF_RVV_WCONVERT_I_OPS): Ditto.
- (DEF_RVV_WCONVERT_U_OPS): Ditto.
- (DEF_RVV_WCONVERT_F_OPS): Ditto.
- (vfloat64m1_t): Ditto.
- (vfloat64m2_t): Ditto.
- (vfloat64m4_t): Ditto.
- (vfloat64m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
- (vuint64m1_t): Ditto.
- (vuint64m2_t): Ditto.
- (vuint64m4_t): Ditto.
- (vuint64m8_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CONVERT_I_OPS): Ditto.
- (DEF_RVV_CONVERT_U_OPS): Ditto.
- (DEF_RVV_WCONVERT_I_OPS): Ditto.
- (DEF_RVV_WCONVERT_U_OPS): Ditto.
- (DEF_RVV_WCONVERT_F_OPS): Ditto.
- (DEF_RVV_F_OPS): Ditto.
- (DEF_RVV_WEXTF_OPS): Ditto.
- (required_extensions_p): Adjust for floating-point support.
- (check_required_extensions): Ditto.
- (unsigned_base_type_p): Ditto.
- (get_mode_for_bitsize): Ditto.
- (rvv_arg_type_info::get_base_vector_type): Ditto.
- (rvv_arg_type_info::get_tree_type): Ditto.
- * config/riscv/riscv-vector-builtins.def (v_f): New define.
- (f): New define.
- (f_v): New define.
- (xu_v): New define.
- (f_w): New define.
- (xu_w): New define.
- * config/riscv/riscv-vector-builtins.h (enum rvv_base_type): New enum.
- (function_expander::arg_mode): New function.
- * config/riscv/vector-iterators.md (sof): New iterator.
- (vfrecp): Ditto.
- (copysign): Ditto.
- (n): Ditto.
- (msac): Ditto.
- (msub): Ditto.
- (fixuns_trunc): Ditto.
- (floatuns): Ditto.
- * config/riscv/vector.md (@pred_broadcast<mode>): New pattern.
- (@pred_<optab><mode>): Ditto.
- (@pred_<optab><mode>_scalar): Ditto.
- (@pred_<optab><mode>_reverse_scalar): Ditto.
- (@pred_<copysign><mode>): Ditto.
- (@pred_<copysign><mode>_scalar): Ditto.
- (@pred_mul_<optab><mode>): Ditto.
- (pred_mul_<optab><mode>_undef_merge): Ditto.
- (*pred_<madd_nmsub><mode>): Ditto.
- (*pred_<macc_nmsac><mode>): Ditto.
- (*pred_mul_<optab><mode>): Ditto.
- (@pred_mul_<optab><mode>_scalar): Ditto.
- (*pred_mul_<optab><mode>_undef_merge_scalar): Ditto.
- (*pred_<madd_nmsub><mode>_scalar): Ditto.
- (*pred_<macc_nmsac><mode>_scalar): Ditto.
- (*pred_mul_<optab><mode>_scalar): Ditto.
- (@pred_neg_mul_<optab><mode>): Ditto.
- (pred_neg_mul_<optab><mode>_undef_merge): Ditto.
- (*pred_<nmadd_msub><mode>): Ditto.
- (*pred_<nmacc_msac><mode>): Ditto.
- (*pred_neg_mul_<optab><mode>): Ditto.
- (@pred_neg_mul_<optab><mode>_scalar): Ditto.
- (*pred_neg_mul_<optab><mode>_undef_merge_scalar): Ditto.
- (*pred_<nmadd_msub><mode>_scalar): Ditto.
- (*pred_<nmacc_msac><mode>_scalar): Ditto.
- (*pred_neg_mul_<optab><mode>_scalar): Ditto.
- (@pred_<misc_op><mode>): Ditto.
- (@pred_class<mode>): Ditto.
- (@pred_dual_widen_<optab><mode>): Ditto.
- (@pred_dual_widen_<optab><mode>_scalar): Ditto.
- (@pred_single_widen_<plus_minus:optab><mode>): Ditto.
- (@pred_single_widen_<plus_minus:optab><mode>_scalar): Ditto.
- (@pred_widen_mul_<optab><mode>): Ditto.
- (@pred_widen_mul_<optab><mode>_scalar): Ditto.
- (@pred_widen_neg_mul_<optab><mode>): Ditto.
- (@pred_widen_neg_mul_<optab><mode>_scalar): Ditto.
- (@pred_cmp<mode>): Ditto.
- (*pred_cmp<mode>): Ditto.
- (*pred_cmp<mode>_narrow): Ditto.
- (@pred_cmp<mode>_scalar): Ditto.
- (*pred_cmp<mode>_scalar): Ditto.
- (*pred_cmp<mode>_scalar_narrow): Ditto.
- (@pred_eqne<mode>_scalar): Ditto.
- (*pred_eqne<mode>_scalar): Ditto.
- (*pred_eqne<mode>_scalar_narrow): Ditto.
- (@pred_merge<mode>_scalar): Ditto.
- (@pred_fcvt_x<v_su>_f<mode>): Ditto.
- (@pred_<fix_cvt><mode>): Ditto.
- (@pred_<float_cvt><mode>): Ditto.
- (@pred_widen_fcvt_x<v_su>_f<mode>): Ditto.
- (@pred_widen_<fix_cvt><mode>): Ditto.
- (@pred_widen_<float_cvt><mode>): Ditto.
- (@pred_extend<mode>): Ditto.
- (@pred_narrow_fcvt_x<v_su>_f<mode>): Ditto.
- (@pred_narrow_<fix_cvt><mode>): Ditto.
- (@pred_narrow_<float_cvt><mode>): Ditto.
- (@pred_trunc<mode>): Ditto.
- (@pred_rod_trunc<mode>): Ditto.
-
-2023-02-22 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/106258
- * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee,
- cgraph_update_edges_for_call_stmt_node, cgraph_node::verify_node):
- Handle BUILT_IN_UNREACHABLE_TRAP like BUILT_IN_UNREACHABLE.
- * cgraphclones.cc (cgraph_node::create_clone): Likewise.
-
-2023-02-22 Thomas Schwinge <thomas@codesourcery.com>
-
- * common.opt (-Wcomplain-wrong-lang): New.
- * doc/invoke.texi (-Wno-complain-wrong-lang): Document it.
- * opts-common.cc (prune_options): Handle it.
- * opts-global.cc (complain_wrong_lang): Use it.
-
-2023-02-21 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/108830
- * doc/invoke.texi: Document -fno-analyzer-suppress-followups.
-
-2023-02-21 Max Filippov <jcmvbkbc@gmail.com>
-
- PR target/108876
- * config/xtensa/xtensa.cc (xtensa_expand_epilogue): Drop emit_use
- for A0_REG.
- * config/xtensa/xtensa.md (sibcall, sibcall_internal)
- (sibcall_value, sibcall_value_internal): Add 'use' expression
- for A0_REG.
-
-2023-02-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108691
- * tree-ssa-dce.cc (eliminate_unnecessary_stmts): Remove
- assert about calls_setjmp not becoming true when it was false.
-
-2023-02-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108793
- * tree-ssa-loop-niter.cc (number_of_iterations_until_wrap):
- Use convert operands to niter_type when computing num.
-
-2023-02-21 Richard Biener <rguenther@suse.de>
+ PR tree-optimization/113463
+ * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
+ Only look through NOP_EXPRs if rhs1 doesn't have wider type than
+ lhs.
- Revert:
- 2023-02-13 Richard Biener <rguenther@suse.de>
+2024-01-19 Jakub Jelinek <jakub@redhat.com>
- PR tree-optimization/108691
- * tree-cfg.cc (notice_special_calls): When the CFG is built
- honor gimple_call_ctrl_altering_p.
- * cfgexpand.cc (expand_call_stmt): Clear cfun->calls_setjmp
- temporarily if the call is not control-altering.
- * calls.cc (emit_call_1): Do not add REG_SETJMP if
- cfun->calls_setjmp is not set. Do not alter cfun->calls_setjmp.
+ PR tree-optimization/113459
+ * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
+ TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
+ of SCALAR_INT_TYPE_MODE if type has BLKmode.
+ (vn_reference_lookup_3): Likewise. Formatting fix.
-2023-02-21 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+2024-01-19 Jakub Jelinek <jakub@redhat.com>
+ Richard Biener <rguenther@suse.de>
- * config/xtensa/xtensa.cc (xtensa_call_save_reg): Change to return
- true if register A0 (return address register) when -Og is specified.
+ * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
+ VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
+ * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
+ but adjust_address also for BLKmode mode and MEM op0.
-2023-02-20 Uroš Bizjak <ubizjak@gmail.com>
+2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
- * config/i386/predicates.md
- (general_x64constmem_operand): New predicate.
- * config/i386/i386.md (*cmpqi_ext<mode>_1):
- Use nonimm_x64constmem_operand.
- (*cmpqi_ext<mode>_3): Use general_x64constmem_operand.
- (*addqi_ext<mode>_1): Ditto.
- (*testqi_ext<mode>_1): Ditto.
- (*andqi_ext<mode>_1): Ditto.
- (*andqi_ext<mode>_1_cc): Ditto.
- (*<any_or:code>qi_ext<mode>_1): Ditto.
- (*xorqi_ext<mode>_1_cc): Ditto.
+ * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
+ extensions.
-2023-02-20 Jakub Jelinek <jakub2redhat.com>
+2024-01-19 Kito Cheng <kito.cheng@sifive.com>
- PR target/108862
- * config/rs6000/rs6000.md (umaddditi4): Swap gen_maddlddi4 with
- gen_umadddi4_highpart{,_le}.
+ * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
-2023-02-20 Kito Cheng <kito.cheng@sifive.com>
+2024-01-19 Kito Cheng <kito.cheng@sifive.com>
- * config/riscv/riscv.md (prefetch): Use r instead of p for the
- address operand.
- (riscv_prefetchi_<mode>): Ditto.
+ * common/config/riscv/riscv-common.cc
+ (riscv_subset_list::parse_std_ext): Remove.
+ (riscv_subset_list::parse_multiletter_ext): Remove.
+ * config/riscv/riscv-subset.h
+ (riscv_subset_list::parse_std_ext): Remove.
+ (riscv_subset_list::parse_multiletter_ext): Remove.
-2023-02-20 Richard Biener <rguenther@suse.de>
+2024-01-19 Kito Cheng <kito.cheng@sifive.com>
- PR tree-optimization/108816
- * tree-vect-loop-manip.cc (vect_loop_versioning): Adjust
- versioning condition split prerequesite, assert required
- invariant.
+ * common/config/riscv/riscv-common.cc
+ (riscv_subset_list::parse_single_std_ext): New parameter.
+ (riscv_subset_list::parse_single_multiletter_ext): Ditto.
+ (riscv_subset_list::parse_single_ext): Ditto.
+ (riscv_subset_list::parse): Relax the order for the input of ISA
+ string.
+ * config/riscv/riscv-subset.h
+ (riscv_subset_list::parse_single_std_ext): New parameter.
+ (riscv_subset_list::parse_single_multiletter_ext): Ditto.
+ (riscv_subset_list::parse_single_ext): Ditto.
-2023-02-20 Richard Biener <rguenther@suse.de>
+2024-01-19 Kito Cheng <kito.cheng@sifive.com>
- PR tree-optimization/108825
- * tree-ssa-loop-manip.cc (verify_loop_closed_ssa): For
- loop-local verfication only verify there's no pending SSA
- update.
+ * common/config/riscv/riscv-common.cc
+ (riscv_subset_list::parse_base_ext): New.
+ (riscv_subset_list::parse): Extract part of logic into
+ riscv_subset_list::parse_base_ext.
+ * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
+ New.
-2023-02-20 Richard Biener <rguenther@suse.de>
+2024-01-19 Kito Cheng <kito.cheng@sifive.com>
- PR tree-optimization/108819
- * tree-ssa-loop-niter.cc (number_of_iterations_cltz): Check
- we have an SSA name as iv_2 as expected.
+ * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
+ sorry message.
-2023-02-18 Jakub Jelinek <jakub@redhat.com>
+2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
- PR tree-optimization/108819
- * tree-ssa-reassoc.cc (update_ops): Fold new stmt in place.
+ * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
+ UNSPEC_CLMUL_VC.
-2023-02-18 Jakub Jelinek <jakub@redhat.com>
+2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
- PR target/108832
- * config/i386/i386-protos.h (ix86_replace_reg_with_reg): Declare.
- * config/i386/i386-expand.cc (ix86_replace_reg_with_reg): New
- function.
- * config/i386/i386.md: Replace replace_rtx calls in all peephole2s
- with ix86_replace_reg_with_reg.
+ PR c/110029
+ * doc/extend.texi (Common Variable Attributes): Explain what
+ happens when multiple variables with cleanups are in the same scope.
-2023-02-18 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
- * doc/invoke.texi (AVR Options): Update link to AVR-LibC.
+ PR ipa/108470
+ * doc/extend.texi (Common Function Attributes): Document that
+ noinline also disables some interprocedural optimizations and
+ improve flow to the part about using inline asm instead to
+ disable calls from being optimized away completely. Remove the
+ sentence that says noipa is mainly for internal compiler testing.
-2023-02-18 Xi Ruoyao <xry111@xry111.site>
+2024-01-18 John David Anglin <danglin@gcc.gnu.org>
- * config.gcc (triplet_abi): Set its value based on $with_abi,
- instead of $target.
- (la_canonical_triplet): Set it after $triplet_abi is set
- correctly.
- * config/loongarch/t-linux (MULTILIB_OSDIRNAMES): Make the
- multiarch tuple for lp64d "loongarch64-linux-gnu" (without
- "f64" suffix).
+ PR tree-optimization/69807
+ * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
-2023-02-18 Andrew Pinski <apinski@marvell.com>
+2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
- * match.pd: Remove #if GIMPLE around the
- "1 - a" pattern
+ PR target/108521
+ * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
+ from x86 Windows Options.
-2023-02-18 Andrew Pinski <apinski@marvell.com>
+2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
- * value-query.h (get_range_query): Return the global ranges
- for a nullptr func.
+ PR c/107942
+ * doc/extend.texi (C Extensions): Add new section to menu.
+ (Function Attributes): Move dangling index entries to....
+ (Const and Volatile Functions): New section.
-2023-02-17 Siddhesh Poyarekar <siddhesh@gotplt.org>
+2024-01-18 David Malcolm <dmalcolm@redhat.com>
- * doc/invoke.texi (@item -Wall): Fix typo in
- -Wuse-after-free.
+ PR middle-end/112684
+ * toplev.cc (toplev::main): Don't ICE in
+ -fdiagnostics-generate-patch when exiting after options,
+ since no edit context will have been created.
-2023-02-17 Uroš Bizjak <ubizjak@gmail.com>
-
- PR target/108831
- * config/i386/predicates.md
- (nonimm_x64constmem_operand): New predicate.
- * config/i386/i386.md (*addqi_ext<mode>_0): New insn pattern.
- (*subqi_ext<mode>_0): Ditto.
- (*andqi_ext<mode>_0): Ditto.
- (*<any_or:code>qi_ext<mode>_0): Ditto.
-
-2023-02-17 Uroš Bizjak <ubizjak@gmail.com>
-
- PR target/108805
- * simplify-rtx.cc (simplify_context::simplify_subreg): Use
- int_outermode instead of GET_MODE (tem) to prevent
- VOIDmode from entering simplify_gen_subreg.
-
-2023-02-17 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108821
- * tree-ssa-loop-im.cc (sm_seq_valid_bb): We can also not
- move volatile accesses.
-
-2023-02-17 Richard Biener <rguenther@suse.de>
-
- * tree-ssa.cc (ssa_undefined_value_p): Assert we are not
- called on virtual operands.
- * tree-ssa-sccvn.cc (vn_phi_lookup): Guard
- ssa_undefined_value_p calls.
- (vn_phi_insert): Likewise.
- (set_ssa_val_to): Likewise.
- (visit_phi): Avoid extra work with equivalences for
- virtual operand PHIs.
-
-2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-bases.cc (class mask_logic): New
- class.
- (class mask_nlogic): Ditto.
- (class mask_notlogic): Ditto.
- (class vmmv): Ditto.
- (class vmclr): Ditto.
- (class vmset): Ditto.
- (class vmnot): Ditto.
- (class vcpop): Ditto.
- (class vfirst): Ditto.
- (class mask_misc): Ditto.
- (class viota): Ditto.
- (class vid): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vmand): Ditto.
- (vmnand): Ditto.
- (vmandn): Ditto.
- (vmxor): Ditto.
- (vmor): Ditto.
- (vmnor): Ditto.
- (vmorn): Ditto.
- (vmxnor): Ditto.
- (vmmv): Ditto.
- (vmclr): Ditto.
- (vmset): Ditto.
- (vmnot): Ditto.
- (vcpop): Ditto.
- (vfirst): Ditto.
- (vmsbf): Ditto.
- (vmsif): Ditto.
- (vmsof): Ditto.
- (viota): Ditto.
- (vid): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
- (struct mask_alu_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc: Ditto.
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns): Fix bug
- for dest it scalar RVV intrinsics.
- * config/riscv/vector-iterators.md (sof): New iterator.
- * config/riscv/vector.md (@pred_<optab>n<mode>): New pattern.
- (@pred_<optab>not<mode>): New pattern.
- (@pred_popcount<VB:mode><P:mode>): New pattern.
- (@pred_ffs<VB:mode><P:mode>): New pattern.
- (@pred_<misc_op><mode>): New pattern.
- (@pred_iota<mode>): New pattern.
- (@pred_series<mode>): New pattern.
-
-2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-functions.def (vadc): Rename.
- (vsbc): Ditto.
- (vmerge): Ditto.
- (vmv_v): Ditto.
- * config/riscv/riscv-vector-builtins.cc: Ditto.
-
-2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-protos.h (sew64_scalar_helper): New function.
- * config/riscv/riscv-v.cc (has_vi_variant_p): Adjust.
- (sew64_scalar_helper): New function.
- * config/riscv/vector.md: Normalization.
-
-2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-functions.def (vsetvlmax): Rearrange.
- (vsm): Ditto.
- (vsse): Ditto.
- (vsoxei64): Ditto.
- (vsub): Ditto.
- (vand): Ditto.
- (vor): Ditto.
- (vxor): Ditto.
- (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- (vmin): Ditto.
- (vmax): Ditto.
- (vminu): Ditto.
- (vmaxu): Ditto.
- (vmul): Ditto.
- (vmulh): Ditto.
- (vmulhu): Ditto.
- (vmulhsu): Ditto.
- (vdiv): Ditto.
- (vrem): Ditto.
- (vdivu): Ditto.
- (vremu): Ditto.
- (vnot): Ditto.
- (vsext): Ditto.
- (vzext): Ditto.
- (vwadd): Ditto.
- (vwsub): Ditto.
- (vwmul): Ditto.
- (vwmulu): Ditto.
- (vwmulsu): Ditto.
- (vwaddu): Ditto.
- (vwsubu): Ditto.
- (vsbc): Ditto.
- (vmsbc): Ditto.
- (vnsra): Ditto.
- (vmerge): Ditto.
- (vmv_v): Ditto.
- (vmsne): Ditto.
- (vmslt): Ditto.
- (vmsgt): Ditto.
- (vmsle): Ditto.
- (vmsge): Ditto.
- (vmsltu): Ditto.
- (vmsgtu): Ditto.
- (vmsleu): Ditto.
- (vmsgeu): Ditto.
- (vnmsac): Ditto.
- (vmadd): Ditto.
- (vnmsub): Ditto.
- (vwmacc): Ditto.
- (vsadd): Ditto.
- (vssub): Ditto.
- (vssubu): Ditto.
- (vaadd): Ditto.
- (vasub): Ditto.
- (vasubu): Ditto.
- (vsmul): Ditto.
- (vssra): Ditto.
- (vssrl): Ditto.
- (vnclip): Ditto.
-
-2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md (@pred_<optab><mode>): Rearrange.
- (@pred_<optab><mode>_scalar): Ditto.
- (*pred_<optab><mode>_scalar): Ditto.
- (*pred_<optab><mode>_extended_scalar): Ditto.
-
-2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (riscv_run_selftests): Remove 'extern'.
- (init_builtins): Ditto.
- (mangle_builtin_type): Ditto.
- (verify_type_context): Ditto.
- (handle_pragma_vector): Ditto.
- (builtin_decl): Ditto.
- (expand_builtin): Ditto.
- (const_vec_all_same_in_range_p): Ditto.
- (legitimize_move): Ditto.
- (emit_vlmax_op): Ditto.
- (emit_nonvlmax_op): Ditto.
- (get_vlmul): Ditto.
- (get_ratio): Ditto.
- (get_ta): Ditto.
- (get_ma): Ditto.
- (get_avl_type): Ditto.
- (calculate_ratio): Ditto.
- (enum vlmul_type): Ditto.
- (simm5_p): Ditto.
- (neg_simm5_p): Ditto.
- (has_vi_variant_p): Ditto.
-
-2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (simm32_p): Remove.
- * config/riscv/riscv-v.cc (simm32_p): Ditto.
- * config/riscv/vector.md: Use immediate_operand
- instead of riscv_vector::simm32_p.
-
-2023-02-16 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/invoke.texi (Optimize Options): Reword the explanation
- getting minimal, maximal and default values of a parameter.
-
-2023-02-16 Patrick Palka <ppalka@redhat.com>
-
- * addresses.h: Mechanically drop 'static' from 'static inline'
- functions via s/^static inline/inline/g.
- * asan.h: Likewise.
- * attribs.h: Likewise.
- * basic-block.h: Likewise.
- * bitmap.h: Likewise.
- * cfghooks.h: Likewise.
- * cfgloop.h: Likewise.
- * cgraph.h: Likewise.
- * cselib.h: Likewise.
- * data-streamer.h: Likewise.
- * debug.h: Likewise.
- * df.h: Likewise.
- * diagnostic.h: Likewise.
- * dominance.h: Likewise.
- * dumpfile.h: Likewise.
- * emit-rtl.h: Likewise.
- * except.h: Likewise.
- * expmed.h: Likewise.
- * expr.h: Likewise.
- * fixed-value.h: Likewise.
- * gengtype.h: Likewise.
- * gimple-expr.h: Likewise.
- * gimple-iterator.h: Likewise.
- * gimple-predict.h: Likewise.
- * gimple-range-fold.h: Likewise.
- * gimple-ssa.h: Likewise.
- * gimple.h: Likewise.
- * graphite.h: Likewise.
- * hard-reg-set.h: Likewise.
- * hash-map.h: Likewise.
- * hash-set.h: Likewise.
- * hash-table.h: Likewise.
- * hwint.h: Likewise.
- * input.h: Likewise.
- * insn-addr.h: Likewise.
- * internal-fn.h: Likewise.
- * ipa-fnsummary.h: Likewise.
- * ipa-icf-gimple.h: Likewise.
- * ipa-inline.h: Likewise.
- * ipa-modref.h: Likewise.
- * ipa-prop.h: Likewise.
- * ira-int.h: Likewise.
- * ira.h: Likewise.
- * lra-int.h: Likewise.
- * lra.h: Likewise.
- * lto-streamer.h: Likewise.
- * memmodel.h: Likewise.
- * omp-general.h: Likewise.
- * optabs-query.h: Likewise.
- * optabs.h: Likewise.
- * plugin.h: Likewise.
- * pretty-print.h: Likewise.
- * range.h: Likewise.
- * read-md.h: Likewise.
- * recog.h: Likewise.
- * regs.h: Likewise.
- * rtl-iter.h: Likewise.
- * rtl.h: Likewise.
- * sbitmap.h: Likewise.
- * sched-int.h: Likewise.
- * sel-sched-ir.h: Likewise.
- * sese.h: Likewise.
- * sparseset.h: Likewise.
- * ssa-iterators.h: Likewise.
- * system.h: Likewise.
- * target-globals.h: Likewise.
- * target.h: Likewise.
- * timevar.h: Likewise.
- * tree-chrec.h: Likewise.
- * tree-data-ref.h: Likewise.
- * tree-iterator.h: Likewise.
- * tree-outof-ssa.h: Likewise.
- * tree-phinodes.h: Likewise.
- * tree-scalar-evolution.h: Likewise.
- * tree-sra.h: Likewise.
- * tree-ssa-alias.h: Likewise.
- * tree-ssa-live.h: Likewise.
- * tree-ssa-loop-manip.h: Likewise.
- * tree-ssa-loop.h: Likewise.
- * tree-ssa-operands.h: Likewise.
- * tree-ssa-propagate.h: Likewise.
- * tree-ssa-sccvn.h: Likewise.
- * tree-ssa.h: Likewise.
- * tree-ssanames.h: Likewise.
- * tree-streamer.h: Likewise.
- * tree-switch-conversion.h: Likewise.
- * tree-vectorizer.h: Likewise.
- * tree.h: Likewise.
- * wide-int.h: Likewise.
-
-2023-02-16 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/108657
- * tree-ssa-dse.cc (initialize_ao_ref_for_dse): If lhs of stmt
- exists and is not a SSA_NAME, call ao_ref_init even if the stmt
- is a call to internal or builtin function.
-
-2023-02-16 Jonathan Wakely <jwakely@redhat.com>
-
- * doc/invoke.texi (C++ Dialect Options): Suggest adding a
- using-declaration to unhide functions.
-
-2023-02-16 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/108783
- * tree-ssa-reassoc.cc (eliminate_redundant_comparison): If lcode
- is equal to TREE_CODE (t), op1 to newop1 and op2 to newop2, set
- t to curr->op. Otherwise, punt if either newop1 or newop2 are
- SSA_NAME_OCCURS_IN_ABNORMAL_PHI SSA_NAMEs.
-
-2023-02-16 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108791
- * tree-ssa-forwprop.cc (optimize_vector_load): Build
- the ADDR_EXPR of a TARGET_MEM_REF using a more meaningful
- type.
-
-2023-02-15 Eric Botcazou <ebotcazou@adacore.com>
-
- PR target/90458
- * config/i386/i386.cc (ix86_compute_frame_layout): Disable the
- effects of -fstack-clash-protection for TARGET_STACK_PROBE.
- (ix86_expand_prologue): Likewise.
-
-2023-02-15 Jan-Benedict Glaw <jbglaw@lug-owl.de>
-
- * config/bpf/bpf.cc (bpf_option_override): Fix doubled space.
-
-2023-02-15 Uroš Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (*cmpqi_ext<mode>_1): Use
- int248_register_operand predicate in zero_extract sub-RTX.
- (*cmpqi_ext<mode>_2): Ditto.
- (*cmpqi_ext<mode>_3): Ditto.
- (*cmpqi_ext<mode>_4): Ditto.
- (*extzvqi_mem_rex64): Ditto.
- (*extzvqi): Ditto.
- (*insvqi_1_mem_rex64): Ditto.
- (@insv<mode>_1): Ditto.
- (*insvqi_1): Ditto.
- (*insvqi_2): Ditto.
- (*insvqi_3): Ditto.
- (*extendqi<SWI24:mode>_ext_1): Ditto.
- (*addqi_ext<mode>_1): Ditto.
- (*addqi_ext<mode>_2): Ditto.
- (*subqi_ext<mode>_2): Ditto.
- (*testqi_ext<mode>_1): Ditto.
- (*testqi_ext<mode>_2): Ditto.
- (*andqi_ext<mode>_1): Ditto.
- (*andqi_ext<mode>_1_cc): Ditto.
- (*andqi_ext<mode>_2): Ditto.
- (*<any_or:code>qi_ext<mode>_1): Ditto.
- (*<any_or:code>qi_ext<mode>_2): Ditto.
- (*xorqi_ext<mode>_1_cc): Ditto.
- (*negqi_ext<mode>_2): Ditto.
- (*ashlqi_ext<mode>_2): Ditto.
- (*<any_shiftrt:insn>qi_ext<mode>_2): Ditto.
-
-2023-02-15 Uroš Bizjak <ubizjak@gmail.com>
-
- * config/i386/predicates.md (int248_register_operand):
- Rename from extr_register_operand.
- * config/i386/i386.md (*extv<mode>): Update for renamed predicate.
- (*extzx<mode>): Ditto.
- (*ashl<dwi>3_doubleword_mask): Use int248_register_operand predicate.
- (*ashl<mode>3_mask): Ditto.
- (*<any_shiftrt:insn><mode>3_mask): Ditto.
- (*<any_shiftrt:insn><dwi>3_doubleword_mask): Ditto.
- (*<any_rotate:insn><mode>3_mask): Ditto.
- (*<btsc><mode>_mask): Ditto.
- (*btr<mode>_mask): Ditto.
- (*jcc_bt<mode>_mask_1): Ditto.
-
-2023-02-15 Richard Biener <rguenther@suse.de>
-
- PR middle-end/26854
- * df-core.cc (df_worklist_propagate_forward): Put later
- blocks on worklist and only earlier blocks on pending.
- (df_worklist_propagate_backward): Likewise.
- (df_worklist_dataflow_doublequeue): Change the iteration
- to process new blocks in the same iteration if that
- maintains the iteration order.
-
-2023-02-15 Marek Polacek <polacek@redhat.com>
-
- PR middle-end/106080
- * gimple-ssa-warn-access.cc (is_auto_decl): Remove. Use auto_var_p
- instead.
-
-2023-02-15 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/predicates.md: Refine codes.
- * config/riscv/riscv-protos.h (RVV_VUNDEF): New macro.
- * config/riscv/riscv-v.cc: Refine codes.
- * config/riscv/riscv-vector-builtins-bases.cc (enum ternop_type): New
- enum.
- (class imac): New class.
- (enum widen_ternop_type): New enum.
- (class iwmac): New class.
- (BASE): New class.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vmacc): Ditto.
- (vnmsac): Ditto.
- (vmadd): Ditto.
- (vnmsub): Ditto.
- (vwmacc): Ditto.
- (vwmaccu): Ditto.
- (vwmaccsu): Ditto.
- (vwmaccus): Ditto.
- * config/riscv/riscv-vector-builtins.cc
- (function_builder::apply_predication): Adjust for multiply-add support.
- (function_expander::add_vundef_operand): Refine codes.
- (function_expander::use_ternop_insn): New function.
- (function_expander::use_widen_ternop_insn): Ditto.
- * config/riscv/riscv-vector-builtins.h: New function.
- * config/riscv/vector.md (@pred_mul_<optab><mode>): New pattern.
- (pred_mul_<optab><mode>_undef_merge): Ditto.
- (*pred_<madd_nmsub><mode>): Ditto.
- (*pred_<macc_nmsac><mode>): Ditto.
- (*pred_mul_<optab><mode>): Ditto.
- (@pred_mul_<optab><mode>_scalar): Ditto.
- (*pred_mul_<optab><mode>_undef_merge_scalar): Ditto.
- (*pred_<madd_nmsub><mode>_scalar): Ditto.
- (*pred_<macc_nmsac><mode>_scalar): Ditto.
- (*pred_mul_<optab><mode>_scalar): Ditto.
- (*pred_mul_<optab><mode>_undef_merge_extended_scalar): Ditto.
- (*pred_<madd_nmsub><mode>_extended_scalar): Ditto.
- (*pred_<macc_nmsac><mode>_extended_scalar): Ditto.
- (*pred_mul_<optab><mode>_extended_scalar): Ditto.
- (@pred_widen_mul_plus<su><mode>): Ditto.
- (@pred_widen_mul_plus<su><mode>_scalar): Ditto.
- (@pred_widen_mul_plussu<mode>): Ditto.
- (@pred_widen_mul_plussu<mode>_scalar): Ditto.
- (@pred_widen_mul_plusus<mode>_scalar): Ditto.
-
-2023-02-15 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/predicates.md (vector_mask_operand): Refine the codes.
- (vector_all_trues_mask_operand): New predicate.
- (vector_undef_operand): New predicate.
- (ltge_operator): New predicate.
- (comparison_except_ltge_operator): New predicate.
- (comparison_except_eqge_operator): New predicate.
- (ge_operator): New predicate.
- * config/riscv/riscv-v.cc (has_vi_variant_p): Add compare support.
- * config/riscv/riscv-vector-builtins-bases.cc (class icmp): New class.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vmseq): Ditto.
- (vmsne): Ditto.
- (vmslt): Ditto.
- (vmsgt): Ditto.
- (vmsle): Ditto.
- (vmsge): Ditto.
- (vmsltu): Ditto.
- (vmsgtu): Ditto.
- (vmsleu): Ditto.
- (vmsgeu): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc
- (struct return_mask_def): Adjust for compare support.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_compare_insn): New function.
- * config/riscv/riscv-vector-builtins.h
- (function_expander::add_integer_operand): Ditto.
- * config/riscv/riscv.cc (riscv_print_operand): Add compare support.
- * config/riscv/riscv.md: Add vector min/max attributes.
- * config/riscv/vector-iterators.md (xnor): New iterator.
- * config/riscv/vector.md (@pred_cmp<mode>): New pattern.
- (*pred_cmp<mode>): Ditto.
- (*pred_cmp<mode>_narrow): Ditto.
- (@pred_ltge<mode>): Ditto.
- (*pred_ltge<mode>): Ditto.
- (*pred_ltge<mode>_narrow): Ditto.
- (@pred_cmp<mode>_scalar): Ditto.
- (*pred_cmp<mode>_scalar): Ditto.
- (*pred_cmp<mode>_scalar_narrow): Ditto.
- (@pred_eqne<mode>_scalar): Ditto.
- (*pred_eqne<mode>_scalar): Ditto.
- (*pred_eqne<mode>_scalar_narrow): Ditto.
- (*pred_cmp<mode>_extended_scalar): Ditto.
- (*pred_cmp<mode>_extended_scalar_narrow): Ditto.
- (*pred_eqne<mode>_extended_scalar): Ditto.
- (*pred_eqne<mode>_extended_scalar_narrow): Ditto.
- (@pred_ge<mode>_scalar): Ditto.
- (@pred_<optab><mode>): Ditto.
- (@pred_n<optab><mode>): Ditto.
- (@pred_<optab>n<mode>): Ditto.
- (@pred_not<mode>): Ditto.
-
-2023-02-15 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/108679
- * ipa-sra.cc (push_param_adjustments_for_index): Do not omit
- creation of non-scalar replacements even if IPA-CP knows their
- contents.
-
-2023-02-15 Jakub Jelinek <jakub@redhat.com>
-
- PR target/108787
- PR target/103109
- * config/rs6000/rs6000.md (<u>maddditi4): Change into umaddditi4 only
- expander, change operand 3 to be TImode, emit maddlddi4 and
- umadddi4_highpart{,_le} with its low half and finally add the high
- half to the result.
-
-2023-02-15 Martin Liska <mliska@suse.cz>
-
- * doc/invoke.texi: Document --param=asan-kernel-mem-intrinsic-prefix.
-
-2023-02-15 Richard Biener <rguenther@suse.de>
-
- * sanopt.cc (sanitize_asan_mark_unpoison): Use bitmap
- for with_poison and alias worklist to it.
- (sanitize_asan_mark_poison): Likewise.
-
-2023-02-15 Richard Biener <rguenther@suse.de>
-
- PR target/108738
- * config/i386/i386-features.cc (scalar_chain::add_to_queue):
- Combine bitmap test and set.
- (scalar_chain::add_insn): Likewise.
- (scalar_chain::analyze_register_chain): Remove redundant
- attempt to add to queue and instead strengthen assert.
- Sink common attempts to mark the def dual-mode.
- (scalar_chain::add_to_queue): Remove redundant insn bitmap
- check.
+2024-01-18 Richard Biener <rguenther@suse.de>
-2023-02-15 Richard Biener <rguenther@suse.de>
+ * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
+ operands vector.
- PR target/108738
- * config/i386/i386-features.cc (convert_scalars_to_vector):
- Switch candidates bitmaps to tree view before building the chains.
+2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
-2023-02-15 Hans-Peter Nilsson <hp@axis.com>
+ * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
+ when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
- * reload1.cc (gen_reload): Correct rtx parameter for fatal_insn
- "failure trying to reload" call.
+2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
+ Jin Ma <jinma@linux.alibaba.com>
+ Xianmiao Qu <cooper.qu@linux.alibaba.com>
+ Christoph Müllner <christoph.muellner@vrull.eu>
-2023-02-15 Hans-Peter Nilsson <hp@axis.com>
+ * config/riscv/thead.cc
+ (th_asm_output_opcode): Rewrite some instructions.
- * gdbinit.in (phrs): New command.
- * sel-sched-dump.cc (debug_hard_reg_set): Remove debug-function.
- * ira-color.cc (debug_hard_reg_set): New, calling print_hard_reg_set.
+2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
+ Jin Ma <jinma@linux.alibaba.com>
+ Xianmiao Qu <cooper.qu@linux.alibaba.com>
+ Christoph Müllner <christoph.muellner@vrull.eu>
-2023-02-14 David Faust <david.faust@oracle.com>
+ * config/riscv/riscv.md (none,thv,rvv): New attribute.
+ (no,yes): Add an attribute to disable alternative
+ for xtheadvector or RVV1.0.
+ * config/riscv/vector.md:
+ Disable alternatives that destination register overlaps
+ source register group for xtheadvector.
- PR target/108790
- * config/bpf/constraints.md (q): New memory constraint.
- * config/bpf/bpf.md (zero_extendhidi2): Use it here.
- (zero_extendqidi2): Likewise.
- (zero_extendsidi2): Likewise.
- (*mov<MM:mode>): Likewise.
+2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
+ Jin Ma <jinma@linux.alibaba.com>
+ Xianmiao Qu <cooper.qu@linux.alibaba.com>
+ Christoph Müllner <christoph.muellner@vrull.eu>
-2023-02-14 Andrew Pinski <apinski@marvell.com>
+ * config/riscv/riscv-vector-builtins-bases.cc
+ (class th_loadstore_width): Define new builtin bases.
+ (class th_extract): Define new builtin bases.
+ (BASE): Define new builtin bases.
+ * config/riscv/riscv-vector-builtins-bases.h:
+ Define new builtin class.
+ * config/riscv/riscv-vector-builtins-shapes.cc
+ (struct th_loadstore_width_def): Define new builtin shapes.
+ (struct th_indexed_loadstore_width_def):
+ Define new builtin shapes.
+ (struct th_extract_def): Define new builtin shapes.
+ (SHAPE): Define new builtin shapes.
+ * config/riscv/riscv-vector-builtins-shapes.h:
+ Define new builtin shapes.
+ * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
+ Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
+ * config/riscv/riscv-vector-builtins.h
+ (enum required_ext): Add new XTheadVector member.
+ (struct function_group_info): Likewise.
+ * config/riscv/t-riscv:
+ Add thead-vector-builtins-functions.def
+ * config/riscv/thead-vector.md
+ (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
+ (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
+ (@pred_store_width<vlmem_op_attr><mode>): Likewise.
+ (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
+ (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
+ (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
+ (@pred_th_extract<mode>): Likewise.
+ (*pred_th_extract<mode>): Likewise.
+ * config/riscv/thead-vector-builtins-functions.def: New file.
+
+2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
+ Jin Ma <jinma@linux.alibaba.com>
+ Xianmiao Qu <cooper.qu@linux.alibaba.com>
+ Christoph Müllner <christoph.muellner@vrull.eu>
+
+ * config.gcc: Add files for XTheadVector intrinsics.
+ * config/riscv/autovec.md: Guard XTheadVector.
+ * config/riscv/predicates.md: Disable immediate vl
+ for XTheadVector.
+ * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
+ Add pragma for XTheadVector.
+ * config/riscv/riscv-string.cc (riscv_expand_block_move):
+ Guard XTheadVector.
+ * config/riscv/riscv-v.cc (vls_mode_valid_p):
+ Avoid autovec.
+ * config/riscv/riscv-vector-builtins-bases.cc:
+ Do not normalize vsetvl instructions for XTheadVector.
+ * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
+ New check type function.
+ (build_one): Adjust for XTheadVector.
+ * config/riscv/riscv-vector-switch.def (ENTRY):
+ Disable fractional mode for the XTheadVector extension.
+ (TUPLE_ENTRY): Likewise.
+ * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
+ Guard XTheadVector.
+ (riscv_preferred_simd_mode): Likewsie.
+ (riscv_autovectorize_vector_modes): Likewise.
+ (riscv_vector_mode_supported_any_target_p): Likewise.
+ (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
+ * config/riscv/thead.cc (th_asm_output_opcode):
+ Rewrite vsetvl instructions.
+ * config/riscv/vector.md:
+ Include thead-vector.md and change fractional LMUL
+ into 1 for vbool.
+ * config/riscv/riscv_th_vector.h: New file.
+ * config/riscv/thead-vector.md: New file.
+
+2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
+ Jin Ma <jinma@linux.alibaba.com>
+ Xianmiao Qu <cooper.qu@linux.alibaba.com>
+ Christoph Müllner <christoph.muellner@vrull.eu>
+
+ * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
+ Add new function to add assembler insn code prefix/suffix.
+ (th_asm_output_opcode):
+ Add Thead function to add assembler insn code prefix/suffix.
+ * config/riscv/riscv.cc (riscv_asm_output_opcode):
+ Implement function to add assembler insn code prefix/suffix.
+ * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
+ Add new function to add assembler insn code prefix/suffix.
+ * config/riscv/thead.cc (th_asm_output_opcode):
+ Implement Thead function to add assembler insn code
+ prefix/suffix.
+
+2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
+ Jin Ma <jinma@linux.alibaba.com>
+ Xianmiao Qu <cooper.qu@linux.alibaba.com>
+ Christoph Müllner <christoph.muellner@vrull.eu>
- PR tree-optimization/108355
- PR tree-optimization/96921
- * match.pd: Add pattern for "1 - bool_val".
+ * common/config/riscv/riscv-common.cc
+ (riscv_subset_list::parse): Add new vendor extension.
+ * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
+ Add test marco.
+ * config/riscv/riscv.opt: Add new mask.
-2023-02-14 Richard Biener <rguenther@suse.de>
+2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
- * tree-ssa-sccvn.cc (vn_phi_compute_hash): Key skipping
- basic block index hashing on the availability of ->cclhs.
- (vn_phi_eq): Avoid re-doing sanity checks for CSE but
- rely on ->cclhs availability.
- (vn_phi_lookup): Set ->cclhs only when we are eventually
- going to CSE the PHI.
- (vn_phi_insert): Likewise.
+ * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
+ to be conditional on macosx-version-min.
-2023-02-14 Eric Botcazou <ebotcazou@adacore.com>
+2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
- * gimplify.cc (gimplify_save_expr): Add missing guard.
+ * config/darwin.cc (darwin_objc1_section): Use the correct
+ meta-data version for constant strings.
+ (machopic_select_section): Assert if we fail to handle CFString
+ sections as Obejctive-C meta-data or drectly.
-2023-02-14 Richard Biener <rguenther@suse.de>
+2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
- PR tree-optimization/108782
- * tree-vect-loop.cc (vect_phi_first_order_recurrence_p):
- Make sure we're not vectorizing an inner loop.
+ * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
+ OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
+ OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
+ versions when the object format is Mach-O.
-2023-02-14 Jakub Jelinek <jakub@redhat.com>
+2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
- PR sanitizer/108777
- * params.opt (-param=asan-kernel-mem-intrinsic-prefix=): New param.
- * asan.h (asan_memfn_rtl): Declare.
- * asan.cc (asan_memfn_rtls): New variable.
- (asan_memfn_rtl): New function.
- * builtins.cc (expand_builtin): If
- param_asan_kernel_mem_intrinsic_prefix and function is
- kernel-{,hw}address sanitized, emit calls to
- __{,hw}asan_{memcpy,memmove,memset} rather than
- {memcpy,memmove,memset}. Use sanitize_flags_p (SANITIZE_ADDRESS)
- instead of flag_sanitize & SANITIZE_ADDRESS to check if
- asan_intercepted_p functions shouldn't be expanded inline.
+ PR target/105522
+ * config/darwin.cc (machopic_select_section): Handle C and C++
+ CFStrings.
+ (darwin_rename_builtins): Move this out of the CFString code.
+ (darwin_libc_has_function): Likewise.
+ (darwin_build_constant_cfstring): Create an anonymous var to
+ hold each CFString.
+ * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
+ CFstrings.
-2023-02-14 Richard Sandiford <richard.sandiford@arm.com>
+2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
- PR tree-optimization/96373
- * tree-vect-stmts.cc (vectorizable_operation): Predicate trapping
- operations on the loop mask. Reject partial vectors if this isn't
- possible.
+ PR bootstrap/113445
+ * haifa-sched.cc (dep_list_size): Make global.
+ * sched-deps.cc (find_inc): Use instead of sd_lists_size().
+ * sched-int.h (dep_list_size): Declare.
-2023-02-13 Richard Sandiford <richard.sandiford@arm.com>
+2024-01-18 Martin Jambor <mjambor@suse.cz>
- PR rtl-optimization/108681
- * lra-spills.cc (lra_final_code_change): Extend subreg replacement
- code to handle bare uses and clobbers.
+ PR tree-optimization/110422
+ * tree-sra.cc (scan_function): Disqualify bases of operands of asm
+ gotos.
-2023-02-13 Vladimir N. Makarov <vmakarov@redhat.com>
+2024-01-18 Richard Biener <rguenther@suse.de>
- * ira.cc (ira_update_equiv_info_by_shuffle_insn): Clear equiv
- caller_save_p flag when clearing defined_p flag.
- (setup_reg_equiv): Ditto.
- * lra-constraints.cc (lra_constraints): Ditto.
+ PR tree-optimization/113475
+ * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
+ * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
+ (phi_analyzer::~phi_analyzer): Deallocate and free collected
+ phi_grous.
+ (phi_analyzer::process_phi): Record allocated phi_groups.
-2023-02-13 Uroš Bizjak <ubizjak@gmail.com>
+2024-01-18 Richard Biener <rguenther@suse.de>
- PR target/108516
- * config/i386/predicates.md (extr_register_operand):
- New special predicate.
- * config/i386/i386.md (*extv<mode>): Use extr_register_operand
- as operand 1 predicate.
- (*exzv<mode>): Ditto.
- (*extendqi<SWI24:mode>_ext_1): New insn pattern.
+ * tree-vect-stmts.cc (vectorizable_store): Do not allocate
+ storage for gvec_oprnds elements.
-2023-02-13 Richard Biener <rguenther@suse.de>
+2024-01-18 Richard Biener <rguenther@suse.de>
- PR tree-optimization/28614
- * tree-ssa-sccvn.cc (can_track_predicate_on_edge): Avoid
- walking all edges in most cases.
- (vn_nary_op_insert_pieces_predicated): Avoid repeated
- calls to can_track_predicate_on_edge unless checking is
- enabled.
- (process_bb): Instead call it once here for each edge
- we register possibly multiple predicates on.
+ * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
+ prefer all later exits we can handle.
+ (vect_analyze_loop_form): Free the allocated loop body.
+ Adjust comments.
-2023-02-13 Richard Biener <rguenther@suse.de>
+2024-01-18 Georg-Johann Lay <avr@gjlay.de>
- PR tree-optimization/108691
- * tree-cfg.cc (notice_special_calls): When the CFG is built
- honor gimple_call_ctrl_altering_p.
- * cfgexpand.cc (expand_call_stmt): Clear cfun->calls_setjmp
- temporarily if the call is not control-altering.
- * calls.cc (emit_call_1): Do not add REG_SETJMP if
- cfun->calls_setjmp is not set. Do not alter cfun->calls_setjmp.
+ * config/avr/avr-log.cc: Tabify.
-2023-02-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR target/108102
- * config/s390/s390.cc (s390_bb_fallthru_entry_likely): Remove.
- (struct s390_sched_state): Initialise to zero.
- (s390_sched_variable_issue): For better debuggability also emit
- the current side.
- (s390_sched_init): Unconditionally reset scheduler state.
+ * config/riscv/autovec.md: Support vi variant.
-2023-02-13 Richard Sandiford <richard.sandiford@arm.com>
+2024-01-18 Georg-Johann Lay <avr@gjlay.de>
- * ifcvt.h (noce_if_info::cond_inverted): New field.
- * ifcvt.cc (cond_move_convert_if_block): Swap the then and else
- values when cond_inverted is true.
- (noce_find_if_block): Allow the condition to be inverted when
- handling conditional moves.
+ * config/avr/avr-devices.cc: Tabify.
-2023-02-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+2024-01-18 Georg-Johann Lay <avr@gjlay.de>
- * config/s390/predicates.md (execute_operation): Use
- constrain_operands instead of extract_constrain_insn in order to
- determine wheter there exists a valid alternative.
+ * config/avr/avr-c.cc: Tabify.
-2023-02-13 Claudiu Zissulescu <claziss@gmail.com>
+2024-01-18 Georg-Johann Lay <avr@gjlay.de>
- * common/config/arc/arc-common.cc (arc_option_optimization_table):
- Remove millicode from list.
+ * config/avr/driver-avr.cc: Tabify.
-2023-02-13 Martin Liska <mliska@suse.cz>
+2024-01-18 Georg-Johann Lay <avr@gjlay.de>
- * doc/invoke.texi: Document ira-simple-lra-insn-threshold.
+ * config/avr/gen-avr-mmcu-texi.cc: Tabify.
-2023-02-13 Richard Biener <rguenther@suse.de>
+2024-01-18 Georg-Johann Lay <avr@gjlay.de>
- PR tree-optimization/106722
- * tree-ssa-dce.cc (mark_last_stmt_necessary): Return
- whether we marked a stmt.
- (mark_control_dependent_edges_necessary): When
- mark_last_stmt_necessary didn't mark any stmt make sure
- to mark its control dependent edges.
- (propagate_necessity): Likewise.
+ * config/avr/gen-avr-mmcu-specs.cc: Tabify.
-2023-02-13 Kito Cheng <kito.cheng@sifive.com>
+2024-01-18 Jakub Jelinek <jakub@redhat.com>
- * config/riscv/riscv.h (RISCV_DWARF_VLENB): New.
- (DWARF_FRAME_REGISTERS): New.
- (DWARF_REG_TO_UNWIND_COLUMN): New.
+ * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
+ minline-strcmp, minline-strncmp, minline-strlen,
+ -param=riscv-vector-abi): Remove Bool keywords.
-2023-02-12 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-18 Jakub Jelinek <jakub@redhat.com>
- * doc/sourcebuild.texi: Remove (broken) direct reference to
- "The GNU configure and build system".
+ PR target/113122
+ * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
+ support. Add missing space after , in emitted assembly in some
+ cases. Formatting fixes.
-2023-02-12 Jin Ma <jinma@linux.alibaba.com>
+2024-01-18 Xi Ruoyao <xry111@xry111.site>
- * config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Change
- gen_add3_insn to gen_rtx_SET.
- (riscv_adjust_libcall_cfi_epilogue): Likewise.
+ * config/loongarch/loongarch.md (movsi_internal): Remove
+ constraint z.
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-18 Georg-Johann Lay <avr@gjlay.de>
- * config/riscv/riscv-vector-builtins-bases.cc (class sat_op): New class.
- (class vnclip): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vaadd): Ditto.
- (vasub): Ditto.
- (vaaddu): Ditto.
- (vasubu): Ditto.
- (vsmul): Ditto.
- (vssra): Ditto.
- (vssrl): Ditto.
- (vnclipu): Ditto.
- (vnclip): Ditto.
- * config/riscv/vector-iterators.md (su): Add instruction.
- (aadd): Ditto.
- (vaalu): Ditto.
- * config/riscv/vector.md (@pred_<sat_op><mode>): New pattern.
- (@pred_<sat_op><mode>_scalar): Ditto.
- (*pred_<sat_op><mode>_scalar): Ditto.
- (*pred_<sat_op><mode>_extended_scalar): Ditto.
- (@pred_narrow_clip<v_su><mode>): Ditto.
- (@pred_narrow_clip<v_su><mode>_scalar): Ditto.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/constraints.md (Wbr): Remove unused constraint.
- * config/riscv/predicates.md: Fix move operand predicate.
- * config/riscv/riscv-vector-builtins-bases.cc (class vnshift): New class.
- (class vncvt_x): Ditto.
- (class vmerge): Ditto.
- (class vmv_v): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vsra): Ditto.
- (vsrl): Ditto.
- (vnsrl): Ditto.
- (vnsra): Ditto.
- (vncvt_x): Ditto.
- (vmerge): Ditto.
- (vmv_v): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct narrow_alu_def): Ditto.
- (struct move_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_WEXTI_OPS): New variable.
- (DEF_RVV_WEXTU_OPS): Ditto
- * config/riscv/riscv-vector-builtins.def (x_x_w): Fix type for suffix.
- (v_v): Ditto.
- (v_x): Ditto.
- (x_w): Ditto.
- (x): Ditto.
- * config/riscv/riscv.cc (riscv_print_operand): Refine ASM printting rule.
- * config/riscv/vector-iterators.md (nmsac):New iterator.
- (nmsub): New iterator.
- * config/riscv/vector.md (@pred_merge<mode>): New pattern.
- (@pred_merge<mode>_scalar): New pattern.
- (*pred_merge<mode>_scalar): New pattern.
- (*pred_merge<mode>_extended_scalar): New pattern.
- (@pred_narrow_<optab><mode>): New pattern.
- (@pred_narrow_<optab><mode>_scalar): New pattern.
- (@pred_trunc<mode>): New pattern.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-bases.cc (class vmadc): New class.
- (class vmsbc): Ditto.
- (BASE): Define new class.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vmadc): New define.
- (vmsbc): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct return_mask_def):
- New class.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_exact_insn): Adjust for new support
- * config/riscv/riscv-vector-builtins.h
- (function_base::has_merge_operand_p): New function.
- * config/riscv/vector-iterators.md: New iterator.
- * config/riscv/vector.md (@pred_madc<mode>): New pattern.
- (@pred_msbc<mode>): Ditto.
- (@pred_madc<mode>_scalar): Ditto.
- (@pred_msbc<mode>_scalar): Ditto.
- (*pred_madc<mode>_scalar): Ditto.
- (*pred_madc<mode>_extended_scalar): Ditto.
- (*pred_msbc<mode>_scalar): Ditto.
- (*pred_msbc<mode>_extended_scalar): Ditto.
- (@pred_madc<mode>_overflow): Ditto.
- (@pred_msbc<mode>_overflow): Ditto.
- (@pred_madc<mode>_overflow_scalar): Ditto.
- (@pred_msbc<mode>_overflow_scalar): Ditto.
- (*pred_madc<mode>_overflow_scalar): Ditto.
- (*pred_madc<mode>_overflow_extended_scalar): Ditto.
- (*pred_msbc<mode>_overflow_scalar): Ditto.
- (*pred_msbc<mode>_overflow_extended_scalar): Ditto.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (simm5_p): Add vadc/vsbc support.
- * config/riscv/riscv-v.cc (simm32_p): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc (class vadc): New class.
- (class vsbc): Ditto.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vadc): Ditto.
- (vsbc): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc
- (struct no_mask_policy_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc
- (rvv_arg_type_info::get_base_vector_type): Add vadc/vsbc support.
- (rvv_arg_type_info::get_tree_type): Ditto.
- (function_expander::use_exact_insn): Ditto.
- * config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Ditto.
- (function_base::use_mask_predication_p): New function.
- * config/riscv/vector-iterators.md: New iterator.
- * config/riscv/vector.md (@pred_adc<mode>): New pattern.
- (@pred_sbc<mode>): Ditto.
- (@pred_adc<mode>_scalar): Ditto.
- (@pred_sbc<mode>_scalar): Ditto.
- (*pred_adc<mode>_scalar): Ditto.
- (*pred_adc<mode>_extended_scalar): Ditto.
- (*pred_sbc<mode>_scalar): Ditto.
- (*pred_sbc<mode>_extended_scalar): Ditto.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: use "zero" reg.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-builtins-bases.cc (class widen_binop): New
- class.
- (class vwmulsu): Ditto.
- (class vwcvt): Ditto.
- (BASE): Add integer widening support.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto
- * config/riscv/riscv-vector-builtins-functions.def (vwadd): New class.
- (vwsub): New class.
- (vwmul): New class.
- (vwmulu): New class.
- (vwmulsu): New class.
- (vwaddu): New class.
- (vwsubu): New class.
- (vwcvt_x): New class.
- (vwcvtu_x): New class.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): New
- class.
- (struct widen_alu_def): New class.
- (SHAPE): New class.
- * config/riscv/riscv-vector-builtins-shapes.h: New class.
- * config/riscv/riscv-vector-builtins.cc
- (rvv_arg_type_info::get_base_vector_type): Add integer widening support.
- (rvv_arg_type_info::get_tree_type): Ditto.
- * config/riscv/riscv-vector-builtins.def (x_x_v): Change into "x_v"
- (x_v): Ditto.
- * config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Add integer
- widening support.
- * config/riscv/riscv-vsetvl.cc (change_insn): Fix reg_equal use bug.
- * config/riscv/riscv.h (X0_REGNUM): New constant.
- * config/riscv/vector-iterators.md: New iterators.
- * config/riscv/vector.md
- (@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>): New
- pattern.
- (@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar):
- Ditto.
- (@pred_single_widen_<plus_minus:optab><any_extend:su><mode>): Ditto.
- (@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar):
- Ditto.
- (@pred_widen_mulsu<mode>): Ditto.
- (@pred_widen_mulsu<mode>_scalar): Ditto.
- (@pred_<optab><mode>): Ditto.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc: Add flag for 'V' extension.
- * config/riscv/riscv-vector-builtins-bases.cc (class vmulh): New class.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vmulh): Add vmulh
- API support.
- (vmulhu): Ditto.
- (vmulhsu): Ditto.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_FULL_V_I_OPS):
- New macro.
- (DEF_RVV_FULL_V_U_OPS): Ditto.
- (vint8mf8_t): Ditto.
- (vint8mf4_t): Ditto.
- (vint8mf2_t): Ditto.
- (vint8m1_t): Ditto.
- (vint8m2_t): Ditto.
- (vint8m4_t): Ditto.
- (vint8m8_t): Ditto.
- (vint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint8mf8_t): Ditto.
- (vuint8mf4_t): Ditto.
- (vuint8mf2_t): Ditto.
- (vuint8m1_t): Ditto.
- (vuint8m2_t): Ditto.
- (vuint8m4_t): Ditto.
- (vuint8m8_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint16m2_t): Ditto.
- (vuint16m4_t): Ditto.
- (vuint16m8_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
- (vuint64m1_t): Ditto.
- (vuint64m2_t): Ditto.
- (vuint64m4_t): Ditto.
- (vuint64m8_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FULL_V_I_OPS): Ditto.
- (DEF_RVV_FULL_V_U_OPS): Ditto.
- (check_required_extensions): Add vmulh support.
- (rvv_arg_type_info::get_tree_type): Ditto.
- * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_FULL_V): Ditto.
- (enum rvv_base_type): Ditto.
- * config/riscv/riscv.opt: Add 'V' extension flag.
- * config/riscv/vector-iterators.md (su): New iterator.
- * config/riscv/vector.md (@pred_mulh<v_su><mode>): New pattern.
- (@pred_mulh<v_su><mode>_scalar): Ditto.
- (*pred_mulh<v_su><mode>_scalar): Ditto.
- (*pred_mulh<v_su><mode>_extended_scalar): Ditto.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/iterators.md: Add sign_extend/zero_extend.
- * config/riscv/riscv-vector-builtins-bases.cc (class ext): New class.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Add vsext/vzext support.
- * config/riscv/riscv-vector-builtins-functions.def (vsext): New macro
- define.
- (vzext): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Adjust
- for vsext/vzext support.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_WEXTI_OPS): New
- macro define.
- (DEF_RVV_QEXTI_OPS): Ditto.
- (DEF_RVV_OEXTI_OPS): Ditto.
- (DEF_RVV_WEXTU_OPS): Ditto.
- (DEF_RVV_QEXTU_OPS): Ditto.
- (DEF_RVV_OEXTU_OPS): Ditto.
- (vint16mf4_t): Ditto.
- (vint16mf2_t): Ditto.
- (vint16m1_t): Ditto.
- (vint16m2_t): Ditto.
- (vint16m4_t): Ditto.
- (vint16m8_t): Ditto.
- (vint32mf2_t): Ditto.
- (vint32m1_t): Ditto.
- (vint32m2_t): Ditto.
- (vint32m4_t): Ditto.
- (vint32m8_t): Ditto.
- (vint64m1_t): Ditto.
- (vint64m2_t): Ditto.
- (vint64m4_t): Ditto.
- (vint64m8_t): Ditto.
- (vuint16mf4_t): Ditto.
- (vuint16mf2_t): Ditto.
- (vuint16m1_t): Ditto.
- (vuint16m2_t): Ditto.
- (vuint16m4_t): Ditto.
- (vuint16m8_t): Ditto.
- (vuint32mf2_t): Ditto.
- (vuint32m1_t): Ditto.
- (vuint32m2_t): Ditto.
- (vuint32m4_t): Ditto.
- (vuint32m8_t): Ditto.
- (vuint64m1_t): Ditto.
- (vuint64m2_t): Ditto.
- (vuint64m4_t): Ditto.
- (vuint64m8_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_WEXTI_OPS): Ditto.
- (DEF_RVV_QEXTI_OPS): Ditto.
- (DEF_RVV_OEXTI_OPS): Ditto.
- (DEF_RVV_WEXTU_OPS): Ditto.
- (DEF_RVV_QEXTU_OPS): Ditto.
- (DEF_RVV_OEXTU_OPS): Ditto.
- (rvv_arg_type_info::get_base_vector_type): Add sign_exted/zero_extend
- support.
- (rvv_arg_type_info::get_tree_type): Ditto.
- * config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Ditto.
- * config/riscv/vector-iterators.md (z): New attribute.
- * config/riscv/vector.md (@pred_<optab><mode>_vf2): New pattern.
- (@pred_<optab><mode>_vf4): Ditto.
- (@pred_<optab><mode>_vf8): Ditto.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/iterators.md: Add saturating Addition && Subtraction.
- * config/riscv/riscv-v.cc (has_vi_variant_p): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vsadd): New def.
- (vssub): Ditto.
- (vsaddu): Ditto.
- (vssubu): Ditto.
- * config/riscv/vector-iterators.md (sll.vi): Adjust for Saturating
- support.
- (sll.vv): Ditto.
- (%3,%v4): Ditto.
- (%3,%4): Ditto.
- * config/riscv/vector.md (@pred_<optab><mode>): New pattern.
- (@pred_<optab><mode>_scalar): New pattern.
- (*pred_<optab><mode>_scalar): New pattern.
- (*pred_<optab><mode>_extended_scalar): New pattern.
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/iterators.md: Add neg and not.
- * config/riscv/riscv-vector-builtins-bases.cc (class unop): New class.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vadd): Rename binop
- into alu.
- (vsub): Ditto.
- (vand): Ditto.
- (vor): Ditto.
- (vxor): Ditto.
- (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- (vmin): Ditto.
- (vmax): Ditto.
- (vminu): Ditto.
- (vmaxu): Ditto.
- (vmul): Ditto.
- (vdiv): Ditto.
- (vrem): Ditto.
- (vdivu): Ditto.
- (vremu): Ditto.
- (vrsub): Ditto.
- (vneg): Ditto.
- (vnot): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct binop_def): Ditto.
- (struct alu_def): Ditto.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc: Support unary C/C/++.
- * config/riscv/vector-iterators.md: New iterator.
- * config/riscv/vector.md (@pred_<optab><mode>): New pattern
-
-2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::compute_probabilities): Skip exit block.
-
-2023-02-11 Jakub Jelinek <jakub@redhat.com>
-
- PR ipa/108605
- * ipa-cp.cc (ipa_agg_value_from_jfunc): Return NULL_TREE also if
- item->offset bit position is too large to be representable as
- unsigned int byte position.
-
-2023-02-11 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/extend.texi (Other Builtins): Adjust link to WG14 N965.
-
-2023-02-10 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * ira.cc (update_equiv_regs): Set up ira_reg_equiv for
- valid_combine only when ira_use_lra_p is true.
-
-2023-02-10 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * params.opt (ira-simple-lra-insn-threshold): Add new param.
- * ira.cc (ira): Use the param to switch on simple LRA.
-
-2023-02-10 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/108687
- * gimple-range-cache.cc (ranger_cache::range_on_edge): Revert
- back to RFD_NONE mode for calculations.
- (ranger_cache::propagate_cache): Call the internal edge range API
- with RFD_READ_ONLY instead of changing the external routine.
-
-2023-02-10 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/108520
- * gimple-range-infer.cc (check_assume_func): Invoke
- gimple_range_global directly instead using global_range_query.
- * value-query.cc (get_range_global): Add function context and
- avoid calling nonnull_arg_p if not cfun.
- (gimple_range_global): Add function context pointer.
- * value-query.h (imple_range_global): Add function context.
-
-2023-02-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/constraints.md (Wdm): Adjust constraint.
- (Wbr): New constraint.
- * config/riscv/predicates.md (reg_or_int_operand): New predicate.
- * config/riscv/riscv-protos.h (emit_pred_op): Remove function.
- (emit_vlmax_op): New function.
- (emit_nonvlmax_op): Ditto.
- (simm32_p): Ditto.
- (neg_simm5_p): Ditto.
- (has_vi_variant_p): Ditto.
- * config/riscv/riscv-v.cc (emit_pred_op): Adjust function.
- (emit_vlmax_op): New function.
- (emit_nonvlmax_op): Ditto.
- (expand_const_vector): Adjust function.
- (legitimize_move): Ditto.
- (simm32_p): New function.
- (simm5_p): Ditto.
- (neg_simm5_p): Ditto.
- (has_vi_variant_p): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc (class vrsub): New class.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vmin): Remove
- unsigned cases.
- (vmax): Ditto.
- (vminu): Remove signed cases.
- (vmaxu): Ditto.
- (vdiv): Remove unsigned cases.
- (vrem): Ditto.
- (vdivu): Remove signed cases.
- (vremu): Ditto.
- (vadd): Adjust.
- (vsub): Ditto.
- (vrsub): New class.
- (vand): Adjust.
- (vor): Ditto.
- (vxor): Ditto.
- (vmul): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_U_OPS): New macro.
- * config/riscv/riscv.h: change VL/VTYPE as fixed reg.
- * config/riscv/vector-iterators.md: New iterators.
- * config/riscv/vector.md (@pred_broadcast<mode>): Adjust pattern for vx
- support.
- (@pred_<optab><mode>_scalar): New pattern.
- (@pred_sub<mode>_reverse_scalar): Ditto.
- (*pred_<optab><mode>_scalar): Ditto.
- (*pred_<optab><mode>_extended_scalar): Ditto.
- (*pred_sub<mode>_reverse_scalar): Ditto.
- (*pred_sub<mode>_extended_reverse_scalar): Ditto.
-
-2023-02-10 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108724
- * tree-vect-stmts.cc (vectorizable_operation): Avoid
- using word_mode vectors when vector lowering will
- decompose them to elementwise operations.
-
-2023-02-10 Jakub Jelinek <jakub@redhat.com>
+ * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
+ in the diagnostic, and capitalize the device name.
+ (print_mcu): Generate specs such that:
+ <*check_rodata_in_ram>: New.
+ <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
+ <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
+ <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
- Revert:
- 2023-02-09 Martin Liska <mliska@suse.cz>
-
- PR target/100758
- * doc/extend.texi: Document that the function
- does not work correctly for old VIA processors.
-
-2023-02-10 Andrew Pinski <apinski@marvell.com>
- Andrew Macleod <amacleod@redhat.com>
-
- PR tree-optimization/108684
- * tree-ssa-dce.cc (simple_dce_from_worklist):
- Check all ssa names and not just non-vdef ones
- before accepting the inline-asm.
- Call unlink_stmt_vdef on the statement before
- removing it.
-
-2023-02-09 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * ira.h (struct ira_reg_equiv_s): Add new field caller_save_p.
- * ira.cc (validate_equiv_mem): Check memref address variance.
- (no_equiv): Clear caller_save_p flag.
- (update_equiv_regs): Define caller save equivalence for
- valid_combine.
- (setup_reg_equiv): Clear defined_p flag for caller save equivalence.
- * lra-constraints.cc (lra_copy_reg_equiv): Add new arg
- call_save_p. Use caller save equivalence depending on the arg.
- (split_reg): Adjust the call.
-
-2023-02-09 Jakub Jelinek <jakub@redhat.com>
-
- PR target/100758
- * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Formatting fixes.
- (cpu_indicator_init): Call get_available_features for all CPUs with
- max_level >= 1, rather than just Intel, AMD or Zhaoxin. Formatting
- fixes.
+2024-01-18 Jakub Jelinek <jakub@redhat.com>
-2023-02-09 Jakub Jelinek <jakub@redhat.com>
+ PR other/113399
+ * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
+ Common and Optimization.
- PR tree-optimization/108688
- * match.pd (bit_field_ref [bit_insert]): Simplify BIT_FIELD_REF
- of BIT_INSERT_EXPR extracting exactly all inserted bits even
- when without mode precision. Formatting fixes.
+2024-01-18 Richard Biener <rguenther@suse.de>
-2023-02-09 Andrew Pinski <apinski@marvell.com>
+ PR tree-optimization/113431
+ * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
+ When there is an invariant load we might not preserve
+ scalar order.
- PR tree-optimization/108688
- * match.pd (bit_field_ref [bit_insert]): Avoid generating
- BIT_FIELD_REFs of non-mode-precision integral operands.
+2024-01-18 Richard Biener <rguenther@suse.de>
-2023-02-09 Martin Liska <mliska@suse.cz>
+ PR tree-optimization/113374
+ * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
+ * tree-vect-loop.cc (move_early_exit_stmts): Update
+ virtual LC PHIs.
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Refactor. Preserve virtual LC PHIs on all exits.
- PR target/100758
- * doc/extend.texi: Document that the function
- does not work correctly for old VIA processors.
+2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
-2023-02-09 Andreas Schwab <schwab@suse.de>
+ * config/loongarch/loongarch.cc (loongarch_split_symbol):
+ Assign the '/u' attribute to the mem.
- * lto-wrapper.cc (merge_and_complain): Handle
- -funwind-tables and -fasynchronous-unwind-tables.
- (append_compiler_options): Likewise.
+2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
-2023-02-09 Richard Biener <rguenther@suse.de>
+ PR middle-end/110847
+ * doc/invoke.texi (Option Summary): Document negative forms of
+ -Wtsan and -Wxor-used-as-pow.
+ (Warning Options): Likewise.
- PR tree-optimization/26854
- * tree-into-ssa.cc (update_ssa): Turn blocks_to_update to tree
- view around insert_updated_phi_nodes_for.
- * tree-ssa-alias.cc (maybe_skip_until): Allocate visited bitmap
- in tree view.
- (walk_aliased_vdefs_1): Likewise.
+2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-02-08 Gerald Pfeifer <gerald@pfeifer.com>
+ PR target/113429
+ * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
- * doc/include/gpl_v3.texi: Change fsf.org to www.fsf.org.
+2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
-2023-02-08 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+ * doc/extend.texi (Common Function Attributes): Re-alphabetize
+ the table.
+ (Common Variable Attributes): Likewise.
+ (Common Type Attributes): Likewise.
- PR target/108505
- * config.gcc (tm_mlib_file): Define new variable.
+2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
-2023-02-08 Jakub Jelinek <jakub@redhat.com>
+ PR middle-end/111659
+ * doc/extend.texi (Common Variable Attributes): Fix long lines
+ in documentation of strict_flex_array + other minor copy-editing.
+ Add a cross-reference to -Wstrict-flex-arrays.
+ * doc/invoke.texi (Option Summary): Fix whitespace in tables
+ before -fstrict-flex-arrays and -Wstrict-flex-arrays.
+ (C Dialect Options): Combine the docs for the two
+ -fstrict-flex-arrays forms into a single entry. Note this option
+ is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
+ (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
+ Minor copy-editing. Add cross references to the strict_flex_array
+ attribute and -fstrict-flex-arrays option. Add note that this
+ option depends on -ftree-vrp.
- PR tree-optimization/108692
- * tree-vect-patterns.cc (vect_widened_op_tree): If rhs_code is
- widened_code which is different from code, don't call
- vect_look_through_possible_promotion but instead just check op is
- SSA_NAME with integral type for which vect_is_simple_use is true
- and call set_op on this_unprom.
+2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
-2023-02-08 Andrea Corallo <andrea.corallo@arm.com>
+ PR target/113221
+ * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
+ only allow REG operands instead of allowing all.
- * config/aarch64/aarch64-protos.h (aarch_ra_sign_key): Remove
- declaration.
- * config/aarch64/aarch64.cc (aarch_ra_sign_key): Remove
- definition.
- * config/aarch64/aarch64.opt (aarch64_ra_sign_key): Rename
- to 'aarch_ra_sign_key'.
- * config/arm/aarch-common.cc (aarch_ra_sign_key): Remove
- declaration.
- * config/arm/arm-protos.h (aarch_ra_sign_key): Likewise.
- * config/arm/arm.cc (enum aarch_key_type): Remove definition.
- * config/arm/arm.opt: Define.
+2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
-2023-02-08 Richard Sandiford <richard.sandiford@arm.com>
+ * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
+ Remove redundant checks in else condition for readablity.
+ (earliest_fuse_vsetvl_info) Print iteration count in debug
+ prints.
+ (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
+ dump details in certain cases.
- PR tree-optimization/108316
- * tree-vect-stmts.cc (get_load_store_type): When using
- internal functions for gather/scatter, make sure that the type
- of the offset argument is consistent with the offset vector type.
+2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
-2023-02-08 Vladimir N. Makarov <vmakarov@redhat.com>
+ * config/riscv/riscv.opt: New -param=vsetvl-strategy.
+ * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
+ * config/riscv/riscv-vsetvl.cc
+ (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
+ (pass_vsetvl::execute): Use vsetvl_strategy.
- Revert:
- 2023-02-07 Vladimir N. Makarov <vmakarov@redhat.com>
+2024-01-17 Jan Hubicka <jh@suse.cz>
- * ira.h (struct ira_reg_equiv_s): Add new field caller_save_p.
- * ira.cc (validate_equiv_mem): Check memref address variance.
- (update_equiv_regs): Define caller save equivalence for
- valid_combine.
- (setup_reg_equiv): Clear defined_p flag for caller save equivalence.
- * lra-constraints.cc (lra_copy_reg_equiv): Add new arg
- call_save_p. Use caller save equivalence depending on the arg.
- (split_reg): Adjust the call.
+ * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
+ accidental hack reseting offset.
-2023-02-08 Jakub Jelinek <jakub@redhat.com>
+2024-01-17 Jan Hubicka <jh@suse.cz>
- * tree.def (SAD_EXPR): Remove outdated comment about missing
- WIDEN_MINUS_EXPR.
+ * config/i386/i386-options.cc (ix86_option_override_internal): Fix
+ handling of X86_TUNE_AVOID_512FMA_CHAINS.
-2023-02-07 Marek Polacek <polacek@redhat.com>
+2024-01-17 Jan Hubicka <jh@suse.cz>
+ Jakub Jelinek <jakub@redhat.com>
- * doc/invoke.texi: Update -fchar8_t documentation.
+ PR tree-optimization/110852
+ * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
+ binary operations
+ (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
+ PRED_COMBINED_VALUE_PREDICTIONS_PHI
+ * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
+ (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
-2023-02-07 Vladimir N. Makarov <vmakarov@redhat.com>
+2024-01-17 Jakub Jelinek <jakub@redhat.com>
- * ira.h (struct ira_reg_equiv_s): Add new field caller_save_p.
- * ira.cc (validate_equiv_mem): Check memref address variance.
- (update_equiv_regs): Define caller save equivalence for
- valid_combine.
- (setup_reg_equiv): Clear defined_p flag for caller save equivalence.
- * lra-constraints.cc (lra_copy_reg_equiv): Add new arg
- call_save_p. Use caller save equivalence depending on the arg.
- (split_reg): Adjust the call.
+ PR tree-optimization/113421
+ * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
+ comment.
+ (bitint_dom_walker::before_dom_children): Add g temporary to simplify
+ formatting. Start at vop rather than cvop even if stmt is a store
+ and needs_operand_addr.
-2023-02-07 Richard Biener <rguenther@suse.de>
+2024-01-17 Jakub Jelinek <jakub@redhat.com>
- PR tree-optimization/26854
- * gimple-fold.cc (has_use_on_stmt): Look at stmt operands
- instead of immediate uses.
-
-2023-02-07 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/106923
- * ipa-split.cc (execute_split_functions): Don't split returns_twice
- functions.
+ PR middle-end/113410
+ * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
+ If access_nelts is integral with larger precision than sizetype,
+ fold_convert it to sizetype.
-2023-02-07 Jakub Jelinek <jakub@redhat.com>
+2024-01-17 Jakub Jelinek <jakub@redhat.com>
- PR tree-optimization/106433
- * cgraph.cc (set_const_flag_1): Recurse on simd clones too.
- (cgraph_node::set_pure_flag): Call set_pure_flag_1 on simd clones too.
+ PR tree-optimization/113408
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
+ VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
+ to handle_cast.
-2023-02-07 Jan Hubicka <jh@suse.cz>
+2024-01-17 Jakub Jelinek <jakub@redhat.com>
- * config/i386/x86-tune.def (X86_TUNE_AVX256_OPTIMAL): Turn off
- for znver4.
-
-2023-02-06 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/mkoffload.cc (gcn_stack_size): New global variable.
- (process_asm): Create a constructor for GCN_STACK_SIZE.
- (main): Parse the -mstack-size option.
-
-2023-02-06 Alex Coplan <alex.coplan@arm.com>
-
- PR target/104921
- * config/aarch64/aarch64-simd.md (aarch64_bfmlal<bt>_lane<q>v4sf):
- Use correct constraint for operand 3.
-
-2023-02-06 Martin Jambor <mjambor@suse.cz>
-
- * ipa-sra.cc (adjust_parameter_descriptions): Fix a typo in a dump.
-
-2023-02-06 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (bytepick_w_ashift_amount):
- New define_int_iterator.
- (bytepick_d_ashift_amount): Likewise.
- (bytepick_imm): New define_int_attr.
- (bytepick_w_lshiftrt_amount): Likewise.
- (bytepick_d_lshiftrt_amount): Likewise.
- (bytepick_w_<bytepick_imm>): New define_insn template.
- (bytepick_w_<bytepick_imm>_extend): Likewise.
- (bytepick_d_<bytepick_imm>): Likewise.
- (bytepick_w): Remove unused define_insn.
- (bytepick_d): Likewise.
- (UNSPEC_BYTEPICK_W): Remove unused unspec.
- (UNSPEC_BYTEPICK_D): Likewise.
- * config/loongarch/predicates.md (const_0_to_3_operand):
- Remove unused define_predicate.
- (const_0_to_7_operand): Likewise.
-
-2023-02-06 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/108655
- * ubsan.cc (sanitize_unreachable_fn): For -funreachable-traps
- or -fsanitize=unreachable -fsanitize-trap=unreachable return
- BUILT_IN_UNREACHABLE_TRAP decl rather than BUILT_IN_TRAP.
-
-2023-02-05 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/install.texi (Specific): Remove PW32.
-
-2023-02-03 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/108647
- * range-op.cc (operator_equal::op1_range,
- operator_not_equal::op1_range): Don't test op2 bound
- equality if op2.undefined_p (), instead set_varying.
- (operator_lt::op1_range, operator_le::op1_range,
- operator_gt::op1_range, operator_ge::op1_range): Return false if
- op2.undefined_p ().
- (operator_lt::op2_range, operator_le::op2_range,
- operator_gt::op2_range, operator_ge::op2_range): Return false if
- op1.undefined_p ().
-
-2023-02-03 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/108639
- * value-range.cc (irange::legacy_equal_p): Compare nonzero bits as
- widest_int.
- (irange::operator==): Same.
-
-2023-02-03 Aldy Hernandez <aldyh@redhat.com>
-
- PR tree-optimization/108647
- * range-op-float.cc (foperator_lt::op1_range): Handle undefined ranges.
- (foperator_lt::op2_range): Same.
- (foperator_le::op1_range): Same.
- (foperator_le::op2_range): Same.
- (foperator_gt::op1_range): Same.
- (foperator_gt::op2_range): Same.
- (foperator_ge::op1_range): Same.
- (foperator_ge::op2_range): Same.
- (foperator_unordered_lt::op1_range): Same.
- (foperator_unordered_lt::op2_range): Same.
- (foperator_unordered_le::op1_range): Same.
- (foperator_unordered_le::op2_range): Same.
- (foperator_unordered_gt::op1_range): Same.
- (foperator_unordered_gt::op2_range): Same.
- (foperator_unordered_ge::op1_range): Same.
- (foperator_unordered_ge::op2_range): Same.
-
-2023-02-03 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/107570
- * tree-vrp.cc (remove_and_update_globals): Reset SCEV.
-
-2023-02-03 Gaius Mulley <gaiusmod2@gmail.com>
-
- * doc/gm2.texi (Internals): Remove from menu.
- (Using): Comment out ifnohtml conditional.
- (Documentation): Use gcc url.
- (License): Node simplified.
- (Copying): New node. Include gpl_v3_without_node.
- (Contributing): Node simplified.
- (Internals): Commented out.
- (Libraries): Node simplified.
- (Indices): Ditto.
- (Contents): Ditto.
- (Functions): Ditto.
-
-2023-02-03 Christophe Lyon <christophe.lyon@arm.com>
-
- * config/arm/mve.md (mve_vabavq_p_<supf><mode>): Add length
- attribute.
- (mve_vqshluq_m_n_s<mode>): Likewise.
- (mve_vshlq_m_<supf><mode>): Likewise.
- (mve_vsriq_m_n_<supf><mode>): Likewise.
- (mve_vsubq_m_<supf><mode>): Likewise.
-
-2023-02-03 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/108384
- * ipa-sra.cc (push_param_adjustments_for_index): Remove a size check
- when comparing to an IPA-CP value.
- (dump_list_of_param_indices): New function.
- (adjust_parameter_descriptions): Check for mismatching IPA-CP values.
- Dump removed candidates using dump_list_of_param_indices.
- * ipa-param-manipulation.cc
- (ipa_param_body_adjustments::modify_expression): Add assert checking
- sizes of a VIEW_CONVERT_EXPR will match.
- (ipa_param_body_adjustments::modify_assignment): Likewise.
-
-2023-02-03 Monk Chiang <monk.chiang@sifive.com>
-
- * config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class.
- * config/riscv/riscv.cc: Ditto.
-
-2023-02-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md (sll.vi): Fix constraint bug.
- (sll.vv): Ditto.
- (%3,%4): Ditto.
- (%3,%v4): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-02-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/predicates.md (pmode_reg_or_uimm5_operand): New predicate.
- * config/riscv/riscv-vector-builtins-bases.cc: New class.
- * config/riscv/riscv-vector-builtins-functions.def (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- * config/riscv/riscv-vector-builtins.cc: Ditto.
- * config/riscv/vector.md (@pred_<optab><mode>_scalar): New pattern.
-
-2023-02-02 Iain Sandoe <iain@sandoe.co.uk>
-
- * toplev.cc (toplev::main): Only print the version information header
- from toplevel main().
-
-2023-02-02 Paul-Antoine Arras <pa@codesourcery.com>
-
- * config/gcn/gcn-valu.md (cond_<expander><mode>): Add
- cond_{ashl|ashr|lshr}
-
-2023-02-02 Richard Sandiford <richard.sandiford@arm.com>
-
- PR rtl-optimization/108086
- * rtl-ssa/insns.h (insn_info): Make m_num_defs a full unsigned int.
- Adjust size-related commentary accordingly.
-
-2023-02-02 Richard Sandiford <richard.sandiford@arm.com>
-
- PR rtl-optimization/108508
- * rtl-ssa/accesses.cc (function_info::split_clobber_group): When
- the splay tree search gives the first clobber in the second group,
- make sure that the root of the first clobber group is updated
- correctly. Enter the new clobber group into the definition splay
- tree.
+ PR middle-end/113406
+ * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
+ regardless of whether is_gimple_reg_type (restype) or not.
-2023-02-02 Jin Ma <jinma@linux.alibaba.com>
-
- * common/config/riscv/riscv-common.cc (riscv_compute_multilib):
- Fix finding best match score.
-
-2023-02-02 Jakub Jelinek <jakub@redhat.com>
-
- PR debug/106746
- PR rtl-optimization/108463
- PR target/108484
- * cselib.cc (cselib_current_insn): Move declaration earlier.
- (cselib_hasher::equal): For debug only locs, temporarily override
- cselib_current_insn to their l->setting_insn for the
- rtx_equal_for_cselib_1 call, so that unsuccessful comparisons don't
- promote some debug locs.
- * sched-deps.cc (sched_analyze_2) <case MEM>: For MEMs in DEBUG_INSNs
- when using cselib call cselib_lookup_from_insn on the address but
- don't substitute it.
-
-2023-02-02 Richard Biener <rguenther@suse.de>
-
- PR middle-end/108625
- * genmatch.cc (expr::gen_transform): Also disallow resimplification
- from pushing to lseq with force_leaf.
- (dt_simplify::gen_1): Likewise.
-
-2023-02-02 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-run.cc: Include libgomp-gcn.h.
- (struct kernargs): Replace the common content with kernargs_abi.
- (struct heap): Delete.
- (main): Read GCN_STACK_SIZE envvar.
- Allocate space for the device stacks.
- Write the new kernargs fields.
- * config/gcn/gcn.cc (gcn_option_override): Remove stack_size_opt.
- (default_requested_args): Remove PRIVATE_SEGMENT_BUFFER_ARG and
- PRIVATE_SEGMENT_WAVE_OFFSET_ARG.
- (gcn_addr_space_convert): Mask the QUEUE_PTR_ARG content.
- (gcn_expand_prologue): Move the TARGET_PACKED_WORK_ITEMS to the top.
- Set up the stacks from the values in the kernargs, not private.
- (gcn_expand_builtin_1): Match the stack configuration in the prologue.
- (gcn_hsa_declare_function_name): Turn off the private segment.
- (gcn_conditional_register_usage): Ensure QUEUE_PTR is fixed.
- * config/gcn/gcn.h (FIXED_REGISTERS): Fix the QUEUE_PTR register.
- * config/gcn/gcn.opt (mstack-size): Change the description.
-
-2023-02-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR target/108443
- * config/arm/arm.h (VALID_MVE_PRED_MODE): Add V2QI.
- * config/arm/arm.cc (thumb2_legitimate_address_p): Use HImode for
- addressing MVE predicate modes.
- (mve_bool_vec_to_const): Change to represent correct MVE predicate
- format.
- (arm_hard_regno_mode_ok): Use VALID_MVE_PRED_MODE instead of checking
- modes.
- (arm_vector_mode_supported_p): Likewise.
- (arm_mode_to_pred_mode): Add V2QI.
- * config/arm/arm-builtins.cc (UNOP_PRED_UNONE_QUALIFIERS): New
- qualifier.
- (UNOP_PRED_PRED_QUALIFIERS): New qualifier
- (BINOP_PRED_UNONE_PRED_QUALIFIERS): New qualifier.
- (v2qi_UP): New macro.
- (v4bi_UP): New macro.
- (v8bi_UP): New macro.
- (v16bi_UP): New macro.
- (arm_expand_builtin_args): Make it able to expand the new predicate
- modes.
- * config/arm/arm-modes.def (V2QI): New mode.
- * config/arm/arm-simd-builtin-types.def (Pred1x16_t, Pred2x8_t
- Pred4x4_t): Remove unused predicate builtin types.
- * config/arm/arm_mve.h (__arm_vctp16q, __arm_vctp32q, __arm_vctp64q,
- __arm_vctp8q, __arm_vpnot, __arm_vctp8q_m, __arm_vctp64q_m,
- __arm_vctp32q_m, __arm_vctp16q_m): Use predicate modes.
- * config/arm/arm_mve_builtins.def (vctp16q, vctp32q, vctp64q, vctp8q,
- vpnot, vctp8q_m, vctp16q_m, vctp32q_m, vctp64q_m): Likewise.
- * config/arm/constraints.md (DB): Check for VALID_MVE_PRED_MODE instead
- of MODE_VECTOR_BOOL.
- * config/arm/iterators.md (MVE_7, MVE_7_HI): Add V2QI
- (MVE_VPRED): Likewise.
- (MVE_vpred): Add V2QI and map upper case predicate modes to lower case.
- (MVE_vctp): New mode attribute.
- (mode1): Remove.
- (VCTPQ): Remove.
- (VCTPQ_M): Remove.
- * config/arm/mve.md (mve_vctp<mode1>qhi): Rename this...
- (mve_vctp<MVE_vctp>q<MVE_vpred>): ... to this. And use new mode
- attributes.
- (mve_vpnothi): Rename this...
- (mve_vpnotv16bi): ... to this.
- (mve_vctp<mode1>q_mhi): Rename this...
- (mve_vctp<MVE_vctp>q_m<MVE_vpred>):... to this.
- (mve_vldrdq_gather_base_z_<supf>v2di,
- mve_vldrdq_gather_offset_z_<supf>v2di,
- mve_vldrdq_gather_shifted_offset_z_<supf>v2di,
- mve_vstrdq_scatter_base_p_<supf>v2di,
- mve_vstrdq_scatter_offset_p_<supf>v2di,
- mve_vstrdq_scatter_offset_p_<supf>v2di_insn,
- mve_vstrdq_scatter_shifted_offset_p_<supf>v2di,
- mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn,
- mve_vstrdq_scatter_base_wb_p_<supf>v2di,
- mve_vldrdq_gather_base_wb_z_<supf>v2di,
- mve_vldrdq_gather_base_nowb_z_<supf>v2di,
- mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Use V2QI insead of HI for
- predicates.
- * config/arm/unspecs.md (VCTP8Q, VCTP16Q, VCTP32Q, VCTP64Q): Replace
- these...
- (VCTP): ... with this.
- (VCTP8Q_M, VCTP16Q_M, VCTP32Q_M, VCTP64Q_M): Replace these...
- (VCTP_M): ... with this.
- * config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Use
- VALID_MVE_PRED_MODE instead of checking for MODE_VECTOR_BOOL class.
-
-2023-02-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR target/107674
- * config/arm/arm.cc (arm_hard_regno_mode_ok): Use new MACRO.
- (arm_modes_tieable_p): Make MVE predicate modes tieable.
- * config/arm/arm.h (VALID_MVE_PRED_MODE): New define.
- * simplify-rtx.cc (simplify_context::simplify_subreg): Teach
- simplify_subreg to simplify subregs where the outermode is not scalar.
-
-2023-02-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR target/107674
- * config/arm/arm-builtins.cc (arm_simd_builtin_type): Rewrite to use
- new qualifiers parameter and use unsigned short type for MVE predicate.
- (arm_init_builtin): Call arm_simd_builtin_type with qualifiers
- parameter.
- (arm_init_crypto_builtins): Likewise.
-
-2023-02-02 Jakub Jelinek <jakub@redhat.com>
-
- PR ipa/107300
- * builtins.def (BUILT_IN_UNREACHABLE_TRAP): New builtin.
- * internal-fn.def (TRAP): Remove.
- * internal-fn.cc (expand_TRAP): Remove.
- * tree.cc (build_common_builtin_nodes): Define
- BUILT_IN_UNREACHABLE_TRAP if not yet defined.
- (builtin_decl_unreachable): Use BUILT_IN_UNREACHABLE_TRAP
- instead of BUILT_IN_TRAP.
- * gimple.cc (gimple_build_builtin_unreachable): Remove
- emitting internal function for BUILT_IN_TRAP.
- * asan.cc (maybe_instrument_call): Handle BUILT_IN_UNREACHABLE_TRAP.
- * cgraph.cc (cgraph_edge::verify_corresponds_to_fndecl): Handle
- BUILT_IN_UNREACHABLE_TRAP instead of BUILT_IN_TRAP.
- * ipa-devirt.cc (possible_polymorphic_call_target_p): Handle
- BUILT_IN_UNREACHABLE_TRAP.
- * builtins.cc (expand_builtin, is_inexpensive_builtin): Likewise.
- * tree-cfg.cc (verify_gimple_call,
- pass_warn_function_return::execute): Likewise.
- * attribs.cc (decl_attributes): Don't report exclusions on
- BUILT_IN_UNREACHABLE_TRAP either.
-
-2023-02-02 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/108601
- * tree-vectorizer.h (vect_can_peel_nonlinear_iv_p): Removed.
- * tree-vect-loop.cc
- (vectorizable_nonlinear_induction): Remove
- vect_can_peel_nonlinear_iv_p.
- (vect_can_peel_nonlinear_iv_p): Don't peel
- nonlinear iv(mult or shift) for epilog when vf is not
- constant and moved the defination to ..
- * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
- .. Here.
+2024-01-17 Jakub Jelinek <jakub@redhat.com>
-2023-02-02 Jakub Jelinek <jakub@redhat.com>
+ * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
+ funcions -> functions, and use were instead of was.
+ * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
+ and guaranteee -> guarantee.
+ * attribs.h (struct attr_access): Fix comment typo funcion -> function.
- PR middle-end/108435
- * tree-nested.cc (convert_nonlocal_omp_clauses)
- <case OMP_CLAUSE_LASTPRIVATE>: If info->new_local_var_chain and *seq
- is not a GIMPLE_BIND, wrap the sequence into a new GIMPLE_BIND
- before calling declare_vars.
- (convert_nonlocal_omp_clauses) <case OMP_CLAUSE_LINEAR>: Merge
- with the OMP_CLAUSE_LASTPRIVATE handling except for whether
- seq is initialized to &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (clause)
- or &OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause).
+2024-01-17 Jakub Jelinek <jakub@redhat.com>
-2023-02-01 Tamar Christina <tamar.christina@arm.com>
+ PR middle-end/113409
+ * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
+ INTEGER_TYPE.
+ (omp_extract_for_data): Use build_bitint_type rather than
+ build_nonstandard_integer_type if either iter_type or loop->v type
+ is BITINT_TYPE.
+ * omp-expand.cc (expand_omp_for_generic,
+ expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
+ BITINT_TYPE like INTEGER_TYPE.
- * common/config/aarch64/aarch64-common.cc
- (struct aarch64_option_extension): Add native_detect and document struct
- a bit more.
- (all_extensions): Set new field native_detect.
- * config/aarch64/aarch64.cc (struct aarch64_option_extension): Delete
- unused struct.
+2024-01-17 Richard Biener <rguenther@suse.de>
-2023-02-01 Martin Liska <mliska@suse.cz>
-
- * ipa-devirt.cc (odr_types_equivalent_p): Respect *warned
- value if set.
-
-2023-02-01 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/108356
- * gimple-range-cache.cc (ranger_cache::range_on_edge): Always
- do a search of the DOM tree for a range.
-
-2023-02-01 Martin Liska <mliska@suse.cz>
-
- PR ipa/108509
- * cgraphunit.cc (walk_polymorphic_call_targets): Insert
- ony non-null values.
- * ipa.cc (walk_polymorphic_call_targets): Likewise.
-
-2023-02-01 Martin Liska <mliska@suse.cz>
-
- PR driver/108572
- * gcc.cc (LINK_COMPRESS_DEBUG_SPEC): Report error only for
- -gz=zstd.
-
-2023-02-01 Jakub Jelinek <jakub@redhat.com>
-
- PR debug/108573
- * ree.cc (combine_reaching_defs): Don't return false for paradoxical
- subregs in DEBUG_INSNs.
-
-2023-02-01 Richard Sandiford <richard.sandiford@arm.com>
-
- * compare-elim.cc (find_flags_uses_in_insn): Guard use of SET_SRC.
-
-2023-02-01 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config/s390/s390.cc (s390_restore_gpr_p): New function.
- (s390_preserve_gpr_arg_in_range_p): New function.
- (s390_preserve_gpr_arg_p): New function.
- (s390_preserve_fpr_arg_p): New function.
- (s390_register_info_stdarg_fpr): Rename to ...
- (s390_register_info_arg_fpr): ... this. Add -mpreserve-args handling.
- (s390_register_info_stdarg_gpr): Rename to ...
- (s390_register_info_arg_gpr): ... this. Add -mpreserve-args handling.
- (s390_register_info): Use the renamed functions above.
- (s390_optimize_register_info): Likewise.
- (save_fpr): Generate CFI for -mpreserve-args.
- (save_gprs): Generate CFI for -mpreserve-args. Drop return value.
- (s390_emit_prologue): Adjust to changed calling convention of save_gprs.
- (s390_optimize_prologue): Likewise.
- * config/s390/s390.opt: New option -mpreserve-args
-
-2023-02-01 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config/s390/s390.cc (save_gprs): Use gen_frame_mem.
- (restore_gprs): Likewise.
- (s390_emit_stack_tie): Make the stack_tie to be dependent on the
- frame pointer if a frame-pointer is used.
- (s390_emit_prologue): Emit stack_tie when frame-pointer is needed.
- * config/s390/s390.md (stack_tie): Add a register operand and
- rename to ...
- (@stack_tie<mode>): ... this.
-
-2023-02-01 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * dwarf2cfi.cc (dwarf2out_frame_debug_cfa_restore): Add
- EMIT_CFI parameter.
- (dwarf2out_frame_debug): Add case for REG_CFA_NORESTORE.
- * reg-notes.def (REG_CFA_NOTE): New reg note definition.
-
-2023-02-01 Richard Biener <rguenther@suse.de>
-
- PR middle-end/108500
- * dominance.cc (assign_dfs_numbers): Replace recursive DFS
- with tree traversal algorithm.
-
-2023-02-01 Jason Merrill <jason@redhat.com>
-
- * doc/invoke.texi: Document -Wno-changes-meaning.
-
-2023-02-01 David Malcolm <dmalcolm@redhat.com>
-
- * doc/invoke.texi (Static Analyzer Options): Add notes about
- limitations of -fanalyzer.
-
-2023-01-31 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/constraints.md (vj): New.
- (vk): Ditto
- * config/riscv/iterators.md: Add more opcode.
- * config/riscv/predicates.md (vector_arith_operand): New.
- (vector_neg_arith_operand): New.
- (vector_shift_operand): New.
- * config/riscv/riscv-vector-builtins-bases.cc (class binop): New.
- * config/riscv/riscv-vector-builtins-bases.h: (vadd): New.
- (vsub): Ditto.
- (vand): Ditto.
- (vor): Ditto.
- (vxor): Ditto.
- (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- (vmin): Ditto.
- (vmax): Ditto.
- (vminu): Ditto.
- (vmaxu): Ditto.
- (vmul): Ditto.
- (vdiv): Ditto.
- (vrem): Ditto.
- (vdivu): Ditto.
- (vremu): Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vadd): New.
- (vsub): Ditto.
- (vand): Ditto.
- (vor): Ditto.
- (vxor): Ditto.
- (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- (vmin): Ditto.
- (vmax): Ditto.
- (vminu): Ditto.
- (vmaxu): Ditto.
- (vmul): Ditto.
- (vdiv): Ditto.
- (vrem): Ditto.
- (vdivu): Ditto.
- (vremu): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct binop_def): New.
- * config/riscv/riscv-vector-builtins-shapes.h (binop): New.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New.
- (DEF_RVV_U_OPS): New.
- (rvv_arg_type_info::get_base_vector_type): Handle
- RVV_BASE_shift_vector.
- (rvv_arg_type_info::get_tree_type): Ditto.
- * config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Add
- RVV_BASE_shift_vector.
- * config/riscv/riscv.cc (riscv_print_operand): Handle 'V'.
- * config/riscv/vector-iterators.md: Handle more opcode.
- * config/riscv/vector.md (@pred_<optab><mode>): New.
-
-2023-01-31 Philipp Tomsich <philipp.tomsich@vrull.eu>
-
- PR target/108589
- * config/aarch64/aarch64.cc (aarch_macro_fusion_pair_p): Check
- REG_P on SET_DEST.
-
-2023-01-31 Richard Sandiford <richard.sandiford@arm.com>
-
- PR tree-optimization/108608
- * tree-vect-loop.cc (vect_transform_reduction): Handle single
- def-use cycles that involve function calls rather than tree codes.
-
-2023-01-31 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/108385
- * gimple-range-gori.cc (gori_compute::compute_operand_range):
- Allow VARYING computations to continue if there is a relation.
- * range-op.cc (pointer_plus_operator::op2_range): New.
-
-2023-01-31 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/108359
- * range-op.cc (range_operator::wi_fold_in_parts_equiv): New.
- (range_operator::fold_range): If op1 is equivalent to op2 then
- invoke new fold_in_parts_equiv to operate on sub-components.
- * range-op.h (wi_fold_in_parts_equiv): New prototype.
-
-2023-01-31 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-gori.cc (gori_compute::compute_operand_range): Do
- not abort calculations if there is a valid relation available.
- (gori_compute::refine_using_relation): Pass correct relation trio.
- (gori_compute::compute_operand1_range): Create trio and use it.
- (gori_compute::compute_operand2_range): Ditto.
- * range-op.cc (operator_plus::op1_range): Use correct trio member.
- (operator_minus::op1_range): Use correct trio member.
- * value-relation.cc (value_relation::create_trio): New.
- * value-relation.h (value_relation::create_trio): New prototype.
-
-2023-01-31 Jakub Jelinek <jakub@redhat.com>
-
- PR target/108599
- * config/i386/i386-expand.cc
- (ix86_convert_const_wide_int_to_broadcast): Return nullptr if
- CONST_WIDE_INT_NUNITS (op) times HOST_BITS_PER_WIDE_INT isn't
- equal to bitsize of mode.
-
-2023-01-31 Jakub Jelinek <jakub@redhat.com>
-
- PR rtl-optimization/108596
- * bb-reorder.cc (fix_up_fall_thru_edges): Handle the case where cur_bb
- ends with asm goto and has a crossing fallthrough edge to the same bb
- that contains at least one of its labels by restoring EDGE_CROSSING
- flag even on possible edge from cur_bb to new_bb successor.
-
-2023-01-31 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/105593
- * config/i386/avx512erintrin.h (_mm512_exp2a23_round_pd,
- _mm512_exp2a23_round_ps, _mm512_rcp28_round_pd, _mm512_rcp28_round_ps,
- _mm512_rsqrt28_round_pd, _mm512_rsqrt28_round_ps): Use
- _mm512_undefined_pd () or _mm512_undefined_ps () instead of using
- uninitialized automatic variable __W.
-
-2023-01-31 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/include/fdl.texi: Change fsf.org to www.fsf.org.
-
-2023-01-30 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (get_vector_mode): New function.
- * config/riscv/riscv-v.cc (get_vector_mode): Ditto.
- * config/riscv/riscv-vector-builtins-bases.cc (enum lst_type): New enum.
- (class loadstore): Adjust for indexed loads/stores support.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: New function declare.
- * config/riscv/riscv-vector-builtins-functions.def (vluxei8): Ditto.
- (vluxei16): Ditto.
- (vluxei32): Ditto.
- (vluxei64): Ditto.
- (vloxei8): Ditto.
- (vloxei16): Ditto.
- (vloxei32): Ditto.
- (vloxei64): Ditto.
- (vsuxei8): Ditto.
- (vsuxei16): Ditto.
- (vsuxei32): Ditto.
- (vsuxei64): Ditto.
- (vsoxei8): Ditto.
- (vsoxei16): Ditto.
- (vsoxei32): Ditto.
- (vsoxei64): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc
- (struct indexed_loadstore_def): New class.
- (SHAPE): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
- * config/riscv/riscv-vector-builtins.cc (required_extensions_p): Adjust
- for indexed loads/stores support.
- (check_required_extensions): Ditto.
- (rvv_arg_type_info::get_base_vector_type): New function.
- (rvv_arg_type_info::get_tree_type): Ditto.
- (function_builder::add_unique_function): Adjust for indexed loads/stores
- support.
- (function_expander::use_exact_insn): New function.
- * config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Adjust for
- indexed loads/stores support.
- (struct rvv_arg_type_info): Ditto.
- (function_expander::index_mode): New function.
- (function_base::apply_tail_policy_p): Ditto.
- (function_base::apply_mask_policy_p): Ditto.
- * config/riscv/vector-iterators.md (unspec): New unspec.
- * config/riscv/vector.md (unspec): Ditto.
- (@pred_indexed_<order>load<VNX1_QHSD:mode><VNX1_QHSDI:mode>): New
- pattern.
- (@pred_indexed_<order>store<VNX1_QHSD:mode><VNX1_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
- (@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
- (@pred_indexed_<order>load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
- (@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
+ PR tree-optimization/113371
+ * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
+ Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
+ * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
+ not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
-2023-01-30 Flavio Cruz <flaviocruz@gmail.com>
+2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
- * config.gcc: Recognize x86_64-*-gnu* targets and include
- i386/gnu64.h.
- * config/i386/gnu64.h: Define configuration for new target
- including ld.so location.
+ PR rtl-optimization/96388
+ PR rtl-optimization/111554
+ * sched-deps.cc (find_inc): Avoid exponential behavior.
-2023-01-30 Philipp Tomsich <philipp.tomsich@vrull.eu>
+2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
- * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
- ampere1a to include SM4.
+ PR c/111693
+ * doc/invoke.texi (Option Summary): Move -Wuseless-cast
+ from C++ Language Options to Warning Options. Add entry for
+ -Wuse-after-free.
+ (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
+ from here....
+ (Warning Options): ...to here. Minor copy-editing to fix typo
+ and grammar.
-2023-01-30 Andrew Pinski <apinski@marvell.com>
+2024-01-17 YunQiang Su <syq@gcc.gnu.org>
- PR tree-optimization/108582
- * tree-ssa-phiopt.cc (match_simplify_replacement): Add check
- for middlebb to have no phi nodes.
+ * config/mips/mips.cc (mips_compute_frame_info): If another
+ register is used as global_pointer, mark $GP live false.
-2023-01-30 Richard Biener <rguenther@suse.de>
+2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
- PR tree-optimization/108574
- * tree-ssa-sccvn.cc (visit_phi): Instead of swapping
- sameval and def, ignore the equivalence if there's the
- danger of oscillating between two values.
+ PR target/112973
+ * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
+ give the section a light copy-editing pass.
-2023-01-30 Andreas Schwab <schwab@suse.de>
+2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
- * common/config/riscv/riscv-common.cc
- (riscv_option_optimization_table)
- [TARGET_DEFAULT_ASYNC_UNWIND_TABLES]: Enable
- -fasynchronous-unwind-tables and -funwind-tables.
- * config.gcc (riscv*-*-linux*): Define
- TARGET_DEFAULT_ASYNC_UNWIND_TABLES.
+ * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
+ * config/aarch64/aarch64-tune.md: Regenerated.
+ * doc/invoke.texi (-mcpu): Add cobalt-100 core.
-2023-01-30 YunQiang Su <yunqiang.su@cipunited.com>
+2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
- * Makefile.in (CROSS_SYSTEM_HEADER_DIR): set according the
- value of includedir.
+ PR target/112573
+ * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
+ badly formed CONST expressions.
-2023-01-30 Richard Biener <rguenther@suse.de>
+2024-01-16 Daniel Cederman <cederman@gaisler.com>
- PR ipa/108511
- * cgraph.cc (possibly_call_in_translation_unit_p): Relax
- assert.
+ * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
-2023-01-30 liuhongt <hongtao.liu@intel.com>
+2024-01-16 Daniel Cederman <cederman@gaisler.com>
- * config/i386/i386.opt: Change AVX512FP16 to AVX512-FP16.
- * doc/invoke.texi: Ditto.
+ * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
+ * config/sparc/sync.md (membar_storeload): Turn into named insn
+ and add GR712RC errata workaround.
+ (membar_v8): Add GR712RC errata workaround.
-2023-01-29 Jan Hubicka <hubicka@ucw.cz>
+2024-01-16 Andreas Larsson <andreas@gaisler.com>
- * ipa-utils.cc: Include calls.h, cfgloop.h and cfganal.h
- (stmt_may_terminate_function_p): If assuming return or EH
- volatile asm is safe.
- (find_always_executed_bbs): Fix handling of terminating BBS and
- infinite loops; add debug output.
- * tree-ssa-alias.cc (stmt_kills_ref_p): Fix debug output
+ * config/sparc/sync.md (*membar_storeload_leon3): Remove
+ (*membar_storeload): Enable for LEON
-2023-01-28 Philipp Tomsich <philipp.tomsich@vrull.eu>
+2024-01-16 Jakub Jelinek <jakub@redhat.com>
- * config/aarch64/aarch64.cc (aarch64_uxt_size): fix an
- off-by-one in checking the permissible shift-amount.
+ PR tree-optimization/113372
+ PR middle-end/90348
+ PR middle-end/110115
+ PR middle-end/111422
+ * cfgexpand.cc (add_scope_conflicts_2): New function.
+ (add_scope_conflicts_1): Use it.
-2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-16 Georg-Johann Lay <avr@gjlay.de>
- * doc/extend.texi (Named Address Spaces): Update link to the
- AVR-Libc manual.
+ * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
+ (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
+ * doc/avr-mmcu.texi: Regenerate.
-2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
- * doc/standards.texi (Standards): Fix markup.
+ PR tree-optimization/113091
+ * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
+ (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
+ scalar use with new function.
+ (vect_bb_slp_mark_live_stmts): New function as entry to existing
+ overriden functions with same name.
+ (vect_slp_analyze_operations): Call new entry function to mark
+ live statements.
-2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * doc/standards.texi (Standards): Update link to Objective-C book.
+ PR target/113404
+ * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
+ for RVV in big-endian mode.
-2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
- * doc/invoke.texi (Instrumentation Options): Update reference to
- AddressSanitizer.
+ * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
+ (riscv_pass_in_vector_p): Delete.
+ (riscv_init_cumulative_args): Delete the checking.
+ (riscv_get_arg_info): Delete the checking.
+ (riscv_function_value): Delete the checking.
+ * config/riscv/riscv.h: Delete the member for checking.
-2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-15 Georg-Johann Lay <avr@gjlay.de>
- * doc/standards.texi: Update Go1 link.
+ * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
-2023-01-28 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
- * config/riscv/predicates.md (pmode_reg_or_0_operand): New predicate.
- * config/riscv/riscv-vector-builtins-bases.cc (class loadstore):
- Support vlse/vsse.
- (BASE): Ditto.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vlse): New class.
- (vsse): New class.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::use_contiguous_load_insn): Support vlse/vsse.
- * config/riscv/vector.md (@pred_strided_load<mode>): New md pattern.
- (@pred_strided_store<mode>): Ditto.
+ * config.gcc: Include riscv_bitmanip.h.
+ * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
+ * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
+ * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
+ (RISCV_BUILTIN_NO_PREFIX): New helper macro.
+ * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
+ * config/riscv/riscv-ftypes.def (2): New ftypes.
+ * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
+ (RISCV_BUILTIN_NO_PREFIX): Likewise.
+ * config/riscv/riscv_bitmanip.h: New file.
-2023-01-28 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
- * config/riscv/vector.md (tail_policy_op_idx): Remove.
- (mask_policy_op_idx): Remove.
- (avl_type_op_idx): Remove.
+ * config.gcc: Include riscv_crypto.h.
+ * config/riscv/riscv_crypto.h: New file.
-2023-01-27 Richard Sandiford <richard.sandiford@arm.com>
+2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
- PR tree-optimization/96373
- * tree.h (sign_mask_for): Declare.
- * tree.cc (sign_mask_for): New function.
- (signed_or_unsigned_type_for): For vector types, try to use the
- related_int_vector_mode.
- * genmatch.cc (commutative_op): Handle conditional internal functions.
- * match.pd: Fold an IFN_COND_MUL+copysign into an IFN_COND_XOR+and.
+ PR middle-end/113354
+ * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
+ in the insn if the corresponding operand does not require hard
+ register anymore.
-2023-01-27 Richard Sandiford <richard.sandiford@arm.com>
+2024-01-15 Georg-Johann Lay <avr@gjlay.de>
- * tree-vectorizer.cc (vector_costs::compare_inside_loop_cost):
- Use the likely minimum VF when bounding the denominators to
- the estimated number of iterations.
+ PR target/107201
+ * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
+ * config/avr/driver-avr.cc (avr_no_devlib): New function.
+ (avr_devicespecs_file): Use it to remove -nodevicelib from the
+ options for cores only.
+ * config/avr/avr-arch.h (avr_get_parch): New prototype.
+ * config/avr/avr-devices.cc (avr_get_parch): New function.
-2023-01-27 Richard Biener <rguenther@suse.de>
+2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR target/55522
- * doc/invoke.texi (-shared): Clarify effect on -ffast-math
- and -Ofast FP environment side-effects.
+ PR target/113247
+ * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
+ * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
+ * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
-2023-01-27 Richard Biener <rguenther@suse.de>
+2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR target/55522
- * config/mips/gnu-user.h (GNU_USER_TARGET_MATHFILE_SPEC):
- Don't add crtfastmath.o for -shared.
+ PR target/113281
+ * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
+ (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
+ * config/riscv/riscv-vector-costs.h: New function.
-2023-01-27 Richard Biener <rguenther@suse.de>
+2024-01-15 Richard Biener <rguenther@suse.de>
- PR target/55522
- * config/ia64/linux.h (ENDFILE_SPEC): Don't add crtfastmath.o
- for -shared.
+ PR tree-optimization/113385
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ First redirect, then split the exit edge.
-2023-01-27 Richard Biener <rguenther@suse.de>
+2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR target/55522
- * config/alpha/linux.h (ENDFILE_SPEC): Don't add
- crtfastmath.o for -shared.
+ * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
+ Remove m_num_vector_iterations.
+ * config/riscv/riscv-vector-costs.h: Ditto.
-2023-01-27 Andrew MacLeod <amacleod@redhat.com>
+2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
- PR tree-optimization/108306
- * range-op.cc (operator_lshift::fold_range): Return [0, 0] not
- varying for shifts that are always out of void range.
- (operator_rshift::fold_range): Return [0, 0] not
- varying for shifts that are always out of void range.
+ PR target/113156
+ * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
+ (-mbranch-cost): Set "Optimization" flag.
-2023-01-27 Andrew MacLeod <amacleod@redhat.com>
+2024-01-15 Jakub Jelinek <jakub@redhat.com>
- PR tree-optimization/108447
- * gimple-range-fold.cc (old_using_range::relation_fold_and_or):
- Do not attempt to fold HONOR_NAN types.
+ PR tree-optimization/113370
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
+ set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
+ set it to just prec % limb_prec.
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * config/riscv/riscv-vector-builtins-shapes.cc (struct loadstore_def):
- Remove _m suffix for "vop_m" C++ overloaded API name.
+ PR target/113393
+ * config/riscv/vector.md: Fix ternary attributes.
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-14 Georg-Johann Lay <avr@gjlay.de>
- * config/riscv/riscv-vector-builtins-bases.cc (BASE): Add vlm/vsm support.
- * config/riscv/riscv-vector-builtins-bases.h: Ditto.
- * config/riscv/riscv-vector-builtins-functions.def (vlm): New define.
- (vsm): Ditto.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct loadstore_def): Add vlm/vsm support.
- * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_B_OPS): Ditto.
- (vbool64_t): Ditto.
- (vbool32_t): Ditto.
- (vbool16_t): Ditto.
- (vbool8_t): Ditto.
- (vbool4_t): Ditto.
- (vbool2_t): Ditto.
- (vbool1_t): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_B_OPS): Ditto.
- (rvv_arg_type_info::get_tree_type): Ditto.
- (function_expander::use_contiguous_load_insn): Ditto.
- * config/riscv/vector.md (@pred_store<mode>): Ditto.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (vsetvl_insn_p): Add condition to avoid ICE.
- (vsetvl_discard_result_insn_p): New function.
- (reg_killed_by_bb_p): rename to find_reg_killed_by.
- (find_reg_killed_by): New name.
- (get_vl): allow it to be called by more functions.
- (has_vsetvl_killed_avl_p): Add condition.
- (get_avl): allow it to be called by more functions.
- (insn_should_be_added_p): New function.
- (get_all_nonphi_defs): Refine function.
- (get_all_sets): Ditto.
- (get_same_bb_set): New function.
- (any_insn_in_bb_p): Ditto.
- (any_set_in_bb_p): Ditto.
- (get_vl_vtype_info): Add VLMAX forward optimization.
- (source_equal_p): Fix issues.
- (extract_single_source): Refine.
- (avl_info::multiple_source_equal_p): New function.
- (avl_info::operator==): Adjust for final version.
- (vl_vtype_info::operator==): Ditto.
- (vl_vtype_info::same_avl_p): Ditto.
- (vector_insn_info::parse_insn): Ditto.
- (vector_insn_info::available_p): New function.
- (vector_insn_info::merge): Adjust for final version.
- (vector_insn_info::dump): Add hard_empty.
- (pass_vsetvl::hard_empty_block_p): New function.
- (pass_vsetvl::backward_demand_fusion): Adjust for final version.
- (pass_vsetvl::forward_demand_fusion): Ditto.
- (pass_vsetvl::demand_fusion): Ditto.
- (pass_vsetvl::cleanup_illegal_dirty_blocks): New function.
- (pass_vsetvl::compute_local_properties): Adjust for final version.
- (pass_vsetvl::can_refine_vsetvl_p): Ditto.
- (pass_vsetvl::refine_vsetvls): Ditto.
- (pass_vsetvl::commit_vsetvls): Ditto.
- (pass_vsetvl::propagate_avl): New function.
- (pass_vsetvl::lazy_vsetvl): Adjust for new version.
- * config/riscv/riscv-vsetvl.h (enum def_type): New enum.
-
-2023-01-27 Jakub Jelinek <jakub@redhat.com>
-
- PR other/108560
- * doc/extend.texi: Fix up return type of __builtin_va_arg_pack_len
- from size_t to int.
-
-2023-01-27 Jakub Jelinek <jakub@redhat.com>
-
- PR ipa/106061
- * cgraph.cc (cgraph_edge::verify_corresponds_to_fndecl): Allow
- redirection of calls to __builtin_trap in addition to redirection
- to __builtin_unreachable.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (before_p): Fix bug.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Refine function args.
- (emit_vsetvl_insn): Ditto.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix constraints.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
-
-2023-01-27 Patrick Palka <ppalka@redhat.com>
- Jakub Jelinek <jakub@redhat.com>
+ PR target/112944
+ * configure.ac [target=avr]: Check availability of emulations
+ avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
+ HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
+ * configure: Regenerate.
+ * config.in: Regenerate.
+ * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
+ __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
+ * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
+ * config/avr/avr-arch.h (enum avr_device_specific_features):
+ Add AVR_ISA_FLMAP.
+ * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
+ AVR_ISA_FLMAP.
+ * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
+ (avr_set_core_architecture): Set avr_arch_index.
+ (have_avrxmega2_flmap, have_avrxmega4_flmap)
+ (have_avrxmega3_rodata_in_flash): Set new static const bool according
+ to configure results.
+ (avr_rodata_in_flash_p): New function using them.
+ (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
+ track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
+ (avr_asm_named_section): Track avr_has_rodata_p.
+ (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
+ and not avr_rodata_in_flash_p ().
+ * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
+ (LINK_SPEC): Add %(link_rodata_in_ram).
+ (LINK_ARCH_SPEC): Remove.
+ * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
+ (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
+ const bool according to configure results.
+ (diagnose_mrodata_in_ram): New function.
+ (print_mcu): Generate specs with the following changes:
+ <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
+ need to extend avr/specs.h each time we add a new bell or whistle.
+ <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
+ -m[no-]rodata-in-ram.
+ <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
+ <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
+ <*cpp>: Add %(cpp_rodata_in_ram).
+ <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
+ requested.
+ <*self_spec>: Add -mflmap or %<mflmap as needed.
+
+2024-01-14 Jeff Law <jlaw@ventanamicro.com>
+
+ * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
+ not the GPR iterator. Adjust pattern name and mode attribute
+ accordingly.
- * tree-core.h (tree_code_type, tree_code_length): For
- C++17 and later, add inline keyword, otherwise don't define
- the arrays, but declare extern arrays.
- * tree.cc (tree_code_type, tree_code_length): Define these
- arrays for C++14 and older.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.h: Change it into public.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder VSETVL
- pass.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::execute): Always call split_all_insns.
-
-2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix incorrect attributes.
-
-2023-01-27 Richard Biener <rguenther@suse.de>
-
- PR target/55522
- * config/loongarch/gnu-user.h (GNU_USER_TARGET_MATHFILE_SPEC):
- Don't add crtfastmath.o for -shared.
-
-2023-01-27 Alexandre Oliva <oliva@gnu.org>
-
- * doc/options.texi (option, RejectNegative): Mention that
- -g-started options are also implicitly negatable.
-
-2023-01-26 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-vector-builtins.cc (register_builtin_types):
- Use get_typenode_from_name to get fixed-width integer type
- nodes.
- * config/riscv/riscv-vector-builtins.def: Update define with
- fixed-width integer type nodes.
-
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (same_bb_and_before_p): Remove it.
- (real_insn_and_same_bb_p): New function.
- (same_bb_and_after_or_equal_p): Remove it.
- (before_p): New function.
- (reg_killed_by_bb_p): Ditto.
- (has_vsetvl_killed_avl_p): Ditto.
- (get_vl): Move location so that we can call it.
- (anticipatable_occurrence_p): Fix issue of AVL=REG support.
- (available_occurrence_p): Ditto.
- (dominate_probability_p): Remove it.
- (can_backward_propagate_p): Remove it.
- (get_all_nonphi_defs): New function.
- (get_all_predecessors): Ditto.
- (any_insn_in_bb_p): Ditto.
- (insert_vsetvl): Adjust AVL REG.
- (source_equal_p): New function.
- (extract_single_source): Ditto.
- (avl_info::single_source_equal_p): Ditto.
- (avl_info::operator==): Adjust for AVL=REG.
- (vl_vtype_info::same_avl_p): Ditto.
- (vector_insn_info::set_demand_info): Remove it.
- (vector_insn_info::compatible_p): Adjust for AVL=REG.
- (vector_insn_info::compatible_avl_p): New function.
- (vector_insn_info::merge): Adjust AVL=REG.
- (vector_insn_info::dump): Ditto.
- (pass_vsetvl::merge_successors): Remove it.
- (enum fusion_type): New enum.
- (pass_vsetvl::get_backward_fusion_type): New function.
- (pass_vsetvl::backward_demand_fusion): Adjust for AVL=REG.
- (pass_vsetvl::forward_demand_fusion): Ditto.
- (pass_vsetvl::demand_fusion): Ditto.
- (pass_vsetvl::prune_expressions): Ditto.
- (pass_vsetvl::compute_local_properties): Ditto.
- (pass_vsetvl::cleanup_vsetvls): Ditto.
- (pass_vsetvl::commit_vsetvls): Ditto.
- (pass_vsetvl::init): Ditto.
- * config/riscv/riscv-vsetvl.h (enum fusion_type): New enum.
- (enum merge_type): New enum.
-
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-13 Jakub Jelinek <jakub@redhat.com>
- * config/riscv/riscv-vsetvl.cc
- (vector_infos_manager::vector_infos_manager): Add probability.
- (vector_infos_manager::dump): Ditto.
- (pass_vsetvl::compute_probabilities): Ditto.
- * config/riscv/riscv-vsetvl.h (struct vector_block_info): Ditto.
+ PR tree-optimization/113361
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
+ Fix up determination of the type for > limb_prec constants.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Georg-Johann Lay <avr@gjlay.de>
- * config/riscv/riscv-vsetvl.cc (vector_insn_info::operator==): Remove dirty_pat.
- (vector_insn_info::merge): Ditto.
- (vector_insn_info::dump): Ditto.
- (pass_vsetvl::merge_successors): Ditto.
- (pass_vsetvl::backward_demand_fusion): Ditto.
- (pass_vsetvl::forward_demand_fusion): Ditto.
- (pass_vsetvl::commit_vsetvls): Ditto.
- * config/riscv/riscv-vsetvl.h: Ditto.
+ * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
+ Add web-link to the avr-gcc wiki.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Georg-Johann Lay <avr@gjlay.de>
- * config/riscv/riscv-vsetvl.cc (add_label_notes): Rename insn to
- rinsn.
+ * doc/extend.texi (AVR Variable Attributes) [address]: Remove
+ documentation for a version without argument, which is not supported.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::backward_demand_fusion): Refine codes.
+ * config/arm/arm_neon.h
+ (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
+ (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
+ (vld1_f16_x4, vld1_f32_x4): New.
+ (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
+ (vld1_bf16_x4): New.
+ (vld1q_types_x4): Updated to use vld1q_x4
+ from arm_neon_builtins.def
+ * config/arm/arm_neon_builtins.def
+ (vld1_x4): Updated entries.
+ (vld1q_x4): New entries, but comes from the old vld1_x4
+ * config/arm/neon.md
+ (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (pass_vsetvl::forward_demand_fusion):
- Add pre-check for redundant flow.
+ * config/arm/arm_neon.h
+ (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
+ (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
+ (vld1_f16_x3, vld1_f32_x3): New.
+ (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
+ (vld1_bf16_x3): New.
+ (vld1q_types_x3): Updated to use vld1q_x3 from
+ arm_neon_builtins.def
+ * config/arm/arm_neon_builtins.def
+ (vld1_x3): Updated entries.
+ (vld1q_x3): New entries, but comes from the old vld1_x2
+ * config/arm/neon.md
+ (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (vector_infos_manager::create_bitmap_vectors): New function.
- (vector_infos_manager::free_bitmap_vectors): Ditto.
- (pass_vsetvl::pre_vsetvl): Adjust codes.
- * config/riscv/riscv-vsetvl.h: New function declaration.
+ * config/arm/arm_neon.h
+ (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
+ (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
+ (vld1_f16_x2, vld1_f32_x2): New.
+ (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
+ (vld1_bf16_x2): New.
+ (vld1q_types_x2): Updated to use vld1q_x2 from
+ arm_neon_builtins.def
+ * config/arm/arm_neon_builtins.def
+ (vld1_x2): Updated entries.
+ (vld1q_x2): New entries, but comes from the old vld1_x2
+ * config/arm/neon.md
+ (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
+ neon_vld1_x2<mode>.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (can_backward_propagate_p): Fix for null iter_bb.
- (vector_insn_info::set_demand_info): New function.
- (pass_vsetvl::emit_local_forward_vsetvls): Adjust for refinement of Phase 3.
- (pass_vsetvl::merge_successors): Ditto.
- (pass_vsetvl::compute_global_backward_infos): Ditto.
- (pass_vsetvl::backward_demand_fusion): Ditto.
- (pass_vsetvl::forward_demand_fusion): Ditto.
- (pass_vsetvl::demand_fusion): New function.
- (pass_vsetvl::lazy_vsetvl): Adjust for refinement of phase 3.
- * config/riscv/riscv-vsetvl.h: New function declaration.
+ * config/arm/arm_neon.h
+ (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
+ (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
+ (vst1q_f16_x4, vst1q_f32_x4): New.
+ (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
+ (vst1q_bf16_x4): New.
+ * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
+ * config/arm/neon.md
+ (neon_vst1q_x4<mode>): New.
+ (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
+ * config/arm/unspecs.md
+ (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (vector_insn_info::operator>=): Fix available condition.
+ * config/arm/arm_neon.h
+ (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
+ (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
+ (vst1q_f16_x3, vst1q_f32_x3): New.
+ (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
+ (vst1q_bf16_x3): New.
+ * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
+ * config/arm/neon.md
+ (neon_vst1q_x3<mode>): New.
+ (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
+ * config/arm/unspecs.md
+ (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (change_vsetvl_insn): New function.
- (pass_vsetvl::compute_global_backward_infos): Simplify codes.
+ * config/arm/arm_neon.h
+ (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
+ (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
+ (vst1q_f16_x2, vst1q_f32_x2): New.
+ (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
+ (vst1q_bf16_x2): New.
+ * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
+ * config/arm/neon.md
+ (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
+ neon_vst1_x2<mode>.
+ * config/arm/iterators.md
+ (VMEMX2): New mode iterator.
+ (VMEMX2_q): New mode attribute.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (loop_basic_block_p): Adjust function.
- (backward_propagate_worthwhile_p): Fix non-worthwhile.
+ * config/arm/arm_neon.h
+ (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
+ (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
+ (vst1_f16_x4, vst1_f32_x4): New.
+ (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
+ (vst1_bf16_x4): New.
+ * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
+ * config/arm/neon.md (vst1_x4<mode>): New.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (change_insn): Adjust in_group in validate_change.
+ * config/arm/arm_neon.h
+ (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
+ (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
+ (vst1_f16_x3, vst1_f32_x3): New.
+ (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
+ (vst1_bf16_x3): New.
+ * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
+ * config/arm/neon.md (vst1_x3<mode>): New.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vsetvl.cc (vector_infos_manager::all_same_avl_p): New function.
- (pass_vsetvl::can_refine_vsetvl_p): Add AVL check.
- (pass_vsetvl::commit_vsetvls): Ditto.
- * config/riscv/riscv-vsetvl.h: New function declaration.
+ * config/arm/arm_neon.h
+ (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
+ (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
+ (vst1_f16_x2, vst1_f32_x2): New.
+ (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
+ (vst1_bf16_x2): New.
+ * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
+ * config/arm/neon.md (vst1_x2<mode>): New.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/vector.md:
+ * config/arm/arm_neon.h
+ (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
+ (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
+ (vld1q_f16_x4, vld1q_f32_x4): New.
+ (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
+ (vld1q_bf16_x4): New.
+ * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
+ * config/arm/neon.md
+ (neon_vld1_x4<mode>): New.
+ (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
+ * config/arm/unspecs.md
+ (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vector-builtins-bases.cc (class loadstore): use
- pred_store for vse.
- * config/riscv/riscv-vector-builtins.cc
- (function_expander::add_mem_operand): Refine function.
- (function_expander::use_contiguous_load_insn): Adjust new
- implementation.
- (function_expander::use_contiguous_store_insn): Ditto.
- * config/riscv/riscv-vector-builtins.h: Refine function.
- * config/riscv/vector.md (@pred_store<mode>): New pattern.
+ * config/arm/arm_neon.h
+ (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
+ (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
+ (vld1q_f16_x3, vld1q_f32_x3): New.
+ (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
+ (vld1q_bf16_x3): New.
+ * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
+ * config/arm/neon.md
+ (neon_vld1_x3<mode>): New.
+ (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
+ * config/arm/unspecs.md
+ (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
-2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
- * config/riscv/riscv-vector-builtins.cc: Change to scalar pointer.
+ * config/arm/arm_neon.h
+ (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
+ (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
+ (vld1q_f16_x2, vld1q_f32_x2): New.
+ (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
+ (vld1q_bf16_x2): New.
+ * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
+ * config/arm/neon.md (vld1_x2<mode>): New.
-2023-01-26 Marek Polacek <polacek@redhat.com>
+2024-01-12 Tamar Christina <tamar.christina@arm.com>
- PR middle-end/108543
- * opts.cc (parse_sanitizer_options): Don't always clear SANITIZE_ADDRESS
- if it was previously set.
+ PR tree-optimization/113287
+ * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
-2023-01-26 Jakub Jelinek <jakub@redhat.com>
+2024-01-12 Tamar Christina <tamar.christina@arm.com>
- PR tree-optimization/108540
- * range-op-float.cc (foperator_equal::fold_range): If both op1 and op2
- are singletons, use range_true even if op1 != op2
- when one range is [-0.0, -0.0] and another [0.0, 0.0]. Similarly,
- even if intersection of the ranges is empty and one has
- zero low bound and another zero high bound, use range_true_and_false
- rather than range_false.
- (foperator_not_equal::fold_range): If both op1 and op2
- are singletons, use range_false even if op1 != op2
- when one range is [-0.0, -0.0] and another [0.0, 0.0]. Similarly,
- even if intersection of the ranges is empty and one has
- zero low bound and another zero high bound, use range_true_and_false
- rather than range_true.
+ * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
+ * tree-vect-loop.cc (vect_transform_loop): Likewise.
-2023-01-26 Jakub Jelinek <jakub@redhat.com>
+2024-01-12 Tamar Christina <tamar.christina@arm.com>
- * value-relation.cc (kind_string): Add const.
- (rr_negate_table, rr_swap_table, rr_intersect_table,
- rr_union_table, rr_transitive_table): Add static const, change
- element type from relation_kind to unsigned char.
- (relation_negate, relation_swap, relation_intersect, relation_union,
- relation_transitive): Cast rr_*_table element to relation_kind.
- (relation_to_code): Add static const.
- (relation_tests): Assert VREL_LAST is smaller than UCHAR_MAX.
+ PR tree-optimization/113178
+ * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
+ alternate exits.
-2023-01-26 Richard Biener <rguenther@suse.de>
+2024-01-12 Tamar Christina <tamar.christina@arm.com>
- PR tree-optimization/108547
- * gimple-predicate-analysis.cc (value_sat_pred_p):
- Use widest_int.
+ PR tree-optimization/113237
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
+ existing LCSSA variable for exit when all exits are early break.
-2023-01-26 Siddhesh Poyarekar <siddhesh@gotplt.org>
+2024-01-12 Tamar Christina <tamar.christina@arm.com>
- PR tree-optimization/108522
- * tree-object-size.cc (compute_object_offset): Make EXPR
- argument non-const. Call component_ref_field_offset.
+ PR tree-optimization/113137
+ PR tree-optimization/113136
+ PR tree-optimization/113172
+ PR tree-optimization/113178
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Maintain PHIs on inverted loops.
+ (vect_do_peeling): Maintain virtual PHIs on inverted loops.
+ * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
+ latch.
+ (vect_create_loop_vinfo): Record all conds instead of only alt ones.
-2023-01-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+2024-01-12 Tamar Christina <tamar.christina@arm.com>
- * config/aarch64/aarch64-option-extensions.def (cssc): Specify
- FEATURE_STRING field.
+ PR tree-optimization/113135
+ * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
+ dependency analysis.
-2023-01-26 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
- * doc/sourcebuild.texi: Refer to projects as GCC and GDB.
+ * config/rs6000/host-darwin.cc (segv_handler): Use the revised
+ diagnostics class member name for abort of error.
-2023-01-25 Iain Sandoe <iain@sandoe.co.uk>
+2024-01-12 Georg-Johann Lay <avr@gjlay.de>
- PR modula2/102343
- PR modula2/108182
- * gcc.cc: Provide default specs for Modula-2 so that when the
- language is not built-in better diagnostics are emitted for
- attempts to use .mod or .m2i file extensions.
+ * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
+ format string to %s argument.
-2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
+2024-01-12 John David Anglin <danglin@gcc.gnu.org>
+ Jakub Jelinek <jakub@redhat.com>
- * config/arm/mve.md (mve_vqnegq_s<mode>): Fix spacing.
+ PR middle-end/113182
+ * varasm.cc (process_pending_assemble_externals,
+ assemble_external_libcall): Use targetm.strip_name_encoding
+ before calling get_identifier.
-2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
+2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
- * config/arm/mve.md (mve_vqabsq_s<mode>): Fix spacing.
+ PR target/113196
+ * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
+ New member variable.
+ * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
+ Declare.
+ * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
+ * config/aarch64/aarch64-simd.md
+ (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
+ (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
+ zip2 for zero-extends to...
+ (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
+ instruction. Fix big-endian handling.
+ (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
+ (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
+ zip1 for zero-extends to...
+ (<optab><Vnarrowq><mode>2): ...a split of this instruction.
+ Fix big-endian handling.
+ (*aarch64_zip1_uxtl): New pattern.
+ (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
+ (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
+ * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
+ (aarch64_gen_shareable_zero): Use it.
+ (aarch64_split_simd_shift_p): New function.
+
+2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
+ (function_beg_insn): New macro.
+ * function.cc (expand_function_start): Initialize function_beg_insn.
+
+2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/112989
+ * config/aarch64/aarch64-sve-builtins.h
+ (function_builder::m_overload_names): Replace with...
+ * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
+ new global.
+ (add_overloaded_function): Update accordingly, using get_identifier
+ to get a GGC-friendly record of the name.
+
+2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/112989
+ * config/aarch64/aarch64-sve-builtins.def: Don't include
+ aarch64-sve-builtins-sme.def.
+ (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
+ * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
+ (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
+ instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
+ requires AARCH64_FL_SME2.
+ * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
+ AARCH64_FL_SME adjustment here.
+ * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
+ include SME intrinsics.
+ (sme_function_groups): New array.
+ (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
+ (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
+
+2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/113281
+ * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
+ (struct cpu_vector_cost): Add regmove struct.
+ (get_vector_costs): Export as global.
+ * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
+ (costs::add_stmt_cost): Ditto.
+ * config/riscv/riscv.cc (get_common_costs): Export global function.
-2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
+2024-01-12 Jakub Jelinek <jakub@redhat.com>
- * config/arm/mve.md (mve_vnegq_f<mode>, mve_vnegq_s<mode>):
- Fix spacing.
+ PR tree-optimization/113334
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
+ wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
+ to determine if number should be extended by all ones rather than zero
+ extended.
-2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
+2024-01-12 Jakub Jelinek <jakub@redhat.com>
- * config/arm/mve.md (@mve_vclzq_s<mode>): Fix spacing.
+ PR tree-optimization/113330
+ * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
+ too large size.
-2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
+2024-01-12 Jakub Jelinek <jakub@redhat.com>
- * config/arm/mve.md (mve_vclsq_s<mode>): Fix spacing.
+ PR tree-optimization/113323
+ * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
+ check for lhs being large/huge _BitInt not in m_names.
-2023-01-25 Richard Biener <rguenther@suse.de>
+2024-01-12 Jakub Jelinek <jakub@redhat.com>
- PR tree-optimization/108523
- * tree-ssa-sccvn.cc (visit_phi): Avoid using the exclusive
- backedge value for the result when using predication to
- prove equivalence.
+ PR tree-optimization/113316
+ * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
+ uninitialized large/huge _BitInt arguments to calls.
-2023-01-25 Richard Biener <rguenther@suse.de>
+2024-01-12 Jakub Jelinek <jakub@redhat.com>
- * doc/lto.texi (Command line options): Reword and update reference
- to removed lto_read_all_file_options.
+ * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
+ TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
+ CEIL (TYPE_PRECISION (t), limb_prec).
+ (bitint_large_huge::handle_cast): Likewise.
-2023-01-25 Richard Sandiford <richard.sandiford@arm.com>
+2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
- * config/aarch64/aarch64.md (umax<mode>3): Separate the CNT and CSSC
- tests.
+ PR sanitizer/113284
+ * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
+ Use assemble_function_label_final () for Power ELF V1 ABI.
+ * output.h (assemble_function_label_final): New function.
+ * varasm.cc (assemble_function_label_raw): Use
+ assemble_function_label_final ().
+ (assemble_function_label_final): New function.
-2023-01-25 Gerald Pfeifer <gerald@pfeifer.com>
+2024-01-12 Richard Biener <rguenther@suse.de>
- * doc/contrib.texi: Add Jose E. Marchesi.
+ PR middle-end/113344
+ * match.pd ((double)float CMP (double)float -> float CMP float):
+ Perform result type check only for vectors.
+ * fold-const.cc (fold_binary_loc): Likewise.
-2023-01-25 Jakub Jelinek <jakub@redhat.com>
+2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
- PR tree-optimization/108498
- * gimple-ssa-store-merging.cc (class store_operand_info):
- End coment with full stop rather than comma.
- (split_group): Likewise.
- (merged_store_group::apply_stores): Clear string_concatenation if
- start or end aren't on a byte boundary.
+ * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
+ (usdot_prod<mode>): Ditto.
+ (sdot_prod<mode>): Ditto.
+ (udot_prod<mode>): Ditto.
-2023-01-25 Siddhesh Poyarekar <siddhesh@gotplt.org>
- Jakub Jelinek <jakub@redhat.com>
+2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
- PR tree-optimization/108522
- * tree-object-size.cc (compute_object_offset): Use
- TREE_OPERAND(ref, 2) for COMPONENT_REF when available.
+ PR target/113288
+ * config/i386/i386-c.cc (ix86_target_macros_internal):
+ Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
-2023-01-24 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+2024-01-12 Richard Biener <rguenther@suse.de>
- * config/xtensa/xtensa.md:
- Fix exit from loops detecting references before overwriting in the
- split pattern.
+ PR target/112280
+ * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
+ Do not generate code when d.testing_p.
-2023-01-24 Vladimir N. Makarov <vmakarov@redhat.com>
+2024-01-12 liuhongt <hongtao.liu@intel.com>
- * lra-constraints.cc (get_hard_regno): Remove final_p arg. Always
- do elimination but only for hard register.
- (operands_match_p, uses_hard_regs_p, process_alt_operands): Adjust
- calls of get_hard_regno.
+ PR target/113039
+ * doc/invoke.texi (fcf-protection=): Update documents.
-2023-01-24 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-d.cc (s390_d_target_versions): Fix detection
- of CPU version.
+2024-01-12 Pan Li <pan2.li@intel.com>
-2023-01-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
+ comments of predicate func riscv_v_ext_mode_p.
- PR target/108177
- * config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
- mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
- as input operand.
+2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
-2023-01-24 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+ * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
+ Modify ABI-name length of vfloat16m8_t
- * config.gcc(csky-*-linux*): Define CSKY_ENABLE_MULTILIB
- and only include 'csky/t-csky-linux' when enable multilib.
- * config/csky/csky-linux-elf.h(SYSROOT_SUFFIX_SPEC): Don't
- define it when disable multilib.
+2024-01-12 Li Wei <liwei@loongson.cn>
-2023-01-24 Richard Biener <rguenther@suse.de>
+ * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
+ Adjust.
- PR tree-optimization/108500
- * dominance.h (calculate_dominance_info): Add parameter
- to indicate fast-query compute, defaulted to true.
- * dominance.cc (calculate_dominance_info): Honor
- fast-query compute parameter.
- * tree-cfgcleanup.cc (cleanup_tree_cfg_noloop): Do
- not compute the dominator fast-query DFS numbers.
+2024-01-12 Li Wei <liwei@loongson.cn>
-2023-01-24 Eric Biggers <ebiggers@google.com>
+ * config/loongarch/loongarch.md (add<mode>3): Removed.
+ (*addsi3): New.
+ (addsi3): Ditto.
+ (adddi3): Ditto.
+ (*addsi3_extended): Removed.
+ (addsi3_extended): New.
- PR bootstrap/90543
- * optc-save-gen.awk: Fix copy-and-paste error.
+2024-01-11 Jin Ma <jinma@linux.alibaba.com>
-2023-01-24 Jakub Jelinek <jakub@redhat.com>
+ * config/riscv/thead.md: Add limits for splits.
- PR c++/108474
- * cgraphbuild.cc: Include gimplify.h.
- (record_reference): Replace VAR_DECLs with DECL_HAS_VALUE_EXPR_P with
- their corresponding DECL_VALUE_EXPR expressions after unsharing.
+2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
-2023-01-24 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+ PR middle-end/113322
+ * expr.cc (do_store_flag): Don't try single bit tests with
+ comparison on vector types.
- PR target/108505
- * config.gcc (tm_file): Move the variable out of loop.
+2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
-2023-01-24 Lulu Cheng <chenglulu@loongson.cn>
- Yang Yujie <yangyujie@loongson.cn>
+ PR tree-optimization/113301
+ * match.pd (`1/x`): Delay signed case until late.
- PR target/107731
- * config/loongarch/loongarch.cc (loongarch_classify_address):
- Add precessint for CONST_INT.
- (loongarch_print_operand_reloc): Operand modifier 'c' is supported.
- (loongarch_print_operand): Increase the processing of '%c'.
- * doc/extend.texi: Adds documents for LoongArch operand modifiers.
- And port the public operand modifiers information to this document.
+2024-01-11 Georg-Johann Lay <avr@gjlay.de>
-2023-01-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+ * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
+ and -msp8 to...
+ (AVR Internal Options): ...this new @subsubsection.
- * doc/invoke.texi (-mbranch-protection): Update documentation.
+2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
-2023-01-23 Richard Biener <rguenther@suse.de>
+ PR rtl-optimization/112918
+ * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
+ (in_class_p): Restrict condition for narrowing class in case of
+ allow_all_reload_class_changes_p.
+ (process_alt_operands): Try to match operand without and with
+ narrowing reg class. Discourage narrowing the class. Finish insn
+ matching only if there is no class narrowing.
+ (curr_insn_transform): Pass true to in_class_p for reg operand win.
- PR target/55522
- * config/sparc/freebsd.h (ENDFILE_SPEC): Don't add crtfastmath.o
- for -shared.
- * config/sparc/linux.h (ENDFILE_SPEC): Likewise.
- * config/sparc/linux64.h (ENDFILE_SPEC): Likewise.
- * config/sparc/sp-elf.h (ENDFILE_SPEC): Likewise.
- * config/sparc/sp64-elf.h (ENDFILE_SPEC): Likewise.
+2024-01-11 Richard Biener <rguenther@suse.de>
-2023-01-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+ PR tree-optimization/112505
+ * tree-vect-loop.cc (vectorizable_induction): Reject
+ bit-precision induction.
- * config/arm/aout.h (ra_auth_code): Add entry in enum.
- * config/arm/arm.cc (emit_multi_reg_push): Add RA_AUTH_CODE register
- to dwarf frame expression.
- (arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
- (arm_expand_prologue): Update frame related information and reg notes
- for pac/pacbit insn.
- (arm_regno_class): Check for pac pseudo reigster.
- (arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
- (arm_init_machine_status): Set pacspval_needed to zero.
- (arm_debugger_regno): Check for PAC register.
- (arm_unwind_emit_sequence): Print .save directive with ra_auth_code
- register.
- (arm_unwind_emit_set): Add entry for IP_REGNUM in switch case.
- (arm_unwind_emit): Update REG_CFA_REGISTER case._
- * config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
- (DWARF_PAC_REGNUM): Define.
- (IS_PAC_REGNUM): Likewise.
- (enum reg_class): Add PAC_REG entry.
- (machine_function): Add pacbti_needed state to structure.
- * config/arm/arm.md (RA_AUTH_CODE): Define.
-
-2023-01-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
-
- * config.gcc ($tm_file): Update variable.
- * config/arm/arm-mlib.h: Create new header file.
- * config/arm/t-rmprofile (MULTI_ARCH_DIRS_RM): Rename mbranch-protection
- multilib arch directory.
- (MULTILIB_REUSE): Add multilib reuse rules.
- (MULTILIB_MATCHES): Add multilib match rules.
-
-2023-01-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
-
- * config/arm/arm-cpus.in (cortex-m85): Define new CPU.
- * config/arm/arm-tables.opt: Regenerate.
- * config/arm/arm-tune.md: Likewise.
- * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m85.
- * (-mfix-cmse-cve-2021-35465): Likewise.
-
-2023-01-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108482
- * tree-vect-generic.cc (expand_vector_operations): Fold remaining
- .LOOP_DIST_ALIAS calls.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
-
- * config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
- * config/arm/arm-protos.h: Update.
- * config/arm/aarch-common-protos.h: Declare
- 'aarch_bti_arch_check'.
- * config/arm/arm.cc (aarch_bti_enabled) Update.
- (aarch_bti_j_insn_p, aarch_pac_insn_p, aarch_gen_bti_c)
- (aarch_gen_bti_j, aarch_bti_arch_check): New functions.
- * config/arm/arm.md (bti_nop): New insn.
- * config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
- (aarch-bti-insert.o): New target.
- * config/arm/unspecs.md (VUNSPEC_BTI_NOP): New unspec.
- * config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Verify arch
- compatibility.
- (gate): Make use of 'aarch_bti_arch_check'.
- * config/arm/arm-passes.def: New file.
- * config/aarch64/aarch64.cc (aarch_bti_arch_check): New function.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
-
- * config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into
- 'aarch-bti-insert.o'.
- * config/aarch64/aarch64-protos.h: Remove 'aarch64_bti_enabled'
- proto.
- * config/aarch64/aarch64.cc (aarch_bti_enabled): Rename.
- (aarch_bti_j_insn_p, aarch_pac_insn_p): New functions.
- (aarch64_output_mi_thunk)
- (aarch64_print_patchable_function_entry)
- (aarch64_file_end_indicate_exec_stack): Update renamed function
- calls to renamed functions.
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
- * config/aarch64/t-aarch64 (aarch-bti-insert.o): Update
- target.
- * config/aarch64/aarch64-bti-insert.cc: Delete.
- * config/arm/aarch-bti-insert.cc: New file including and
- generalizing code from aarch64-bti-insert.cc.
- * config/arm/aarch-common-protos.h: Update.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
-
- * config/arm/arm.h (arm_arch8m_main): Declare it.
- * config/arm/arm-protos.h (arm_current_function_pac_enabled_p):
- Declare it.
- * config/arm/arm.cc (arm_arch8m_main): Define it.
- (arm_option_reconfigure_globals): Set arm_arch8m_main.
- (arm_compute_frame_layout, arm_expand_prologue)
- (thumb2_expand_return, arm_expand_epilogue)
- (arm_conditional_register_usage): Update for pac codegen.
- (arm_current_function_pac_enabled_p): New function.
- (aarch_bti_enabled) New function.
- (use_return_insn): Return zero when pac is enabled.
- * config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp):
- Add new patterns.
- * config/arm/unspecs.md (UNSPEC_PAC_NOP)
- (VUNSPEC_PACBTI_NOP, VUNSPEC_AUT_NOP): Add unspecs.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
-
- * config/arm/t-rmprofile: Add multilib rules for march +pacbti and
- mbranch-protection.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
- Tejas Belagod <tbelagod@arm.com>
-
- * config/arm/arm.cc (arm_file_start): Emit EABI attributes for
- Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
- Tejas Belagod <tbelagod@arm.com>
- Srinath Parvathaneni <srinath.parvathaneni@arm.com>
-
- * ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass): Introduce
- new pseudo register class _UVRSC_PAC.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
- Tejas Belagod <tbelagod@arm.com>
-
- * config/arm/arm-c.cc (arm_cpu_builtins): Define
- __ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
- __ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
- Tejas Belagod <tbelagod@arm.com>
-
- * doc/sourcebuild.texi: Document arm_pacbti_hw.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
- Tejas Belagod <tbelagod@arm.com>
- Richard Earnshaw <Richard.Earnshaw@arm.com>
-
- * config/arm/arm.cc (arm_configure_build_target): Parse and validate
- -mbranch-protection option and initialize appropriate data structures.
- * config/arm/arm.opt (-mbranch-protection): New option.
- * doc/invoke.texi (Arm Options): Document it.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
- Tejas Belagod <tbelagod@arm.com>
-
- * config/arm/arm.h (TARGET_HAVE_PACBTI): New macro.
- * config/arm/arm-cpus.in (pacbti): New feature.
- * doc/invoke.texi (Arm Options): Document it.
-
-2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
- Tejas Belagod <tbelagod@arm.com>
-
- * common/config/aarch64/aarch64-common.cc: Include aarch-common.h.
- (all_architectures): Fix comment.
- (aarch64_parse_extension): Rename return type, enum value names.
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Rename
- factored out aarch_ra_sign_scope and aarch_ra_sign_key variables.
- Also rename corresponding enum values.
- * config/aarch64/aarch64-opts.h (aarch64_function_type): Factor
- out aarch64_function_type and move it to common code as
- aarch_function_type in aarch-common.h.
- * config/aarch64/aarch64-protos.h: Include common types header,
- move out types aarch64_parse_opt_result and aarch64_key_type to
- aarch-common.h
- * config/aarch64/aarch64.cc: Move mbranch-protection parsing types
- and functions out into aarch-common.h and aarch-common.cc. Fix up
- all the name changes resulting from the move.
- * config/aarch64/aarch64.md: Fix up aarch64_ra_sign_key type name change
- and enum value.
- * config/aarch64/aarch64.opt: Include aarch-common.h to import
- type move. Fix up name changes from factoring out common code and
- data.
- * config/arm/aarch-common-protos.h: Export factored out routines to both
- backends.
- * config/arm/aarch-common.cc: Include newly factored out types.
- Move all mbranch-protection code and data structures from
- aarch64.cc.
- * config/arm/aarch-common.h: New header that declares types shared
- between aarch32 and aarch64 backends.
- * config/arm/arm-protos.h: Declare types and variables that are
- made common to aarch64 and aarch32 backends - aarch_ra_sign_key,
- aarch_ra_sign_scope and aarch_enable_bti.
- * config/arm/arm.opt (config/arm/aarch-common.h): Include header.
- (aarch_ra_sign_scope, aarch_enable_bti): Declare variable.
- * config/arm/arm.cc: Add missing includes.
-
-2023-01-23 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/install.texi (amdgcn, nvptx): Require newlib 4.3.0.
-
-2023-01-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/108449
- * cgraphunit.cc (check_global_declaration): Do not turn
- undefined statics into externs.
-
-2023-01-22 Dimitar Dimitrov <dimitar@dinux.eu>
+2024-01-11 Richard Biener <rguenther@suse.de>
- * config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Fix value for QI
- and HI input modes.
- * config/pru/pru.md (clz): Fix generated code for QI and HI
- input modes.
+ PR tree-optimization/113126
+ * match.pd ((double)float CMP (double)float -> float CMP float):
+ Make sure the boolean type is the same.
+ * fold-const.cc (fold_binary_loc): Likewise.
-2023-01-22 Cupertino Miranda <cupertino.miranda@oracle.com>
+2024-01-11 Richard Biener <rguenther@suse.de>
- * config/v850/v850.cc (v850_select_section): Put const volatile
- objects into read-only sections.
+ PR tree-optimization/112636
+ * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
+ estimate_numbers_of_iterations before querying
+ get_max_loop_iterations_int.
+ (pass_ch::execute): Initialize SCEV and loops appropriately.
-2023-01-20 Tejas Belagod <tejas.belagod@arm.com>
+2024-01-11 Georg-Johann Lay <avr@gjlay.de>
- * config/aarch64/arm_neon.h (vmull_p64, vmull_high_p64, vaeseq_u8,
- vaesdq_u8, vaesmcq_u8, vaesimcq_u8): Gate under "nothing+aes".
- (vsha1*_u32, vsha256*_u32): Gate under "nothing+sha2".
+ * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
+ Reduced Tiny.
+ * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
+ * doc/extend.texi (AVR Variable Attributes): Improve documentation
+ of io, io_low and address attributes.
+ * doc/invoke.texi (AVR Options): Add some anchors for external refs.
+ * doc/avr-mmcu.texi: Rebuild.
-2023-01-20 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/108457
- * tree-ssa-loop-niter.cc (build_cltz_expr): Use
- SCALAR_INT_TYPE_MODE (utype) directly as C[LT]Z_DEFINED_VALUE_AT_ZERO
- argument instead of a temporary. Formatting fixes.
-
-2023-01-19 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/108447
- * value-relation.cc (rr_union_table): Fix VREL_UNDEFINED row order.
- (relation_tests): Add self-tests for relation_{intersect,union}
- commutativity.
- * selftest.h (relation_tests): Declare.
- * function-tests.cc (test_ranges): Call it.
-
-2023-01-19 H.J. Lu <hjl.tools@gmail.com>
-
- PR target/108436
- * config/i386/i386-expand.cc (ix86_expand_builtin): Check
- invalid third argument to __builtin_ia32_prefetch.
-
-2023-01-19 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/108459
- * omp-expand.cc (expand_omp_for_init_counts): Use fold_build1 rather
- than fold_unary for NEGATE_EXPR.
-
-2023-01-19 Christophe Lyon <christophe.lyon@arm.com>
-
- PR target/108411
- * config/aarch64/aarch64.cc (aarch64_layout_arg): Improve
- comment. Move assert about alignment a bit later.
-
-2023-01-19 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/108440
- * tree-ssa-forwprop.cc: Include gimple-range.h.
- (simplify_rotate): For the forms with T2 wider than T and shift counts of
- Y and B - Y add & (B - 1) masking for the rotate count if Y could be equal
- to B. For the forms with T2 wider than T and shift counts of
- Y and (-Y) & (B - 1), don't punt if range could be [B, B2], but only if
- range doesn't guarantee Y < B or Y = N * B. If range doesn't guarantee
- Y < B, also add & (B - 1) masking for the rotate count. Use lazily created
- pass specific ranger instead of get_global_range_query.
- (pass_forwprop::execute): Disable that ranger at the end of pass if it has
- been created.
+2024-01-11 Yang Yujie <yangyujie@loongson.cn>
-2023-01-19 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+ PR target/113233
+ * config/loongarch/genopts/loongarch.opt.in: Mark options with
+ the "Save" property.
+ * config/loongarch/loongarch.opt: Same.
+ * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
+ according to la_target.
+ * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
+ RESTORE} for the la_target structure; Rename option conditions
+ to have the same "la_" prefix.
+ * config/loongarch/loongarch.h: Same.
- * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Use
- exact_log2 (INTVAL (operands[2])) >= 0 as condition for gating
- the pattern.
- (aarch64_simd_vec_copy_lane<mode>): Likewise.
- (aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.
+2024-01-11 Pan Li <pan2.li@intel.com>
-2023-01-19 Alexandre Oliva <oliva@adacore.com>
+ * loop-unroll.cc (insert_var_expansion_initialization): Leverage
+ MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
- PR debug/106746
- * sched-deps.cc (sched_analyze_2): Skip cselib address lookup
- within debug insns.
+2024-01-11 Alex Coplan <alex.coplan@arm.com>
-2023-01-18 Martin Jambor <mjambor@suse.cz>
+ PR target/113077
+ * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
+ fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
+ (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
+ synthesize these if needed. Update caller ...
+ (ldp_bb_info::fuse_pair): ... here.
+ (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
+ and either insn is frame-related.
+ (find_trailing_add): Punt on frame-related insns.
+ * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
+ REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
- PR ipa/107944
- * cgraph.cc (cgraph_node::remove): Check whether nodes up the
- lcone_of chain also do not need the body.
+2024-01-11 YunQiang Su <syq@gcc.gnu.org>
-2023-01-18 Richard Biener <rguenther@suse.de>
+ * config/mips/mips.cc (mips_start_function_definition):
+ Add ATTRIBUTE_UNUSED.
- Revert:
- 2022-12-16 Richard Biener <rguenther@suse.de>
-
- PR middle-end/108086
- * tree-inline.cc (remap_ssa_name): Do not unshare the
- result from the decl_map.
-
-2023-01-18 Murray Steele <murray.steele@arm.com>
-
- PR target/108442
- * config/arm/arm_mve.h (__arm_vst1q_p_u8): Use prefixed intrinsic
- function.
- (__arm_vst1q_p_s8): Likewise.
- (__arm_vld1q_z_u8): Likewise.
- (__arm_vld1q_z_s8): Likewise.
- (__arm_vst1q_p_u16): Likewise.
- (__arm_vst1q_p_s16): Likewise.
- (__arm_vld1q_z_u16): Likewise.
- (__arm_vld1q_z_s16): Likewise.
- (__arm_vst1q_p_u32): Likewise.
- (__arm_vst1q_p_s32): Likewise.
- (__arm_vld1q_z_u32): Likewise.
- (__arm_vld1q_z_s32): Likewise.
- (__arm_vld1q_z_f16): Likewise.
- (__arm_vst1q_p_f16): Likewise.
- (__arm_vld1q_z_f32): Likewise.
- (__arm_vst1q_p_f32): Likewise.
+2024-01-11 Richard Biener <rguenther@suse.de>
-2023-01-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ PR middle-end/112740
+ * expr.cc (store_constructor): Check the integer vector
+ mask has a single bit per element before using sign-extension
+ to expand an uniform vector.
- * config/xtensa/xtensa.md (xorsi3_internal):
- Rename from the original of "xorsi3".
- (xorsi3): New expansion pattern that emits addition rather than
- bitwise-XOR when the second source is a constant of -2147483648
- if TARGET_DENSITY.
+2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-01-18 Kewen Lin <linkw@linux.ibm.com>
- Andrew Pinski <apinski@marvell.com>
+ * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
+ preempt VLS on unknown NITERS loop.
- PR target/108396
- * config/rs6000/rs6000-overload.def (VEC_VSUBCUQ): Fix typo
- vec_vsubcuqP with vec_vsubcuq.
+2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
-2023-01-18 Kewen Lin <linkw@linux.ibm.com>
+ * doc/invoke.texi: Add -mevex512.
- PR target/108348
- * config/rs6000/rs6000.cc (rs6000_opaque_type_invalid_use_p): Add the
- support for invalid uses of MMA opaque type in function arguments.
+2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
-2023-01-18 liuhongt <hongtao.liu@intel.com>
+ * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
+ (*nor<mode>3): Likewise.
+ (nor<mode>3): Likewise.
+ (*negsi2_extended): New template.
+ (*<optab>si3_internal): Likewise.
+ (*one_cmplsi2_internal): Likewise.
+ (*norsi3_internal): Likewise.
+ (*<optab>nsi_internal): Likewise.
+ (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
+ modified bit operation to make the optimization work.
- PR target/55522
- * config/i386/cygwin.h (ENDFILE_SPEC): Link crtfastmath.o
- whenever -mdaz-ftz is specified. Don't link crtfastmath.o when
- -share or -mno-daz-ftz is specified.
- * config/i386/darwin.h (ENDFILE_SPEC): Ditto.
- * config/i386/mingw32.h (ENDFILE_SPEC): Ditto.
+2024-01-11 liuhongt <hongtao.liu@intel.com>
-2023-01-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+ PR target/104401
+ * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
- * config/bpf/bpf.cc (bpf_option_override): Disable
- -fstack-protector.
+2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-2023-01-17 Jakub Jelinek <jakub@redhat.com>
+ * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
+ (get_vector_costs): Ditto.
+ (riscv_builtin_vectorization_cost): Ditto.
- PR tree-optimization/106523
- * tree-ssa-forwprop.cc (simplify_rotate): For the
- patterns with (-Y) & (B - 1) in one operand's shift
- count and Y in another, if T2 has wider precision than T,
- punt if Y could have a value in [B, B2 - 1] range.
+2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
+
+2024-01-10 Antoni Boucher <bouanto@zoho.com>
+
+ PR jit/111396
+ * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
+ ipa_free_size_summary.
+ * ipa-icf.cc (ipa_icf_cc_finalize): New function.
+ * ipa-profile.cc (ipa_profile_cc_finalize): New function.
+ * ipa-prop.cc (ipa_prop_cc_finalize): New function.
+ * ipa-prop.h (ipa_prop_cc_finalize): New function.
+ * ipa-sra.cc (ipa_sra_cc_finalize): New function.
+ * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
+ ipa_sra_cc_finalize): New functions.
+ * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
+ ipa_prop_cc_finalize, ipa_profile_cc_finalize and
+ ipa_sra_cc_finalize
+ Include ipa-utils.h.
+
+2024-01-10 Jin Ma <jinma@linux.alibaba.com>
+
+ * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
+ (th_int_get_save_adjustment): Likewise.
+ (th_int_adjust_cfi_prologue): Likewise.
+ * config/riscv/riscv.cc (BITSET_P): Moved away from here.
+ (TH_INT_INTERRUPT): New macro.
+ (riscv_expand_prologue): Add the processing of XTheadInt.
+ (riscv_expand_epilogue): Likewise.
+ * config/riscv/riscv.h (BITSET_P): Moved to here.
+ * config/riscv/riscv.md: New unspec.
+ * config/riscv/thead.cc (th_int_get_mask): New function.
+ (th_int_get_save_adjustment): Likewise.
+ (th_int_adjust_cfi_prologue): Likewise.
+ * config/riscv/thead.md (th_int_push): New pattern.
+ (th_int_pop): new pattern.
+
+2024-01-10 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/112468
+ * doc/sourcebuild.texi: Document ifn_copysign.
+ * match.pd: Only apply transformation if target supports the IFN.
+
+2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
+
+ PR tree-optimization/112581
+ * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
+ mark_ssa_maybe_undefs.
+ * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
+ variables can not be reassociated.
+ (init_range_entry): Check for uninitialized variables too.
+ (init_reassoc): Call mark_ssa_maybe_undefs.
+
+2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
+
+ * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
+ Also handle sign extension.
+
+2024-01-10 Alex Coplan <alex.coplan@arm.com>
+
+ * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
+ to 0.
+ (-mlate-ldp-fusion): Likewise.
+
+2024-01-10 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/113287
+ * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
+ instead of using BRANCH_EDGE to determine true edge.
+
+2024-01-10 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/113078
+ * tree-vect-loop.cc (check_reduction_path): Canonicalize
+ .COND_SUB to .COND_ADD.
+
+2024-01-10 David Malcolm <dmalcolm@redhat.com>
+
+ * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
+ Handle prefix mappings before calling find_opt.
+ (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
+ "-fno-"-prefixed command-line option.
+ * opts-common.cc (get_option_prefix_remapping): New.
+ * opts.h (get_option_prefix_remapping): New decl.
+
+2024-01-10 David Malcolm <dmalcolm@redhat.com>
+
+ * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
+ m_urlifier to pp_output_formatted_text.
+ * pretty-print.cc: Add #define of INCLUDE_VECTOR.
+ (obstack_append_string): New overload, taking a length.
+ (urlify_quoted_string): Pass in an obstack ptr, rather than using
+ that of the pp's buffer. Generalize to handle trailing text in
+ the buffer beyond the run of quoted text.
+ (class quoting_info): New.
+ (on_begin_quote): New.
+ (on_end_quote): New.
+ (pp_format): Refactor phase 1 and phase 2 quoting support, moving
+ it to calls to on_begin_quote and on_end_quote.
+ (struct auto_obstack): New.
+ (quoting_info::handle_phase_3): New.
+ (pp_output_formatted_text): Add urlifier param. Use it if there
+ is deferred urlification. Delete m_quotes.
+ (selftest::pp_printf_with_urlifier): Pass urlifier to
+ pp_output_formatted_text.
+ (selftest::test_urlification): Update results for the existing
+ case of quoted text stradding chunks; add more such test cases.
+ * pretty-print.h (class quoting_info): New forward decl.
+ (chunk_info::m_quotes): New field.
+ (pp_output_formatted_text): Add optional urlifier param.
+
+2024-01-10 David Malcolm <dmalcolm@redhat.com>
+
+ * pretty-print.cc (selftest::test_pp_format): Add selftest
+ coverage for numbered args.
+
+2024-01-10 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/113144
+ PR tree-optimization/113145
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Update all BB that the original exits dominated.
-2023-01-16 H.J. Lu <hjl.tools@gmail.com>
+2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
- PR target/105980
- * config/i386/i386.cc (x86_output_mi_thunk): Disable
- -mforce-indirect-call for PIC in 32-bit mode.
+ * dwarf2out.cc (modified_type_die): Extend the support of reverse
+ storage order to enumeration types if -gstrict-dwarf is not passed.
+ (gen_enumeration_type_die): Add REVERSE parameter and generate the
+ DIE immediately after the existing one if it is true.
+ (gen_tagged_type_die): Add REVERSE parameter and pass it in the
+ call to gen_enumeration_type_die.
+ (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
+ first recursive call as well as the call to gen_tagged_type_die.
+ (gen_type_die): Add REVERSE parameter and pass it in the call to
+ gen_type_die_with_usage.
-2023-01-16 Jan Hubicka <hubicka@ucw.cz>
+2024-01-10 Jakub Jelinek <jakub@redhat.com>
- PR ipa/106077
- * ipa-modref.cc (modref_access_analysis::analyze): Use
- find_always_executed_bbs.
- * ipa-sra.cc (process_scan_results): Likewise.
- * ipa-utils.cc (stmt_may_terminate_function_p): New function.
- (find_always_executed_bbs): New function.
- * ipa-utils.h (stmt_may_terminate_function_p): Declare.
- (find_always_executed_bbs): Declare.
+ PR tree-optimization/113120
+ * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
+ with root->size TYPE_PRECISION don't build anything new.
+ Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
+ rather than build_nonstandard_integer_type.
-2023-01-16 Jan Hubicka <jh@suse.cz>
+2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
- * config/i386/i386.cc (ix86_vectorize_builtin_scatter): Guard scatter
- by TARGET_USE_SCATTER.
- * config/i386/i386.h (TARGET_USE_SCATTER_2PARTS,
- TARGET_USE_SCATTER_4PARTS, TARGET_USE_SCATTER): New macros.
- * config/i386/x86-tune.def (TARGET_USE_SCATTER_2PARTS,
- TARGET_USE_SCATTER_4PARTS, TARGET_USE_SCATTER): New tunes.
- (X86_TUNE_AVOID_256FMA_CHAINS, X86_TUNE_AVOID_512FMA_CHAINS): Disable
- for znver4. (X86_TUNE_USE_GATHER): Disable for zen4.
+ * config/i386/i386.opt: Adjust document.
+ * doc/invoke.texi: Add description for
+ -mapx-inline-asm-use-gpr32.
-2023-01-16 Richard Biener <rguenther@suse.de>
+2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR target/55522
- * config/sol2.h (ENDFILE_SPEC): Don't add crtfastmath.o for -shared.
+ * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
+ (avg<v_double_trunc>3_floor): New pattern.
+ (<u>avg<v_double_trunc>3_ceil): Remove.
+ (avg<v_double_trunc>3_ceil): New pattern.
+ (uavg<mode>3_floor): Ditto.
+ (uavg<mode>3_ceil): Ditto.
+ * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
+ (enum insn_type): Ditto.
+ * config/riscv/riscv-v.cc: Ditto.
+ * config/riscv/vector-iterators.md (ashiftrt): Remove.
+ (ASHIFTRT): Ditto.
+ * config/riscv/vector.md: Add VLS modes.
-2023-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
+2024-01-10 Kewen Lin <linkw@linux.ibm.com>
- PR target/96795
- PR target/107515
- * config/arm/arm_mve.h (__ARM_mve_coerce2): Split types.
- (__ARM_mve_coerce3): Likewise.
+ PR target/111480
+ * config/rs6000/vsx.md (VCZLSBB): New int iterator.
+ (vczlsbb_char): New int attribute.
+ (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
+ (vc<vczlsbb_char>zlsbb_<mode>): ... this.
+ (*vctzlsbb_zext_<mode>): Rename to ...
+ (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
+ cover vclzlsbb.
-2023-01-16 Andrew Carlotti <andrew.carlotti@arm.com>
+2024-01-10 Kewen Lin <linkw@linux.ibm.com>
- * tree-ssa-loop-niter.cc (build_popcount_expr): Add IFN support.
+ PR target/112606
+ * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
+ of the last argument from altivec_register_operand to any_operand. If
+ operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
+ otherwise if it doesn't satisfy altivec_register_operand, force it to
+ REG using copy_to_mode_reg.
-2023-01-16 Andrew Carlotti <andrew.carlotti@arm.com>
+2024-01-10 Kewen Lin <linkw@linux.ibm.com>
- * tree-ssa-loop-niter.cc (number_of_iterations_cltz): New.
- (number_of_iterations_bitcount): Add call to the above.
- (number_of_iterations_exit_assumptions): Add EQ_EXPR case for
- c[lt]z idiom recognition.
+ PR middle-end/113100
+ * builtins.cc (expand_builtin_stack_address): Guard stack point
+ adjustment with SPARC_STACK_BOUNDARY_HACK.
-2023-01-16 Andrew Carlotti <andrew.carlotti@arm.com>
+2024-01-10 Yang Yujie <yangyujie@loongson.cn>
- * doc/sourcebuild.texi: Add missing target attributes.
+ * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
+ argument string definitions.
+ * config/loongarch/loongarch-str.h: Same.
+ * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
+ as aliases to -mexplicit-relocs={always,none}
+ * config/loongarch/loongarch.opt: Regenerate.
+ * config/loongarch/loongarch.cc: Same.
+
+2024-01-10 Yang Yujie <yangyujie@loongson.cn>
+
+ * config/loongarch/loongarch-def.h: Define constants with
+ enums instead of Macros.
+
+2024-01-10 Yang Yujie <yangyujie@loongson.cn>
+
+ * config/loongarch/genopts/loongarch-strings: Rename.
+ * config/loongarch/genopts/loongarch.opt.in: Same.
+ * config/loongarch/loongarch-cpu.cc: Same.
+ * config/loongarch/loongarch-def.cc: Same.
+ * config/loongarch/loongarch-def.h: Same.
+ * config/loongarch/loongarch-opts.cc: Same.
+ * config/loongarch/loongarch-opts.h: Same.
+ * config/loongarch/loongarch-str.h: Same.
+ * config/loongarch/loongarch.opt: Same.
+
+2024-01-10 Yang Yujie <yangyujie@loongson.cn>
+
+ * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
+ variable with the common la_ prefix.
+ * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
+ flags as saved using TargetVariable.
+ * config/loongarch/loongarch.opt: Same.
+ * config/loongarch/loongarch-def.h: Define evolution_set to
+ mark changes to the -march default.
+ * config/loongarch/loongarch-driver.cc: Same.
+ * config/loongarch/loongarch-opts.cc: Same.
+ * config/loongarch/loongarch-opts.h: Define and use ISA evolution
+ conditions around the la_target structure.
+ * config/loongarch/loongarch.cc: Same.
+ * config/loongarch/loongarch.md: Same.
+ * config/loongarch/loongarch-builtins.cc: Same.
+ * config/loongarch/loongarch-c.cc: Same.
+ * config/loongarch/lasx.md: Same.
+ * config/loongarch/lsx.md: Same.
+ * config/loongarch/sync.md: Same.
-2023-01-16 Andrew Carlotti <andrew.carlotti@arm.com>
+2024-01-09 Jeff Law <jlaw@ventanamicro.com>
- PR tree-optimization/94793
- * tree-scalar-evolution.cc (expression_expensive_p): Add checks
- for c[lt]z optabs.
- * tree-ssa-loop-niter.cc (build_cltz_expr): New.
- (number_of_iterations_cltz_complement): New.
- (number_of_iterations_bitcount): Add call to the above.
+ * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
+ no less.
-2023-01-16 Jonathan Wakely <jwakely@redhat.com>
+2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
- * doc/extend.texi (Common Function Attributes): Fix grammar.
+ * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
-2023-01-16 Jakub Jelinek <jakub@redhat.com>
+2024-01-09 Tamar Christina <tamar.christina@arm.com>
- PR other/108413
- * config/riscv/riscv-vsetvl.h: Add space in between Copyright and (C).
- * config/riscv/riscv-vsetvl.cc: Likewise.
+ * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
+ restart_loop.
+ (vectorizable_live_operation): Likewise.
-2023-01-16 Jakub Jelinek <jakub@redhat.com>
+2024-01-09 Tamar Christina <tamar.christina@arm.com>
- PR c++/105593
- * config/i386/xmmintrin.h (_mm_undefined_ps): Temporarily
- disable -Winit-self using pragma GCC diagnostic ignored.
- * config/i386/emmintrin.h (_mm_undefined_pd, _mm_undefined_si128):
- Likewise.
- * config/i386/avxintrin.h (_mm256_undefined_pd, _mm256_undefined_ps,
- _mm256_undefined_si256): Likewise.
- * config/i386/avx512fintrin.h (_mm512_undefined_pd,
- _mm512_undefined_ps, _mm512_undefined_epi32): Likewise.
- * config/i386/avx512fp16intrin.h (_mm_undefined_ph,
- _mm256_undefined_ph, _mm512_undefined_ph): Likewise.
+ PR tree-optimization/113199
+ * tree-vect-loop.cc (vectorizable_live_operation_1): Use
+ BIT_FIELD_REF.
-2023-01-16 Kewen Lin <linkw@linux.ibm.com>
+2024-01-09 Jakub Jelinek <jakub@redhat.com>
- PR target/108272
- * config/rs6000/rs6000.cc (rs6000_opaque_type_invalid_use_p): Add the
- support for invalid uses in inline asm, factor out the checking and
- erroring to lambda function check_and_error_invalid_use.
+ PR target/113270
+ * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
+ * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
+ GTY(()) declaration before the definition, drop GTY(()) drom the
+ definition.
-2023-01-15 Aldy Hernandez <aldyh@redhat.com>
+2024-01-09 Richard Biener <rguenther@suse.de>
- PR tree-optimization/107608
- * range-op-float.cc (range_operator_float::fold_range): Avoid
- folding into INF when flag_trapping_math.
- * value-range.h (frange::known_isinf): Return false for possible NANs.
+ PR tree-optimization/113026
+ * tree-vect-loop-manip.cc (vect_do_peeling): Remove
+ redundant and wrong niter bound setting. Move niter
+ bound adjustment down.
-2023-01-15 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+2024-01-09 Tamar Christina <tamar.christina@arm.com>
- * config.gcc (csky-*-*): Support --with-float=softfp.
+ PR middle-end/113163
+ * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
+ Reject non-linear inductions that aren't supported.
-2023-01-14 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
- * config/xtensa/xtensa-protos.h (order_regs_for_local_alloc):
- Rename to xtensa_adjust_reg_alloc_order.
- * config/xtensa/xtensa.cc (xtensa_adjust_reg_alloc_order):
- Ditto. And also remove code to reorder register numbers for
- leaf functions, rename the tables, and adjust the allocation
- order for the call0 ABI to use register A0 more.
- (xtensa_leaf_regs): Remove.
- * config/xtensa/xtensa.h (REG_ALLOC_ORDER): Cosmetics.
- (order_regs_for_local_alloc): Rename as the above.
- (LEAF_REGISTERS, LEAF_REG_REMAP, leaf_function): Remove.
+ * config/arc/arc.cc (arc_shift_alg): New enumerated type for
+ left shift implementation strategies.
+ (arc_shift_info): Type for each entry of the shift strategy table.
+ (arc_shift_context_idx): Return a integer value for each code
+ generation context, used as an index
+ (arc_ashl_alg): Table indexed by context and shifted bit count.
+ (arc_split_ashl): Use the arc_ashl_alg table to select SImode
+ left shift implementation.
+ (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
+ provide accurate costs, when optimizing for speed or size.
-2023-01-14 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * config/aarch64/aarch64-sve.md (aarch64_vec_duplicate_vq<mode>_le):
- Change to define_insn_and_split to fold ldr+dup to ld1rq.
- * config/aarch64/predicates.md (aarch64_sve_dup_ld1rq_operand): New.
+ * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
-2023-01-14 Alexandre Oliva <oliva@adacore.com>
+2024-01-09 Julian Brown <julian@codesourcery.com>
- * hash-table.h (is_deleted): Precheck !is_empty.
- (mark_deleted): Postcheck !is_empty.
- (copy constructor): Test is_empty before is_deleted.
+ * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
+ processed out before gimplification.
+ * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
+ * tree.def (OMP_ARRAY_SECTION): New tree code.
-2023-01-14 Alexandre Oliva <oliva@adacore.com>
+2024-01-09 Jakub Jelinek <jakub@redhat.com>
- PR target/40457
- * config/arm/arm.md (movmisaligndi): Prefer aligned SImode
- moves.
+ PR tree-optimization/113210
+ * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
+ value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
+ INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
+ minus 1.
-2023-01-13 Eric Botcazou <ebotcazou@adacore.com>
+2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
- PR rtl-optimization/108274
- * function.cc (thread_prologue_and_epilogue_insns): Also update the
- DF information for calls in a few more cases.
+ PR rtl-optimization/113140
+ * reorg.cc (fill_slots_from_thread): If we are to branch after the
+ last instruction of the function, create an end label.
-2023-01-13 John David Anglin <danglin@gcc.gnu.org>
+2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
+ Hongtao Liu <hongtao.liu@intel.com>
- * config/pa/pa-linux.h (TARGET_SYNC_LIBCALL): Delete define.
- * config/pa/pa.cc (pa_init_libfuncs): Use MAX_SYNC_LIBFUNC_SIZE
- define.
- * config/pa/pa.h (TARGET_SYNC_LIBCALLS): Use flag_sync_libcalls.
- (MAX_SYNC_LIBFUNC_SIZE): Define.
- (TARGET_CPU_CPP_BUILTINS): Define __SOFTFP__ when soft float is
- enabled.
- * config/pa/pa.md (atomic_storeqi): Emit __atomic_exchange_1
- libcall when sync libcalls are disabled.
- (atomic_storehi, atomic_storesi, atomic_storedi): Likewise.
- (atomic_loaddi): Emit __atomic_load_8 libcall when sync libcalls
- are disabled on 32-bit target.
- * config/pa/pa.opt (matomic-libcalls): New option.
- * doc/invoke.texi (HPPA Options): Update.
-
-2023-01-13 Alexander Monakov <amonakov@ispras.ru>
-
- PR rtl-optimization/108117
- PR rtl-optimization/108132
- * sched-deps.cc (deps_analyze_insn): Do not schedule across
- calls before reload.
-
-2023-01-13 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
-
- * common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde
- options for -mlibarch.
- * config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options.
- * doc/invoke.texi (CDE): Document options for Cortex-M55 CPU.
-
-2023-01-13 Qing Zhao <qing.zhao@oracle.com>
-
- * attribs.cc (strict_flex_array_level_of): Move this function to ...
- * attribs.h (strict_flex_array_level_of): Remove the declaration.
- * gimple-array-bounds.cc (array_bounds_checker::check_array_ref):
- replace the referece to strict_flex_array_level_of with
- DECL_NOT_FLEXARRAY.
- * tree.cc (component_ref_size): Likewise.
-
-2023-01-13 Richard Biener <rguenther@suse.de>
-
- PR target/55522
- * config/arm/linux-eabi.h (ENDFILE_SPEC): Don't add
- crtfastmath.o for -shared.
- * config/arm/unknown-elf.h (STARTFILE_SPEC): Likewise.
-
-2023-01-13 Richard Biener <rguenther@suse.de>
-
- PR target/55522
- * config/aarch64/aarch64-elf-raw.h (ENDFILE_SPEC): Don't add
- crtfastmath.o for -shared.
- * config/aarch64/aarch64-freebsd.h (GNU_USER_TARGET_MATHFILE_SPEC):
- Likewise.
- * config/aarch64/aarch64-linux.h (GNU_USER_TARGET_MATHFILE_SPEC):
- Likewise.
+ PR target/112992
+ * config/i386/i386-expand.cc
+ (ix86_convert_const_wide_int_to_broadcast): Allow call to
+ ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
+ (ix86_broadcast_from_constant): Revert recent change; Return a
+ suitable MEMREF independently of mode/target combinations.
+ (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
+ to decide whether expansion is possible/preferrable. Only try
+ forcing DImode constants to memory (and trying again) if calling
+ ix86_expand_vector_init_duplicate fails with an DImode immediate
+ constant.
+ (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
+ V4SImode for suitable immediate constants.
+ <case E_V4DImode>: Try using V8SImode for suitable constants.
+ <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
+ <case E_V2HImode>: Likewise.
+ <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
+ <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
+ <label widen>: Handle CONT_INTs via simplify_binary_operation.
+ Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
+ <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
+ <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
+ (ix86_expand_vector_init): Move try using a broadcast for all_same
+ with ix86_expand_vector_init_duplicate before using constant pool.
+
+2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
+
+2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/arm/arm-cpus.in (cortex-m52): New cpu.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/arm-tune.md: Regenerate.
-2023-01-13 Richard Sandiford <richard.sandiford@arm.com>
+2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
- * config/aarch64/aarch64.cc (aarch64_dwarf_frame_reg_mode): New
- function.
- (TARGET_DWARF_FRAME_REG_MODE): Define.
+ * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
+ (vec_init<mode><lasxhalf>): .. this, and extend to mode.
+ (@vec_concatz<mode>): New insn pattern.
+ * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
+ Handle VALS containing two vectors.
-2023-01-13 Richard Biener <rguenther@suse.de>
+2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR target/107209
- * config/aarch64/aarch64.cc (aarch64_gimple_fold_builtin): Don't
- update EH info on the fly.
+ * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
+ (vundefined): Ditto.
-2023-01-13 Richard Biener <rguenther@suse.de>
+2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
+
+ * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
+ Add new function_base for crypto vector.
+ (class bitmanip): Ditto.
+ (class b_reverse):Ditto.
+ (class vwsll): Ditto.
+ (class clmul): Ditto.
+ (class vg_nhab): Ditto.
+ (class crypto_vv):Ditto.
+ (class crypto_vi):Ditto.
+ (class vaeskf2_vsm3c):Ditto.
+ (class vsm3me): Ditto.
+ (BASE): Add BASE declaration for crypto vector.
+ * config/riscv/riscv-vector-builtins-bases.h: Ditto.
+ * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
+ Add crypto vector intrinsic definition.
+ (vbrev): Ditto.
+ (vclz): Ditto.
+ (vctz): Ditto.
+ (vwsll): Ditto.
+ (vandn): Ditto.
+ (vbrev8): Ditto.
+ (vrev8): Ditto.
+ (vrol): Ditto.
+ (vror): Ditto.
+ (vclmul): Ditto.
+ (vclmulh): Ditto.
+ (vghsh): Ditto.
+ (vgmul): Ditto.
+ (vaesef): Ditto.
+ (vaesem): Ditto.
+ (vaesdf): Ditto.
+ (vaesdm): Ditto.
+ (vaesz): Ditto.
+ (vaeskf1): Ditto.
+ (vaeskf2): Ditto.
+ (vsha2ms): Ditto.
+ (vsha2ch): Ditto.
+ (vsha2cl): Ditto.
+ (vsm4k): Ditto.
+ (vsm4r): Ditto.
+ (vsm3me): Ditto.
+ (vsm3c): Ditto.
+ * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
+ Add new function_shape for crypto vector.
+ (struct crypto_vi_def): Ditto.
+ (struct crypto_vv_no_op_type_def): Ditto.
+ (SHAPE): Add SHAPE declaration of crypto vector.
+ * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
+ * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data type for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (vuint32mf2_t): Ditto.
+ (vuint32m1_t): Ditto.
+ (vuint32m2_t): Ditto.
+ (vuint32m4_t): Ditto.
+ (vuint32m8_t): Ditto.
+ (vuint64m1_t): Ditto.
+ (vuint64m2_t): Ditto.
+ (vuint64m4_t): Ditto.
+ (vuint64m8_t): Ditto.
+ * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data struct for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
+ * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
- PR tree-optimization/108387
- * tree-ssa-sccvn.cc (visit_nary_op): Check for SSA_NAME
- value before inserting expression into the tables.
+2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
-2023-01-12 Andrew Pinski <apinski@marvell.com>
- Roger Sayle <roger@nextmovesoftware.com>
+ PR sanitizer/113251
+ * varasm.cc (assemble_function_label_raw): Do not call
+ asan_function_start () without the current function.
- PR tree-optimization/92342
- * match.pd ((m1 CMP m2) * d -> (m1 CMP m2) ? d : 0):
- Use tcc_comparison and :c for the multiply.
- (b & -(a CMP c) -> (a CMP c)?b:0): New pattern.
+2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
-2023-01-12 Christophe Lyon <christophe.lyon@arm.com>
- Richard Sandiford <richard.sandiford@arm.com>
+ PR target/113225
+ * btfout.cc (btf_collect_datasec): Skip creating BTF info for
+ extern and kernel_helper attributed function decls.
- PR target/105549
- * config/aarch64/aarch64.cc (aarch64_function_arg_alignment):
- Check DECL_PACKED for bitfield.
- (aarch64_layout_arg): Warn when parameter passing ABI changes.
- (aarch64_function_arg_boundary): Do not warn here.
- (aarch64_gimplify_va_arg_expr): Warn when parameter passing ABI
- changes.
+2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
-2023-01-12 Christophe Lyon <christophe.lyon@arm.com>
- Richard Sandiford <richard.sandiford@arm.com>
+ * btfout.cc (output_btf_strs): Changed.
- * config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Fix
- comment.
- (aarch64_layout_arg): Factorize warning conditions.
- (aarch64_function_arg_boundary): Fix typo.
- * function.cc (currently_expanding_function_start): New variable.
- (expand_function_start): Handle
- currently_expanding_function_start.
- * function.h (currently_expanding_function_start): Declare.
+2024-01-08 Tobias Burnus <tobias@codesourcery.com>
-2023-01-12 Richard Biener <rguenther@suse.de>
+ * config/gcn/mkoffload.cc (main): Handle gfx1100
+ when setting the default XNACK.
- PR tree-optimization/99412
- * tree-ssa-reassoc.cc (is_phi_for_stmt): Remove.
- (swap_ops_for_binary_stmt): Remove reduction handling.
- (rewrite_expr_tree_parallel): Adjust.
- (reassociate_bb): Likewise.
- * tree-parloops.cc (build_new_reduction): Handle MINUS_EXPR.
+2024-01-08 Tobias Burnus <tobias@codesourcery.com>
-2023-01-12 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
+ * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
+ (ASM_SPEC): Handle gfx1100.
+ * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
+ (enum gcn_isa): Add ISA_RDNA3.
+ (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
+ * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
+ * config/gcn/gcn.cc (gcn_option_override,
+ gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
+ (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
+ TARGET_RDNA2 to TARGET_RDNA2_PLUS.
+ (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
+ with gfx1100.
+ * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
+ (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
+ __gfx1100__.
+ * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
+ * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
+ * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
+ (isa_has_combined_avgprs, main): Handle gfx1100.
+ * config/gcn/t-omp-device (isa): Add gfx1100.
- * config/xtensa/xtensa.md (ctzsi2, ffssi2):
- Rearrange the emitting codes.
+2024-01-08 Richard Biener <rguenther@suse.de>
-2023-01-12 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ * doc/invoke.texi (-mmovbe): Clarify.
- * config/xtensa/xtensa.md (*btrue):
- Correct value of the attribute "length" that depends on
- TARGET_DENSITY and operands, and add '?' character to the register
- constraint of the compared operand.
+2024-01-08 Richard Biener <rguenther@suse.de>
-2023-01-12 Alexandre Oliva <oliva@adacore.com>
+ PR tree-optimization/113026
+ * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
+ Avoid an epilog in more cases.
+ * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
+ epilogues niter upper bounds and estimates.
- * hash-table.h (expand): Check elements and deleted counts.
- (verify): Likewise.
+2024-01-08 Jakub Jelinek <jakub@redhat.com>
-2023-01-11 Roger Sayle <roger@nextmovesoftware.com>
+ PR tree-optimization/113228
+ * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
- PR tree-optimization/71343
- * tree-ssa-sccvn.cc (visit_nary_op) <case LSHIFT_EXPR>: Make
- the value number of the expression X << C the same as the value
- number for the multiplication X * (1<<C).
-
-2023-01-11 David Faust <david.faust@oracle.com>
-
- PR target/108293
- * config/bpf/bpf.cc (bpf_print_operand): Correct handling for
- floating point modes.
+2024-01-08 Jakub Jelinek <jakub@redhat.com>
-2023-01-11 Eric Botcazou <ebotcazou@adacore.com>
-
- PR tree-optimization/108199
- * tree-sra.cc (sra_modify_expr): Deal with reverse storage order
- for bit-field references.
+ PR tree-optimization/113120
+ * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
+ large _BitInt zero INTEGER_CST PHI argument.
-2023-01-11 Kewen Lin <linkw@linux.ibm.com>
+2024-01-08 Jakub Jelinek <jakub@redhat.com>
- * config/rs6000/rs6000.cc (rs6000_option_override_internal): Make
- OPTION_MASK_P10_FUSION implicit setting honour Power10 tuning setting.
- * config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Remove
- OPTION_MASK_P10_FUSION.
+ PR tree-optimization/113119
+ * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
+ both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
+ is before REALPART_EXPR.
-2023-01-11 Richard Biener <rguenther@suse.de>
+2024-01-08 Georg-Johann Lay <avr@gjlay.de>
- PR tree-optimization/107767
- * tree-cfgcleanup.cc (phi_alternatives_equal): Export.
- * tree-cfgcleanup.h (phi_alternatives_equal): Declare.
- * tree-switch-conversion.cc (switch_conversion::collect):
- Count unique non-default targets accounting for later
- merging opportunities.
+ PR target/112952
+ * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
+ range when diagnosing attribute "io" and "io_low" are out of range.
+ (avr_eval_addr_attrib): Don't ICE on empty address at that place.
+ (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
+ in contexts other than static storage.
+ (avr_asm_output_aligned_decl_common): Move output of decls with
+ attribute "address", "io", and "io_low" to...
+ (avr_output_addr_attrib): ...this new function.
+ (avr_asm_asm_output_aligned_bss): Remove output for decls with
+ attribute "address", "io", and "io_low".
+ (avr_encode_section_info): Rectify handling of decls with attribute
+ "address", "io", and "io_low".
-2023-01-11 Martin Liska <mliska@suse.cz>
+2024-01-08 Andrew Stubbs <ams@codesourcery.com>
- PR middle-end/107976
- * params.opt: Limit JT params.
- * stmt.cc (emit_case_dispatch_table): Use auto_vec.
+ * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
+ (elf_flags): Remove XNACK from the default value.
+ (main): Set a default XNACK according to the arch.
-2023-01-11 Richard Biener <rguenther@suse.de>
+2024-01-08 Andrew Stubbs <ams@codesourcery.com>
- PR tree-optimization/108352
- * tree-ssa-threadbackward.cc
- (back_threader_profitability::profitable_path_p): Adjust
- heuristic that allows non-multi-way branch threads creating
- irreducible loops.
- * doc/invoke.texi (--param fsm-scale-path-blocks): Remove.
- (--param fsm-scale-path-stmts): Adjust.
- * params.opt (--param=fsm-scale-path-blocks=): Remove.
- (-param=fsm-scale-path-stmts=): Adjust description.
+ * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
+ (process_asm): Don't count avgprs.
-2023-01-11 Richard Biener <rguenther@suse.de>
+2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
- PR tree-optimization/108353
- * tree-ssa-propagate.cc (cfg_blocks_back, ssa_edge_worklist_back):
- Remove.
- (add_ssa_edge): Simplify.
- (add_control_edge): Likewise.
- (ssa_prop_init): Likewise.
- (ssa_prop_fini): Likewise.
- (ssa_propagation_engine::ssa_propagate): Likewise.
+ * config/i386/i386.opt: Add supported sub-features.
+ * doc/extend.texi: Add description for target attribute.
-2023-01-11 Andreas Krebbel <krebbel@linux.ibm.com>
+2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
- * config/s390/s390.md (*not<mode>): New pattern.
+ * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
-2023-01-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
+ Uros Bizjak <ubizjak@gmail.com>
- * config/xtensa/xtensa.cc (xtensa_insn_cost):
- Let insn cost for size be obtained by applying COSTS_N_INSNS()
- to instruction length and then dividing by 3.
+ PR target/113231
+ * config/i386/i386-features.cc (compute_convert_gain): Include
+ the overhead of explicit load and store (movd) instructions when
+ converting non-store scalar operations with memory destinations.
+ Various indentation whitespace fixes.
-2023-01-10 Richard Biener <rguenther@suse.de>
+2024-01-07 Tamar Christina <tamar.christina@arm.com>
- PR tree-optimization/106293
- * tree-ssa-dse.cc (dse_classify_store): Use a worklist to
- process degenerate PHI defs.
+ * config/arm/neon.md (cbranch<mode>4): New.
-2023-01-10 Roger Sayle <roger@nextmovesoftware.com>
+2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR rtl-optimization/106421
- * cprop.cc (bypass_block): Check that DEST is local to this
- function (non-NULL) before calling find_edge.
+ * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
-2023-01-10 Martin Jambor <mjambor@suse.cz>
+2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
- PR ipa/108110
- * ipa-param-manipulation.h (ipa_param_body_adjustments): New members
- sort_replacements, lookup_first_base_replacement and
- m_sorted_replacements_p.
- * ipa-param-manipulation.cc: Define INCLUDE_ALGORITHM.
- (ipa_param_body_adjustments::register_replacement): Set
- m_sorted_replacements_p to false.
- (compare_param_body_replacement): New function.
- (ipa_param_body_adjustments::sort_replacements): Likewise.
- (ipa_param_body_adjustments::common_initialization): Call
- sort_replacements.
- (ipa_param_body_adjustments::ipa_param_body_adjustments): Initialize
- m_sorted_replacements_p.
- (ipa_param_body_adjustments::lookup_replacement_1): Rework to use
- std::lower_bound.
- (ipa_param_body_adjustments::lookup_first_base_replacement): New
- function.
- (ipa_param_body_adjustments::modify_call_stmt): Use
- lookup_first_base_replacement.
- * omp-simd-clone.cc (ipa_simd_modify_function_body): Call
- adjustments->sort_replacements.
+ * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
-2023-01-10 Richard Biener <rguenther@suse.de>
+2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR tree-optimization/108314
- * tree-vect-stmts.cc (vectorizable_condition): Do not
- perform BIT_NOT_EXPR optimization for EXTRACT_LAST_REDUCTION.
+ PR target/113248
+ * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
+ Update the MAX_SEW.
-2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * config/csky/csky-linux-elf.h (SYSROOT_SUFFIX_SPEC): New.
+ * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
+ (variable_vectorized_p): Teach loop invariant.
+ (has_unexpected_spills_p): Ditto.
-2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * config/csky/csky.h (MULTILIB_DEFAULTS): Fix float abi option.
+ * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
+ * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
+ * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
-2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
- * config/csky/csky.cc (csky_cpu_cpp_builtins): Add builtin
- defines for soft float abi.
+ PR target/113104
+ * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
+ (aarch64-vect-compare-costs): ...this.
+ * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
+ Replace with...
+ (-param=aarch64-vect-compare-costs=): ...this new param.
+ * config/aarch64/aarch64.cc (aarch64_override_options_internal):
+ Don't disable it when vectorizing for Advanced SIMD only.
+ (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
+ whenever aarch64_vect_compare_costs is true.
+
+2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
+ Modify the method of determining the memory offset of [x]vld/[x]vst.
+ (lasx_mxst_<lasxfmt_f>): Likewise.
+ * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
+ (loongarch_address_insns): Likewise.
+ * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
+ (lsx_st_<lsxfmt_f>): Likewise.
+ * config/loongarch/predicates.md (aq10b_operand): Likewise.
+ (aq10h_operand): Likewise.
+ (aq10w_operand): Likewise.
+ (aq10d_operand): Likewise.
+
+2024-01-05 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113217
+ * config/aarch64/aarch64-ldp-fusion.cc
+ (ldp_bb_info::try_fuse_pair): If the second access can throw,
+ narrow the move range to exactly that insn.
+
+2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * asan.cc (asan_function_start): Drop switch_to_section ().
+ (asan_emit_stack_protection): Set .LASANPC alignment.
+ * config/i386/i386.cc: Use assemble_function_label_raw ()
+ instead of ASM_OUTPUT_LABEL ().
+ * config/s390/s390.cc (s390_asm_output_function_label):
+ Likewise.
+ * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
+ * final.cc (final_start_function_1): Drop
+ asan_function_start ().
+ * output.h (assemble_function_label_raw): New function.
+ * varasm.cc (assemble_function_label_raw): Likewise.
+
+2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * config/aarch64/aarch64.cc (aarch64_declare_function_name):
+ Use ASM_OUTPUT_FUNCTION_LABEL ().
+ * config/alpha/alpha.cc (alpha_start_function): Likewise.
+ * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
+ * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
+ * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
+ * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
+ * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
+ * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
+ * config/ia64/ia64.cc (ia64_start_function): Likewise.
+ * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
+ Likewise.
+ * config/microblaze/microblaze.cc (microblaze_function_prologue):
+ Likewise.
+ * config/mips/mips.cc (mips_start_unique_function): Return the
+ tree.
+ (mips_start_function_definition): Use
+ ASM_OUTPUT_FUNCTION_LABEL ().
+ (mips_finish_stub): Pass the tree to
+ mips_start_function_definition ().
+ (mips16_build_function_stub): Likewise.
+ (mips16_build_call_stub): Likewise.
+ (mips_output_function_prologue): Likewise.
+ * config/pa/pa.cc (pa_output_function_label): Use
+ ASM_OUTPUT_FUNCTION_LABEL ().
+ * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
+ * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
+ Likewise.
+ (rs6000_xcoff_declare_function_name): Likewise.
-2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+2024-01-05 Jakub Jelinek <jakub@redhat.com>
- * config/csky/csky.md (smart_bseti): Change condition to CSKY_ISA_FEATURE (E1).
- (smart_bclri): Likewise.
- (fast_bseti): Change condition to CSKY_ISA_FEATURE (E2).
- (fast_bclri): Likewise.
- (fast_cmpnesi_i): Likewise.
- (*fast_cmpltsi_i): Likewise.
- (*fast_cmpgeusi_i): Likewise.
+ PR tree-optimization/113201
+ * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
+ replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
-2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+2024-01-05 Jakub Jelinek <jakub@redhat.com>
- * config/csky/csky_insn_fpuv3.md (l<frm_pattern><fixsuop><mode>si2): Test
- flag_fp_int_builtin_inexact || !flag_trapping_math.
- (<frm_pattern><mode>2): Likewise.
+ PR tree-optimization/90693
+ * tree-ssa-math-opts.cc (match_single_bit_test): If
+ tree_expr_nonzero_p (arg), remember it in the second argument to
+ IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
+ arg ^ (arg - 1) > arg - 1.
+ * internal-fn.cc (expand_POPCOUNT): If second argument to
+ IFN_POPCOUNT suggests arg is non-zero, try to expand it as
+ arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
+
+2024-01-05 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/riscv-v.cc (expand_load_store):
+ Remove `value`.
+ (expand_cond_len_op): Ditto.
+ (expand_gather_scatter): Ditto.
+ (expand_lanes_load_store): Ditto.
+ (expand_fold_extract_last): Ditto.
-2023-01-10 Andreas Krebbel <krebbel@linux.ibm.com>
+2024-01-05 Pan Li <pan2.li@intel.com>
- * config/s390/s390.cc (s390_register_info): Check call_used_regs
- instead of hard-coding the register numbers for call saved
- registers.
- (s390_optimize_register_info): Likewise.
+ Revert:
+ 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
+
+ * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
+ Add new function_base for crypto vector.
+ (class bitmanip): Ditto.
+ (class b_reverse):Ditto.
+ (class vwsll): Ditto.
+ (class clmul): Ditto.
+ (class vg_nhab): Ditto.
+ (class crypto_vv):Ditto.
+ (class crypto_vi):Ditto.
+ (class vaeskf2_vsm3c):Ditto.
+ (class vsm3me): Ditto.
+ (BASE): Add BASE declaration for crypto vector.
+ * config/riscv/riscv-vector-builtins-bases.h: Ditto.
+ * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
+ Add crypto vector intrinsic definition.
+ (vbrev): Ditto.
+ (vclz): Ditto.
+ (vctz): Ditto.
+ (vwsll): Ditto.
+ (vandn): Ditto.
+ (vbrev8): Ditto.
+ (vrev8): Ditto.
+ (vrol): Ditto.
+ (vror): Ditto.
+ (vclmul): Ditto.
+ (vclmulh): Ditto.
+ (vghsh): Ditto.
+ (vgmul): Ditto.
+ (vaesef): Ditto.
+ (vaesem): Ditto.
+ (vaesdf): Ditto.
+ (vaesdm): Ditto.
+ (vaesz): Ditto.
+ (vaeskf1): Ditto.
+ (vaeskf2): Ditto.
+ (vsha2ms): Ditto.
+ (vsha2ch): Ditto.
+ (vsha2cl): Ditto.
+ (vsm4k): Ditto.
+ (vsm4r): Ditto.
+ (vsm3me): Ditto.
+ (vsm3c): Ditto.
+ * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
+ Add new function_shape for crypto vector.
+ (struct crypto_vi_def): Ditto.
+ (struct crypto_vv_no_op_type_def): Ditto.
+ (SHAPE): Add SHAPE declaration of crypto vector.
+ * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
+ * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data type for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (vuint32mf2_t): Ditto.
+ (vuint32m1_t): Ditto.
+ (vuint32m2_t): Ditto.
+ (vuint32m4_t): Ditto.
+ (vuint32m8_t): Ditto.
+ (vuint64m1_t): Ditto.
+ (vuint64m2_t): Ditto.
+ (vuint64m4_t): Ditto.
+ (vuint64m8_t): Ditto.
+ * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data struct for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
+ * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
+
+2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
+
+ * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
+ Add new function_base for crypto vector.
+ (class bitmanip): Ditto.
+ (class b_reverse):Ditto.
+ (class vwsll): Ditto.
+ (class clmul): Ditto.
+ (class vg_nhab): Ditto.
+ (class crypto_vv):Ditto.
+ (class crypto_vi):Ditto.
+ (class vaeskf2_vsm3c):Ditto.
+ (class vsm3me): Ditto.
+ (BASE): Add BASE declaration for crypto vector.
+ * config/riscv/riscv-vector-builtins-bases.h: Ditto.
+ * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
+ Add crypto vector intrinsic definition.
+ (vbrev): Ditto.
+ (vclz): Ditto.
+ (vctz): Ditto.
+ (vwsll): Ditto.
+ (vandn): Ditto.
+ (vbrev8): Ditto.
+ (vrev8): Ditto.
+ (vrol): Ditto.
+ (vror): Ditto.
+ (vclmul): Ditto.
+ (vclmulh): Ditto.
+ (vghsh): Ditto.
+ (vgmul): Ditto.
+ (vaesef): Ditto.
+ (vaesem): Ditto.
+ (vaesdf): Ditto.
+ (vaesdm): Ditto.
+ (vaesz): Ditto.
+ (vaeskf1): Ditto.
+ (vaeskf2): Ditto.
+ (vsha2ms): Ditto.
+ (vsha2ch): Ditto.
+ (vsha2cl): Ditto.
+ (vsm4k): Ditto.
+ (vsm4r): Ditto.
+ (vsm3me): Ditto.
+ (vsm3c): Ditto.
+ * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
+ Add new function_shape for crypto vector.
+ (struct crypto_vi_def): Ditto.
+ (struct crypto_vv_no_op_type_def): Ditto.
+ (SHAPE): Add SHAPE declaration of crypto vector.
+ * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
+ * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data type for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (vuint32mf2_t): Ditto.
+ (vuint32m1_t): Ditto.
+ (vuint32m2_t): Ditto.
+ (vuint32m4_t): Ditto.
+ (vuint32m8_t): Ditto.
+ (vuint64m1_t): Ditto.
+ (vuint64m2_t): Ditto.
+ (vuint64m4_t): Ditto.
+ (vuint64m8_t): Ditto.
+ * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data struct for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
+ * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
-2023-01-09 Eric Botcazou <ebotcazou@adacore.com>
+2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * doc/gm2.texi (Overview): Fix @node markers.
- (Using): Likewise. Remove subsections that were moved to Overview
- from the menu and move others around.
+ * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
-2023-01-09 Richard Biener <rguenther@suse.de>
+2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
- PR middle-end/108209
- * genmatch.cc (commutative_op): Fix return value for
- user-id with non-commutative first replacement.
+ PR tree-optimization/113186
+ * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
+ Match `^` with the `==` for 1bit integral types.
+ * match.pd (maybe_cmp): Allow for bit_xor for 1bit
+ integral types.
-2023-01-09 Jakub Jelinek <jakub@redhat.com>
+2024-01-04 David Malcolm <dmalcolm@redhat.com>
- PR target/107453
- * calls.cc (expand_call): For calls with
- TYPE_NO_NAMED_ARGS_STDARG_P (funtype) use zero for n_named_args.
- Formatting fix.
+ * toplev.cc (general_init): Pass lang_mask to urlifier.
-2023-01-09 Richard Biener <rguenther@suse.de>
+2024-01-04 David Malcolm <dmalcolm@redhat.com>
- PR middle-end/69482
- * cfgexpand.cc (discover_nonconstant_array_refs_r): Volatile
- qualified accesses also force objects to memory.
+ * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
+ param.
+ (diagnostic_context::make_option_url): Update for lang_mask param.
+ * gcc-urlifier.cc: Include "opts.h" and "options.h".
+ (gcc_urlifier::gcc_urlifier): Add lang_mask param.
+ (gcc_urlifier::m_lang_mask): New field.
+ (doc_urls): Make static.
+ (gcc_urlifier::get_url_for_quoted_text): Use label_text.
+ (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
+ Look for an option by name before trying a binary search in
+ doc_urls.
+ (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
+ (gcc_urlifier::get_url_suffix_for_option): New.
+ (make_gcc_urlifier): Add lang_mask param.
+ (selftest::gcc_urlifier_cc_tests): Update for above changes.
+ Verify that a URL is found for "-fpack-struct".
+ * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
+ * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
+ * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
+ to make_gcc_urlifier.
+ * opts-diagnostic.h (get_option_url): Add lang_mask param.
+ * opts.cc (get_option_html_page): Remove special-casing for
+ analyzer and LTO.
+ (get_option_url_suffix): New.
+ (get_option_url): Reimplement.
+ (selftest::test_get_option_html_page): Rename to...
+ (selftest::test_get_option_url_suffix): ...this and update for
+ above changes.
+ (selftest::opts_cc_tests): Update for renaming.
+ * opts.h: Include "rich-location.h".
+ (get_option_url_suffix): New decl.
+
+2024-01-04 David Malcolm <dmalcolm@redhat.com>
+
+ * Makefile.in (ALL_OPT_URL_FILES): New.
+ (GCC_OBJS): Add options-urls.o.
+ (OBJS): Likewise.
+ (OBJS-libcommon): Likewise.
+ (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
+ inputs to opt-gather.awk.
+ (options-urls.cc): New Makefile target.
+ * opt-functions.awk (url_suffix): New function.
+ (lang_url_suffix): New function.
+ * options-urls-cc-gen.awk: New file.
+ * opts.h (get_opt_url_suffix): New decl.
+
+2024-01-04 David Malcolm <dmalcolm@redhat.com>
+
+ * params.opt.urls: New file, autogenerated by
+ regenerate-opt-urls.py.
+
+2024-01-04 David Malcolm <dmalcolm@redhat.com>
+
+ * common.opt.urls: New file, autogenerated by
+ regenerate-opt-urls.py.
+ * config/aarch64/aarch64.opt.urls: Likewise.
+ * config/alpha/alpha.opt.urls: Likewise.
+ * config/alpha/elf.opt.urls: Likewise.
+ * config/arc/arc-tables.opt.urls: Likewise.
+ * config/arc/arc.opt.urls: Likewise.
+ * config/arm/arm-tables.opt.urls: Likewise.
+ * config/arm/arm.opt.urls: Likewise.
+ * config/arm/vxworks.opt.urls: Likewise.
+ * config/avr/avr.opt.urls: Likewise.
+ * config/bpf/bpf.opt.urls: Likewise.
+ * config/c6x/c6x-tables.opt.urls: Likewise.
+ * config/c6x/c6x.opt.urls: Likewise.
+ * config/cris/cris.opt.urls: Likewise.
+ * config/cris/elf.opt.urls: Likewise.
+ * config/csky/csky.opt.urls: Likewise.
+ * config/csky/csky_tables.opt.urls: Likewise.
+ * config/darwin.opt.urls: Likewise.
+ * config/dragonfly.opt.urls: Likewise.
+ * config/epiphany/epiphany.opt.urls: Likewise.
+ * config/fr30/fr30.opt.urls: Likewise.
+ * config/freebsd.opt.urls: Likewise.
+ * config/frv/frv.opt.urls: Likewise.
+ * config/ft32/ft32.opt.urls: Likewise.
+ * config/fused-madd.opt.urls: Likewise.
+ * config/g.opt.urls: Likewise.
+ * config/gcn/gcn.opt.urls: Likewise.
+ * config/gnu-user.opt.urls: Likewise.
+ * config/h8300/h8300.opt.urls: Likewise.
+ * config/hpux11.opt.urls: Likewise.
+ * config/i386/cygming.opt.urls: Likewise.
+ * config/i386/cygwin.opt.urls: Likewise.
+ * config/i386/djgpp.opt.urls: Likewise.
+ * config/i386/i386.opt.urls: Likewise.
+ * config/i386/mingw-w64.opt.urls: Likewise.
+ * config/i386/mingw.opt.urls: Likewise.
+ * config/i386/nto.opt.urls: Likewise.
+ * config/ia64/ia64.opt.urls: Likewise.
+ * config/ia64/ilp32.opt.urls: Likewise.
+ * config/ia64/vms.opt.urls: Likewise.
+ * config/iq2000/iq2000.opt.urls: Likewise.
+ * config/linux-android.opt.urls: Likewise.
+ * config/linux.opt.urls: Likewise.
+ * config/lm32/lm32.opt.urls: Likewise.
+ * config/loongarch/loongarch.opt.urls: Likewise.
+ * config/lynx.opt.urls: Likewise.
+ * config/m32c/m32c.opt.urls: Likewise.
+ * config/m32r/m32r.opt.urls: Likewise.
+ * config/m68k/ieee.opt.urls: Likewise.
+ * config/m68k/m68k-tables.opt.urls: Likewise.
+ * config/m68k/m68k.opt.urls: Likewise.
+ * config/m68k/uclinux.opt.urls: Likewise.
+ * config/mcore/mcore.opt.urls: Likewise.
+ * config/microblaze/microblaze.opt.urls: Likewise.
+ * config/mips/mips-tables.opt.urls: Likewise.
+ * config/mips/mips.opt.urls: Likewise.
+ * config/mips/sde.opt.urls: Likewise.
+ * config/mmix/mmix.opt.urls: Likewise.
+ * config/mn10300/mn10300.opt.urls: Likewise.
+ * config/moxie/moxie.opt.urls: Likewise.
+ * config/msp430/msp430.opt.urls: Likewise.
+ * config/nds32/nds32-elf.opt.urls: Likewise.
+ * config/nds32/nds32-linux.opt.urls: Likewise.
+ * config/nds32/nds32.opt.urls: Likewise.
+ * config/netbsd-elf.opt.urls: Likewise.
+ * config/netbsd.opt.urls: Likewise.
+ * config/nios2/elf.opt.urls: Likewise.
+ * config/nios2/nios2.opt.urls: Likewise.
+ * config/nvptx/nvptx-gen.opt.urls: Likewise.
+ * config/nvptx/nvptx.opt.urls: Likewise.
+ * config/openbsd.opt.urls: Likewise.
+ * config/or1k/elf.opt.urls: Likewise.
+ * config/or1k/or1k.opt.urls: Likewise.
+ * config/pa/pa-hpux.opt.urls: Likewise.
+ * config/pa/pa-hpux1010.opt.urls: Likewise.
+ * config/pa/pa-hpux1111.opt.urls: Likewise.
+ * config/pa/pa-hpux1131.opt.urls: Likewise.
+ * config/pa/pa.opt.urls: Likewise.
+ * config/pa/pa64-hpux.opt.urls: Likewise.
+ * config/pdp11/pdp11.opt.urls: Likewise.
+ * config/pru/pru.opt.urls: Likewise.
+ * config/riscv/riscv.opt.urls: Likewise.
+ * config/rl78/rl78.opt.urls: Likewise.
+ * config/rpath.opt.urls: Likewise.
+ * config/rs6000/476.opt.urls: Likewise.
+ * config/rs6000/aix64.opt.urls: Likewise.
+ * config/rs6000/darwin.opt.urls: Likewise.
+ * config/rs6000/linux64.opt.urls: Likewise.
+ * config/rs6000/rs6000-tables.opt.urls: Likewise.
+ * config/rs6000/rs6000.opt.urls: Likewise.
+ * config/rs6000/sysv4.opt.urls: Likewise.
+ * config/rtems.opt.urls: Likewise.
+ * config/rx/elf.opt.urls: Likewise.
+ * config/rx/rx.opt.urls: Likewise.
+ * config/s390/s390.opt.urls: Likewise.
+ * config/s390/tpf.opt.urls: Likewise.
+ * config/sh/sh.opt.urls: Likewise.
+ * config/sh/superh.opt.urls: Likewise.
+ * config/sol2.opt.urls: Likewise.
+ * config/sparc/long-double-switch.opt.urls: Likewise.
+ * config/sparc/sparc.opt.urls: Likewise.
+ * config/stormy16/stormy16.opt.urls: Likewise.
+ * config/v850/v850.opt.urls: Likewise.
+ * config/vax/elf.opt.urls: Likewise.
+ * config/vax/vax.opt.urls: Likewise.
+ * config/visium/visium.opt.urls: Likewise.
+ * config/vms/vms.opt.urls: Likewise.
+ * config/vxworks-smp.opt.urls: Likewise.
+ * config/vxworks.opt.urls: Likewise.
+ * config/xtensa/elf.opt.urls: Likewise.
+ * config/xtensa/uclinux.opt.urls: Likewise.
+ * config/xtensa/xtensa.opt.urls: Likewise.
+ * config/bfin/bfin.opt.urls: New file.
+
+2024-01-04 David Malcolm <dmalcolm@redhat.com>
+
+ * Makefile.in (OPT_URLS_HTML_DEPS): New.
+ (regenerate-opt-urls): New target.
+ (regenerate-opt-urls-unit-test): New target.
+ * doc/options.texi (Option properties): Add UrlSuffix and
+ description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
+ * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
+ reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
+ and Makefile.in's OPT_URLS_HTML_DEPS.
+ (Anatomy of a Target Back End): Add
+ reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
+ * regenerate-opt-urls.py: New file.
+
+2024-01-04 David Malcolm <dmalcolm@redhat.com>
-2023-01-09 Martin Liska <mliska@suse.cz>
+ * diagnostic-format-sarif.cc
+ (sarif_builder::make_logical_location_object): Convert to...
+ (make_sarif_logical_location_object): ...this.
+ (sarif_builder::set_any_logical_locs_arr): Update for above
+ change.
+ (sarif_builder::make_thread_flow_location_object): Call
+ maybe_add_sarif_properties on each diagnostic_event.
+ * diagnostic-format-sarif.h (class logical_location): New forward
+ decl.
+ (make_sarif_logical_location_object): New decl.
+ * diagnostic-path.h (class sarif_object): New forward decl.
+ (diagnostic_event::maybe_add_sarif_properties): New vfunc.
- PR lto/108330
- * lto-cgraph.cc (compute_ltrans_boundary): Do not insert
- NULL (deleleted value) to a hash_set.
+2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
+ Patrick Lin <patrick@andestech.com>
+ Rufus Chen <rufus@andestech.com>
+ Monk Chiang <monk.chiang@sifive.com>
-2023-01-08 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
+ with Nan-boxing value.
+ * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
- * config/xtensa/xtensa.md (*splice_bits):
- New insn_and_split pattern.
+2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
+ Jeff Law <jlaw@ventanamicro.com>
-2023-01-07 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+ PR rtl-optimization/104914
+ * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
+ a sign or zero extension is only required if the modified field
+ overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
+ targets, don't refer to the temporarily incorrectly extended value
+ using a SUBREG, but instead generate an explicit TRUNCATE rtx.
- * config/xtensa/xtensa.cc
- (xtensa_split_imm_two_addends, xtensa_emit_add_imm):
- New helper functions.
- (xtensa_set_return_address, xtensa_output_mi_thunk):
- Change to use the helper function.
- (xtensa_emit_adjust_stack_ptr): Ditto.
- And also change to try reusing the content of scratch register
- A9 if the register is not modified in the function body.
+2024-01-04 Pan Li <pan2.li@intel.com>
-2023-01-07 LIU Hao <lh_mouse@126.com>
+ Revert:
+ 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- PR middle-end/108300
- * config/xtensa/xtensa-dynconfig.c: Define `WIN32_LEAN_AND_MEAN`
- before <windows.h>.
- * diagnostic-color.cc: Likewise.
- * plugin.cc: Likewise.
- * prefix.cc: Likewise.
+ * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
-2023-01-06 Joseph Myers <joseph@codesourcery.com>
+2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * doc/extend.texi (__builtin_tgmath): Do not restate standard rule
- for handling real integer types.
+ * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
-2023-01-06 Tamar Christina <tamar.christina@arm.com>
+2024-01-04 Kito Cheng <kito.cheng@sifive.com>
- Revert:
- 2022-12-12 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-simd.md (*aarch64_simd_movv2hf): New.
- (mov<mode>, movmisalign<mode>, aarch64_dup_lane<mode>,
- aarch64_store_lane0<mode>, aarch64_simd_vec_set<mode>,
- @aarch64_simd_vec_copy_lane<mode>, vec_set<mode>,
- reduc_<optab>_scal_<mode>, reduc_<fmaxmin>_scal_<mode>,
- aarch64_reduc_<optab>_internal<mode>, aarch64_get_lane<mode>,
- vec_init<mode><Vel>, vec_extract<mode><Vel>): Support V2HF.
- (aarch64_simd_dupv2hf): New.
- * config/aarch64/aarch64.cc (aarch64_classify_vector_mode):
- Add E_V2HFmode.
- * config/aarch64/iterators.md (VHSDF_P): New.
- (V2F, VMOVE, nunits, Vtype, Vmtype, Vetype, stype, VEL,
- Vel, q, vp): Add V2HF.
- * config/arm/types.md (neon_fp_reduc_add_h): New.
-
-2023-01-06 Martin Liska <mliska@suse.cz>
-
- PR middle-end/107966
- * doc/options.texi: Fix Var documentation in internal manual.
-
-2023-01-05 Roger Sayle <roger@nextmovesoftware.com>
+ * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
+ offset of fcsr.
- Revert:
- 2023-01-03 Roger Sayle <roger@nextmovesoftware.com>
+2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * config/i386/i386-expand.cc (ix86_expand_int_movcc): Rewrite
- RTL expansion to allow condition (mask) to be shared/reused,
- by avoiding overwriting pseudos and adding REG_EQUAL notes.
+ * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
+ (compute_nregs_for_mode): Refine LMUL.
+ (max_number_of_live_regs): Ditto.
+ (compute_estimated_lmul): Ditto.
+ (has_unexpected_spills_p): Ditto.
-2023-01-05 Iain Sandoe <iain@sandoe.co.uk>
+2024-01-04 Li Wei <liwei@loongson.cn>
- * common.opt: Add -static-libgm2.
- * config/darwin.h (LINK_SPEC): Handle static-libgm2.
- * doc/gm2.texi: Document static-libgm2.
- * gcc.cc (driver_handle_option): Allow static-libgm2.
+ * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
+ Remove useless forward declaration.
+ (loongarch_is_even_extraction): Remove useless forward declaration.
+ (loongarch_try_expand_lsx_vshuf_const): Removed.
+ (loongarch_expand_vec_perm_const_1): Merged.
+ (loongarch_is_double_duplicate): Removed.
+ (loongarch_is_center_extraction): Ditto.
+ (loongarch_is_reversing_permutation): Ditto.
+ (loongarch_is_di_misalign_extract): Ditto.
+ (loongarch_is_si_misalign_extract): Ditto.
+ (loongarch_is_lasx_lowpart_extract): Ditto.
+ (loongarch_is_op_reverse_perm): Ditto.
+ (loongarch_is_single_op_perm): Ditto.
+ (loongarch_is_divisible_perm): Ditto.
+ (loongarch_is_triple_stride_extract): Ditto.
+ (loongarch_expand_vec_perm_const_2): Merged.
+ (loongarch_expand_vec_perm_const): New.
+ (loongarch_vectorize_vec_perm_const): Adjust.
-2023-01-05 Tejas Joshi <TejasSanjay.Joshi@amd.com>
+2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
- * common/config/i386/i386-common.cc (processor_alias_table):
- Use CPU_ZNVER4 for znver4.
- * config/i386/i386.md: Add znver4.md.
- * config/i386/znver4.md: New.
+ * omp-general.cc: Fix comment typos and misplaced/confusing
+ comments. Delete redundant include of omp-general.h.
-2023-01-04 Jakub Jelinek <jakub@redhat.com>
+2024-01-04 YunQiang Su <syq@gcc.gnu.org>
- PR tree-optimization/108253
- * tree-vrp.cc (maybe_set_nonzero_bits): Handle var with pointer
- types.
+ PR rtl-optimization/104914
+ * config/mips/mips.md (insqisi_extended): New patterns.
+ (inshisi_extended): Ditto.
-2023-01-04 Jakub Jelinek <jakub@redhat.com>
+2024-01-04 YunQiang Su <syq@gcc.gnu.org>
- PR middle-end/108237
- * generic-match-head.cc: Include tree-pass.h.
- (canonicalize_math_p, optimize_vectors_before_lowering_p): Define
- to false if cfun and cfun->curr_properties has PROP_gimple_opt_math
- resp. PROP_gimple_lvec property set.
+ * config/mips/mips.cc (mips_insn_cost): New function.
-2023-01-04 Jakub Jelinek <jakub@redhat.com>
+2024-01-04 YunQiang Su <syq@gcc.gnu.org>
- PR sanitizer/108256
- * convert.cc (do_narrow): Punt for MULT_EXPR if original
- type doesn't wrap around and -fsanitize=signed-integer-overflow
- is on.
- * fold-const.cc (fold_unary_loc) <CASE_CONVERT>: Likewise.
+ * config/mips/mips.md (perf_ratio): New attribute.
-2023-01-04 Hu, Lin1 <lin1.hu@intel.com>
+2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Emeraldrapids.
- * common/config/i386/i386-common.cc: Add Emeraldrapids.
+ PR target/113206
+ PR target/113209
+ * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
+ (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
+ blocks belong to infinite loop.
+ (pre_vsetvl::emit_vsetvl): Remove fake edges.
+ * config/riscv/t-riscv: Add a new include file.
-2023-01-04 Hu, Lin1 <lin1.hu@intel.com>
+2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- * common/config/i386/cpuinfo.h (get_intel_cpu): Remove case 0xb5
- for meteorlake.
+ * config/riscv/vector.md: Fix indent.
-2023-01-03 Sandra Loosemore <sandra@codesourcery.com>
+2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
- * cgraph.h (struct cgraph_node): Add gc_candidate bit, modify
- default constructor to initialize it.
- * cgraphunit.cc (expand_all_functions): Save gc_candidate functions
- for last and iterate to handle recursive calls. Delete leftover
- candidates at the end.
- * omp-simd-clone.cc (simd_clone_create): Set gc_candidate bit
- on local clones.
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Clear
- gc_candidate bit when a clone is used.
+ * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
+ OMP_CLAUSE__SIMDUID_.
+ * tree.cc (omp_clause_num_ops): Update position of entry for
+ OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
+ (omp_clause_code_name): Likewise.
-2023-01-03 Florian Weimer <fweimer@redhat.com>
+2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
- Revert:
- 2023-01-02 Florian Weimer <fweimer@redhat.com>
-
- * dwarf2cfi.cc (init_return_column_size): Remove.
- (init_one_dwarf_reg_size): Adjust.
- (generate_dwarf_reg_sizes): New function. Extracted
- from expand_builtin_init_dwarf_reg_sizes.
- (expand_builtin_init_dwarf_reg_sizes): Call
- generate_dwarf_reg_sizes.
- * target.def (init_dwarf_reg_sizes_extra): Adjust
- hook signature.
- * config/msp430/msp430.cc
- (msp430_init_dwarf_reg_sizes_extra): Adjust.
- * config/rs6000/rs6000.cc
- (rs6000_init_dwarf_reg_sizes_extra): Likewise.
- * doc/tm.texi: Update.
-
-2023-01-03 Florian Weimer <fweimer@redhat.com>
+ * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
+ printing of FUNC_MAP/IND_FUNC_MAP labels.
- Revert:
- 2023-01-02 Florian Weimer <fweimer@redhat.com>
-
- * debug.h (dwarf_reg_sizes_constant): Declare.
- * dwarf2cfi.cc (dwarf_reg_sizes_constant): New function.
-
-2023-01-03 Siddhesh Poyarekar <siddhesh@gotplt.org>
-
- PR tree-optimization/105043
- * doc/extend.texi (Object Size Checking): Split out into two
- subsections and mention _FORTIFY_SOURCE.
-
-2023-01-03 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc (ix86_expand_int_movcc): Rewrite
- RTL expansion to allow condition (mask) to be shared/reused,
- by avoiding overwriting pseudos and adding REG_EQUAL notes.
-
-2023-01-03 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/108229
- * config/i386/i386-features.cc
- (general_scalar_chain::compute_convert_gain) <case PLUS>: Consider
- the gain/cost of converting a MEM operand.
-
-2023-01-03 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/108264
- * expr.cc (store_expr): For stores into SUBREG_PROMOTED_* targets
- from source which doesn't have scalar integral mode first convert
- it to outer_mode.
-
-2023-01-03 Jakub Jelinek <jakub@redhat.com>
-
- PR rtl-optimization/108263
- * cfgrtl.cc (fixup_reorder_chain): Avoid trying to redirect
- asm goto to EXIT.
-
-2023-01-02 Alexander Monakov <amonakov@ispras.ru>
-
- PR target/87832
- * config/i386/lujiazui.md (lujiazui_div): New automaton.
- (lua_div): New unit.
- (lua_idiv_qi): Correct unit in the reservation.
- (lua_idiv_qi_load): Ditto.
- (lua_idiv_hi): Ditto.
- (lua_idiv_hi_load): Ditto.
- (lua_idiv_si): Ditto.
- (lua_idiv_si_load): Ditto.
- (lua_idiv_di): Ditto.
- (lua_idiv_di_load): Ditto.
- (lua_fdiv_SF): Ditto.
- (lua_fdiv_SF_load): Ditto.
- (lua_fdiv_DF): Ditto.
- (lua_fdiv_DF_load): Ditto.
- (lua_fdiv_XF): Ditto.
- (lua_fdiv_XF_load): Ditto.
- (lua_ssediv_SF): Ditto.
- (lua_ssediv_load_SF): Ditto.
- (lua_ssediv_V4SF): Ditto.
- (lua_ssediv_load_V4SF): Ditto.
- (lua_ssediv_V8SF): Ditto.
- (lua_ssediv_load_V8SF): Ditto.
- (lua_ssediv_SD): Ditto.
- (lua_ssediv_load_SD): Ditto.
- (lua_ssediv_V2DF): Ditto.
- (lua_ssediv_load_V2DF): Ditto.
- (lua_ssediv_V4DF): Ditto.
- (lua_ssediv_load_V4DF): Ditto.
-
-2023-01-02 Florian Weimer <fweimer@redhat.com>
-
- * debug.h (dwarf_reg_sizes_constant): Declare.
- * dwarf2cfi.cc (dwarf_reg_sizes_constant): New function.
-
-2023-01-02 Florian Weimer <fweimer@redhat.com>
-
- * dwarf2cfi.cc (init_return_column_size): Remove.
- (init_one_dwarf_reg_size): Adjust.
- (generate_dwarf_reg_sizes): New function. Extracted
- from expand_builtin_init_dwarf_reg_sizes.
- (expand_builtin_init_dwarf_reg_sizes): Call
- generate_dwarf_reg_sizes.
- * target.def (init_dwarf_reg_sizes_extra): Adjust
- hook signature.
- * config/msp430/msp430.cc
- (msp430_init_dwarf_reg_sizes_extra): Adjust.
- * config/rs6000/rs6000.cc
- (rs6000_init_dwarf_reg_sizes_extra): Likewise.
- * doc/tm.texi: Update.
-
-2023-01-02 Jakub Jelinek <jakub@redhat.com>
+2024-01-03 Jakub Jelinek <jakub@redhat.com>
* gcc.cc (process_command): Update copyright notice dates.
* gcov-dump.cc (print_version): Ditto.
* doc/install.texi: Ditto.
* doc/invoke.texi: Ditto.
-2023-01-01 Roger Sayle <roger@nextmovesoftware.com>
- Uroš Bizjak <ubizjak@gmail.com>
+2024-01-03 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/simd.md (fmax<mode>3): New define_insn.
+ (fmin<mode>3): Likewise.
+ (reduc_fmax_scal_<mode>3): New define_expand.
+ (reduc_fmin_scal_<mode>3): Likewise.
+
+2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/113112
+ * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
+ (max_number_of_live_regs): Ditto.
+ (has_unexpected_spills_p): Ditto.
+
+2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
+ Jin Ma <jinma@linux.alibaba.com>
+ Xianmiao Qu <cooper.qu@linux.alibaba.com>
+ Christoph Müllner <christoph.muellner@vrull.eu>
+
+ * config/riscv/vector.md:
+ Use vector_length_operand for vsetvl patterns.
+
+2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
+ (expand_cond_len_op): Add simplification of dummy len and dummy mask.
+
+2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
+
+ * config/aarch64/aarch64-tuning-flags.def
+ (AARCH64_EXTRA_TUNING_OPTION): New tuning option
+ AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
+ * config/aarch64/aarch64.cc
+ (aarch64_override_options_internal): Set
+ param_fully_pipelined_fma according to tuning option.
+ * config/aarch64/tuning_models/ampere1.h: Add
+ AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
+ * config/aarch64/tuning_models/ampere1a.h: Likewise.
+ * config/aarch64/tuning_models/ampere1b.h: Likewise.
+
+2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
+
+ * config/riscv/vector-crypto.md: Modify copyright year.
+
+2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
+
+2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config.in: Regenerate.
+ * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
+ * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
+ Added TLS Le Relax support.
+ (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
+ * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
+ * configure: Regenerate.
+ * configure.ac: Check if binutils supports TLS le relax.
+
+2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
+
+ * config/riscv/iterators.md: Add rotate insn name.
+ * config/riscv/riscv.md: Add new insns name for crypto vector.
+ * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
+ * config/riscv/vector.md: Add the corresponding attr for crypto vector.
+ * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
- * config/i386/i386.md (extendditi2): New define_insn.
- (define_split): Use DWIH mode iterator to treat new extendditi2
- identically to existing extendsidi2_1.
- (define_peephole2): Likewise.
- (define_peephole2): Likewise.
- (define_Split): Likewise.
+2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+ PR target/113112
+ * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
+ pointer type liveness count.
\f
-Copyright (C) 2023 Free Software Foundation, Inc.
+Copyright (C) 2024 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / thirdparty / gcc.git / blobdiff