+2024-03-22 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
+ for deprecated SIGNAL and INTERRUPT usage without respective header.
+
+2024-03-22 Andrew Stubbs <ams@baylibre.com>
+
+ * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
+ (atomic_load<mode>): Adjust RDNA cache settings.
+ (atomic_store<mode>): Likewise.
+ (atomic_exchange<mode>): Likewise.
+
+2024-03-22 Andrew Stubbs <ams@baylibre.com>
+
+ * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
+ RDNA devices.
+
+2024-03-22 Andrew Stubbs <ams@baylibre.com>
+
+ * config.gcc (amdgcn): Add gfx1103 entries.
+ * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
+ (gcn_local_sym_hash): Likewise.
+ * config/gcn/gcn-opts.h (enum processor_type): Likewise.
+ (TARGET_GFX1103): New macro.
+ * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
+ (gcn_omp_device_kind_arch_isa): Likewise.
+ (output_file_start): Likewise.
+ (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
+ * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
+ * config/gcn/gcn.opt: Add gfx1103.
+ * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
+ (main): Handle gfx1103.
+ * config/gcn/t-omp-device: Add gfx1103 isa.
+ * doc/install.texi (amdgcn): Add gfx1103.
+ * doc/invoke.texi (-march): Likewise.
+
+2024-03-22 Andrew Stubbs <ams@baylibre.com>
+
+ * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
+ bitmasks.
+ (do_compare_and_jump): Remove now-redundant similar code.
+ * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
+ bitmasks.
+ (add_mask_and_len_args): Likewise.
+
+2024-03-22 Pan Li <pan2.li@intel.com>
+
+ * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
+ macro __riscv_v_fixed_vlen when zvl.
+ * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
+ New static func to take care of the RVV types decorated by
+ the attributes.
+
+2024-03-22 Andrew Pinski <quic_apinski@quicinc.com>
+
+ PR c/109619
+ * builtins.cc (fold_builtin_1): Use error_operand_p
+ instead of checking against ERROR_MARK.
+ (fold_builtin_2): Likewise.
+ (fold_builtin_3): Likewise.
+
+2024-03-22 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/111736
+ * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
+ SANITIZE_NULL instrumentation for non-generic address spaces
+ for which targetm.addr_space.zero_address_valid (as) is true.
+
+2024-03-22 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/114405
+ * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
+ Set rprec to limb_prec rather than 0 if tprec is divisible by
+ limb_prec. In the last bf_cur handling, set rprec to (tprec + bo_bit)
+ % limb_prec rather than tprec % limb_prec and use just rprec instead
+ of rprec + bo_bit. For build_bit_field_ref offset, divide
+ (tprec + bo_bit) by limb_prec rather than just tprec.
+
+2024-03-22 Christoph Müllner <christoph.muellner@vrull.eu>
+
+ PR target/114194
+ * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
+ Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
+
+2024-03-22 Jeff Law <jlaw@ventanamicro.com>
+
+ * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
+ tie for scalable and final stack adjustment if needed.
+ Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
+
+2024-03-22 Pan Li <pan2.li@intel.com>
+
+ PR target/114352
+ * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
+ New struct for func decl and target name.
+ (struct riscv_func_target_hasher): New hasher for hash table mapping
+ from the fn_decl to fn_target_name.
+ (riscv_func_decl_hash): New func to compute the hash for fn_decl.
+ (riscv_func_target_hasher::hash): New func to impl hash interface.
+ (riscv_func_target_hasher::equal): New func to impl equal interface.
+ (riscv_cmdline_subset_list): New static var for cmdline subset list.
+ (riscv_func_target_table_lazy_init): New func to lazy init the func
+ target hash table.
+ (riscv_func_target_get): New func to get target name from hash table.
+ (riscv_func_target_put): New func to put target name into hash table.
+ (riscv_func_target_remove_and_destory): New func to remove target
+ info from the hash table and destory it.
+ (riscv_parse_arch_string): Set the static var cmdline_subset_list.
+ * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
+ var for cmdline subset list.
+ (riscv_func_target_get): New func decl.
+ (riscv_func_target_put): Ditto.
+ (riscv_func_target_remove_and_destory): Ditto.
+ * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
+ Take cmdline_subset_list instead of current_subset_list when clone.
+ (riscv_process_target_attr): Record the func target info to hash table.
+ (riscv_option_valid_attribute_p): Add new arg tree fndel.
+ * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
+ func target info and print the arch message.
+
+2024-03-22 Pan Li <pan2.li@intel.com>
+
+ PR target/114352
+ * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
+ Replace implied, combine and check to func finalize.
+ (riscv_subset_list::finalize): New func impl to take care of
+ implied, combine ext and related checks.
+ * config/riscv/riscv-subset.h: Add func decl for finalize.
+ * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
+ Finalize the ext before return succeed.
+ * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
+ machine mode before when set cur function.
+
+2024-03-21 Andrew Stubbs <ams@baylibre.com>
+
+ * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
+
+2024-03-21 Andrew Stubbs <ams@baylibre.com>
+
+ * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
+
+2024-03-21 Andrew Stubbs <ams@baylibre.com>
+
+ * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
+ device_malloc call.
+
+2024-03-21 liuhongt <hongtao.liu@intel.com>
+
+ PR tree-optimization/114396
+ * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
+ and true to wi::from_mpz.
+
+2024-03-21 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/111736
+ * asan.cc (instrument_derefs): Do not instrument accesses
+ to non-generic address-spaces.
+
+2024-03-21 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/113727
+ * tree-sra.cc (analyze_access_subtree): Do not allow
+ replacements in subtrees when grp_partial_lhs.
+
+2024-03-21 liuhongt <hongtao.liu@intel.com>
+
+ PR middle-end/114347
+ * doc/invoke.texi: Document -fexcess-precision=16.
+
+2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
+
+ * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
+ field contains a DECL_NAME.
+
+2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
+
+ * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
+ Add assert to validate the string is set.
+ * config/bpf/core-builtins.cc (cr_final): Make string struct
+ field as const.
+ (process_enum_value): Correct for field type change.
+ (process_type): Set access string to "0".
+
+2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
+
+ * config/bpf/core-builtins.cc (core_field_info): Add
+ support for POINTER_PLUS_EXPR in the root of the field expression.
+ (bpf_core_get_index): Likewise.
+ (pack_field_expr): Make the BTF type to point to the structure
+ related node, instead of its pointer type.
+ (make_core_safe_access_index): Correct to new code.
+
+2024-03-20 Xi Ruoyao <xry111@xry111.site>
+
+ PR target/114407
+ * config/loongarch/loongarch-opts.cc (loongarch_config_target):
+ Fix typo in diagnostic message, enabing -> enabling.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
+ TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
+ nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
+ function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
+ function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
+ function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
+ skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
+ csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-20 Yury Khrustalev <yury.khrustalev@arm.com>
+
+ * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/114365
+ * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
+ a PHI node, set iv2 to its result afterwards.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
+ probabbility -> probability.
+ (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
+
+2024-03-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR bootstrap/114369
+ * system.h (vec_step): Define to vec_step_ when compiling
+ with clang on PowerPC.
+
+2024-03-20 demin.han <demin.han@starfivetech.com>
+
+ PR target/112651
+ * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
+ (enum rvv_max_lmul_enum): Ditto
+ (TARGET_MAX_LMUL): Ditto
+ * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
+ * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
+ (costs::better_main_loop_than_p): Ditto
+ * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
+
+2024-03-20 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/113396
+ * tree-dfa.cc (get_ref_base_and_extent): Use index range
+ bounds only if they fit within the address-range constraints
+ of offset_int.
+
+2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
+
+ * config/loongarch/loongarch.cc
+ (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
+ UNITS_PER_FPREG macros.
+ (loongarch_hard_regno_nregs): Ditto.
+ (loongarch_class_max_nregs): Ditto.
+ (loongarch_get_separate_components): Ditto.
+ (loongarch_process_components): Ditto.
+ * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
+ (UNITS_PER_HWFPVALUE): Ditto.
+ (UNITS_PER_FPVALUE): Ditto.
+
+2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
+
+ * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
+ of loongarch_expand_vec_cmp()'s return value.
+ (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
+ * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
+ (vec_cmpu<ILSX:mode><mode_i>): Ditto.
+ * config/loongarch/loongarch-protos.h
+ (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
+ type from bool to void.
+ * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
+
+2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
+
+ * config/loongarch/loongarch-protos.h
+ (loongarch_cfun_has_cprestore_slot_p): Delete.
+ (loongarch_adjust_insn_length): Delete.
+ (current_section_name): Delete.
+ (loongarch_split_symbol_type): Delete.
+ * config/loongarch/loongarch.cc
+ (loongarch_case_values_threshold): Delete.
+ (loongarch_spill_class): Delete.
+ (TARGET_OPTAB_SUPPORTED_P): Delete.
+ (TARGET_CASE_VALUES_THRESHOLD): Delete.
+ (TARGET_SPILL_CLASS): Delete.
+
+2024-03-20 Lewis Hyatt <lhyatt@gmail.com>
+
+ PR c++/111918
+ * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
+ * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
+ Make use of DK_ANY to indicate a diagnostic was initially enabled.
+ (diagnostic_context::diagnostic_enabled): Do not change the type of
+ a diagnostic if the saved classification is type DK_ANY.
+
+2024-03-19 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/108802
+ PR ipa/114254
+ * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
+ at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
+ a pointer parameter.
+ (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
+ parameter, also recognize the case when pfn pointer is loaded in its
+ own BB.
+
+2024-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR target/99829
+ * lra-constraints.cc (lra_constraints): Prevent removing insn
+ with reverse equivalence to memory if the memory was reloaded.
+
+2024-03-19 David Malcolm <dmalcolm@redhat.com>
+
+ PR middle-end/114348
+ * diagnostic-format-json.cc
+ (json_stderr_output_format::machine_readable_stderr_p): New.
+ (json_file_output_format::machine_readable_stderr_p): New.
+ * diagnostic-format-sarif.cc
+ (sarif_stream_output_format::machine_readable_stderr_p): New.
+ (sarif_file_output_format::machine_readable_stderr_p): New.
+ * diagnostic.cc (diagnostic_context::action_after_output): Move
+ "fnotice" to before "finish" call, so that we still have the
+ diagnostic_context.
+ (fnotice): Bail out if the user requested one of the
+ machine-readable diagnostic output formats on stderr.
+ * diagnostic.h
+ (diagnostic_output_format::machine_readable_stderr_p): New pure
+ virtual function.
+ (diagnostic_text_output_format::machine_readable_stderr_p): New.
+ (diagnostic_context::get_output_format): New accessor.
+
+2024-03-19 Edwin Lu <ewlu@rivosinc.com>
+
+ PR target/114175
+ * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
+ riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL
+
+2024-03-19 Jonathan Wakely <jwakely@redhat.com>
+
+ * doc/install.texi (Prerequisites): Document use of autogen for
+ libstdc++.
+
+2024-03-19 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114151
+ PR tree-optimization/114269
+ PR tree-optimization/114322
+ PR tree-optimization/114074
+ * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
+ unsigned arithmetic when actual overflow on constant operands
+ is observed.
+
+2024-03-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
+ arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-19 Xi Ruoyao <xry111@xry111.site>
+
+ PR target/114175
+ * config/loongarch/loongarch.cc
+ (loongarch_setup_incoming_varargs): Only skip
+ loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
+ functions if arg.type is NULL.
+
+2024-03-19 Christophe Lyon <christophe.lyon@linaro.org>
+
+ PR target/114323
+ * config/arm/arm-mve-builtins.cc
+ (function_instance::reads_global_state_p): Take CP_READ_MEMORY
+ into account.
+
+2024-03-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
+ function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
+ rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-19 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114375
+ * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
+ load permutation for masked loads but reject it when any
+ such is necessary.
+ * tree-vect-stmts.cc (vectorizable_load): Reject masked
+ VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
+ supported.
+
+2024-03-19 Mary Bennett <mary.bennett@embecosm.com>
+
+ * common/config/riscv/riscv-common.cc: Create XCVbi extension
+ support.
+ * config/riscv/riscv.opt: Likewise.
+ * config/riscv/corev.md: Implement cv_branch<mode> pattern
+ for cv.beqimm and cv.bneimm.
+ * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
+ branch instruction pattern.
+ * config/riscv/constraints.md: Implement constraints
+ cv_bi_s5 - signed 5-bit immediate.
+ * config/riscv/predicates.md: Implement predicate
+ const_int5s_operand - signed 5 bit immediate.
+ * doc/sourcebuild.texi: Add XCVbi documentation.
+
+2024-03-19 Chen Jiawei <jiawei@iscas.ac.cn>
+
+ * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
+ (RISCV_CORE): Ditto.
+ * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
+ option.
+ * config/riscv/riscv.cc: New def.
+ * config/riscv/riscv.md: New include.
+ * config/riscv/xiangshan.md: New file.
+
+2024-03-18 David Malcolm <dmalcolm@redhat.com>
+
+ PR analyzer/110902
+ PR analyzer/110928
+ PR analyzer/111305
+ PR analyzer/111441
+ * selftest.h (ASSERT_NE_AT): New macro.
+
+2024-03-18 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/111822
+ * config/i386/i386-features.cc (smode_convert_cst): New function
+ to handle SImode, DImode and TImode immediates, generalized from
+ timode_convert_cst.
+ (timode_convert_cst): Remove.
+ (scalar_chain::convert_op): Unify from
+ general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
+ (general_scalar_chain::convert_op): Remove.
+ (timode_scalar_chain::convert_op): Remove.
+ (timode_scalar_chain::convert_insn): Update the call to
+ renamed timode_convert_cst.
+ * config/i386/i386-features.h (class scalar_chain):
+ Redeclare convert_op as protected class member.
+ (class general_calar_chain): Remove convert_op.
+ (class timode_scalar_chain): Ditto.
+
+2024-03-18 Jan Hubicka <jh@suse.cz>
+
+ * config/i386/zn4zn5.md: Add file missed in the previous commit.
+
+2024-03-18 Jan Hubicka <jh@suse.cz>
+ Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com>
+
+ * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
+ * common/config/i386/i386-common.cc (processor_names): Add znver5.
+ (processor_alias_table): Likewise.
+ * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
+ family.
+ (processor_subtypes): Add znver5.
+ * config.gcc (x86_64-*-* |...): Likewise.
+ * config/i386/driver-i386.cc (host_detect_local_cpu): Let
+ march=native detect znver5 cpu's.
+ * config/i386/i386-c.cc (ix86_target_macros_internal): Add
+ znver5.
+ * config/i386/i386-options.cc (m_ZNVER5): New definition
+ (processor_cost_table): Add znver5.
+ * config/i386/i386.cc (ix86_reassociation_width): Likewise.
+ * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
+ (PTA_ZNVER5): New definition.
+ * config/i386/i386.md (define_attr "cpu"): Add znver5.
+ (Scheduling descriptions) Add znver5.md.
+ * config/i386/x86-tune-costs.h (znver5_cost): New definition.
+ * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
+ (ix86_adjust_cost): Likewise.
+ * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
+ (avx512_store_by_pieces): Add m_ZNVER5.
+ * doc/extend.texi: Add znver5.
+ * doc/invoke.texi: Likewise.
+ * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
+
+2024-03-18 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
+ * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
+ * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
+ * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
+ (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
+ (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
+
+2024-03-18 liuhongt <hongtao.liu@intel.com>
+
+ PR target/114334
+ * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
+ (MODEF248): New mode iterator.
+ (ssevecmodesuffix): Hanlde BF and HF.
+ * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
+ (<code><mode>3): Ditto.
+
+2024-03-18 John David Anglin <danglin@gcc.gnu.org>
+
+ PR rtl-optimization/112415
+ * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
+ for symbolic memory operands.
+ (pa_legitimate_address_p): Revise LO_SUM condition.
+ * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move
+ comment about GNU linker to predicates.md.
+ * config/pa/predicates.md (floating_point_store_memory_operand):
+ Revise condition for symbolic memory operands. Update
+ comment.
+
+2024-03-17 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
+
+2024-03-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114175
+ * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
+ ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
+ if arg.type is NULL.
+
+2024-03-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/114329
+ * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
+ build_bit_field_ref method.
+ (bitint_large_huge::build_bit_field_ref): New method.
+ (bitint_large_huge::lower_mergeable_stmt): Use it.
+
+2024-03-15 YunQiang Su <syq@gcc.gnu.org>
+
+ * config/riscv/riscv.opt.urls: Regenerated.
+ * config/rs6000/sysv4.opt.urls: Likewise.
+ * config/xtensa/xtensa.opt.urls: Likewise.
+
+2024-03-15 Jakub Jelinek <jakub@redhat.com>
+
+ * lower-subreg.cc (resolve_simple_move): Fix comment typo,
+ betwee -> between.
+ * edit-context.cc (class line_event): Fix comment typo,
+ betweeen -> between.
+
+2024-03-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114339
+ * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
+ a pasto, compare code against LE rather than GE.
+
+2024-03-15 Joe Ramsay <Joe.Ramsay@arm.com>
+
+ * match.pd: Fix truncation pattern for -fno-signed-zeroes
+
+2024-03-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114332
+ * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
+
+2024-03-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/113466
+ * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
+ member.
+ (bitint_large_huge::bitint_large_huge): Initialize it.
+ (bitint_large_huge::~bitint_large_huge): Release it.
+ (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
+ before which at least one statement has been inserted.
+ (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
+ calls to a different block and add corresponding PHIs.
+
+2024-03-15 YunQiang Su <syq@gcc.gnu.org>
+
+ * config/mips/mips.opt: Support -mstrict-align, and use
+ TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
+ as alias.
+ * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
+ * config/mips/mips.opt.urls: Regenerate.
+ * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
+
+2024-03-15 Tejas Belagod <tejas.belagod@arm.com>
+
+ PR middle-end/114108
+ * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
+ vect_convert_output with the correct vecitype.
+
+2024-03-15 Chenghui Pan <panchenghui@loongson.cn>
+
+ * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
+ Remove masking of operand 3.
+
+2024-03-14 Jason Merrill <jason@redhat.com>
+
+ * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
+ comments.
+
+2024-03-14 John David Anglin <danglin@gcc.gnu.org>
+
+ PR target/114288
+ * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
+ 14-bit displacements before reload for modes that may use
+ a floating-point load or store.
+
+2024-03-14 David Faust <david.faust@oracle.com>
+
+ * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
+
+2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
+ patterns ahead of the l32i.n and s32i.n.
+
+2024-03-14 Jakub Jelinek <jakub@redhat.com>
+
+ * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
+
+2024-03-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/113907
+ * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
+ SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
+ functions.
+
+2024-03-14 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/loongarch.md (any_ge): Remove.
+ (sge<u>_<X:mode><GPR:mode>): Remove.
+
+2024-03-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114310
+ * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
+ TImode force newval into a register.
+
+2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
+
+ * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
+ (OMP_CLAUSE__CACHE__READONLY): New macro.
+ * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
+ uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
+ OMP_CLAUSE__CACHE__READONLY.
+ * tree-pretty-print.cc (dump_omp_clause): Add support for printing
+ OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
+
+2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/s390/s390.cc (s390_encode_section_info): Adjust the check
+ for misaligned symbols.
+ * config/s390/s390.opt: Improve documentation.
+
+2024-03-14 Jakub Jelinek <jakub@redhat.com>
+
+ * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
+ flags and probability from ad_edge to e edge. If CDI_DOMINATORS
+ are computed, recompute immediate dominator of other_edge->src
+ and other_edge->dest.
+ (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
+ for the returns_twice call case to the gsi_for_stmt (stmt) to deal
+ with update it for bb splitting.
+
+2024-03-14 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386-features.cc
+ (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
+ (convert_scalars_to_vector): Ditto.
+ * config/i386/i386-features.h (class scalar_chain): New
+ memeber control_flow_insns.
+
+2024-03-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114319
+ * gimple-ssa-store-merging.cc
+ (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
+ allow matching __builtin_bswap64 if there is bswapsi2 optab.
+
+2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * config/s390/s390.cc (s390_secondary_reload): Guard
+ SYMBOL_FLAG_NOTALIGN2_P.
+
+2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * config/s390/s390-builtin-types.def: Update to reflect latest
+ changes.
+ * config/s390/s390-builtins.def: Streamline vector builtins with
+ LLVM.
+
+2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * config/s390/s390-builtins.def (vec_permi): Deprecate.
+ (vec_ctd): Deprecate.
+ (vec_ctd_s64): Deprecate.
+ (vec_ctd_u64): Deprecate.
+ (vec_ctsl): Deprecate.
+ (vec_ctul): Deprecate.
+ (vec_ld2f): Deprecate.
+ (vec_st2f): Deprecate.
+ (vec_insert): Deprecate overloads with bool vectors.
+
+2024-03-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114313
+ * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
+ TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
+ (bitint_large_huge::handle_load): Pass NULL_TREE rather than
+ rhs_type to limb_access for the bitfield load cases.
+ (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
+ lhs_type to limb_access if nlhs is non-NULL.
+
+2024-03-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/112709
+ * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
+ build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
+ gsi_safe_insert_before instead of gsi_insert_before.
+
+2024-03-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/112709
+ * gimple-iterator.h (gsi_safe_insert_before,
+ gsi_safe_insert_seq_before): Declare.
+ * gimple-iterator.cc: Include gimplify.h.
+ (edge_before_returns_twice_call, adjust_before_returns_twice_call,
+ gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
+ * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
+ instrument_nonnull_arg, instrument_nonnull_return): Use
+ gsi_safe_insert_before instead of gsi_insert_before.
+ (maybe_instrument_pointer_overflow): Use force_gimple_operand,
+ gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
+ instead of force_gimple_operand_gsi.
+ (instrument_object_size): Likewise. Use gsi_safe_insert_before
+ instead of gsi_insert_before.
+
+2024-03-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114121
+ * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
+ converted operand properly.
+ (chrec_fold_multiply): Likewise. Handle missed recursion.
+
+2024-03-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/112709
+ * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
+ stores on the caller side unless it is a call to a builtin or
+ internal function or function doesn't return by hidden reference.
+ (maybe_instrument_call): Likewise.
+ (instrument_derefs): Instrument stores to RESULT_DECL if
+ returning by hidden reference.
+
+2024-03-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/114293
+ * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
+ max is smaller than min, set max to ~(size_t)0.
+
+2024-03-12 Pan Li <pan2.li@intel.com>
+
+ * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
+ code style greater than 80 chars.
+ (riscv_cpu_cpp_builtins): Fix useless empty line, indent
+ with 3 space(s) and argument unalignment.
+
+2024-03-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114297
+ * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
+ live stmts SLP node to vect_create_epilog_for_reduction.
+
+2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
+
+ PR driver/114314
+ * common.opt (fmultiflags): Add RejectNegative.
+
+2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
+ * config/aarch64/aarch64.opt: Likewise.
+ * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
+ * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
+ (aarch64_expand_epilogue): Likewise.
+ (aarch64_post_cfi_startproc): Likewise.
+ (aarch64_handle_no_branch_protection): Copy and rename.
+ (aarch64_handle_standard_branch_protection): Likewise.
+ (aarch64_handle_pac_ret_protection): Likewise.
+ (aarch64_handle_pac_ret_leaf): Likewise.
+ (aarch64_handle_pac_ret_b_key): Likewise.
+ (aarch64_handle_bti_protection): Likewise.
+ (aarch64_override_options): Update branch protection validation.
+ (aarch64_handle_attr_branch_protection): Likewise.
+ * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
+ Pass branch protection type description as argument.
+ (struct aarch_branch_protect_type): Move from aarch-common.h.
+ * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
+ Remove.
+ (aarch_handle_standard_branch_protection): Remove.
+ (aarch_handle_pac_ret_protection): Remove.
+ (aarch_handle_pac_ret_leaf): Remove.
+ (aarch_handle_pac_ret_b_key): Remove.
+ (aarch_handle_bti_protection): Remove.
+ (aarch_validate_mbranch_protection): Pass branch protection type
+ description as argument.
+ * config/arm/aarch-common.h (enum aarch_key_type): Remove.
+ (struct aarch_branch_protect_type): Remove.
+ * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
+ * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
+ (arm_handle_standard_branch_protection): Likewise.
+ (arm_handle_pac_ret_protection): Likewise.
+ (arm_handle_pac_ret_leaf): Likewise.
+ (arm_handle_bti_protection): Likewise.
+ (arm_configure_build_target): Update branch protection validation.
+ * config/arm/arm.opt: Remove aarch_ra_sign_key.
+
+2024-03-11 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/114299
+ * gimplify.cc (internal_get_tmp_var): When gimplification
+ of VAL failed, return a decl.
+
+2024-03-11 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/114278
+ * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
+ longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
+
+2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR debug/113519
+ PR debug/113777
+ * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
+ generate the DIE with the same parent as in the regular case.
+
+2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
+
+ PR middle-end/95351
+ * fold-const.cc (merge_truthop_with_opposite_arm): Use
+ the type of the operands of the comparison and not the type
+ of the comparison.
+
+2024-03-10 jlaw <jeffreyalaw@gmail.com>
+
+ PR tree-optimization/110199
+ * tree-ssa-scopedtables.cc
+ (avail_exprs_stack::simplify_binary_operation): Generalize handling
+ of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
+ comparison operands for other cases.
+
+2024-03-10 Pan Li <pan2.li@intel.com>
+
+ * tree-vect-stmts.cc (vectorizable_store): Enable the assert
+ during transform process.
+ (vectorizable_load): Ditto.
+
+2024-03-10 jlaw <jeffreyalaw@gmail.com>
+
+ PR target/102250
+ * doc/install.texi: Document need for python when building
+ RISC-V compilers.
+
+2024-03-10 jlaw <jeffreyalaw@gmail.com>
+
+ PR target/111362
+ * mode-switching.cc (optimize_mode_switching): Only process
+ NONDEBUG insns.
+
+2024-03-09 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.md: Fix typos in comment, indentation glitches
+ and some other nits.
+
+2024-03-09 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114284
+ * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
+ src containing MEMs unless prop.likely_profitable_p ().
+
+2024-03-09 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
+ Support 'Q' for R_LARCH_RELAX for TLS IE.
+ (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
+ IE.
+ * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
+
+2024-03-09 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
+ usum_widenqihi and add_zero_extend1.
+ [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
+ sub+sign_extend.
+ * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
+ Compute exact insn lengths.
+ (*usum_widenqihi3): Allow input operands to commute.
+
+2024-03-09 Jakub Jelinek <jakub@redhat.com>
+
+ * config/i386/i386.opt.urls: Regenerate.
+
+2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
+ In loongarch64, a sign extension operation is added when
+ operands[2] is a register operand and the mode is SImode.
+
+2024-03-08 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/113757
+ * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
+ id->killed_new_ssa_names.
+
+2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR target/113790
+ * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
+ for non-reload pseudo too.
+
+2024-03-08 David Faust <david.faust@oracle.com>
+
+ * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
+ not attempt inline expansion if size is above threshold.
+ * config/bpf/bpf.opt (-minline-memops-threshold): New option.
+ * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
+ Document.
+
+2024-03-08 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114269
+ PR tree-optimization/114074
+ * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
+ in the third CASE_CONVERT case as well.
+ (chrec_fold_multiply): Handle sign-conversions from unsigned
+ by performing the operation in the unsigned type.
+
+2024-03-08 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
+ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
+
+2024-03-08 Jakub Jelinek <jakub@redhat.com>
+
+ * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
+ asm_noperands < 0 means it is not asm goto too.
+
+2024-03-08 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/38534
+ * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
+ option.
+ * config/i386/i386-options.cc (ix86_set_func_type): Don't use
+ TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
+ ix86_noreturn_no_callee_saved_registers is enabled.
+ * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
+
+2024-03-08 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/113918
+ * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
+ on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
+
+2024-03-08 demin.han <demin.han@starfivetech.com>
+
+ PR target/114264
+ * config/riscv/riscv-vector-costs.cc: Fix ICE
+
+2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
+
+ * fwprop.cc (forward_propagate_into): Return false for volatile set
+ source rtx.
+
+2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
+
+ PR target/113618
+ * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
+ (aarch64_expand_cpymem): Emit single load/store only.
+ (aarch64_set_one_block): Emit single stores only.
+
+2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR middle-end/114196
+ * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
+ vectorization guards.
+
+2024-03-07 Jonathan Wakely <jwakely@redhat.com>
+
+ * doc/cppopts.texi: Remove incorrect claim about -dD not
+ outputting predefined macros.
+
+2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
+
+ PR target/113950
+ * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
+ and simplify else if with else.
+
+2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
+
+ * system.h: Include safe-ctype.h after C++ standard headers.
+
+2024-03-07 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/110079
+ * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
+ asm goto.
+
+2024-03-07 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/105533
+ * expmed.cc (choose_mult_variant): Only try the val - 1 variant
+ if val is not HOST_WIDE_INT_MIN or if mode has exactly
+ HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
+ val - 1.
+
+2024-03-07 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/105533
+ * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
+ Multiple op->off by BITS_PER_UNIT instead of shifting it left by
+ LOG2_BITS_PER_UNIT.
+
+2024-03-07 Yang Yujie <yangyujie@loongson.cn>
+
+ * config.gcc: Add a case for loongarch*-*-linux-musl*.
+ * config/loongarch/linux.h: Disable the multilib-compatible
+ treatment for *musl* targets.
+ * config/loongarch/musl.h: New file.
+
+2024-03-07 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/114009
+ * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
+ argument even for GENERIC, not just for GIMPLE.
+ * match.pd (a * !a -> 0): New simplifications.
+
+2024-03-07 demin.han <demin.han@starfivetech.com>
+
+ * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
+ * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
+ (expand_vec_cmp_float): Adapt arguments
+
+2024-03-06 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/114232
+ * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
+ of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
+ (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
+ (<plusminus:insn>v2qi3): Enable for optimize_size instead
+ of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
+ (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
+ (<any_shift:insn>v2qi3): Enable for optimize_size instead
+ of optimize_function_for_size_p.
+
+2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/114200
+ PR target/114202
+ * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
+
+2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
+ (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
+ offset handling.
+ (costs::add_stmt_cost): Also adjust cost for statements without
+ stmt_info.
+ * config/riscv/riscv-vector-costs.h: Define zero constant.
+
+2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
+
+ PR target/113915
+ * config/arm/arm.md (NOCOND): Improve comment.
+ (arm_rev*) Add predicable.
+ * config/arm/arm.cc (arm_final_prescan_insn): Add check for
+ PREDICABLE_YES.
+
+2024-03-06 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/113001
+ PR target/112871
+ * config/riscv/riscv.cc (expand_conditional_move): Do not swap
+ operands when the comparison operand is the same as the false
+ arm for a NE test.
+
+2024-03-06 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
+ Eliminate common code and use generic code instead.
+
+2024-03-06 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
+ rtx cost.
+
+2024-03-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114239
+ * tree-vect-loop.cc (vect_get_vect_def): Remove.
+ (vect_create_epilog_for_reduction): The passed in stmt_info
+ should now be the live stmt that produces the scalar reduction
+ result. Revert PR114192 fix. Base reduction info off
+ info_for_reduction. Remove special handling of
+ early-break/peeled, restore original vector def gathering.
+ Make sure to pick the correct exit PHIs.
+ (vectorizable_live_operation): Pass in the proper stmt_info
+ for early break exits.
+
+2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
+ out-of-class definitions of static constants.
+
+2024-03-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114249
+ * tree-vect-slp.cc (vect_build_slp_instance): Move making
+ a BB reduction lane number even ...
+ (vect_slp_check_for_roots): ... here to avoid leaking
+ pattern defs.
+
+2024-03-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114246
+ * tree-ssa-dse.cc (increment_start_addr): Strip useless
+ type conversions from the adjusted address.
+
+2024-03-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/114190
+ * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
+ Call df_remove_problem for df_note before calling df_analyze.
+
+2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
+ Indu Bhagat <indu.bhagat@oracle.com>
+
+ PR debug/114186
+ * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
+ in the correct order of the dimensions.
+ (gen_ctf_subrange_type): Refactor out handling of
+ DW_TAG_subrange_type DIE to here.
+
+2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR sanitizer/97696
+ * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
+
+2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
+ and luti_strided.
+ * config/aarch64/aarch64-sme.md
+ (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
+ (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
+ (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
+ * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
+ (early_ra::maybe_convert_to_strided_access): Remove support for
+ strided LUTI2 and LUTI4.
+
+2024-03-05 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/113510
+ * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
+ low_register_operand.
+
+2024-03-05 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
+ in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
+ to "X = Y, X o= CST".
+
+2024-03-05 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
+ s9 as an alias of r22.
+
+2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/avr/avr-protos.h (avr_out_insv): New proto.
+ * config/avr/avr.cc (avr_out_insv): New function.
+ (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
+ (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
+ * config/avr/avr.md (define_attr "adjust_len") Add insv.
+ (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
+ Add constraint alternative where the 3rd operand is a power
+ of 2, and the source register may differ from the destination.
+ (*insv.any_shift.<mode>_split): Call avr_out_insv to output
+ instructions. Set attr "length" to "insv".
+ * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
+
+2024-03-05 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114231
+ * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
+ processing a BB SLP root.
+
+2024-03-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/114211
+ * lower-subreg.cc (resolve_simple_move): For double-word
+ rotates by BITS_PER_WORD if there is overlap between source
+ and destination use a temporary.
+
+2024-03-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114157
+ * gimple-lower-bitint.cc: Include stor-layout.h.
+ (mergeable_op): Return true for BIT_FIELD_REF.
+ (struct bitint_large_huge): Declare handle_bit_field_ref method.
+ (bitint_large_huge::handle_bit_field_ref): New method.
+ (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
+
+2024-03-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114116
+ * config/i386/i386.h (enum call_saved_registers_type): Add
+ TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
+ * config/i386/i386-options.cc (ix86_set_func_type): Remove
+ has_no_callee_saved_registers variable, add no_callee_saved_registers
+ instead, initialize it depending on whether it is
+ no_callee_saved_registers function or not. Don't set it if
+ no_caller_saved_registers attribute is present. Adjust users.
+ * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
+ TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
+ TYPE_NO_CALLEE_SAVED_REGISTERS.
+ (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
+
+2024-03-05 Pan Li <pan2.li@intel.com>
+
+ * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
+ mode_size related code.
+
+2024-03-05 Patrick Palka <ppalka@redhat.com>
+
+ * doc/invoke.texi (-Wno-global-module): Document.
+
+2024-03-04 David Faust <david.faust@oracle.com>
+
+ * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
+ * config/bpf/bpf.cc (bpf_expand_setmem): New.
+ * config/bpf/bpf.md (setmemdi): New define_expand.
+
+2024-03-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/113010
+ * combine.cc (simplify_comparison): Guard the
+ WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
+ and initialize inner_mode.
+
+2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
+ VMLALDAVAXQ_U cases.
+ (VMLALDAVXQ): Remove iterator.
+ (VMLALDAVXQ_P): Likewise.
+ (VMLALDAVAXQ): Likewise.
+ * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
+ mode iterator attribute with V4BI mode.
+ * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
+ VMLALDAVAXQ_U): Remove unused unspecs.
+
+2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
+ * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
+ attribute.
+ * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
+ vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
+ vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
+ vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
+ vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
+ vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
+ vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
+ vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
+ vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
+ vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
+
+2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
+
+ * config/arm/arm.md (mve_unpredicated_insn): New attribute.
+ * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
+ (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
+ (MVE_VPT_PREDICABLE_INSN_P): Likewise.
+ * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
+ * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
+ (arm_vcx1q<a>v16qi): Likewise.
+ (arm_vcx1qav16qi): Likewise.
+ (arm_vcx1qv16qi): Likewise.
+ (arm_vcx2q<a>_p_v16qi): Likewise.
+ (arm_vcx2q<a>v16qi): Likewise.
+ (arm_vcx2qav16qi): Likewise.
+ (arm_vcx2qv16qi): Likewise.
+ (arm_vcx3q<a>_p_v16qi): Likewise.
+ (arm_vcx3q<a>v16qi): Likewise.
+ (arm_vcx3qav16qi): Likewise.
+ (arm_vcx3qv16qi): Likewise.
+ (@mve_<mve_insn>q_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q_<supf>v4si): Likewise.
+ (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q_f<mode>): Likewise.
+ (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q_m_f<mode>): Likewise.
+ (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
+ (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
+ (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
+ (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
+ (mve_v<absneg_str>q_f<mode>): Likewise.
+ (mve_<mve_addsubmul>q<mode>): Likewise.
+ (mve_<mve_addsubmul>q_f<mode>): Likewise.
+ (mve_vadciq_<supf>v4si): Likewise.
+ (mve_vadciq_m_<supf>v4si): Likewise.
+ (mve_vadcq_<supf>v4si): Likewise.
+ (mve_vadcq_m_<supf>v4si): Likewise.
+ (mve_vandq_<supf><mode>): Likewise.
+ (mve_vandq_f<mode>): Likewise.
+ (mve_vandq_m_<supf><mode>): Likewise.
+ (mve_vandq_m_f<mode>): Likewise.
+ (mve_vandq_s<mode>): Likewise.
+ (mve_vandq_u<mode>): Likewise.
+ (mve_vbicq_<supf><mode>): Likewise.
+ (mve_vbicq_f<mode>): Likewise.
+ (mve_vbicq_m_<supf><mode>): Likewise.
+ (mve_vbicq_m_f<mode>): Likewise.
+ (mve_vbicq_m_n_<supf><mode>): Likewise.
+ (mve_vbicq_n_<supf><mode>): Likewise.
+ (mve_vbicq_s<mode>): Likewise.
+ (mve_vbicq_u<mode>): Likewise.
+ (@mve_vclzq_s<mode>): Likewise.
+ (mve_vclzq_u<mode>): Likewise.
+ (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
+ (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
+ (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
+ (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
+ (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
+ (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
+ (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
+ (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
+ (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
+ (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
+ (mve_vcvtaq_<supf><mode>): Likewise.
+ (mve_vcvtaq_m_<supf><mode>): Likewise.
+ (mve_vcvtbq_f16_f32v8hf): Likewise.
+ (mve_vcvtbq_f32_f16v4sf): Likewise.
+ (mve_vcvtbq_m_f16_f32v8hf): Likewise.
+ (mve_vcvtbq_m_f32_f16v4sf): Likewise.
+ (mve_vcvtmq_<supf><mode>): Likewise.
+ (mve_vcvtmq_m_<supf><mode>): Likewise.
+ (mve_vcvtnq_<supf><mode>): Likewise.
+ (mve_vcvtnq_m_<supf><mode>): Likewise.
+ (mve_vcvtpq_<supf><mode>): Likewise.
+ (mve_vcvtpq_m_<supf><mode>): Likewise.
+ (mve_vcvtq_from_f_<supf><mode>): Likewise.
+ (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
+ (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
+ (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
+ (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
+ (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
+ (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
+ (mve_vcvtq_to_f_<supf><mode>): Likewise.
+ (mve_vcvttq_f16_f32v8hf): Likewise.
+ (mve_vcvttq_f32_f16v4sf): Likewise.
+ (mve_vcvttq_m_f16_f32v8hf): Likewise.
+ (mve_vcvttq_m_f32_f16v4sf): Likewise.
+ (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
+ (mve_vdwdupq_wb_u<mode>_insn): Likewise.
+ (mve_veorq_s><mode>): Likewise.
+ (mve_veorq_u><mode>): Likewise.
+ (mve_veorq_f<mode>): Likewise.
+ (mve_vidupq_m_wb_u<mode>_insn): Likewise.
+ (mve_vidupq_u<mode>_insn): Likewise.
+ (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
+ (mve_viwdupq_wb_u<mode>_insn): Likewise.
+ (mve_vldrbq_<supf><mode>): Likewise.
+ (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
+ (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
+ (mve_vldrbq_z_<supf><mode>): Likewise.
+ (mve_vldrdq_gather_base_<supf>v2di): Likewise.
+ (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
+ (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
+ (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
+ (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
+ (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
+ (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
+ (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
+ (mve_vldrhq_<supf><mode>): Likewise.
+ (mve_vldrhq_fv8hf): Likewise.
+ (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
+ (mve_vldrhq_gather_offset_fv8hf): Likewise.
+ (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
+ (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
+ (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
+ (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
+ (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
+ (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
+ (mve_vldrhq_z_<supf><mode>): Likewise.
+ (mve_vldrhq_z_fv8hf): Likewise.
+ (mve_vldrwq_<supf>v4si): Likewise.
+ (mve_vldrwq_fv4sf): Likewise.
+ (mve_vldrwq_gather_base_<supf>v4si): Likewise.
+ (mve_vldrwq_gather_base_fv4sf): Likewise.
+ (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
+ (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
+ (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
+ (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
+ (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
+ (mve_vldrwq_gather_base_z_fv4sf): Likewise.
+ (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
+ (mve_vldrwq_gather_offset_fv4sf): Likewise.
+ (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
+ (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
+ (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
+ (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
+ (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
+ (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
+ (mve_vldrwq_z_<supf>v4si): Likewise.
+ (mve_vldrwq_z_fv4sf): Likewise.
+ (mve_vmvnq_s<mode>): Likewise.
+ (mve_vmvnq_u<mode>): Likewise.
+ (mve_vornq_<supf><mode>): Likewise.
+ (mve_vornq_f<mode>): Likewise.
+ (mve_vornq_m_<supf><mode>): Likewise.
+ (mve_vornq_m_f<mode>): Likewise.
+ (mve_vornq_s<mode>): Likewise.
+ (mve_vornq_u<mode>): Likewise.
+ (mve_vorrq_<supf><mode>): Likewise.
+ (mve_vorrq_f<mode>): Likewise.
+ (mve_vorrq_m_<supf><mode>): Likewise.
+ (mve_vorrq_m_f<mode>): Likewise.
+ (mve_vorrq_m_n_<supf><mode>): Likewise.
+ (mve_vorrq_n_<supf><mode>): Likewise.
+ (mve_vorrq_s<mode>): Likewise.
+ (mve_vorrq_s<mode>): Likewise.
+ (mve_vsbciq_<supf>v4si): Likewise.
+ (mve_vsbciq_m_<supf>v4si): Likewise.
+ (mve_vsbcq_<supf>v4si): Likewise.
+ (mve_vsbcq_m_<supf>v4si): Likewise.
+ (mve_vshlcq_<supf><mode>): Likewise.
+ (mve_vshlcq_m_<supf><mode>): Likewise.
+ (mve_vshrq_m_n_<supf><mode>): Likewise.
+ (mve_vshrq_n_<supf><mode>): Likewise.
+ (mve_vstrbq_<supf><mode>): Likewise.
+ (mve_vstrbq_p_<supf><mode>): Likewise.
+ (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
+ (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
+ (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
+ (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
+ (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
+ (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
+ (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
+ (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
+ (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
+ (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
+ (mve_vstrhq_<supf><mode>): Likewise.
+ (mve_vstrhq_fv8hf): Likewise.
+ (mve_vstrhq_p_<supf><mode>): Likewise.
+ (mve_vstrhq_p_fv8hf): Likewise.
+ (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
+ (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
+ (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
+ (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
+ (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
+ (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
+ (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
+ (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
+ (mve_vstrwq_<supf>v4si): Likewise.
+ (mve_vstrwq_fv4sf): Likewise.
+ (mve_vstrwq_p_<supf>v4si): Likewise.
+ (mve_vstrwq_p_fv4sf): Likewise.
+ (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
+ (mve_vstrwq_scatter_base_fv4sf): Likewise.
+ (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
+ (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
+ (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
+ (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
+ (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
+ (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
+ (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
+ (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
+ (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
+ (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
+ (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
+ (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
+ (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
+ (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
+
+2024-03-04 Marek Polacek <polacek@redhat.com>
+
+ * doc/extend.texi: Update [[gnu::no_dangling]].
+
+2024-03-04 Andrew Stubbs <ams@baylibre.com>
+
+ * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
+ * expr.cc (store_constructor): Likewise.
+ (do_store_flag): Likewise.
+
+2024-03-04 Mark Wielaard <mark@klomp.org>
+
+ * common.opt.urls: Regenerate.
+ * config/avr/avr.opt.urls: Likewise.
+ * config/i386/i386.opt.urls: Likewise.
+ * config/pru/pru.opt.urls: Likewise.
+ * config/riscv/riscv.opt.urls: Likewise.
+ * config/rs6000/rs6000.opt.urls: Likewise.
+
+2024-03-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114197
+ * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
+ there are volatile bitfield accesses.
+ (pass_if_conversion::execute): Throw away result if the
+ if-converted and original loops are not nested as expected.
+
+2024-03-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114164
+ * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
+ the code generated for mask argument setup is not supported.
+
+2024-03-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114203
+ * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
+ adjustment before making the result defined at zero.
+
+2024-03-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114192
+ * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
+ appropriate def for the live out stmt in case of an alternate
+ exit.
+
+2024-03-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114209
+ * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
+ unshare_expr when creating a MEM_REF from MEM_REF.
+ (bitint_large_huge::lower_stmt): Call unshare_expr.
+
+2024-03-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114184
+ * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
+ is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
+ register.
+
+2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR target/114187
+ * simplify-rtx.cc (simplify_context::simplify_subreg): Call
+ lowpart_subreg to perform type conversion, to avoid confusion
+ over the offset to use in the call to simplify_reg_subreg.
+
+2024-03-03 Greg McGary <gkm@rivosinc.com>
+
+ PR rtl-optimization/113010
+ * combine.cc (simplify_comparison): Simplify a SUBREG on
+ WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
+ MEM load.
+
+2024-03-03 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
+ Use bool in place of int for boolean logic (if possible).
+ Move declarations to definitions (if possible).
+ * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
+ * config/avr/avr-dimode.md: Same.
+ * config/avr/constraints.md: Same.
+ * config/avr/predicates.md: Same.
+
+2024-03-03 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/113720
+ * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
+ (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
+ simplify insn RTX using UMUL_HIGHPART rtx_code.
+ (*umuldi3_highpart_const): Remove.
+
+2024-03-03 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/114100
+ * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
+ * config/avr/avr.cc (_reg_unused_after): Make static. And
+ add 3rd argument to skip the current insn.
+ (reg_unused_after): Adjust call of reg_unused_after.
+ (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
+ unneeded frame pointer adjustments.
+
+2024-03-03 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/92729
+ * config/avr/avr.md (define_attr "cc"): Remove.
+ * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
+ from prototype.
+ * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
+ its uses. Add insn argument.
+ (avr_out_plus_symbol): Remove pcc argument and its uses.
+ (avr_out_plus): Remove pcc argument and its uses.
+ Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
+ (avr_out_round): Adjust call of avr_out_plus.
+
+2024-03-03 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
+ from r14-9273.
+
+2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
+
+ PR target/101737
+ * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
+ is not an insn, but e.g. a code label.
+
+2024-03-02 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
+ * config/avr/avr.cc: Use them instead of magic numbers when it
+ means a register number.
+
+2024-03-02 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.cc: Adjust some comments.
+
+2024-03-02 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/114100
+ * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
+ the low part of the frame pointer with 8-bit stack pointer.
+
+2024-03-01 Patrick Palka <ppalka@redhat.com>
+
+ PR c++/104919
+ PR c++/106009
+ * tree-inline.cc (remap_decl): Handle copy_decl returning the
+ original decl.
+ (remap_decls): Handle remap_decl returning the original decl.
+ (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
+ CONST_DECL.
+
+2024-03-01 Jeff Law <jlaw@ventanamicro.com>
+
+ * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
+ type attribute.
+ (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
+ (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
+ (movhi_internal, movqi_internal): Likewise.
+ (movsf_softfloat, movsf_hardfloat): Likewise.
+ (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
+ (movdf_softfloat): Likewise.
+
+2024-03-01 Marek Polacek <polacek@redhat.com>
+
+ PR c++/110358
+ PR c++/109642
+ * doc/extend.texi: Document gnu::no_dangling.
+ * doc/invoke.texi: Mention that gnu::no_dangling disables
+ -Wdangling-reference.
+
+2024-03-01 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.opt: Overhaul help screen.
+
+2024-03-01 Jakub Jelinek <jakub@redhat.com>
+ Tobias Burnus <tburnus@baylibre.com>
+
+ PR c++/110347
+ * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
+ lang_hooks.decls.omp_disregard_value_expr for
+ (first)private in target regions.
+
+2024-03-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114136
+ * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
+ n_named_args initially before INIT_CUMULATIVE_ARGS to
+ structure_value_addr_parm rather than 0, after it don't modify
+ it if strict_argument_naming and clear only if
+ !pretend_outgoing_varargs_named.
+
+2024-03-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/114015
+ * dwarf2out.cc (should_move_die_to_comdat): Return false for
+ aggregates without DW_AT_byte_size attribute or with non-constant
+ DW_AT_byte_size.
+
+2024-03-01 Georg-Johann Lay <avr@gjlay.de>
+
+ * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
+ valid values for level.
+
+2024-03-01 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/114070
+ * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
+ Allow the folding if before lowering and the current IL
+ isn't supported with vcond_mask.
+
+2024-03-01 xuli <xuli1@eswincomputing.com>
+
+ * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
+ attribute to riscv_attribute_table.
+ (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
+ (riscv_fntype_abi): Add riscv_vector_cc attribute check.
+ * doc/extend.texi: Add riscv_vector_cc attribute description.
+
+2024-03-01 Pan Li <pan2.li@intel.com>
+
+ PR target/112817
+ * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
+ RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
+ * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
+ (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
+ * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
+ comments for option replacement.
+ * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
+ riscv_autovec_preference to rvv_vector_bits.
+ (vls_mode_valid_p): Ditto.
+ (estimated_poly_value): Ditto.
+ * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
+ vector chunks and honor new option mrvv-vector-bits.
+ (riscv_override_options_internal): Update comments and rename the
+ vector chunks.
+ * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
+ internal option param=riscv-autovec-preference.
+
+2024-03-01 Jakub Jelinek <jakub@redhat.com>
+
+ * function.cc (assign_parms): Only call assign_parms_setup_varargs
+ early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
+
+2024-03-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114156
+ * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
+ rhs1 of a VCE to have no underlying variable if it is a load and
+ handle that case.
+
+2024-02-29 David Malcolm <dmalcolm@redhat.com>
+
+ PR analyzer/114159
+ * function.cc (function_name): Make param const.
+ * function.h (function_name): Likewise.
+
+2024-02-29 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/114100
+ * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
+ * config/avr/avr.opt (-mfuse-add=): New target option.
+ * common/config/avr/avr-common.cc (avr_option_optimization_table)
+ [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
+ [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
+ * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
+ * config/avr/avr-protos.h (avr_split_tiny_move)
+ (make_avr_pass_fuse_add): New protos.
+ * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
+ avr_split_tiny_move to split indirect memory accesses.
+ (gen_move_clobbercc): New define_expand helper.
+ * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
+ (avr_pass_fuse_add): New class from rtl_opt_pass.
+ (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
+ (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
+ (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
+ of PLUS addressing for AVR_TINY.
+ (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
+ (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
+ (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
+
+2024-02-29 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/114132
+ * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
+ * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
+ (avr_function_arg): Set it.
+ (avr_frame_pointer_required_p): Use it instead of .nregs.
+
+2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
+
+ PR target/108174
+ * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
+ static and mark with GTY.
+
+2024-02-29 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/loongarch.md
+ (loongarch_<crc>_w_<size>_w_extended): New define_insn.
+
+2024-02-29 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/loongarch.md (CRC): New define_int_iterator.
+ (crc): New define_int_attr.
+ (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
+ into ...
+ (loongarch_<crc>_w_<size>_w): ... here.
+
+2024-02-29 Kito Cheng <kito.cheng@sifive.com>
+
+ PR target/114130
+ * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
+ extend the expected value if needed.
+
+2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
+
+ * config.gcc (target_gtfiles): Change coreout to btfext-out.
+ (extra_objs): Change coreout to btfext-out.
+ * config/bpf/coreout.cc: Rename to btfext-out.cc.
+ * config/bpf/btfext-out.cc: Add.
+ * config/bpf/coreout.h: Rename to btfext-out.h.
+ * config/bpf/btfext-out.h: Add.
+ * config/bpf/core-builtins.cc: Change include.
+ * config/bpf/core-builtins.h: Change include.
+ * config/bpf/t-bpf: Accomodate renamed files.
+
+2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
+
+ PR target/113453
+ * config/bpf/bpf.cc (bpf_function_prologue): Define target
+ hook.
+ * config/bpf/coreout.cc (brf_ext_info_section)
+ (btf_ext_info): Move from coreout.h
+ (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
+ (bpf_core_reloc): Rename to btf_ext_core_reloc.
+ (btf_ext): Add static variable.
+ (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
+ (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
+ (btf_ext_add_string, btf_funcinfo_type_callback)
+ (btf_add_func_info_for, btf_validate_funcinfo)
+ (btf_ext_info_len, output_btfext_func_info): Add function.
+ (output_btfext_header, bpf_core_reloc_add)
+ (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
+ Change to support new structs.
+ * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
+ Move and change in coreout.cc.
+ (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
+
+2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
+
+ * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
+ enabled by default for BPF.
+ (bpf_file_end): Call BTF deallocation.
+ (bpf_asm_init_sections): Correct condition.
+ * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
+ deallocation.
+ (ctf_debuf_finish): Correct condition for calling
+ ctf_debug_finalize.
+
+2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
+
+ * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
+ (traverse_btf_func_types): Define function.
+ * ctfc.h (funcs_traverse_callback): Typedef for function
+ prototype.
+ (traverse_btf_func_types): Add prototype.
+
+2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
+
+ * btfout.cc (btf_collect_dataset): Corrects BTF type id.
+
+2024-02-28 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/113831
+ PR tree-optimization/108355
+ * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
+ PR113831 fix.
+
+2024-02-28 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114121
+ * tree-ssa-sccvn.h (vn_reference_s::offset,
+ vn_reference_s::max_size): New fields.
+ (vn_reference_insert_pieces): Adjust prototype.
+ * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
+ * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
+ size, allow using "don't know" state.
+ (vn_walk_cb_data::finish): Pass along offset/max_size.
+ (vn_reference_lookup_or_insert_for_pieces): Take offset and
+ max_size as argument and use it.
+ (vn_reference_lookup_3): Properly adjust offset and max_size
+ according to the adjusted ao_ref.
+ (vn_reference_lookup_pieces): Initialize offset and max_size.
+ (vn_reference_lookup): Likewise.
+ (vn_reference_lookup_call): Likewise.
+ (vn_reference_insert): Likewise.
+ (visit_reference_op_call): Likewise.
+ (vn_reference_insert_pieces): Take offset and max_size
+ as argument and use it.
+
+2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
+
+ PR tree-optimization/114075
+ * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
+ point vectors
+
+2024-02-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/114041
+ * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
+ INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
+
+2024-02-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/113988
+ * stor-layout.h (bitwise_mode_for_size): Declare.
+ * stor-layout.cc (bitwise_mode_for_size): New function.
+ * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
+ Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
+ Use BITS_PER_UNIT instead of 8.
+
+2024-02-27 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/113871
+ * config/i386/mmx.md (V248FI): Add V2BF mode.
+ (V24FI_32): Ditto.
+
+2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
+
+ * tree-ssa-dse.cc (compute_trims): Fix description. Return early
+ if either ref->offset is not byte aligned or ref->size is not known
+ to be equal to ref->max_size.
+ (maybe_trim_complex_store): Fix description.
+ (maybe_trim_constructor_store): Likewise.
+ (maybe_trim_partially_dead_store): Likewise.
+
+2024-02-27 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/mmintrin.h: Warn if this header is included without
+ defining __ENABLE_DEPRECATED_IWMMXT.
+
+2024-02-27 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114074
+ * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
+ * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
+ Handle poly vs. non-poly multiplication correctly with respect
+ to undefined behavior on overflow.
+
+2024-02-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/114044
+ * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
+ DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
+ * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
+ expand_PARITY): Declare.
+ * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
+ expand_CTZ, expand_FFS, expand_PARITY): New functions.
+ (expand_POPCOUNT): Use expand_bitquery.
+
+2024-02-27 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114081
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Perform manual dominator update for prologue peeling.
+ (vect_do_peeling): Properly update dominators after adding the
+ prologue-around guard.
+
+2024-02-26 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
+ (mstrict-X): Tag as "Optimization".
+
+2024-02-26 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
+ an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
+
+2024-02-26 Jakub Jelinek <jakub@redhat.com>
+ H.J. Lu <hjl.tools@gmail.com>
+
+ PR rtl-optimization/113617
+ * varasm.cc (default_elf_select_rtx_section): For
+ references to private symbols in comdat sections
+ use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
+ or .rodata.<comdat> comdat sections.
+
+2024-02-26 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114099
+ * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+ Create and fill in a needed virtual LC PHI for the alternate
+ exits. Remove code dealing with that missing.
+
+2024-02-26 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/114068
+ * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
+ New function.
+ (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
+ on the main exit if needed. Remove band-aid for the case
+ it was missing.
+
+2024-02-26 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/114097
+ * config/i386/i386-options.cc (ix86_set_func_type): Check
+ interrupt instead of noreturn attribute.
+
+2024-02-26 Jakub Jelinek <jakub@redhat.com>
+
+ * config/i386/i386.cc (ix86_bitint_type_info): Add support for
+ !TARGET_64BIT.
+
+2024-02-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/114090
+ * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
+ Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
+ types.
+ ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
+
+2024-02-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114084
+ * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
+ if all subtrees of var0 come from one of the op0 or op1 operands
+ and all subtrees of con0 come from the other one. Don't clear
+ variables which are never used afterwards.
+
+2024-02-26 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/114070
+ * genmatch.cc (parser::parse_c_expr): Do not record operand
+ lists but only mark operators used.
+ * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
+ Properly guard the case of tcc_comparison changing the VEC_COND
+ value operand type.
+
+2024-02-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/114094
+ * config/i386/i386.cc (x86_function_profiler): Add missing new-line
+ to printed instruction.
+
+2024-02-26 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/114098
+ * config/i386/amxtileintrin.h (_tile_loadconfig): Use
+ __builtin_ia32_ldtilecfg.
+ (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
+ * config/i386/i386-builtin.def (BDESC): Add
+ __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
+ * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
+ IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
+ * config/i386/i386.md (ldtilecfg): New pattern.
+ (sttilecfg): Likewise.
+
2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/113205
projects / thirdparty / gcc.git / blobdiff