/* Machine description for AArch64 architecture.
- Copyright (C) 2012-2016 Free Software Foundation, Inc.
+ Copyright (C) 2012-2020 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GCC.
10 - CODE_FOR_<name><mode>. */
BUILTIN_VDC (COMBINE, combine, 0)
+ VAR1 (COMBINEP, combine, 0, di)
BUILTIN_VB (BINOP, pmul, 0)
BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0)
BUILTIN_VHSDF_DF (UNOP, sqrt, 2)
BUILTIN_VDC (GETREG, get_dregoi, 0)
BUILTIN_VDC (GETREG, get_dregci, 0)
BUILTIN_VDC (GETREG, get_dregxi, 0)
+ VAR1 (GETREGP, get_dregoi, 0, di)
+ VAR1 (GETREGP, get_dregci, 0, di)
+ VAR1 (GETREGP, get_dregxi, 0, di)
/* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */
BUILTIN_VQ (GETREG, get_qregoi, 0)
BUILTIN_VQ (GETREG, get_qregci, 0)
BUILTIN_VQ (GETREG, get_qregxi, 0)
+ VAR1 (GETREGP, get_qregoi, 0, v2di)
+ VAR1 (GETREGP, get_qregci, 0, v2di)
+ VAR1 (GETREGP, get_qregxi, 0, v2di)
/* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */
BUILTIN_VQ (SETREG, set_qregoi, 0)
BUILTIN_VQ (SETREG, set_qregci, 0)
BUILTIN_VQ (SETREG, set_qregxi, 0)
+ VAR1 (SETREGP, set_qregoi, 0, v2di)
+ VAR1 (SETREGP, set_qregci, 0, v2di)
+ VAR1 (SETREGP, set_qregxi, 0, v2di)
+ /* Implemented by aarch64_ld1x2<VQ:mode>. */
+ BUILTIN_VQ (LOADSTRUCT, ld1x2, 0)
+ /* Implemented by aarch64_ld1x2<VDC:mode>. */
+ BUILTIN_VDC (LOADSTRUCT, ld1x2, 0)
/* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */
BUILTIN_VDC (LOADSTRUCT, ld2, 0)
BUILTIN_VDC (LOADSTRUCT, ld3, 0)
BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
+ /* Implemented by aarch64_<sur><dotprod>{_lane}{q}<dot_mode>. */
+ BUILTIN_VB (TERNOP, sdot, 0)
+ BUILTIN_VB (TERNOPU, udot, 0)
+ BUILTIN_VB (QUADOP_LANE, sdot_lane, 0)
+ BUILTIN_VB (QUADOPU_LANE, udot_lane, 0)
+ BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0)
+ BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0)
+
+ /* Implemented by aarch64_fcadd<rot><mode>. */
+ BUILTIN_VHSDF (BINOP, fcadd90, 0)
+ BUILTIN_VHSDF (BINOP, fcadd270, 0)
+
+ /* Implemented by aarch64_fcmla{_lane}{q}<rot><mode>. */
+ BUILTIN_VHSDF (TERNOP, fcmla0, 0)
+ BUILTIN_VHSDF (TERNOP, fcmla90, 0)
+ BUILTIN_VHSDF (TERNOP, fcmla180, 0)
+ BUILTIN_VHSDF (TERNOP, fcmla270, 0)
+ BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0)
+ BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0)
+ BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0)
+ BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0)
+
+ BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0)
+ BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0)
+ BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0)
+ BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0)
+
BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
VAR1 (SHIFTIMM, ashr_simd, 0, di)
BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
+ VAR2 (SHIFTINSERTP, ssli_n, 0, di, v2di)
BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
/* Implemented by aarch64_<sur>qshl<u>_n<mode>. */
BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
BUILTIN_VB (UNOP, rbit, 0)
/* Implemented by
- aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */
+ aarch64_<PERMUTE:perm_insn><mode>. */
BUILTIN_VALL (BINOP, zip1, 0)
BUILTIN_VALL (BINOP, zip2, 0)
BUILTIN_VALL (BINOP, uzp1, 0)
BUILTIN_VALL (BINOP, trn1, 0)
BUILTIN_VALL (BINOP, trn2, 0)
- /* Implemented by
- aarch64_frecp<FRECP:frecp_suffix><mode>. */
BUILTIN_GPF_F16 (UNOP, frecpe, 0)
BUILTIN_GPF_F16 (UNOP, frecpx, 0)
/* Implemented by aarch64_ld1<VALL_F16:mode>. */
BUILTIN_VALL_F16 (LOAD1, ld1, 0)
+ VAR1(STORE1P, ld1, 0, v2di)
/* Implemented by aarch64_st1<VALL_F16:mode>. */
BUILTIN_VALL_F16 (STORE1, st1, 0)
+ VAR1(STORE1P, st1, 0, v2di)
+
+ /* Implemented by aarch64_ld1x3<VALLDIF:mode>. */
+ BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0)
+
+ /* Implemented by aarch64_ld1x4<VALLDIF:mode>. */
+ BUILTIN_VALLDIF (LOADSTRUCT, ld1x4, 0)
+
+ /* Implemented by aarch64_st1x2<VALLDIF:mode>. */
+ BUILTIN_VALLDIF (STORESTRUCT, st1x2, 0)
+
+ /* Implemented by aarch64_st1x3<VALLDIF:mode>. */
+ BUILTIN_VALLDIF (STORESTRUCT, st1x3, 0)
+
+ /* Implemented by aarch64_st1x4<VALLDIF:mode>. */
+ BUILTIN_VALLDIF (STORESTRUCT, st1x4, 0)
/* Implemented by fma<mode>4. */
BUILTIN_VHSDF (TERNOP, fma, 4)
/* Implemented by aarch64_simd_bsl<mode>. */
BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
+ VAR2 (BSL_P, simd_bsl,0, di, v2di)
BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
BUILTIN_GPI (UNOP, fix_truncdf, 2)
BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
- BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
\ No newline at end of file
+ BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
+
+ /* Implemented by aarch64_sm3ss1qv4si. */
+ VAR1 (TERNOPU, sm3ss1q, 0, v4si)
+ /* Implemented by aarch64_sm3tt<sm3tt_op>qv4si. */
+ VAR1 (QUADOPUI, sm3tt1aq, 0, v4si)
+ VAR1 (QUADOPUI, sm3tt1bq, 0, v4si)
+ VAR1 (QUADOPUI, sm3tt2aq, 0, v4si)
+ VAR1 (QUADOPUI, sm3tt2bq, 0, v4si)
+ /* Implemented by aarch64_sm3partw<sm3part_op>qv4si. */
+ VAR1 (TERNOPU, sm3partw1q, 0, v4si)
+ VAR1 (TERNOPU, sm3partw2q, 0, v4si)
+ /* Implemented by aarch64_sm4eqv4si. */
+ VAR1 (BINOPU, sm4eq, 0, v4si)
+ /* Implemented by aarch64_sm4ekeyqv4si. */
+ VAR1 (BINOPU, sm4ekeyq, 0, v4si)
+ /* Implemented by aarch64_crypto_sha512hqv2di. */
+ VAR1 (TERNOPU, crypto_sha512hq, 0, v2di)
+ /* Implemented by aarch64_sha512h2qv2di. */
+ VAR1 (TERNOPU, crypto_sha512h2q, 0, v2di)
+ /* Implemented by aarch64_crypto_sha512su0qv2di. */
+ VAR1 (BINOPU, crypto_sha512su0q, 0, v2di)
+ /* Implemented by aarch64_crypto_sha512su1qv2di. */
+ VAR1 (TERNOPU, crypto_sha512su1q, 0, v2di)
+ /* Implemented by eor3q<mode>4. */
+ BUILTIN_VQ_I (TERNOPU, eor3q, 4)
+ BUILTIN_VQ_I (TERNOP, eor3q, 4)
+ /* Implemented by aarch64_rax1qv2di. */
+ VAR1 (BINOPU, rax1q, 0, v2di)
+ /* Implemented by aarch64_xarqv2di. */
+ VAR1 (TERNOPUI, xarq, 0, v2di)
+ /* Implemented by bcaxq<mode>4. */
+ BUILTIN_VQ_I (TERNOPU, bcaxq, 4)
+ BUILTIN_VQ_I (TERNOP, bcaxq, 4)
+
+ /* Implemented by aarch64_fml<f16mac1>l<f16quad>_low<mode>. */
+ VAR1 (TERNOP, fmlal_low, 0, v2sf)
+ VAR1 (TERNOP, fmlsl_low, 0, v2sf)
+ VAR1 (TERNOP, fmlalq_low, 0, v4sf)
+ VAR1 (TERNOP, fmlslq_low, 0, v4sf)
+ /* Implemented by aarch64_fml<f16mac1>l<f16quad>_high<mode>. */
+ VAR1 (TERNOP, fmlal_high, 0, v2sf)
+ VAR1 (TERNOP, fmlsl_high, 0, v2sf)
+ VAR1 (TERNOP, fmlalq_high, 0, v4sf)
+ VAR1 (TERNOP, fmlslq_high, 0, v4sf)
+ /* Implemented by aarch64_fml<f16mac1>l_lane_lowv2sf. */
+ VAR1 (QUADOP_LANE, fmlal_lane_low, 0, v2sf)
+ VAR1 (QUADOP_LANE, fmlsl_lane_low, 0, v2sf)
+ /* Implemented by aarch64_fml<f16mac1>l_laneq_lowv2sf. */
+ VAR1 (QUADOP_LANE, fmlal_laneq_low, 0, v2sf)
+ VAR1 (QUADOP_LANE, fmlsl_laneq_low, 0, v2sf)
+ /* Implemented by aarch64_fml<f16mac1>lq_lane_lowv4sf. */
+ VAR1 (QUADOP_LANE, fmlalq_lane_low, 0, v4sf)
+ VAR1 (QUADOP_LANE, fmlslq_lane_low, 0, v4sf)
+ /* Implemented by aarch64_fml<f16mac1>lq_laneq_lowv4sf. */
+ VAR1 (QUADOP_LANE, fmlalq_laneq_low, 0, v4sf)
+ VAR1 (QUADOP_LANE, fmlslq_laneq_low, 0, v4sf)
+ /* Implemented by aarch64_fml<f16mac1>l_lane_highv2sf. */
+ VAR1 (QUADOP_LANE, fmlal_lane_high, 0, v2sf)
+ VAR1 (QUADOP_LANE, fmlsl_lane_high, 0, v2sf)
+ /* Implemented by aarch64_fml<f16mac1>l_laneq_highv2sf. */
+ VAR1 (QUADOP_LANE, fmlal_laneq_high, 0, v2sf)
+ VAR1 (QUADOP_LANE, fmlsl_laneq_high, 0, v2sf)
+ /* Implemented by aarch64_fml<f16mac1>lq_lane_highv4sf. */
+ VAR1 (QUADOP_LANE, fmlalq_lane_high, 0, v4sf)
+ VAR1 (QUADOP_LANE, fmlslq_lane_high, 0, v4sf)
+ /* Implemented by aarch64_fml<f16mac1>lq_laneq_highv4sf. */
+ VAR1 (QUADOP_LANE, fmlalq_laneq_high, 0, v4sf)
+ VAR1 (QUADOP_LANE, fmlslq_laneq_high, 0, v4sf)
+
+ /* Implemented by aarch64_<frintnzs_op><mode>. */
+ BUILTIN_VSFDF (UNOP, frint32z, 0)
+ BUILTIN_VSFDF (UNOP, frint32x, 0)
+ BUILTIN_VSFDF (UNOP, frint64z, 0)
+ BUILTIN_VSFDF (UNOP, frint64x, 0)
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