; Options for the Synopsys DesignWare ARC port of the compiler
;
-; Copyright (C) 2005-2017 Free Software Foundation, Inc.
+; Copyright (C) 2005-2021 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
config/arc/arc-opts.h
mbig-endian
-Target Report RejectNegative Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Compile code for big endian mode.
mlittle-endian
-Target Report RejectNegative InverseMask(BIG_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN)
Compile code for little endian mode. This is the default.
mno-cond-exec
-Target Report RejectNegative Mask(NO_COND_EXEC)
+Target RejectNegative Mask(NO_COND_EXEC)
Disable ARCompact specific pass to generate conditional execution instructions.
mA6
-Target Report
+Target
Generate ARCompact 32-bit code for ARC600 processor.
mARC600
-Target Report
+Target
Same as -mA6.
mARC601
-Target Report
+Target
Generate ARCompact 32-bit code for ARC601 processor.
mA7
-Target Report
+Target
Generate ARCompact 32-bit code for ARC700 processor.
mARC700
-Target Report
+Target
Same as -mA7.
+mjli-always
+Target Mask(JLI_ALWAYS)
+Force all calls to be made via a jli instruction.
+
mmpy-option=
Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
--mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
+-mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
Enum
Name(arc_mpy) Type(int)
Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
mdiv-rem
-Target Report Mask(DIVREM)
+Target Mask(DIVREM)
Enable DIV-REM instructions for ARCv2.
mcode-density
-Target Report Mask(CODE_DENSITY)
+Target Mask(CODE_DENSITY)
Enable code density instructions for ARCv2.
mmixed-code
-Target Report Mask(MIXED_CODE_SET)
+Target Mask(MIXED_CODE_SET)
Tweak register allocation to help 16-bit instruction generation.
; originally this was:
;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
; We use an explict definition for the negative form because that is the
; actually interesting option, and we want that to have its own comment.
mvolatile-cache
-Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
+Target RejectNegative Mask(VOLATILE_CACHE_SET)
Use ordinarily cached memory accesses for volatile references.
mno-volatile-cache
-Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
+Target RejectNegative InverseMask(VOLATILE_CACHE_SET)
Enable cache bypass for volatile references.
mbarrel-shifter
-Target Report Mask(BARREL_SHIFTER)
+Target Mask(BARREL_SHIFTER)
Generate instructions supported by barrel shifter.
mnorm
-Target Report Mask(NORM_SET)
+Target Mask(NORM_SET)
Generate norm instruction.
mswap
-Target Report Mask(SWAP_SET)
+Target Mask(SWAP_SET)
Generate swap instruction.
mmul64
-Target Report Mask(MUL64_SET)
+Target Mask(MUL64_SET)
Generate mul64 and mulu64 instructions.
mno-mpy
-Target Report Mask(NOMPY_SET) Warn(%qs is deprecated)
+Target Mask(NOMPY_SET) Warn(%qs is deprecated)
Do not generate mpy instructions for ARC700.
mea
-Target Report Mask(EA_SET)
-Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported.
+Target Mask(EA_SET)
+Generate extended arithmetic instructions, only valid for ARC700.
msoft-float
-Target Report Mask(0)
+Target Mask(0)
Dummy flag. This is the default unless FPX switches are provided explicitly.
mlong-calls
-Target Report Mask(LONG_CALLS_SET)
+Target Mask(LONG_CALLS_SET)
Generate call insns as register indirect calls.
mno-brcc
-Target Report Mask(NO_BRCC_SET)
+Target Mask(NO_BRCC_SET)
Do no generate BRcc instructions in arc_reorg.
msdata
-Target Report InverseMask(NO_SDATA_SET)
+Target InverseMask(NO_SDATA_SET)
Generate sdata references. This is the default, unless you compile for PIC.
-mno-millicode
-Target Report Mask(NO_MILLICODE_THUNK_SET)
-Do not generate millicode thunks (needed only with -Os).
+mmillicode
+Target Mask(MILLICODE_THUNK_SET)
+Generate millicode thunks.
mspfp
-Target Report Mask(SPFP_COMPACT_SET)
+Target Mask(SPFP_COMPACT_SET)
FPX: Generate Single Precision FPX (compact) instructions.
mspfp-compact
-Target Report Mask(SPFP_COMPACT_SET) MaskExists
+Target Mask(SPFP_COMPACT_SET) MaskExists
FPX: Generate Single Precision FPX (compact) instructions.
mspfp-fast
-Target Report Mask(SPFP_FAST_SET)
+Target Mask(SPFP_FAST_SET)
FPX: Generate Single Precision FPX (fast) instructions.
margonaut
-Target Report Mask(ARGONAUT_SET)
+Target Mask(ARGONAUT_SET)
FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
mdpfp
-Target Report Mask(DPFP_COMPACT_SET)
+Target Mask(DPFP_COMPACT_SET)
FPX: Generate Double Precision FPX (compact) instructions.
mdpfp-compact
-Target Report Mask(DPFP_COMPACT_SET) MaskExists
+Target Mask(DPFP_COMPACT_SET) MaskExists
FPX: Generate Double Precision FPX (compact) instructions.
mdpfp-fast
-Target Report Mask(DPFP_FAST_SET)
+Target Mask(DPFP_FAST_SET)
FPX: Generate Double Precision FPX (fast) instructions.
mno-dpfp-lrsr
-Target Report Mask(DPFP_DISABLE_LRSR)
+Target Mask(DPFP_DISABLE_LRSR)
Disable LR and SR instructions from using FPX extension aux registers.
msimd
-Target Report Mask(SIMD_SET)
+Target Mask(SIMD_SET)
Enable generation of ARC SIMD instructions via target-specific builtins.
mcpu=
msize-level=
Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
-size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
+Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
misize
-Target Report PchIgnore Var(TARGET_DUMPISIZE)
+Target PchIgnore Var(TARGET_DUMPISIZE)
Annotate assembler instructions with estimated addresses.
mmultcost=
Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
-mtune=ARC600
-Target RejectNegative Var(arc_tune, TUNE_ARC600)
-Tune for ARC600 cpu.
+mtune=
+Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE)
+-mtune=TUNE Tune code for given ARC variant.
+
+Enum
+Name(arc_tune_attr) Type(int)
+
+EnumValue
+Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600)
+
+EnumValue
+Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600)
-mtune=ARC601
-Target RejectNegative Var(arc_tune, TUNE_ARC600)
-Tune for ARC601 cpu.
+EnumValue
+Enum(arc_tune_attr) String(arc7xx) Value(ARC_TUNE_ARC7XX)
+
+EnumValue
+Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD)
-mtune=ARC700
-Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
-Tune for ARC700 R4.2 Cpu with standard multiplier block.
+EnumValue
+Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC)
-mtune=ARC700-xmac
-Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
-Tune for ARC700 R4.2 Cpu with XMAC block.
+EnumValue
+Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC)
-mtune=ARC725D
-Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
-Tune for ARC700 R4.2 Cpu with XMAC block.
+EnumValue
+Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC)
-mtune=ARC750D
-Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
-Tune for ARC700 R4.2 Cpu with XMAC block.
+EnumValue
+Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3)
mindexed-loads
Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
Enable the use of pre/post modify with register displacement.
mmul32x16
-Target Report Mask(MULMAC_32BY16_SET)
+Target Mask(MULMAC_32BY16_SET)
Generate 32x16 multiply and mac instructions.
; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
Use pc-relative switch case tables - this enables case table shortening.
mcompact-casesi
-Target Var(TARGET_COMPACT_CASESI)
+Target Warn(%qs is deprecated)
Enable compact casesi pattern.
mq-class
-Target Var(TARGET_Q_CLASS)
+Target Warn(%qs is deprecated)
Enable 'q' instruction alternatives.
mexpand-adddi
-Target Var(TARGET_EXPAND_ADDDI)
+Target Warn(%qs is deprecated)
Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
; Flags used by the assembler, but for which we define preprocessor
; macro symbols as well.
mcrc
-Target Report Warn(%qs is deprecated)
+Target Warn(%qs is deprecated)
Enable variable polynomial CRC extension.
mdsp-packa
-Target Report Warn(%qs is deprecated)
+Target Warn(%qs is deprecated)
Enable DSP 3.1 Pack A extensions.
mdvbf
-Target Report Warn(%qs is deprecated)
+Target Warn(%qs is deprecated)
Enable dual viterbi butterfly extension.
mmac-d16
-Target Report Undocumented Warn(%qs is deprecated)
+Target Undocumented Warn(%qs is deprecated)
mmac-24
-Target Report Undocumented Warn(%qs is deprecated)
+Target Undocumented Warn(%qs is deprecated)
mtelephony
-Target Report RejectNegative Warn(%qs is deprecated)
+Target RejectNegative Warn(%qs is deprecated)
Enable Dual and Single Operand Instructions for Telephony.
mxy
-Target Report
+Target
Enable XY Memory extension (DSP version 3).
; ARC700 4.10 extension instructions
mlock
-Target Report
+Target
Enable Locked Load/Store Conditional extension.
mswape
-Target Report
+Target
Enable swap byte ordering extension instruction.
mrtsc
-Target Report Warn(%qs is deprecated)
+Target Warn(%qs is deprecated)
Enable 64-bit Time-Stamp Counter extension instruction.
EB
Pass -marclinux_prof option through to linker.
;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
-;Target InverseMask(NO_LRA)
-; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
-; so don't enable by default.
mlra
-Target Mask(LRA)
-Enable lra.
+Target Var(arc_lra_flag) Init(1) Save
+Use LRA instead of reload.
mlra-priority-none
Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
Target RejectNegative Joined
matomic
-Target Report Mask(ATOMIC)
+Target Mask(ATOMIC)
Enable atomic instructions.
mll64
-Target Report Mask(LL64)
+Target Mask(LL64)
Enable double load/store instructions for ARC HS.
mfpu=
Target RejectNegative Var(arc_tp_regno,-1)
mbitops
-Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
+Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
Enable use of NPS400 bit operations.
mcmem
-Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
+Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
Enable use of NPS400 xld/xst extension.
munaligned-access
-Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
+Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
Enable unaligned word and halfword accesses to packed data.
mirq-ctrl-saved=
mrgf-banked-regs=
Target RejectNegative Joined Var(arc_deferred_options) Defer
Specifies the number of registers replicated in second register bank on entry to fast interrupt.
+
+mlpc-width=
+Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
+Sets LP_COUNT register width. Possible values are 8, 16, 20, 24, 28, and 32.
+
+Enum
+Name(arc_lpc) Type(int)
+
+EnumValue
+Enum(arc_lpc) String(8) Value(8)
+
+EnumValue
+Enum(arc_lpc) String(16) Value(16)
+
+EnumValue
+Enum(arc_lpc) String(20) Value(20)
+
+EnumValue
+Enum(arc_lpc) String(24) Value(24)
+
+EnumValue
+Enum(arc_lpc) String(28) Value(28)
+
+EnumValue
+Enum(arc_lpc) String(32) Value(32)
+
+mrf16
+Target Mask(RF16)
+Enable 16-entry register file.
+
+mbranch-index
+Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
+Enable use of BI/BIH instructions when available.
+
+mcode-density-frame
+Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
+Enable ENTER_S and LEAVE_S opcodes for ARCv2.
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