config.gcc (with_fpu): Allow --with-fpu=vfp3.

[thirdparty/gcc.git] / gcc / config / arm / aof.h

diff --git a/gcc/config/arm/aof.h b/gcc/config/arm/aof.h
index e6694dc1bc74571715a8ced40a3b655381a5523b..71d87a520dbd891c924068e050378e6a02f49485 100644 (file)
--- a/gcc/config/arm/aof.h
+++ b/gcc/config/arm/aof.h
@@ -187,7 +187,10 @@ do {                                       \
 #define CTORS_SECTION_ASM_OP "\tAREA\t|C$$gnu_ctorsvec|, DATA, READONLY"
 #define DTORS_SECTION_ASM_OP "\tAREA\t|C$$gnu_dtorsvec|, DATA, READONLY"
 
-/* Output of Assembler Instructions.  */
+/* Output of Assembler Instructions.  Note that the ?xx registers are
+   there so that VFPv3/NEON registers D16-D31 have the same spacing as D0-D15
+   (each of which is overlaid on two S registers), although there are no
+   actual single-precision registers which correspond to D16-D31.  */
 
 #define REGISTER_NAMES                         \
 {                                              \
@@ -210,7 +213,11 @@ do {                                       \
   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  \
   "s8",  "s9",  "s10", "s11", "s12", "s13", "s14", "s15", \
   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
-  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",  \
+  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
+  "d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
+  "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
+  "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
+  "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
   "vfpcc"                                      \
 }