[Arm] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16.

[thirdparty/gcc.git] / gcc / config / arm / arm.h

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 1a5ffea31d5bfd67fc67e4f3cdd1fefe7bfff409..8bf393e620f2db24f506d35d06d45877c801fbb5 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -246,6 +246,15 @@ emission of floating point pcs attributes.  */
 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later.  */
 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA)
 
+/* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions.  */
+#define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm)
+
+/* FPU supports Brain half-precision floating-point (BFloat16) extension.  */
+#define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \
+                       && arm_arch8_2 && arm_arch_bf16)
+#define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \
+                         && arm_arch8_2 && arm_arch_bf16)
+
 /* Q-bit is present.  */
 #define TARGET_ARM_QBIT \
   (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7))
@@ -517,6 +526,12 @@ extern int arm_arch_crc;
 /* Nonzero if chip supports the ARMv8-M Security Extensions.  */
 extern int arm_arch_cmse;
 
+/* Nonzero if chip supports the I8MM instructions.  */
+extern int arm_arch_i8mm;
+
+/* Nonzero if chip supports the BFloat16 instructions.  */
+extern int arm_arch_bf16;
+
 #ifndef TARGET_DEFAULT
 #define TARGET_DEFAULT  (MASK_APCS_FRAME)
 #endif