]
"TARGET_THUMB1"
"add\\t%Q0, %Q0, %Q2\;adc\\t%R0, %R0, %R2"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*arm_adddi3"
operands[2] = gen_lowpart (SImode, operands[2]);
}"
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*adddi_sesidi_di"
operands[2] = gen_lowpart (SImode, operands[2]);
}"
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*adddi_zesidi_di"
operands[2] = gen_lowpart (SImode, operands[2]);
}"
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_expand "addsi3"
operands[3] = GEN_INT (offset);
operands[2] = GEN_INT (INTVAL (operands[2]) - offset);
}
- [(set_attr "length" "2,2,2,2,2,2,2,4,4,4")]
+ [(set_attr "length" "2,2,2,2,2,2,2,4,4,4")
+ (set_attr "type" "alus_imm,alus_imm,alus_reg,alus_reg,alus_reg,
+ alus_reg,alus_reg,multiple,multiple,multiple")]
)
;; Reloading and elimination of the frame pointer can
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "alus_imm,alus_imm,*")]
+ (set_attr "type" "alus_imm,alus_imm,alus_reg")]
)
(define_insn "*addsi3_compare0_scratch"
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "type" "alus_imm,alus_imm,*")
- ]
+ (set_attr "type" "alus_imm,alus_imm,alus_reg")]
)
(define_insn "*compare_negsi_si"
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*")
(set_attr "length" "2,4")
- (set_attr "predicable_short_it" "yes,no")]
+ (set_attr "predicable_short_it" "yes,no")
+ (set_attr "type" "alus_reg")]
)
;; This is the canonicalization of addsi3_compare0_for_combiner when the
"@
add%.\\t%0, %1, %3
sub%.\\t%0, %1, #%n3"
- [(set_attr "conds" "set")]
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_reg")]
)
;; Convert the sequence
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*,*")
(set_attr "length" "4")
- (set_attr "predicable_short_it" "yes,no,no")]
+ (set_attr "predicable_short_it" "yes,no,no")
+ (set_attr "type" "adc_reg,adc_reg,adc_imm")]
)
(define_insn "*addsi3_carryin_alt2_<optab>"
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*,*")
(set_attr "length" "4")
- (set_attr "predicable_short_it" "yes,no,no")]
+ (set_attr "predicable_short_it" "yes,no,no")
+ (set_attr "type" "adc_reg,adc_reg,adc_imm")]
)
(define_insn "*addsi3_carryin_shift_<optab>"
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
"adc%.\\t%0, %1, %2"
- [(set_attr "conds" "set")]
+ [(set_attr "conds" "set")
+ (set_attr "type" "adcs_reg")]
)
(define_insn "*subsi3_carryin"
[(set_attr "conds" "use")
(set_attr "arch" "*,a")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "adc_reg,adc_imm")]
)
(define_insn "*subsi3_carryin_const"
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
"TARGET_32BIT"
"sbc\\t%0, %1, #%B2"
- [(set_attr "conds" "use")]
+ [(set_attr "conds" "use")
+ (set_attr "type" "adc_imm")]
)
(define_insn "*subsi3_carryin_compare"
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
"TARGET_32BIT"
"sbcs\\t%0, %1, %2"
- [(set_attr "conds" "set")]
+ [(set_attr "conds" "set")
+ (set_attr "type" "adcs_reg")]
)
(define_insn "*subsi3_carryin_compare_const"
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
"TARGET_32BIT"
"sbcs\\t%0, %1, #%B2"
- [(set_attr "conds" "set")]
+ [(set_attr "conds" "set")
+ (set_attr "type" "adcs_imm")]
)
(define_insn "*subsi3_carryin_shift"
operands[2] = gen_lowpart (SImode, operands[2]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn "*thumb_subdi3"
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB1"
"sub\\t%Q0, %Q0, %Q2\;sbc\\t%R0, %R0, %R2"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*subdi_di_zesidi"
operands[5] = GEN_INT (~0);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*subdi_di_sesidi"
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*subdi_zesidi_di"
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*subdi_sesidi_di"
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*subdi_zesidi_zesidi"
operands[0] = gen_lowpart (SImode, operands[0]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_expand "subsi3"
"TARGET_THUMB1"
"sub\\t%0, %1, %2"
[(set_attr "length" "2")
- (set_attr "conds" "set")])
+ (set_attr "conds" "set")
+ (set_attr "type" "alus_reg")]
+)
; ??? Check Thumb-2 split length
(define_insn_and_split "*arm_subsi3_insn"
(set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
- (set_attr "type" "*,*,*,*,alu_imm,alu_imm,*,*,alu_imm")]
+ (set_attr "type" "alu_reg,alu_reg,alu_reg,alu_reg,alu_imm,alu_imm,alu_reg,alu_reg,multiple")]
)
(define_peephole2
gen_highpart_mode (SImode, DImode, operands[2]));
}"
- [(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
+ [(set_attr "type" "neon_int_1,neon_int_1,multiple,multiple,multiple,multiple,neon_int_1,neon_int_1")
(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,
avoid_neon_for_64bits,avoid_neon_for_64bits")
(set_attr "length" "*,*,8,8,8,8,*,*")
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
}"
- [(set_attr "length" "8")]
+ [(set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn "*anddi_sesdi_di"
(match_operand:DI 1 "s_register_operand" "0,r")))]
"TARGET_32BIT"
"#"
- [(set_attr "length" "8")]
+ [(set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_expand "andsi3"
(set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes")
(const_int 12)
- (const_int 8)))]
+ (const_int 8)))
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*ne_zeroextractsi_shifted"
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
"
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*ite_ne_zeroextractsi"
<< INTVAL (operands[3]));
"
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*ite_ne_zeroextractsi_shifted"
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
"
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_split
operands[2] = gen_lowpart (SImode, operands[2]);
}"
[(set_attr "length" "8")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*anddi_notzesidi_di"
}"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*anddi_notsesidi_di"
}"
[(set_attr "length" "8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "multiple")]
)
(define_insn "andsi_notsi_si"
"TARGET_32BIT"
"bic%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "logic_reg")]
)
(define_insn "thumb1_bicsi3"
"TARGET_THUMB1"
"bic\\t%0, %1"
[(set_attr "length" "2")
- (set_attr "conds" "set")])
+ (set_attr "conds" "set")
+ (set_attr "type" "logics_reg")]
+)
(define_insn "andsi_not_shiftsi_si"
[(set (match_operand:SI 0 "s_register_operand" "=r")
gen_highpart_mode (SImode, DImode, operands[2]));
}"
- [(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
+ [(set_attr "type" "neon_int_1,neon_int_1,multiple,multiple,multiple,multiple,neon_int_1,neon_int_1")
(set_attr "length" "*,*,8,8,8,8,*,*")
(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")]
)
#"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "logic_reg,multiple")]
)
(define_insn "*iordi_sesidi_di"
"TARGET_32BIT"
"#"
[(set_attr "length" "8")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "type" "multiple")]
)
(define_expand "iorsi3"
"TARGET_THUMB1"
"orr\\t%0, %2"
[(set_attr "length" "2")
- (set_attr "conds" "set")])
+ (set_attr "conds" "set")
+ (set_attr "type" "logics_reg")])
(define_peephole2
[(match_scratch:SI 3 "r")
}"
[(set_attr "length" "*,8,8,8,8,*")
- (set_attr "type" "neon_int_1,*,*,*,*,neon_int_1")
+ (set_attr "type" "neon_int_1,multiple,multiple,multiple,multiple,neon_int_1")
(set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")]
)
#"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "logic_reg")]
)
(define_insn "*xordi_sesidi_di"
"TARGET_32BIT"
"#"
[(set_attr "length" "8")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "type" "multiple")]
)
(define_expand "xorsi3"
[(set_attr "length" "4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no")
- (set_attr "type" "logic_imm,logic_reg,logic_reg,logic_reg")]
+ (set_attr "type" "logic_imm,logic_reg,logic_reg,multiple")]
)
(define_insn "*thumb1_xorsi3_insn"
[(set_attr "length" "8")
(set_attr "ce_count" "2")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "multiple")]
)
; ??? Are these four splitters still beneficial when the Thumb-2 bitfield
"TARGET_32BIT"
"bic%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "logic_shift_reg")]
)
(define_insn "*smax_m1"
"TARGET_32BIT"
"orr%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "logic_shift_reg")]
)
(define_insn_and_split "*arm_smax_insn"
(match_dup 2)))]
""
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_expand "sminsi3"
"TARGET_32BIT"
"and%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "logic_shift_reg")]
)
(define_insn_and_split "*arm_smin_insn"
(match_dup 2)))]
""
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple,multiple")]
)
(define_expand "umaxsi3"
(match_dup 2)))]
""
[(set_attr "conds" "clob")
- (set_attr "length" "8,8,12")]
+ (set_attr "length" "8,8,12")
+ (set_attr "type" "store1")]
)
(define_expand "uminsi3"
(match_dup 2)))]
""
[(set_attr "conds" "clob")
- (set_attr "length" "8,8,12")]
+ (set_attr "length" "8,8,12")
+ (set_attr "type" "store1")]
)
(define_insn "*store_minmaxsi"
(set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes")
(const_int 14)
- (const_int 12)))]
+ (const_int 12)))
+ (set_attr "type" "multiple")]
)
; Reject the frame pointer in operand[1], since reloading this after
(set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes")
(const_int 14)
- (const_int 12)))]
+ (const_int 12)))
+ (set_attr "type" "multiple")]
)
(define_code_iterator SAT [smin smax])
return "usat%?\t%0, %1, %3";
}
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "alus_imm")]
)
(define_insn "*satsi_<SAT:code>_shift"
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_expand "ashlsi3"
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn "*rrx"
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_expand "lshrsi3"
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn "*thumb1_negdi2"
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB1"
"mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1"
- [(set_attr "length" "6")]
+ [(set_attr "length" "6")
+ (set_attr "type" "multiple")]
)
(define_expand "negsi2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no")
(set_attr "arch" "t2,*")
- (set_attr "length" "4")]
+ (set_attr "length" "4")
+ (set_attr "type" "alu_reg")]
)
(define_insn "*thumb1_negsi2"
(neg:SI (match_operand:SI 1 "register_operand" "l")))]
"TARGET_THUMB1"
"neg\\t%0, %1"
- [(set_attr "length" "2")]
+ [(set_attr "length" "2")
+ (set_attr "type" "alu_imm")]
)
(define_expand "negsf2"
DONE;
}
[(set_attr "length" "8,8,4,4")
- (set_attr "arch" "a,a,t2,t2")]
+ (set_attr "arch" "a,a,t2,t2")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*negdi_zero_extendsidi"
operands[0] = gen_lowpart (SImode, operands[0]);
}
[(set_attr "conds" "clob")
- (set_attr "length" "8")] ;; length in thumb is 4
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")] ;; length in thumb is 4
)
;; abssi2 doesn't really clobber the condition codes if a different register
[(set_attr "conds" "clob,*")
(set_attr "shift" "1")
(set_attr "predicable" "no, yes")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*thumb1_abssi2"
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
""
- [(set_attr "length" "6")]
+ [(set_attr "length" "6")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*arm_neg_abssi2"
[(set_attr "conds" "clob,*")
(set_attr "shift" "1")
(set_attr "predicable" "no, yes")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*thumb1_neg_abssi2"
(set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
""
- [(set_attr "length" "6")]
+ [(set_attr "length" "6")
+ (set_attr "type" "multiple")]
)
(define_expand "abssf2"
}"
[(set_attr "length" "*,8,8,*")
(set_attr "predicable" "no,yes,yes,no")
- (set_attr "type" "neon_int_1,*,*,neon_int_1")
+ (set_attr "type" "neon_int_1,multiple,multiple,neon_int_1")
(set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")]
)
(set_attr "ce_count" "2")
(set_attr "shift" "1")
(set_attr "predicable" "yes")
- (set_attr "arch" "neon_for_64bits,*,a,t,avoid_neon_for_64bits")]
+ (set_attr "arch" "neon_for_64bits,*,a,t,avoid_neon_for_64bits")
+ (set_attr "type" "multiple,mov_reg,multiple,multiple,multiple")]
)
;; Splits for all extensions to DImode
"tst%?\\t%0, #255"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "logic_imm")]
)
(define_expand "extendhisi2"
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"sxtah%?\\t%0, %2, %1"
+ [(set_attr "type" "alu_shift_reg")]
)
(define_expand "extendqihi2"
}
"
[(set_attr "length" "8,12,16,8,8")
- (set_attr "type" "*,*,*,load2,store2")
+ (set_attr "type" "multiple,multiple,multiple,load2,store2")
(set_attr "arm_pool_range" "*,*,*,1020,*")
(set_attr "arm_neg_pool_range" "*,*,*,1004,*")
(set_attr "thumb2_pool_range" "*,*,*,4094,*")
}
}"
[(set_attr "length" "4,4,6,2,2,6,4,4")
- (set_attr "type" "*,mov_reg,*,load2,store2,load2,store2,mov_reg")
+ (set_attr "type" "multiple,mov_reg,multiple,load2,store2,load2,store2,mov_reg")
(set_attr "pool_range" "*,*,*,*,*,1018,*,*")]
)
"movt%?\t%0, #:upper16:%c2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "length" "4")]
+ (set_attr "length" "4")
+ (set_attr "type" "mov_imm")]
)
(define_insn "*arm_movsi_insn"
str\\t%1, %0
mov\\t%0, %1"
[(set_attr "length" "2,2,4,4,2,2,2,2,2")
- (set_attr "type" "*,*,*,*,load1,store1,load1,store1,*")
+ (set_attr "type" "mov_reg,mov_imm,multiple,multiple,load1,store1,load1,store1,mov_reg")
(set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")
(set_attr "conds" "set,clob,*,*,nocond,nocond,nocond,nocond,nocond")])
INTVAL (operands[2]));
return \"add\\t%0, %|pc\";
"
- [(set_attr "length" "2")]
+ [(set_attr "length" "2")
+ (set_attr "type" "alu_reg")]
)
(define_insn "pic_add_dot_plus_eight"
INTVAL (operands[2]));
return \"add%?\\t%0, %|pc, %1\";
"
- [(set_attr "predicable" "yes")]
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_reg")]
)
(define_insn "tls_load_dot_plus_eight"
INTVAL (operands[2]));
return \"ldr%?\\t%0, [%|pc, %1]\t\t@ tls_load_dot_plus_eight\";
"
- [(set_attr "predicable" "yes")]
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "load1")]
)
;; PIC references to local variables can generate pic_add_dot_plus_eight
return \"ldrh %0, %1\";
}"
[(set_attr "length" "2,4,2,2,2,2")
- (set_attr "type" "*,load1,store1,*,*,*")
+ (set_attr "type" "alus_imm,load1,store1,mov_reg,mov_reg,mov_imm")
(set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
mov\\t%0, %1
mov\\t%0, %1"
[(set_attr "length" "2")
- (set_attr "type" "*,load1,store1,load1,store1,mov_reg,mov_reg")
+ (set_attr "type" "alus_imm,load1,store1,load1,store1,mov_reg,mov_reg")
(set_attr "pool_range" "*,*,*,1018,*,*,*")
(set_attr "conds" "clob,nocond,nocond,nocond,nocond,nocond,nocond")]
)
}
"
[(set_attr "length" "8,12,16,8,8")
- (set_attr "type" "*,*,*,load2,store2")
+ (set_attr "type" "multiple,multiple,multiple,load2,store2")
(set_attr "arm_pool_range" "*,*,*,1020,*")
(set_attr "thumb2_pool_range" "*,*,*,1018,*")
(set_attr "arm_neg_pool_range" "*,*,*,1004,*")
}
"
[(set_attr "length" "4,2,2,6,4,4")
- (set_attr "type" "*,load2,store2,load2,store2,mov_reg")
+ (set_attr "type" "multiple,load2,store2,load2,store2,mov_reg")
(set_attr "pool_range" "*,*,*,1018,*,*")]
)
\f
(and (ge (minus (match_dup 3) (pc)) (const_int -2040))
(le (minus (match_dup 3) (pc)) (const_int 2048)))
(const_int 6)
- (const_int 8))))]
+ (const_int 8))))
+ (set_attr "type" "multiple")]
)
(define_insn "cbranchsi4_scratch"
(and (ge (minus (match_dup 3) (pc)) (const_int -2040))
(le (minus (match_dup 3) (pc)) (const_int 2048)))
(const_int 6)
- (const_int 8))))]
+ (const_int 8))))
+ (set_attr "type" "multiple")]
)
(define_insn "*negated_cbranchsi4"
(and (ge (minus (match_dup 3) (pc)) (const_int -2040))
(le (minus (match_dup 3) (pc)) (const_int 2048)))
(const_int 6)
- (const_int 8))))]
+ (const_int 8))))
+ (set_attr "type" "multiple")]
)
(define_insn "*tbit_cbranch"
(and (ge (minus (match_dup 3) (pc)) (const_int -2040))
(le (minus (match_dup 3) (pc)) (const_int 2048)))
(const_int 6)
- (const_int 8))))]
+ (const_int 8))))
+ (set_attr "type" "multiple")]
)
(define_insn "*tlobits_cbranch"
(and (ge (minus (match_dup 3) (pc)) (const_int -2040))
(le (minus (match_dup 3) (pc)) (const_int 2048)))
(const_int 6)
- (const_int 8))))]
+ (const_int 8))))
+ (set_attr "type" "multiple")]
)
(define_insn "*tstsi3_cbranch"
(and (ge (minus (match_dup 2) (pc)) (const_int -2040))
(le (minus (match_dup 2) (pc)) (const_int 2048)))
(const_int 6)
- (const_int 8))))]
+ (const_int 8))))
+ (set_attr "type" "multiple")]
)
(define_insn "*cbranchne_decr1"
(and (ge (minus (match_dup 4) (pc)) (const_int -2038))
(le (minus (match_dup 4) (pc)) (const_int 2048)))
(const_int 8)
- (const_int 10)))])]
+ (const_int 10)))])
+ (set_attr "type" "multiple")]
)
(define_insn "*addsi3_cbranch"
(and (ge (minus (match_dup 5) (pc)) (const_int -2038))
(le (minus (match_dup 5) (pc)) (const_int 2048)))
(const_int 8)
- (const_int 10)))))]
+ (const_int 10)))))
+ (set_attr "type" "multiple")]
)
(define_insn "*addsi3_cbranch_scratch"
(and (ge (minus (match_dup 4) (pc)) (const_int -2040))
(le (minus (match_dup 4) (pc)) (const_int 2048)))
(const_int 6)
- (const_int 8))))]
+ (const_int 8))))
+ (set_attr "type" "multiple")]
)
operands[2] = gen_lowpart (SImode, operands[2]);
}
[(set_attr "conds" "set")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*arm_cmpdi_unsigned"
[(set_attr "conds" "set")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "arch" "t2,t2,*")
- (set_attr "length" "6,6,8")]
+ (set_attr "length" "6,6,8")
+ (set_attr "type" "multiple")]
)
(define_insn "*arm_cmpdi_zero"
(clobber (match_scratch:SI 1 "=r"))]
"TARGET_32BIT"
"orr%.\\t%1, %Q0, %R0"
- [(set_attr "conds" "set")]
+ [(set_attr "conds" "set")
+ (set_attr "type" "logics_reg")]
)
(define_insn "*thumb_cmpdi_zero"
"TARGET_THUMB1"
"orr\\t%1, %Q0, %R0"
[(set_attr "conds" "set")
- (set_attr "length" "2")]
+ (set_attr "length" "2")
+ (set_attr "type" "logics_reg")]
)
; This insn allows redundant compares to be removed by cse, nothing should
"TARGET_32BIT"
"\\t%@ deleted compare"
[(set_attr "conds" "set")
- (set_attr "length" "0")]
+ (set_attr "length" "0")
+ (set_attr "type" "no_insn")]
)
\f
(const_int 0)))]
""
[(set_attr "conds" "use")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*mov_negscc"
operands[3] = GEN_INT (~0);
}
[(set_attr "conds" "use")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*mov_notscc"
operands[4] = GEN_INT (~0);
}
[(set_attr "conds" "use")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_expand "cstoresi4"
"@
neg\\t%0, %1\;adc\\t%0, %0, %1
neg\\t%2, %1\;adc\\t%0, %1, %2"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "multiple")]
)
(define_insn "*cstoresi_ne0_thumb1_insn"
(match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r"))))]
"TARGET_THUMB1"
"cmp\\t%1, %2\;sbc\\t%0, %0, %0"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "cstoresi_ltu_thumb1"
(neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:SI (match_dup 3)))]
"operands[3] = gen_reg_rtx (SImode);"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "multiple")]
)
;; Used as part of the expansion of thumb les sequence.
(match_operand:SI 4 "thumb1_cmp_operand" "lI"))))]
"TARGET_THUMB1"
"cmp\\t%3, %4\;adc\\t%0, %1, %2"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "multiple")]
)
\f
(and (ge (minus (match_dup 0) (pc)) (const_int -2044))
(le (minus (match_dup 0) (pc)) (const_int 2048))))
(const_int 2)
- (const_int 4)))]
+ (const_int 4)))
+ (set_attr "type" "branch")]
)
(define_insn "*thumb_jump"
(and (ge (minus (match_dup 0) (pc)) (const_int -2044))
(le (minus (match_dup 0) (pc)) (const_int 2048)))
(const_int 2)
- (const_int 4)))]
+ (const_int 4)))
+ (set_attr "type" "branch")]
)
(define_expand "call"
"TARGET_ARM"
"teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
[(set_attr "length" "8")
- (set_attr "conds" "set")]
+ (set_attr "conds" "set")
+ (set_attr "type" "multiple")]
)
;; Call subroutine returning any type.
return \"cmp\\t%0, %1\;ldrls\\t%|pc, [%|pc, %0, asl #2]\;b\\t%l3\";
"
[(set_attr "conds" "clob")
- (set_attr "length" "12")]
+ (set_attr "length" "12")
+ (set_attr "type" "multiple")]
)
(define_expand "thumb1_casesi_internal_pic"
(clobber (reg:SI LR_REGNUM))])]
"TARGET_THUMB1"
"* return thumb1_output_casesi(operands);"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "multiple")]
)
(define_expand "indirect_jump"
(match_operand:SI 0 "s_register_operand" "r"))]
"TARGET_ARM"
"mov%?\\t%|pc, %0\\t%@ indirect register jump"
- [(set_attr "predicable" "yes")]
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "branch")]
)
(define_insn "*load_indirect_jump"
"TARGET_THUMB1"
"mov\\tpc, %0"
[(set_attr "conds" "clob")
- (set_attr "length" "2")]
+ (set_attr "length" "2")
+ (set_attr "type" "branch")]
)
\f
[(set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes")
(const_int 2)
- (const_int 4)))]
+ (const_int 4)))
+ (set_attr "type" "mov_reg")]
)
\f
operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
}
[(set_attr "conds" "use")
- (set_attr "type" "mov_reg")
+ (set_attr "type" "multiple")
(set_attr "length" "8")]
)
operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
}
[(set_attr "conds" "use")
- (set_attr "length" "4,8")]
+ (set_attr "length" "4,8")
+ (set_attr "type" "logic_imm,multiple")]
)
; A series of splitters for the compare_scc pattern below. Note that
else
rc = reverse_condition (rc);
operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
-})
+}
+ [(set_attr "type" "multiple")]
+)
;; Attempt to improve the sequence generated by the compare_scc splitters
;; not to use conditional execution.
return \"\";
"
[(set_attr "conds" "use")
- (set_attr "type" "mov_reg")
+ (set_attr "type" "mov_reg,mov_reg,multiple")
(set_attr "length" "4,4,8")]
)
return \"%i5%d4\\t%0, %1, #1\";
"
[(set_attr "conds" "clob")
- (set_attr "length" "12")]
+ (set_attr "length" "12")
+ (set_attr "type" "multiple")]
)
(define_insn "*cond_sub"
return \"sub%d4\\t%0, %1, #1\";
"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*cmp_ite0"
}"
[(set_attr "conds" "set")
(set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
+ (set_attr "type" "multiple")
(set_attr_alternative "length"
[(const_int 6)
(const_int 8)
(const_int 10))
(if_then_else (eq_attr "is_thumb" "no")
(const_int 8)
- (const_int 10))])]
+ (const_int 10))])
+ (set_attr "type" "multiple")]
)
(define_insn "*cmp_and"
(const_int 10))
(if_then_else (eq_attr "is_thumb" "no")
(const_int 8)
- (const_int 10))])]
+ (const_int 10))])
+ (set_attr "type" "multiple")]
)
(define_insn "*cmp_ior"
(const_int 10))
(if_then_else (eq_attr "is_thumb" "no")
(const_int 8)
- (const_int 10))])]
+ (const_int 10))])
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "*ior_scc_scc"
DOM_CC_X_OR_Y),
CC_REGNUM);"
[(set_attr "conds" "clob")
- (set_attr "length" "16")])
+ (set_attr "length" "16")
+ (set_attr "type" "multiple")]
+)
; If the above pattern is followed by a CMP insn, then the compare is
; redundant, since we can rework the conditional instruction that follows.
(set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
""
[(set_attr "conds" "set")
- (set_attr "length" "16")])
+ (set_attr "length" "16")
+ (set_attr "type" "multiple")]
+)
(define_insn_and_split "*and_scc_scc"
[(set (match_operand:SI 0 "s_register_operand" "=Ts")
DOM_CC_X_AND_Y),
CC_REGNUM);"
[(set_attr "conds" "clob")
- (set_attr "length" "16")])
+ (set_attr "length" "16")
+ (set_attr "type" "multiple")]
+)
; If the above pattern is followed by a CMP insn, then the compare is
; redundant, since we can rework the conditional instruction that follows.
(set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
""
[(set_attr "conds" "set")
- (set_attr "length" "16")])
+ (set_attr "length" "16")
+ (set_attr "type" "multiple")]
+)
;; If there is no dominance in the comparison, then we can still save an
;; instruction in the AND case, since we can know that the second compare
operands[8] = gen_rtx_COMPARE (GET_MODE (operands[7]), operands[4],
operands[5]);"
[(set_attr "conds" "clob")
- (set_attr "length" "20")])
+ (set_attr "length" "20")
+ (set_attr "type" "multiple")]
+)
(define_split
[(set (reg:CC_NOOV CC_REGNUM)
FAIL;
}
[(set_attr "conds" "clob")
- (set_attr "length" "12")]
+ (set_attr "length" "12")
+ (set_attr "type" "multiple")]
)
(define_insn_and_split "movcond_addsi"
}
"
[(set_attr "conds" "clob")
- (set_attr "enabled_for_depr_it" "no,yes,yes")]
+ (set_attr "enabled_for_depr_it" "no,yes,yes")
+ (set_attr "type" "multiple")]
)
(define_insn "movcond"
return \"\";
"
[(set_attr "conds" "clob")
- (set_attr "length" "8,8,12")]
+ (set_attr "length" "8,8,12")
+ (set_attr "type" "multiple")]
)
;; ??? The patterns below need checking for Thumb-2 usefulness.
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_plus_move"
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_imm" )
- (const_string "*"))
+ (const_string "alu_reg"))
(const_string "alu_imm")
- (const_string "*")
- (const_string "*")])]
+ (const_string "alu_reg")
+ (const_string "alu_reg")])]
)
(define_insn "*ifcompare_move_plus"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_move_plus"
sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "4,4,8,8")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_imm" )
- (const_string "*"))
- (const_string "alu_imm")
- (const_string "*")
- (const_string "*")])]
+ (set_attr "type" "alu_reg,alu_imm,multiple,multiple")]
)
(define_insn "*ifcompare_arith_arith"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "12")]
+ (set_attr "length" "12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_arith_arith"
"TARGET_ARM"
"%I6%d5\\t%0, %1, %2\;%I7%D5\\t%0, %3, %4"
[(set_attr "conds" "use")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn "*ifcompare_arith_move"
return \"\";
"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_arith_move"
%I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "4,8")
- (set_attr "type" "*,*")]
+ (set_attr "type" "alu_shift_reg,multiple")]
)
(define_insn "*ifcompare_move_arith"
return \"%I7%D6\\t%0, %2, %3\";
"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_move_arith"
%I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "4,8")
- (set_attr "type" "*,*")]
+ (set_attr "type" "alu_shift_reg,multiple")]
)
(define_insn "*ifcompare_move_not"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_move_not"
mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2"
[(set_attr "conds" "use")
(set_attr "type" "mvn_reg")
- (set_attr "length" "4,8,8")]
+ (set_attr "length" "4,8,8")
+ (set_attr "type" "mvn_reg,multiple,multiple")]
)
(define_insn "*ifcompare_not_move"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_not_move"
mov%D4\\t%0, %1\;mvn%d4\\t%0, %2
mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2"
[(set_attr "conds" "use")
- (set_attr "type" "mvn_reg")
+ (set_attr "type" "mvn_reg,multiple,multiple")
(set_attr "length" "4,8,8")]
)
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_shift_move"
[(set_attr "conds" "use")
(set_attr "shift" "2")
(set_attr "length" "4,8,8")
- (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "mov_shift")
- (const_string "mov_shift_reg")))]
+ (set_attr "type" "mov_shift_reg,multiple,multiple")]
)
(define_insn "*ifcompare_move_shift"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_move_shift"
[(set_attr "conds" "use")
(set_attr "shift" "2")
(set_attr "length" "4,8,8")
- (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "mov_shift")
- (const_string "mov_shift_reg")))]
+ (set_attr "type" "mov_shift_reg,multiple,multiple")]
)
(define_insn "*ifcompare_shift_shift"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "12")]
+ (set_attr "length" "12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_shift_shift"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "12")]
+ (set_attr "length" "12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_not_arith"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "12")]
+ (set_attr "length" "12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_arith_not"
"TARGET_ARM"
"mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3"
[(set_attr "conds" "use")
- (set_attr "type" "mvn_reg")
+ (set_attr "type" "multiple")
(set_attr "length" "8")]
)
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_neg_move"
mov%D4\\t%0, %1\;rsb%d4\\t%0, %2, #0
mvn%D4\\t%0, #%B1\;rsb%d4\\t%0, %2, #0"
[(set_attr "conds" "use")
- (set_attr "length" "4,8,8")]
+ (set_attr "length" "4,8,8")
+ (set_attr "type" "logic_shift_imm,multiple,multiple")]
)
(define_insn "*ifcompare_move_neg"
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
- (set_attr "length" "8,12")]
+ (set_attr "length" "8,12")
+ (set_attr "type" "multiple")]
)
(define_insn "*if_move_neg"
mov%d4\\t%0, %1\;rsb%D4\\t%0, %2, #0
mvn%d4\\t%0, #%B1\;rsb%D4\\t%0, %2, #0"
[(set_attr "conds" "use")
- (set_attr "length" "4,8,8")]
+ (set_attr "length" "4,8,8")
+ (set_attr "type" "logic_shift_imm,multiple,multiple")]
)
(define_insn "*arith_adjacentmem"
[(unspec_volatile [(const_int 0)] VUNSPEC_THUMB1_INTERWORK)]
"TARGET_THUMB1"
"* return thumb1_output_interwork ();"
- [(set_attr "length" "8")]
+ [(set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
;; Note - although unspec_volatile's USE all hard registers,
mvn%D4\\t%0, %2
mov%d4\\t%0, %1\;mvn%D4\\t%0, %2"
[(set_attr "conds" "use")
- (set_attr "type" "mvn_reg")
+ (set_attr "type" "mvn_reg,multiple")
(set_attr "length" "4,8")]
)
return \"mvnne\\t%0, #0\";
"
[(set_attr "conds" "clob")
- (set_attr "length" "8")]
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
)
(define_insn "*not_signextract_onebit"
return \"movne\\t%0, #0\";
"
[(set_attr "conds" "clob")
- (set_attr "length" "12")]
+ (set_attr "length" "12")
+ (set_attr "type" "multiple")]
)
;; ??? The above patterns need auditing for Thumb-2
UNSPEC_PRLG_STK))]
""
""
- [(set_attr "length" "0")]
+ [(set_attr "length" "0")
+ (set_attr "type" "block")]
)
;; Pop (as used in epilogue RTL)
assemble_align (32);
return \"\";
"
+ [(set_attr "type" "no_insn")]
)
(define_insn "align_8"
assemble_align (64);
return \"\";
"
+ [(set_attr "type" "no_insn")]
)
(define_insn "consttable_end"
making_const_table = FALSE;
return \"\";
"
+ [(set_attr "type" "no_insn")]
)
(define_insn "consttable_1"
assemble_zeros (3);
return \"\";
"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "no_insn")]
)
(define_insn "consttable_2"
assemble_zeros (2);
return \"\";
"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "no_insn")]
)
(define_insn "consttable_4"
}
return \"\";
}"
- [(set_attr "length" "4")]
+ [(set_attr "length" "4")
+ (set_attr "type" "no_insn")]
)
(define_insn "consttable_8"
}
return \"\";
}"
- [(set_attr "length" "8")]
+ [(set_attr "length" "8")
+ (set_attr "type" "no_insn")]
)
(define_insn "consttable_16"
}
return \"\";
}"
- [(set_attr "length" "16")]
+ [(set_attr "length" "16")
+ (set_attr "type" "no_insn")]
)
;; Miscellaneous Thumb patterns
(use (label_ref (match_operand 1 "" "")))]
"TARGET_THUMB1"
"mov\\t%|pc, %0"
- [(set_attr "length" "2")]
+ [(set_attr "length" "2")
+ (set_attr "type" "no_insn")]
)
;; V5 Instructions,
(match_operand:SI 1 "" "")
(match_operand:SI 2 "" ""))]
"TARGET_32BIT && arm_arch5e"
- "pld\\t%a0")
+ "pld\\t%a0"
+ [(set_attr "type" "load1")]
+)
;; General predication pattern
[(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_REGISTER_USE)]
""
"%@ %0 needed"
- [(set_attr "length" "0")]
+ [(set_attr "length" "0")
+ (set_attr "type" "no_insn")]
)
thumb_set_return_address (operands[0], operands[1]);
DONE;
}"
+ [(set_attr "type" "mov_reg")]
)
\f
(unspec:SI [(const_int 0)] UNSPEC_TLS))]
"TARGET_HARD_TP"
"mrc%?\\tp15, 0, %0, c13, c0, 3\\t@ load_tp_hard"
- [(set_attr "predicable" "yes")]
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "mov_reg")]
)
;; Doesn't clobber R1-R3. Must use r0 for the first operand.
(clobber (reg:CC CC_REGNUM))]
"TARGET_SOFT_TP"
"bl\\t__aeabi_read_tp\\t@ load_tp_soft"
- [(set_attr "conds" "clob")]
+ [(set_attr "conds" "clob")
+ (set_attr "type" "branch")]
)
;; tls descriptor call
return "bl\\t%c0(tlscall)";
}
[(set_attr "conds" "clob")
- (set_attr "length" "4")]
+ (set_attr "length" "4")
+ (set_attr "type" "branch")]
)
;; For thread pointer builtin
"movt%?\t%0, %L1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "length" "4")]
+ (set_attr "length" "4")
+ (set_attr "type" "mov_imm")]
)
(define_insn "*arm_rev"
rev%?\t%0, %1
rev%?\t%0, %1"
[(set_attr "arch" "t1,t2,32")
- (set_attr "length" "2,2,4")]
+ (set_attr "length" "2,2,4")
+ (set_attr "type" "rev")]
)
(define_expand "arm_legacy_rev"
revsh%?\t%0, %1
revsh%?\t%0, %1"
[(set_attr "arch" "t1,t2,32")
- (set_attr "length" "2,2,4")]
+ (set_attr "length" "2,2,4")
+ (set_attr "type" "rev")]
)
(define_insn "*arm_rev16"
rev16%?\t%0, %1
rev16%?\t%0, %1"
[(set_attr "arch" "t1,t2,32")
- (set_attr "length" "2,2,4")]
+ (set_attr "length" "2,2,4")
+ (set_attr "type" "rev")]
)
(define_expand "bswaphi2"
projects / thirdparty / gcc.git / blobdiff