;;- Machine description for ARM for GNU compiler
-;; Copyright (C) 1991-2019 Free Software Foundation, Inc.
+;; Copyright (C) 1991-2020 Free Software Foundation, Inc.
;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
;; and Martin Simmons (@harleqn.co.uk).
;; More major hacks by Richard Earnshaw (rearnsha@arm.com).
[(R0_REGNUM 0) ; First CORE register
(R1_REGNUM 1) ; Second CORE register
(R4_REGNUM 4) ; Fifth CORE register
+ (FDPIC_REGNUM 9) ; FDPIC register
(IP_REGNUM 12) ; Scratch register
(SP_REGNUM 13) ; Stack pointer
(LR_REGNUM 14) ; Return address register
(LAST_ARM_REGNUM 15) ;
(CC_REGNUM 100) ; Condition code pseudo register
(VFPCC_REGNUM 101) ; VFP Condition code pseudo register
+ (APSRQ_REGNUM 104) ; Q bit pseudo register
+ (APSRGE_REGNUM 105) ; GE bits pseudo register
]
)
;; 3rd operand to select_dominance_cc_mode
; arm_arch6. "v6t2" for Thumb-2 with arm_arch6 and "v8mb" for ARMv8-M
; Baseline. This attribute is used to compute attribute "enabled",
; use type "any" to enable an alternative in all cases.
-(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,v8mb,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2,armv6_or_vfpv3,neon"
+(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,v8mb,iwmmxt,iwmmxt2,armv6_or_vfpv3,neon"
(const_string "any"))
(define_attr "arch_enabled" "no,yes"
(match_test "TARGET_THUMB1 && arm_arch8"))
(const_string "yes")
- (and (eq_attr "arch" "avoid_neon_for_64bits")
- (match_test "TARGET_NEON")
- (not (match_test "TARGET_PREFER_NEON_64BITS")))
- (const_string "yes")
-
- (and (eq_attr "arch" "neon_for_64bits")
- (match_test "TARGET_NEON")
- (match_test "TARGET_PREFER_NEON_64BITS"))
- (const_string "yes")
-
(and (eq_attr "arch" "iwmmxt2")
(match_test "TARGET_REALLY_IWMMXT2"))
(const_string "yes")
(include "marvell-pj4.md")
(include "xgene1.md")
+;; define_subst and associated attributes
+
+(define_subst "add_setq"
+ [(set (match_operand:SI 0 "" "")
+ (match_operand:SI 1 "" ""))]
+ ""
+ [(set (match_dup 0)
+ (match_dup 1))
+ (set (reg:CC APSRQ_REGNUM)
+ (unspec:CC [(reg:CC APSRQ_REGNUM)] UNSPEC_Q_SET))])
+
+(define_subst_attr "add_clobber_q_name" "add_setq" "" "_setq")
+(define_subst_attr "add_clobber_q_pred" "add_setq" "!ARM_Q_BIT_READ"
+ "ARM_Q_BIT_READ")
\f
;;---------------------------------------------------------------------------
;; Insn patterns
[(parallel
[(set (match_operand:DI 0 "s_register_operand")
(plus:DI (match_operand:DI 1 "s_register_operand")
- (match_operand:DI 2 "arm_adddi_operand")))
+ (match_operand:DI 2 "reg_or_int_operand")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
if (TARGET_THUMB1)
{
- if (!REG_P (operands[1]))
- operands[1] = force_reg (DImode, operands[1]);
if (!REG_P (operands[2]))
- operands[2] = force_reg (DImode, operands[2]);
- }
+ operands[2] = force_reg (DImode, operands[2]);
+ }
+ else
+ {
+ rtx lo_result, hi_result, lo_dest, hi_dest;
+ rtx lo_op1, hi_op1, lo_op2, hi_op2;
+ arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
+ &lo_op2, &hi_op2);
+ lo_result = lo_dest = gen_lowpart (SImode, operands[0]);
+ hi_result = hi_dest = gen_highpart (SImode, operands[0]);
+
+ if (lo_op2 == const0_rtx)
+ {
+ lo_dest = lo_op1;
+ if (!arm_add_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+ /* Assume hi_op2 won't also be zero. */
+ emit_insn (gen_addsi3 (hi_dest, hi_op1, hi_op2));
+ }
+ else
+ {
+ if (!arm_add_operand (lo_op2, SImode))
+ lo_op2 = force_reg (SImode, lo_op2);
+ if (!arm_not_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+
+ emit_insn (gen_addsi3_compare_op1 (lo_dest, lo_op1, lo_op2));
+ rtx carry = gen_rtx_LTU (SImode, gen_rtx_REG (CC_Cmode, CC_REGNUM),
+ const0_rtx);
+ if (hi_op2 == const0_rtx)
+ emit_insn (gen_add0si3_carryin (hi_dest, hi_op1, carry));
+ else
+ emit_insn (gen_addsi3_carryin (hi_dest, hi_op1, hi_op2, carry));
+ }
+
+ if (lo_result != lo_dest)
+ emit_move_insn (lo_result, lo_dest);
+ if (hi_result != hi_dest)
+ emit_move_insn (gen_highpart (SImode, operands[0]), hi_dest);
+ DONE;
+ }
"
)
-(define_insn_and_split "*arm_adddi3"
- [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r,&r,&r")
- (plus:DI (match_operand:DI 1 "arm_general_register_operand" "%0, 0, r, 0, r")
- (match_operand:DI 2 "arm_general_adddi_operand" "r, 0, r, Dd, Dd")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT && !TARGET_NEON"
- "#"
- "TARGET_32BIT && ((!TARGET_NEON && !TARGET_IWMMXT) || reload_completed)"
- [(parallel [(set (reg:CC_C CC_REGNUM)
- (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
- (match_dup 1)))
- (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
- (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
- "
+(define_expand "addvsi4"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "arm_add_operand")
+ (match_operand 3 "")]
+ "TARGET_32BIT"
+{
+ if (CONST_INT_P (operands[2]))
+ emit_insn (gen_addsi3_compareV_imm (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_addsi3_compareV_reg (operands[0], operands[1], operands[2]));
+ arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
+
+ DONE;
+})
+
+(define_expand "addvdi4"
+ [(match_operand:DI 0 "s_register_operand")
+ (match_operand:DI 1 "s_register_operand")
+ (match_operand:DI 2 "reg_or_int_operand")
+ (match_operand 3 "")]
+ "TARGET_32BIT"
+{
+ rtx lo_result, hi_result;
+ rtx lo_op1, hi_op1, lo_op2, hi_op2;
+ arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
+ &lo_op2, &hi_op2);
+ lo_result = gen_lowpart (SImode, operands[0]);
+ hi_result = gen_highpart (SImode, operands[0]);
+
+ if (lo_op2 == const0_rtx)
+ {
+ emit_move_insn (lo_result, lo_op1);
+ if (!arm_add_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+
+ emit_insn (gen_addvsi4 (hi_result, hi_op1, hi_op2, operands[3]));
+ }
+ else
+ {
+ if (!arm_add_operand (lo_op2, SImode))
+ lo_op2 = force_reg (SImode, lo_op2);
+ if (!arm_not_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+
+ emit_insn (gen_addsi3_compare_op1 (lo_result, lo_op1, lo_op2));
+
+ if (hi_op2 == const0_rtx)
+ emit_insn (gen_addsi3_cin_vout_0 (hi_result, hi_op1));
+ else if (CONST_INT_P (hi_op2))
+ emit_insn (gen_addsi3_cin_vout_imm (hi_result, hi_op1, hi_op2));
+ else
+ emit_insn (gen_addsi3_cin_vout_reg (hi_result, hi_op1, hi_op2));
+
+ arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
+ }
+
+ DONE;
+})
+
+(define_expand "addsi3_cin_vout_reg"
+ [(parallel
+ [(set (match_dup 3)
+ (compare:CC_V
+ (plus:DI
+ (plus:DI (match_dup 4)
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
+ (sign_extend:DI (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_dup 2)))])]
+ "TARGET_32BIT"
{
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[5] = gen_highpart_mode (SImode, DImode, operands[2]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- }"
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
+ operands[3] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ }
)
-(define_insn_and_split "*adddi_sesidi_di"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (plus:DI (sign_extend:DI
- (match_operand:SI 2 "s_register_operand" "r,r"))
- (match_operand:DI 1 "s_register_operand" "0,r")))
- (clobber (reg:CC CC_REGNUM))]
+(define_insn "*addsi3_cin_vout_reg_insn"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (plus:DI
+ (match_operand:DI 3 "arm_carry_operation" "")
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r")))
+ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "l,r")))
+ (sign_extend:DI
+ (plus:SI (plus:SI (match_operand:SI 4 "arm_carry_operation" "")
+ (match_dup 1))
+ (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand" "=l,r")
+ (plus:SI (plus:SI (match_dup 4) (match_dup 1))
+ (match_dup 2)))]
+ "TARGET_32BIT"
+ "@
+ adcs%?\\t%0, %0, %2
+ adcs%?\\t%0, %1, %2"
+ [(set_attr "type" "alus_sreg")
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,4")]
+)
+
+(define_expand "addsi3_cin_vout_imm"
+ [(parallel
+ [(set (match_dup 3)
+ (compare:CC_V
+ (plus:DI
+ (plus:DI (match_dup 4)
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (match_dup 2))
+ (sign_extend:DI (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_operand 2 "arm_adcimm_operand")))])]
"TARGET_32BIT"
- "#"
- "TARGET_32BIT && reload_completed"
- [(parallel [(set (reg:CC_C CC_REGNUM)
- (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
- (match_dup 1)))
- (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
- (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2)
- (const_int 31))
- (match_dup 4))
- (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
- "
{
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- }"
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
+ operands[3] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ }
)
-(define_insn_and_split "*adddi_zesidi_di"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (plus:DI (zero_extend:DI
- (match_operand:SI 2 "s_register_operand" "r,r"))
- (match_operand:DI 1 "s_register_operand" "0,r")))
- (clobber (reg:CC CC_REGNUM))]
+(define_insn "*addsi3_cin_vout_imm_insn"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (plus:DI
+ (match_operand:DI 3 "arm_carry_operation" "")
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r,r")))
+ (match_operand 2 "arm_adcimm_operand" "I,K"))
+ (sign_extend:DI
+ (plus:SI (plus:SI (match_operand:SI 4 "arm_carry_operation" "")
+ (match_dup 1))
+ (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (plus:SI (plus:SI (match_dup 4) (match_dup 1))
+ (match_dup 2)))]
+ "TARGET_32BIT"
+ "@
+ adcs%?\\t%0, %1, %2
+ sbcs%?\\t%0, %1, #%B2"
+ [(set_attr "type" "alus_imm")]
+)
+
+(define_expand "addsi3_cin_vout_0"
+ [(parallel
+ [(set (match_dup 2)
+ (compare:CC_V
+ (plus:DI (match_dup 3)
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (sign_extend:DI (plus:SI (match_dup 4) (match_dup 1)))))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (match_dup 4) (match_dup 1)))])]
"TARGET_32BIT"
- "#"
- "TARGET_32BIT && reload_completed"
- [(parallel [(set (reg:CC_C CC_REGNUM)
- (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
- (match_dup 1)))
- (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
- (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0))
- (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
- "
{
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- }"
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
+ operands[2] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[3] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[4] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ }
)
-(define_expand "addv<mode>4"
- [(match_operand:SIDI 0 "register_operand")
- (match_operand:SIDI 1 "register_operand")
- (match_operand:SIDI 2 "register_operand")
+(define_insn "*addsi3_cin_vout_0_insn"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (match_operand:DI 2 "arm_carry_operation" "")
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))
+ (sign_extend:DI (plus:SI
+ (match_operand:SI 3 "arm_carry_operation" "")
+ (match_dup 1)))))
+ (set (match_operand:SI 0 "s_register_operand" "=r")
+ (plus:SI (match_dup 3) (match_dup 1)))]
+ "TARGET_32BIT"
+ "adcs%?\\t%0, %1, #0"
+ [(set_attr "type" "alus_imm")]
+)
+
+(define_expand "uaddvsi4"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "arm_add_operand")
(match_operand 3 "")]
"TARGET_32BIT"
{
- emit_insn (gen_add<mode>3_compareV (operands[0], operands[1], operands[2]));
- arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
+ emit_insn (gen_addsi3_compare_op1 (operands[0], operands[1], operands[2]));
+ arm_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]);
DONE;
})
-(define_expand "uaddv<mode>4"
- [(match_operand:SIDI 0 "register_operand")
- (match_operand:SIDI 1 "register_operand")
- (match_operand:SIDI 2 "register_operand")
+(define_expand "uaddvdi4"
+ [(match_operand:DI 0 "s_register_operand")
+ (match_operand:DI 1 "s_register_operand")
+ (match_operand:DI 2 "reg_or_int_operand")
(match_operand 3 "")]
"TARGET_32BIT"
{
- emit_insn (gen_add<mode>3_compareC (operands[0], operands[1], operands[2]));
- arm_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]);
+ rtx lo_result, hi_result;
+ rtx lo_op1, hi_op1, lo_op2, hi_op2;
+ arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
+ &lo_op2, &hi_op2);
+ lo_result = gen_lowpart (SImode, operands[0]);
+ hi_result = gen_highpart (SImode, operands[0]);
+
+ if (lo_op2 == const0_rtx)
+ {
+ emit_move_insn (lo_result, lo_op1);
+ if (!arm_add_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+
+ gen_uaddvsi4 (hi_result, hi_op1, hi_op2, operands[3]);
+ }
+ else
+ {
+ if (!arm_add_operand (lo_op2, SImode))
+ lo_op2 = force_reg (SImode, lo_op2);
+ if (!arm_not_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+
+ emit_insn (gen_addsi3_compare_op1 (lo_result, lo_op1, lo_op2));
+
+ if (hi_op2 == const0_rtx)
+ emit_insn (gen_addsi3_cin_cout_0 (hi_result, hi_op1));
+ else if (CONST_INT_P (hi_op2))
+ emit_insn (gen_addsi3_cin_cout_imm (hi_result, hi_op1, hi_op2));
+ else
+ emit_insn (gen_addsi3_cin_cout_reg (hi_result, hi_op1, hi_op2));
+
+ arm_gen_unlikely_cbranch (GEU, CC_ADCmode, operands[3]);
+ }
DONE;
})
+(define_expand "addsi3_cin_cout_reg"
+ [(parallel
+ [(set (match_dup 3)
+ (compare:CC_ADC
+ (plus:DI
+ (plus:DI (match_dup 4)
+ (zero_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
+ (const_int 4294967296)))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_dup 2)))])]
+ "TARGET_32BIT"
+ {
+ operands[3] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ }
+)
+
+(define_insn "*addsi3_cin_cout_reg_insn"
+ [(set (reg:CC_ADC CC_REGNUM)
+ (compare:CC_ADC
+ (plus:DI
+ (plus:DI
+ (match_operand:DI 3 "arm_carry_operation" "")
+ (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r")))
+ (zero_extend:DI (match_operand:SI 2 "s_register_operand" "l,r")))
+ (const_int 4294967296)))
+ (set (match_operand:SI 0 "s_register_operand" "=l,r")
+ (plus:SI (plus:SI (match_operand:SI 4 "arm_carry_operation" "")
+ (match_dup 1))
+ (match_dup 2)))]
+ "TARGET_32BIT"
+ "@
+ adcs%?\\t%0, %0, %2
+ adcs%?\\t%0, %1, %2"
+ [(set_attr "type" "alus_sreg")
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,4")]
+)
+
+(define_expand "addsi3_cin_cout_imm"
+ [(parallel
+ [(set (match_dup 3)
+ (compare:CC_ADC
+ (plus:DI
+ (plus:DI (match_dup 4)
+ (zero_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (match_dup 6))
+ (const_int 4294967296)))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_operand:SI 2 "arm_adcimm_operand")))])]
+ "TARGET_32BIT"
+ {
+ operands[3] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ operands[6] = GEN_INT (UINTVAL (operands[2]) & 0xffffffff);
+ }
+)
+
+(define_insn "*addsi3_cin_cout_imm_insn"
+ [(set (reg:CC_ADC CC_REGNUM)
+ (compare:CC_ADC
+ (plus:DI
+ (plus:DI
+ (match_operand:DI 3 "arm_carry_operation" "")
+ (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r,r")))
+ (match_operand:DI 5 "const_int_operand" "n,n"))
+ (const_int 4294967296)))
+ (set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (plus:SI (plus:SI (match_operand:SI 4 "arm_carry_operation" "")
+ (match_dup 1))
+ (match_operand:SI 2 "arm_adcimm_operand" "I,K")))]
+ "TARGET_32BIT
+ && (UINTVAL (operands[2]) & 0xffffffff) == UINTVAL (operands[5])"
+ "@
+ adcs%?\\t%0, %1, %2
+ sbcs%?\\t%0, %1, #%B2"
+ [(set_attr "type" "alus_imm")]
+)
+
+(define_expand "addsi3_cin_cout_0"
+ [(parallel
+ [(set (match_dup 2)
+ (compare:CC_ADC
+ (plus:DI (match_dup 3)
+ (zero_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (const_int 4294967296)))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (match_dup 4) (match_dup 1)))])]
+ "TARGET_32BIT"
+ {
+ operands[2] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[3] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[4] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ }
+)
+
+(define_insn "*addsi3_cin_cout_0_insn"
+ [(set (reg:CC_ADC CC_REGNUM)
+ (compare:CC_ADC
+ (plus:DI
+ (match_operand:DI 2 "arm_carry_operation" "")
+ (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))
+ (const_int 4294967296)))
+ (set (match_operand:SI 0 "s_register_operand" "=r")
+ (plus:SI (match_operand:SI 3 "arm_carry_operation" "") (match_dup 1)))]
+ "TARGET_32BIT"
+ "adcs%?\\t%0, %1, #0"
+ [(set_attr "type" "alus_imm")]
+)
+
(define_expand "addsi3"
[(set (match_operand:SI 0 "s_register_operand")
(plus:SI (match_operand:SI 1 "s_register_operand")
]
)
-(define_insn_and_split "adddi3_compareV"
- [(set (reg:CC_V CC_REGNUM)
- (ne:CC_V
- (plus:TI
- (sign_extend:TI (match_operand:DI 1 "register_operand" "r"))
- (sign_extend:TI (match_operand:DI 2 "register_operand" "r")))
- (sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
- (set (match_operand:DI 0 "register_operand" "=&r")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT"
- "#"
- "&& reload_completed"
- [(parallel [(set (reg:CC_C CC_REGNUM)
- (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
- (match_dup 1)))
- (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
- (parallel [(set (reg:CC_V CC_REGNUM)
- (ne:CC_V
- (plus:DI (plus:DI
- (sign_extend:DI (match_dup 4))
- (sign_extend:DI (match_dup 5)))
- (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
- (plus:DI (sign_extend:DI
- (plus:SI (match_dup 4) (match_dup 5)))
- (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
- (set (match_dup 3) (plus:SI (plus:SI
- (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CC_C CC_REGNUM)
- (const_int 0))))])]
- "
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[5] = gen_highpart (SImode, operands[2]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- }"
- [(set_attr "conds" "set")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
-
-(define_insn "addsi3_compareV"
+(define_insn "addsi3_compareV_reg"
[(set (reg:CC_V CC_REGNUM)
- (ne:CC_V
+ (compare:CC_V
(plus:DI
- (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "%l,0,r"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand" "l,r,r")))
(sign_extend:DI (plus:SI (match_dup 1) (match_dup 2)))))
- (set (match_operand:SI 0 "register_operand" "=r")
+ (set (match_operand:SI 0 "register_operand" "=l,r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_32BIT"
"adds%?\\t%0, %1, %2"
[(set_attr "conds" "set")
+ (set_attr "arch" "t2,t2,*")
+ (set_attr "length" "2,2,4")
(set_attr "type" "alus_sreg")]
)
-(define_insn "*addsi3_compareV_upper"
+(define_insn "*addsi3_compareV_reg_nosum"
[(set (reg:CC_V CC_REGNUM)
- (ne:CC_V
+ (compare:CC_V
(plus:DI
- (plus:DI
- (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
- (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
- (plus:DI (sign_extend:DI
- (plus:SI (match_dup 1) (match_dup 2)))
- (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
- (set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI
- (plus:SI (match_dup 1) (match_dup 2))
- (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+ (sign_extend:DI (match_operand:SI 0 "register_operand" "%l,r"))
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "l,r")))
+ (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))]
"TARGET_32BIT"
- "adcs%?\\t%0, %1, %2"
+ "cmn%?\\t%0, %1"
[(set_attr "conds" "set")
- (set_attr "type" "adcs_reg")]
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,4")
+ (set_attr "type" "alus_sreg")]
)
-(define_insn_and_split "adddi3_compareC"
- [(set (reg:CC_C CC_REGNUM)
- (ne:CC_C
- (plus:TI
- (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
- (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
- (zero_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
- (set (match_operand:DI 0 "register_operand" "=&r")
- (plus:DI (match_dup 1) (match_dup 2)))]
+(define_insn "subvsi3_intmin"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (sign_extend:DI
+ (match_operand:SI 1 "register_operand" "r"))
+ (const_int 2147483648))
+ (sign_extend:DI (plus:SI (match_dup 1) (const_int -2147483648)))))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_dup 1) (const_int -2147483648)))]
"TARGET_32BIT"
- "#"
- "&& reload_completed"
- [(parallel [(set (reg:CC_C CC_REGNUM)
- (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
- (match_dup 1)))
- (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
- (parallel [(set (reg:CC_C CC_REGNUM)
- (ne:CC_C
- (plus:DI (plus:DI
- (zero_extend:DI (match_dup 4))
- (zero_extend:DI (match_dup 5)))
- (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
- (plus:DI (zero_extend:DI
- (plus:SI (match_dup 4) (match_dup 5)))
- (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
- (set (match_dup 3) (plus:SI
- (plus:SI (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CC_C CC_REGNUM)
- (const_int 0))))])]
- "
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[5] = gen_highpart (SImode, operands[2]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- }"
- [(set_attr "conds" "set")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
+ "subs%?\\t%0, %1, #-2147483648"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_imm")]
)
-(define_insn "*addsi3_compareC_upper"
- [(set (reg:CC_C CC_REGNUM)
- (ne:CC_C
+(define_insn "addsi3_compareV_imm"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
(plus:DI
- (plus:DI
- (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
- (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
- (plus:DI (zero_extend:DI
- (plus:SI (match_dup 1) (match_dup 2)))
- (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
- (set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI
- (plus:SI (match_dup 1) (match_dup 2))
- (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
- "TARGET_32BIT"
- "adcs%?\\t%0, %1, %2"
+ (sign_extend:DI
+ (match_operand:SI 1 "register_operand" "l,0,l,0,r,r"))
+ (match_operand 2 "arm_addimm_operand" "Pd,Py,Px,Pw,I,L"))
+ (sign_extend:DI (plus:SI (match_dup 1) (match_dup 2)))))
+ (set (match_operand:SI 0 "register_operand" "=l,l,l,l,r,r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT
+ && INTVAL (operands[2]) == ARM_SIGN_EXTEND (INTVAL (operands[2]))"
+ "@
+ adds%?\\t%0, %1, %2
+ adds%?\\t%0, %0, %2
+ subs%?\\t%0, %1, #%n2
+ subs%?\\t%0, %0, #%n2
+ adds%?\\t%0, %1, %2
+ subs%?\\t%0, %1, #%n2"
[(set_attr "conds" "set")
- (set_attr "type" "adcs_reg")]
+ (set_attr "arch" "t2,t2,t2,t2,*,*")
+ (set_attr "length" "2,2,2,2,4,4")
+ (set_attr "type" "alus_imm")]
)
-(define_insn "addsi3_compareC"
- [(set (reg:CC_C CC_REGNUM)
- (ne:CC_C
+(define_insn "addsi3_compareV_imm_nosum"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
(plus:DI
- (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
- (zero_extend:DI
- (plus:SI (match_dup 1) (match_dup 2)))))
- (set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT"
- "adds%?\\t%0, %1, %2"
+ (sign_extend:DI
+ (match_operand:SI 0 "register_operand" "l,r,r"))
+ (match_operand 1 "arm_addimm_operand" "Pw,I,L"))
+ (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))]
+ "TARGET_32BIT
+ && INTVAL (operands[1]) == ARM_SIGN_EXTEND (INTVAL (operands[1]))"
+ "@
+ cmp%?\\t%0, #%n1
+ cmn%?\\t%0, %1
+ cmp%?\\t%0, #%n1"
[(set_attr "conds" "set")
- (set_attr "type" "alus_sreg")]
+ (set_attr "arch" "t2,*,*")
+ (set_attr "length" "2,4,4")
+ (set_attr "type" "alus_imm")]
+)
+
+;; We can handle more constants efficently if we can clobber either a scratch
+;; or the other source operand. We deliberately leave this late as in
+;; high register pressure situations it's not worth forcing any reloads.
+(define_peephole2
+ [(match_scratch:SI 2 "l")
+ (set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (sign_extend:DI
+ (match_operand:SI 0 "low_register_operand"))
+ (match_operand 1 "const_int_operand"))
+ (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))]
+ "TARGET_THUMB2
+ && satisfies_constraint_Pd (operands[1])"
+ [(parallel[
+ (set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI (sign_extend:DI (match_dup 0))
+ (sign_extend:DI (match_dup 1)))
+ (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))
+ (set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))])]
+)
+
+(define_peephole2
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (sign_extend:DI
+ (match_operand:SI 0 "low_register_operand"))
+ (match_operand 1 "const_int_operand"))
+ (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))]
+ "TARGET_THUMB2
+ && dead_or_set_p (peep2_next_insn (0), operands[0])
+ && satisfies_constraint_Py (operands[1])"
+ [(parallel[
+ (set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI (sign_extend:DI (match_dup 0))
+ (sign_extend:DI (match_dup 1)))
+ (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))
+ (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))])]
)
(define_insn "addsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r")
(match_operand:SI 2 "arm_add_operand" "I,L,r"))
(const_int 0)))
)
(define_insn "*addsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r")
(match_operand:SI 1 "arm_add_operand" "I,L, r"))
(const_int 0)))]
;; the operands, and we know that the use of the condition code is
;; either GEU or LTU, so we can use the carry flag from the addition
;; instead of doing the compare a second time.
-(define_insn "*addsi3_compare_op1"
+(define_insn "addsi3_compare_op1"
[(set (reg:CC_C CC_REGNUM)
(compare:CC_C
- (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r")
- (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r"))
+ (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,rk,rk")
+ (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,rkI,L"))
(match_dup 1)))
- (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r")
+ (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,rk,rk")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_32BIT"
"@
subs%?\\t%0, %1, #%n2
subs%?\\t%0, %0, #%n2
adds%?\\t%0, %1, %2
- subs%?\\t%0, %1, #%n2
- adds%?\\t%0, %1, %2"
+ subs%?\\t%0, %1, #%n2"
[(set_attr "conds" "set")
- (set_attr "arch" "t2,t2,t2,t2,*,*,*")
- (set_attr "length" "2,2,2,2,4,4,4")
- (set_attr "type"
- "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")]
+ (set_attr "arch" "t2,t2,t2,t2,*,*")
+ (set_attr "length" "2,2,2,2,4,4")
+ (set (attr "type")
+ (if_then_else (match_operand 2 "const_int_operand")
+ (const_string "alu_imm")
+ (const_string "alu_sreg")))]
)
(define_insn "*addsi3_compare_op2"
[(set (reg:CC_C CC_REGNUM)
(compare:CC_C
- (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r")
- (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r"))
+ (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r")
+ (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,rI,L"))
(match_dup 2)))
- (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r")
+ (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_32BIT"
"@
subs%?\\t%0, %1, #%n2
subs%?\\t%0, %0, #%n2
adds%?\\t%0, %1, %2
- subs%?\\t%0, %1, #%n2
- adds%?\\t%0, %1, %2"
+ subs%?\\t%0, %1, #%n2"
[(set_attr "conds" "set")
- (set_attr "arch" "t2,t2,t2,t2,*,*,*")
- (set_attr "length" "2,2,2,2,4,4,4")
- (set_attr "type"
- "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")]
+ (set_attr "arch" "t2,t2,t2,t2,*,*")
+ (set_attr "length" "2,2,2,2,4,4")
+ (set (attr "type")
+ (if_then_else (match_operand 2 "const_int_operand")
+ (const_string "alu_imm")
+ (const_string "alu_sreg")))]
)
(define_insn "*compare_addsi2_op0"
[(set (reg:CC_C CC_REGNUM)
(compare:CC_C
- (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r")
- (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r"))
+ (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r")
+ (match_operand:SI 1 "arm_add_operand" "l,Pw,rI,L"))
(match_dup 0)))]
"TARGET_32BIT"
"@
- cmp%?\\t%0, #%n1
- cmn%?\\t%0, %1
cmn%?\\t%0, %1
cmp%?\\t%0, #%n1
- cmn%?\\t%0, %1"
+ cmn%?\\t%0, %1
+ cmp%?\\t%0, #%n1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "arch" "t2,t2,*,*,*")
- (set_attr "predicable_short_it" "yes,yes,no,no,no")
- (set_attr "length" "2,2,4,4,4")
- (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
+ (set_attr "arch" "t2,t2,*,*")
+ (set_attr "predicable_short_it" "yes,yes,no,no")
+ (set_attr "length" "2,2,4,4")
+ (set (attr "type")
+ (if_then_else (match_operand 1 "const_int_operand")
+ (const_string "alu_imm")
+ (const_string "alu_sreg")))]
)
(define_insn "*compare_addsi2_op1"
[(set (reg:CC_C CC_REGNUM)
(compare:CC_C
- (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r")
- (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r"))
+ (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r")
+ (match_operand:SI 1 "arm_add_operand" "l,Pw,rI,L"))
(match_dup 1)))]
"TARGET_32BIT"
"@
- cmp%?\\t%0, #%n1
- cmn%?\\t%0, %1
cmn%?\\t%0, %1
cmp%?\\t%0, #%n1
- cmn%?\\t%0, %1"
+ cmn%?\\t%0, %1
+ cmp%?\\t%0, #%n1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "arch" "t2,t2,*,*,*")
- (set_attr "predicable_short_it" "yes,yes,no,no,no")
- (set_attr "length" "2,2,4,4,4")
- (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
+ (set_attr "arch" "t2,t2,*,*")
+ (set_attr "predicable_short_it" "yes,yes,no,no")
+ (set_attr "length" "2,2,4,4")
+ (set (attr "type")
+ (if_then_else (match_operand 1 "const_int_operand")
+ (const_string "alu_imm")
+ (const_string "alu_sreg")))]
)
-(define_insn "*addsi3_carryin_<optab>"
+(define_insn "addsi3_carryin"
[(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%l,r,r")
(match_operand:SI 2 "arm_not_operand" "0,rI,K"))
- (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
+ (match_operand:SI 3 "arm_carry_operation" "")))]
"TARGET_32BIT"
"@
adc%?\\t%0, %1, %2
(set_attr "type" "adc_reg,adc_reg,adc_imm")]
)
-(define_insn "*addsi3_carryin_alt2_<optab>"
+;; Canonicalization of the above when the immediate is zero.
+(define_insn "add0si3_carryin"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (plus:SI (match_operand:SI 2 "arm_carry_operation" "")
+ (match_operand:SI 1 "arm_not_operand" "r")))]
+ "TARGET_32BIT"
+ "adc%?\\t%0, %1, #0"
+ [(set_attr "conds" "use")
+ (set_attr "predicable" "yes")
+ (set_attr "length" "4")
+ (set_attr "type" "adc_imm")]
+)
+
+(define_insn "*addsi3_carryin_alt2"
[(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
- (plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
+ (plus:SI (plus:SI (match_operand:SI 3 "arm_carry_operation" "")
(match_operand:SI 1 "s_register_operand" "%l,r,r"))
- (match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))]
+ (match_operand:SI 2 "arm_not_operand" "l,rI,K")))]
"TARGET_32BIT"
"@
adc%?\\t%0, %1, %2
(set_attr "type" "adc_reg,adc_reg,adc_imm")]
)
-(define_insn "*addsi3_carryin_shift_<optab>"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+(define_insn "*addsi3_carryin_shift"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(plus:SI (plus:SI
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "reg_or_int_operand" "rM")])
- (match_operand:SI 1 "s_register_operand" "r"))
- (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r")])
+ (match_operand:SI 5 "arm_carry_operation" ""))
+ (match_operand:SI 1 "s_register_operand" "r,r")))]
"TARGET_32BIT"
"adc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
+ (set_attr "arch" "32,a")
+ (set_attr "shift" "3")
(set_attr "predicable" "yes")
- (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift_imm")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "alu_shift_imm,alu_shift_reg")]
)
-(define_insn "*addsi3_carryin_clobercc_<optab>"
+(define_insn "*addsi3_carryin_clobercc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
- (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))
+ (match_operand:SI 3 "arm_carry_operation" "")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
"adcs%?\\t%0, %1, %2"
(set_attr "type" "adcs_reg")]
)
-(define_expand "subv<mode>4"
- [(match_operand:SIDI 0 "register_operand")
- (match_operand:SIDI 1 "register_operand")
- (match_operand:SIDI 2 "register_operand")
+(define_expand "subvsi4"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "arm_rhs_operand")
+ (match_operand:SI 2 "arm_add_operand")
+ (match_operand 3 "")]
+ "TARGET_32BIT"
+{
+ if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2]))
+ {
+ /* If both operands are constants we can decide the result statically. */
+ wi::overflow_type overflow;
+ wide_int val = wi::sub (rtx_mode_t (operands[1], SImode),
+ rtx_mode_t (operands[2], SImode),
+ SIGNED, &overflow);
+ emit_move_insn (operands[0], GEN_INT (val.to_shwi ()));
+ if (overflow != wi::OVF_NONE)
+ emit_jump_insn (gen_jump (operands[3]));
+ DONE;
+ }
+ else if (CONST_INT_P (operands[2]))
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ /* Special case for INT_MIN. */
+ if (INTVAL (operands[2]) == 0x80000000)
+ emit_insn (gen_subvsi3_intmin (operands[0], operands[1]));
+ else
+ emit_insn (gen_addsi3_compareV_imm (operands[0], operands[1],
+ operands[2]));
+ }
+ else if (CONST_INT_P (operands[1]))
+ emit_insn (gen_subvsi3_imm1 (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_subvsi3 (operands[0], operands[1], operands[2]));
+
+ arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
+ DONE;
+})
+
+(define_expand "subvdi4"
+ [(match_operand:DI 0 "s_register_operand")
+ (match_operand:DI 1 "reg_or_int_operand")
+ (match_operand:DI 2 "reg_or_int_operand")
(match_operand 3 "")]
"TARGET_32BIT"
{
- emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
+ rtx lo_result, hi_result;
+ rtx lo_op1, hi_op1, lo_op2, hi_op2;
+ lo_result = gen_lowpart (SImode, operands[0]);
+ hi_result = gen_highpart (SImode, operands[0]);
+ machine_mode mode = CCmode;
+
+ if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2]))
+ {
+ /* If both operands are constants we can decide the result statically. */
+ wi::overflow_type overflow;
+ wide_int val = wi::sub (rtx_mode_t (operands[1], DImode),
+ rtx_mode_t (operands[2], DImode),
+ SIGNED, &overflow);
+ emit_move_insn (operands[0], GEN_INT (val.to_shwi ()));
+ if (overflow != wi::OVF_NONE)
+ emit_jump_insn (gen_jump (operands[3]));
+ DONE;
+ }
+ else if (CONST_INT_P (operands[1]))
+ {
+ arm_decompose_di_binop (operands[2], operands[1], &lo_op2, &hi_op2,
+ &lo_op1, &hi_op1);
+ if (const_ok_for_arm (INTVAL (lo_op1)))
+ {
+ emit_insn (gen_rsb_imm_compare (lo_result, lo_op1, lo_op2,
+ GEN_INT (~UINTVAL (lo_op1))));
+ /* We could potentially use RSC here in Arm state, but not
+ in Thumb, so it's probably not worth the effort of handling
+ this. */
+ hi_op1 = force_reg (SImode, hi_op1);
+ mode = CC_RSBmode;
+ goto highpart;
+ }
+ operands[1] = force_reg (DImode, operands[1]);
+ }
+
+ arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
+ &lo_op2, &hi_op2);
+ if (lo_op2 == const0_rtx)
+ {
+ emit_move_insn (lo_result, lo_op1);
+ if (!arm_add_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+ emit_insn (gen_subvsi4 (hi_result, hi_op1, hi_op2, operands[3]));
+ DONE;
+ }
+
+ if (CONST_INT_P (lo_op2) && !arm_addimm_operand (lo_op2, SImode))
+ lo_op2 = force_reg (SImode, lo_op2);
+ if (CONST_INT_P (lo_op2))
+ emit_insn (gen_cmpsi2_addneg (lo_result, lo_op1, lo_op2,
+ GEN_INT (-INTVAL (lo_op2))));
+ else
+ emit_insn (gen_subsi3_compare1 (lo_result, lo_op1, lo_op2));
+
+ highpart:
+ if (!arm_not_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+ rtx ccreg = gen_rtx_REG (mode, CC_REGNUM);
+ if (CONST_INT_P (hi_op2))
+ emit_insn (gen_subvsi3_borrow_imm (hi_result, hi_op1, hi_op2,
+ gen_rtx_LTU (SImode, ccreg, const0_rtx),
+ gen_rtx_LTU (DImode, ccreg,
+ const0_rtx)));
+ else
+ emit_insn (gen_subvsi3_borrow (hi_result, hi_op1, hi_op2,
+ gen_rtx_LTU (SImode, ccreg, const0_rtx),
+ gen_rtx_LTU (DImode, ccreg, const0_rtx)));
arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
DONE;
})
-(define_expand "usubv<mode>4"
- [(match_operand:SIDI 0 "register_operand")
- (match_operand:SIDI 1 "register_operand")
- (match_operand:SIDI 2 "register_operand")
+(define_expand "usubvsi4"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "arm_rhs_operand")
+ (match_operand:SI 2 "arm_add_operand")
(match_operand 3 "")]
"TARGET_32BIT"
{
- emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
- arm_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
+ machine_mode mode = CCmode;
+ if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2]))
+ {
+ /* If both operands are constants we can decide the result statically. */
+ wi::overflow_type overflow;
+ wide_int val = wi::sub (rtx_mode_t (operands[1], SImode),
+ rtx_mode_t (operands[2], SImode),
+ UNSIGNED, &overflow);
+ emit_move_insn (operands[0], GEN_INT (val.to_shwi ()));
+ if (overflow != wi::OVF_NONE)
+ emit_jump_insn (gen_jump (operands[3]));
+ DONE;
+ }
+ else if (CONST_INT_P (operands[2]))
+ emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
+ GEN_INT (-INTVAL (operands[2]))));
+ else if (CONST_INT_P (operands[1]))
+ {
+ mode = CC_RSBmode;
+ emit_insn (gen_rsb_imm_compare (operands[0], operands[1], operands[2],
+ GEN_INT (~UINTVAL (operands[1]))));
+ }
+ else
+ emit_insn (gen_subsi3_compare1 (operands[0], operands[1], operands[2]));
+ arm_gen_unlikely_cbranch (LTU, mode, operands[3]);
DONE;
})
-(define_insn_and_split "subdi3_compare1"
- [(set (reg:CC CC_REGNUM)
- (compare:CC
- (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "register_operand" "r")))
- (set (match_operand:DI 0 "register_operand" "=&r")
- (minus:DI (match_dup 1) (match_dup 2)))]
+(define_expand "usubvdi4"
+ [(match_operand:DI 0 "s_register_operand")
+ (match_operand:DI 1 "reg_or_int_operand")
+ (match_operand:DI 2 "reg_or_int_operand")
+ (match_operand 3 "")]
"TARGET_32BIT"
- "#"
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 4) (match_dup 5)))
- (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))])]
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[5] = gen_highpart (SImode, operands[2]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- }
- [(set_attr "conds" "set")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
+{
+ rtx lo_result, hi_result;
+ rtx lo_op1, hi_op1, lo_op2, hi_op2;
+ lo_result = gen_lowpart (SImode, operands[0]);
+ hi_result = gen_highpart (SImode, operands[0]);
+ machine_mode mode = CCmode;
+
+ if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2]))
+ {
+ /* If both operands are constants we can decide the result statically. */
+ wi::overflow_type overflow;
+ wide_int val = wi::sub (rtx_mode_t (operands[1], DImode),
+ rtx_mode_t (operands[2], DImode),
+ UNSIGNED, &overflow);
+ emit_move_insn (operands[0], GEN_INT (val.to_shwi ()));
+ if (overflow != wi::OVF_NONE)
+ emit_jump_insn (gen_jump (operands[3]));
+ DONE;
+ }
+ else if (CONST_INT_P (operands[1]))
+ {
+ arm_decompose_di_binop (operands[2], operands[1], &lo_op2, &hi_op2,
+ &lo_op1, &hi_op1);
+ if (const_ok_for_arm (INTVAL (lo_op1)))
+ {
+ emit_insn (gen_rsb_imm_compare (lo_result, lo_op1, lo_op2,
+ GEN_INT (~UINTVAL (lo_op1))));
+ /* We could potentially use RSC here in Arm state, but not
+ in Thumb, so it's probably not worth the effort of handling
+ this. */
+ hi_op1 = force_reg (SImode, hi_op1);
+ mode = CC_RSBmode;
+ goto highpart;
+ }
+ operands[1] = force_reg (DImode, operands[1]);
+ }
+
+ arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
+ &lo_op2, &hi_op2);
+ if (lo_op2 == const0_rtx)
+ {
+ emit_move_insn (lo_result, lo_op1);
+ if (!arm_add_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+ emit_insn (gen_usubvsi4 (hi_result, hi_op1, hi_op2, operands[3]));
+ DONE;
+ }
+
+ if (CONST_INT_P (lo_op2) && !arm_addimm_operand (lo_op2, SImode))
+ lo_op2 = force_reg (SImode, lo_op2);
+ if (CONST_INT_P (lo_op2))
+ emit_insn (gen_cmpsi2_addneg (lo_result, lo_op1, lo_op2,
+ GEN_INT (-INTVAL (lo_op2))));
+ else
+ emit_insn (gen_subsi3_compare1 (lo_result, lo_op1, lo_op2));
+
+ highpart:
+ if (!arm_not_operand (hi_op2, SImode))
+ hi_op2 = force_reg (SImode, hi_op2);
+ rtx ccreg = gen_rtx_REG (mode, CC_REGNUM);
+ if (CONST_INT_P (hi_op2))
+ emit_insn (gen_usubvsi3_borrow_imm (hi_result, hi_op1, hi_op2,
+ GEN_INT (UINTVAL (hi_op2) & 0xffffffff),
+ gen_rtx_LTU (SImode, ccreg, const0_rtx),
+ gen_rtx_LTU (DImode, ccreg,
+ const0_rtx)));
+ else
+ emit_insn (gen_usubvsi3_borrow (hi_result, hi_op1, hi_op2,
+ gen_rtx_LTU (SImode, ccreg, const0_rtx),
+ gen_rtx_LTU (DImode, ccreg, const0_rtx)));
+ arm_gen_unlikely_cbranch (LTU, CC_Bmode, operands[3]);
+
+ DONE;
+})
(define_insn "subsi3_compare1"
[(set (reg:CC CC_REGNUM)
(set_attr "type" "alus_sreg")]
)
-(define_insn "*subsi3_carryin"
+(define_insn "subvsi3"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (minus:DI
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "l,r"))
+ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "l,r")))
+ (sign_extend:DI (minus:SI (match_dup 1) (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand" "=l,r")
+ (minus:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT"
+ "subs%?\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,4")
+ (set_attr "type" "alus_sreg")]
+)
+
+(define_insn "subvsi3_imm1"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (minus:DI
+ (match_operand 1 "arm_immediate_operand" "I")
+ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
+ (sign_extend:DI (minus:SI (match_dup 1) (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand" "=r")
+ (minus:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT"
+ "rsbs%?\\t%0, %2, %1"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_imm")]
+)
+
+(define_insn "subsi3_carryin"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I,Pz")
(match_operand:SI 2 "s_register_operand" "r,r,r"))
(set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
)
+;; Special canonicalization of the above when operand1 == (const_int 1):
+;; in this case the 'borrow' needs to treated like subtracting from the carry.
+(define_insn "rsbsi_carryin_reg"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (minus:SI (match_operand:SI 1 "arm_carry_operation" "")
+ (match_operand:SI 2 "s_register_operand" "r")))]
+ "TARGET_ARM"
+ "rsc%?\\t%0, %2, #1"
+ [(set_attr "conds" "use")
+ (set_attr "predicable" "yes")
+ (set_attr "type" "adc_imm")]
+)
+
+;; SBC performs Rn - Rm - ~C, but -Rm = ~Rm + 1 => Rn + ~Rm + 1 - ~C
+;; => Rn + ~Rm + C, which is essentially ADC Rd, Rn, ~Rm
+(define_insn "*add_not_cin"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (plus:SI
+ (plus:SI (not:SI (match_operand:SI 1 "s_register_operand" "r,r"))
+ (match_operand:SI 3 "arm_carry_operation" ""))
+ (match_operand:SI 2 "arm_rhs_operand" "r,I")))]
+ "TARGET_ARM || (TARGET_THUMB2 && !CONST_INT_P (operands[2]))"
+ "@
+ sbc%?\\t%0, %2, %1
+ rsc%?\\t%0, %1, %2"
+ [(set_attr "conds" "use")
+ (set_attr "predicable" "yes")
+ (set_attr "arch" "*,a")
+ (set_attr "type" "adc_reg,adc_imm")]
+)
+
+;; On Arm we can also use the same trick when the non-inverted operand is
+;; shifted, using RSC.
+(define_insn "add_not_shift_cin"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (plus:SI
+ (plus:SI (match_operator:SI 3 "shift_operator"
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "shift_amount_operand" "M,r")])
+ (not:SI (match_operand:SI 4 "s_register_operand" "r,r")))
+ (match_operand:SI 5 "arm_carry_operation" "")))]
+ "TARGET_ARM"
+ "rsc%?\\t%0, %4, %1%S3"
+ [(set_attr "conds" "use")
+ (set_attr "predicable" "yes")
+ (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+)
+
+(define_insn "cmpsi3_carryin_<CC_EXTEND>out"
+ [(set (reg:<CC_EXTEND> CC_REGNUM)
+ (compare:<CC_EXTEND>
+ (SE:DI (match_operand:SI 1 "s_register_operand" "0,r"))
+ (plus:DI (match_operand:DI 3 "arm_borrow_operation" "")
+ (SE:DI (match_operand:SI 2 "s_register_operand" "l,r")))))
+ (clobber (match_scratch:SI 0 "=l,r"))]
+ "TARGET_32BIT"
+ "sbcs\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,4")
+ (set_attr "type" "adc_reg")]
+)
+
+;; Similar to the above, but handling a constant which has a different
+;; canonicalization.
+(define_insn "cmpsi3_imm_carryin_<CC_EXTEND>out"
+ [(set (reg:<CC_EXTEND> CC_REGNUM)
+ (compare:<CC_EXTEND>
+ (SE:DI (match_operand:SI 1 "s_register_operand" "r,r"))
+ (plus:DI (match_operand:DI 3 "arm_borrow_operation" "")
+ (match_operand:DI 2 "arm_adcimm_operand" "I,K"))))
+ (clobber (match_scratch:SI 0 "=l,r"))]
+ "TARGET_32BIT"
+ "@
+ sbcs\\t%0, %1, %2
+ adcs\\t%0, %1, #%B2"
+ [(set_attr "conds" "set")
+ (set_attr "type" "adc_imm")]
+)
+
+;; Further canonicalization when the constant is zero.
+(define_insn "cmpsi3_0_carryin_<CC_EXTEND>out"
+ [(set (reg:<CC_EXTEND> CC_REGNUM)
+ (compare:<CC_EXTEND>
+ (SE:DI (match_operand:SI 1 "s_register_operand" "r,r"))
+ (match_operand:DI 2 "arm_borrow_operation" "")))
+ (clobber (match_scratch:SI 0 "=l,r"))]
+ "TARGET_32BIT"
+ "sbcs\\t%0, %1, #0"
+ [(set_attr "conds" "set")
+ (set_attr "type" "adc_imm")]
+)
+
(define_insn "*subsi3_carryin_const"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(minus:SI (plus:SI
(set_attr "type" "adc_imm")]
)
-(define_insn "*subsi3_carryin_compare"
- [(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "s_register_operand" "r")))
- (set (match_operand:SI 0 "s_register_operand" "=r")
- (minus:SI (minus:SI (match_dup 1) (match_dup 2))
- (match_operand:SI 3 "arm_borrow_operation" "")))]
+(define_insn "*subsi3_carryin_shift"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (minus:SI (minus:SI
+ (match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operator:SI 2 "shift_operator"
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r")]))
+ (match_operand:SI 5 "arm_borrow_operation" "")))]
"TARGET_32BIT"
- "sbcs\\t%0, %1, %2"
- [(set_attr "conds" "set")
- (set_attr "type" "adcs_reg")]
-)
-
-(define_insn "*subsi3_carryin_compare_const"
- [(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r")
- (match_operand:SI 2 "const_int_I_operand" "I")))
- (set (match_operand:SI 0 "s_register_operand" "=r")
- (minus:SI (plus:SI
- (match_dup 1)
- (match_operand:SI 3 "arm_neg_immediate_operand" "L"))
- (match_operand:SI 4 "arm_borrow_operation" "")))]
- "TARGET_32BIT
- && (INTVAL (operands[2])
- == trunc_int_for_mode (-INTVAL (operands[3]), SImode))"
- "sbcs\\t%0, %1, #%n3"
- [(set_attr "conds" "set")
- (set_attr "type" "adcs_imm")]
+ "sbc%?\\t%0, %1, %3%S2"
+ [(set_attr "conds" "use")
+ (set_attr "arch" "32,a")
+ (set_attr "shift" "3")
+ (set_attr "predicable" "yes")
+ (set_attr "type" "alu_shift_imm,alu_shift_reg")]
)
-(define_insn "*subsi3_carryin_compare_const0"
- [(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r")
- (const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=r")
- (minus:SI (match_dup 1)
- (match_operand:SI 2 "arm_borrow_operation" "")))]
+(define_insn "*subsi3_carryin_shift_alt"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (minus:SI (minus:SI
+ (match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 5 "arm_borrow_operation" ""))
+ (match_operator:SI 2 "shift_operator"
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r")])))]
"TARGET_32BIT"
- "sbcs\\t%0, %1, #0"
- [(set_attr "conds" "set")
- (set_attr "type" "adcs_imm")]
+ "sbc%?\\t%0, %1, %3%S2"
+ [(set_attr "conds" "use")
+ (set_attr "arch" "32,a")
+ (set_attr "shift" "3")
+ (set_attr "predicable" "yes")
+ (set_attr "type" "alu_shift_imm,alu_shift_reg")]
)
-(define_insn "*subsi3_carryin_shift"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+;; No RSC in Thumb2
+(define_insn "*rsbsi3_carryin_shift"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (minus:SI
- (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "reg_or_int_operand" "rM")]))
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r")])
+ (match_operand:SI 1 "s_register_operand" "r,r"))
(match_operand:SI 5 "arm_borrow_operation" "")))]
- "TARGET_32BIT"
- "sbc%?\\t%0, %1, %3%S2"
+ "TARGET_ARM"
+ "rsc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
- (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift_imm")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "alu_shift_imm,alu_shift_reg")]
)
-(define_insn "*rsbsi3_carryin_shift"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+(define_insn "*rsbsi3_carryin_shift_alt"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (minus:SI
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "reg_or_int_operand" "rM")])
- (match_operand:SI 1 "s_register_operand" "r"))
- (match_operand:SI 5 "arm_borrow_operation" "")))]
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r")])
+ (match_operand:SI 5 "arm_borrow_operation" ""))
+ (match_operand:SI 1 "s_register_operand" "r,r")))]
"TARGET_ARM"
"rsc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
- (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift_imm")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "alu_shift_imm,alu_shift_reg")]
)
; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
(define_expand "subdi3"
[(parallel
[(set (match_operand:DI 0 "s_register_operand")
- (minus:DI (match_operand:DI 1 "s_register_operand")
- (match_operand:DI 2 "s_register_operand")))
+ (minus:DI (match_operand:DI 1 "reg_or_int_operand")
+ (match_operand:DI 2 "s_register_operand")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
if (TARGET_THUMB1)
{
if (!REG_P (operands[1]))
- operands[1] = force_reg (DImode, operands[1]);
- if (!REG_P (operands[2]))
- operands[2] = force_reg (DImode, operands[2]);
- }
- "
-)
-
-(define_insn_and_split "*arm_subdi3"
- [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r")
- (minus:DI (match_operand:DI 1 "arm_general_register_operand" "0,r,0")
- (match_operand:DI 2 "arm_general_register_operand" "r,0,0")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT && !TARGET_NEON"
- "#" ; "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
- "&& (!TARGET_IWMMXT || reload_completed)"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[5] = gen_highpart (SImode, operands[2]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- }
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
+ operands[1] = force_reg (DImode, operands[1]);
+ }
+ else
+ {
+ rtx lo_result, hi_result, lo_dest, hi_dest;
+ rtx lo_op1, hi_op1, lo_op2, hi_op2;
+ rtx condition;
+
+ /* Since operands[1] may be an integer, pass it second, so that
+ any necessary simplifications will be done on the decomposed
+ constant. */
+ arm_decompose_di_binop (operands[2], operands[1], &lo_op2, &hi_op2,
+ &lo_op1, &hi_op1);
+ lo_result = lo_dest = gen_lowpart (SImode, operands[0]);
+ hi_result = hi_dest = gen_highpart (SImode, operands[0]);
+
+ if (!arm_rhs_operand (lo_op1, SImode))
+ lo_op1 = force_reg (SImode, lo_op1);
+
+ if ((TARGET_THUMB2 && ! s_register_operand (hi_op1, SImode))
+ || !arm_rhs_operand (hi_op1, SImode))
+ hi_op1 = force_reg (SImode, hi_op1);
+
+ rtx cc_reg;
+ if (lo_op1 == const0_rtx)
+ {
+ cc_reg = gen_rtx_REG (CC_RSBmode, CC_REGNUM);
+ emit_insn (gen_negsi2_0compare (lo_dest, lo_op2));
+ }
+ else if (CONST_INT_P (lo_op1))
+ {
+ cc_reg = gen_rtx_REG (CC_RSBmode, CC_REGNUM);
+ emit_insn (gen_rsb_imm_compare (lo_dest, lo_op1, lo_op2,
+ GEN_INT (~UINTVAL (lo_op1))));
+ }
+ else
+ {
+ cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
+ emit_insn (gen_subsi3_compare (lo_dest, lo_op1, lo_op2));
+ }
-(define_insn_and_split "*subdi_di_zesidi"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (minus:DI (match_operand:DI 1 "s_register_operand" "0,r")
- (zero_extend:DI
- (match_operand:SI 2 "s_register_operand" "r,r"))))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT"
- "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0"
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (set (match_dup 3) (minus:SI (match_dup 4)
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- }
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
+ condition = gen_rtx_LTU (SImode, cc_reg, const0_rtx);
-(define_insn_and_split "*subdi_di_sesidi"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (minus:DI (match_operand:DI 1 "s_register_operand" "0,r")
- (sign_extend:DI
- (match_operand:SI 2 "s_register_operand" "r,r"))))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT"
- "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31"
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (set (match_dup 3) (minus:SI (minus:SI (match_dup 4)
- (ashiftrt:SI (match_dup 2)
- (const_int 31)))
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- }
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
+ if (hi_op1 == const0_rtx)
+ emit_insn (gen_negsi2_carryin (hi_dest, hi_op2, condition));
+ else
+ emit_insn (gen_subsi3_carryin (hi_dest, hi_op1, hi_op2, condition));
-(define_insn_and_split "*subdi_zesidi_di"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (minus:DI (zero_extend:DI
- (match_operand:SI 2 "s_register_operand" "r,r"))
- (match_operand:DI 1 "s_register_operand" "0,r")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_ARM"
- "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0"
- ; is equivalent to:
- ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, #0"
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 2) (match_dup 1)))
- (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))])
- (set (match_dup 3) (minus:SI (minus:SI (const_int 0) (match_dup 4))
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- }
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
+ if (lo_result != lo_dest)
+ emit_move_insn (lo_result, lo_dest);
-(define_insn_and_split "*subdi_sesidi_di"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (minus:DI (sign_extend:DI
- (match_operand:SI 2 "s_register_operand" "r,r"))
- (match_operand:DI 1 "s_register_operand" "0,r")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_ARM"
- "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31"
- ; is equivalent to:
- ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, %2, asr #31"
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 2) (match_dup 1)))
- (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))])
- (set (match_dup 3) (minus:SI (minus:SI
- (ashiftrt:SI (match_dup 2)
- (const_int 31))
- (match_dup 4))
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- }
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
+ if (hi_result != hi_dest)
+ emit_move_insn (hi_result, hi_dest);
-(define_insn_and_split "*subdi_zesidi_zesidi"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (minus:DI (zero_extend:DI
- (match_operand:SI 1 "s_register_operand" "r"))
- (zero_extend:DI
- (match_operand:SI 2 "s_register_operand" "r"))))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT"
- "#" ; "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1"
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 1))
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- }
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
+ DONE;
+ }
+ "
)
(define_expand "subsi3"
)
(define_insn "subsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I")
(match_operand:SI 2 "arm_rhs_operand" "I,r,r"))
(const_int 0)))
subs%?\\t%0, %1, %2
rsbs%?\\t%0, %2, %1"
[(set_attr "conds" "set")
- (set_attr "type" "alus_imm,alus_sreg,alus_sreg")]
+ (set_attr "type" "alus_imm,alus_sreg,alus_imm")]
+)
+
+;; To keep the comparison in canonical form we express it as (~reg cmp ~0)
+;; rather than (0 cmp reg). This gives the same results for unsigned
+;; and equality compares which is what we mostly need here.
+(define_insn "rsb_imm_compare"
+ [(set (reg:CC_RSB CC_REGNUM)
+ (compare:CC_RSB (not:SI (match_operand:SI 2 "s_register_operand" "r"))
+ (match_operand 3 "const_int_operand" "")))
+ (set (match_operand:SI 0 "s_register_operand" "=r")
+ (minus:SI (match_operand 1 "arm_immediate_operand" "I")
+ (match_dup 2)))]
+ "TARGET_32BIT && ~UINTVAL (operands[1]) == UINTVAL (operands[3])"
+ "rsbs\\t%0, %2, %1"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_imm")]
+)
+
+;; Similarly, but the result is unused.
+(define_insn "rsb_imm_compare_scratch"
+ [(set (reg:CC_RSB CC_REGNUM)
+ (compare:CC_RSB (not:SI (match_operand:SI 2 "s_register_operand" "r"))
+ (match_operand 1 "arm_not_immediate_operand" "K")))
+ (clobber (match_scratch:SI 0 "=r"))]
+ "TARGET_32BIT"
+ "rsbs\\t%0, %2, #%B1"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_imm")]
+)
+
+;; Compare the sum of a value plus a carry against a constant. Uses
+;; RSC, so the result is swapped. Only available on Arm
+(define_insn "rscsi3_<CC_EXTEND>out_scratch"
+ [(set (reg:CC_SWP CC_REGNUM)
+ (compare:CC_SWP
+ (plus:DI (SE:DI (match_operand:SI 2 "s_register_operand" "r"))
+ (match_operand:DI 3 "arm_borrow_operation" ""))
+ (match_operand 1 "arm_immediate_operand" "I")))
+ (clobber (match_scratch:SI 0 "=r"))]
+ "TARGET_ARM"
+ "rscs\\t%0, %2, %1"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_imm")]
+)
+
+(define_insn "usubvsi3_borrow"
+ [(set (reg:CC_B CC_REGNUM)
+ (compare:CC_B
+ (zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r"))
+ (plus:DI (match_operand:DI 4 "arm_borrow_operation" "")
+ (zero_extend:DI
+ (match_operand:SI 2 "s_register_operand" "l,r")))))
+ (set (match_operand:SI 0 "s_register_operand" "=l,r")
+ (minus:SI (match_dup 1)
+ (plus:SI (match_operand:SI 3 "arm_borrow_operation" "")
+ (match_dup 2))))]
+ "TARGET_32BIT"
+ "sbcs%?\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,4")]
+)
+
+(define_insn "usubvsi3_borrow_imm"
+ [(set (reg:CC_B CC_REGNUM)
+ (compare:CC_B
+ (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r,r"))
+ (plus:DI (match_operand:DI 5 "arm_borrow_operation" "")
+ (match_operand:DI 3 "const_int_operand" "n,n"))))
+ (set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (minus:SI (match_dup 1)
+ (plus:SI (match_operand:SI 4 "arm_borrow_operation" "")
+ (match_operand:SI 2 "arm_adcimm_operand" "I,K"))))]
+ "TARGET_32BIT
+ && (UINTVAL (operands[2]) & 0xffffffff) == UINTVAL (operands[3])"
+ "@
+ sbcs%?\\t%0, %1, %2
+ adcs%?\\t%0, %1, #%B2"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_imm")]
+)
+
+(define_insn "subvsi3_borrow"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (minus:DI
+ (minus:DI
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "0,r"))
+ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "l,r")))
+ (match_operand:DI 4 "arm_borrow_operation" ""))
+ (sign_extend:DI
+ (minus:SI (minus:SI (match_dup 1) (match_dup 2))
+ (match_operand:SI 3 "arm_borrow_operation" "")))))
+ (set (match_operand:SI 0 "s_register_operand" "=l,r")
+ (minus:SI (minus:SI (match_dup 1) (match_dup 2))
+ (match_dup 3)))]
+ "TARGET_32BIT"
+ "sbcs%?\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,4")]
+)
+
+(define_insn "subvsi3_borrow_imm"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (minus:DI
+ (minus:DI
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r,r"))
+ (match_operand 2 "arm_adcimm_operand" "I,K"))
+ (match_operand:DI 4 "arm_borrow_operation" ""))
+ (sign_extend:DI
+ (minus:SI (minus:SI (match_dup 1) (match_dup 2))
+ (match_operand:SI 3 "arm_borrow_operation" "")))))
+ (set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (minus:SI (minus:SI (match_dup 1) (match_dup 2))
+ (match_dup 3)))]
+ "TARGET_32BIT
+ && INTVAL (operands[2]) == ARM_SIGN_EXTEND (INTVAL (operands[2]))"
+ "@
+ sbcs%?\\t%0, %1, %2
+ adcs%?\\t%0, %1, #%B2"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_imm")]
)
(define_expand "subsf3"
""
)
-;; Use `&' and then `0' to prevent the operands 0 and 1 being the same
-(define_insn "*arm_mulsi3"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
- (mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
- (match_operand:SI 1 "s_register_operand" "%0,r")))]
- "TARGET_32BIT && !arm_arch6"
+;; Use `&' and then `0' to prevent operands 0 and 2 being the same
+(define_insn "*mul"
+ [(set (match_operand:SI 0 "s_register_operand" "=l,r,&r,&r")
+ (mult:SI (match_operand:SI 2 "s_register_operand" "l,r,r,r")
+ (match_operand:SI 1 "s_register_operand" "%0,r,0,r")))]
+ "TARGET_32BIT"
"mul%?\\t%0, %2, %1"
[(set_attr "type" "mul")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "arch" "t2,v6,nov6,nov6")
+ (set_attr "length" "4")
+ (set_attr "predicable_short_it" "yes,no,*,*")]
)
-(define_insn "*arm_mulsi3_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
- (mult:SI (match_operand:SI 1 "s_register_operand" "0,l,r")
- (match_operand:SI 2 "s_register_operand" "l,0,r")))]
- "TARGET_32BIT && arm_arch6"
- "mul%?\\t%0, %1, %2"
- [(set_attr "type" "mul")
+;; MLA and MLS instruction. Use operand 1 for the accumulator to prefer
+;; reusing the same register.
+
+(define_insn "*mla"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r,&r")
+ (plus:SI
+ (mult:SI (match_operand:SI 3 "s_register_operand" "r,r,r,r")
+ (match_operand:SI 2 "s_register_operand" "%r,r,0,r"))
+ (match_operand:SI 1 "s_register_operand" "r,0,r,r")))]
+ "TARGET_32BIT"
+ "mla%?\\t%0, %3, %2, %1"
+ [(set_attr "type" "mla")
(set_attr "predicable" "yes")
- (set_attr "arch" "t2,t2,*")
- (set_attr "length" "4")
- (set_attr "predicable_short_it" "yes,yes,no")]
+ (set_attr "arch" "v6,nov6,nov6,nov6")]
+)
+
+(define_insn "*mls"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (minus:SI
+ (match_operand:SI 1 "s_register_operand" "r")
+ (mult:SI (match_operand:SI 3 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r"))))]
+ "TARGET_32BIT && arm_arch_thumb2"
+ "mls%?\\t%0, %3, %2, %1"
+ [(set_attr "type" "mla")
+ (set_attr "predicable" "yes")]
)
(define_insn "*mulsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (mult:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%0,r"))
(const_int 0)))
)
(define_insn "*mulsi3_compare0_v6"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (mult:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (mult:SI
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
)
(define_insn "*mulsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (mult:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%0,r"))
(const_int 0)))
)
(define_insn "*mulsi_compare0_scratch_v6"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (mult:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (mult:SI
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(set_attr "type" "muls")]
)
-;; Unnamed templates to match MLA instruction.
-
-(define_insn "*mulsi3addsi"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
- (plus:SI
- (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
- (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
- (match_operand:SI 3 "s_register_operand" "r,r,0,0")))]
- "TARGET_32BIT && !arm_arch6"
- "mla%?\\t%0, %2, %1, %3"
- [(set_attr "type" "mla")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*mulsi3addsi_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (plus:SI
- (mult:SI (match_operand:SI 2 "s_register_operand" "r")
- (match_operand:SI 1 "s_register_operand" "r"))
- (match_operand:SI 3 "s_register_operand" "r")))]
- "TARGET_32BIT && arm_arch6"
- "mla%?\\t%0, %2, %1, %3"
- [(set_attr "type" "mla")
- (set_attr "predicable" "yes")]
-)
-
(define_insn "*mulsi3addsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
(match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
)
(define_insn "*mulsi3addsi_compare0_v6"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 1 "s_register_operand" "r"))
)
(define_insn "*mulsi3addsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
(match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
)
(define_insn "*mulsi3addsi_compare0_scratch_v6"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 1 "s_register_operand" "r"))
(set_attr "type" "mlas")]
)
-(define_insn "*mulsi3subsi"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (minus:SI
- (match_operand:SI 3 "s_register_operand" "r")
- (mult:SI (match_operand:SI 2 "s_register_operand" "r")
- (match_operand:SI 1 "s_register_operand" "r"))))]
- "TARGET_32BIT && arm_arch_thumb2"
- "mls%?\\t%0, %2, %1, %3"
- [(set_attr "type" "mla")
- (set_attr "predicable" "yes")]
-)
-
-(define_expand "maddsidi4"
- [(set (match_operand:DI 0 "s_register_operand")
- (plus:DI
- (mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
- (match_operand:DI 3 "s_register_operand")))]
- "TARGET_32BIT"
- "")
-
-(define_insn "*mulsidi3adddi"
- [(set (match_operand:DI 0 "s_register_operand" "=&r")
- (plus:DI
- (mult:DI
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
- (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
- (match_operand:DI 1 "s_register_operand" "0")))]
- "TARGET_32BIT && !arm_arch6"
- "smlal%?\\t%Q0, %R0, %3, %2"
- [(set_attr "type" "smlal")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*mulsidi3adddi_v6"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (plus:DI
- (mult:DI
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))
- (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
- (match_operand:DI 1 "s_register_operand" "0")))]
- "TARGET_32BIT && arm_arch6"
- "smlal%?\\t%Q0, %R0, %3, %2"
- [(set_attr "type" "smlal")
- (set_attr "predicable" "yes")]
-)
-
;; 32x32->64 widening multiply.
-;; As with mulsi3, the only difference between the v3-5 and v6+
-;; versions of these patterns is the requirement that the output not
-;; overlap the inputs, but that still means we have to have a named
-;; expander and two different starred insns.
+;; The only difference between the v3-5 and v6+ versions is the requirement
+;; that the output does not overlap with either input.
-(define_expand "mulsidi3"
+(define_expand "<Us>mulsidi3"
[(set (match_operand:DI 0 "s_register_operand")
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand"))))]
+ (SE:DI (match_operand:SI 1 "s_register_operand"))
+ (SE:DI (match_operand:SI 2 "s_register_operand"))))]
"TARGET_32BIT"
- ""
-)
-
-(define_insn "*mulsidi3_nov6"
- [(set (match_operand:DI 0 "s_register_operand" "=&r")
- (mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
- "TARGET_32BIT && !arm_arch6"
- "smull%?\\t%Q0, %R0, %1, %2"
- [(set_attr "type" "smull")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*mulsidi3_v6"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
- "TARGET_32BIT && arm_arch6"
- "smull%?\\t%Q0, %R0, %1, %2"
- [(set_attr "type" "smull")
- (set_attr "predicable" "yes")]
+ {
+ emit_insn (gen_<US>mull (gen_lowpart (SImode, operands[0]),
+ gen_highpart (SImode, operands[0]),
+ operands[1], operands[2]));
+ DONE;
+ }
)
-(define_expand "umulsidi3"
- [(set (match_operand:DI 0 "s_register_operand")
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand"))))]
+(define_insn "<US>mull"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
+ (mult:SI
+ (match_operand:SI 2 "s_register_operand" "%r,r")
+ (match_operand:SI 3 "s_register_operand" "r,r")))
+ (set (match_operand:SI 1 "s_register_operand" "=r,&r")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI (SE:DI (match_dup 2)) (SE:DI (match_dup 3)))
+ (const_int 32))))]
"TARGET_32BIT"
- ""
-)
-
-(define_insn "*umulsidi3_nov6"
- [(set (match_operand:DI 0 "s_register_operand" "=&r")
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
- "TARGET_32BIT && !arm_arch6"
- "umull%?\\t%Q0, %R0, %1, %2"
+ "<US>mull%?\\t%0, %1, %2, %3"
[(set_attr "type" "umull")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*umulsidi3_v6"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
- "TARGET_32BIT && arm_arch6"
- "umull%?\\t%Q0, %R0, %1, %2"
- [(set_attr "type" "umull")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "arch" "v6,nov6")]
)
-(define_expand "umaddsidi4"
+(define_expand "<Us>maddsidi4"
[(set (match_operand:DI 0 "s_register_operand")
(plus:DI
(mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
+ (SE:DI (match_operand:SI 1 "s_register_operand"))
+ (SE:DI (match_operand:SI 2 "s_register_operand")))
(match_operand:DI 3 "s_register_operand")))]
"TARGET_32BIT"
- "")
-
-(define_insn "*umulsidi3adddi"
- [(set (match_operand:DI 0 "s_register_operand" "=&r")
- (plus:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
- (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
- (match_operand:DI 1 "s_register_operand" "0")))]
- "TARGET_32BIT && !arm_arch6"
- "umlal%?\\t%Q0, %R0, %3, %2"
- [(set_attr "type" "umlal")
- (set_attr "predicable" "yes")]
+ {
+ emit_insn (gen_<US>mlal (gen_lowpart (SImode, operands[0]),
+ gen_lowpart (SImode, operands[3]),
+ gen_highpart (SImode, operands[0]),
+ gen_highpart (SImode, operands[3]),
+ operands[1], operands[2]));
+ DONE;
+ }
)
-(define_insn "*umulsidi3adddi_v6"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (plus:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))
- (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
- (match_operand:DI 1 "s_register_operand" "0")))]
- "TARGET_32BIT && arm_arch6"
- "umlal%?\\t%Q0, %R0, %3, %2"
+(define_insn "<US>mlal"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
+ (plus:SI
+ (mult:SI
+ (match_operand:SI 4 "s_register_operand" "%r,r")
+ (match_operand:SI 5 "s_register_operand" "r,r"))
+ (match_operand:SI 1 "s_register_operand" "0,0")))
+ (set (match_operand:SI 2 "s_register_operand" "=r,&r")
+ (plus:SI
+ (truncate:SI
+ (lshiftrt:DI
+ (plus:DI
+ (mult:DI (SE:DI (match_dup 4)) (SE:DI (match_dup 5)))
+ (zero_extend:DI (match_dup 1)))
+ (const_int 32)))
+ (match_operand:SI 3 "s_register_operand" "2,2")))]
+ "TARGET_32BIT"
+ "<US>mlal%?\\t%0, %2, %4, %5"
[(set_attr "type" "umlal")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "arch" "v6,nov6")]
)
-(define_expand "smulsi3_highpart"
+(define_expand "<US>mulsi3_highpart"
[(parallel
[(set (match_operand:SI 0 "s_register_operand")
(truncate:SI
(lshiftrt:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
+ (SE:DI (match_operand:SI 1 "s_register_operand"))
+ (SE:DI (match_operand:SI 2 "s_register_operand")))
(const_int 32))))
(clobber (match_scratch:SI 3 ""))])]
"TARGET_32BIT"
""
)
-(define_insn "*smulsi3_highpart_nov6"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- "TARGET_32BIT && !arm_arch6"
- "smull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "smull")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*smulsi3_highpart_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+(define_insn "*<US>mull_high"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r")
(truncate:SI
(lshiftrt:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
+ (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r"))
+ (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r")))
(const_int 32))))
- (clobber (match_scratch:SI 3 "=r"))]
- "TARGET_32BIT && arm_arch6"
- "smull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "smull")
- (set_attr "predicable" "yes")]
-)
-
-(define_expand "umulsi3_highpart"
- [(parallel
- [(set (match_operand:SI 0 "s_register_operand")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 ""))])]
+ (clobber (match_scratch:SI 3 "=r,&r,&r"))]
"TARGET_32BIT"
- ""
-)
-
-(define_insn "*umulsi3_highpart_nov6"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- "TARGET_32BIT && !arm_arch6"
- "umull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "umull")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*umulsi3_highpart_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=r"))]
- "TARGET_32BIT && arm_arch6"
- "umull%?\\t%3, %0, %2, %1"
+ "<US>mull%?\\t%3, %0, %2, %1"
[(set_attr "type" "umull")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "arch" "v6,nov6,nov6")]
)
(define_insn "mulhisi3"
(set_attr "predicable" "yes")]
)
-(define_insn "maddhisi4"
+(define_expand "maddhisi4"
+ [(set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "s_register_operand"))
+ (sign_extend:SI
+ (match_operand:HI 2 "s_register_operand")))
+ (match_operand:SI 3 "s_register_operand")))]
+ "TARGET_DSP_MULTIPLY"
+ {
+ /* If this function reads the Q bit from ACLE intrinsics break up the
+ multiplication and accumulation as an overflow during accumulation will
+ clobber the Q flag. */
+ if (ARM_Q_BIT_READ)
+ {
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_insn (gen_mulhisi3 (tmp, operands[1], operands[2]));
+ emit_insn (gen_addsi3 (operands[0], tmp, operands[3]));
+ DONE;
+ }
+ }
+)
+
+(define_insn "*arm_maddhisi4"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (plus:SI (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "s_register_operand" "r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "s_register_operand" "r")))
+ (match_operand:SI 3 "s_register_operand" "r")))]
+ "TARGET_DSP_MULTIPLY && !ARM_Q_BIT_READ"
+ "smlabb%?\\t%0, %1, %2, %3"
+ [(set_attr "type" "smlaxy")
+ (set_attr "predicable" "yes")]
+)
+
+(define_insn "arm_smlabb_setq"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (mult:SI (sign_extend:SI
(match_operand:HI 1 "s_register_operand" "r"))
(sign_extend:SI
(match_operand:HI 2 "s_register_operand" "r")))
- (match_operand:SI 3 "s_register_operand" "r")))]
+ (match_operand:SI 3 "s_register_operand" "r")))
+ (set (reg:CC APSRQ_REGNUM)
+ (unspec:CC [(reg:CC APSRQ_REGNUM)] UNSPEC_Q_SET))]
"TARGET_DSP_MULTIPLY"
"smlabb%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")]
)
+(define_expand "arm_smlabb"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "s_register_operand")
+ (match_operand:SI 3 "s_register_operand")]
+ "TARGET_DSP_MULTIPLY"
+ {
+ rtx mult1 = gen_lowpart (HImode, operands[1]);
+ rtx mult2 = gen_lowpart (HImode, operands[2]);
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_arm_smlabb_setq (operands[0], mult1, mult2, operands[3]));
+ else
+ emit_insn (gen_maddhisi4 (operands[0], mult1, mult2, operands[3]));
+ DONE;
+ }
+)
+
;; Note: there is no maddhisi4ibt because this one is canonical form
-(define_insn "*maddhisi4tb"
+(define_insn "maddhisi4tb"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (mult:SI (ashiftrt:SI
(match_operand:SI 1 "s_register_operand" "r")
(sign_extend:SI
(match_operand:HI 2 "s_register_operand" "r")))
(match_operand:SI 3 "s_register_operand" "r")))]
+ "TARGET_DSP_MULTIPLY && !ARM_Q_BIT_READ"
+ "smlatb%?\\t%0, %1, %2, %3"
+ [(set_attr "type" "smlaxy")
+ (set_attr "predicable" "yes")]
+)
+
+(define_insn "arm_smlatb_setq"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "s_register_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 2 "s_register_operand" "r")))
+ (match_operand:SI 3 "s_register_operand" "r")))
+ (set (reg:CC APSRQ_REGNUM)
+ (unspec:CC [(reg:CC APSRQ_REGNUM)] UNSPEC_Q_SET))]
"TARGET_DSP_MULTIPLY"
"smlatb%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")]
)
-(define_insn "*maddhisi4tt"
+(define_expand "arm_smlatb"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "s_register_operand")
+ (match_operand:SI 3 "s_register_operand")]
+ "TARGET_DSP_MULTIPLY"
+ {
+ rtx mult2 = gen_lowpart (HImode, operands[2]);
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_arm_smlatb_setq (operands[0], operands[1],
+ mult2, operands[3]));
+ else
+ emit_insn (gen_maddhisi4tb (operands[0], operands[1],
+ mult2, operands[3]));
+ DONE;
+ }
+)
+
+(define_insn "maddhisi4tt"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (mult:SI (ashiftrt:SI
(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "s_register_operand" "r")
(const_int 16)))
(match_operand:SI 3 "s_register_operand" "r")))]
+ "TARGET_DSP_MULTIPLY && !ARM_Q_BIT_READ"
+ "smlatt%?\\t%0, %1, %2, %3"
+ [(set_attr "type" "smlaxy")
+ (set_attr "predicable" "yes")]
+)
+
+(define_insn "arm_smlatt_setq"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "s_register_operand" "r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "s_register_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 3 "s_register_operand" "r")))
+ (set (reg:CC APSRQ_REGNUM)
+ (unspec:CC [(reg:CC APSRQ_REGNUM)] UNSPEC_Q_SET))]
"TARGET_DSP_MULTIPLY"
"smlatt%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")]
)
+(define_expand "arm_smlatt"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "s_register_operand")
+ (match_operand:SI 3 "s_register_operand")]
+ "TARGET_DSP_MULTIPLY"
+ {
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_arm_smlatt_setq (operands[0], operands[1],
+ operands[2], operands[3]));
+ else
+ emit_insn (gen_maddhisi4tt (operands[0], operands[1],
+ operands[2], operands[3]));
+ DONE;
+ }
+)
+
(define_insn "maddhidi4"
[(set (match_operand:DI 0 "s_register_operand" "=r")
(plus:DI
[(set_attr "type" "smlalxy")
(set_attr "predicable" "yes")])
+(define_insn "arm_<smlaw_op><add_clobber_q_name>_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")
+ (match_operand:SI 3 "s_register_operand" "r")]
+ SMLAWBT))]
+ "TARGET_DSP_MULTIPLY && <add_clobber_q_pred>"
+ "<smlaw_op>%?\\t%0, %1, %2, %3"
+ [(set_attr "type" "smlaxy")
+ (set_attr "predicable" "yes")]
+)
+
+(define_expand "arm_<smlaw_op>"
+ [(set (match_operand:SI 0 "s_register_operand")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "s_register_operand")
+ (match_operand:SI 3 "s_register_operand")]
+ SMLAWBT))]
+ "TARGET_DSP_MULTIPLY"
+ {
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_arm_<smlaw_op>_setq_insn (operands[0], operands[1],
+ operands[2], operands[3]));
+ else
+ emit_insn (gen_arm_<smlaw_op>_insn (operands[0], operands[1],
+ operands[2], operands[3]));
+ DONE;
+ }
+)
+
(define_expand "mulsf3"
[(set (match_operand:SF 0 "s_register_operand")
(mult:SF (match_operand:SF 1 "s_register_operand")
"")
\f
+; Expand logical operations. The mid-end expander does not split off memory
+; operands or complex immediates, which leads to fewer LDRD/STRD instructions.
+; So an explicit expander is needed to generate better code.
+
+(define_expand "<LOGICAL:optab>di3"
+ [(set (match_operand:DI 0 "s_register_operand")
+ (LOGICAL:DI (match_operand:DI 1 "s_register_operand")
+ (match_operand:DI 2 "arm_<optab>di_operand")))]
+ "TARGET_32BIT"
+ {
+ rtx low = simplify_gen_binary (<CODE>, SImode,
+ gen_lowpart (SImode, operands[1]),
+ gen_lowpart (SImode, operands[2]));
+ rtx high = simplify_gen_binary (<CODE>, SImode,
+ gen_highpart (SImode, operands[1]),
+ gen_highpart_mode (SImode, DImode,
+ operands[2]));
+
+ emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0]), low));
+ emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]), high));
+ DONE;
+ }
+)
+
+(define_expand "one_cmpldi2"
+ [(set (match_operand:DI 0 "s_register_operand")
+ (not:DI (match_operand:DI 1 "s_register_operand")))]
+ "TARGET_32BIT"
+ {
+ rtx low = simplify_gen_unary (NOT, SImode,
+ gen_lowpart (SImode, operands[1]),
+ SImode);
+ rtx high = simplify_gen_unary (NOT, SImode,
+ gen_highpart_mode (SImode, DImode,
+ operands[1]),
+ SImode);
+
+ emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0]), low));
+ emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]), high));
+ DONE;
+ }
+)
+
;; Split DImode and, ior, xor operations. Simply perform the logical
;; operation on the upper and lower halves of the registers.
;; This is needed for atomic operations in arm_split_atomic_op.
)
(define_insn "*andsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operand:SI 2 "arm_not_operand" "I,K,r"))
(const_int 0)))
)
(define_insn "*andsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (match_operand:SI 0 "s_register_operand" "r,r,r")
(match_operand:SI 1 "arm_not_operand" "I,K,r"))
(const_int 0)))
)
(define_insn "*zeroextractsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (zero_extract:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (zero_extract:SI
(match_operand:SI 0 "s_register_operand" "r")
(match_operand 1 "const_int_operand" "n")
(match_operand 2 "const_int_operand" "n"))
&& INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
&& INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
- (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
(match_dup 0) (const_int 1)))]
"
operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
"TARGET_ARM"
"#"
"TARGET_ARM"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
- (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
(match_dup 0) (const_int 1)))]
"
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
&& INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
&& INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)
&& !reg_overlap_mentioned_p (operands[0], operands[4])"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
- (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
(match_dup 0) (match_dup 4)))]
"
operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
"TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
"#"
"TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
- (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
(match_dup 0) (match_dup 3)))]
"
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
)
(define_insn "andsi_not_shiftsi_si"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(and:SI (not:SI (match_operator:SI 4 "shift_operator"
- [(match_operand:SI 2 "s_register_operand" "r")
- (match_operand:SI 3 "arm_rhs_operand" "rM")]))
- (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_ARM"
+ [(match_operand:SI 2 "s_register_operand" "r,r")
+ (match_operand:SI 3 "shift_amount_operand" "M,r")]))
+ (match_operand:SI 1 "s_register_operand" "r,r")))]
+ "TARGET_32BIT"
"bic%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
- (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "logic_shift_imm")
- (const_string "logic_shift_reg")))]
+ (set_attr "arch" "32,a")
+ (set_attr "type" "logic_shift_imm,logic_shift_reg")]
)
;; Shifted bics pattern used to set up CC status register and not reusing
;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2
;; does not support shift by register.
(define_insn "andsi_not_shiftsi_si_scc_no_reuse"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (not:SI (match_operator:SI 0 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "arm_rhs_operand" "rM")]))
- (match_operand:SI 3 "s_register_operand" "r"))
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "shift_amount_operand" "M,r")]))
+ (match_operand:SI 3 "s_register_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:SI 4 "=r"))]
- "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
+ (clobber (match_scratch:SI 4 "=r,r"))]
+ "TARGET_32BIT"
"bics%?\\t%4, %3, %1%S0"
[(set_attr "predicable" "yes")
+ (set_attr "arch" "32,a")
(set_attr "conds" "set")
(set_attr "shift" "1")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "logic_shift_imm")
- (const_string "logic_shift_reg")))]
+ (set_attr "type" "logic_shift_imm,logic_shift_reg")]
)
;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also
;; getting reused later.
(define_insn "andsi_not_shiftsi_si_scc"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (not:SI (match_operator:SI 0 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "arm_rhs_operand" "rM")]))
- (match_operand:SI 3 "s_register_operand" "r"))
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "shift_amount_operand" "M,r")]))
+ (match_operand:SI 3 "s_register_operand" "r,r"))
(const_int 0)))
- (set (match_operand:SI 4 "s_register_operand" "=r")
+ (set (match_operand:SI 4 "s_register_operand" "=r,r")
(and:SI (not:SI (match_op_dup 0
[(match_dup 1)
(match_dup 2)]))
(match_dup 3)))])]
- "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
+ "TARGET_32BIT"
"bics%?\\t%4, %3, %1%S0"
[(set_attr "predicable" "yes")
+ (set_attr "arch" "32,a")
(set_attr "conds" "set")
(set_attr "shift" "1")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "logic_shift_imm")
- (const_string "logic_shift_reg")))]
+ (set_attr "type" "logic_shift_imm,logic_shift_reg")]
)
(define_insn "*andsi_notsi_si_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
)
(define_insn "*andsi_notsi_si_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
)
(define_insn "*iorsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
(match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
(const_int 0)))
)
(define_insn "*iorsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
(match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
(const_int 0)))
)
(define_insn "*xorsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r")
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (xor:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "I,r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r")
)
(define_insn "*xorsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r")
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (xor:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_rhs_operand" "I,r"))
(const_int 0)))]
"TARGET_32BIT"
(set_attr "type" "multiple")]
)
+
+(define_expand "arm_<ss_op>"
+ [(set (match_operand:SI 0 "s_register_operand")
+ (SSPLUSMINUS:SI (match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "s_register_operand")))]
+ "TARGET_DSP_MULTIPLY"
+ {
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_arm_<ss_op>_setq_insn (operands[0],
+ operands[1], operands[2]));
+ else
+ emit_insn (gen_arm_<ss_op>_insn (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+)
+
+(define_insn "arm_<ss_op><add_clobber_q_name>_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (SSPLUSMINUS:SI (match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")))]
+ "TARGET_DSP_MULTIPLY && <add_clobber_q_pred>"
+ "<ss_op>%?\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_dsp_reg")]
+)
+
(define_code_iterator SAT [smin smax])
(define_code_attr SATrev [(smin "smax") (smax "smin")])
(define_code_attr SATlo [(smin "1") (smax "2")])
(define_code_attr SAThi [(smin "2") (smax "1")])
-(define_insn "*satsi_<SAT:code>"
+(define_expand "arm_ssat"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "const_int_operand")]
+ "TARGET_32BIT && arm_arch6"
+ {
+ HOST_WIDE_INT val = INTVAL (operands[2]);
+ /* The builtin checking code should have ensured the right
+ range for the immediate. */
+ gcc_assert (IN_RANGE (val, 1, 32));
+ HOST_WIDE_INT upper_bound = (HOST_WIDE_INT_1 << (val - 1)) - 1;
+ HOST_WIDE_INT lower_bound = -upper_bound - 1;
+ rtx up_rtx = gen_int_mode (upper_bound, SImode);
+ rtx lo_rtx = gen_int_mode (lower_bound, SImode);
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_satsi_smin_setq (operands[0], lo_rtx,
+ up_rtx, operands[1]));
+ else
+ emit_insn (gen_satsi_smin (operands[0], lo_rtx, up_rtx, operands[1]));
+ DONE;
+ }
+)
+
+(define_expand "arm_usat"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "const_int_operand")]
+ "TARGET_32BIT && arm_arch6"
+ {
+ HOST_WIDE_INT val = INTVAL (operands[2]);
+ /* The builtin checking code should have ensured the right
+ range for the immediate. */
+ gcc_assert (IN_RANGE (val, 0, 31));
+ HOST_WIDE_INT upper_bound = (HOST_WIDE_INT_1 << val) - 1;
+ rtx up_rtx = gen_int_mode (upper_bound, SImode);
+ rtx lo_rtx = CONST0_RTX (SImode);
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_satsi_smin_setq (operands[0], lo_rtx, up_rtx,
+ operands[1]));
+ else
+ emit_insn (gen_satsi_smin (operands[0], lo_rtx, up_rtx, operands[1]));
+ DONE;
+ }
+)
+
+(define_insn "arm_get_apsr"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI [(reg:CC APSRQ_REGNUM)] UNSPEC_APSR_READ))]
+ "TARGET_ARM_QBIT"
+ "mrs%?\t%0, APSR"
+ [(set_attr "predicable" "yes")
+ (set_attr "conds" "use")]
+)
+
+(define_insn "arm_set_apsr"
+ [(set (reg:CC APSRQ_REGNUM)
+ (unspec_volatile:CC
+ [(match_operand:SI 0 "s_register_operand" "r")] VUNSPEC_APSR_WRITE))]
+ "TARGET_ARM_QBIT"
+ "msr%?\tAPSR_nzcvq, %0"
+ [(set_attr "predicable" "yes")
+ (set_attr "conds" "set")]
+)
+
+;; Read the APSR and extract the Q bit (bit 27)
+(define_expand "arm_saturation_occurred"
+ [(match_operand:SI 0 "s_register_operand")]
+ "TARGET_ARM_QBIT"
+ {
+ rtx apsr = gen_reg_rtx (SImode);
+ emit_insn (gen_arm_get_apsr (apsr));
+ emit_insn (gen_extzv (operands[0], apsr, CONST1_RTX (SImode),
+ gen_int_mode (27, SImode)));
+ DONE;
+ }
+)
+
+;; Read the APSR and set the Q bit (bit position 27) according to operand 0
+(define_expand "arm_set_saturation"
+ [(match_operand:SI 0 "reg_or_int_operand")]
+ "TARGET_ARM_QBIT"
+ {
+ rtx apsr = gen_reg_rtx (SImode);
+ emit_insn (gen_arm_get_apsr (apsr));
+ rtx to_insert = gen_reg_rtx (SImode);
+ if (CONST_INT_P (operands[0]))
+ emit_move_insn (to_insert, operands[0] == CONST0_RTX (SImode)
+ ? CONST0_RTX (SImode) : CONST1_RTX (SImode));
+ else
+ {
+ rtx cmp = gen_rtx_NE (SImode, operands[0], CONST0_RTX (SImode));
+ emit_insn (gen_cstoresi4 (to_insert, cmp, operands[0],
+ CONST0_RTX (SImode)));
+ }
+ emit_insn (gen_insv (apsr, CONST1_RTX (SImode),
+ gen_int_mode (27, SImode), to_insert));
+ emit_insn (gen_arm_set_apsr (apsr));
+ DONE;
+ }
+)
+
+(define_insn "satsi_<SAT:code><add_clobber_q_name>"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(SAT:SI (<SATrev>:SI (match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 1 "const_int_operand" "i"))
(match_operand:SI 2 "const_int_operand" "i")))]
- "TARGET_32BIT && arm_arch6
+ "TARGET_32BIT && arm_arch6 && <add_clobber_q_pred>
&& arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
{
int mask;
(match_operand:SI 5 "const_int_operand" "i")])
(match_operand:SI 1 "const_int_operand" "i"))
(match_operand:SI 2 "const_int_operand" "i")))]
- "TARGET_32BIT && arm_arch6
+ "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ
&& arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
{
int mask;
)
(define_insn "*shiftsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
)
(define_insn "*shiftsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
- (match_operand:SI 2 "shift_amount_operand" "M,rM")])))]
+ (match_operand:SI 2 "shift_amount_operand" "M,r")])))]
"TARGET_32BIT"
"mvn%?\\t%0, %1%S3"
[(set_attr "predicable" "yes")
(set_attr "type" "mvn_shift,mvn_shift_reg")])
(define_insn "*not_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
- (match_operand:SI 2 "shift_amount_operand" "M,rM")]))
+ (match_operand:SI 2 "shift_amount_operand" "M,r")]))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r")
(not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
(set_attr "type" "mvn_shift,mvn_shift_reg")])
(define_insn "*not_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
- (match_operand:SI 2 "shift_amount_operand" "M,rM")]))
+ (match_operand:SI 2 "shift_amount_operand" "M,r")]))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r,r"))]
"TARGET_32BIT"
; ARMv6+ unaligned load/store instructions (used for packed structure accesses).
+(define_insn "unaligned_loaddi"
+ [(set (match_operand:DI 0 "s_register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "memory_operand" "m")]
+ UNSPEC_UNALIGNED_LOAD))]
+ "TARGET_32BIT && TARGET_LDRD"
+ "*
+ return output_move_double (operands, true, NULL);
+ "
+ [(set_attr "length" "8")
+ (set_attr "type" "load_8")])
+
(define_insn "unaligned_loadsi"
[(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
(unspec:SI [(match_operand:SI 1 "memory_operand" "m,Uw,m")]
(set_attr "predicable_short_it" "no,yes,no")
(set_attr "type" "load_byte")])
+(define_insn "unaligned_storedi"
+ [(set (match_operand:DI 0 "memory_operand" "=m")
+ (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
+ UNSPEC_UNALIGNED_STORE))]
+ "TARGET_32BIT && TARGET_LDRD"
+ "*
+ return output_move_double (operands, true, NULL);
+ "
+ [(set_attr "length" "8")
+ (set_attr "type" "store_8")])
+
(define_insn "unaligned_storesi"
[(set (match_operand:SI 0 "memory_operand" "=m,Uw,m")
(unspec:SI [(match_operand:SI 1 "s_register_operand" "l,l,r")]
\f
;; Unary arithmetic insns
-(define_expand "negvsi3"
- [(match_operand:SI 0 "register_operand")
- (match_operand:SI 1 "register_operand")
+(define_expand "negv<SIDI:mode>3"
+ [(match_operand:SIDI 0 "s_register_operand")
+ (match_operand:SIDI 1 "s_register_operand")
(match_operand 2 "")]
"TARGET_32BIT"
{
- emit_insn (gen_subsi3_compare (operands[0], const0_rtx, operands[1]));
- arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
-
- DONE;
-})
-
-(define_expand "negvdi3"
- [(match_operand:DI 0 "register_operand")
- (match_operand:DI 1 "register_operand")
- (match_operand 2 "")]
- "TARGET_ARM"
-{
- emit_insn (gen_negdi2_compare (operands[0], operands[1]));
- arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
-
+ emit_insn (gen_subv<mode>4 (operands[0], const0_rtx, operands[1],
+ operands[2]));
DONE;
})
-
-(define_insn_and_split "negdi2_compare"
- [(set (reg:CC CC_REGNUM)
- (compare:CC
- (const_int 0)
- (match_operand:DI 1 "register_operand" "0,r")))
- (set (match_operand:DI 0 "register_operand" "=r,&r")
- (minus:DI (const_int 0) (match_dup 1)))]
- "TARGET_ARM"
- "#"
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (const_int 0) (match_dup 1)))
- (set (match_dup 0) (minus:SI (const_int 0)
- (match_dup 1)))])
- (parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (const_int 0) (match_dup 3)))
- (set (match_dup 2)
- (minus:SI
- (minus:SI (const_int 0) (match_dup 3))
- (ltu:SI (reg:CC CC_REGNUM)
- (const_int 0))))])]
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[3] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- }
- [(set_attr "conds" "set")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
-
-(define_expand "negdi2"
- [(parallel
- [(set (match_operand:DI 0 "s_register_operand")
- (neg:DI (match_operand:DI 1 "s_register_operand")))
- (clobber (reg:CC CC_REGNUM))])]
- "TARGET_EITHER"
- {
- if (TARGET_NEON)
- {
- emit_insn (gen_negdi2_neon (operands[0], operands[1]));
- DONE;
- }
- }
-)
-
-;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
-;; The first alternative allows the common case of a *full* overlap.
-(define_insn_and_split "*negdi2_insn"
- [(set (match_operand:DI 0 "s_register_operand" "=r,&r")
- (neg:DI (match_operand:DI 1 "s_register_operand" "0,r")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT"
- "#" ; rsbs %Q0, %Q1, #0; rsc %R0, %R1, #0 (ARM)
- ; negs %Q0, %Q1 ; sbc %R0, %R1, %R1, lsl #1 (Thumb-2)
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (const_int 0) (match_dup 1)))
- (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
- (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[3] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- }
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
-
-(define_insn "*negsi2_carryin_compare"
- [(set (reg:CC CC_REGNUM)
- (compare:CC (const_int 0)
- (match_operand:SI 1 "s_register_operand" "r")))
- (set (match_operand:SI 0 "s_register_operand" "=r")
- (minus:SI (minus:SI (const_int 0)
- (match_dup 1))
- (match_operand:SI 2 "arm_borrow_operation" "")))]
- "TARGET_ARM"
- "rscs\\t%0, %1, #0"
- [(set_attr "conds" "set")
- (set_attr "type" "alus_imm")]
-)
-
(define_expand "negsi2"
[(set (match_operand:SI 0 "s_register_operand")
(neg:SI (match_operand:SI 1 "s_register_operand")))]
[(set (match_operand:SI 0 "s_register_operand" "=l,r")
(neg:SI (match_operand:SI 1 "s_register_operand" "l,r")))]
"TARGET_32BIT"
- "rsb%?\\t%0, %1, #0"
- [(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "yes,no")
- (set_attr "arch" "t2,*")
- (set_attr "length" "4")
- (set_attr "type" "alu_sreg")]
-)
-
-(define_expand "negsf2"
- [(set (match_operand:SF 0 "s_register_operand")
- (neg:SF (match_operand:SF 1 "s_register_operand")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT"
- ""
-)
-
-(define_expand "negdf2"
- [(set (match_operand:DF 0 "s_register_operand")
- (neg:DF (match_operand:DF 1 "s_register_operand")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
- "")
-
-(define_insn_and_split "*zextendsidi_negsi"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))]
- "TARGET_32BIT"
- "#"
- ""
- [(set (match_dup 2)
- (neg:SI (match_dup 1)))
- (set (match_dup 3)
- (const_int 0))]
- {
- operands[2] = gen_lowpart (SImode, operands[0]);
- operands[3] = gen_highpart (SImode, operands[0]);
- }
- [(set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
-
-;; Negate an extended 32-bit value.
-(define_insn_and_split "*negdi_extendsidi"
- [(set (match_operand:DI 0 "s_register_operand" "=l,r")
- (neg:DI (sign_extend:DI
- (match_operand:SI 1 "s_register_operand" "l,r"))))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT"
- "#"
- "&& reload_completed"
- [(const_int 0)]
- {
- rtx low = gen_lowpart (SImode, operands[0]);
- rtx high = gen_highpart (SImode, operands[0]);
-
- if (reg_overlap_mentioned_p (low, operands[1]))
- {
- /* Input overlaps the low word of the output. Use:
- asr Rhi, Rin, #31
- rsbs Rlo, Rin, #0
- rsc Rhi, Rhi, #0 (thumb2: sbc Rhi, Rhi, Rhi, lsl #1). */
- rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
-
- emit_insn (gen_rtx_SET (high,
- gen_rtx_ASHIFTRT (SImode, operands[1],
- GEN_INT (31))));
-
- emit_insn (gen_subsi3_compare (low, const0_rtx, operands[1]));
- if (TARGET_ARM)
- emit_insn (gen_rtx_SET (high,
- gen_rtx_MINUS (SImode,
- gen_rtx_MINUS (SImode,
- const0_rtx,
- high),
- gen_rtx_LTU (SImode,
- cc_reg,
- const0_rtx))));
- else
- {
- rtx two_x = gen_rtx_ASHIFT (SImode, high, GEN_INT (1));
- emit_insn (gen_rtx_SET (high,
- gen_rtx_MINUS (SImode,
- gen_rtx_MINUS (SImode,
- high,
- two_x),
- gen_rtx_LTU (SImode,
- cc_reg,
- const0_rtx))));
- }
- }
- else
- {
- /* No overlap, or overlap on high word. Use:
- rsb Rlo, Rin, #0
- bic Rhi, Rlo, Rin
- asr Rhi, Rhi, #31
- Flags not needed for this sequence. */
- emit_insn (gen_rtx_SET (low, gen_rtx_NEG (SImode, operands[1])));
- emit_insn (gen_rtx_SET (high,
- gen_rtx_AND (SImode,
- gen_rtx_NOT (SImode, operands[1]),
- low)));
- emit_insn (gen_rtx_SET (high,
- gen_rtx_ASHIFTRT (SImode, high,
- GEN_INT (31))));
- }
- DONE;
- }
- [(set_attr "length" "12")
+ "rsb%?\\t%0, %1, #0"
+ [(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "yes,no")
(set_attr "arch" "t2,*")
- (set_attr "type" "multiple")]
+ (set_attr "length" "4")
+ (set_attr "type" "alu_imm")]
+)
+
+;; To keep the comparison in canonical form we express it as (~reg cmp ~0)
+;; rather than (0 cmp reg). This gives the same results for unsigned
+;; and equality compares which is what we mostly need here.
+(define_insn "negsi2_0compare"
+ [(set (reg:CC_RSB CC_REGNUM)
+ (compare:CC_RSB (not:SI (match_operand:SI 1 "s_register_operand" "l,r"))
+ (const_int -1)))
+ (set (match_operand:SI 0 "s_register_operand" "=l,r")
+ (neg:SI (match_dup 1)))]
+ "TARGET_32BIT"
+ "@
+ negs\\t%0, %1
+ rsbs\\t%0, %1, #0"
+ [(set_attr "conds" "set")
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,*")
+ (set_attr "type" "alus_imm")]
)
-(define_insn_and_split "*negdi_zero_extendsidi"
- [(set (match_operand:DI 0 "s_register_operand" "=r,&r")
- (neg:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r"))))
- (clobber (reg:CC CC_REGNUM))]
+(define_insn "negsi2_carryin"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (minus:SI (neg:SI (match_operand:SI 1 "s_register_operand" "r,r"))
+ (match_operand:SI 2 "arm_borrow_operation" "")))]
"TARGET_32BIT"
- "#" ; "rsbs\\t%Q0, %1, #0\;sbc\\t%R0,%R0,%R0"
- ;; Don't care what register is input to sbc,
- ;; since we just need to propagate the carry.
- "&& reload_completed"
- [(parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (const_int 0) (match_dup 1)))
- (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
- (set (match_dup 2) (minus:SI (minus:SI (match_dup 2) (match_dup 2))
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))]
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- }
- [(set_attr "conds" "clob")
- (set_attr "length" "8")
- (set_attr "type" "multiple")] ;; length in thumb is 4
+ "@
+ rsc\\t%0, %1, #0
+ sbc\\t%0, %1, %1, lsl #1"
+ [(set_attr "conds" "use")
+ (set_attr "arch" "a,t2")
+ (set_attr "type" "adc_imm,adc_reg")]
+)
+
+(define_expand "negsf2"
+ [(set (match_operand:SF 0 "s_register_operand")
+ (neg:SF (match_operand:SF 1 "s_register_operand")))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
+ ""
)
+(define_expand "negdf2"
+ [(set (match_operand:DF 0 "s_register_operand")
+ (neg:DF (match_operand:DF 1 "s_register_operand")))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
+ "")
+
;; abssi2 doesn't really clobber the condition codes if a different register
;; is being set. To keep things simple, assume during rtl manipulations that
;; it does, but tell the final scan operator the truth. Similarly for
)
(define_insn "*notsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
(not:SI (match_dup 1)))]
)
(define_insn "*notsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"TARGET_32BIT"
\f
;; Zero and sign extension instructions.
-(define_insn "zero_extend<mode>di2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,?r")
- (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
- "<qhs_zextenddi_cstr>")))]
+(define_expand "zero_extend<mode>di2"
+ [(set (match_operand:DI 0 "s_register_operand" "")
+ (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>" "")))]
"TARGET_32BIT <qhs_zextenddi_cond>"
- "#"
- [(set_attr "length" "4,8")
- (set_attr "arch" "*,*")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "mov_reg,multiple")]
+ {
+ rtx res_lo, res_hi, op0_lo, op0_hi;
+ res_lo = gen_lowpart (SImode, operands[0]);
+ res_hi = gen_highpart (SImode, operands[0]);
+ if (can_create_pseudo_p ())
+ {
+ op0_lo = <MODE>mode == SImode ? operands[1] : gen_reg_rtx (SImode);
+ op0_hi = gen_reg_rtx (SImode);
+ }
+ else
+ {
+ op0_lo = <MODE>mode == SImode ? operands[1] : res_lo;
+ op0_hi = res_hi;
+ }
+ if (<MODE>mode != SImode)
+ emit_insn (gen_rtx_SET (op0_lo,
+ gen_rtx_ZERO_EXTEND (SImode, operands[1])));
+ emit_insn (gen_movsi (op0_hi, const0_rtx));
+ if (res_lo != op0_lo)
+ emit_move_insn (res_lo, op0_lo);
+ if (res_hi != op0_hi)
+ emit_move_insn (res_hi, op0_hi);
+ DONE;
+ }
)
-(define_insn "extend<mode>di2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,?r,?r")
- (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
- "<qhs_extenddi_cstr>")))]
+(define_expand "extend<mode>di2"
+ [(set (match_operand:DI 0 "s_register_operand" "")
+ (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>" "")))]
"TARGET_32BIT <qhs_sextenddi_cond>"
- "#"
- [(set_attr "length" "4,8,8")
- (set_attr "ce_count" "2")
- (set_attr "shift" "1")
- (set_attr "predicable" "yes")
- (set_attr "arch" "*,a,t")
- (set_attr "type" "mov_reg,multiple,multiple")]
+ {
+ rtx res_lo, res_hi, op0_lo, op0_hi;
+ res_lo = gen_lowpart (SImode, operands[0]);
+ res_hi = gen_highpart (SImode, operands[0]);
+ if (can_create_pseudo_p ())
+ {
+ op0_lo = <MODE>mode == SImode ? operands[1] : gen_reg_rtx (SImode);
+ op0_hi = gen_reg_rtx (SImode);
+ }
+ else
+ {
+ op0_lo = <MODE>mode == SImode ? operands[1] : res_lo;
+ op0_hi = res_hi;
+ }
+ if (<MODE>mode != SImode)
+ emit_insn (gen_rtx_SET (op0_lo,
+ gen_rtx_SIGN_EXTEND (SImode, operands[1])));
+ emit_insn (gen_ashrsi3 (op0_hi, op0_lo, GEN_INT (31)));
+ if (res_lo != op0_lo)
+ emit_move_insn (res_lo, op0_lo);
+ if (res_hi != op0_hi)
+ emit_move_insn (res_hi, op0_hi);
+ DONE;
+ }
)
;; Splits for all extensions to DImode
(define_split
[(set (match_operand:DI 0 "s_register_operand" "")
(zero_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
- "TARGET_32BIT && reload_completed && !IS_VFP_REGNUM (REGNO (operands[0]))"
+ "TARGET_32BIT"
[(set (match_dup 0) (match_dup 1))]
{
rtx lo_part = gen_lowpart (SImode, operands[0]);
machine_mode src_mode = GET_MODE (operands[1]);
- if (REG_P (operands[0])
- && !reg_overlap_mentioned_p (operands[0], operands[1]))
- emit_clobber (operands[0]);
- if (!REG_P (lo_part) || src_mode != SImode
- || !rtx_equal_p (lo_part, operands[1]))
- {
- if (src_mode == SImode)
- emit_move_insn (lo_part, operands[1]);
- else
- emit_insn (gen_rtx_SET (lo_part,
- gen_rtx_ZERO_EXTEND (SImode, operands[1])));
- operands[1] = lo_part;
- }
+ if (src_mode == SImode)
+ emit_move_insn (lo_part, operands[1]);
+ else
+ emit_insn (gen_rtx_SET (lo_part,
+ gen_rtx_ZERO_EXTEND (SImode, operands[1])));
operands[0] = gen_highpart (SImode, operands[0]);
operands[1] = const0_rtx;
})
(define_split
[(set (match_operand:DI 0 "s_register_operand" "")
(sign_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
- "TARGET_32BIT && reload_completed && !IS_VFP_REGNUM (REGNO (operands[0]))"
+ "TARGET_32BIT"
[(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
{
rtx lo_part = gen_lowpart (SImode, operands[0]);
machine_mode src_mode = GET_MODE (operands[1]);
- if (REG_P (operands[0])
- && !reg_overlap_mentioned_p (operands[0], operands[1]))
- emit_clobber (operands[0]);
-
- if (!REG_P (lo_part) || src_mode != SImode
- || !rtx_equal_p (lo_part, operands[1]))
- {
- if (src_mode == SImode)
- emit_move_insn (lo_part, operands[1]);
- else
- emit_insn (gen_rtx_SET (lo_part,
- gen_rtx_SIGN_EXTEND (SImode, operands[1])));
- operands[1] = lo_part;
- }
+ if (src_mode == SImode)
+ emit_move_insn (lo_part, operands[1]);
+ else
+ emit_insn (gen_rtx_SET (lo_part,
+ gen_rtx_SIGN_EXTEND (SImode, operands[1])));
+ operands[1] = lo_part;
operands[0] = gen_highpart (SImode, operands[0]);
})
(set_attr "predicable" "yes")]
)
+(define_insn "arm_<sup>xtb16"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")] USXTB16))]
+ "TARGET_INT_SIMD"
+ "<sup>xtb16%?\\t%0, %1"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_dsp_reg")])
+
+(define_insn "arm_<simd32_op>"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")] SIMD32_NOGE_BINOP))]
+ "TARGET_INT_SIMD"
+ "<simd32_op>%?\\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_dsp_reg")])
+
+(define_insn "arm_usada8"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")
+ (match_operand:SI 3 "s_register_operand" "r")] UNSPEC_USADA8))]
+ "TARGET_INT_SIMD"
+ "usada8%?\\t%0, %1, %2, %3"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_dsp_reg")])
+
+(define_insn "arm_<simd32_op>"
+ [(set (match_operand:DI 0 "s_register_operand" "=r")
+ (unspec:DI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")
+ (match_operand:DI 3 "s_register_operand" "0")] SIMD32_DIMODE))]
+ "TARGET_INT_SIMD"
+ "<simd32_op>%?\\t%Q0, %R0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "smlald")])
+
+(define_insn "arm_<simd32_op>"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")] SIMD32_GE))
+ (set (reg:CC APSRGE_REGNUM)
+ (unspec:CC [(reg:CC APSRGE_REGNUM)] UNSPEC_GE_SET))]
+ "TARGET_INT_SIMD"
+ "<simd32_op>%?\\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_sreg")])
+
+(define_insn "arm_<simd32_op><add_clobber_q_name>_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")
+ (match_operand:SI 3 "s_register_operand" "r")] SIMD32_TERNOP_Q))]
+ "TARGET_INT_SIMD && <add_clobber_q_pred>"
+ "<simd32_op>%?\\t%0, %1, %2, %3"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_sreg")])
+
+(define_expand "arm_<simd32_op>"
+ [(set (match_operand:SI 0 "s_register_operand")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "s_register_operand")
+ (match_operand:SI 3 "s_register_operand")] SIMD32_TERNOP_Q))]
+ "TARGET_INT_SIMD"
+ {
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_arm_<simd32_op>_setq_insn (operands[0], operands[1],
+ operands[2], operands[3]));
+ else
+ emit_insn (gen_arm_<simd32_op>_insn (operands[0], operands[1],
+ operands[2], operands[3]));
+ DONE;
+ }
+)
+
+(define_insn "arm_<simd32_op><add_clobber_q_name>_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")] SIMD32_BINOP_Q))]
+ "TARGET_INT_SIMD && <add_clobber_q_pred>"
+ "<simd32_op>%?\\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_sreg")])
+
+(define_expand "arm_<simd32_op>"
+ [(set (match_operand:SI 0 "s_register_operand")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "s_register_operand")] SIMD32_BINOP_Q))]
+ "TARGET_INT_SIMD"
+ {
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_arm_<simd32_op>_setq_insn (operands[0], operands[1],
+ operands[2]));
+ else
+ emit_insn (gen_arm_<simd32_op>_insn (operands[0], operands[1],
+ operands[2]));
+ DONE;
+ }
+)
+
+(define_insn "arm_<simd32_op><add_clobber_q_name>_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "<sup>sat16_imm" "i")] USSAT16))]
+ "TARGET_INT_SIMD && <add_clobber_q_pred>"
+ "<simd32_op>%?\\t%0, %2, %1"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_sreg")])
+
+(define_expand "arm_<simd32_op>"
+ [(set (match_operand:SI 0 "s_register_operand")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand")
+ (match_operand:SI 2 "<sup>sat16_imm")] USSAT16))]
+ "TARGET_INT_SIMD"
+ {
+ if (ARM_Q_BIT_READ)
+ emit_insn (gen_arm_<simd32_op>_setq_insn (operands[0], operands[1],
+ operands[2]));
+ else
+ emit_insn (gen_arm_<simd32_op>_insn (operands[0], operands[1],
+ operands[2]));
+ DONE;
+ }
+)
+
+(define_insn "arm_sel"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")
+ (reg:CC APSRGE_REGNUM)] UNSPEC_SEL))]
+ "TARGET_INT_SIMD"
+ "sel%?\\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "alu_sreg")])
+
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "s_register_operand")
(float_extend:DF (match_operand:SF 1 "s_register_operand")))]
(match_operand:DI 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (aligned_operand (operands[0], DImode));
+ gcc_checking_assert (aligned_operand (operands[1], DImode));
if (can_create_pseudo_p ())
{
if (!REG_P (operands[0]))
{
rtx base, offset, tmp;
+ gcc_checking_assert (aligned_operand (operands[0], SImode));
+ gcc_checking_assert (aligned_operand (operands[1], SImode));
if (TARGET_32BIT || TARGET_HAVE_MOVT)
{
/* Everything except mem = const or mem = mem can be done easily. */
(match_operand:HI 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (aligned_operand (operands[0], HImode));
+ gcc_checking_assert (aligned_operand (operands[1], HImode));
if (TARGET_ARM)
{
if (can_create_pseudo_p ())
(match_operand:HF 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (aligned_operand (operands[0], HFmode));
+ gcc_checking_assert (aligned_operand (operands[1], HFmode));
if (TARGET_32BIT)
{
if (MEM_P (operands[0]))
(match_operand:SF 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (aligned_operand (operands[0], SFmode));
+ gcc_checking_assert (aligned_operand (operands[1], SFmode));
if (TARGET_32BIT)
{
if (MEM_P (operands[0]))
(match_operand:DF 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (aligned_operand (operands[0], DFmode));
+ gcc_checking_assert (aligned_operand (operands[1], DFmode));
if (TARGET_32BIT)
{
if (MEM_P (operands[0]))
[(set (pc) (if_then_else
(match_operator 0 "expandable_comparison_operator"
[(match_operand:DI 1 "s_register_operand")
- (match_operand:DI 2 "cmpdi_operand")])
+ (match_operand:DI 2 "reg_or_int_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
"TARGET_32BIT"
(define_insn "*cmpsi_shiftsi"
[(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:SI 0 "s_register_operand" "r,r,r")
+ (compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r,r,r")
- (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))]
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "shift_amount_operand" "M,r")])))]
"TARGET_32BIT"
"cmp\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "arch" "32,a,a")
- (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
+ (set_attr "arch" "32,a")
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*cmpsi_shiftsi_swp"
[(set (reg:CC_SWP CC_REGNUM)
(compare:CC_SWP (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r,r,r")
- (match_operand:SI 2 "shift_amount_operand" "M,r,M")])
- (match_operand:SI 0 "s_register_operand" "r,r,r")))]
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "shift_amount_operand" "M,r")])
+ (match_operand:SI 0 "s_register_operand" "r,r")))]
"TARGET_32BIT"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "arch" "32,a,a")
- (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
+ (set_attr "arch" "32,a")
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*arm_cmpsi_negshiftsi_si"
[(set (reg:CC_Z CC_REGNUM)
(compare:CC_Z
(neg:SI (match_operator:SI 1 "shift_operator"
- [(match_operand:SI 2 "s_register_operand" "r")
- (match_operand:SI 3 "reg_or_int_operand" "rM")]))
- (match_operand:SI 0 "s_register_operand" "r")))]
- "TARGET_ARM"
+ [(match_operand:SI 2 "s_register_operand" "r,r")
+ (match_operand:SI 3 "shift_amount_operand" "M,r")]))
+ (match_operand:SI 0 "s_register_operand" "r,r")))]
+ "TARGET_32BIT"
"cmn%?\\t%0, %2%S1"
[(set_attr "conds" "set")
- (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alus_shift_imm")
- (const_string "alus_shift_reg")))
+ (set_attr "arch" "32,a")
+ (set_attr "shift" "2")
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")
(set_attr "predicable" "yes")]
)
-;; DImode comparisons. The generic code generates branches that
-;; if-conversion cannot reduce to a conditional compare, so we do
-;; that directly.
-
-(define_insn_and_split "*arm_cmpdi_insn"
- [(set (reg:CC_NCV CC_REGNUM)
- (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r")
- (match_operand:DI 1 "arm_di_operand" "rDi")))
- (clobber (match_scratch:SI 2 "=r"))]
- "TARGET_32BIT"
- "#" ; "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
- "&& reload_completed"
- [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 0) (match_dup 1)))
- (parallel [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 3) (match_dup 4)))
- (set (match_dup 2)
- (minus:SI (match_dup 5)
- (ltu:SI (reg:CC CC_REGNUM) (const_int 0))))])]
- {
- operands[3] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- if (CONST_INT_P (operands[1]))
- {
- operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);
- if (operands[4] == const0_rtx)
- operands[5] = operands[3];
- else
- operands[5] = gen_rtx_PLUS (SImode, operands[3],
- gen_int_mode (-UINTVAL (operands[4]),
- SImode));
- }
- else
- {
- operands[4] = gen_highpart (SImode, operands[1]);
- operands[5] = gen_rtx_MINUS (SImode, operands[3], operands[4]);
- }
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- }
- [(set_attr "conds" "set")
- (set_attr "length" "8")
- (set_attr "type" "multiple")]
-)
-
-(define_insn_and_split "*arm_cmpdi_unsigned"
- [(set (reg:CC_CZ CC_REGNUM)
- (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "l,r,r,r")
- (match_operand:DI 1 "arm_di_operand" "Py,r,Di,rDi")))]
-
- "TARGET_32BIT"
- "#" ; "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1"
- "&& reload_completed"
- [(set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 2) (match_dup 3)))
- (cond_exec (eq:SI (reg:CC CC_REGNUM) (const_int 0))
- (set (reg:CC CC_REGNUM)
- (compare:CC (match_dup 0) (match_dup 1))))]
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- if (CONST_INT_P (operands[1]))
- operands[3] = gen_highpart_mode (SImode, DImode, operands[1]);
- else
- operands[3] = gen_highpart (SImode, operands[1]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- }
- [(set_attr "conds" "set")
- (set_attr "enabled_for_short_it" "yes,yes,no,*")
- (set_attr "arch" "t2,t2,t2,a")
- (set_attr "length" "6,6,10,8")
- (set_attr "type" "multiple")]
-)
-
-(define_insn "*arm_cmpdi_zero"
- [(set (reg:CC_Z CC_REGNUM)
- (compare:CC_Z (match_operand:DI 0 "s_register_operand" "r")
- (const_int 0)))
- (clobber (match_scratch:SI 1 "=r"))]
- "TARGET_32BIT"
- "orrs%?\\t%1, %Q0, %R0"
- [(set_attr "conds" "set")
- (set_attr "type" "logics_reg")]
-)
-
; This insn allows redundant compares to be removed by cse, nothing should
; ever appear in the output file since (set (reg x) (reg x)) is a no-op that
; is deleted later on. The match_dup will match the mode here, so that
(set_attr "type" "multiple")]
)
+(define_insn "*negscc_borrow"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (neg:SI (match_operand:SI 1 "arm_borrow_operation" "")))]
+ "TARGET_32BIT"
+ "sbc\\t%0, %0, %0"
+ [(set_attr "conds" "use")
+ (set_attr "length" "4")
+ (set_attr "type" "adc_reg")]
+)
+
(define_insn_and_split "*mov_negscc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
[(match_operand 2 "cc_register" "") (const_int 0)])))]
- "TARGET_ARM"
+ "TARGET_ARM && !arm_borrow_operation (operands[1], SImode)"
"#" ; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
- "TARGET_ARM"
+ "&& true"
[(set (match_dup 0)
(if_then_else:SI (match_dup 1)
(match_dup 3)
[(set (match_operand:SI 0 "s_register_operand")
(match_operator:SI 1 "expandable_comparison_operator"
[(match_operand:DI 2 "s_register_operand")
- (match_operand:DI 3 "cmpdi_operand")]))]
+ (match_operand:DI 3 "reg_or_int_operand")]))]
"TARGET_32BIT"
"{
if (!arm_validize_comparison (&operands[1],
: !REG_P (callee))
XEXP (operands[0], 0) = force_reg (Pmode, callee);
+ if (TARGET_FDPIC && !SYMBOL_REF_P (XEXP (operands[0], 0)))
+ /* Indirect call: set r9 with FDPIC value of callee. */
+ XEXP (operands[0], 0)
+ = arm_load_function_descriptor (XEXP (operands[0], 0));
+
if (detect_cmse_nonsecure_call (addr))
{
pat = gen_nonsecure_call_internal (operands[0], operands[1],
pat = gen_call_internal (operands[0], operands[1], operands[2]);
arm_emit_call_insn (pat, XEXP (operands[0], 0), false);
}
+
+ /* Restore FDPIC register (r9) after call. */
+ if (TARGET_FDPIC)
+ {
+ rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
+ rtx initial_fdpic_reg
+ = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM);
+
+ emit_insn (gen_restore_pic_register_after_call (fdpic_reg,
+ initial_fdpic_reg));
+ }
+
DONE;
}"
)
+(define_insn "restore_pic_register_after_call"
+ [(set (match_operand:SI 0 "s_register_operand" "+r,r")
+ (unspec:SI [(match_dup 0)
+ (match_operand:SI 1 "nonimmediate_operand" "r,m")]
+ UNSPEC_PIC_RESTORE))]
+ ""
+ "@
+ mov\t%0, %1
+ ldr\t%0, %1"
+)
+
(define_expand "call_internal"
[(parallel [(call (match_operand 0 "memory_operand")
(match_operand 1 "general_operand"))
: !REG_P (callee))
XEXP (operands[1], 0) = force_reg (Pmode, callee);
+ if (TARGET_FDPIC && !SYMBOL_REF_P (XEXP (operands[1], 0)))
+ /* Indirect call: set r9 with FDPIC value of callee. */
+ XEXP (operands[1], 0)
+ = arm_load_function_descriptor (XEXP (operands[1], 0));
+
if (detect_cmse_nonsecure_call (addr))
{
pat = gen_nonsecure_call_value_internal (operands[0], operands[1],
operands[2], operands[3]);
arm_emit_call_insn (pat, XEXP (operands[1], 0), false);
}
+
+ /* Restore FDPIC register (r9) after call. */
+ if (TARGET_FDPIC)
+ {
+ rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
+ rtx initial_fdpic_reg
+ = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM);
+
+ emit_insn (gen_restore_pic_register_after_call (fdpic_reg,
+ initial_fdpic_reg));
+ }
+
DONE;
}"
)
(define_expand "return_addr_mask"
[(set (match_dup 1)
- (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+ (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand")
(if_then_else:SI (eq (match_dup 1) (const_int 0))
(const_int 67108860)))] ; 0x03fffffc
"TARGET_ARM"
"
- operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
+ operands[1] = gen_rtx_REG (CC_NZmode, CC_REGNUM);
")
(define_insn "*check_arch2"
- [(set (match_operand:CC_NOOV 0 "cc_register" "")
- (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+ [(set (match_operand:CC_NZ 0 "cc_register" "")
+ (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
(const_int 0)))]
"TARGET_ARM"
"teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
(const_int 0))
(match_operand 1 "" "")
(match_operand 2 "" "")])]
- "TARGET_EITHER"
+ "TARGET_EITHER && !TARGET_FDPIC"
"
{
int i;
(define_expand "untyped_return"
[(match_operand:BLK 0 "memory_operand")
(match_operand 1 "" "")]
- "TARGET_EITHER"
+ "TARGET_EITHER && !TARGET_FDPIC"
"
{
int i;
{
if (flag_pic)
{
+ rtx pic_reg;
+
+ if (TARGET_FDPIC)
+ pic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
+ else
+ pic_reg = operands[3];
+
/* Forces recomputing of GOT base now. */
- legitimize_pic_address (operands[1], SImode, operands[2], operands[3],
+ legitimize_pic_address (operands[1], SImode, operands[2], pic_reg,
true /*compute_now*/);
}
else
[(set_attr "arch" "t1,32")]
)
+;; DO NOT SPLIT THIS INSN. It's important for security reasons that the
+;; canary value does not live beyond the life of this sequence.
(define_insn "*stack_protect_set_insn"
[(set (match_operand:SI 0 "memory_operand" "=m,m")
(unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "+&l,&r"))]
(clobber (match_dup 1))]
""
"@
- ldr\\t%1, [%1]\;str\\t%1, %0\;movs\t%1,#0
- ldr\\t%1, [%1]\;str\\t%1, %0\;mov\t%1,#0"
+ ldr\\t%1, [%1]\;str\\t%1, %0\;movs\t%1, #0
+ ldr\\t%1, [%1]\;str\\t%1, %0\;mov\t%1, #0"
[(set_attr "length" "8,12")
(set_attr "conds" "clob,nocond")
(set_attr "type" "multiple")
if (flag_pic)
{
+ rtx pic_reg;
+
+ if (TARGET_FDPIC)
+ pic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
+ else
+ pic_reg = operands[4];
+
/* Forces recomputing of GOT base now. */
- legitimize_pic_address (operands[1], SImode, operands[3], operands[4],
+ legitimize_pic_address (operands[1], SImode, operands[3], pic_reg,
true /*compute_now*/);
}
else
"")
(define_insn "*arith_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r,r")
(set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*arith_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r,r")
(set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*sub_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
- (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r,r,r")
- (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r")]))
(const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
+ (set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (match_dup 1)
(match_op_dup 2 [(match_dup 3) (match_dup 4)])))]
"TARGET_32BIT"
"subs%?\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
- (set_attr "arch" "32,a,a")
- (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
+ (set_attr "arch" "32,a")
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*sub_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
- (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r,r,r")
- (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r")]))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=r,r,r"))]
+ (clobber (match_scratch:SI 0 "=r,r"))]
"TARGET_32BIT"
"subs%?\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
- (set_attr "arch" "32,a,a")
- (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
+ (set_attr "arch" "32,a")
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")])
\f
(define_insn_and_split "*and_scc"
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && reload_completed"
[(parallel
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2))
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (minus:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (cond_exec (ne:CC_NZ (reg:CC_NZ CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 1)))])
(define_insn_and_split "*compare_scc"
(compare
(and:SI
(match_operator 4 "arm_comparison_operator"
- [(match_operand:SI 0 "s_register_operand"
- "l,l,l,r,r,r,r,r,r")
- (match_operand:SI 1 "arm_add_operand"
- "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
+ [(match_operand:SI 0 "s_register_operand"
+ "l,l,l,r,r,r,r,r,r,r")
+ (match_operand:SI 1 "arm_add_operand"
+ "lPy,lPy,lPy,rI,L,r,rI,L,rI,L")])
(match_operator:SI 5 "arm_comparison_operator"
- [(match_operand:SI 2 "s_register_operand"
- "l,r,r,l,l,r,r,r,r")
- (match_operand:SI 3 "arm_add_operand"
- "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
+ [(match_operand:SI 2 "s_register_operand"
+ "l,r,r,l,l,r,r,r,r,r")
+ (match_operand:SI 3 "arm_add_operand"
+ "lPy,rI,L,lPy,lPy,r,rI,rI,L,L")]))
(const_int 0)))]
"TARGET_32BIT"
"*
\"it\\t%d5\",
\"it\\t%d4\"
};
- static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
- CMP_CMP, CMN_CMP, CMP_CMP,
- CMN_CMP, CMP_CMN, CMN_CMN};
+ static const int cmp_idx[] = {CMP_CMP, CMP_CMP, CMP_CMN,
+ CMP_CMP, CMN_CMP, CMP_CMP,
+ CMP_CMP, CMN_CMP, CMP_CMN,
+ CMN_CMN};
int swap =
comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
}"
[(set_attr "conds" "set")
(set_attr "predicable" "no")
- (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
- (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
+ (set_attr "arch" "t2,t2,t2,t2,t2,t2,any,any,any,any")
+ (set_attr "enabled_for_short_it" "yes,no,no,no,no,yes,no,no,no,no")
(set_attr_alternative "length"
[(const_int 6)
(const_int 8)
(const_int 8)
(const_int 8)
(const_int 8)
+ (const_int 6)
(if_then_else (eq_attr "is_thumb" "no")
(const_int 8)
(const_int 10))
(ior:SI
(match_operator 4 "arm_comparison_operator"
[(match_operand:SI 0 "s_register_operand"
- "l,l,l,r,r,r,r,r,r")
+ "l,l,l,r,r,r,r,r,r,r")
(match_operand:SI 1 "arm_add_operand"
- "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
+ "lPy,lPy,lPy,rI,L,r,rI,L,rI,L")])
(match_operator:SI 5 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand"
- "l,r,r,l,l,r,r,r,r")
+ "l,r,r,l,l,r,r,r,r,r")
(match_operand:SI 3 "arm_add_operand"
- "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
+ "lPy,rI,L,lPy,lPy,r,rI,rI,L,L")]))
(const_int 0)))]
"TARGET_32BIT"
"*
\"it\\t%D4\",
\"it\\t%D5\"
};
- static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
- CMP_CMP, CMN_CMP, CMP_CMP,
- CMN_CMP, CMP_CMN, CMN_CMN};
+ static const int cmp_idx[] = {CMP_CMP, CMP_CMP, CMP_CMN,
+ CMP_CMP, CMN_CMP, CMP_CMP,
+ CMP_CMP, CMN_CMP, CMP_CMN,
+ CMN_CMN};
int swap =
comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
}
"
[(set_attr "conds" "set")
- (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
- (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
+ (set_attr "arch" "t2,t2,t2,t2,t2,t2,any,any,any,any")
+ (set_attr "enabled_for_short_it" "yes,no,no,no,no,yes,no,no,no,no")
(set_attr_alternative "length"
[(const_int 6)
(const_int 8)
(const_int 8)
(const_int 8)
(const_int 8)
+ (const_int 6)
(if_then_else (eq_attr "is_thumb" "no")
(const_int 8)
(const_int 10))
)
(define_split
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (ior:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (ior:SI
(and:SI (match_operand:SI 0 "s_register_operand" "")
(const_int 1))
(match_operator:SI 1 "arm_comparison_operator"
[(set (match_dup 4)
(ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
(match_dup 0)))
- (set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
+ (set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (and:SI (match_dup 4) (const_int 1))
(const_int 0)))]
"")
(define_split
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (ior:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (ior:SI
(match_operator:SI 1 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand" "")
(match_operand:SI 3 "arm_add_operand" "")])
[(set (match_dup 4)
(ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
(match_dup 0)))
- (set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
+ (set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (and:SI (match_dup 4) (const_int 1))
(const_int 0)))]
"")
;; ??? The conditional patterns above need checking for Thumb-2 usefulness
"TARGET_32BIT"
"#"
"&& reload_completed"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (match_dup 3)
(match_dup 4))
(const_int 0)))
(set_attr "type" "mrs")]
)
+;; Doesn't clobber R1-R3. Must use r0 for the first operand.
+(define_insn "load_tp_soft_fdpic"
+ [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
+ (clobber (reg:SI FDPIC_REGNUM))
+ (clobber (reg:SI LR_REGNUM))
+ (clobber (reg:SI IP_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_SOFT_TP && TARGET_FDPIC"
+ "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
+ [(set_attr "conds" "clob")
+ (set_attr "type" "branch")]
+)
+
;; Doesn't clobber R1-R3. Must use r0 for the first operand.
(define_insn "load_tp_soft"
[(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
(clobber (reg:SI LR_REGNUM))
(clobber (reg:SI IP_REGNUM))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_SOFT_TP"
+ "TARGET_SOFT_TP && !TARGET_FDPIC"
"bl\\t__aeabi_read_tp\\t@ load_tp_soft"
[(set_attr "conds" "clob")
(set_attr "type" "branch")]
projects / thirdparty / gcc.git / blobdiff