Update copyright years.

[thirdparty/gcc.git] / gcc / config / arm / cortex-a15.md

diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md
index 4ad87121d6dbb6e2514d301aaa3bcf674026d562..f6f52f7b1786720b44aa55ccf771c491d55bccb9 100644 (file)
--- a/gcc/config/arm/cortex-a15.md
+++ b/gcc/config/arm/cortex-a15.md
@@ -1,5 +1,5 @@
 ;; ARM Cortex-A15 pipeline description
-;; Copyright (C) 2011-2013 Free Software Foundation, Inc.
+;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
 ;;
 ;; Written by Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
 
@@ -61,25 +61,35 @@
 ;; Simple ALU without shift
 (define_insn_reservation "cortex_a15_alu" 2
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
-                             mov_imm,mov_reg,\
-                             mvn_imm,mvn_reg")
-            (eq_attr "neon_type" "none")))
+       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,clz,rbit,rev,alu_dsp_reg,\
+                        shift_imm,shift_reg,\
+                        mov_imm,mov_reg,\
+                        mvn_imm,mvn_reg,\
+                        mrs,multiple"))
   "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
 
 ;; ALU ops with immediate shift
+;; crc is also included here so that appropriate scheduling of CRC32 ARMv8-A
+;; instructions can be performed when tuning for the Cortex-A57 since that
+;; core reuses the Cortex-A15 pipeline description for the moment.
 (define_insn_reservation "cortex_a15_alu_shift" 3
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift")
-            (eq_attr "neon_type" "none")))
+       (eq_attr "type" "extend,\
+                        alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
+                        crc,logic_shift_imm,logics_shift_imm,\
+                        mov_shift,mvn_shift"))
   "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
               |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
 
 ;; ALU ops with register controlled shift
 (define_insn_reservation "cortex_a15_alu_shift_reg" 3
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                        logic_shift_reg,logics_shift_reg,\
+                        mov_shift_reg,mvn_shift_reg"))
   "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
    |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
    |(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
@@ -89,15 +99,13 @@
 ;; 32-bit multiplies
 (define_insn_reservation "cortex_a15_mult32" 3
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "mul32" "yes")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "mul32" "yes"))
   "ca15_issue1,ca15_mx")
 
 ;; 64-bit multiplies
 (define_insn_reservation "cortex_a15_mult64" 4
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "mul64" "yes")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "widen_mul64" "yes"))
   "ca15_issue1,ca15_mx*2")
 
 ;; Integer divide
@@ -114,8 +122,7 @@
 ;; Block all issue pipes for a cycle
 (define_insn_reservation "cortex_a15_block" 1
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "block")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "type" "block"))
   "ca15_issue3")
 
 ;; Branch execution Unit
@@ -124,8 +131,7 @@
 ;; No latency as there is no result
 (define_insn_reservation "cortex_a15_branch" 0
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "branch")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "type" "branch"))
   "ca15_issue1,ca15_bx")
 
 ;; Load-store execution Unit
@@ -133,40 +139,35 @@
 ;; Loads of up to two words.
 (define_insn_reservation "cortex_a15_load1" 4
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "load_byte,load1,load2")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "type" "load_byte,load_4,load_8"))
   "ca15_issue1,ca15_ls,ca15_ldr,nothing")
 
 ;; Loads of three or four words.
 (define_insn_reservation "cortex_a15_load3" 5
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "load3,load4")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "type" "load_12,load_16"))
   "ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing")
 
 ;; Stores of up to two words.
 (define_insn_reservation "cortex_a15_store1" 0
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "store1,store2")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "type" "store_4,store_8"))
   "ca15_issue1,ca15_ls,ca15_str")
 
 ;; Stores of three or four words.
 (define_insn_reservation "cortex_a15_store3" 0
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "store3,store4")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "type" "store_12,store_16"))
   "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str")
 
 ;; We include Neon.md here to ensure that the branch can block the Neon units.
-(include "cortex-a15-neon.md")
+(include "../arm/cortex-a15-neon.md")
 
 ;; We lie with calls.  They take up all issue slots, and form a block in the
 ;; pipeline.  The result however is available the next cycle.
 (define_insn_reservation "cortex_a15_call" 1
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "call")
-           (eq_attr "neon_type" "none")))
+       (eq_attr "type" "call"))
   "ca15_issue3,\
    ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx_ij+ca15_cx_ik+ca15_ls1+ca15_ls2+\
    ca15_cx_imac1+ca15_cx_ialu1+ca15_cx_ialu2+ca15_cx_ishf+\