;; ARM Cortex-A15 pipeline description
-;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
+;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
;;
;; Written by Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "extend,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
crc,logic_shift_imm,logics_shift_imm,\
mov_shift,mvn_shift"))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
;; 64-bit multiplies
(define_insn_reservation "cortex_a15_mult64" 4
(and (eq_attr "tune" "cortexa15")
- (eq_attr "mul64" "yes"))
+ (eq_attr "widen_mul64" "yes"))
"ca15_issue1,ca15_mx*2")
;; Integer divide