;; ARM Cortex-A5 pipeline description
-;; Copyright (C) 2010-2018 Free Software Foundation, Inc.
+;; Copyright (C) 2010-2020 Free Software Foundation, Inc.
;; Contributed by CodeSourcery.
;;
;; This file is part of GCC.
adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2
(define_insn_reservation "cortex_a5_mul" 2
(and (eq_attr "tune" "cortexa5")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))
+ (eq_attr "widen_mul64" "yes")))
"cortex_a5_ex1")
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