Update copyright years.

[thirdparty/gcc.git] / gcc / config / arm / cortex-a7.md

diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index 261375047ca66c95e172567da4d747518c1db51d..8f326d7727a650369afa4a1ba97e45b2c1678031 100644 (file)
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -1,5 +1,5 @@
 ;; ARM Cortex-A7 pipeline description
-;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
+;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by ARM Ltd.
 ;; Based on cortex-a5.md which was originally contributed by CodeSourcery.
@@ -133,34 +133,34 @@
 
 ;; ALU instruction with register operands can dual-issue
 ;; with a younger immediate-based instruction.
-(define_insn_reservation "cortex_a7_alu_reg" 2
+(define_insn_reservation "cortex_a7_alu_sreg" 2
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\
+       (eq_attr "type" "alu_sreg,alus_sreg,logic_reg,logics_reg,\
                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
-                        bfm,clz,rbit,rev,\
+                        bfm,clz,rbit,rev,alu_dsp_reg,\
                         shift_imm,shift_reg,mov_reg,mvn_reg"))
   "cortex_a7_ex1")
 
 (define_insn_reservation "cortex_a7_alu_shift" 2
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+       (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
                         logic_shift_imm,logics_shift_imm,\
                         alu_shift_reg,alus_shift_reg,\
                         logic_shift_reg,logics_shift_reg,\
                         mov_shift,mov_shift_reg,\
                         mvn_shift,mvn_shift_reg,\
-                        mrs,multiple,no_insn"))
+                        mrs,multiple"))
   "cortex_a7_ex1")
 
 ;; Forwarding path for unshifted operands.
-(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
-  "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul")
+(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
+  "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_mul")
 
-(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
+(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
   "cortex_a7_store*"
   "arm_no_early_store_addr_dep")
 
-(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift"
+(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
   "cortex_a7_alu_shift"
   "arm_no_early_alu_shift_dep")
 
@@ -171,7 +171,7 @@
 (define_insn_reservation "cortex_a7_mul" 2
   (and (eq_attr "tune" "cortexa7")
        (ior (eq_attr "mul32" "yes")
-            (eq_attr "mul64" "yes")))
+           (eq_attr "widen_mul64" "yes")))
   "cortex_a7_both")
 
 ;; Forward the result of a multiply operation to the accumulator 
@@ -196,42 +196,42 @@
 
 (define_insn_reservation "cortex_a7_load1" 2
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "load_byte,load1"))
+       (eq_attr "type" "load_byte,load_4"))
   "cortex_a7_ex1")
 
 (define_insn_reservation "cortex_a7_store1" 0
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "store1"))
+       (eq_attr "type" "store_4"))
   "cortex_a7_ex1")
 
 (define_insn_reservation "cortex_a7_load2" 2
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "load2"))
+       (eq_attr "type" "load_8"))
   "cortex_a7_both")
 
 (define_insn_reservation "cortex_a7_store2" 0
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "store2"))
+       (eq_attr "type" "store_8"))
   "cortex_a7_both")
 
 (define_insn_reservation "cortex_a7_load3" 3
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "load3"))
+       (eq_attr "type" "load_12"))
   "cortex_a7_both, cortex_a7_ex1")
 
 (define_insn_reservation "cortex_a7_store3" 0
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "store4"))
+       (eq_attr "type" "store_16"))
   "cortex_a7_both, cortex_a7_ex1")
 
 (define_insn_reservation "cortex_a7_load4" 3
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "load4"))
+       (eq_attr "type" "load_16"))
   "cortex_a7_both, cortex_a7_both")
 
 (define_insn_reservation "cortex_a7_store4" 0
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "store3"))
+       (eq_attr "type" "store_12"))
   "cortex_a7_both, cortex_a7_both")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;