;; ARM Cortex-A8 scheduling description.
-;; Copyright (C) 2007 Free Software Foundation, Inc.
+;; Copyright (C) 2007-2020 Free Software Foundation, Inc.
;; Contributed by CodeSourcery.
;; This file is part of GCC.
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-;; Boston, MA 02110-1301, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
(define_automaton "cortex_a8")
"(cortex_a8_alu0+cortex_a8_issue_ls)|\
(cortex_a8_alu1+cortex_a8_issue_ls)")
-;; ...and in the case of two micro-ops. We don't need to reserve
-;; cortex_a8_issue_ls here because dual issue is altogether forbidden
+;; ...and in the case of two micro-ops. Dual issue is altogether forbidden
;; during the issue cycle of the first micro-op. (Instead of modelling
;; a separate issue unit, we instead reserve alu0 and alu1 to
;; prevent any other instructions from being issued upon that first cycle.)
;; Even though the load/store pipeline is usually available in either
-;; ALU pipe, multi-cycle instructions always issue in pipeline 0. This
-;; reservation is therefore the same as cortex_a8_multiply_2 below.
+;; ALU pipe, multi-cycle instructions always issue in pipeline 0.
(define_reservation "cortex_a8_load_store_2"
- "cortex_a8_alu0+cortex_a8_alu1,\
- cortex_a8_alu0")
+ "cortex_a8_alu0+cortex_a8_alu1+cortex_a8_issue_ls,\
+ cortex_a8_alu0+cortex_a8_issue_ls")
;; The flow of a single-cycle multiplication.
(define_reservation "cortex_a8_multiply"
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
- (ior (and (eq_attr "type" "alu")
- (not (eq_attr "insn" "mov,mvn")))
- (eq_attr "insn" "clz")))
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_sreg,alus_sreg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,clz,rbit,rev,alu_dsp_reg,\
+ shift_imm,shift_reg,\
+ multiple"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
(and (eq_attr "tune" "cortexa8")
- (and (eq_attr "type" "alu_shift")
- (not (eq_attr "insn" "mov,mvn"))))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ extend"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift_reg" 2
(and (eq_attr "tune" "cortexa8")
- (and (eq_attr "type" "alu_shift_reg")
- (not (eq_attr "insn" "mov,mvn"))))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg"))
"cortex_a8_default")
;; Move instructions.
(define_insn_reservation "cortex_a8_mov" 1
(and (eq_attr "tune" "cortexa8")
- (and (eq_attr "type" "alu,alu_shift,alu_shift_reg")
- (eq_attr "insn" "mov,mvn")))
+ (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\
+ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
+ mrs"))
"cortex_a8_default")
;; Exceptions to the default latencies for data processing instructions.
"arm_no_early_alu_shift_value_dep")
;; Multiplication instructions. These are categorized according to their
-;; reservation behaviour and the need below to distinguish certain
+;; reservation behavior and the need below to distinguish certain
;; varieties for bypasses. Results are available at the E5 stage
;; (but some of these are multi-cycle instructions which explains the
;; latencies below).
(define_insn_reservation "cortex_a8_mul" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "insn" "mul,smulxy,smmul"))
+ (eq_attr "type" "mul,smulxy,smmul"))
"cortex_a8_multiply_2")
(define_insn_reservation "cortex_a8_mla" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "insn" "mla,smlaxy,smlawy,smmla,smlad,smlsd"))
+ (eq_attr "type" "mla,smlaxy,smlawy,smmla,smlad,smlsd"))
"cortex_a8_multiply_2")
(define_insn_reservation "cortex_a8_mull" 7
(and (eq_attr "tune" "cortexa8")
- (eq_attr "insn" "smull,umull,smlal,umlal,umaal,smlalxy"))
+ (eq_attr "type" "smull,umull,smlal,umlal,umaal,smlalxy"))
"cortex_a8_multiply_3")
(define_insn_reservation "cortex_a8_smulwy" 5
(and (eq_attr "tune" "cortexa8")
- (eq_attr "insn" "smulwy,smuad,smusd"))
+ (eq_attr "type" "smulwy,smuad,smusd"))
"cortex_a8_multiply")
;; smlald and smlsld are multiply-accumulate instructions but do not
;; cannot go in cortex_a8_mla above. (See below for bypass details.)
(define_insn_reservation "cortex_a8_smlald" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "insn" "smlald,smlsld"))
+ (eq_attr "type" "smlald,smlsld"))
"cortex_a8_multiply_2")
;; A multiply with a single-register result or an MLA, followed by an
;; We assume 64-bit alignment for doubleword loads.
(define_insn_reservation "cortex_a8_load1_2" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "load1,load2,load_byte"))
+ (eq_attr "type" "load_4,load_8,load_byte"))
"cortex_a8_load_store_1")
(define_bypass 2 "cortex_a8_load1_2"
;; issued as two micro-ops.
(define_insn_reservation "cortex_a8_load3_4" 5
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "load3,load4"))
+ (eq_attr "type" "load_12,load_16"))
"cortex_a8_load_store_2")
(define_bypass 4 "cortex_a8_load3_4"
(define_insn_reservation "cortex_a8_store1_2" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "store1,store2"))
+ (eq_attr "type" "store_4,store_8"))
"cortex_a8_load_store_1")
(define_insn_reservation "cortex_a8_store3_4" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "store3,store4"))
+ (eq_attr "type" "store_12,store_16"))
"cortex_a8_load_store_2")
;; An ALU instruction acting as a producer for a store instruction
;; reads the value to be stored at the start of E3 and the ALU insn
;; writes it at the end of E2. Move instructions actually produce the
;; result at the end of E1, but since we don't have delay slots, the
-;; scheduling behaviour will be the same.
+;; scheduling behavior will be the same.
(define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\
cortex_a8_alu_shift_reg,cortex_a8_mov"
"cortex_a8_store1_2,cortex_a8_store3_4"
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