;; ARM Cortex-A8 scheduling description.
-;; Copyright (C) 2007-2013 Free Software Foundation, Inc.
+;; Copyright (C) 2007-2020 Free Software Foundation, Inc.
;; Contributed by CodeSourcery.
;; This file is part of GCC.
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,clz"))
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_sreg,alus_sreg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,clz,rbit,rev,alu_dsp_reg,\
+ shift_imm,shift_reg,\
+ multiple"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "extend,arlo_shift"))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ extend"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift_reg" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "arlo_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg"))
"cortex_a8_default")
;; Move instructions.
(define_insn_reservation "cortex_a8_mov" 1
(and (eq_attr "tune" "cortexa8")
(eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\
- mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
+ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
+ mrs"))
"cortex_a8_default")
;; Exceptions to the default latencies for data processing instructions.
;; We assume 64-bit alignment for doubleword loads.
(define_insn_reservation "cortex_a8_load1_2" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "load1,load2,load_byte"))
+ (eq_attr "type" "load_4,load_8,load_byte"))
"cortex_a8_load_store_1")
(define_bypass 2 "cortex_a8_load1_2"
;; issued as two micro-ops.
(define_insn_reservation "cortex_a8_load3_4" 5
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "load3,load4"))
+ (eq_attr "type" "load_12,load_16"))
"cortex_a8_load_store_2")
(define_bypass 4 "cortex_a8_load3_4"
(define_insn_reservation "cortex_a8_store1_2" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "store1,store2"))
+ (eq_attr "type" "store_4,store_8"))
"cortex_a8_load_store_1")
(define_insn_reservation "cortex_a8_store3_4" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "store3,store4"))
+ (eq_attr "type" "store_12,store_16"))
"cortex_a8_load_store_2")
;; An ALU instruction acting as a producer for a store instruction